1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
4 * Copyright (C) 2005 - 2009 Myricom, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
36 * Contact Information:
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/dca.h>
54 #include <linux/inet.h>
56 #include <linux/ethtool.h>
57 #include <linux/firmware.h>
58 #include <linux/delay.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
68 #include <asm/byteorder.h>
70 #include <asm/processor.h>
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
78 #define MYRI10GE_VERSION_STR "1.4.4-1.412"
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
85 #define MYRI10GE_MAX_ETHER_MTU 9014
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
105 #define MYRI10GE_MAX_SLICES 32
107 struct myri10ge_rx_buffer_state {
110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
114 struct myri10ge_tx_buffer_state {
117 DECLARE_PCI_UNMAP_ADDR(bus)
118 DECLARE_PCI_UNMAP_LEN(len)
121 struct myri10ge_cmd {
127 struct myri10ge_rx_buf {
128 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
137 int mask; /* number of rx slots -1 */
141 struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
143 __be32 __iomem *send_go; /* "go" doorbell ptr */
144 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
145 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
147 struct myri10ge_tx_buffer_state *info;
148 int mask; /* number of transmit slots -1 */
149 int req ____cacheline_aligned; /* transmit slots submitted */
150 int pkt_start; /* packets started */
153 int done ____cacheline_aligned; /* transmit slots completed */
154 int pkt_done; /* packets completed */
159 struct myri10ge_rx_done {
160 struct mcp_slot *entry;
164 struct net_lro_mgr lro_mgr;
165 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
168 struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
177 struct myri10ge_slice_state {
178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
191 #ifdef CONFIG_MYRI10GE_DCA
194 __be32 __iomem *dca_tag;
199 struct myri10ge_priv {
200 struct myri10ge_slice_state *ss;
201 int tx_boundary; /* boundary transmits cannot cross */
203 int running; /* running? */
204 int csum_flag; /* rx_csums? */
208 struct net_device *dev;
209 struct net_device_stats stats;
210 spinlock_t stats_lock;
213 unsigned long board_span;
214 unsigned long iomem_base;
215 __be32 __iomem *irq_deassert;
216 char *mac_addr_string;
217 struct mcp_cmd_response *cmd;
219 struct pci_dev *pdev;
222 struct msix_entry *msix_vectors;
223 #ifdef CONFIG_MYRI10GE_DCA
227 unsigned int rdma_tags_available;
229 __be32 __iomem *intr_coal_delay_ptr;
233 wait_queue_head_t down_wq;
234 struct work_struct watchdog_work;
235 struct timer_list watchdog_timer;
240 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
241 char *product_code_string;
242 char fw_version[128];
246 int adopted_rx_filter_bug;
247 u8 mac_addr[6]; /* eeprom mac address */
248 unsigned long serial_number;
249 int vendor_specific_offset;
250 int fw_multicast_support;
251 unsigned long features;
258 unsigned int board_number;
261 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
262 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
263 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
264 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
266 static char *myri10ge_fw_name = NULL;
267 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
268 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
270 #define MYRI10GE_MAX_BOARDS 8
271 static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
272 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
273 module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
275 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
277 static int myri10ge_ecrc_enable = 1;
278 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
279 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
281 static int myri10ge_small_bytes = -1; /* -1 == auto */
282 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
283 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
285 static int myri10ge_msi = 1; /* enable msi by default */
286 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
287 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
289 static int myri10ge_intr_coal_delay = 75;
290 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
291 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
293 static int myri10ge_flow_control = 1;
294 module_param(myri10ge_flow_control, int, S_IRUGO);
295 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
297 static int myri10ge_deassert_wait = 1;
298 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
299 MODULE_PARM_DESC(myri10ge_deassert_wait,
300 "Wait when deasserting legacy interrupts");
302 static int myri10ge_force_firmware = 0;
303 module_param(myri10ge_force_firmware, int, S_IRUGO);
304 MODULE_PARM_DESC(myri10ge_force_firmware,
305 "Force firmware to assume aligned completions");
307 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
308 module_param(myri10ge_initial_mtu, int, S_IRUGO);
309 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
311 static int myri10ge_napi_weight = 64;
312 module_param(myri10ge_napi_weight, int, S_IRUGO);
313 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
315 static int myri10ge_watchdog_timeout = 1;
316 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
317 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
319 static int myri10ge_max_irq_loops = 1048576;
320 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
321 MODULE_PARM_DESC(myri10ge_max_irq_loops,
322 "Set stuck legacy IRQ detection threshold");
324 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
326 static int myri10ge_debug = -1; /* defaults above */
327 module_param(myri10ge_debug, int, 0);
328 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
330 static int myri10ge_lro = 1;
331 module_param(myri10ge_lro, int, S_IRUGO);
332 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
334 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
335 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
336 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
337 "Number of LRO packets to be aggregated");
339 static int myri10ge_fill_thresh = 256;
340 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
341 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
343 static int myri10ge_reset_recover = 1;
345 static int myri10ge_max_slices = 1;
346 module_param(myri10ge_max_slices, int, S_IRUGO);
347 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
349 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
350 module_param(myri10ge_rss_hash, int, S_IRUGO);
351 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
353 static int myri10ge_dca = 1;
354 module_param(myri10ge_dca, int, S_IRUGO);
355 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
357 #define MYRI10GE_FW_OFFSET 1024*1024
358 #define MYRI10GE_HIGHPART_TO_U32(X) \
359 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
360 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
362 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
364 static void myri10ge_set_multicast_list(struct net_device *dev);
365 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
367 static inline void put_be32(__be32 val, __be32 __iomem * p)
369 __raw_writel((__force __u32) val, (__force void __iomem *)p);
372 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
375 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
376 struct myri10ge_cmd *data, int atomic)
379 char buf_bytes[sizeof(*buf) + 8];
380 struct mcp_cmd_response *response = mgp->cmd;
381 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
382 u32 dma_low, dma_high, result, value;
385 /* ensure buf is aligned to 8 bytes */
386 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
388 buf->data0 = htonl(data->data0);
389 buf->data1 = htonl(data->data1);
390 buf->data2 = htonl(data->data2);
391 buf->cmd = htonl(cmd);
392 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
393 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
395 buf->response_addr.low = htonl(dma_low);
396 buf->response_addr.high = htonl(dma_high);
397 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
399 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
401 /* wait up to 15ms. Longest command is the DMA benchmark,
402 * which is capped at 5ms, but runs from a timeout handler
403 * that runs every 7.8ms. So a 15ms timeout leaves us with
407 /* if atomic is set, do not sleep,
408 * and try to get the completion quickly
409 * (1ms will be enough for those commands) */
410 for (sleep_total = 0;
412 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
418 /* use msleep for most command */
419 for (sleep_total = 0;
421 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
426 result = ntohl(response->result);
427 value = ntohl(response->data);
428 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
432 } else if (result == MXGEFW_CMD_UNKNOWN) {
434 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
436 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
437 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
439 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
443 dev_err(&mgp->pdev->dev,
444 "command %d failed, result = %d\n",
450 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
456 * The eeprom strings on the lanaiX have the format
459 * PT:ddd mmm xx xx:xx:xx xx\0
460 * PV:ddd mmm xx xx:xx:xx xx\0
462 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
467 ptr = mgp->eeprom_strings;
468 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
470 while (*ptr != '\0' && ptr < limit) {
471 if (memcmp(ptr, "MAC=", 4) == 0) {
473 mgp->mac_addr_string = ptr;
474 for (i = 0; i < 6; i++) {
475 if ((ptr + 2) > limit)
478 simple_strtoul(ptr, &ptr, 16);
482 if (memcmp(ptr, "PC=", 3) == 0) {
484 mgp->product_code_string = ptr;
486 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
488 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
490 while (ptr < limit && *ptr++) ;
496 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
501 * Enable or disable periodic RDMAs from the host to make certain
502 * chipsets resend dropped PCIe messages
505 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
507 char __iomem *submit;
508 __be32 buf[16] __attribute__ ((__aligned__(8)));
509 u32 dma_low, dma_high;
512 /* clear confirmation addr */
516 /* send a rdma command to the PCIe engine, and wait for the
517 * response in the confirmation address. The firmware should
518 * write a -1 there to indicate it is alive and well
520 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
521 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
523 buf[0] = htonl(dma_high); /* confirm addr MSW */
524 buf[1] = htonl(dma_low); /* confirm addr LSW */
525 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
526 buf[3] = htonl(dma_high); /* dummy addr MSW */
527 buf[4] = htonl(dma_low); /* dummy addr LSW */
528 buf[5] = htonl(enable); /* enable? */
530 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
532 myri10ge_pio_copy(submit, &buf, sizeof(buf));
533 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
535 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
536 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
537 (enable ? "enable" : "disable"));
541 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
542 struct mcp_gen_header *hdr)
544 struct device *dev = &mgp->pdev->dev;
546 /* check firmware type */
547 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
548 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
552 /* save firmware version for ethtool */
553 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
555 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
556 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
558 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
559 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
560 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
561 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
562 MXGEFW_VERSION_MINOR);
568 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
570 unsigned crc, reread_crc;
571 const struct firmware *fw;
572 struct device *dev = &mgp->pdev->dev;
573 unsigned char *fw_readback;
574 struct mcp_gen_header *hdr;
579 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
580 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
583 goto abort_with_nothing;
588 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
589 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
590 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
596 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
597 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
598 dev_err(dev, "Bad firmware file\n");
602 hdr = (void *)(fw->data + hdr_offset);
604 status = myri10ge_validate_firmware(mgp, hdr);
608 crc = crc32(~0, fw->data, fw->size);
609 for (i = 0; i < fw->size; i += 256) {
610 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
612 min(256U, (unsigned)(fw->size - i)));
616 fw_readback = vmalloc(fw->size);
621 /* corruption checking is good for parity recovery and buggy chipset */
622 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
623 reread_crc = crc32(~0, fw_readback, fw->size);
625 if (crc != reread_crc) {
626 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
627 (unsigned)fw->size, reread_crc, crc);
631 *size = (u32) fw->size;
634 release_firmware(fw);
640 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
642 struct mcp_gen_header *hdr;
643 struct device *dev = &mgp->pdev->dev;
644 const size_t bytes = sizeof(struct mcp_gen_header);
648 /* find running firmware header */
649 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
651 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
652 dev_err(dev, "Running firmware has bad header offset (%d)\n",
657 /* copy header of running firmware from SRAM to host memory to
658 * validate firmware */
659 hdr = kmalloc(bytes, GFP_KERNEL);
661 dev_err(dev, "could not malloc firmware hdr\n");
664 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
665 status = myri10ge_validate_firmware(mgp, hdr);
668 /* check to see if adopted firmware has bug where adopting
669 * it will cause broadcasts to be filtered unless the NIC
670 * is kept in ALLMULTI mode */
671 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
672 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
673 mgp->adopted_rx_filter_bug = 1;
674 dev_warn(dev, "Adopting fw %d.%d.%d: "
675 "working around rx filter bug\n",
676 mgp->fw_ver_major, mgp->fw_ver_minor,
682 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
684 struct myri10ge_cmd cmd;
687 /* probe for IPv6 TSO support */
688 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
689 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
692 mgp->max_tso6 = cmd.data0;
693 mgp->features |= NETIF_F_TSO6;
696 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
698 dev_err(&mgp->pdev->dev,
699 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
703 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
708 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
710 char __iomem *submit;
711 __be32 buf[16] __attribute__ ((__aligned__(8)));
712 u32 dma_low, dma_high, size;
716 status = myri10ge_load_hotplug_firmware(mgp, &size);
720 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
722 /* Do not attempt to adopt firmware if there
727 status = myri10ge_adopt_running_firmware(mgp);
729 dev_err(&mgp->pdev->dev,
730 "failed to adopt running firmware\n");
733 dev_info(&mgp->pdev->dev,
734 "Successfully adopted running firmware\n");
735 if (mgp->tx_boundary == 4096) {
736 dev_warn(&mgp->pdev->dev,
737 "Using firmware currently running on NIC"
739 dev_warn(&mgp->pdev->dev,
740 "performance consider loading optimized "
742 dev_warn(&mgp->pdev->dev, "via hotplug\n");
745 mgp->fw_name = "adopted";
746 mgp->tx_boundary = 2048;
747 myri10ge_dummy_rdma(mgp, 1);
748 status = myri10ge_get_firmware_capabilities(mgp);
752 /* clear confirmation addr */
756 /* send a reload command to the bootstrap MCP, and wait for the
757 * response in the confirmation address. The firmware should
758 * write a -1 there to indicate it is alive and well
760 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
761 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
763 buf[0] = htonl(dma_high); /* confirm addr MSW */
764 buf[1] = htonl(dma_low); /* confirm addr LSW */
765 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
767 /* FIX: All newest firmware should un-protect the bottom of
768 * the sram before handoff. However, the very first interfaces
769 * do not. Therefore the handoff copy must skip the first 8 bytes
771 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
772 buf[4] = htonl(size - 8); /* length of code */
773 buf[5] = htonl(8); /* where to copy to */
774 buf[6] = htonl(0); /* where to jump to */
776 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
778 myri10ge_pio_copy(submit, &buf, sizeof(buf));
783 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
787 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
788 dev_err(&mgp->pdev->dev, "handoff failed\n");
791 myri10ge_dummy_rdma(mgp, 1);
792 status = myri10ge_get_firmware_capabilities(mgp);
797 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
799 struct myri10ge_cmd cmd;
802 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
803 | (addr[2] << 8) | addr[3]);
805 cmd.data1 = ((addr[4] << 8) | (addr[5]));
807 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
811 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
813 struct myri10ge_cmd cmd;
816 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
817 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
821 "myri10ge: %s: Failed to set flow control mode\n",
830 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
832 struct myri10ge_cmd cmd;
835 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
836 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
838 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
842 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
844 struct myri10ge_cmd cmd;
847 struct page *dmatest_page;
848 dma_addr_t dmatest_bus;
851 dmatest_page = alloc_page(GFP_KERNEL);
854 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
857 /* Run a small DMA test.
858 * The magic multipliers to the length tell the firmware
859 * to do DMA read, write, or read+write tests. The
860 * results are returned in cmd.data0. The upper 16
861 * bits or the return is the number of transfers completed.
862 * The lower 16 bits is the time in 0.5us ticks that the
863 * transfers took to complete.
866 len = mgp->tx_boundary;
868 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
869 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
870 cmd.data2 = len * 0x10000;
871 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
876 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
877 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
878 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
879 cmd.data2 = len * 0x1;
880 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
885 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
887 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
888 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
889 cmd.data2 = len * 0x10001;
890 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
895 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
896 (cmd.data0 & 0xffff);
899 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
900 put_page(dmatest_page);
902 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
903 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
909 static int myri10ge_reset(struct myri10ge_priv *mgp)
911 struct myri10ge_cmd cmd;
912 struct myri10ge_slice_state *ss;
915 #ifdef CONFIG_MYRI10GE_DCA
916 unsigned long dca_tag_off;
919 /* try to send a reset command to the card to see if it
921 memset(&cmd, 0, sizeof(cmd));
922 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
924 dev_err(&mgp->pdev->dev, "failed reset\n");
928 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
930 * Use non-ndis mcp_slot (eg, 4 bytes total,
931 * no toeplitz hash value returned. Older firmware will
932 * not understand this command, but will use the correct
933 * sized mcp_slot, so we ignore error returns
935 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
936 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
938 /* Now exchange information about interrupts */
940 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
941 cmd.data0 = (u32) bytes;
942 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
945 * Even though we already know how many slices are supported
946 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
947 * has magic side effects, and must be called after a reset.
948 * It must be called prior to calling any RSS related cmds,
949 * including assigning an interrupt queue for anything but
950 * slice 0. It must also be called *after*
951 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
952 * the firmware to compute offsets.
955 if (mgp->num_slices > 1) {
957 /* ask the maximum number of slices it supports */
958 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
961 dev_err(&mgp->pdev->dev,
962 "failed to get number of slices\n");
966 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
967 * to setting up the interrupt queue DMA
970 cmd.data0 = mgp->num_slices;
971 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
972 if (mgp->dev->real_num_tx_queues > 1)
973 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
974 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
977 /* Firmware older than 1.4.32 only supports multiple
978 * RX queues, so if we get an error, first retry using a
979 * single TX queue before giving up */
980 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
981 mgp->dev->real_num_tx_queues = 1;
982 cmd.data0 = mgp->num_slices;
983 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
984 status = myri10ge_send_cmd(mgp,
985 MXGEFW_CMD_ENABLE_RSS_QUEUES,
990 dev_err(&mgp->pdev->dev,
991 "failed to set number of slices\n");
996 for (i = 0; i < mgp->num_slices; i++) {
998 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
999 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1001 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1006 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1007 for (i = 0; i < mgp->num_slices; i++) {
1010 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1012 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1014 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1016 status |= myri10ge_send_cmd
1017 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1018 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1020 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1023 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1025 #ifdef CONFIG_MYRI10GE_DCA
1026 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1027 dca_tag_off = cmd.data0;
1028 for (i = 0; i < mgp->num_slices; i++) {
1031 ss->dca_tag = (__iomem __be32 *)
1032 (mgp->sram + dca_tag_off + 4 * i);
1037 #endif /* CONFIG_MYRI10GE_DCA */
1039 /* reset mcp/driver shared state back to 0 */
1041 mgp->link_changes = 0;
1042 for (i = 0; i < mgp->num_slices; i++) {
1045 memset(ss->rx_done.entry, 0, bytes);
1048 ss->tx.pkt_start = 0;
1049 ss->tx.pkt_done = 0;
1051 ss->rx_small.cnt = 0;
1052 ss->rx_done.idx = 0;
1053 ss->rx_done.cnt = 0;
1054 ss->tx.wake_queue = 0;
1055 ss->tx.stop_queue = 0;
1058 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1059 myri10ge_change_pause(mgp, mgp->pause);
1060 myri10ge_set_multicast_list(mgp->dev);
1064 #ifdef CONFIG_MYRI10GE_DCA
1066 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1069 ss->cached_dca_tag = tag;
1070 put_be32(htonl(tag), ss->dca_tag);
1073 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1075 int cpu = get_cpu();
1078 if (cpu != ss->cpu) {
1079 tag = dca_get_tag(cpu);
1080 if (ss->cached_dca_tag != tag)
1081 myri10ge_write_dca(ss, cpu, tag);
1086 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1089 struct pci_dev *pdev = mgp->pdev;
1091 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1093 if (!myri10ge_dca) {
1094 dev_err(&pdev->dev, "dca disabled by administrator\n");
1097 err = dca_add_requester(&pdev->dev);
1101 "dca_add_requester() failed, err=%d\n", err);
1104 mgp->dca_enabled = 1;
1105 for (i = 0; i < mgp->num_slices; i++)
1106 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1109 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1111 struct pci_dev *pdev = mgp->pdev;
1114 if (!mgp->dca_enabled)
1116 mgp->dca_enabled = 0;
1117 err = dca_remove_requester(&pdev->dev);
1120 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1122 struct myri10ge_priv *mgp;
1123 unsigned long event;
1125 mgp = dev_get_drvdata(dev);
1126 event = *(unsigned long *)data;
1128 if (event == DCA_PROVIDER_ADD)
1129 myri10ge_setup_dca(mgp);
1130 else if (event == DCA_PROVIDER_REMOVE)
1131 myri10ge_teardown_dca(mgp);
1134 #endif /* CONFIG_MYRI10GE_DCA */
1137 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1138 struct mcp_kreq_ether_recv *src)
1142 low = src->addr_low;
1143 src->addr_low = htonl(DMA_BIT_MASK(32));
1144 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1146 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1148 src->addr_low = low;
1149 put_be32(low, &dst->addr_low);
1153 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1155 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1157 if ((skb->protocol == htons(ETH_P_8021Q)) &&
1158 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1159 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1160 skb->csum = hw_csum;
1161 skb->ip_summed = CHECKSUM_COMPLETE;
1166 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1167 struct skb_frag_struct *rx_frags, int len, int hlen)
1169 struct skb_frag_struct *skb_frags;
1171 skb->len = skb->data_len = len;
1172 skb->truesize = len + sizeof(struct sk_buff);
1173 /* attach the page(s) */
1175 skb_frags = skb_shinfo(skb)->frags;
1177 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1178 len -= rx_frags->size;
1181 skb_shinfo(skb)->nr_frags++;
1184 /* pskb_may_pull is not available in irq context, but
1185 * skb_pull() (for ether_pad and eth_type_trans()) requires
1186 * the beginning of the packet in skb_headlen(), move it
1188 skb_copy_to_linear_data(skb, va, hlen);
1189 skb_shinfo(skb)->frags[0].page_offset += hlen;
1190 skb_shinfo(skb)->frags[0].size -= hlen;
1191 skb->data_len -= hlen;
1193 skb_pull(skb, MXGEFW_PAD);
1197 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1198 int bytes, int watchdog)
1203 if (unlikely(rx->watchdog_needed && !watchdog))
1206 /* try to refill entire ring */
1207 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1208 idx = rx->fill_cnt & rx->mask;
1209 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1210 /* we can use part of previous page */
1213 /* we need a new page */
1215 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1216 MYRI10GE_ALLOC_ORDER);
1217 if (unlikely(page == NULL)) {
1218 if (rx->fill_cnt - rx->cnt < 16)
1219 rx->watchdog_needed = 1;
1223 rx->page_offset = 0;
1224 rx->bus = pci_map_page(mgp->pdev, page, 0,
1225 MYRI10GE_ALLOC_SIZE,
1226 PCI_DMA_FROMDEVICE);
1228 rx->info[idx].page = rx->page;
1229 rx->info[idx].page_offset = rx->page_offset;
1230 /* note that this is the address of the start of the
1232 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1233 rx->shadow[idx].addr_low =
1234 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1235 rx->shadow[idx].addr_high =
1236 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1238 /* start next packet on a cacheline boundary */
1239 rx->page_offset += SKB_DATA_ALIGN(bytes);
1241 #if MYRI10GE_ALLOC_SIZE > 4096
1242 /* don't cross a 4KB boundary */
1243 if ((rx->page_offset >> 12) !=
1244 ((rx->page_offset + bytes - 1) >> 12))
1245 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1249 /* copy 8 descriptors to the firmware at a time */
1250 if ((idx & 7) == 7) {
1251 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1252 &rx->shadow[idx - 7]);
1258 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1259 struct myri10ge_rx_buffer_state *info, int bytes)
1261 /* unmap the recvd page if we're the only or last user of it */
1262 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1263 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1264 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1265 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1266 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1270 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1271 * page into an skb */
1274 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1275 int bytes, int len, __wsum csum)
1277 struct myri10ge_priv *mgp = ss->mgp;
1278 struct sk_buff *skb;
1279 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1280 int i, idx, hlen, remainder;
1281 struct pci_dev *pdev = mgp->pdev;
1282 struct net_device *dev = mgp->dev;
1286 idx = rx->cnt & rx->mask;
1287 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1289 /* Fill skb_frag_struct(s) with data from our receive */
1290 for (i = 0, remainder = len; remainder > 0; i++) {
1291 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1292 rx_frags[i].page = rx->info[idx].page;
1293 rx_frags[i].page_offset = rx->info[idx].page_offset;
1294 if (remainder < MYRI10GE_ALLOC_SIZE)
1295 rx_frags[i].size = remainder;
1297 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1299 idx = rx->cnt & rx->mask;
1300 remainder -= MYRI10GE_ALLOC_SIZE;
1303 if (dev->features & NETIF_F_LRO) {
1304 rx_frags[0].page_offset += MXGEFW_PAD;
1305 rx_frags[0].size -= MXGEFW_PAD;
1307 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1308 /* opaque, will come back in get_frag_header */
1310 (void *)(__force unsigned long)csum, csum);
1315 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1317 /* allocate an skb to attach the page(s) to. This is done
1318 * after trying LRO, so as to avoid skb allocation overheads */
1320 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1321 if (unlikely(skb == NULL)) {
1322 ss->stats.rx_dropped++;
1325 put_page(rx_frags[i].page);
1330 /* Attach the pages to the skb, and trim off any padding */
1331 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1332 if (skb_shinfo(skb)->frags[0].size <= 0) {
1333 put_page(skb_shinfo(skb)->frags[0].page);
1334 skb_shinfo(skb)->nr_frags = 0;
1336 skb->protocol = eth_type_trans(skb, dev);
1337 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1339 if (mgp->csum_flag) {
1340 if ((skb->protocol == htons(ETH_P_IP)) ||
1341 (skb->protocol == htons(ETH_P_IPV6))) {
1343 skb->ip_summed = CHECKSUM_COMPLETE;
1345 myri10ge_vlan_ip_csum(skb, csum);
1347 netif_receive_skb(skb);
1352 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1354 struct pci_dev *pdev = ss->mgp->pdev;
1355 struct myri10ge_tx_buf *tx = &ss->tx;
1356 struct netdev_queue *dev_queue;
1357 struct sk_buff *skb;
1360 while (tx->pkt_done != mcp_index) {
1361 idx = tx->done & tx->mask;
1362 skb = tx->info[idx].skb;
1365 tx->info[idx].skb = NULL;
1366 if (tx->info[idx].last) {
1368 tx->info[idx].last = 0;
1371 len = pci_unmap_len(&tx->info[idx], len);
1372 pci_unmap_len_set(&tx->info[idx], len, 0);
1374 ss->stats.tx_bytes += skb->len;
1375 ss->stats.tx_packets++;
1376 dev_kfree_skb_irq(skb);
1378 pci_unmap_single(pdev,
1379 pci_unmap_addr(&tx->info[idx],
1384 pci_unmap_page(pdev,
1385 pci_unmap_addr(&tx->info[idx],
1391 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1393 * Make a minimal effort to prevent the NIC from polling an
1394 * idle tx queue. If we can't get the lock we leave the queue
1395 * active. In this case, either a thread was about to start
1396 * using the queue anyway, or we lost a race and the NIC will
1397 * waste some of its resources polling an inactive queue for a
1401 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1402 __netif_tx_trylock(dev_queue)) {
1403 if (tx->req == tx->done) {
1404 tx->queue_active = 0;
1405 put_be32(htonl(1), tx->send_stop);
1409 __netif_tx_unlock(dev_queue);
1412 /* start the queue if we've stopped it */
1413 if (netif_tx_queue_stopped(dev_queue)
1414 && tx->req - tx->done < (tx->mask >> 1)) {
1416 netif_tx_wake_queue(dev_queue);
1421 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1423 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1424 struct myri10ge_priv *mgp = ss->mgp;
1425 unsigned long rx_bytes = 0;
1426 unsigned long rx_packets = 0;
1427 unsigned long rx_ok;
1429 int idx = rx_done->idx;
1430 int cnt = rx_done->cnt;
1435 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1436 length = ntohs(rx_done->entry[idx].length);
1437 rx_done->entry[idx].length = 0;
1438 checksum = csum_unfold(rx_done->entry[idx].checksum);
1439 if (length <= mgp->small_bytes)
1440 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1444 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1447 rx_packets += rx_ok;
1448 rx_bytes += rx_ok * (unsigned long)length;
1450 idx = cnt & (mgp->max_intr_slots - 1);
1455 ss->stats.rx_packets += rx_packets;
1456 ss->stats.rx_bytes += rx_bytes;
1459 lro_flush_all(&rx_done->lro_mgr);
1461 /* restock receive rings if needed */
1462 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1463 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1464 mgp->small_bytes + MXGEFW_PAD, 0);
1465 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1466 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1471 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1473 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1475 if (unlikely(stats->stats_updated)) {
1476 unsigned link_up = ntohl(stats->link_up);
1477 if (mgp->link_state != link_up) {
1478 mgp->link_state = link_up;
1480 if (mgp->link_state == MXGEFW_LINK_UP) {
1481 if (netif_msg_link(mgp))
1483 "myri10ge: %s: link up\n",
1485 netif_carrier_on(mgp->dev);
1486 mgp->link_changes++;
1488 if (netif_msg_link(mgp))
1490 "myri10ge: %s: link %s\n",
1492 (link_up == MXGEFW_LINK_MYRINET ?
1493 "mismatch (Myrinet detected)" :
1495 netif_carrier_off(mgp->dev);
1496 mgp->link_changes++;
1499 if (mgp->rdma_tags_available !=
1500 ntohl(stats->rdma_tags_available)) {
1501 mgp->rdma_tags_available =
1502 ntohl(stats->rdma_tags_available);
1503 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1504 "%d tags left\n", mgp->dev->name,
1505 mgp->rdma_tags_available);
1507 mgp->down_cnt += stats->link_down;
1508 if (stats->link_down)
1509 wake_up(&mgp->down_wq);
1513 static int myri10ge_poll(struct napi_struct *napi, int budget)
1515 struct myri10ge_slice_state *ss =
1516 container_of(napi, struct myri10ge_slice_state, napi);
1519 #ifdef CONFIG_MYRI10GE_DCA
1520 if (ss->mgp->dca_enabled)
1521 myri10ge_update_dca(ss);
1524 /* process as many rx events as NAPI will allow */
1525 work_done = myri10ge_clean_rx_done(ss, budget);
1527 if (work_done < budget) {
1528 napi_complete(napi);
1529 put_be32(htonl(3), ss->irq_claim);
1534 static irqreturn_t myri10ge_intr(int irq, void *arg)
1536 struct myri10ge_slice_state *ss = arg;
1537 struct myri10ge_priv *mgp = ss->mgp;
1538 struct mcp_irq_data *stats = ss->fw_stats;
1539 struct myri10ge_tx_buf *tx = &ss->tx;
1540 u32 send_done_count;
1543 /* an interrupt on a non-zero receive-only slice is implicitly
1544 * valid since MSI-X irqs are not shared */
1545 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1546 napi_schedule(&ss->napi);
1547 return (IRQ_HANDLED);
1550 /* make sure it is our IRQ, and that the DMA has finished */
1551 if (unlikely(!stats->valid))
1554 /* low bit indicates receives are present, so schedule
1555 * napi poll handler */
1556 if (stats->valid & 1)
1557 napi_schedule(&ss->napi);
1559 if (!mgp->msi_enabled && !mgp->msix_enabled) {
1560 put_be32(0, mgp->irq_deassert);
1561 if (!myri10ge_deassert_wait)
1567 /* Wait for IRQ line to go low, if using INTx */
1571 /* check for transmit completes and receives */
1572 send_done_count = ntohl(stats->send_done_count);
1573 if (send_done_count != tx->pkt_done)
1574 myri10ge_tx_done(ss, (int)send_done_count);
1575 if (unlikely(i > myri10ge_max_irq_loops)) {
1576 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1579 schedule_work(&mgp->watchdog_work);
1581 if (likely(stats->valid == 0))
1587 /* Only slice 0 updates stats */
1589 myri10ge_check_statblock(mgp);
1591 put_be32(htonl(3), ss->irq_claim + 1);
1592 return (IRQ_HANDLED);
1596 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1598 struct myri10ge_priv *mgp = netdev_priv(netdev);
1602 cmd->autoneg = AUTONEG_DISABLE;
1603 cmd->speed = SPEED_10000;
1604 cmd->duplex = DUPLEX_FULL;
1607 * parse the product code to deterimine the interface type
1608 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1609 * after the 3rd dash in the driver's cached copy of the
1610 * EEPROM's product code string.
1612 ptr = mgp->product_code_string;
1614 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1618 for (i = 0; i < 3; i++, ptr++) {
1619 ptr = strchr(ptr, '-');
1621 printk(KERN_ERR "myri10ge: %s: Invalid product "
1622 "code %s\n", netdev->name,
1623 mgp->product_code_string);
1627 if (*ptr == 'R' || *ptr == 'Q') {
1628 /* We've found either an XFP or quad ribbon fiber */
1629 cmd->port = PORT_FIBRE;
1635 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1637 struct myri10ge_priv *mgp = netdev_priv(netdev);
1639 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1640 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1641 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1642 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1646 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1648 struct myri10ge_priv *mgp = netdev_priv(netdev);
1650 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1655 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1657 struct myri10ge_priv *mgp = netdev_priv(netdev);
1659 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1660 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1665 myri10ge_get_pauseparam(struct net_device *netdev,
1666 struct ethtool_pauseparam *pause)
1668 struct myri10ge_priv *mgp = netdev_priv(netdev);
1671 pause->rx_pause = mgp->pause;
1672 pause->tx_pause = mgp->pause;
1676 myri10ge_set_pauseparam(struct net_device *netdev,
1677 struct ethtool_pauseparam *pause)
1679 struct myri10ge_priv *mgp = netdev_priv(netdev);
1681 if (pause->tx_pause != mgp->pause)
1682 return myri10ge_change_pause(mgp, pause->tx_pause);
1683 if (pause->rx_pause != mgp->pause)
1684 return myri10ge_change_pause(mgp, pause->tx_pause);
1685 if (pause->autoneg != 0)
1691 myri10ge_get_ringparam(struct net_device *netdev,
1692 struct ethtool_ringparam *ring)
1694 struct myri10ge_priv *mgp = netdev_priv(netdev);
1696 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1697 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1698 ring->rx_jumbo_max_pending = 0;
1699 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1700 ring->rx_mini_pending = ring->rx_mini_max_pending;
1701 ring->rx_pending = ring->rx_max_pending;
1702 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1703 ring->tx_pending = ring->tx_max_pending;
1706 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1708 struct myri10ge_priv *mgp = netdev_priv(netdev);
1716 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1718 struct myri10ge_priv *mgp = netdev_priv(netdev);
1722 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1724 u32 flags = ethtool_op_get_flags(netdev);
1725 err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO));
1732 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1734 struct myri10ge_priv *mgp = netdev_priv(netdev);
1735 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1738 netdev->features |= flags;
1740 netdev->features &= ~flags;
1744 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1745 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1746 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1747 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1748 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1749 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1750 "tx_heartbeat_errors", "tx_window_errors",
1751 /* device-specific stats */
1752 "tx_boundary", "WC", "irq", "MSI", "MSIX",
1753 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1754 "serial_number", "watchdog_resets",
1755 #ifdef CONFIG_MYRI10GE_DCA
1756 "dca_capable_firmware", "dca_device_present",
1758 "link_changes", "link_up", "dropped_link_overflow",
1759 "dropped_link_error_or_filtered",
1760 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1761 "dropped_unicast_filtered", "dropped_multicast_filtered",
1762 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1763 "dropped_no_big_buffer"
1766 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1767 "----------- slice ---------",
1768 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1769 "rx_small_cnt", "rx_big_cnt",
1770 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1772 "LRO avg aggr", "LRO no_desc"
1775 #define MYRI10GE_NET_STATS_LEN 21
1776 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1777 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1780 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1782 struct myri10ge_priv *mgp = netdev_priv(netdev);
1785 switch (stringset) {
1787 memcpy(data, *myri10ge_gstrings_main_stats,
1788 sizeof(myri10ge_gstrings_main_stats));
1789 data += sizeof(myri10ge_gstrings_main_stats);
1790 for (i = 0; i < mgp->num_slices; i++) {
1791 memcpy(data, *myri10ge_gstrings_slice_stats,
1792 sizeof(myri10ge_gstrings_slice_stats));
1793 data += sizeof(myri10ge_gstrings_slice_stats);
1799 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1801 struct myri10ge_priv *mgp = netdev_priv(netdev);
1805 return MYRI10GE_MAIN_STATS_LEN +
1806 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1813 myri10ge_get_ethtool_stats(struct net_device *netdev,
1814 struct ethtool_stats *stats, u64 * data)
1816 struct myri10ge_priv *mgp = netdev_priv(netdev);
1817 struct myri10ge_slice_state *ss;
1821 /* force stats update */
1822 (void)myri10ge_get_stats(netdev);
1823 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1824 data[i] = ((unsigned long *)&mgp->stats)[i];
1826 data[i++] = (unsigned int)mgp->tx_boundary;
1827 data[i++] = (unsigned int)mgp->wc_enabled;
1828 data[i++] = (unsigned int)mgp->pdev->irq;
1829 data[i++] = (unsigned int)mgp->msi_enabled;
1830 data[i++] = (unsigned int)mgp->msix_enabled;
1831 data[i++] = (unsigned int)mgp->read_dma;
1832 data[i++] = (unsigned int)mgp->write_dma;
1833 data[i++] = (unsigned int)mgp->read_write_dma;
1834 data[i++] = (unsigned int)mgp->serial_number;
1835 data[i++] = (unsigned int)mgp->watchdog_resets;
1836 #ifdef CONFIG_MYRI10GE_DCA
1837 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1838 data[i++] = (unsigned int)(mgp->dca_enabled);
1840 data[i++] = (unsigned int)mgp->link_changes;
1842 /* firmware stats are useful only in the first slice */
1844 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1845 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1847 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1848 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1849 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1850 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1851 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1853 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1854 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1855 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1856 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1857 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1859 for (slice = 0; slice < mgp->num_slices; slice++) {
1860 ss = &mgp->ss[slice];
1862 data[i++] = (unsigned int)ss->tx.pkt_start;
1863 data[i++] = (unsigned int)ss->tx.pkt_done;
1864 data[i++] = (unsigned int)ss->tx.req;
1865 data[i++] = (unsigned int)ss->tx.done;
1866 data[i++] = (unsigned int)ss->rx_small.cnt;
1867 data[i++] = (unsigned int)ss->rx_big.cnt;
1868 data[i++] = (unsigned int)ss->tx.wake_queue;
1869 data[i++] = (unsigned int)ss->tx.stop_queue;
1870 data[i++] = (unsigned int)ss->tx.linearized;
1871 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1872 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1873 if (ss->rx_done.lro_mgr.stats.flushed)
1874 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1875 ss->rx_done.lro_mgr.stats.flushed;
1878 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1882 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1884 struct myri10ge_priv *mgp = netdev_priv(netdev);
1885 mgp->msg_enable = value;
1888 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1890 struct myri10ge_priv *mgp = netdev_priv(netdev);
1891 return mgp->msg_enable;
1894 static const struct ethtool_ops myri10ge_ethtool_ops = {
1895 .get_settings = myri10ge_get_settings,
1896 .get_drvinfo = myri10ge_get_drvinfo,
1897 .get_coalesce = myri10ge_get_coalesce,
1898 .set_coalesce = myri10ge_set_coalesce,
1899 .get_pauseparam = myri10ge_get_pauseparam,
1900 .set_pauseparam = myri10ge_set_pauseparam,
1901 .get_ringparam = myri10ge_get_ringparam,
1902 .get_rx_csum = myri10ge_get_rx_csum,
1903 .set_rx_csum = myri10ge_set_rx_csum,
1904 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1905 .set_sg = ethtool_op_set_sg,
1906 .set_tso = myri10ge_set_tso,
1907 .get_link = ethtool_op_get_link,
1908 .get_strings = myri10ge_get_strings,
1909 .get_sset_count = myri10ge_get_sset_count,
1910 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1911 .set_msglevel = myri10ge_set_msglevel,
1912 .get_msglevel = myri10ge_get_msglevel,
1913 .get_flags = ethtool_op_get_flags,
1914 .set_flags = ethtool_op_set_flags
1917 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1919 struct myri10ge_priv *mgp = ss->mgp;
1920 struct myri10ge_cmd cmd;
1921 struct net_device *dev = mgp->dev;
1922 int tx_ring_size, rx_ring_size;
1923 int tx_ring_entries, rx_ring_entries;
1924 int i, slice, status;
1927 /* get ring sizes */
1928 slice = ss - mgp->ss;
1930 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1931 tx_ring_size = cmd.data0;
1933 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1936 rx_ring_size = cmd.data0;
1938 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1939 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1940 ss->tx.mask = tx_ring_entries - 1;
1941 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1945 /* allocate the host shadow rings */
1947 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1948 * sizeof(*ss->tx.req_list);
1949 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1950 if (ss->tx.req_bytes == NULL)
1951 goto abort_with_nothing;
1953 /* ensure req_list entries are aligned to 8 bytes */
1954 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1955 ALIGN((unsigned long)ss->tx.req_bytes, 8);
1956 ss->tx.queue_active = 0;
1958 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1959 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1960 if (ss->rx_small.shadow == NULL)
1961 goto abort_with_tx_req_bytes;
1963 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1964 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1965 if (ss->rx_big.shadow == NULL)
1966 goto abort_with_rx_small_shadow;
1968 /* allocate the host info rings */
1970 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1971 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1972 if (ss->tx.info == NULL)
1973 goto abort_with_rx_big_shadow;
1975 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1976 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1977 if (ss->rx_small.info == NULL)
1978 goto abort_with_tx_info;
1980 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1981 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1982 if (ss->rx_big.info == NULL)
1983 goto abort_with_rx_small_info;
1985 /* Fill the receive rings */
1987 ss->rx_small.cnt = 0;
1988 ss->rx_big.fill_cnt = 0;
1989 ss->rx_small.fill_cnt = 0;
1990 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1991 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1992 ss->rx_small.watchdog_needed = 0;
1993 ss->rx_big.watchdog_needed = 0;
1994 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1995 mgp->small_bytes + MXGEFW_PAD, 0);
1997 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1999 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
2000 dev->name, slice, ss->rx_small.fill_cnt);
2001 goto abort_with_rx_small_ring;
2004 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2005 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
2007 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
2008 dev->name, slice, ss->rx_big.fill_cnt);
2009 goto abort_with_rx_big_ring;
2014 abort_with_rx_big_ring:
2015 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2016 int idx = i & ss->rx_big.mask;
2017 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2019 put_page(ss->rx_big.info[idx].page);
2022 abort_with_rx_small_ring:
2023 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2024 int idx = i & ss->rx_small.mask;
2025 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2026 mgp->small_bytes + MXGEFW_PAD);
2027 put_page(ss->rx_small.info[idx].page);
2030 kfree(ss->rx_big.info);
2032 abort_with_rx_small_info:
2033 kfree(ss->rx_small.info);
2038 abort_with_rx_big_shadow:
2039 kfree(ss->rx_big.shadow);
2041 abort_with_rx_small_shadow:
2042 kfree(ss->rx_small.shadow);
2044 abort_with_tx_req_bytes:
2045 kfree(ss->tx.req_bytes);
2046 ss->tx.req_bytes = NULL;
2047 ss->tx.req_list = NULL;
2053 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2055 struct myri10ge_priv *mgp = ss->mgp;
2056 struct sk_buff *skb;
2057 struct myri10ge_tx_buf *tx;
2060 /* If not allocated, skip it */
2061 if (ss->tx.req_list == NULL)
2064 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2065 idx = i & ss->rx_big.mask;
2066 if (i == ss->rx_big.fill_cnt - 1)
2067 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2068 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2070 put_page(ss->rx_big.info[idx].page);
2073 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2074 idx = i & ss->rx_small.mask;
2075 if (i == ss->rx_small.fill_cnt - 1)
2076 ss->rx_small.info[idx].page_offset =
2077 MYRI10GE_ALLOC_SIZE;
2078 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2079 mgp->small_bytes + MXGEFW_PAD);
2080 put_page(ss->rx_small.info[idx].page);
2083 while (tx->done != tx->req) {
2084 idx = tx->done & tx->mask;
2085 skb = tx->info[idx].skb;
2088 tx->info[idx].skb = NULL;
2090 len = pci_unmap_len(&tx->info[idx], len);
2091 pci_unmap_len_set(&tx->info[idx], len, 0);
2093 ss->stats.tx_dropped++;
2094 dev_kfree_skb_any(skb);
2096 pci_unmap_single(mgp->pdev,
2097 pci_unmap_addr(&tx->info[idx],
2102 pci_unmap_page(mgp->pdev,
2103 pci_unmap_addr(&tx->info[idx],
2108 kfree(ss->rx_big.info);
2110 kfree(ss->rx_small.info);
2114 kfree(ss->rx_big.shadow);
2116 kfree(ss->rx_small.shadow);
2118 kfree(ss->tx.req_bytes);
2119 ss->tx.req_bytes = NULL;
2120 ss->tx.req_list = NULL;
2123 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2125 struct pci_dev *pdev = mgp->pdev;
2126 struct myri10ge_slice_state *ss;
2127 struct net_device *netdev = mgp->dev;
2131 mgp->msi_enabled = 0;
2132 mgp->msix_enabled = 0;
2135 if (mgp->num_slices > 1) {
2137 pci_enable_msix(pdev, mgp->msix_vectors,
2140 mgp->msix_enabled = 1;
2143 "Error %d setting up MSI-X\n", status);
2147 if (mgp->msix_enabled == 0) {
2148 status = pci_enable_msi(pdev);
2151 "Error %d setting up MSI; falling back to xPIC\n",
2154 mgp->msi_enabled = 1;
2158 if (mgp->msix_enabled) {
2159 for (i = 0; i < mgp->num_slices; i++) {
2161 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2162 "%s:slice-%d", netdev->name, i);
2163 status = request_irq(mgp->msix_vectors[i].vector,
2164 myri10ge_intr, 0, ss->irq_desc,
2168 "slice %d failed to allocate IRQ\n", i);
2171 free_irq(mgp->msix_vectors[i].vector,
2175 pci_disable_msix(pdev);
2180 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2181 mgp->dev->name, &mgp->ss[0]);
2183 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2184 if (mgp->msi_enabled)
2185 pci_disable_msi(pdev);
2191 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2193 struct pci_dev *pdev = mgp->pdev;
2196 if (mgp->msix_enabled) {
2197 for (i = 0; i < mgp->num_slices; i++)
2198 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2200 free_irq(pdev->irq, &mgp->ss[0]);
2202 if (mgp->msi_enabled)
2203 pci_disable_msi(pdev);
2204 if (mgp->msix_enabled)
2205 pci_disable_msix(pdev);
2209 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2210 void **ip_hdr, void **tcpudp_hdr,
2211 u64 * hdr_flags, void *priv)
2214 struct vlan_ethhdr *veh;
2216 u8 *va = page_address(frag->page) + frag->page_offset;
2217 unsigned long ll_hlen;
2218 /* passed opaque through lro_receive_frags() */
2219 __wsum csum = (__force __wsum) (unsigned long)priv;
2221 /* find the mac header, aborting if not IPv4 */
2223 eh = (struct ethhdr *)va;
2226 if (eh->h_proto != htons(ETH_P_IP)) {
2227 if (eh->h_proto == htons(ETH_P_8021Q)) {
2228 veh = (struct vlan_ethhdr *)va;
2229 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2232 ll_hlen += VLAN_HLEN;
2235 * HW checksum starts ETH_HLEN bytes into
2236 * frame, so we must subtract off the VLAN
2237 * header's checksum before csum can be used
2239 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2245 *hdr_flags = LRO_IPV4;
2247 iph = (struct iphdr *)(va + ll_hlen);
2249 if (iph->protocol != IPPROTO_TCP)
2251 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2253 *hdr_flags |= LRO_TCP;
2254 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2256 /* verify the IP checksum */
2257 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2260 /* verify the checksum */
2261 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2262 ntohs(iph->tot_len) - (iph->ihl << 2),
2263 IPPROTO_TCP, csum)))
2269 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2271 struct myri10ge_cmd cmd;
2272 struct myri10ge_slice_state *ss;
2275 ss = &mgp->ss[slice];
2277 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2279 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2281 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2282 (mgp->sram + cmd.data0);
2285 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2287 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2288 (mgp->sram + cmd.data0);
2291 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2292 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2293 (mgp->sram + cmd.data0);
2295 ss->tx.send_go = (__iomem __be32 *)
2296 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2297 ss->tx.send_stop = (__iomem __be32 *)
2298 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2303 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2305 struct myri10ge_cmd cmd;
2306 struct myri10ge_slice_state *ss;
2309 ss = &mgp->ss[slice];
2310 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2311 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2312 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2313 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2314 if (status == -ENOSYS) {
2315 dma_addr_t bus = ss->fw_stats_bus;
2318 bus += offsetof(struct mcp_irq_data, send_done_count);
2319 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2320 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2321 status = myri10ge_send_cmd(mgp,
2322 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2324 /* Firmware cannot support multicast without STATS_DMA_V2 */
2325 mgp->fw_multicast_support = 0;
2327 mgp->fw_multicast_support = 1;
2332 static int myri10ge_open(struct net_device *dev)
2334 struct myri10ge_slice_state *ss;
2335 struct myri10ge_priv *mgp = netdev_priv(dev);
2336 struct myri10ge_cmd cmd;
2337 int i, status, big_pow2, slice;
2339 struct net_lro_mgr *lro_mgr;
2341 if (mgp->running != MYRI10GE_ETH_STOPPED)
2344 mgp->running = MYRI10GE_ETH_STARTING;
2345 status = myri10ge_reset(mgp);
2347 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2348 goto abort_with_nothing;
2351 if (mgp->num_slices > 1) {
2352 cmd.data0 = mgp->num_slices;
2353 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2354 if (mgp->dev->real_num_tx_queues > 1)
2355 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2356 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2360 "myri10ge: %s: failed to set number of slices\n",
2362 goto abort_with_nothing;
2364 /* setup the indirection table */
2365 cmd.data0 = mgp->num_slices;
2366 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2369 status |= myri10ge_send_cmd(mgp,
2370 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2374 "myri10ge: %s: failed to setup rss tables\n",
2376 goto abort_with_nothing;
2379 /* just enable an identity mapping */
2380 itable = mgp->sram + cmd.data0;
2381 for (i = 0; i < mgp->num_slices; i++)
2382 __raw_writeb(i, &itable[i]);
2385 cmd.data1 = myri10ge_rss_hash;
2386 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2390 "myri10ge: %s: failed to enable slices\n",
2392 goto abort_with_nothing;
2396 status = myri10ge_request_irq(mgp);
2398 goto abort_with_nothing;
2400 /* decide what small buffer size to use. For good TCP rx
2401 * performance, it is important to not receive 1514 byte
2402 * frames into jumbo buffers, as it confuses the socket buffer
2403 * accounting code, leading to drops and erratic performance.
2406 if (dev->mtu <= ETH_DATA_LEN)
2407 /* enough for a TCP header */
2408 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2409 ? (128 - MXGEFW_PAD)
2410 : (SMP_CACHE_BYTES - MXGEFW_PAD);
2412 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2413 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2415 /* Override the small buffer size? */
2416 if (myri10ge_small_bytes > 0)
2417 mgp->small_bytes = myri10ge_small_bytes;
2419 /* Firmware needs the big buff size as a power of 2. Lie and
2420 * tell him the buffer is larger, because we only use 1
2421 * buffer/pkt, and the mtu will prevent overruns.
2423 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2424 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2425 while (!is_power_of_2(big_pow2))
2427 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2429 big_pow2 = MYRI10GE_ALLOC_SIZE;
2430 mgp->big_bytes = big_pow2;
2433 /* setup the per-slice data structures */
2434 for (slice = 0; slice < mgp->num_slices; slice++) {
2435 ss = &mgp->ss[slice];
2437 status = myri10ge_get_txrx(mgp, slice);
2440 "myri10ge: %s: failed to get ring sizes or locations\n",
2442 goto abort_with_rings;
2444 status = myri10ge_allocate_rings(ss);
2446 goto abort_with_rings;
2448 /* only firmware which supports multiple TX queues
2449 * supports setting up the tx stats on non-zero
2451 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2452 status = myri10ge_set_stats(mgp, slice);
2455 "myri10ge: %s: Couldn't set stats DMA\n",
2457 goto abort_with_rings;
2460 lro_mgr = &ss->rx_done.lro_mgr;
2462 lro_mgr->features = LRO_F_NAPI;
2463 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2464 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2465 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2466 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2467 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2468 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2469 lro_mgr->frag_align_pad = 2;
2470 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2471 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2473 /* must happen prior to any irq */
2474 napi_enable(&(ss)->napi);
2477 /* now give firmware buffers sizes, and MTU */
2478 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2479 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2480 cmd.data0 = mgp->small_bytes;
2482 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2483 cmd.data0 = big_pow2;
2485 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2487 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2489 goto abort_with_rings;
2493 * Set Linux style TSO mode; this is needed only on newer
2494 * firmware versions. Older versions default to Linux
2498 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2499 if (status && status != -ENOSYS) {
2500 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2502 goto abort_with_rings;
2505 mgp->link_state = ~0U;
2506 mgp->rdma_tags_available = 15;
2508 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2510 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2512 goto abort_with_rings;
2515 mgp->running = MYRI10GE_ETH_RUNNING;
2516 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2517 add_timer(&mgp->watchdog_timer);
2518 netif_tx_wake_all_queues(dev);
2525 napi_disable(&mgp->ss[slice].napi);
2527 for (i = 0; i < mgp->num_slices; i++)
2528 myri10ge_free_rings(&mgp->ss[i]);
2530 myri10ge_free_irq(mgp);
2533 mgp->running = MYRI10GE_ETH_STOPPED;
2537 static int myri10ge_close(struct net_device *dev)
2539 struct myri10ge_priv *mgp = netdev_priv(dev);
2540 struct myri10ge_cmd cmd;
2541 int status, old_down_cnt;
2544 if (mgp->running != MYRI10GE_ETH_RUNNING)
2547 if (mgp->ss[0].tx.req_bytes == NULL)
2550 del_timer_sync(&mgp->watchdog_timer);
2551 mgp->running = MYRI10GE_ETH_STOPPING;
2552 for (i = 0; i < mgp->num_slices; i++) {
2553 napi_disable(&mgp->ss[i].napi);
2555 netif_carrier_off(dev);
2557 netif_tx_stop_all_queues(dev);
2558 old_down_cnt = mgp->down_cnt;
2560 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2562 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2565 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2566 if (old_down_cnt == mgp->down_cnt)
2567 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2569 netif_tx_disable(dev);
2570 myri10ge_free_irq(mgp);
2571 for (i = 0; i < mgp->num_slices; i++)
2572 myri10ge_free_rings(&mgp->ss[i]);
2574 mgp->running = MYRI10GE_ETH_STOPPED;
2578 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2579 * backwards one at a time and handle ring wraps */
2582 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2583 struct mcp_kreq_ether_send *src, int cnt)
2585 int idx, starting_slot;
2586 starting_slot = tx->req;
2589 idx = (starting_slot + cnt) & tx->mask;
2590 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2596 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2597 * at most 32 bytes at a time, so as to avoid involving the software
2598 * pio handler in the nic. We re-write the first segment's flags
2599 * to mark them valid only after writing the entire chain.
2603 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2607 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2608 struct mcp_kreq_ether_send *srcp;
2611 idx = tx->req & tx->mask;
2613 last_flags = src->flags;
2616 dst = dstp = &tx->lanai[idx];
2619 if ((idx + cnt) < tx->mask) {
2620 for (i = 0; i < (cnt - 1); i += 2) {
2621 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2622 mb(); /* force write every 32 bytes */
2627 /* submit all but the first request, and ensure
2628 * that it is submitted below */
2629 myri10ge_submit_req_backwards(tx, src, cnt);
2633 /* submit the first request */
2634 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2635 mb(); /* barrier before setting valid flag */
2638 /* re-write the last 32-bits with the valid flags */
2639 src->flags = last_flags;
2640 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2646 * Transmit a packet. We need to split the packet so that a single
2647 * segment does not cross myri10ge->tx_boundary, so this makes segment
2648 * counting tricky. So rather than try to count segments up front, we
2649 * just give up if there are too few segments to hold a reasonably
2650 * fragmented packet currently available. If we run
2651 * out of segments while preparing a packet for DMA, we just linearize
2655 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2657 struct myri10ge_priv *mgp = netdev_priv(dev);
2658 struct myri10ge_slice_state *ss;
2659 struct mcp_kreq_ether_send *req;
2660 struct myri10ge_tx_buf *tx;
2661 struct skb_frag_struct *frag;
2662 struct netdev_queue *netdev_queue;
2665 __be32 high_swapped;
2667 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2668 u16 pseudo_hdr_offset, cksum_offset, queue;
2669 int cum_len, seglen, boundary, rdma_count;
2672 queue = skb_get_queue_mapping(skb);
2673 ss = &mgp->ss[queue];
2674 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2679 avail = tx->mask - 1 - (tx->req - tx->done);
2682 max_segments = MXGEFW_MAX_SEND_DESC;
2684 if (skb_is_gso(skb)) {
2685 mss = skb_shinfo(skb)->gso_size;
2686 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2689 if ((unlikely(avail < max_segments))) {
2690 /* we are out of transmit resources */
2692 netif_tx_stop_queue(netdev_queue);
2696 /* Setup checksum offloading, if needed */
2698 pseudo_hdr_offset = 0;
2700 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2701 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2702 cksum_offset = skb_transport_offset(skb);
2703 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2704 /* If the headers are excessively large, then we must
2705 * fall back to a software checksum */
2706 if (unlikely(!mss && (cksum_offset > 255 ||
2707 pseudo_hdr_offset > 127))) {
2708 if (skb_checksum_help(skb))
2711 pseudo_hdr_offset = 0;
2713 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2714 flags |= MXGEFW_FLAGS_CKSUM;
2720 if (mss) { /* TSO */
2721 /* this removes any CKSUM flag from before */
2722 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2724 /* negative cum_len signifies to the
2725 * send loop that we are still in the
2726 * header portion of the TSO packet.
2727 * TSO header can be at most 1KB long */
2728 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2730 /* for IPv6 TSO, the checksum offset stores the
2731 * TCP header length, to save the firmware from
2732 * the need to parse the headers */
2733 if (skb_is_gso_v6(skb)) {
2734 cksum_offset = tcp_hdrlen(skb);
2735 /* Can only handle headers <= max_tso6 long */
2736 if (unlikely(-cum_len > mgp->max_tso6))
2737 return myri10ge_sw_tso(skb, dev);
2739 /* for TSO, pseudo_hdr_offset holds mss.
2740 * The firmware figures out where to put
2741 * the checksum by parsing the header. */
2742 pseudo_hdr_offset = mss;
2744 /* Mark small packets, and pad out tiny packets */
2745 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2746 flags |= MXGEFW_FLAGS_SMALL;
2748 /* pad frames to at least ETH_ZLEN bytes */
2749 if (unlikely(skb->len < ETH_ZLEN)) {
2750 if (skb_padto(skb, ETH_ZLEN)) {
2751 /* The packet is gone, so we must
2753 ss->stats.tx_dropped += 1;
2756 /* adjust the len to account for the zero pad
2757 * so that the nic can know how long it is */
2758 skb->len = ETH_ZLEN;
2762 /* map the skb for DMA */
2763 len = skb->len - skb->data_len;
2764 idx = tx->req & tx->mask;
2765 tx->info[idx].skb = skb;
2766 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2767 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2768 pci_unmap_len_set(&tx->info[idx], len, len);
2770 frag_cnt = skb_shinfo(skb)->nr_frags;
2775 /* "rdma_count" is the number of RDMAs belonging to the
2776 * current packet BEFORE the current send request. For
2777 * non-TSO packets, this is equal to "count".
2778 * For TSO packets, rdma_count needs to be reset
2779 * to 0 after a segment cut.
2781 * The rdma_count field of the send request is
2782 * the number of RDMAs of the packet starting at
2783 * that request. For TSO send requests with one ore more cuts
2784 * in the middle, this is the number of RDMAs starting
2785 * after the last cut in the request. All previous
2786 * segments before the last cut implicitly have 1 RDMA.
2788 * Since the number of RDMAs is not known beforehand,
2789 * it must be filled-in retroactively - after each
2790 * segmentation cut or at the end of the entire packet.
2794 /* Break the SKB or Fragment up into pieces which
2795 * do not cross mgp->tx_boundary */
2796 low = MYRI10GE_LOWPART_TO_U32(bus);
2797 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2802 if (unlikely(count == max_segments))
2803 goto abort_linearize;
2806 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2807 seglen = boundary - low;
2810 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2811 cum_len_next = cum_len + seglen;
2812 if (mss) { /* TSO */
2813 (req - rdma_count)->rdma_count = rdma_count + 1;
2815 if (likely(cum_len >= 0)) { /* payload */
2816 int next_is_first, chop;
2818 chop = (cum_len_next > mss);
2819 cum_len_next = cum_len_next % mss;
2820 next_is_first = (cum_len_next == 0);
2821 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2822 flags_next |= next_is_first *
2824 rdma_count |= -(chop | next_is_first);
2825 rdma_count += chop & !next_is_first;
2826 } else if (likely(cum_len_next >= 0)) { /* header ends */
2832 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2833 flags_next = MXGEFW_FLAGS_TSO_PLD |
2834 MXGEFW_FLAGS_FIRST |
2835 (small * MXGEFW_FLAGS_SMALL);
2838 req->addr_high = high_swapped;
2839 req->addr_low = htonl(low);
2840 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2841 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2842 req->rdma_count = 1;
2843 req->length = htons(seglen);
2844 req->cksum_offset = cksum_offset;
2845 req->flags = flags | ((cum_len & 1) * odd_flag);
2849 cum_len = cum_len_next;
2854 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2855 if (unlikely(cksum_offset > seglen))
2856 cksum_offset -= seglen;
2861 if (frag_idx == frag_cnt)
2864 /* map next fragment for DMA */
2865 idx = (count + tx->req) & tx->mask;
2866 frag = &skb_shinfo(skb)->frags[frag_idx];
2869 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2870 len, PCI_DMA_TODEVICE);
2871 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2872 pci_unmap_len_set(&tx->info[idx], len, len);
2875 (req - rdma_count)->rdma_count = rdma_count;
2879 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2880 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2881 MXGEFW_FLAGS_FIRST)));
2882 idx = ((count - 1) + tx->req) & tx->mask;
2883 tx->info[idx].last = 1;
2884 myri10ge_submit_req(tx, tx->req_list, count);
2885 /* if using multiple tx queues, make sure NIC polls the
2887 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2888 tx->queue_active = 1;
2889 put_be32(htonl(1), tx->send_go);
2894 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2896 netif_tx_stop_queue(netdev_queue);
2898 dev->trans_start = jiffies;
2902 /* Free any DMA resources we've alloced and clear out the skb
2903 * slot so as to not trip up assertions, and to avoid a
2904 * double-free if linearizing fails */
2906 last_idx = (idx + 1) & tx->mask;
2907 idx = tx->req & tx->mask;
2908 tx->info[idx].skb = NULL;
2910 len = pci_unmap_len(&tx->info[idx], len);
2912 if (tx->info[idx].skb != NULL)
2913 pci_unmap_single(mgp->pdev,
2914 pci_unmap_addr(&tx->info[idx],
2918 pci_unmap_page(mgp->pdev,
2919 pci_unmap_addr(&tx->info[idx],
2922 pci_unmap_len_set(&tx->info[idx], len, 0);
2923 tx->info[idx].skb = NULL;
2925 idx = (idx + 1) & tx->mask;
2926 } while (idx != last_idx);
2927 if (skb_is_gso(skb)) {
2929 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2934 if (skb_linearize(skb))
2941 dev_kfree_skb_any(skb);
2942 ss->stats.tx_dropped += 1;
2947 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2949 struct sk_buff *segs, *curr;
2950 struct myri10ge_priv *mgp = netdev_priv(dev);
2951 struct myri10ge_slice_state *ss;
2954 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2962 status = myri10ge_xmit(curr, dev);
2964 dev_kfree_skb_any(curr);
2969 dev_kfree_skb_any(segs);
2974 dev_kfree_skb_any(skb);
2978 ss = &mgp->ss[skb_get_queue_mapping(skb)];
2979 dev_kfree_skb_any(skb);
2980 ss->stats.tx_dropped += 1;
2984 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2986 struct myri10ge_priv *mgp = netdev_priv(dev);
2987 struct myri10ge_slice_netstats *slice_stats;
2988 struct net_device_stats *stats = &mgp->stats;
2991 spin_lock(&mgp->stats_lock);
2992 memset(stats, 0, sizeof(*stats));
2993 for (i = 0; i < mgp->num_slices; i++) {
2994 slice_stats = &mgp->ss[i].stats;
2995 stats->rx_packets += slice_stats->rx_packets;
2996 stats->tx_packets += slice_stats->tx_packets;
2997 stats->rx_bytes += slice_stats->rx_bytes;
2998 stats->tx_bytes += slice_stats->tx_bytes;
2999 stats->rx_dropped += slice_stats->rx_dropped;
3000 stats->tx_dropped += slice_stats->tx_dropped;
3002 spin_unlock(&mgp->stats_lock);
3006 static void myri10ge_set_multicast_list(struct net_device *dev)
3008 struct myri10ge_priv *mgp = netdev_priv(dev);
3009 struct myri10ge_cmd cmd;
3010 struct dev_mc_list *mc_list;
3011 __be32 data[2] = { 0, 0 };
3014 /* can be called from atomic contexts,
3015 * pass 1 to force atomicity in myri10ge_send_cmd() */
3016 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3018 /* This firmware is known to not support multicast */
3019 if (!mgp->fw_multicast_support)
3022 /* Disable multicast filtering */
3024 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3026 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3027 " error status: %d\n", dev->name, err);
3031 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3032 /* request to disable multicast filtering, so quit here */
3036 /* Flush the filters */
3038 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3042 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3043 ", error status: %d\n", dev->name, err);
3047 /* Walk the multicast list, and add each address */
3048 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
3049 memcpy(data, &mc_list->dmi_addr, 6);
3050 cmd.data0 = ntohl(data[0]);
3051 cmd.data1 = ntohl(data[1]);
3052 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3056 printk(KERN_ERR "myri10ge: %s: Failed "
3057 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3058 "%d\t", dev->name, err);
3059 printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
3063 /* Enable multicast filtering */
3064 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3066 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3067 "error status: %d\n", dev->name, err);
3077 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3079 struct sockaddr *sa = addr;
3080 struct myri10ge_priv *mgp = netdev_priv(dev);
3083 if (!is_valid_ether_addr(sa->sa_data))
3084 return -EADDRNOTAVAIL;
3086 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3089 "myri10ge: %s: changing mac address failed with %d\n",
3094 /* change the dev structure */
3095 memcpy(dev->dev_addr, sa->sa_data, 6);
3099 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3101 struct myri10ge_priv *mgp = netdev_priv(dev);
3104 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3105 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3106 dev->name, new_mtu);
3109 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3110 dev->name, dev->mtu, new_mtu);
3112 /* if we change the mtu on an active device, we must
3113 * reset the device so the firmware sees the change */
3114 myri10ge_close(dev);
3124 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3125 * Only do it if the bridge is a root port since we don't want to disturb
3126 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3129 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3131 struct pci_dev *bridge = mgp->pdev->bus->self;
3132 struct device *dev = &mgp->pdev->dev;
3139 if (!myri10ge_ecrc_enable || !bridge)
3142 /* check that the bridge is a root port */
3143 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3144 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3145 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3146 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3147 if (myri10ge_ecrc_enable > 1) {
3148 struct pci_dev *prev_bridge, *old_bridge = bridge;
3150 /* Walk the hierarchy up to the root port
3151 * where ECRC has to be enabled */
3153 prev_bridge = bridge;
3154 bridge = bridge->bus->self;
3155 if (!bridge || prev_bridge == bridge) {
3157 "Failed to find root port"
3158 " to force ECRC\n");
3162 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3163 pci_read_config_word(bridge,
3164 cap + PCI_CAP_FLAGS, &val);
3165 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3166 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3169 "Forcing ECRC on non-root port %s"
3170 " (enabling on root port %s)\n",
3171 pci_name(old_bridge), pci_name(bridge));
3174 "Not enabling ECRC on non-root port %s\n",
3180 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3184 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3186 dev_err(dev, "failed reading ext-conf-space of %s\n",
3188 dev_err(dev, "\t pci=nommconf in use? "
3189 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3192 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3195 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3196 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3197 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3201 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3202 * when the PCI-E Completion packets are aligned on an 8-byte
3203 * boundary. Some PCI-E chip sets always align Completion packets; on
3204 * the ones that do not, the alignment can be enforced by enabling
3205 * ECRC generation (if supported).
3207 * When PCI-E Completion packets are not aligned, it is actually more
3208 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3210 * If the driver can neither enable ECRC nor verify that it has
3211 * already been enabled, then it must use a firmware image which works
3212 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3213 * should also ensure that it never gives the device a Read-DMA which is
3214 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
3215 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3216 * firmware image, and set tx_boundary to 4KB.
3219 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3221 struct pci_dev *pdev = mgp->pdev;
3222 struct device *dev = &pdev->dev;
3225 mgp->tx_boundary = 4096;
3227 * Verify the max read request size was set to 4KB
3228 * before trying the test with 4KB.
3230 status = pcie_get_readrq(pdev);
3232 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3235 if (status != 4096) {
3236 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3237 mgp->tx_boundary = 2048;
3240 * load the optimized firmware (which assumes aligned PCIe
3241 * completions) in order to see if it works on this host.
3243 mgp->fw_name = myri10ge_fw_aligned;
3244 status = myri10ge_load_firmware(mgp, 1);
3250 * Enable ECRC if possible
3252 myri10ge_enable_ecrc(mgp);
3255 * Run a DMA test which watches for unaligned completions and
3256 * aborts on the first one seen.
3259 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3261 return; /* keep the aligned firmware */
3263 if (status != -E2BIG)
3264 dev_warn(dev, "DMA test failed: %d\n", status);
3265 if (status == -ENOSYS)
3266 dev_warn(dev, "Falling back to ethp! "
3267 "Please install up to date fw\n");
3269 /* fall back to using the unaligned firmware */
3270 mgp->tx_boundary = 2048;
3271 mgp->fw_name = myri10ge_fw_unaligned;
3275 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3279 if (myri10ge_force_firmware == 0) {
3280 int link_width, exp_cap;
3283 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3284 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3285 link_width = (lnk >> 4) & 0x3f;
3287 /* Check to see if Link is less than 8 or if the
3288 * upstream bridge is known to provide aligned
3290 if (link_width < 8) {
3291 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3293 mgp->tx_boundary = 4096;
3294 mgp->fw_name = myri10ge_fw_aligned;
3296 myri10ge_firmware_probe(mgp);
3299 if (myri10ge_force_firmware == 1) {
3300 dev_info(&mgp->pdev->dev,
3301 "Assuming aligned completions (forced)\n");
3302 mgp->tx_boundary = 4096;
3303 mgp->fw_name = myri10ge_fw_aligned;
3305 dev_info(&mgp->pdev->dev,
3306 "Assuming unaligned completions (forced)\n");
3307 mgp->tx_boundary = 2048;
3308 mgp->fw_name = myri10ge_fw_unaligned;
3311 if (myri10ge_fw_name != NULL) {
3313 mgp->fw_name = myri10ge_fw_name;
3315 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3316 myri10ge_fw_names[mgp->board_number] != NULL &&
3317 strlen(myri10ge_fw_names[mgp->board_number])) {
3318 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3322 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3327 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3329 struct myri10ge_priv *mgp;
3330 struct net_device *netdev;
3332 mgp = pci_get_drvdata(pdev);
3337 netif_device_detach(netdev);
3338 if (netif_running(netdev)) {
3339 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3341 myri10ge_close(netdev);
3344 myri10ge_dummy_rdma(mgp, 0);
3345 pci_save_state(pdev);
3346 pci_disable_device(pdev);
3348 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3351 static int myri10ge_resume(struct pci_dev *pdev)
3353 struct myri10ge_priv *mgp;
3354 struct net_device *netdev;
3358 mgp = pci_get_drvdata(pdev);
3362 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3363 msleep(5); /* give card time to respond */
3364 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3365 if (vendor == 0xffff) {
3366 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3371 status = pci_restore_state(pdev);
3375 status = pci_enable_device(pdev);
3377 dev_err(&pdev->dev, "failed to enable device\n");
3381 pci_set_master(pdev);
3383 myri10ge_reset(mgp);
3384 myri10ge_dummy_rdma(mgp, 1);
3386 /* Save configuration space to be restored if the
3387 * nic resets due to a parity error */
3388 pci_save_state(pdev);
3390 if (netif_running(netdev)) {
3392 status = myri10ge_open(netdev);
3395 goto abort_with_enabled;
3398 netif_device_attach(netdev);
3403 pci_disable_device(pdev);
3407 #endif /* CONFIG_PM */
3409 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3411 struct pci_dev *pdev = mgp->pdev;
3412 int vs = mgp->vendor_specific_offset;
3415 /*enter read32 mode */
3416 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3418 /*read REBOOT_STATUS (0xfffffff0) */
3419 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3420 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3425 * This watchdog is used to check whether the board has suffered
3426 * from a parity error and needs to be recovered.
3428 static void myri10ge_watchdog(struct work_struct *work)
3430 struct myri10ge_priv *mgp =
3431 container_of(work, struct myri10ge_priv, watchdog_work);
3432 struct myri10ge_tx_buf *tx;
3438 mgp->watchdog_resets++;
3439 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3440 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3441 /* Bus master DMA disabled? Check to see
3442 * if the card rebooted due to a parity error
3443 * For now, just report it */
3444 reboot = myri10ge_read_reboot(mgp);
3446 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3447 mgp->dev->name, reboot,
3448 myri10ge_reset_recover ? " " : " not");
3449 if (myri10ge_reset_recover == 0)
3452 myri10ge_reset_recover--;
3455 * A rebooted nic will come back with config space as
3456 * it was after power was applied to PCIe bus.
3457 * Attempt to restore config space which was saved
3458 * when the driver was loaded, or the last time the
3459 * nic was resumed from power saving mode.
3461 pci_restore_state(mgp->pdev);
3463 /* save state again for accounting reasons */
3464 pci_save_state(mgp->pdev);
3467 /* if we get back -1's from our slot, perhaps somebody
3468 * powered off our card. Don't try to reset it in
3470 if (cmd == 0xffff) {
3471 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3472 if (vendor == 0xffff) {
3474 "myri10ge: %s: device disappeared!\n",
3479 /* Perhaps it is a software error. Try to reset */
3481 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3483 for (i = 0; i < mgp->num_slices; i++) {
3484 tx = &mgp->ss[i].tx;
3486 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3487 mgp->dev->name, i, tx->queue_active, tx->req,
3488 tx->done, tx->pkt_start, tx->pkt_done,
3489 (int)ntohl(mgp->ss[i].fw_stats->
3493 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3494 mgp->dev->name, i, tx->queue_active, tx->req,
3495 tx->done, tx->pkt_start, tx->pkt_done,
3496 (int)ntohl(mgp->ss[i].fw_stats->
3502 myri10ge_close(mgp->dev);
3503 status = myri10ge_load_firmware(mgp, 1);
3505 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3508 myri10ge_open(mgp->dev);
3513 * We use our own timer routine rather than relying upon
3514 * netdev->tx_timeout because we have a very large hardware transmit
3515 * queue. Due to the large queue, the netdev->tx_timeout function
3516 * cannot detect a NIC with a parity error in a timely fashion if the
3517 * NIC is lightly loaded.
3519 static void myri10ge_watchdog_timer(unsigned long arg)
3521 struct myri10ge_priv *mgp;
3522 struct myri10ge_slice_state *ss;
3523 int i, reset_needed;
3526 mgp = (struct myri10ge_priv *)arg;
3528 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3529 for (i = 0, reset_needed = 0;
3530 i < mgp->num_slices && reset_needed == 0; ++i) {
3533 if (ss->rx_small.watchdog_needed) {
3534 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3535 mgp->small_bytes + MXGEFW_PAD,
3537 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3538 myri10ge_fill_thresh)
3539 ss->rx_small.watchdog_needed = 0;
3541 if (ss->rx_big.watchdog_needed) {
3542 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3544 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3545 myri10ge_fill_thresh)
3546 ss->rx_big.watchdog_needed = 0;
3549 if (ss->tx.req != ss->tx.done &&
3550 ss->tx.done == ss->watchdog_tx_done &&
3551 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3552 /* nic seems like it might be stuck.. */
3553 if (rx_pause_cnt != mgp->watchdog_pause) {
3554 if (net_ratelimit())
3556 "myri10ge %s slice %d:"
3557 "TX paused, check link partner\n",
3561 "myri10ge %s slice %d stuck:",
3566 ss->watchdog_tx_done = ss->tx.done;
3567 ss->watchdog_tx_req = ss->tx.req;
3569 mgp->watchdog_pause = rx_pause_cnt;
3572 schedule_work(&mgp->watchdog_work);
3575 mod_timer(&mgp->watchdog_timer,
3576 jiffies + myri10ge_watchdog_timeout * HZ);
3580 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3582 struct myri10ge_slice_state *ss;
3583 struct pci_dev *pdev = mgp->pdev;
3587 if (mgp->ss == NULL)
3590 for (i = 0; i < mgp->num_slices; i++) {
3592 if (ss->rx_done.entry != NULL) {
3593 bytes = mgp->max_intr_slots *
3594 sizeof(*ss->rx_done.entry);
3595 dma_free_coherent(&pdev->dev, bytes,
3596 ss->rx_done.entry, ss->rx_done.bus);
3597 ss->rx_done.entry = NULL;
3599 if (ss->fw_stats != NULL) {
3600 bytes = sizeof(*ss->fw_stats);
3601 dma_free_coherent(&pdev->dev, bytes,
3602 ss->fw_stats, ss->fw_stats_bus);
3603 ss->fw_stats = NULL;
3610 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3612 struct myri10ge_slice_state *ss;
3613 struct pci_dev *pdev = mgp->pdev;
3617 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3618 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3619 if (mgp->ss == NULL) {
3623 for (i = 0; i < mgp->num_slices; i++) {
3625 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3626 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3629 if (ss->rx_done.entry == NULL)
3631 memset(ss->rx_done.entry, 0, bytes);
3632 bytes = sizeof(*ss->fw_stats);
3633 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3636 if (ss->fw_stats == NULL)
3640 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3641 myri10ge_napi_weight);
3645 myri10ge_free_slices(mgp);
3650 * This function determines the number of slices supported.
3651 * The number slices is the minumum of the number of CPUS,
3652 * the number of MSI-X irqs supported, the number of slices
3653 * supported by the firmware
3655 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3657 struct myri10ge_cmd cmd;
3658 struct pci_dev *pdev = mgp->pdev;
3660 int i, status, ncpus, msix_cap;
3662 mgp->num_slices = 1;
3663 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3664 ncpus = num_online_cpus();
3666 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3667 (myri10ge_max_slices == -1 && ncpus < 2))
3670 /* try to load the slice aware rss firmware */
3671 old_fw = mgp->fw_name;
3672 if (myri10ge_fw_name != NULL) {
3673 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3675 mgp->fw_name = myri10ge_fw_name;
3676 } else if (old_fw == myri10ge_fw_aligned)
3677 mgp->fw_name = myri10ge_fw_rss_aligned;
3679 mgp->fw_name = myri10ge_fw_rss_unaligned;
3680 status = myri10ge_load_firmware(mgp, 0);
3682 dev_info(&pdev->dev, "Rss firmware not found\n");
3686 /* hit the board with a reset to ensure it is alive */
3687 memset(&cmd, 0, sizeof(cmd));
3688 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3690 dev_err(&mgp->pdev->dev, "failed reset\n");
3695 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3697 /* tell it the size of the interrupt queues */
3698 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3699 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3701 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3705 /* ask the maximum number of slices it supports */
3706 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3710 mgp->num_slices = cmd.data0;
3712 /* Only allow multiple slices if MSI-X is usable */
3713 if (!myri10ge_msi) {
3717 /* if the admin did not specify a limit to how many
3718 * slices we should use, cap it automatically to the
3719 * number of CPUs currently online */
3720 if (myri10ge_max_slices == -1)
3721 myri10ge_max_slices = ncpus;
3723 if (mgp->num_slices > myri10ge_max_slices)
3724 mgp->num_slices = myri10ge_max_slices;
3726 /* Now try to allocate as many MSI-X vectors as we have
3727 * slices. We give up on MSI-X if we can only get a single
3730 mgp->msix_vectors = kzalloc(mgp->num_slices *
3731 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3732 if (mgp->msix_vectors == NULL)
3734 for (i = 0; i < mgp->num_slices; i++) {
3735 mgp->msix_vectors[i].entry = i;
3738 while (mgp->num_slices > 1) {
3739 /* make sure it is a power of two */
3740 while (!is_power_of_2(mgp->num_slices))
3742 if (mgp->num_slices == 1)
3744 status = pci_enable_msix(pdev, mgp->msix_vectors,
3747 pci_disable_msix(pdev);
3751 mgp->num_slices = status;
3757 if (mgp->msix_vectors != NULL) {
3758 kfree(mgp->msix_vectors);
3759 mgp->msix_vectors = NULL;
3763 mgp->num_slices = 1;
3764 mgp->fw_name = old_fw;
3765 myri10ge_load_firmware(mgp, 0);
3768 static const struct net_device_ops myri10ge_netdev_ops = {
3769 .ndo_open = myri10ge_open,
3770 .ndo_stop = myri10ge_close,
3771 .ndo_start_xmit = myri10ge_xmit,
3772 .ndo_get_stats = myri10ge_get_stats,
3773 .ndo_validate_addr = eth_validate_addr,
3774 .ndo_change_mtu = myri10ge_change_mtu,
3775 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3776 .ndo_set_mac_address = myri10ge_set_mac_address,
3779 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3781 struct net_device *netdev;
3782 struct myri10ge_priv *mgp;
3783 struct device *dev = &pdev->dev;
3785 int status = -ENXIO;
3787 unsigned hdr_offset, ss_offset;
3788 static int board_number;
3790 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3791 if (netdev == NULL) {
3792 dev_err(dev, "Could not allocate ethernet device\n");
3796 SET_NETDEV_DEV(netdev, &pdev->dev);
3798 mgp = netdev_priv(netdev);
3801 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3802 mgp->pause = myri10ge_flow_control;
3803 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3804 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3805 mgp->board_number = board_number;
3806 init_waitqueue_head(&mgp->down_wq);
3808 if (pci_enable_device(pdev)) {
3809 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3811 goto abort_with_netdev;
3814 /* Find the vendor-specific cap so we can check
3815 * the reboot register later on */
3816 mgp->vendor_specific_offset
3817 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3819 /* Set our max read request to 4KB */
3820 status = pcie_set_readrq(pdev, 4096);
3822 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3824 goto abort_with_enabled;
3827 pci_set_master(pdev);
3829 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3833 "64-bit pci address mask was refused, "
3835 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3838 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3839 goto abort_with_enabled;
3841 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3842 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3843 &mgp->cmd_bus, GFP_KERNEL);
3844 if (mgp->cmd == NULL)
3845 goto abort_with_enabled;
3847 mgp->board_span = pci_resource_len(pdev, 0);
3848 mgp->iomem_base = pci_resource_start(pdev, 0);
3850 mgp->wc_enabled = 0;
3852 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3853 MTRR_TYPE_WRCOMB, 1);
3855 mgp->wc_enabled = 1;
3857 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3858 if (mgp->sram == NULL) {
3859 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3860 mgp->board_span, mgp->iomem_base);
3862 goto abort_with_mtrr;
3865 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3866 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3867 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3868 if (mgp->sram_size > mgp->board_span ||
3869 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3871 "invalid sram_size %dB or board span %ldB\n",
3872 mgp->sram_size, mgp->board_span);
3873 goto abort_with_ioremap;
3875 memcpy_fromio(mgp->eeprom_strings,
3876 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3877 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3878 status = myri10ge_read_mac_addr(mgp);
3880 goto abort_with_ioremap;
3882 for (i = 0; i < ETH_ALEN; i++)
3883 netdev->dev_addr[i] = mgp->mac_addr[i];
3885 myri10ge_select_firmware(mgp);
3887 status = myri10ge_load_firmware(mgp, 1);
3889 dev_err(&pdev->dev, "failed to load firmware\n");
3890 goto abort_with_ioremap;
3892 myri10ge_probe_slices(mgp);
3893 status = myri10ge_alloc_slices(mgp);
3895 dev_err(&pdev->dev, "failed to alloc slice state\n");
3896 goto abort_with_firmware;
3898 netdev->real_num_tx_queues = mgp->num_slices;
3899 status = myri10ge_reset(mgp);
3901 dev_err(&pdev->dev, "failed reset\n");
3902 goto abort_with_slices;
3904 #ifdef CONFIG_MYRI10GE_DCA
3905 myri10ge_setup_dca(mgp);
3907 pci_set_drvdata(pdev, mgp);
3908 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3909 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3910 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3911 myri10ge_initial_mtu = 68;
3913 netdev->netdev_ops = &myri10ge_netdev_ops;
3914 netdev->mtu = myri10ge_initial_mtu;
3915 netdev->base_addr = mgp->iomem_base;
3916 netdev->features = mgp->features;
3919 netdev->features |= NETIF_F_HIGHDMA;
3921 netdev->features |= NETIF_F_LRO;
3923 /* make sure we can get an irq, and that MSI can be
3924 * setup (if available). Also ensure netdev->irq
3925 * is set to correct value if MSI is enabled */
3926 status = myri10ge_request_irq(mgp);
3928 goto abort_with_firmware;
3929 netdev->irq = pdev->irq;
3930 myri10ge_free_irq(mgp);
3932 /* Save configuration space to be restored if the
3933 * nic resets due to a parity error */
3934 pci_save_state(pdev);
3936 /* Setup the watchdog timer */
3937 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3938 (unsigned long)mgp);
3940 spin_lock_init(&mgp->stats_lock);
3941 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3942 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3943 status = register_netdev(netdev);
3945 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3946 goto abort_with_state;
3948 if (mgp->msix_enabled)
3949 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3950 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3951 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3953 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3954 mgp->msi_enabled ? "MSI" : "xPIC",
3955 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3956 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3962 pci_restore_state(pdev);
3965 myri10ge_free_slices(mgp);
3967 abort_with_firmware:
3968 myri10ge_dummy_rdma(mgp, 0);
3971 if (mgp->mac_addr_string != NULL)
3973 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3974 mgp->mac_addr_string, mgp->serial_number);
3980 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3982 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3983 mgp->cmd, mgp->cmd_bus);
3986 pci_disable_device(pdev);
3989 free_netdev(netdev);
3996 * Does what is necessary to shutdown one Myrinet device. Called
3997 * once for each Myrinet card by the kernel when a module is
4000 static void myri10ge_remove(struct pci_dev *pdev)
4002 struct myri10ge_priv *mgp;
4003 struct net_device *netdev;
4005 mgp = pci_get_drvdata(pdev);
4009 flush_scheduled_work();
4011 unregister_netdev(netdev);
4013 #ifdef CONFIG_MYRI10GE_DCA
4014 myri10ge_teardown_dca(mgp);
4016 myri10ge_dummy_rdma(mgp, 0);
4018 /* avoid a memory leak */
4019 pci_restore_state(pdev);
4025 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4027 myri10ge_free_slices(mgp);
4028 if (mgp->msix_vectors != NULL)
4029 kfree(mgp->msix_vectors);
4030 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4031 mgp->cmd, mgp->cmd_bus);
4033 free_netdev(netdev);
4034 pci_disable_device(pdev);
4035 pci_set_drvdata(pdev, NULL);
4038 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
4039 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
4041 static struct pci_device_id myri10ge_pci_tbl[] = {
4042 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4044 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4048 MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4050 static struct pci_driver myri10ge_driver = {
4052 .probe = myri10ge_probe,
4053 .remove = myri10ge_remove,
4054 .id_table = myri10ge_pci_tbl,
4056 .suspend = myri10ge_suspend,
4057 .resume = myri10ge_resume,
4061 #ifdef CONFIG_MYRI10GE_DCA
4063 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4065 int err = driver_for_each_device(&myri10ge_driver.driver,
4067 myri10ge_notify_dca_device);
4074 static struct notifier_block myri10ge_dca_notifier = {
4075 .notifier_call = myri10ge_notify_dca,
4079 #endif /* CONFIG_MYRI10GE_DCA */
4081 static __init int myri10ge_init_module(void)
4083 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4084 MYRI10GE_VERSION_STR);
4086 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4088 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4089 myri10ge_driver.name, myri10ge_rss_hash);
4090 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4092 #ifdef CONFIG_MYRI10GE_DCA
4093 dca_register_notify(&myri10ge_dca_notifier);
4095 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4096 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4098 return pci_register_driver(&myri10ge_driver);
4101 module_init(myri10ge_init_module);
4103 static __exit void myri10ge_cleanup_module(void)
4105 #ifdef CONFIG_MYRI10GE_DCA
4106 dca_unregister_notify(&myri10ge_dca_notifier);
4108 pci_unregister_driver(&myri10ge_driver);
4111 module_exit(myri10ge_cleanup_module);