2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
60 #define MV643XX_ETH_TX_FAST_REFILL
63 * Registers shared between all ports.
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
84 #define UNICAST_PROMISCUOUS_MODE 0x00000001
85 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
91 #define TX_FIFO_EMPTY 0x00000400
92 #define TX_IN_PROGRESS 0x00000080
93 #define PORT_SPEED_MASK 0x00000030
94 #define PORT_SPEED_1000 0x00000010
95 #define PORT_SPEED_100 0x00000020
96 #define PORT_SPEED_10 0x00000000
97 #define FLOW_CONTROL_ENABLED 0x00000008
98 #define FULL_DUPLEX 0x00000004
99 #define LINK_UP 0x00000002
100 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
101 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
103 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
104 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
105 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
106 #define INT_TX_END_0 0x00080000
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x0007fbfc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
111 #define INT_EXT_LINK 0x00100000
112 #define INT_EXT_PHY 0x00010000
113 #define INT_EXT_TX_ERROR_0 0x00000100
114 #define INT_EXT_TX_0 0x00000001
115 #define INT_EXT_TX 0x0000ffff
116 #define INT_MASK(p) (0x0468 + ((p) << 10))
117 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
118 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
119 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
120 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
121 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
122 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
123 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
124 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
125 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
126 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
127 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
128 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
129 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
130 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
131 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
132 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
136 * SDMA configuration register.
138 #define RX_BURST_SIZE_16_64BIT (4 << 1)
139 #define BLM_RX_NO_SWAP (1 << 4)
140 #define BLM_TX_NO_SWAP (1 << 5)
141 #define TX_BURST_SIZE_16_64BIT (4 << 22)
143 #if defined(__BIG_ENDIAN)
144 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
145 RX_BURST_SIZE_16_64BIT | \
146 TX_BURST_SIZE_16_64BIT
147 #elif defined(__LITTLE_ENDIAN)
148 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
149 RX_BURST_SIZE_16_64BIT | \
152 TX_BURST_SIZE_16_64BIT
154 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
159 * Port serial control register.
161 #define SET_MII_SPEED_TO_100 (1 << 24)
162 #define SET_GMII_SPEED_TO_1000 (1 << 23)
163 #define SET_FULL_DUPLEX_MODE (1 << 21)
164 #define MAX_RX_PACKET_9700BYTE (5 << 17)
165 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
166 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
167 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
168 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
169 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
170 #define FORCE_LINK_PASS (1 << 1)
171 #define SERIAL_PORT_ENABLE (1 << 0)
173 #define DEFAULT_RX_QUEUE_SIZE 400
174 #define DEFAULT_TX_QUEUE_SIZE 800
180 #if defined(__BIG_ENDIAN)
182 u16 byte_cnt; /* Descriptor buffer byte count */
183 u16 buf_size; /* Buffer size */
184 u32 cmd_sts; /* Descriptor command status */
185 u32 next_desc_ptr; /* Next descriptor pointer */
186 u32 buf_ptr; /* Descriptor buffer pointer */
190 u16 byte_cnt; /* buffer byte count */
191 u16 l4i_chk; /* CPU provided TCP checksum */
192 u32 cmd_sts; /* Command/status field */
193 u32 next_desc_ptr; /* Pointer to next descriptor */
194 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196 #elif defined(__LITTLE_ENDIAN)
198 u32 cmd_sts; /* Descriptor command status */
199 u16 buf_size; /* Buffer size */
200 u16 byte_cnt; /* Descriptor buffer byte count */
201 u32 buf_ptr; /* Descriptor buffer pointer */
202 u32 next_desc_ptr; /* Next descriptor pointer */
206 u32 cmd_sts; /* Command/status field */
207 u16 l4i_chk; /* CPU provided TCP checksum */
208 u16 byte_cnt; /* buffer byte count */
209 u32 buf_ptr; /* pointer to buffer for this descriptor*/
210 u32 next_desc_ptr; /* Pointer to next descriptor */
213 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
216 /* RX & TX descriptor command */
217 #define BUFFER_OWNED_BY_DMA 0x80000000
219 /* RX & TX descriptor status */
220 #define ERROR_SUMMARY 0x00000001
222 /* RX descriptor status */
223 #define LAYER_4_CHECKSUM_OK 0x40000000
224 #define RX_ENABLE_INTERRUPT 0x20000000
225 #define RX_FIRST_DESC 0x08000000
226 #define RX_LAST_DESC 0x04000000
228 /* TX descriptor command */
229 #define TX_ENABLE_INTERRUPT 0x00800000
230 #define GEN_CRC 0x00400000
231 #define TX_FIRST_DESC 0x00200000
232 #define TX_LAST_DESC 0x00100000
233 #define ZERO_PADDING 0x00080000
234 #define GEN_IP_V4_CHECKSUM 0x00040000
235 #define GEN_TCP_UDP_CHECKSUM 0x00020000
236 #define UDP_FRAME 0x00010000
237 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
238 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
240 #define TX_IHL_SHIFT 11
243 /* global *******************************************************************/
244 struct mv643xx_eth_shared_private {
246 * Ethernet controller base address.
251 * Points at the right SMI instance to use.
253 struct mv643xx_eth_shared_private *smi;
256 * Protects access to SMI_REG, which is shared between ports.
258 struct mutex phy_lock;
261 * If we have access to the error interrupt pin (which is
262 * somewhat misnamed as it not only reflects internal errors
263 * but also reflects SMI completion), use that to wait for
264 * SMI access completion instead of polling the SMI busy bit.
267 wait_queue_head_t smi_busy_wait;
270 * Per-port MBUS window access register value.
275 * Hardware-specific parameters.
278 int extended_rx_coal_limit;
279 int tx_bw_control_moved;
283 /* per-port *****************************************************************/
284 struct mib_counters {
285 u64 good_octets_received;
286 u32 bad_octets_received;
287 u32 internal_mac_transmit_err;
288 u32 good_frames_received;
289 u32 bad_frames_received;
290 u32 broadcast_frames_received;
291 u32 multicast_frames_received;
292 u32 frames_64_octets;
293 u32 frames_65_to_127_octets;
294 u32 frames_128_to_255_octets;
295 u32 frames_256_to_511_octets;
296 u32 frames_512_to_1023_octets;
297 u32 frames_1024_to_max_octets;
298 u64 good_octets_sent;
299 u32 good_frames_sent;
300 u32 excessive_collision;
301 u32 multicast_frames_sent;
302 u32 broadcast_frames_sent;
303 u32 unrec_mac_control_received;
305 u32 good_fc_received;
307 u32 undersize_received;
308 u32 fragments_received;
309 u32 oversize_received;
311 u32 mac_receive_error;
326 struct rx_desc *rx_desc_area;
327 dma_addr_t rx_desc_dma;
328 int rx_desc_area_size;
329 struct sk_buff **rx_skb;
341 struct tx_desc *tx_desc_area;
342 dma_addr_t tx_desc_dma;
343 int tx_desc_area_size;
344 struct sk_buff **tx_skb;
347 struct mv643xx_eth_private {
348 struct mv643xx_eth_shared_private *shared;
351 struct net_device *dev;
357 struct mib_counters mib_counters;
358 struct work_struct tx_timeout_task;
359 struct mii_if_info mii;
364 int default_rx_ring_size;
365 unsigned long rx_desc_sram_addr;
366 int rx_desc_sram_size;
368 struct napi_struct napi;
369 struct timer_list rx_oom;
370 struct rx_queue rxq[8];
375 int default_tx_ring_size;
376 unsigned long tx_desc_sram_addr;
377 int tx_desc_sram_size;
379 struct tx_queue txq[8];
380 #ifdef MV643XX_ETH_TX_FAST_REFILL
381 int tx_clean_threshold;
386 /* port register accessors **************************************************/
387 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
389 return readl(mp->shared->base + offset);
392 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
394 writel(data, mp->shared->base + offset);
398 /* rxq/txq helper functions *************************************************/
399 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
401 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
404 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
406 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
409 static void rxq_enable(struct rx_queue *rxq)
411 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
412 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
415 static void rxq_disable(struct rx_queue *rxq)
417 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
418 u8 mask = 1 << rxq->index;
420 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
421 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
425 static void txq_reset_hw_ptr(struct tx_queue *txq)
427 struct mv643xx_eth_private *mp = txq_to_mp(txq);
428 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
431 addr = (u32)txq->tx_desc_dma;
432 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
436 static void txq_enable(struct tx_queue *txq)
438 struct mv643xx_eth_private *mp = txq_to_mp(txq);
439 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
442 static void txq_disable(struct tx_queue *txq)
444 struct mv643xx_eth_private *mp = txq_to_mp(txq);
445 u8 mask = 1 << txq->index;
447 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
448 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
452 static void __txq_maybe_wake(struct tx_queue *txq)
454 struct mv643xx_eth_private *mp = txq_to_mp(txq);
457 * netif_{stop,wake}_queue() flow control only applies to
460 BUG_ON(txq->index != 0);
462 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
463 netif_wake_queue(mp->dev);
467 /* rx ***********************************************************************/
468 static void txq_reclaim(struct tx_queue *txq, int force);
470 static int rxq_refill(struct rx_queue *rxq, int budget, int *oom)
476 * Reserve 2+14 bytes for an ethernet header (the hardware
477 * automatically prepends 2 bytes of dummy data to each
478 * received packet), 16 bytes for up to four VLAN tags, and
479 * 4 bytes for the trailing FCS -- 36 bytes total.
481 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
484 * Make sure that the skb size is a multiple of 8 bytes, as
485 * the lower three bits of the receive descriptor's buffer
486 * size field are ignored by the hardware.
488 skb_size = (skb_size + 7) & ~7;
491 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
496 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
502 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
504 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
507 rxq->rx_desc_count++;
509 rx = rxq->rx_used_desc++;
510 if (rxq->rx_used_desc == rxq->rx_ring_size)
511 rxq->rx_used_desc = 0;
513 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
514 skb_size, DMA_FROM_DEVICE);
515 rxq->rx_desc_area[rx].buf_size = skb_size;
516 rxq->rx_skb[rx] = skb;
518 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
523 * The hardware automatically prepends 2 bytes of
524 * dummy data to each received packet, so that the
525 * IP header ends up 16-byte aligned.
533 static int rxq_process(struct rx_queue *rxq, int budget)
535 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
536 struct net_device_stats *stats = &mp->dev->stats;
540 while (rx < budget && rxq->rx_desc_count) {
541 struct rx_desc *rx_desc;
542 unsigned int cmd_sts;
545 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
547 cmd_sts = rx_desc->cmd_sts;
548 if (cmd_sts & BUFFER_OWNED_BY_DMA)
552 skb = rxq->rx_skb[rxq->rx_curr_desc];
553 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
556 if (rxq->rx_curr_desc == rxq->rx_ring_size)
557 rxq->rx_curr_desc = 0;
559 dma_unmap_single(NULL, rx_desc->buf_ptr,
560 rx_desc->buf_size, DMA_FROM_DEVICE);
561 rxq->rx_desc_count--;
567 * Note that the descriptor byte count includes 2 dummy
568 * bytes automatically inserted by the hardware at the
569 * start of the packet (which we don't count), and a 4
570 * byte CRC at the end of the packet (which we do count).
573 stats->rx_bytes += rx_desc->byte_cnt - 2;
576 * In case we received a packet without first / last bits
577 * on, or the error summary bit is set, the packet needs
580 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
581 (RX_FIRST_DESC | RX_LAST_DESC))
582 || (cmd_sts & ERROR_SUMMARY)) {
585 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
586 (RX_FIRST_DESC | RX_LAST_DESC)) {
588 dev_printk(KERN_ERR, &mp->dev->dev,
589 "received packet spanning "
590 "multiple descriptors\n");
593 if (cmd_sts & ERROR_SUMMARY)
599 * The -4 is for the CRC in the trailer of the
602 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
604 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
605 skb->ip_summed = CHECKSUM_UNNECESSARY;
607 (cmd_sts & 0x0007fff8) >> 3);
609 skb->protocol = eth_type_trans(skb, mp->dev);
610 netif_receive_skb(skb);
613 mp->dev->last_rx = jiffies;
619 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
621 struct mv643xx_eth_private *mp;
626 mp = container_of(napi, struct mv643xx_eth_private, napi);
628 #ifdef MV643XX_ETH_TX_FAST_REFILL
629 if (++mp->tx_clean_threshold > 5) {
630 mp->tx_clean_threshold = 0;
631 for (i = 0; i < mp->txq_count; i++)
632 txq_reclaim(mp->txq + i, 0);
634 if (netif_carrier_ok(mp->dev)) {
635 spin_lock_irq(&mp->lock);
636 __txq_maybe_wake(mp->txq);
637 spin_unlock_irq(&mp->lock);
644 for (i = mp->rxq_count - 1; work_done < budget && i >= 0; i--) {
645 struct rx_queue *rxq = mp->rxq + i;
647 work_done += rxq_process(rxq, budget - work_done);
648 work_done += rxq_refill(rxq, budget - work_done, &oom);
651 if (work_done < budget) {
653 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
654 netif_rx_complete(mp->dev, napi);
655 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
661 static inline void oom_timer_wrapper(unsigned long data)
663 struct mv643xx_eth_private *mp = (void *)data;
665 napi_schedule(&mp->napi);
669 /* tx ***********************************************************************/
670 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
674 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
675 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
676 if (fragp->size <= 8 && fragp->page_offset & 7)
683 static int txq_alloc_desc_index(struct tx_queue *txq)
687 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
689 tx_desc_curr = txq->tx_curr_desc++;
690 if (txq->tx_curr_desc == txq->tx_ring_size)
691 txq->tx_curr_desc = 0;
693 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
698 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
700 int nr_frags = skb_shinfo(skb)->nr_frags;
703 for (frag = 0; frag < nr_frags; frag++) {
704 skb_frag_t *this_frag;
706 struct tx_desc *desc;
708 this_frag = &skb_shinfo(skb)->frags[frag];
709 tx_index = txq_alloc_desc_index(txq);
710 desc = &txq->tx_desc_area[tx_index];
713 * The last fragment will generate an interrupt
714 * which will free the skb on TX completion.
716 if (frag == nr_frags - 1) {
717 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
718 ZERO_PADDING | TX_LAST_DESC |
720 txq->tx_skb[tx_index] = skb;
722 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
723 txq->tx_skb[tx_index] = NULL;
727 desc->byte_cnt = this_frag->size;
728 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
729 this_frag->page_offset,
735 static inline __be16 sum16_as_be(__sum16 sum)
737 return (__force __be16)sum;
740 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
742 struct mv643xx_eth_private *mp = txq_to_mp(txq);
743 int nr_frags = skb_shinfo(skb)->nr_frags;
745 struct tx_desc *desc;
749 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
751 tx_index = txq_alloc_desc_index(txq);
752 desc = &txq->tx_desc_area[tx_index];
755 txq_submit_frag_skb(txq, skb);
757 length = skb_headlen(skb);
758 txq->tx_skb[tx_index] = NULL;
760 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
762 txq->tx_skb[tx_index] = skb;
765 desc->byte_cnt = length;
766 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
768 if (skb->ip_summed == CHECKSUM_PARTIAL) {
771 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
772 skb->protocol != htons(ETH_P_8021Q));
774 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
776 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
778 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
779 switch (mac_hdr_len - ETH_HLEN) {
783 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
786 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
789 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
790 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
794 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
795 "mac header length is %d?!\n", mac_hdr_len);
799 switch (ip_hdr(skb)->protocol) {
801 cmd_sts |= UDP_FRAME;
802 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
805 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
811 /* Errata BTS #50, IHL must be 5 if no HW checksum */
812 cmd_sts |= 5 << TX_IHL_SHIFT;
816 /* ensure all other descriptors are written before first cmd_sts */
818 desc->cmd_sts = cmd_sts;
820 /* clear TX_END interrupt status */
821 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
822 rdl(mp, INT_CAUSE(mp->port_num));
824 /* ensure all descriptors are written before poking hardware */
828 txq->tx_desc_count += nr_frags + 1;
831 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
833 struct mv643xx_eth_private *mp = netdev_priv(dev);
834 struct net_device_stats *stats = &dev->stats;
835 struct tx_queue *txq;
838 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
840 dev_printk(KERN_DEBUG, &dev->dev,
841 "failed to linearize skb with tiny "
842 "unaligned fragment\n");
843 return NETDEV_TX_BUSY;
846 spin_lock_irqsave(&mp->lock, flags);
850 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
851 spin_unlock_irqrestore(&mp->lock, flags);
852 if (txq->index == 0 && net_ratelimit())
853 dev_printk(KERN_ERR, &dev->dev,
854 "primary tx queue full?!\n");
859 txq_submit_skb(txq, skb);
860 stats->tx_bytes += skb->len;
862 dev->trans_start = jiffies;
864 if (txq->index == 0) {
867 entries_left = txq->tx_ring_size - txq->tx_desc_count;
868 if (entries_left < MAX_SKB_FRAGS + 1)
869 netif_stop_queue(dev);
872 spin_unlock_irqrestore(&mp->lock, flags);
878 /* tx rate control **********************************************************/
880 * Set total maximum TX rate (shared by all TX queues for this port)
881 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
883 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
889 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
890 if (token_rate > 1023)
893 mtu = (mp->dev->mtu + 255) >> 8;
897 bucket_size = (burst + 255) >> 8;
898 if (bucket_size > 65535)
901 if (mp->shared->tx_bw_control_moved) {
902 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
903 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
904 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
906 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
907 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
908 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
912 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
914 struct mv643xx_eth_private *mp = txq_to_mp(txq);
918 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
919 if (token_rate > 1023)
922 bucket_size = (burst + 255) >> 8;
923 if (bucket_size > 65535)
926 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
927 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
928 (bucket_size << 10) | token_rate);
931 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
933 struct mv643xx_eth_private *mp = txq_to_mp(txq);
938 * Turn on fixed priority mode.
940 if (mp->shared->tx_bw_control_moved)
941 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
943 off = TXQ_FIX_PRIO_CONF(mp->port_num);
946 val |= 1 << txq->index;
950 static void txq_set_wrr(struct tx_queue *txq, int weight)
952 struct mv643xx_eth_private *mp = txq_to_mp(txq);
957 * Turn off fixed priority mode.
959 if (mp->shared->tx_bw_control_moved)
960 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
962 off = TXQ_FIX_PRIO_CONF(mp->port_num);
965 val &= ~(1 << txq->index);
969 * Configure WRR weight for this queue.
971 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
974 val = (val & ~0xff) | (weight & 0xff);
979 /* mii management interface *************************************************/
980 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
982 struct mv643xx_eth_shared_private *msp = dev_id;
984 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
985 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
986 wake_up(&msp->smi_busy_wait);
993 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
995 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
998 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1000 if (msp->err_interrupt == NO_IRQ) {
1003 for (i = 0; !smi_is_done(msp); i++) {
1012 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1013 msecs_to_jiffies(100)))
1019 static int smi_reg_read(struct mv643xx_eth_private *mp,
1020 unsigned int addr, unsigned int reg)
1022 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1023 void __iomem *smi_reg = msp->base + SMI_REG;
1026 mutex_lock(&msp->phy_lock);
1028 if (smi_wait_ready(msp)) {
1029 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1034 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1036 if (smi_wait_ready(msp)) {
1037 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1042 ret = readl(smi_reg);
1043 if (!(ret & SMI_READ_VALID)) {
1044 printk("%s: SMI bus read not valid\n", mp->dev->name);
1052 mutex_unlock(&msp->phy_lock);
1057 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1058 unsigned int reg, unsigned int value)
1060 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1061 void __iomem *smi_reg = msp->base + SMI_REG;
1063 mutex_lock(&msp->phy_lock);
1065 if (smi_wait_ready(msp)) {
1066 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1067 mutex_unlock(&msp->phy_lock);
1071 writel(SMI_OPCODE_WRITE | (reg << 21) |
1072 (addr << 16) | (value & 0xffff), smi_reg);
1074 mutex_unlock(&msp->phy_lock);
1080 /* mib counters *************************************************************/
1081 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1083 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1086 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1090 for (i = 0; i < 0x80; i += 4)
1094 static void mib_counters_update(struct mv643xx_eth_private *mp)
1096 struct mib_counters *p = &mp->mib_counters;
1098 p->good_octets_received += mib_read(mp, 0x00);
1099 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1100 p->bad_octets_received += mib_read(mp, 0x08);
1101 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1102 p->good_frames_received += mib_read(mp, 0x10);
1103 p->bad_frames_received += mib_read(mp, 0x14);
1104 p->broadcast_frames_received += mib_read(mp, 0x18);
1105 p->multicast_frames_received += mib_read(mp, 0x1c);
1106 p->frames_64_octets += mib_read(mp, 0x20);
1107 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1108 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1109 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1110 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1111 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1112 p->good_octets_sent += mib_read(mp, 0x38);
1113 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1114 p->good_frames_sent += mib_read(mp, 0x40);
1115 p->excessive_collision += mib_read(mp, 0x44);
1116 p->multicast_frames_sent += mib_read(mp, 0x48);
1117 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1118 p->unrec_mac_control_received += mib_read(mp, 0x50);
1119 p->fc_sent += mib_read(mp, 0x54);
1120 p->good_fc_received += mib_read(mp, 0x58);
1121 p->bad_fc_received += mib_read(mp, 0x5c);
1122 p->undersize_received += mib_read(mp, 0x60);
1123 p->fragments_received += mib_read(mp, 0x64);
1124 p->oversize_received += mib_read(mp, 0x68);
1125 p->jabber_received += mib_read(mp, 0x6c);
1126 p->mac_receive_error += mib_read(mp, 0x70);
1127 p->bad_crc_event += mib_read(mp, 0x74);
1128 p->collision += mib_read(mp, 0x78);
1129 p->late_collision += mib_read(mp, 0x7c);
1133 /* ethtool ******************************************************************/
1134 struct mv643xx_eth_stats {
1135 char stat_string[ETH_GSTRING_LEN];
1142 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1143 offsetof(struct net_device, stats.m), -1 }
1145 #define MIBSTAT(m) \
1146 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1147 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1149 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1158 MIBSTAT(good_octets_received),
1159 MIBSTAT(bad_octets_received),
1160 MIBSTAT(internal_mac_transmit_err),
1161 MIBSTAT(good_frames_received),
1162 MIBSTAT(bad_frames_received),
1163 MIBSTAT(broadcast_frames_received),
1164 MIBSTAT(multicast_frames_received),
1165 MIBSTAT(frames_64_octets),
1166 MIBSTAT(frames_65_to_127_octets),
1167 MIBSTAT(frames_128_to_255_octets),
1168 MIBSTAT(frames_256_to_511_octets),
1169 MIBSTAT(frames_512_to_1023_octets),
1170 MIBSTAT(frames_1024_to_max_octets),
1171 MIBSTAT(good_octets_sent),
1172 MIBSTAT(good_frames_sent),
1173 MIBSTAT(excessive_collision),
1174 MIBSTAT(multicast_frames_sent),
1175 MIBSTAT(broadcast_frames_sent),
1176 MIBSTAT(unrec_mac_control_received),
1178 MIBSTAT(good_fc_received),
1179 MIBSTAT(bad_fc_received),
1180 MIBSTAT(undersize_received),
1181 MIBSTAT(fragments_received),
1182 MIBSTAT(oversize_received),
1183 MIBSTAT(jabber_received),
1184 MIBSTAT(mac_receive_error),
1185 MIBSTAT(bad_crc_event),
1187 MIBSTAT(late_collision),
1190 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1192 struct mv643xx_eth_private *mp = netdev_priv(dev);
1195 err = mii_ethtool_gset(&mp->mii, cmd);
1198 * The MAC does not support 1000baseT_Half.
1200 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1201 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1206 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1208 struct mv643xx_eth_private *mp = netdev_priv(dev);
1211 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1213 cmd->supported = SUPPORTED_MII;
1214 cmd->advertising = ADVERTISED_MII;
1215 switch (port_status & PORT_SPEED_MASK) {
1217 cmd->speed = SPEED_10;
1219 case PORT_SPEED_100:
1220 cmd->speed = SPEED_100;
1222 case PORT_SPEED_1000:
1223 cmd->speed = SPEED_1000;
1229 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1230 cmd->port = PORT_MII;
1231 cmd->phy_address = 0;
1232 cmd->transceiver = XCVR_INTERNAL;
1233 cmd->autoneg = AUTONEG_DISABLE;
1240 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1242 struct mv643xx_eth_private *mp = netdev_priv(dev);
1245 * The MAC does not support 1000baseT_Half.
1247 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1249 return mii_ethtool_sset(&mp->mii, cmd);
1252 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1257 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1258 struct ethtool_drvinfo *drvinfo)
1260 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1261 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1262 strncpy(drvinfo->fw_version, "N/A", 32);
1263 strncpy(drvinfo->bus_info, "platform", 32);
1264 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1267 static int mv643xx_eth_nway_reset(struct net_device *dev)
1269 struct mv643xx_eth_private *mp = netdev_priv(dev);
1271 return mii_nway_restart(&mp->mii);
1274 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1279 static u32 mv643xx_eth_get_link(struct net_device *dev)
1281 struct mv643xx_eth_private *mp = netdev_priv(dev);
1283 return mii_link_ok(&mp->mii);
1286 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1291 static void mv643xx_eth_get_strings(struct net_device *dev,
1292 uint32_t stringset, uint8_t *data)
1296 if (stringset == ETH_SS_STATS) {
1297 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1298 memcpy(data + i * ETH_GSTRING_LEN,
1299 mv643xx_eth_stats[i].stat_string,
1305 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1306 struct ethtool_stats *stats,
1309 struct mv643xx_eth_private *mp = netdev_priv(dev);
1312 mib_counters_update(mp);
1314 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1315 const struct mv643xx_eth_stats *stat;
1318 stat = mv643xx_eth_stats + i;
1320 if (stat->netdev_off >= 0)
1321 p = ((void *)mp->dev) + stat->netdev_off;
1323 p = ((void *)mp) + stat->mp_off;
1325 data[i] = (stat->sizeof_stat == 8) ?
1326 *(uint64_t *)p : *(uint32_t *)p;
1330 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1332 if (sset == ETH_SS_STATS)
1333 return ARRAY_SIZE(mv643xx_eth_stats);
1338 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1339 .get_settings = mv643xx_eth_get_settings,
1340 .set_settings = mv643xx_eth_set_settings,
1341 .get_drvinfo = mv643xx_eth_get_drvinfo,
1342 .nway_reset = mv643xx_eth_nway_reset,
1343 .get_link = mv643xx_eth_get_link,
1344 .set_sg = ethtool_op_set_sg,
1345 .get_strings = mv643xx_eth_get_strings,
1346 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1347 .get_sset_count = mv643xx_eth_get_sset_count,
1350 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1351 .get_settings = mv643xx_eth_get_settings_phyless,
1352 .set_settings = mv643xx_eth_set_settings_phyless,
1353 .get_drvinfo = mv643xx_eth_get_drvinfo,
1354 .nway_reset = mv643xx_eth_nway_reset_phyless,
1355 .get_link = mv643xx_eth_get_link_phyless,
1356 .set_sg = ethtool_op_set_sg,
1357 .get_strings = mv643xx_eth_get_strings,
1358 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1359 .get_sset_count = mv643xx_eth_get_sset_count,
1363 /* address handling *********************************************************/
1364 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1369 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1370 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1372 addr[0] = (mac_h >> 24) & 0xff;
1373 addr[1] = (mac_h >> 16) & 0xff;
1374 addr[2] = (mac_h >> 8) & 0xff;
1375 addr[3] = mac_h & 0xff;
1376 addr[4] = (mac_l >> 8) & 0xff;
1377 addr[5] = mac_l & 0xff;
1380 static void init_mac_tables(struct mv643xx_eth_private *mp)
1384 for (i = 0; i < 0x100; i += 4) {
1385 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1386 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1389 for (i = 0; i < 0x10; i += 4)
1390 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1393 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1394 int table, unsigned char entry)
1396 unsigned int table_reg;
1398 /* Set "accepts frame bit" at specified table entry */
1399 table_reg = rdl(mp, table + (entry & 0xfc));
1400 table_reg |= 0x01 << (8 * (entry & 3));
1401 wrl(mp, table + (entry & 0xfc), table_reg);
1404 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1410 mac_l = (addr[4] << 8) | addr[5];
1411 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1413 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1414 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1416 table = UNICAST_TABLE(mp->port_num);
1417 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1420 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1422 struct mv643xx_eth_private *mp = netdev_priv(dev);
1424 /* +2 is for the offset of the HW addr type */
1425 memcpy(dev->dev_addr, addr + 2, 6);
1427 init_mac_tables(mp);
1428 uc_addr_set(mp, dev->dev_addr);
1433 static int addr_crc(unsigned char *addr)
1438 for (i = 0; i < 6; i++) {
1441 crc = (crc ^ addr[i]) << 8;
1442 for (j = 7; j >= 0; j--) {
1443 if (crc & (0x100 << j))
1451 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1453 struct mv643xx_eth_private *mp = netdev_priv(dev);
1455 struct dev_addr_list *addr;
1458 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1459 if (dev->flags & IFF_PROMISC)
1460 port_config |= UNICAST_PROMISCUOUS_MODE;
1462 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1463 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1465 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1466 int port_num = mp->port_num;
1467 u32 accept = 0x01010101;
1469 for (i = 0; i < 0x100; i += 4) {
1470 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1471 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1476 for (i = 0; i < 0x100; i += 4) {
1477 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1478 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1481 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1482 u8 *a = addr->da_addr;
1485 if (addr->da_addrlen != 6)
1488 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1489 table = SPECIAL_MCAST_TABLE(mp->port_num);
1490 set_filter_table_entry(mp, table, a[5]);
1492 int crc = addr_crc(a);
1494 table = OTHER_MCAST_TABLE(mp->port_num);
1495 set_filter_table_entry(mp, table, crc);
1501 /* rx/tx queue initialisation ***********************************************/
1502 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1504 struct rx_queue *rxq = mp->rxq + index;
1505 struct rx_desc *rx_desc;
1511 rxq->rx_ring_size = mp->default_rx_ring_size;
1513 rxq->rx_desc_count = 0;
1514 rxq->rx_curr_desc = 0;
1515 rxq->rx_used_desc = 0;
1517 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1519 if (index == 0 && size <= mp->rx_desc_sram_size) {
1520 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1521 mp->rx_desc_sram_size);
1522 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1524 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1529 if (rxq->rx_desc_area == NULL) {
1530 dev_printk(KERN_ERR, &mp->dev->dev,
1531 "can't allocate rx ring (%d bytes)\n", size);
1534 memset(rxq->rx_desc_area, 0, size);
1536 rxq->rx_desc_area_size = size;
1537 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1539 if (rxq->rx_skb == NULL) {
1540 dev_printk(KERN_ERR, &mp->dev->dev,
1541 "can't allocate rx skb ring\n");
1545 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1546 for (i = 0; i < rxq->rx_ring_size; i++) {
1550 if (nexti == rxq->rx_ring_size)
1553 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1554 nexti * sizeof(struct rx_desc);
1561 if (index == 0 && size <= mp->rx_desc_sram_size)
1562 iounmap(rxq->rx_desc_area);
1564 dma_free_coherent(NULL, size,
1572 static void rxq_deinit(struct rx_queue *rxq)
1574 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1579 for (i = 0; i < rxq->rx_ring_size; i++) {
1580 if (rxq->rx_skb[i]) {
1581 dev_kfree_skb(rxq->rx_skb[i]);
1582 rxq->rx_desc_count--;
1586 if (rxq->rx_desc_count) {
1587 dev_printk(KERN_ERR, &mp->dev->dev,
1588 "error freeing rx ring -- %d skbs stuck\n",
1589 rxq->rx_desc_count);
1592 if (rxq->index == 0 &&
1593 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1594 iounmap(rxq->rx_desc_area);
1596 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1597 rxq->rx_desc_area, rxq->rx_desc_dma);
1602 static int txq_init(struct mv643xx_eth_private *mp, int index)
1604 struct tx_queue *txq = mp->txq + index;
1605 struct tx_desc *tx_desc;
1611 txq->tx_ring_size = mp->default_tx_ring_size;
1613 txq->tx_desc_count = 0;
1614 txq->tx_curr_desc = 0;
1615 txq->tx_used_desc = 0;
1617 size = txq->tx_ring_size * sizeof(struct tx_desc);
1619 if (index == 0 && size <= mp->tx_desc_sram_size) {
1620 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1621 mp->tx_desc_sram_size);
1622 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1624 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1629 if (txq->tx_desc_area == NULL) {
1630 dev_printk(KERN_ERR, &mp->dev->dev,
1631 "can't allocate tx ring (%d bytes)\n", size);
1634 memset(txq->tx_desc_area, 0, size);
1636 txq->tx_desc_area_size = size;
1637 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1639 if (txq->tx_skb == NULL) {
1640 dev_printk(KERN_ERR, &mp->dev->dev,
1641 "can't allocate tx skb ring\n");
1645 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1646 for (i = 0; i < txq->tx_ring_size; i++) {
1647 struct tx_desc *txd = tx_desc + i;
1651 if (nexti == txq->tx_ring_size)
1655 txd->next_desc_ptr = txq->tx_desc_dma +
1656 nexti * sizeof(struct tx_desc);
1663 if (index == 0 && size <= mp->tx_desc_sram_size)
1664 iounmap(txq->tx_desc_area);
1666 dma_free_coherent(NULL, size,
1674 static void txq_reclaim(struct tx_queue *txq, int force)
1676 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1677 unsigned long flags;
1679 spin_lock_irqsave(&mp->lock, flags);
1680 while (txq->tx_desc_count > 0) {
1682 struct tx_desc *desc;
1684 struct sk_buff *skb;
1688 tx_index = txq->tx_used_desc;
1689 desc = &txq->tx_desc_area[tx_index];
1690 cmd_sts = desc->cmd_sts;
1692 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1695 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1698 txq->tx_used_desc = tx_index + 1;
1699 if (txq->tx_used_desc == txq->tx_ring_size)
1700 txq->tx_used_desc = 0;
1701 txq->tx_desc_count--;
1703 addr = desc->buf_ptr;
1704 count = desc->byte_cnt;
1705 skb = txq->tx_skb[tx_index];
1706 txq->tx_skb[tx_index] = NULL;
1708 if (cmd_sts & ERROR_SUMMARY) {
1709 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1710 mp->dev->stats.tx_errors++;
1714 * Drop mp->lock while we free the skb.
1716 spin_unlock_irqrestore(&mp->lock, flags);
1718 if (cmd_sts & TX_FIRST_DESC)
1719 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1721 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1724 dev_kfree_skb_irq(skb);
1726 spin_lock_irqsave(&mp->lock, flags);
1728 spin_unlock_irqrestore(&mp->lock, flags);
1731 static void txq_deinit(struct tx_queue *txq)
1733 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1736 txq_reclaim(txq, 1);
1738 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1740 if (txq->index == 0 &&
1741 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1742 iounmap(txq->tx_desc_area);
1744 dma_free_coherent(NULL, txq->tx_desc_area_size,
1745 txq->tx_desc_area, txq->tx_desc_dma);
1751 /* netdev ops and related ***************************************************/
1752 static void handle_link_event(struct mv643xx_eth_private *mp)
1754 struct net_device *dev = mp->dev;
1760 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1761 if (!(port_status & LINK_UP)) {
1762 if (netif_carrier_ok(dev)) {
1765 printk(KERN_INFO "%s: link down\n", dev->name);
1767 netif_carrier_off(dev);
1768 netif_stop_queue(dev);
1770 for (i = 0; i < mp->txq_count; i++) {
1771 struct tx_queue *txq = mp->txq + i;
1773 txq_reclaim(txq, 1);
1774 txq_reset_hw_ptr(txq);
1780 switch (port_status & PORT_SPEED_MASK) {
1784 case PORT_SPEED_100:
1787 case PORT_SPEED_1000:
1794 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1795 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1797 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1798 "flow control %sabled\n", dev->name,
1799 speed, duplex ? "full" : "half",
1802 if (!netif_carrier_ok(dev)) {
1803 netif_carrier_on(dev);
1804 netif_wake_queue(dev);
1808 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1810 struct net_device *dev = (struct net_device *)dev_id;
1811 struct mv643xx_eth_private *mp = netdev_priv(dev);
1815 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1816 (INT_TX_END | INT_RX | INT_EXT);
1821 if (int_cause & INT_EXT) {
1822 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1823 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1824 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1827 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1828 handle_link_event(mp);
1831 * RxBuffer or RxError set for any of the 8 queues?
1833 if (int_cause & INT_RX) {
1834 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1835 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1836 rdl(mp, INT_MASK(mp->port_num));
1838 napi_schedule(&mp->napi);
1842 * TxBuffer or TxError set for any of the 8 queues?
1844 if (int_cause_ext & INT_EXT_TX) {
1847 for (i = 0; i < mp->txq_count; i++)
1848 txq_reclaim(mp->txq + i, 0);
1851 * Enough space again in the primary TX queue for a
1854 if (netif_carrier_ok(dev)) {
1855 spin_lock(&mp->lock);
1856 __txq_maybe_wake(mp->txq);
1857 spin_unlock(&mp->lock);
1862 * Any TxEnd interrupts?
1864 if (int_cause & INT_TX_END) {
1867 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1869 spin_lock(&mp->lock);
1870 for (i = 0; i < 8; i++) {
1871 struct tx_queue *txq = mp->txq + i;
1875 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1879 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1880 expected_ptr = (u32)txq->tx_desc_dma +
1881 txq->tx_curr_desc * sizeof(struct tx_desc);
1883 if (hw_desc_ptr != expected_ptr)
1886 spin_unlock(&mp->lock);
1892 static void phy_reset(struct mv643xx_eth_private *mp)
1896 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1901 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1905 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1906 } while (data >= 0 && data & BMCR_RESET);
1909 static void port_start(struct mv643xx_eth_private *mp)
1915 * Perform PHY reset, if there is a PHY.
1917 if (mp->phy_addr != -1) {
1918 struct ethtool_cmd cmd;
1920 mv643xx_eth_get_settings(mp->dev, &cmd);
1922 mv643xx_eth_set_settings(mp->dev, &cmd);
1926 * Configure basic link parameters.
1928 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1930 pscr |= SERIAL_PORT_ENABLE;
1931 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1933 pscr |= DO_NOT_FORCE_LINK_FAIL;
1934 if (mp->phy_addr == -1)
1935 pscr |= FORCE_LINK_PASS;
1936 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1938 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1941 * Configure TX path and queues.
1943 tx_set_rate(mp, 1000000000, 16777216);
1944 for (i = 0; i < mp->txq_count; i++) {
1945 struct tx_queue *txq = mp->txq + i;
1947 txq_reset_hw_ptr(txq);
1948 txq_set_rate(txq, 1000000000, 16777216);
1949 txq_set_fixed_prio_mode(txq);
1953 * Add configured unicast address to address filter table.
1955 uc_addr_set(mp, mp->dev->dev_addr);
1958 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1959 * frames to RX queue #0.
1961 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1964 * Treat BPDUs as normal multicasts, and disable partition mode.
1966 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1969 * Enable the receive queues.
1971 for (i = 0; i < mp->rxq_count; i++) {
1972 struct rx_queue *rxq = mp->rxq + i;
1973 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1976 addr = (u32)rxq->rx_desc_dma;
1977 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1984 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1986 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1989 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1990 if (mp->shared->extended_rx_coal_limit) {
1994 val |= (coal & 0x8000) << 10;
1995 val |= (coal & 0x7fff) << 7;
2000 val |= (coal & 0x3fff) << 8;
2002 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2005 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2007 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2011 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2014 static int mv643xx_eth_open(struct net_device *dev)
2016 struct mv643xx_eth_private *mp = netdev_priv(dev);
2021 wrl(mp, INT_CAUSE(mp->port_num), 0);
2022 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2023 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2025 err = request_irq(dev->irq, mv643xx_eth_irq,
2026 IRQF_SHARED, dev->name, dev);
2028 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2032 init_mac_tables(mp);
2034 napi_enable(&mp->napi);
2037 for (i = 0; i < mp->rxq_count; i++) {
2038 err = rxq_init(mp, i);
2041 rxq_deinit(mp->rxq + i);
2045 rxq_refill(mp->rxq + i, INT_MAX, &oom);
2049 mp->rx_oom.expires = jiffies + (HZ / 10);
2050 add_timer(&mp->rx_oom);
2053 for (i = 0; i < mp->txq_count; i++) {
2054 err = txq_init(mp, i);
2057 txq_deinit(mp->txq + i);
2062 netif_carrier_off(dev);
2063 netif_stop_queue(dev);
2070 wrl(mp, INT_MASK_EXT(mp->port_num),
2071 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2073 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2079 for (i = 0; i < mp->rxq_count; i++)
2080 rxq_deinit(mp->rxq + i);
2082 free_irq(dev->irq, dev);
2087 static void port_reset(struct mv643xx_eth_private *mp)
2092 for (i = 0; i < mp->rxq_count; i++)
2093 rxq_disable(mp->rxq + i);
2094 for (i = 0; i < mp->txq_count; i++)
2095 txq_disable(mp->txq + i);
2098 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2100 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2105 /* Reset the Enable bit in the Configuration Register */
2106 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2107 data &= ~(SERIAL_PORT_ENABLE |
2108 DO_NOT_FORCE_LINK_FAIL |
2110 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2113 static int mv643xx_eth_stop(struct net_device *dev)
2115 struct mv643xx_eth_private *mp = netdev_priv(dev);
2118 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2119 rdl(mp, INT_MASK(mp->port_num));
2121 napi_disable(&mp->napi);
2123 del_timer_sync(&mp->rx_oom);
2125 netif_carrier_off(dev);
2126 netif_stop_queue(dev);
2128 free_irq(dev->irq, dev);
2131 mib_counters_update(mp);
2133 for (i = 0; i < mp->rxq_count; i++)
2134 rxq_deinit(mp->rxq + i);
2135 for (i = 0; i < mp->txq_count; i++)
2136 txq_deinit(mp->txq + i);
2141 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2143 struct mv643xx_eth_private *mp = netdev_priv(dev);
2145 if (mp->phy_addr != -1)
2146 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2151 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2153 struct mv643xx_eth_private *mp = netdev_priv(dev);
2155 if (new_mtu < 64 || new_mtu > 9500)
2159 tx_set_rate(mp, 1000000000, 16777216);
2161 if (!netif_running(dev))
2165 * Stop and then re-open the interface. This will allocate RX
2166 * skbs of the new MTU.
2167 * There is a possible danger that the open will not succeed,
2168 * due to memory being full.
2170 mv643xx_eth_stop(dev);
2171 if (mv643xx_eth_open(dev)) {
2172 dev_printk(KERN_ERR, &dev->dev,
2173 "fatal error on re-opening device after "
2180 static void tx_timeout_task(struct work_struct *ugly)
2182 struct mv643xx_eth_private *mp;
2184 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2185 if (netif_running(mp->dev)) {
2186 netif_stop_queue(mp->dev);
2191 __txq_maybe_wake(mp->txq);
2195 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2197 struct mv643xx_eth_private *mp = netdev_priv(dev);
2199 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2201 schedule_work(&mp->tx_timeout_task);
2204 #ifdef CONFIG_NET_POLL_CONTROLLER
2205 static void mv643xx_eth_netpoll(struct net_device *dev)
2207 struct mv643xx_eth_private *mp = netdev_priv(dev);
2209 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2210 rdl(mp, INT_MASK(mp->port_num));
2212 mv643xx_eth_irq(dev->irq, dev);
2214 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2218 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2220 struct mv643xx_eth_private *mp = netdev_priv(dev);
2221 return smi_reg_read(mp, addr, reg);
2224 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2226 struct mv643xx_eth_private *mp = netdev_priv(dev);
2227 smi_reg_write(mp, addr, reg, val);
2231 /* platform glue ************************************************************/
2233 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2234 struct mbus_dram_target_info *dram)
2236 void __iomem *base = msp->base;
2241 for (i = 0; i < 6; i++) {
2242 writel(0, base + WINDOW_BASE(i));
2243 writel(0, base + WINDOW_SIZE(i));
2245 writel(0, base + WINDOW_REMAP_HIGH(i));
2251 for (i = 0; i < dram->num_cs; i++) {
2252 struct mbus_dram_window *cs = dram->cs + i;
2254 writel((cs->base & 0xffff0000) |
2255 (cs->mbus_attr << 8) |
2256 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2257 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2259 win_enable &= ~(1 << i);
2260 win_protect |= 3 << (2 * i);
2263 writel(win_enable, base + WINDOW_BAR_ENABLE);
2264 msp->win_protect = win_protect;
2267 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2270 * Check whether we have a 14-bit coal limit field in bits
2271 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2272 * SDMA config register.
2274 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2275 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2276 msp->extended_rx_coal_limit = 1;
2278 msp->extended_rx_coal_limit = 0;
2281 * Check whether the TX rate control registers are in the
2282 * old or the new place.
2284 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2285 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2286 msp->tx_bw_control_moved = 1;
2288 msp->tx_bw_control_moved = 0;
2291 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2293 static int mv643xx_eth_version_printed = 0;
2294 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2295 struct mv643xx_eth_shared_private *msp;
2296 struct resource *res;
2299 if (!mv643xx_eth_version_printed++)
2300 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2301 "driver version %s\n", mv643xx_eth_driver_version);
2304 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2309 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2312 memset(msp, 0, sizeof(*msp));
2314 msp->base = ioremap(res->start, res->end - res->start + 1);
2315 if (msp->base == NULL)
2319 if (pd != NULL && pd->shared_smi != NULL)
2320 msp->smi = platform_get_drvdata(pd->shared_smi);
2322 mutex_init(&msp->phy_lock);
2324 msp->err_interrupt = NO_IRQ;
2325 init_waitqueue_head(&msp->smi_busy_wait);
2328 * Check whether the error interrupt is hooked up.
2330 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2334 err = request_irq(res->start, mv643xx_eth_err_irq,
2335 IRQF_SHARED, "mv643xx_eth", msp);
2337 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2338 msp->err_interrupt = res->start;
2343 * (Re-)program MBUS remapping windows if we are asked to.
2345 if (pd != NULL && pd->dram != NULL)
2346 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2349 * Detect hardware parameters.
2351 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2352 infer_hw_params(msp);
2354 platform_set_drvdata(pdev, msp);
2364 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2366 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2368 if (msp->err_interrupt != NO_IRQ)
2369 free_irq(msp->err_interrupt, msp);
2376 static struct platform_driver mv643xx_eth_shared_driver = {
2377 .probe = mv643xx_eth_shared_probe,
2378 .remove = mv643xx_eth_shared_remove,
2380 .name = MV643XX_ETH_SHARED_NAME,
2381 .owner = THIS_MODULE,
2385 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2387 int addr_shift = 5 * mp->port_num;
2390 data = rdl(mp, PHY_ADDR);
2391 data &= ~(0x1f << addr_shift);
2392 data |= (phy_addr & 0x1f) << addr_shift;
2393 wrl(mp, PHY_ADDR, data);
2396 static int phy_addr_get(struct mv643xx_eth_private *mp)
2400 data = rdl(mp, PHY_ADDR);
2402 return (data >> (5 * mp->port_num)) & 0x1f;
2405 static void set_params(struct mv643xx_eth_private *mp,
2406 struct mv643xx_eth_platform_data *pd)
2408 struct net_device *dev = mp->dev;
2410 if (is_valid_ether_addr(pd->mac_addr))
2411 memcpy(dev->dev_addr, pd->mac_addr, 6);
2413 uc_addr_get(mp, dev->dev_addr);
2415 if (pd->phy_addr == -1) {
2418 if (pd->force_phy_addr || pd->phy_addr) {
2419 mp->phy_addr = pd->phy_addr & 0x3f;
2420 phy_addr_set(mp, mp->phy_addr);
2422 mp->phy_addr = phy_addr_get(mp);
2426 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2427 if (pd->rx_queue_size)
2428 mp->default_rx_ring_size = pd->rx_queue_size;
2429 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2430 mp->rx_desc_sram_size = pd->rx_sram_size;
2432 mp->rxq_count = pd->rx_queue_count ? : 1;
2434 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2435 if (pd->tx_queue_size)
2436 mp->default_tx_ring_size = pd->tx_queue_size;
2437 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2438 mp->tx_desc_sram_size = pd->tx_sram_size;
2440 mp->txq_count = pd->tx_queue_count ? : 1;
2443 static int phy_detect(struct mv643xx_eth_private *mp)
2448 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2452 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2455 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2459 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2462 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2467 static int phy_init(struct mv643xx_eth_private *mp,
2468 struct mv643xx_eth_platform_data *pd)
2470 struct ethtool_cmd cmd;
2473 err = phy_detect(mp);
2475 dev_printk(KERN_INFO, &mp->dev->dev,
2476 "no PHY detected at addr %d\n", mp->phy_addr);
2481 mp->mii.phy_id = mp->phy_addr;
2482 mp->mii.phy_id_mask = 0x3f;
2483 mp->mii.reg_num_mask = 0x1f;
2484 mp->mii.dev = mp->dev;
2485 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2486 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2488 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2490 memset(&cmd, 0, sizeof(cmd));
2492 cmd.port = PORT_MII;
2493 cmd.transceiver = XCVR_INTERNAL;
2494 cmd.phy_address = mp->phy_addr;
2495 if (pd->speed == 0) {
2496 cmd.autoneg = AUTONEG_ENABLE;
2497 cmd.speed = SPEED_100;
2498 cmd.advertising = ADVERTISED_10baseT_Half |
2499 ADVERTISED_10baseT_Full |
2500 ADVERTISED_100baseT_Half |
2501 ADVERTISED_100baseT_Full;
2502 if (mp->mii.supports_gmii)
2503 cmd.advertising |= ADVERTISED_1000baseT_Full;
2505 cmd.autoneg = AUTONEG_DISABLE;
2506 cmd.speed = pd->speed;
2507 cmd.duplex = pd->duplex;
2510 mv643xx_eth_set_settings(mp->dev, &cmd);
2515 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2519 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2520 if (pscr & SERIAL_PORT_ENABLE) {
2521 pscr &= ~SERIAL_PORT_ENABLE;
2522 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2525 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2526 if (mp->phy_addr == -1) {
2527 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2528 if (speed == SPEED_1000)
2529 pscr |= SET_GMII_SPEED_TO_1000;
2530 else if (speed == SPEED_100)
2531 pscr |= SET_MII_SPEED_TO_100;
2533 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2535 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2536 if (duplex == DUPLEX_FULL)
2537 pscr |= SET_FULL_DUPLEX_MODE;
2540 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2543 static int mv643xx_eth_probe(struct platform_device *pdev)
2545 struct mv643xx_eth_platform_data *pd;
2546 struct mv643xx_eth_private *mp;
2547 struct net_device *dev;
2548 struct resource *res;
2549 DECLARE_MAC_BUF(mac);
2552 pd = pdev->dev.platform_data;
2554 dev_printk(KERN_ERR, &pdev->dev,
2555 "no mv643xx_eth_platform_data\n");
2559 if (pd->shared == NULL) {
2560 dev_printk(KERN_ERR, &pdev->dev,
2561 "no mv643xx_eth_platform_data->shared\n");
2565 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2569 mp = netdev_priv(dev);
2570 platform_set_drvdata(pdev, mp);
2572 mp->shared = platform_get_drvdata(pd->shared);
2573 mp->port_num = pd->port_number;
2579 spin_lock_init(&mp->lock);
2581 mib_counters_clear(mp);
2582 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2584 if (mp->phy_addr != -1) {
2585 err = phy_init(mp, pd);
2589 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2591 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2593 init_pscr(mp, pd->speed, pd->duplex);
2595 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2597 init_timer(&mp->rx_oom);
2598 mp->rx_oom.data = (unsigned long)mp;
2599 mp->rx_oom.function = oom_timer_wrapper;
2602 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2604 dev->irq = res->start;
2606 dev->hard_start_xmit = mv643xx_eth_xmit;
2607 dev->open = mv643xx_eth_open;
2608 dev->stop = mv643xx_eth_stop;
2609 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2610 dev->set_mac_address = mv643xx_eth_set_mac_address;
2611 dev->do_ioctl = mv643xx_eth_ioctl;
2612 dev->change_mtu = mv643xx_eth_change_mtu;
2613 dev->tx_timeout = mv643xx_eth_tx_timeout;
2614 #ifdef CONFIG_NET_POLL_CONTROLLER
2615 dev->poll_controller = mv643xx_eth_netpoll;
2617 dev->watchdog_timeo = 2 * HZ;
2620 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2621 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2623 SET_NETDEV_DEV(dev, &pdev->dev);
2625 if (mp->shared->win_protect)
2626 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2628 err = register_netdev(dev);
2632 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2633 mp->port_num, print_mac(mac, dev->dev_addr));
2635 if (mp->tx_desc_sram_size > 0)
2636 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2646 static int mv643xx_eth_remove(struct platform_device *pdev)
2648 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2650 unregister_netdev(mp->dev);
2651 flush_scheduled_work();
2652 free_netdev(mp->dev);
2654 platform_set_drvdata(pdev, NULL);
2659 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2661 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2663 /* Mask all interrupts on ethernet port */
2664 wrl(mp, INT_MASK(mp->port_num), 0);
2665 rdl(mp, INT_MASK(mp->port_num));
2667 if (netif_running(mp->dev))
2671 static struct platform_driver mv643xx_eth_driver = {
2672 .probe = mv643xx_eth_probe,
2673 .remove = mv643xx_eth_remove,
2674 .shutdown = mv643xx_eth_shutdown,
2676 .name = MV643XX_ETH_NAME,
2677 .owner = THIS_MODULE,
2681 static int __init mv643xx_eth_init_module(void)
2685 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2687 rc = platform_driver_register(&mv643xx_eth_driver);
2689 platform_driver_unregister(&mv643xx_eth_shared_driver);
2694 module_init(mv643xx_eth_init_module);
2696 static void __exit mv643xx_eth_cleanup_module(void)
2698 platform_driver_unregister(&mv643xx_eth_driver);
2699 platform_driver_unregister(&mv643xx_eth_shared_driver);
2701 module_exit(mv643xx_eth_cleanup_module);
2703 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2704 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2705 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2706 MODULE_LICENSE("GPL");
2707 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2708 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);