2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/phy.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
62 * Registers shared between all ports.
64 #define PHY_ADDR 0x0000
65 #define SMI_REG 0x0004
66 #define SMI_BUSY 0x10000000
67 #define SMI_READ_VALID 0x08000000
68 #define SMI_OPCODE_READ 0x04000000
69 #define SMI_OPCODE_WRITE 0x00000000
70 #define ERR_INT_CAUSE 0x0080
71 #define ERR_INT_SMI_DONE 0x00000010
72 #define ERR_INT_MASK 0x0084
73 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76 #define WINDOW_BAR_ENABLE 0x0290
77 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
90 #define TX_FIFO_EMPTY 0x00000400
91 #define TX_IN_PROGRESS 0x00000080
92 #define PORT_SPEED_MASK 0x00000030
93 #define PORT_SPEED_1000 0x00000010
94 #define PORT_SPEED_100 0x00000020
95 #define PORT_SPEED_10 0x00000000
96 #define FLOW_CONTROL_ENABLED 0x00000008
97 #define FULL_DUPLEX 0x00000004
98 #define LINK_UP 0x00000002
99 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
100 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
102 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
103 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
104 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
105 #define INT_TX_END 0x07f80000
106 #define INT_RX 0x000003fc
107 #define INT_EXT 0x00000002
108 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
109 #define INT_EXT_LINK_PHY 0x00110000
110 #define INT_EXT_TX 0x000000ff
111 #define INT_MASK(p) (0x0468 + ((p) << 10))
112 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
114 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
118 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
119 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
120 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_16_64BIT (4 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_16_64BIT (4 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 128
169 #define DEFAULT_TX_QUEUE_SIZE 256
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
232 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
233 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
235 #define TX_IHL_SHIFT 11
238 /* global *******************************************************************/
239 struct mv643xx_eth_shared_private {
241 * Ethernet controller base address.
246 * Points at the right SMI instance to use.
248 struct mv643xx_eth_shared_private *smi;
251 * Provides access to local SMI interface.
253 struct mii_bus smi_bus;
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
262 wait_queue_head_t smi_busy_wait;
265 * Per-port MBUS window access register value.
270 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
277 #define TX_BW_CONTROL_ABSENT 0
278 #define TX_BW_CONTROL_OLD_LAYOUT 1
279 #define TX_BW_CONTROL_NEW_LAYOUT 2
282 /* per-port *****************************************************************/
283 struct mib_counters {
284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
304 u32 good_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
310 u32 mac_receive_error;
325 struct rx_desc *rx_desc_area;
326 dma_addr_t rx_desc_dma;
327 int rx_desc_area_size;
328 struct sk_buff **rx_skb;
340 struct tx_desc *tx_desc_area;
341 dma_addr_t tx_desc_dma;
342 int tx_desc_area_size;
344 struct sk_buff_head tx_skb;
346 unsigned long tx_packets;
347 unsigned long tx_bytes;
348 unsigned long tx_dropped;
351 struct mv643xx_eth_private {
352 struct mv643xx_eth_shared_private *shared;
355 struct net_device *dev;
357 struct phy_device *phy;
359 struct timer_list mib_counters_timer;
360 spinlock_t mib_counters_lock;
361 struct mib_counters mib_counters;
363 struct work_struct tx_timeout_task;
365 struct napi_struct napi;
376 int default_rx_ring_size;
377 unsigned long rx_desc_sram_addr;
378 int rx_desc_sram_size;
380 struct timer_list rx_oom;
381 struct rx_queue rxq[8];
386 int default_tx_ring_size;
387 unsigned long tx_desc_sram_addr;
388 int tx_desc_sram_size;
390 struct tx_queue txq[8];
394 /* port register accessors **************************************************/
395 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
397 return readl(mp->shared->base + offset);
400 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
402 writel(data, mp->shared->base + offset);
406 /* rxq/txq helper functions *************************************************/
407 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
409 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
412 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
414 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
417 static void rxq_enable(struct rx_queue *rxq)
419 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
420 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
423 static void rxq_disable(struct rx_queue *rxq)
425 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
426 u8 mask = 1 << rxq->index;
428 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
429 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
433 static void txq_reset_hw_ptr(struct tx_queue *txq)
435 struct mv643xx_eth_private *mp = txq_to_mp(txq);
436 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
439 addr = (u32)txq->tx_desc_dma;
440 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
444 static void txq_enable(struct tx_queue *txq)
446 struct mv643xx_eth_private *mp = txq_to_mp(txq);
447 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
450 static void txq_disable(struct tx_queue *txq)
452 struct mv643xx_eth_private *mp = txq_to_mp(txq);
453 u8 mask = 1 << txq->index;
455 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
456 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
460 static void txq_maybe_wake(struct tx_queue *txq)
462 struct mv643xx_eth_private *mp = txq_to_mp(txq);
463 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
465 if (netif_tx_queue_stopped(nq)) {
466 __netif_tx_lock(nq, smp_processor_id());
467 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
468 netif_tx_wake_queue(nq);
469 __netif_tx_unlock(nq);
474 /* rx napi ******************************************************************/
475 static int rxq_process(struct rx_queue *rxq, int budget)
477 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
478 struct net_device_stats *stats = &mp->dev->stats;
482 while (rx < budget && rxq->rx_desc_count) {
483 struct rx_desc *rx_desc;
484 unsigned int cmd_sts;
488 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
490 cmd_sts = rx_desc->cmd_sts;
491 if (cmd_sts & BUFFER_OWNED_BY_DMA)
495 skb = rxq->rx_skb[rxq->rx_curr_desc];
496 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
499 if (rxq->rx_curr_desc == rxq->rx_ring_size)
500 rxq->rx_curr_desc = 0;
502 dma_unmap_single(NULL, rx_desc->buf_ptr,
503 rx_desc->buf_size, DMA_FROM_DEVICE);
504 rxq->rx_desc_count--;
507 mp->work_rx_refill |= 1 << rxq->index;
509 byte_cnt = rx_desc->byte_cnt;
514 * Note that the descriptor byte count includes 2 dummy
515 * bytes automatically inserted by the hardware at the
516 * start of the packet (which we don't count), and a 4
517 * byte CRC at the end of the packet (which we do count).
520 stats->rx_bytes += byte_cnt - 2;
523 * In case we received a packet without first / last bits
524 * on, or the error summary bit is set, the packet needs
527 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
528 (RX_FIRST_DESC | RX_LAST_DESC))
529 || (cmd_sts & ERROR_SUMMARY)) {
532 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
533 (RX_FIRST_DESC | RX_LAST_DESC)) {
535 dev_printk(KERN_ERR, &mp->dev->dev,
536 "received packet spanning "
537 "multiple descriptors\n");
540 if (cmd_sts & ERROR_SUMMARY)
546 * The -4 is for the CRC in the trailer of the
549 skb_put(skb, byte_cnt - 2 - 4);
551 if (cmd_sts & LAYER_4_CHECKSUM_OK)
552 skb->ip_summed = CHECKSUM_UNNECESSARY;
553 skb->protocol = eth_type_trans(skb, mp->dev);
554 netif_receive_skb(skb);
557 mp->dev->last_rx = jiffies;
561 mp->work_rx &= ~(1 << rxq->index);
566 static int rxq_refill(struct rx_queue *rxq, int budget)
568 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
573 * Reserve 2+14 bytes for an ethernet header (the hardware
574 * automatically prepends 2 bytes of dummy data to each
575 * received packet), 16 bytes for up to four VLAN tags, and
576 * 4 bytes for the trailing FCS -- 36 bytes total.
578 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
581 * Make sure that the skb size is a multiple of 8 bytes, as
582 * the lower three bits of the receive descriptor's buffer
583 * size field are ignored by the hardware.
585 skb_size = (skb_size + 7) & ~7;
588 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
593 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
595 mp->work_rx_oom |= 1 << rxq->index;
599 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
601 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
604 rxq->rx_desc_count++;
606 rx = rxq->rx_used_desc++;
607 if (rxq->rx_used_desc == rxq->rx_ring_size)
608 rxq->rx_used_desc = 0;
610 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
611 skb_size, DMA_FROM_DEVICE);
612 rxq->rx_desc_area[rx].buf_size = skb_size;
613 rxq->rx_skb[rx] = skb;
615 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
620 * The hardware automatically prepends 2 bytes of
621 * dummy data to each received packet, so that the
622 * IP header ends up 16-byte aligned.
627 if (refilled < budget)
628 mp->work_rx_refill &= ~(1 << rxq->index);
635 /* tx ***********************************************************************/
636 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
640 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
641 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
642 if (fragp->size <= 8 && fragp->page_offset & 7)
649 static int txq_alloc_desc_index(struct tx_queue *txq)
653 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
655 tx_desc_curr = txq->tx_curr_desc++;
656 if (txq->tx_curr_desc == txq->tx_ring_size)
657 txq->tx_curr_desc = 0;
659 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
664 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
666 int nr_frags = skb_shinfo(skb)->nr_frags;
669 for (frag = 0; frag < nr_frags; frag++) {
670 skb_frag_t *this_frag;
672 struct tx_desc *desc;
674 this_frag = &skb_shinfo(skb)->frags[frag];
675 tx_index = txq_alloc_desc_index(txq);
676 desc = &txq->tx_desc_area[tx_index];
679 * The last fragment will generate an interrupt
680 * which will free the skb on TX completion.
682 if (frag == nr_frags - 1) {
683 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
684 ZERO_PADDING | TX_LAST_DESC |
687 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
691 desc->byte_cnt = this_frag->size;
692 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
693 this_frag->page_offset,
699 static inline __be16 sum16_as_be(__sum16 sum)
701 return (__force __be16)sum;
704 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
706 struct mv643xx_eth_private *mp = txq_to_mp(txq);
707 int nr_frags = skb_shinfo(skb)->nr_frags;
709 struct tx_desc *desc;
714 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
717 if (skb->ip_summed == CHECKSUM_PARTIAL) {
720 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
721 skb->protocol != htons(ETH_P_8021Q));
723 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
724 if (unlikely(tag_bytes & ~12)) {
725 if (skb_checksum_help(skb) == 0)
732 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
734 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
736 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
738 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
740 switch (ip_hdr(skb)->protocol) {
742 cmd_sts |= UDP_FRAME;
743 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
746 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
753 /* Errata BTS #50, IHL must be 5 if no HW checksum */
754 cmd_sts |= 5 << TX_IHL_SHIFT;
757 tx_index = txq_alloc_desc_index(txq);
758 desc = &txq->tx_desc_area[tx_index];
761 txq_submit_frag_skb(txq, skb);
762 length = skb_headlen(skb);
764 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
768 desc->l4i_chk = l4i_chk;
769 desc->byte_cnt = length;
770 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
772 __skb_queue_tail(&txq->tx_skb, skb);
774 /* ensure all other descriptors are written before first cmd_sts */
776 desc->cmd_sts = cmd_sts;
778 /* clear TX_END status */
779 mp->work_tx_end &= ~(1 << txq->index);
781 /* ensure all descriptors are written before poking hardware */
785 txq->tx_desc_count += nr_frags + 1;
790 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
792 struct mv643xx_eth_private *mp = netdev_priv(dev);
794 struct tx_queue *txq;
795 struct netdev_queue *nq;
797 queue = skb_get_queue_mapping(skb);
798 txq = mp->txq + queue;
799 nq = netdev_get_tx_queue(dev, queue);
801 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
803 dev_printk(KERN_DEBUG, &dev->dev,
804 "failed to linearize skb with tiny "
805 "unaligned fragment\n");
806 return NETDEV_TX_BUSY;
809 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
811 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
816 if (!txq_submit_skb(txq, skb)) {
819 txq->tx_bytes += skb->len;
821 dev->trans_start = jiffies;
823 entries_left = txq->tx_ring_size - txq->tx_desc_count;
824 if (entries_left < MAX_SKB_FRAGS + 1)
825 netif_tx_stop_queue(nq);
832 /* tx napi ******************************************************************/
833 static void txq_kick(struct tx_queue *txq)
835 struct mv643xx_eth_private *mp = txq_to_mp(txq);
836 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
840 __netif_tx_lock(nq, smp_processor_id());
842 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
845 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
846 expected_ptr = (u32)txq->tx_desc_dma +
847 txq->tx_curr_desc * sizeof(struct tx_desc);
849 if (hw_desc_ptr != expected_ptr)
853 __netif_tx_unlock(nq);
855 mp->work_tx_end &= ~(1 << txq->index);
858 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
860 struct mv643xx_eth_private *mp = txq_to_mp(txq);
861 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
864 __netif_tx_lock(nq, smp_processor_id());
867 while (reclaimed < budget && txq->tx_desc_count > 0) {
869 struct tx_desc *desc;
873 tx_index = txq->tx_used_desc;
874 desc = &txq->tx_desc_area[tx_index];
875 cmd_sts = desc->cmd_sts;
877 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
880 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
883 txq->tx_used_desc = tx_index + 1;
884 if (txq->tx_used_desc == txq->tx_ring_size)
885 txq->tx_used_desc = 0;
888 txq->tx_desc_count--;
891 if (cmd_sts & TX_LAST_DESC)
892 skb = __skb_dequeue(&txq->tx_skb);
894 if (cmd_sts & ERROR_SUMMARY) {
895 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
896 mp->dev->stats.tx_errors++;
899 if (cmd_sts & TX_FIRST_DESC) {
900 dma_unmap_single(NULL, desc->buf_ptr,
901 desc->byte_cnt, DMA_TO_DEVICE);
903 dma_unmap_page(NULL, desc->buf_ptr,
904 desc->byte_cnt, DMA_TO_DEVICE);
911 __netif_tx_unlock(nq);
913 if (reclaimed < budget)
914 mp->work_tx &= ~(1 << txq->index);
920 /* tx rate control **********************************************************/
922 * Set total maximum TX rate (shared by all TX queues for this port)
923 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
925 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
931 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
932 if (token_rate > 1023)
935 mtu = (mp->dev->mtu + 255) >> 8;
939 bucket_size = (burst + 255) >> 8;
940 if (bucket_size > 65535)
943 switch (mp->shared->tx_bw_control) {
944 case TX_BW_CONTROL_OLD_LAYOUT:
945 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
946 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
947 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
949 case TX_BW_CONTROL_NEW_LAYOUT:
950 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
951 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
952 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
957 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
959 struct mv643xx_eth_private *mp = txq_to_mp(txq);
963 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
964 if (token_rate > 1023)
967 bucket_size = (burst + 255) >> 8;
968 if (bucket_size > 65535)
971 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
972 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
973 (bucket_size << 10) | token_rate);
976 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
978 struct mv643xx_eth_private *mp = txq_to_mp(txq);
983 * Turn on fixed priority mode.
986 switch (mp->shared->tx_bw_control) {
987 case TX_BW_CONTROL_OLD_LAYOUT:
988 off = TXQ_FIX_PRIO_CONF(mp->port_num);
990 case TX_BW_CONTROL_NEW_LAYOUT:
991 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
997 val |= 1 << txq->index;
1002 static void txq_set_wrr(struct tx_queue *txq, int weight)
1004 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1009 * Turn off fixed priority mode.
1012 switch (mp->shared->tx_bw_control) {
1013 case TX_BW_CONTROL_OLD_LAYOUT:
1014 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1016 case TX_BW_CONTROL_NEW_LAYOUT:
1017 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1023 val &= ~(1 << txq->index);
1027 * Configure WRR weight for this queue.
1029 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1032 val = (val & ~0xff) | (weight & 0xff);
1038 /* mii management interface *************************************************/
1039 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1041 struct mv643xx_eth_shared_private *msp = dev_id;
1043 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1044 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1045 wake_up(&msp->smi_busy_wait);
1052 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1054 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1057 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1059 if (msp->err_interrupt == NO_IRQ) {
1062 for (i = 0; !smi_is_done(msp); i++) {
1071 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1072 msecs_to_jiffies(100)))
1078 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1080 struct mv643xx_eth_shared_private *msp = bus->priv;
1081 void __iomem *smi_reg = msp->base + SMI_REG;
1084 if (smi_wait_ready(msp)) {
1085 printk("mv643xx_eth: SMI bus busy timeout\n");
1089 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1091 if (smi_wait_ready(msp)) {
1092 printk("mv643xx_eth: SMI bus busy timeout\n");
1096 ret = readl(smi_reg);
1097 if (!(ret & SMI_READ_VALID)) {
1098 printk("mv643xx_eth: SMI bus read not valid\n");
1102 return ret & 0xffff;
1105 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1107 struct mv643xx_eth_shared_private *msp = bus->priv;
1108 void __iomem *smi_reg = msp->base + SMI_REG;
1110 if (smi_wait_ready(msp)) {
1111 printk("mv643xx_eth: SMI bus busy timeout\n");
1115 writel(SMI_OPCODE_WRITE | (reg << 21) |
1116 (addr << 16) | (val & 0xffff), smi_reg);
1118 if (smi_wait_ready(msp)) {
1119 printk("mv643xx_eth: SMI bus busy timeout\n");
1127 /* statistics ***************************************************************/
1128 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1130 struct mv643xx_eth_private *mp = netdev_priv(dev);
1131 struct net_device_stats *stats = &dev->stats;
1132 unsigned long tx_packets = 0;
1133 unsigned long tx_bytes = 0;
1134 unsigned long tx_dropped = 0;
1137 for (i = 0; i < mp->txq_count; i++) {
1138 struct tx_queue *txq = mp->txq + i;
1140 tx_packets += txq->tx_packets;
1141 tx_bytes += txq->tx_bytes;
1142 tx_dropped += txq->tx_dropped;
1145 stats->tx_packets = tx_packets;
1146 stats->tx_bytes = tx_bytes;
1147 stats->tx_dropped = tx_dropped;
1152 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1154 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1157 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1161 for (i = 0; i < 0x80; i += 4)
1165 static void mib_counters_update(struct mv643xx_eth_private *mp)
1167 struct mib_counters *p = &mp->mib_counters;
1169 spin_lock(&mp->mib_counters_lock);
1170 p->good_octets_received += mib_read(mp, 0x00);
1171 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1172 p->bad_octets_received += mib_read(mp, 0x08);
1173 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1174 p->good_frames_received += mib_read(mp, 0x10);
1175 p->bad_frames_received += mib_read(mp, 0x14);
1176 p->broadcast_frames_received += mib_read(mp, 0x18);
1177 p->multicast_frames_received += mib_read(mp, 0x1c);
1178 p->frames_64_octets += mib_read(mp, 0x20);
1179 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1180 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1181 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1182 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1183 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1184 p->good_octets_sent += mib_read(mp, 0x38);
1185 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1186 p->good_frames_sent += mib_read(mp, 0x40);
1187 p->excessive_collision += mib_read(mp, 0x44);
1188 p->multicast_frames_sent += mib_read(mp, 0x48);
1189 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1190 p->unrec_mac_control_received += mib_read(mp, 0x50);
1191 p->fc_sent += mib_read(mp, 0x54);
1192 p->good_fc_received += mib_read(mp, 0x58);
1193 p->bad_fc_received += mib_read(mp, 0x5c);
1194 p->undersize_received += mib_read(mp, 0x60);
1195 p->fragments_received += mib_read(mp, 0x64);
1196 p->oversize_received += mib_read(mp, 0x68);
1197 p->jabber_received += mib_read(mp, 0x6c);
1198 p->mac_receive_error += mib_read(mp, 0x70);
1199 p->bad_crc_event += mib_read(mp, 0x74);
1200 p->collision += mib_read(mp, 0x78);
1201 p->late_collision += mib_read(mp, 0x7c);
1202 spin_unlock(&mp->mib_counters_lock);
1204 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1207 static void mib_counters_timer_wrapper(unsigned long _mp)
1209 struct mv643xx_eth_private *mp = (void *)_mp;
1211 mib_counters_update(mp);
1215 /* ethtool ******************************************************************/
1216 struct mv643xx_eth_stats {
1217 char stat_string[ETH_GSTRING_LEN];
1224 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1225 offsetof(struct net_device, stats.m), -1 }
1227 #define MIBSTAT(m) \
1228 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1229 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1231 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1240 MIBSTAT(good_octets_received),
1241 MIBSTAT(bad_octets_received),
1242 MIBSTAT(internal_mac_transmit_err),
1243 MIBSTAT(good_frames_received),
1244 MIBSTAT(bad_frames_received),
1245 MIBSTAT(broadcast_frames_received),
1246 MIBSTAT(multicast_frames_received),
1247 MIBSTAT(frames_64_octets),
1248 MIBSTAT(frames_65_to_127_octets),
1249 MIBSTAT(frames_128_to_255_octets),
1250 MIBSTAT(frames_256_to_511_octets),
1251 MIBSTAT(frames_512_to_1023_octets),
1252 MIBSTAT(frames_1024_to_max_octets),
1253 MIBSTAT(good_octets_sent),
1254 MIBSTAT(good_frames_sent),
1255 MIBSTAT(excessive_collision),
1256 MIBSTAT(multicast_frames_sent),
1257 MIBSTAT(broadcast_frames_sent),
1258 MIBSTAT(unrec_mac_control_received),
1260 MIBSTAT(good_fc_received),
1261 MIBSTAT(bad_fc_received),
1262 MIBSTAT(undersize_received),
1263 MIBSTAT(fragments_received),
1264 MIBSTAT(oversize_received),
1265 MIBSTAT(jabber_received),
1266 MIBSTAT(mac_receive_error),
1267 MIBSTAT(bad_crc_event),
1269 MIBSTAT(late_collision),
1272 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1274 struct mv643xx_eth_private *mp = netdev_priv(dev);
1277 err = phy_read_status(mp->phy);
1279 err = phy_ethtool_gset(mp->phy, cmd);
1282 * The MAC does not support 1000baseT_Half.
1284 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1285 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1290 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1292 struct mv643xx_eth_private *mp = netdev_priv(dev);
1295 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1297 cmd->supported = SUPPORTED_MII;
1298 cmd->advertising = ADVERTISED_MII;
1299 switch (port_status & PORT_SPEED_MASK) {
1301 cmd->speed = SPEED_10;
1303 case PORT_SPEED_100:
1304 cmd->speed = SPEED_100;
1306 case PORT_SPEED_1000:
1307 cmd->speed = SPEED_1000;
1313 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1314 cmd->port = PORT_MII;
1315 cmd->phy_address = 0;
1316 cmd->transceiver = XCVR_INTERNAL;
1317 cmd->autoneg = AUTONEG_DISABLE;
1324 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1326 struct mv643xx_eth_private *mp = netdev_priv(dev);
1329 * The MAC does not support 1000baseT_Half.
1331 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1333 return phy_ethtool_sset(mp->phy, cmd);
1336 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1341 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1342 struct ethtool_drvinfo *drvinfo)
1344 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1345 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1346 strncpy(drvinfo->fw_version, "N/A", 32);
1347 strncpy(drvinfo->bus_info, "platform", 32);
1348 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1351 static int mv643xx_eth_nway_reset(struct net_device *dev)
1353 struct mv643xx_eth_private *mp = netdev_priv(dev);
1355 return genphy_restart_aneg(mp->phy);
1358 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1363 static u32 mv643xx_eth_get_link(struct net_device *dev)
1365 return !!netif_carrier_ok(dev);
1368 static void mv643xx_eth_get_strings(struct net_device *dev,
1369 uint32_t stringset, uint8_t *data)
1373 if (stringset == ETH_SS_STATS) {
1374 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1375 memcpy(data + i * ETH_GSTRING_LEN,
1376 mv643xx_eth_stats[i].stat_string,
1382 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1383 struct ethtool_stats *stats,
1386 struct mv643xx_eth_private *mp = netdev_priv(dev);
1389 mv643xx_eth_get_stats(dev);
1390 mib_counters_update(mp);
1392 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1393 const struct mv643xx_eth_stats *stat;
1396 stat = mv643xx_eth_stats + i;
1398 if (stat->netdev_off >= 0)
1399 p = ((void *)mp->dev) + stat->netdev_off;
1401 p = ((void *)mp) + stat->mp_off;
1403 data[i] = (stat->sizeof_stat == 8) ?
1404 *(uint64_t *)p : *(uint32_t *)p;
1408 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1410 if (sset == ETH_SS_STATS)
1411 return ARRAY_SIZE(mv643xx_eth_stats);
1416 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1417 .get_settings = mv643xx_eth_get_settings,
1418 .set_settings = mv643xx_eth_set_settings,
1419 .get_drvinfo = mv643xx_eth_get_drvinfo,
1420 .nway_reset = mv643xx_eth_nway_reset,
1421 .get_link = mv643xx_eth_get_link,
1422 .set_sg = ethtool_op_set_sg,
1423 .get_strings = mv643xx_eth_get_strings,
1424 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1425 .get_sset_count = mv643xx_eth_get_sset_count,
1428 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1429 .get_settings = mv643xx_eth_get_settings_phyless,
1430 .set_settings = mv643xx_eth_set_settings_phyless,
1431 .get_drvinfo = mv643xx_eth_get_drvinfo,
1432 .nway_reset = mv643xx_eth_nway_reset_phyless,
1433 .get_link = mv643xx_eth_get_link,
1434 .set_sg = ethtool_op_set_sg,
1435 .get_strings = mv643xx_eth_get_strings,
1436 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1437 .get_sset_count = mv643xx_eth_get_sset_count,
1441 /* address handling *********************************************************/
1442 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1447 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1448 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1450 addr[0] = (mac_h >> 24) & 0xff;
1451 addr[1] = (mac_h >> 16) & 0xff;
1452 addr[2] = (mac_h >> 8) & 0xff;
1453 addr[3] = mac_h & 0xff;
1454 addr[4] = (mac_l >> 8) & 0xff;
1455 addr[5] = mac_l & 0xff;
1458 static void init_mac_tables(struct mv643xx_eth_private *mp)
1462 for (i = 0; i < 0x100; i += 4) {
1463 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1464 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1467 for (i = 0; i < 0x10; i += 4)
1468 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1471 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1472 int table, unsigned char entry)
1474 unsigned int table_reg;
1476 /* Set "accepts frame bit" at specified table entry */
1477 table_reg = rdl(mp, table + (entry & 0xfc));
1478 table_reg |= 0x01 << (8 * (entry & 3));
1479 wrl(mp, table + (entry & 0xfc), table_reg);
1482 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1488 mac_l = (addr[4] << 8) | addr[5];
1489 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1491 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1492 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1494 table = UNICAST_TABLE(mp->port_num);
1495 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1498 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1500 struct mv643xx_eth_private *mp = netdev_priv(dev);
1502 /* +2 is for the offset of the HW addr type */
1503 memcpy(dev->dev_addr, addr + 2, 6);
1505 init_mac_tables(mp);
1506 uc_addr_set(mp, dev->dev_addr);
1511 static int addr_crc(unsigned char *addr)
1516 for (i = 0; i < 6; i++) {
1519 crc = (crc ^ addr[i]) << 8;
1520 for (j = 7; j >= 0; j--) {
1521 if (crc & (0x100 << j))
1529 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1531 struct mv643xx_eth_private *mp = netdev_priv(dev);
1533 struct dev_addr_list *addr;
1536 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1537 if (dev->flags & IFF_PROMISC)
1538 port_config |= UNICAST_PROMISCUOUS_MODE;
1540 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1541 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1543 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1544 int port_num = mp->port_num;
1545 u32 accept = 0x01010101;
1547 for (i = 0; i < 0x100; i += 4) {
1548 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1549 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1554 for (i = 0; i < 0x100; i += 4) {
1555 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1556 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1559 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1560 u8 *a = addr->da_addr;
1563 if (addr->da_addrlen != 6)
1566 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1567 table = SPECIAL_MCAST_TABLE(mp->port_num);
1568 set_filter_table_entry(mp, table, a[5]);
1570 int crc = addr_crc(a);
1572 table = OTHER_MCAST_TABLE(mp->port_num);
1573 set_filter_table_entry(mp, table, crc);
1579 /* rx/tx queue initialisation ***********************************************/
1580 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1582 struct rx_queue *rxq = mp->rxq + index;
1583 struct rx_desc *rx_desc;
1589 rxq->rx_ring_size = mp->default_rx_ring_size;
1591 rxq->rx_desc_count = 0;
1592 rxq->rx_curr_desc = 0;
1593 rxq->rx_used_desc = 0;
1595 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1597 if (index == 0 && size <= mp->rx_desc_sram_size) {
1598 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1599 mp->rx_desc_sram_size);
1600 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1602 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1607 if (rxq->rx_desc_area == NULL) {
1608 dev_printk(KERN_ERR, &mp->dev->dev,
1609 "can't allocate rx ring (%d bytes)\n", size);
1612 memset(rxq->rx_desc_area, 0, size);
1614 rxq->rx_desc_area_size = size;
1615 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1617 if (rxq->rx_skb == NULL) {
1618 dev_printk(KERN_ERR, &mp->dev->dev,
1619 "can't allocate rx skb ring\n");
1623 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1624 for (i = 0; i < rxq->rx_ring_size; i++) {
1628 if (nexti == rxq->rx_ring_size)
1631 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1632 nexti * sizeof(struct rx_desc);
1639 if (index == 0 && size <= mp->rx_desc_sram_size)
1640 iounmap(rxq->rx_desc_area);
1642 dma_free_coherent(NULL, size,
1650 static void rxq_deinit(struct rx_queue *rxq)
1652 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1657 for (i = 0; i < rxq->rx_ring_size; i++) {
1658 if (rxq->rx_skb[i]) {
1659 dev_kfree_skb(rxq->rx_skb[i]);
1660 rxq->rx_desc_count--;
1664 if (rxq->rx_desc_count) {
1665 dev_printk(KERN_ERR, &mp->dev->dev,
1666 "error freeing rx ring -- %d skbs stuck\n",
1667 rxq->rx_desc_count);
1670 if (rxq->index == 0 &&
1671 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1672 iounmap(rxq->rx_desc_area);
1674 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1675 rxq->rx_desc_area, rxq->rx_desc_dma);
1680 static int txq_init(struct mv643xx_eth_private *mp, int index)
1682 struct tx_queue *txq = mp->txq + index;
1683 struct tx_desc *tx_desc;
1689 txq->tx_ring_size = mp->default_tx_ring_size;
1691 txq->tx_desc_count = 0;
1692 txq->tx_curr_desc = 0;
1693 txq->tx_used_desc = 0;
1695 size = txq->tx_ring_size * sizeof(struct tx_desc);
1697 if (index == 0 && size <= mp->tx_desc_sram_size) {
1698 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1699 mp->tx_desc_sram_size);
1700 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1702 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1707 if (txq->tx_desc_area == NULL) {
1708 dev_printk(KERN_ERR, &mp->dev->dev,
1709 "can't allocate tx ring (%d bytes)\n", size);
1712 memset(txq->tx_desc_area, 0, size);
1714 txq->tx_desc_area_size = size;
1716 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1717 for (i = 0; i < txq->tx_ring_size; i++) {
1718 struct tx_desc *txd = tx_desc + i;
1722 if (nexti == txq->tx_ring_size)
1726 txd->next_desc_ptr = txq->tx_desc_dma +
1727 nexti * sizeof(struct tx_desc);
1730 skb_queue_head_init(&txq->tx_skb);
1735 static void txq_deinit(struct tx_queue *txq)
1737 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1740 txq_reclaim(txq, txq->tx_ring_size, 1);
1742 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1744 if (txq->index == 0 &&
1745 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1746 iounmap(txq->tx_desc_area);
1748 dma_free_coherent(NULL, txq->tx_desc_area_size,
1749 txq->tx_desc_area, txq->tx_desc_dma);
1753 /* netdev ops and related ***************************************************/
1754 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1759 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1760 (INT_TX_END | INT_RX | INT_EXT);
1765 if (int_cause & INT_EXT)
1766 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1768 int_cause &= INT_TX_END | INT_RX;
1770 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1771 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1772 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1773 mp->work_rx |= (int_cause & INT_RX) >> 2;
1776 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1777 if (int_cause_ext) {
1778 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1779 if (int_cause_ext & INT_EXT_LINK_PHY)
1781 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1787 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1789 struct net_device *dev = (struct net_device *)dev_id;
1790 struct mv643xx_eth_private *mp = netdev_priv(dev);
1792 if (unlikely(!mv643xx_eth_collect_events(mp)))
1795 wrl(mp, INT_MASK(mp->port_num), 0);
1796 napi_schedule(&mp->napi);
1801 static void handle_link_event(struct mv643xx_eth_private *mp)
1803 struct net_device *dev = mp->dev;
1809 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1810 if (!(port_status & LINK_UP)) {
1811 if (netif_carrier_ok(dev)) {
1814 printk(KERN_INFO "%s: link down\n", dev->name);
1816 netif_carrier_off(dev);
1818 for (i = 0; i < mp->txq_count; i++) {
1819 struct tx_queue *txq = mp->txq + i;
1821 txq_reclaim(txq, txq->tx_ring_size, 1);
1822 txq_reset_hw_ptr(txq);
1828 switch (port_status & PORT_SPEED_MASK) {
1832 case PORT_SPEED_100:
1835 case PORT_SPEED_1000:
1842 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1843 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1845 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1846 "flow control %sabled\n", dev->name,
1847 speed, duplex ? "full" : "half",
1850 if (!netif_carrier_ok(dev))
1851 netif_carrier_on(dev);
1854 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1856 struct mv643xx_eth_private *mp;
1859 mp = container_of(napi, struct mv643xx_eth_private, napi);
1861 mp->work_rx_refill |= mp->work_rx_oom;
1862 mp->work_rx_oom = 0;
1865 while (work_done < budget) {
1870 if (mp->work_link) {
1872 handle_link_event(mp);
1876 queue_mask = mp->work_tx | mp->work_tx_end |
1877 mp->work_rx | mp->work_rx_refill;
1879 if (mv643xx_eth_collect_events(mp))
1884 queue = fls(queue_mask) - 1;
1885 queue_mask = 1 << queue;
1887 work_tbd = budget - work_done;
1891 if (mp->work_tx_end & queue_mask) {
1892 txq_kick(mp->txq + queue);
1893 } else if (mp->work_tx & queue_mask) {
1894 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1895 txq_maybe_wake(mp->txq + queue);
1896 } else if (mp->work_rx & queue_mask) {
1897 work_done += rxq_process(mp->rxq + queue, work_tbd);
1898 } else if (mp->work_rx_refill & queue_mask) {
1899 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1905 if (work_done < budget) {
1906 if (mp->work_rx_oom)
1907 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1908 napi_complete(napi);
1909 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1915 static inline void oom_timer_wrapper(unsigned long data)
1917 struct mv643xx_eth_private *mp = (void *)data;
1919 napi_schedule(&mp->napi);
1922 static void phy_reset(struct mv643xx_eth_private *mp)
1926 data = phy_read(mp->phy, MII_BMCR);
1931 if (phy_write(mp->phy, MII_BMCR, data) < 0)
1935 data = phy_read(mp->phy, MII_BMCR);
1936 } while (data >= 0 && data & BMCR_RESET);
1939 static void port_start(struct mv643xx_eth_private *mp)
1945 * Perform PHY reset, if there is a PHY.
1947 if (mp->phy != NULL) {
1948 struct ethtool_cmd cmd;
1950 mv643xx_eth_get_settings(mp->dev, &cmd);
1952 mv643xx_eth_set_settings(mp->dev, &cmd);
1956 * Configure basic link parameters.
1958 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1960 pscr |= SERIAL_PORT_ENABLE;
1961 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1963 pscr |= DO_NOT_FORCE_LINK_FAIL;
1964 if (mp->phy == NULL)
1965 pscr |= FORCE_LINK_PASS;
1966 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1968 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1971 * Configure TX path and queues.
1973 tx_set_rate(mp, 1000000000, 16777216);
1974 for (i = 0; i < mp->txq_count; i++) {
1975 struct tx_queue *txq = mp->txq + i;
1977 txq_reset_hw_ptr(txq);
1978 txq_set_rate(txq, 1000000000, 16777216);
1979 txq_set_fixed_prio_mode(txq);
1983 * Add configured unicast address to address filter table.
1985 uc_addr_set(mp, mp->dev->dev_addr);
1988 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1989 * frames to RX queue #0, and include the pseudo-header when
1990 * calculating receive checksums.
1992 wrl(mp, PORT_CONFIG(mp->port_num), 0x02000000);
1995 * Treat BPDUs as normal multicasts, and disable partition mode.
1997 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2000 * Enable the receive queues.
2002 for (i = 0; i < mp->rxq_count; i++) {
2003 struct rx_queue *rxq = mp->rxq + i;
2004 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2007 addr = (u32)rxq->rx_desc_dma;
2008 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2015 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2017 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2020 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2021 if (mp->shared->extended_rx_coal_limit) {
2025 val |= (coal & 0x8000) << 10;
2026 val |= (coal & 0x7fff) << 7;
2031 val |= (coal & 0x3fff) << 8;
2033 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2036 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2038 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2042 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2045 static int mv643xx_eth_open(struct net_device *dev)
2047 struct mv643xx_eth_private *mp = netdev_priv(dev);
2051 wrl(mp, INT_CAUSE(mp->port_num), 0);
2052 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2053 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2055 err = request_irq(dev->irq, mv643xx_eth_irq,
2056 IRQF_SHARED, dev->name, dev);
2058 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2062 init_mac_tables(mp);
2064 napi_enable(&mp->napi);
2066 for (i = 0; i < mp->rxq_count; i++) {
2067 err = rxq_init(mp, i);
2070 rxq_deinit(mp->rxq + i);
2074 rxq_refill(mp->rxq + i, INT_MAX);
2077 if (mp->work_rx_oom) {
2078 mp->rx_oom.expires = jiffies + (HZ / 10);
2079 add_timer(&mp->rx_oom);
2082 for (i = 0; i < mp->txq_count; i++) {
2083 err = txq_init(mp, i);
2086 txq_deinit(mp->txq + i);
2091 netif_carrier_off(dev);
2098 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2099 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2105 for (i = 0; i < mp->rxq_count; i++)
2106 rxq_deinit(mp->rxq + i);
2108 free_irq(dev->irq, dev);
2113 static void port_reset(struct mv643xx_eth_private *mp)
2118 for (i = 0; i < mp->rxq_count; i++)
2119 rxq_disable(mp->rxq + i);
2120 for (i = 0; i < mp->txq_count; i++)
2121 txq_disable(mp->txq + i);
2124 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2126 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2131 /* Reset the Enable bit in the Configuration Register */
2132 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2133 data &= ~(SERIAL_PORT_ENABLE |
2134 DO_NOT_FORCE_LINK_FAIL |
2136 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2139 static int mv643xx_eth_stop(struct net_device *dev)
2141 struct mv643xx_eth_private *mp = netdev_priv(dev);
2144 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2145 rdl(mp, INT_MASK(mp->port_num));
2147 del_timer_sync(&mp->mib_counters_timer);
2149 napi_disable(&mp->napi);
2151 del_timer_sync(&mp->rx_oom);
2153 netif_carrier_off(dev);
2155 free_irq(dev->irq, dev);
2158 mv643xx_eth_get_stats(dev);
2159 mib_counters_update(mp);
2161 for (i = 0; i < mp->rxq_count; i++)
2162 rxq_deinit(mp->rxq + i);
2163 for (i = 0; i < mp->txq_count; i++)
2164 txq_deinit(mp->txq + i);
2169 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2171 struct mv643xx_eth_private *mp = netdev_priv(dev);
2173 if (mp->phy != NULL)
2174 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2179 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
2183 if (new_mtu < 64 || new_mtu > 9500)
2187 tx_set_rate(mp, 1000000000, 16777216);
2189 if (!netif_running(dev))
2193 * Stop and then re-open the interface. This will allocate RX
2194 * skbs of the new MTU.
2195 * There is a possible danger that the open will not succeed,
2196 * due to memory being full.
2198 mv643xx_eth_stop(dev);
2199 if (mv643xx_eth_open(dev)) {
2200 dev_printk(KERN_ERR, &dev->dev,
2201 "fatal error on re-opening device after "
2208 static void tx_timeout_task(struct work_struct *ugly)
2210 struct mv643xx_eth_private *mp;
2212 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2213 if (netif_running(mp->dev)) {
2214 netif_tx_stop_all_queues(mp->dev);
2217 netif_tx_wake_all_queues(mp->dev);
2221 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2223 struct mv643xx_eth_private *mp = netdev_priv(dev);
2225 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2227 schedule_work(&mp->tx_timeout_task);
2230 #ifdef CONFIG_NET_POLL_CONTROLLER
2231 static void mv643xx_eth_netpoll(struct net_device *dev)
2233 struct mv643xx_eth_private *mp = netdev_priv(dev);
2235 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2236 rdl(mp, INT_MASK(mp->port_num));
2238 mv643xx_eth_irq(dev->irq, dev);
2240 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2245 /* platform glue ************************************************************/
2247 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2248 struct mbus_dram_target_info *dram)
2250 void __iomem *base = msp->base;
2255 for (i = 0; i < 6; i++) {
2256 writel(0, base + WINDOW_BASE(i));
2257 writel(0, base + WINDOW_SIZE(i));
2259 writel(0, base + WINDOW_REMAP_HIGH(i));
2265 for (i = 0; i < dram->num_cs; i++) {
2266 struct mbus_dram_window *cs = dram->cs + i;
2268 writel((cs->base & 0xffff0000) |
2269 (cs->mbus_attr << 8) |
2270 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2271 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2273 win_enable &= ~(1 << i);
2274 win_protect |= 3 << (2 * i);
2277 writel(win_enable, base + WINDOW_BAR_ENABLE);
2278 msp->win_protect = win_protect;
2281 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2284 * Check whether we have a 14-bit coal limit field in bits
2285 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2286 * SDMA config register.
2288 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2289 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2290 msp->extended_rx_coal_limit = 1;
2292 msp->extended_rx_coal_limit = 0;
2295 * Check whether the MAC supports TX rate control, and if
2296 * yes, whether its associated registers are in the old or
2299 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2300 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) {
2301 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2303 writel(7, msp->base + TX_BW_RATE(0));
2304 if (readl(msp->base + TX_BW_RATE(0)) & 7)
2305 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2307 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2311 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2313 static int mv643xx_eth_version_printed = 0;
2314 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2315 struct mv643xx_eth_shared_private *msp;
2316 struct resource *res;
2319 if (!mv643xx_eth_version_printed++)
2320 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2321 "driver version %s\n", mv643xx_eth_driver_version);
2324 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2329 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2332 memset(msp, 0, sizeof(*msp));
2334 msp->base = ioremap(res->start, res->end - res->start + 1);
2335 if (msp->base == NULL)
2339 * Set up and register SMI bus.
2341 if (pd == NULL || pd->shared_smi == NULL) {
2342 msp->smi_bus.priv = msp;
2343 msp->smi_bus.name = "mv643xx_eth smi";
2344 msp->smi_bus.read = smi_bus_read;
2345 msp->smi_bus.write = smi_bus_write,
2346 snprintf(msp->smi_bus.id, MII_BUS_ID_SIZE, "%d", pdev->id);
2347 msp->smi_bus.dev = &pdev->dev;
2348 msp->smi_bus.phy_mask = 0xffffffff;
2349 if (mdiobus_register(&msp->smi_bus) < 0)
2353 msp->smi = platform_get_drvdata(pd->shared_smi);
2356 msp->err_interrupt = NO_IRQ;
2357 init_waitqueue_head(&msp->smi_busy_wait);
2360 * Check whether the error interrupt is hooked up.
2362 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2366 err = request_irq(res->start, mv643xx_eth_err_irq,
2367 IRQF_SHARED, "mv643xx_eth", msp);
2369 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2370 msp->err_interrupt = res->start;
2375 * (Re-)program MBUS remapping windows if we are asked to.
2377 if (pd != NULL && pd->dram != NULL)
2378 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2381 * Detect hardware parameters.
2383 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2384 infer_hw_params(msp);
2386 platform_set_drvdata(pdev, msp);
2398 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2400 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2401 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2403 if (pd == NULL || pd->shared_smi == NULL)
2404 mdiobus_unregister(&msp->smi_bus);
2405 if (msp->err_interrupt != NO_IRQ)
2406 free_irq(msp->err_interrupt, msp);
2413 static struct platform_driver mv643xx_eth_shared_driver = {
2414 .probe = mv643xx_eth_shared_probe,
2415 .remove = mv643xx_eth_shared_remove,
2417 .name = MV643XX_ETH_SHARED_NAME,
2418 .owner = THIS_MODULE,
2422 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2424 int addr_shift = 5 * mp->port_num;
2427 data = rdl(mp, PHY_ADDR);
2428 data &= ~(0x1f << addr_shift);
2429 data |= (phy_addr & 0x1f) << addr_shift;
2430 wrl(mp, PHY_ADDR, data);
2433 static int phy_addr_get(struct mv643xx_eth_private *mp)
2437 data = rdl(mp, PHY_ADDR);
2439 return (data >> (5 * mp->port_num)) & 0x1f;
2442 static void set_params(struct mv643xx_eth_private *mp,
2443 struct mv643xx_eth_platform_data *pd)
2445 struct net_device *dev = mp->dev;
2447 if (is_valid_ether_addr(pd->mac_addr))
2448 memcpy(dev->dev_addr, pd->mac_addr, 6);
2450 uc_addr_get(mp, dev->dev_addr);
2452 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2453 if (pd->rx_queue_size)
2454 mp->default_rx_ring_size = pd->rx_queue_size;
2455 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2456 mp->rx_desc_sram_size = pd->rx_sram_size;
2458 mp->rxq_count = pd->rx_queue_count ? : 1;
2460 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2461 if (pd->tx_queue_size)
2462 mp->default_tx_ring_size = pd->tx_queue_size;
2463 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2464 mp->tx_desc_sram_size = pd->tx_sram_size;
2466 mp->txq_count = pd->tx_queue_count ? : 1;
2469 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2472 struct mii_bus *bus = &mp->shared->smi->smi_bus;
2473 struct phy_device *phydev;
2478 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2479 start = phy_addr_get(mp) & 0x1f;
2482 start = phy_addr & 0x1f;
2487 for (i = 0; i < num; i++) {
2488 int addr = (start + i) & 0x1f;
2490 if (bus->phy_map[addr] == NULL)
2491 mdiobus_scan(bus, addr);
2493 if (phydev == NULL) {
2494 phydev = bus->phy_map[addr];
2496 phy_addr_set(mp, addr);
2503 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2505 struct phy_device *phy = mp->phy;
2509 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2512 phy->autoneg = AUTONEG_ENABLE;
2515 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2517 phy->autoneg = AUTONEG_DISABLE;
2518 phy->advertising = 0;
2520 phy->duplex = duplex;
2522 phy_start_aneg(phy);
2525 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2529 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2530 if (pscr & SERIAL_PORT_ENABLE) {
2531 pscr &= ~SERIAL_PORT_ENABLE;
2532 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2535 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2536 if (mp->phy == NULL) {
2537 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2538 if (speed == SPEED_1000)
2539 pscr |= SET_GMII_SPEED_TO_1000;
2540 else if (speed == SPEED_100)
2541 pscr |= SET_MII_SPEED_TO_100;
2543 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2545 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2546 if (duplex == DUPLEX_FULL)
2547 pscr |= SET_FULL_DUPLEX_MODE;
2550 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2553 static int mv643xx_eth_probe(struct platform_device *pdev)
2555 struct mv643xx_eth_platform_data *pd;
2556 struct mv643xx_eth_private *mp;
2557 struct net_device *dev;
2558 struct resource *res;
2559 DECLARE_MAC_BUF(mac);
2562 pd = pdev->dev.platform_data;
2564 dev_printk(KERN_ERR, &pdev->dev,
2565 "no mv643xx_eth_platform_data\n");
2569 if (pd->shared == NULL) {
2570 dev_printk(KERN_ERR, &pdev->dev,
2571 "no mv643xx_eth_platform_data->shared\n");
2575 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2579 mp = netdev_priv(dev);
2580 platform_set_drvdata(pdev, mp);
2582 mp->shared = platform_get_drvdata(pd->shared);
2583 mp->port_num = pd->port_number;
2588 dev->real_num_tx_queues = mp->txq_count;
2590 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2591 mp->phy = phy_scan(mp, pd->phy_addr);
2593 if (mp->phy != NULL) {
2594 phy_init(mp, pd->speed, pd->duplex);
2595 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2597 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2600 init_pscr(mp, pd->speed, pd->duplex);
2603 mib_counters_clear(mp);
2605 init_timer(&mp->mib_counters_timer);
2606 mp->mib_counters_timer.data = (unsigned long)mp;
2607 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2608 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2609 add_timer(&mp->mib_counters_timer);
2611 spin_lock_init(&mp->mib_counters_lock);
2613 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2615 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2617 init_timer(&mp->rx_oom);
2618 mp->rx_oom.data = (unsigned long)mp;
2619 mp->rx_oom.function = oom_timer_wrapper;
2622 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2624 dev->irq = res->start;
2626 dev->get_stats = mv643xx_eth_get_stats;
2627 dev->hard_start_xmit = mv643xx_eth_xmit;
2628 dev->open = mv643xx_eth_open;
2629 dev->stop = mv643xx_eth_stop;
2630 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2631 dev->set_mac_address = mv643xx_eth_set_mac_address;
2632 dev->do_ioctl = mv643xx_eth_ioctl;
2633 dev->change_mtu = mv643xx_eth_change_mtu;
2634 dev->tx_timeout = mv643xx_eth_tx_timeout;
2635 #ifdef CONFIG_NET_POLL_CONTROLLER
2636 dev->poll_controller = mv643xx_eth_netpoll;
2638 dev->watchdog_timeo = 2 * HZ;
2641 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2642 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2644 SET_NETDEV_DEV(dev, &pdev->dev);
2646 if (mp->shared->win_protect)
2647 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2649 err = register_netdev(dev);
2653 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2654 mp->port_num, print_mac(mac, dev->dev_addr));
2656 if (mp->tx_desc_sram_size > 0)
2657 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2667 static int mv643xx_eth_remove(struct platform_device *pdev)
2669 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2671 unregister_netdev(mp->dev);
2672 if (mp->phy != NULL)
2673 phy_detach(mp->phy);
2674 flush_scheduled_work();
2675 free_netdev(mp->dev);
2677 platform_set_drvdata(pdev, NULL);
2682 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2684 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2686 /* Mask all interrupts on ethernet port */
2687 wrl(mp, INT_MASK(mp->port_num), 0);
2688 rdl(mp, INT_MASK(mp->port_num));
2690 if (netif_running(mp->dev))
2694 static struct platform_driver mv643xx_eth_driver = {
2695 .probe = mv643xx_eth_probe,
2696 .remove = mv643xx_eth_remove,
2697 .shutdown = mv643xx_eth_shutdown,
2699 .name = MV643XX_ETH_NAME,
2700 .owner = THIS_MODULE,
2704 static int __init mv643xx_eth_init_module(void)
2708 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2710 rc = platform_driver_register(&mv643xx_eth_driver);
2712 platform_driver_unregister(&mv643xx_eth_shared_driver);
2717 module_init(mv643xx_eth_init_module);
2719 static void __exit mv643xx_eth_cleanup_module(void)
2721 platform_driver_unregister(&mv643xx_eth_driver);
2722 platform_driver_unregister(&mv643xx_eth_shared_driver);
2724 module_exit(mv643xx_eth_cleanup_module);
2726 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2727 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2728 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2729 MODULE_LICENSE("GPL");
2730 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2731 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);