2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
55 #include <linux/types.h>
56 #include <linux/inet_lro.h>
57 #include <asm/system.h>
59 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
60 static char mv643xx_eth_driver_version[] = "1.4";
64 * Registers shared between all ports.
66 #define PHY_ADDR 0x0000
67 #define SMI_REG 0x0004
68 #define SMI_BUSY 0x10000000
69 #define SMI_READ_VALID 0x08000000
70 #define SMI_OPCODE_READ 0x04000000
71 #define SMI_OPCODE_WRITE 0x00000000
72 #define ERR_INT_CAUSE 0x0080
73 #define ERR_INT_SMI_DONE 0x00000010
74 #define ERR_INT_MASK 0x0084
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 #define PORT_CONFIG 0x0000
86 #define UNICAST_PROMISCUOUS_MODE 0x00000001
87 #define PORT_CONFIG_EXT 0x0004
88 #define MAC_ADDR_LOW 0x0014
89 #define MAC_ADDR_HIGH 0x0018
90 #define SDMA_CONFIG 0x001c
91 #define TX_BURST_SIZE_16_64BIT 0x01000000
92 #define TX_BURST_SIZE_4_64BIT 0x00800000
93 #define BLM_TX_NO_SWAP 0x00000020
94 #define BLM_RX_NO_SWAP 0x00000010
95 #define RX_BURST_SIZE_16_64BIT 0x00000008
96 #define RX_BURST_SIZE_4_64BIT 0x00000004
97 #define PORT_SERIAL_CONTROL 0x003c
98 #define SET_MII_SPEED_TO_100 0x01000000
99 #define SET_GMII_SPEED_TO_1000 0x00800000
100 #define SET_FULL_DUPLEX_MODE 0x00200000
101 #define MAX_RX_PACKET_9700BYTE 0x000a0000
102 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
103 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
104 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
105 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
106 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
107 #define FORCE_LINK_PASS 0x00000002
108 #define SERIAL_PORT_ENABLE 0x00000001
109 #define PORT_STATUS 0x0044
110 #define TX_FIFO_EMPTY 0x00000400
111 #define TX_IN_PROGRESS 0x00000080
112 #define PORT_SPEED_MASK 0x00000030
113 #define PORT_SPEED_1000 0x00000010
114 #define PORT_SPEED_100 0x00000020
115 #define PORT_SPEED_10 0x00000000
116 #define FLOW_CONTROL_ENABLED 0x00000008
117 #define FULL_DUPLEX 0x00000004
118 #define LINK_UP 0x00000002
119 #define TXQ_COMMAND 0x0048
120 #define TXQ_FIX_PRIO_CONF 0x004c
121 #define TX_BW_RATE 0x0050
122 #define TX_BW_MTU 0x0058
123 #define TX_BW_BURST 0x005c
124 #define INT_CAUSE 0x0060
125 #define INT_TX_END 0x07f80000
126 #define INT_RX 0x000003fc
127 #define INT_EXT 0x00000002
128 #define INT_CAUSE_EXT 0x0064
129 #define INT_EXT_LINK_PHY 0x00110000
130 #define INT_EXT_TX 0x000000ff
131 #define INT_MASK 0x0068
132 #define INT_MASK_EXT 0x006c
133 #define TX_FIFO_URGENT_THRESHOLD 0x0074
134 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
135 #define TX_BW_RATE_MOVED 0x00e0
136 #define TX_BW_MTU_MOVED 0x00e8
137 #define TX_BW_BURST_MOVED 0x00ec
138 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
139 #define RXQ_COMMAND 0x0280
140 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
141 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
142 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
143 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
146 * Misc per-port registers.
148 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
149 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
150 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
151 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
155 * SDMA configuration register default value.
157 #if defined(__BIG_ENDIAN)
158 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
159 (RX_BURST_SIZE_4_64BIT | \
160 TX_BURST_SIZE_4_64BIT)
161 #elif defined(__LITTLE_ENDIAN)
162 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
163 (RX_BURST_SIZE_4_64BIT | \
166 TX_BURST_SIZE_4_64BIT)
168 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
175 #define DEFAULT_RX_QUEUE_SIZE 128
176 #define DEFAULT_TX_QUEUE_SIZE 256
182 #if defined(__BIG_ENDIAN)
184 u16 byte_cnt; /* Descriptor buffer byte count */
185 u16 buf_size; /* Buffer size */
186 u32 cmd_sts; /* Descriptor command status */
187 u32 next_desc_ptr; /* Next descriptor pointer */
188 u32 buf_ptr; /* Descriptor buffer pointer */
192 u16 byte_cnt; /* buffer byte count */
193 u16 l4i_chk; /* CPU provided TCP checksum */
194 u32 cmd_sts; /* Command/status field */
195 u32 next_desc_ptr; /* Pointer to next descriptor */
196 u32 buf_ptr; /* pointer to buffer for this descriptor*/
198 #elif defined(__LITTLE_ENDIAN)
200 u32 cmd_sts; /* Descriptor command status */
201 u16 buf_size; /* Buffer size */
202 u16 byte_cnt; /* Descriptor buffer byte count */
203 u32 buf_ptr; /* Descriptor buffer pointer */
204 u32 next_desc_ptr; /* Next descriptor pointer */
208 u32 cmd_sts; /* Command/status field */
209 u16 l4i_chk; /* CPU provided TCP checksum */
210 u16 byte_cnt; /* buffer byte count */
211 u32 buf_ptr; /* pointer to buffer for this descriptor*/
212 u32 next_desc_ptr; /* Pointer to next descriptor */
215 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
218 /* RX & TX descriptor command */
219 #define BUFFER_OWNED_BY_DMA 0x80000000
221 /* RX & TX descriptor status */
222 #define ERROR_SUMMARY 0x00000001
224 /* RX descriptor status */
225 #define LAYER_4_CHECKSUM_OK 0x40000000
226 #define RX_ENABLE_INTERRUPT 0x20000000
227 #define RX_FIRST_DESC 0x08000000
228 #define RX_LAST_DESC 0x04000000
229 #define RX_IP_HDR_OK 0x02000000
230 #define RX_PKT_IS_IPV4 0x01000000
231 #define RX_PKT_IS_ETHERNETV2 0x00800000
232 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
233 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
234 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
236 /* TX descriptor command */
237 #define TX_ENABLE_INTERRUPT 0x00800000
238 #define GEN_CRC 0x00400000
239 #define TX_FIRST_DESC 0x00200000
240 #define TX_LAST_DESC 0x00100000
241 #define ZERO_PADDING 0x00080000
242 #define GEN_IP_V4_CHECKSUM 0x00040000
243 #define GEN_TCP_UDP_CHECKSUM 0x00020000
244 #define UDP_FRAME 0x00010000
245 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
246 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
248 #define TX_IHL_SHIFT 11
251 /* global *******************************************************************/
252 struct mv643xx_eth_shared_private {
254 * Ethernet controller base address.
259 * Points at the right SMI instance to use.
261 struct mv643xx_eth_shared_private *smi;
264 * Provides access to local SMI interface.
266 struct mii_bus *smi_bus;
269 * If we have access to the error interrupt pin (which is
270 * somewhat misnamed as it not only reflects internal errors
271 * but also reflects SMI completion), use that to wait for
272 * SMI access completion instead of polling the SMI busy bit.
275 wait_queue_head_t smi_busy_wait;
278 * Per-port MBUS window access register value.
283 * Hardware-specific parameters.
286 int extended_rx_coal_limit;
290 #define TX_BW_CONTROL_ABSENT 0
291 #define TX_BW_CONTROL_OLD_LAYOUT 1
292 #define TX_BW_CONTROL_NEW_LAYOUT 2
294 static int mv643xx_eth_open(struct net_device *dev);
295 static int mv643xx_eth_stop(struct net_device *dev);
298 /* per-port *****************************************************************/
299 struct mib_counters {
300 u64 good_octets_received;
301 u32 bad_octets_received;
302 u32 internal_mac_transmit_err;
303 u32 good_frames_received;
304 u32 bad_frames_received;
305 u32 broadcast_frames_received;
306 u32 multicast_frames_received;
307 u32 frames_64_octets;
308 u32 frames_65_to_127_octets;
309 u32 frames_128_to_255_octets;
310 u32 frames_256_to_511_octets;
311 u32 frames_512_to_1023_octets;
312 u32 frames_1024_to_max_octets;
313 u64 good_octets_sent;
314 u32 good_frames_sent;
315 u32 excessive_collision;
316 u32 multicast_frames_sent;
317 u32 broadcast_frames_sent;
318 u32 unrec_mac_control_received;
320 u32 good_fc_received;
322 u32 undersize_received;
323 u32 fragments_received;
324 u32 oversize_received;
326 u32 mac_receive_error;
332 struct lro_counters {
347 struct rx_desc *rx_desc_area;
348 dma_addr_t rx_desc_dma;
349 int rx_desc_area_size;
350 struct sk_buff **rx_skb;
352 struct net_lro_mgr lro_mgr;
353 struct net_lro_desc lro_arr[8];
365 struct tx_desc *tx_desc_area;
366 dma_addr_t tx_desc_dma;
367 int tx_desc_area_size;
369 struct sk_buff_head tx_skb;
371 unsigned long tx_packets;
372 unsigned long tx_bytes;
373 unsigned long tx_dropped;
376 struct mv643xx_eth_private {
377 struct mv643xx_eth_shared_private *shared;
381 struct net_device *dev;
383 struct phy_device *phy;
385 struct timer_list mib_counters_timer;
386 spinlock_t mib_counters_lock;
387 struct mib_counters mib_counters;
389 struct lro_counters lro_counters;
391 struct work_struct tx_timeout_task;
393 struct napi_struct napi;
402 struct sk_buff_head rx_recycle;
408 unsigned long rx_desc_sram_addr;
409 int rx_desc_sram_size;
411 struct timer_list rx_oom;
412 struct rx_queue rxq[8];
418 unsigned long tx_desc_sram_addr;
419 int tx_desc_sram_size;
421 struct tx_queue txq[8];
425 /* port register accessors **************************************************/
426 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
428 return readl(mp->shared->base + offset);
431 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
433 return readl(mp->base + offset);
436 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
438 writel(data, mp->shared->base + offset);
441 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
443 writel(data, mp->base + offset);
447 /* rxq/txq helper functions *************************************************/
448 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
450 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
453 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
455 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
458 static void rxq_enable(struct rx_queue *rxq)
460 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
461 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
464 static void rxq_disable(struct rx_queue *rxq)
466 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
467 u8 mask = 1 << rxq->index;
469 wrlp(mp, RXQ_COMMAND, mask << 8);
470 while (rdlp(mp, RXQ_COMMAND) & mask)
474 static void txq_reset_hw_ptr(struct tx_queue *txq)
476 struct mv643xx_eth_private *mp = txq_to_mp(txq);
479 addr = (u32)txq->tx_desc_dma;
480 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
481 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
484 static void txq_enable(struct tx_queue *txq)
486 struct mv643xx_eth_private *mp = txq_to_mp(txq);
487 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
490 static void txq_disable(struct tx_queue *txq)
492 struct mv643xx_eth_private *mp = txq_to_mp(txq);
493 u8 mask = 1 << txq->index;
495 wrlp(mp, TXQ_COMMAND, mask << 8);
496 while (rdlp(mp, TXQ_COMMAND) & mask)
500 static void txq_maybe_wake(struct tx_queue *txq)
502 struct mv643xx_eth_private *mp = txq_to_mp(txq);
503 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
505 if (netif_tx_queue_stopped(nq)) {
506 __netif_tx_lock(nq, smp_processor_id());
507 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
508 netif_tx_wake_queue(nq);
509 __netif_tx_unlock(nq);
514 /* rx napi ******************************************************************/
516 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
517 u64 *hdr_flags, void *priv)
519 unsigned long cmd_sts = (unsigned long)priv;
522 * Make sure that this packet is Ethernet II, is not VLAN
523 * tagged, is IPv4, has a valid IP header, and is TCP.
525 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
526 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
527 RX_PKT_IS_VLAN_TAGGED)) !=
528 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
529 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
532 skb_reset_network_header(skb);
533 skb_set_transport_header(skb, ip_hdrlen(skb));
534 *iphdr = ip_hdr(skb);
535 *tcph = tcp_hdr(skb);
536 *hdr_flags = LRO_IPV4 | LRO_TCP;
541 static int rxq_process(struct rx_queue *rxq, int budget)
543 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
544 struct net_device_stats *stats = &mp->dev->stats;
545 int lro_flush_needed;
548 lro_flush_needed = 0;
550 while (rx < budget && rxq->rx_desc_count) {
551 struct rx_desc *rx_desc;
552 unsigned int cmd_sts;
556 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
558 cmd_sts = rx_desc->cmd_sts;
559 if (cmd_sts & BUFFER_OWNED_BY_DMA)
563 skb = rxq->rx_skb[rxq->rx_curr_desc];
564 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
567 if (rxq->rx_curr_desc == rxq->rx_ring_size)
568 rxq->rx_curr_desc = 0;
570 dma_unmap_single(NULL, rx_desc->buf_ptr,
571 rx_desc->buf_size, DMA_FROM_DEVICE);
572 rxq->rx_desc_count--;
575 mp->work_rx_refill |= 1 << rxq->index;
577 byte_cnt = rx_desc->byte_cnt;
582 * Note that the descriptor byte count includes 2 dummy
583 * bytes automatically inserted by the hardware at the
584 * start of the packet (which we don't count), and a 4
585 * byte CRC at the end of the packet (which we do count).
588 stats->rx_bytes += byte_cnt - 2;
591 * In case we received a packet without first / last bits
592 * on, or the error summary bit is set, the packet needs
595 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
596 != (RX_FIRST_DESC | RX_LAST_DESC))
600 * The -4 is for the CRC in the trailer of the
603 skb_put(skb, byte_cnt - 2 - 4);
605 if (cmd_sts & LAYER_4_CHECKSUM_OK)
606 skb->ip_summed = CHECKSUM_UNNECESSARY;
607 skb->protocol = eth_type_trans(skb, mp->dev);
609 if (skb->dev->features & NETIF_F_LRO &&
610 skb->ip_summed == CHECKSUM_UNNECESSARY) {
611 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
612 lro_flush_needed = 1;
614 netif_receive_skb(skb);
621 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
622 (RX_FIRST_DESC | RX_LAST_DESC)) {
624 dev_printk(KERN_ERR, &mp->dev->dev,
625 "received packet spanning "
626 "multiple descriptors\n");
629 if (cmd_sts & ERROR_SUMMARY)
635 if (lro_flush_needed)
636 lro_flush_all(&rxq->lro_mgr);
639 mp->work_rx &= ~(1 << rxq->index);
644 static int rxq_refill(struct rx_queue *rxq, int budget)
646 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
650 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
654 struct rx_desc *rx_desc;
656 skb = __skb_dequeue(&mp->rx_recycle);
658 skb = dev_alloc_skb(mp->skb_size +
659 dma_get_cache_alignment() - 1);
666 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
668 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
671 rxq->rx_desc_count++;
673 rx = rxq->rx_used_desc++;
674 if (rxq->rx_used_desc == rxq->rx_ring_size)
675 rxq->rx_used_desc = 0;
677 rx_desc = rxq->rx_desc_area + rx;
679 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
680 mp->skb_size, DMA_FROM_DEVICE);
681 rx_desc->buf_size = mp->skb_size;
682 rxq->rx_skb[rx] = skb;
684 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
688 * The hardware automatically prepends 2 bytes of
689 * dummy data to each received packet, so that the
690 * IP header ends up 16-byte aligned.
695 if (refilled < budget)
696 mp->work_rx_refill &= ~(1 << rxq->index);
703 /* tx ***********************************************************************/
704 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
708 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
709 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
710 if (fragp->size <= 8 && fragp->page_offset & 7)
717 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
719 int nr_frags = skb_shinfo(skb)->nr_frags;
722 for (frag = 0; frag < nr_frags; frag++) {
723 skb_frag_t *this_frag;
725 struct tx_desc *desc;
727 this_frag = &skb_shinfo(skb)->frags[frag];
728 tx_index = txq->tx_curr_desc++;
729 if (txq->tx_curr_desc == txq->tx_ring_size)
730 txq->tx_curr_desc = 0;
731 desc = &txq->tx_desc_area[tx_index];
734 * The last fragment will generate an interrupt
735 * which will free the skb on TX completion.
737 if (frag == nr_frags - 1) {
738 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
739 ZERO_PADDING | TX_LAST_DESC |
742 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
746 desc->byte_cnt = this_frag->size;
747 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
748 this_frag->page_offset,
754 static inline __be16 sum16_as_be(__sum16 sum)
756 return (__force __be16)sum;
759 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
761 struct mv643xx_eth_private *mp = txq_to_mp(txq);
762 int nr_frags = skb_shinfo(skb)->nr_frags;
764 struct tx_desc *desc;
769 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
772 if (skb->ip_summed == CHECKSUM_PARTIAL) {
775 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
776 skb->protocol != htons(ETH_P_8021Q));
778 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
779 if (unlikely(tag_bytes & ~12)) {
780 if (skb_checksum_help(skb) == 0)
787 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
789 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
791 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
793 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
795 switch (ip_hdr(skb)->protocol) {
797 cmd_sts |= UDP_FRAME;
798 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
801 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
808 /* Errata BTS #50, IHL must be 5 if no HW checksum */
809 cmd_sts |= 5 << TX_IHL_SHIFT;
812 tx_index = txq->tx_curr_desc++;
813 if (txq->tx_curr_desc == txq->tx_ring_size)
814 txq->tx_curr_desc = 0;
815 desc = &txq->tx_desc_area[tx_index];
818 txq_submit_frag_skb(txq, skb);
819 length = skb_headlen(skb);
821 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
825 desc->l4i_chk = l4i_chk;
826 desc->byte_cnt = length;
827 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
829 __skb_queue_tail(&txq->tx_skb, skb);
831 /* ensure all other descriptors are written before first cmd_sts */
833 desc->cmd_sts = cmd_sts;
835 /* clear TX_END status */
836 mp->work_tx_end &= ~(1 << txq->index);
838 /* ensure all descriptors are written before poking hardware */
842 txq->tx_desc_count += nr_frags + 1;
847 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
849 struct mv643xx_eth_private *mp = netdev_priv(dev);
851 struct tx_queue *txq;
852 struct netdev_queue *nq;
854 queue = skb_get_queue_mapping(skb);
855 txq = mp->txq + queue;
856 nq = netdev_get_tx_queue(dev, queue);
858 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
860 dev_printk(KERN_DEBUG, &dev->dev,
861 "failed to linearize skb with tiny "
862 "unaligned fragment\n");
863 return NETDEV_TX_BUSY;
866 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
868 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
873 if (!txq_submit_skb(txq, skb)) {
876 txq->tx_bytes += skb->len;
878 dev->trans_start = jiffies;
880 entries_left = txq->tx_ring_size - txq->tx_desc_count;
881 if (entries_left < MAX_SKB_FRAGS + 1)
882 netif_tx_stop_queue(nq);
889 /* tx napi ******************************************************************/
890 static void txq_kick(struct tx_queue *txq)
892 struct mv643xx_eth_private *mp = txq_to_mp(txq);
893 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
897 __netif_tx_lock(nq, smp_processor_id());
899 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
902 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
903 expected_ptr = (u32)txq->tx_desc_dma +
904 txq->tx_curr_desc * sizeof(struct tx_desc);
906 if (hw_desc_ptr != expected_ptr)
910 __netif_tx_unlock(nq);
912 mp->work_tx_end &= ~(1 << txq->index);
915 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
917 struct mv643xx_eth_private *mp = txq_to_mp(txq);
918 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
921 __netif_tx_lock(nq, smp_processor_id());
924 while (reclaimed < budget && txq->tx_desc_count > 0) {
926 struct tx_desc *desc;
930 tx_index = txq->tx_used_desc;
931 desc = &txq->tx_desc_area[tx_index];
932 cmd_sts = desc->cmd_sts;
934 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
937 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
940 txq->tx_used_desc = tx_index + 1;
941 if (txq->tx_used_desc == txq->tx_ring_size)
942 txq->tx_used_desc = 0;
945 txq->tx_desc_count--;
948 if (cmd_sts & TX_LAST_DESC)
949 skb = __skb_dequeue(&txq->tx_skb);
951 if (cmd_sts & ERROR_SUMMARY) {
952 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
953 mp->dev->stats.tx_errors++;
956 if (cmd_sts & TX_FIRST_DESC) {
957 dma_unmap_single(NULL, desc->buf_ptr,
958 desc->byte_cnt, DMA_TO_DEVICE);
960 dma_unmap_page(NULL, desc->buf_ptr,
961 desc->byte_cnt, DMA_TO_DEVICE);
965 if (skb_queue_len(&mp->rx_recycle) <
967 skb_recycle_check(skb, mp->skb_size +
968 dma_get_cache_alignment() - 1))
969 __skb_queue_head(&mp->rx_recycle, skb);
975 __netif_tx_unlock(nq);
977 if (reclaimed < budget)
978 mp->work_tx &= ~(1 << txq->index);
984 /* tx rate control **********************************************************/
986 * Set total maximum TX rate (shared by all TX queues for this port)
987 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
989 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
995 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
996 if (token_rate > 1023)
999 mtu = (mp->dev->mtu + 255) >> 8;
1003 bucket_size = (burst + 255) >> 8;
1004 if (bucket_size > 65535)
1005 bucket_size = 65535;
1007 switch (mp->shared->tx_bw_control) {
1008 case TX_BW_CONTROL_OLD_LAYOUT:
1009 wrlp(mp, TX_BW_RATE, token_rate);
1010 wrlp(mp, TX_BW_MTU, mtu);
1011 wrlp(mp, TX_BW_BURST, bucket_size);
1013 case TX_BW_CONTROL_NEW_LAYOUT:
1014 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1015 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1016 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1021 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1023 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1027 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1028 if (token_rate > 1023)
1031 bucket_size = (burst + 255) >> 8;
1032 if (bucket_size > 65535)
1033 bucket_size = 65535;
1035 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1036 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1039 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1041 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1046 * Turn on fixed priority mode.
1049 switch (mp->shared->tx_bw_control) {
1050 case TX_BW_CONTROL_OLD_LAYOUT:
1051 off = TXQ_FIX_PRIO_CONF;
1053 case TX_BW_CONTROL_NEW_LAYOUT:
1054 off = TXQ_FIX_PRIO_CONF_MOVED;
1059 val = rdlp(mp, off);
1060 val |= 1 << txq->index;
1065 static void txq_set_wrr(struct tx_queue *txq, int weight)
1067 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1072 * Turn off fixed priority mode.
1075 switch (mp->shared->tx_bw_control) {
1076 case TX_BW_CONTROL_OLD_LAYOUT:
1077 off = TXQ_FIX_PRIO_CONF;
1079 case TX_BW_CONTROL_NEW_LAYOUT:
1080 off = TXQ_FIX_PRIO_CONF_MOVED;
1085 val = rdlp(mp, off);
1086 val &= ~(1 << txq->index);
1090 * Configure WRR weight for this queue.
1093 val = rdlp(mp, off);
1094 val = (val & ~0xff) | (weight & 0xff);
1095 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
1100 /* mii management interface *************************************************/
1101 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1103 struct mv643xx_eth_shared_private *msp = dev_id;
1105 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1106 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1107 wake_up(&msp->smi_busy_wait);
1114 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1116 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1119 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1121 if (msp->err_interrupt == NO_IRQ) {
1124 for (i = 0; !smi_is_done(msp); i++) {
1133 if (!smi_is_done(msp)) {
1134 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1135 msecs_to_jiffies(100));
1136 if (!smi_is_done(msp))
1143 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1145 struct mv643xx_eth_shared_private *msp = bus->priv;
1146 void __iomem *smi_reg = msp->base + SMI_REG;
1149 if (smi_wait_ready(msp)) {
1150 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1154 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1156 if (smi_wait_ready(msp)) {
1157 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1161 ret = readl(smi_reg);
1162 if (!(ret & SMI_READ_VALID)) {
1163 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1167 return ret & 0xffff;
1170 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1172 struct mv643xx_eth_shared_private *msp = bus->priv;
1173 void __iomem *smi_reg = msp->base + SMI_REG;
1175 if (smi_wait_ready(msp)) {
1176 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1180 writel(SMI_OPCODE_WRITE | (reg << 21) |
1181 (addr << 16) | (val & 0xffff), smi_reg);
1183 if (smi_wait_ready(msp)) {
1184 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1192 /* statistics ***************************************************************/
1193 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1195 struct mv643xx_eth_private *mp = netdev_priv(dev);
1196 struct net_device_stats *stats = &dev->stats;
1197 unsigned long tx_packets = 0;
1198 unsigned long tx_bytes = 0;
1199 unsigned long tx_dropped = 0;
1202 for (i = 0; i < mp->txq_count; i++) {
1203 struct tx_queue *txq = mp->txq + i;
1205 tx_packets += txq->tx_packets;
1206 tx_bytes += txq->tx_bytes;
1207 tx_dropped += txq->tx_dropped;
1210 stats->tx_packets = tx_packets;
1211 stats->tx_bytes = tx_bytes;
1212 stats->tx_dropped = tx_dropped;
1217 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1219 u32 lro_aggregated = 0;
1220 u32 lro_flushed = 0;
1221 u32 lro_no_desc = 0;
1224 for (i = 0; i < mp->rxq_count; i++) {
1225 struct rx_queue *rxq = mp->rxq + i;
1227 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1228 lro_flushed += rxq->lro_mgr.stats.flushed;
1229 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1232 mp->lro_counters.lro_aggregated = lro_aggregated;
1233 mp->lro_counters.lro_flushed = lro_flushed;
1234 mp->lro_counters.lro_no_desc = lro_no_desc;
1237 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1239 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1242 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1246 for (i = 0; i < 0x80; i += 4)
1250 static void mib_counters_update(struct mv643xx_eth_private *mp)
1252 struct mib_counters *p = &mp->mib_counters;
1254 spin_lock_bh(&mp->mib_counters_lock);
1255 p->good_octets_received += mib_read(mp, 0x00);
1256 p->bad_octets_received += mib_read(mp, 0x08);
1257 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1258 p->good_frames_received += mib_read(mp, 0x10);
1259 p->bad_frames_received += mib_read(mp, 0x14);
1260 p->broadcast_frames_received += mib_read(mp, 0x18);
1261 p->multicast_frames_received += mib_read(mp, 0x1c);
1262 p->frames_64_octets += mib_read(mp, 0x20);
1263 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1264 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1265 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1266 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1267 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1268 p->good_octets_sent += mib_read(mp, 0x38);
1269 p->good_frames_sent += mib_read(mp, 0x40);
1270 p->excessive_collision += mib_read(mp, 0x44);
1271 p->multicast_frames_sent += mib_read(mp, 0x48);
1272 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1273 p->unrec_mac_control_received += mib_read(mp, 0x50);
1274 p->fc_sent += mib_read(mp, 0x54);
1275 p->good_fc_received += mib_read(mp, 0x58);
1276 p->bad_fc_received += mib_read(mp, 0x5c);
1277 p->undersize_received += mib_read(mp, 0x60);
1278 p->fragments_received += mib_read(mp, 0x64);
1279 p->oversize_received += mib_read(mp, 0x68);
1280 p->jabber_received += mib_read(mp, 0x6c);
1281 p->mac_receive_error += mib_read(mp, 0x70);
1282 p->bad_crc_event += mib_read(mp, 0x74);
1283 p->collision += mib_read(mp, 0x78);
1284 p->late_collision += mib_read(mp, 0x7c);
1285 spin_unlock_bh(&mp->mib_counters_lock);
1287 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1290 static void mib_counters_timer_wrapper(unsigned long _mp)
1292 struct mv643xx_eth_private *mp = (void *)_mp;
1294 mib_counters_update(mp);
1298 /* interrupt coalescing *****************************************************/
1300 * Hardware coalescing parameters are set in units of 64 t_clk
1303 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1305 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1307 * In the ->set*() methods, we round the computed register value
1308 * to the nearest integer.
1310 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1312 u32 val = rdlp(mp, SDMA_CONFIG);
1315 if (mp->shared->extended_rx_coal_limit)
1316 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1318 temp = (val & 0x003fff00) >> 8;
1321 do_div(temp, mp->shared->t_clk);
1323 return (unsigned int)temp;
1326 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1331 temp = (u64)usec * mp->shared->t_clk;
1333 do_div(temp, 64000000);
1335 val = rdlp(mp, SDMA_CONFIG);
1336 if (mp->shared->extended_rx_coal_limit) {
1340 val |= (temp & 0x8000) << 10;
1341 val |= (temp & 0x7fff) << 7;
1346 val |= (temp & 0x3fff) << 8;
1348 wrlp(mp, SDMA_CONFIG, val);
1351 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1355 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1357 do_div(temp, mp->shared->t_clk);
1359 return (unsigned int)temp;
1362 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1366 temp = (u64)usec * mp->shared->t_clk;
1368 do_div(temp, 64000000);
1373 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1377 /* ethtool ******************************************************************/
1378 struct mv643xx_eth_stats {
1379 char stat_string[ETH_GSTRING_LEN];
1386 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1387 offsetof(struct net_device, stats.m), -1 }
1389 #define MIBSTAT(m) \
1390 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1391 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1393 #define LROSTAT(m) \
1394 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1395 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1397 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1406 MIBSTAT(good_octets_received),
1407 MIBSTAT(bad_octets_received),
1408 MIBSTAT(internal_mac_transmit_err),
1409 MIBSTAT(good_frames_received),
1410 MIBSTAT(bad_frames_received),
1411 MIBSTAT(broadcast_frames_received),
1412 MIBSTAT(multicast_frames_received),
1413 MIBSTAT(frames_64_octets),
1414 MIBSTAT(frames_65_to_127_octets),
1415 MIBSTAT(frames_128_to_255_octets),
1416 MIBSTAT(frames_256_to_511_octets),
1417 MIBSTAT(frames_512_to_1023_octets),
1418 MIBSTAT(frames_1024_to_max_octets),
1419 MIBSTAT(good_octets_sent),
1420 MIBSTAT(good_frames_sent),
1421 MIBSTAT(excessive_collision),
1422 MIBSTAT(multicast_frames_sent),
1423 MIBSTAT(broadcast_frames_sent),
1424 MIBSTAT(unrec_mac_control_received),
1426 MIBSTAT(good_fc_received),
1427 MIBSTAT(bad_fc_received),
1428 MIBSTAT(undersize_received),
1429 MIBSTAT(fragments_received),
1430 MIBSTAT(oversize_received),
1431 MIBSTAT(jabber_received),
1432 MIBSTAT(mac_receive_error),
1433 MIBSTAT(bad_crc_event),
1435 MIBSTAT(late_collision),
1436 LROSTAT(lro_aggregated),
1437 LROSTAT(lro_flushed),
1438 LROSTAT(lro_no_desc),
1442 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1443 struct ethtool_cmd *cmd)
1447 err = phy_read_status(mp->phy);
1449 err = phy_ethtool_gset(mp->phy, cmd);
1452 * The MAC does not support 1000baseT_Half.
1454 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1455 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1461 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1462 struct ethtool_cmd *cmd)
1466 port_status = rdlp(mp, PORT_STATUS);
1468 cmd->supported = SUPPORTED_MII;
1469 cmd->advertising = ADVERTISED_MII;
1470 switch (port_status & PORT_SPEED_MASK) {
1472 cmd->speed = SPEED_10;
1474 case PORT_SPEED_100:
1475 cmd->speed = SPEED_100;
1477 case PORT_SPEED_1000:
1478 cmd->speed = SPEED_1000;
1484 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1485 cmd->port = PORT_MII;
1486 cmd->phy_address = 0;
1487 cmd->transceiver = XCVR_INTERNAL;
1488 cmd->autoneg = AUTONEG_DISABLE;
1496 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1498 struct mv643xx_eth_private *mp = netdev_priv(dev);
1500 if (mp->phy != NULL)
1501 return mv643xx_eth_get_settings_phy(mp, cmd);
1503 return mv643xx_eth_get_settings_phyless(mp, cmd);
1507 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1509 struct mv643xx_eth_private *mp = netdev_priv(dev);
1511 if (mp->phy == NULL)
1515 * The MAC does not support 1000baseT_Half.
1517 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1519 return phy_ethtool_sset(mp->phy, cmd);
1522 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1523 struct ethtool_drvinfo *drvinfo)
1525 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1526 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1527 strncpy(drvinfo->fw_version, "N/A", 32);
1528 strncpy(drvinfo->bus_info, "platform", 32);
1529 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1532 static int mv643xx_eth_nway_reset(struct net_device *dev)
1534 struct mv643xx_eth_private *mp = netdev_priv(dev);
1536 if (mp->phy == NULL)
1539 return genphy_restart_aneg(mp->phy);
1542 static u32 mv643xx_eth_get_link(struct net_device *dev)
1544 return !!netif_carrier_ok(dev);
1548 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1550 struct mv643xx_eth_private *mp = netdev_priv(dev);
1552 ec->rx_coalesce_usecs = get_rx_coal(mp);
1553 ec->tx_coalesce_usecs = get_tx_coal(mp);
1559 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1561 struct mv643xx_eth_private *mp = netdev_priv(dev);
1563 set_rx_coal(mp, ec->rx_coalesce_usecs);
1564 set_tx_coal(mp, ec->tx_coalesce_usecs);
1570 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1572 struct mv643xx_eth_private *mp = netdev_priv(dev);
1574 er->rx_max_pending = 4096;
1575 er->tx_max_pending = 4096;
1576 er->rx_mini_max_pending = 0;
1577 er->rx_jumbo_max_pending = 0;
1579 er->rx_pending = mp->rx_ring_size;
1580 er->tx_pending = mp->tx_ring_size;
1581 er->rx_mini_pending = 0;
1582 er->rx_jumbo_pending = 0;
1586 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1588 struct mv643xx_eth_private *mp = netdev_priv(dev);
1590 if (er->rx_mini_pending || er->rx_jumbo_pending)
1593 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1594 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1596 if (netif_running(dev)) {
1597 mv643xx_eth_stop(dev);
1598 if (mv643xx_eth_open(dev)) {
1599 dev_printk(KERN_ERR, &dev->dev,
1600 "fatal error on re-opening device after "
1601 "ring param change\n");
1610 mv643xx_eth_get_rx_csum(struct net_device *dev)
1612 struct mv643xx_eth_private *mp = netdev_priv(dev);
1614 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1618 mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1620 struct mv643xx_eth_private *mp = netdev_priv(dev);
1622 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1627 static void mv643xx_eth_get_strings(struct net_device *dev,
1628 uint32_t stringset, uint8_t *data)
1632 if (stringset == ETH_SS_STATS) {
1633 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1634 memcpy(data + i * ETH_GSTRING_LEN,
1635 mv643xx_eth_stats[i].stat_string,
1641 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1642 struct ethtool_stats *stats,
1645 struct mv643xx_eth_private *mp = netdev_priv(dev);
1648 mv643xx_eth_get_stats(dev);
1649 mib_counters_update(mp);
1650 mv643xx_eth_grab_lro_stats(mp);
1652 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1653 const struct mv643xx_eth_stats *stat;
1656 stat = mv643xx_eth_stats + i;
1658 if (stat->netdev_off >= 0)
1659 p = ((void *)mp->dev) + stat->netdev_off;
1661 p = ((void *)mp) + stat->mp_off;
1663 data[i] = (stat->sizeof_stat == 8) ?
1664 *(uint64_t *)p : *(uint32_t *)p;
1668 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1670 if (sset == ETH_SS_STATS)
1671 return ARRAY_SIZE(mv643xx_eth_stats);
1676 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1677 .get_settings = mv643xx_eth_get_settings,
1678 .set_settings = mv643xx_eth_set_settings,
1679 .get_drvinfo = mv643xx_eth_get_drvinfo,
1680 .nway_reset = mv643xx_eth_nway_reset,
1681 .get_link = mv643xx_eth_get_link,
1682 .get_coalesce = mv643xx_eth_get_coalesce,
1683 .set_coalesce = mv643xx_eth_set_coalesce,
1684 .get_ringparam = mv643xx_eth_get_ringparam,
1685 .set_ringparam = mv643xx_eth_set_ringparam,
1686 .get_rx_csum = mv643xx_eth_get_rx_csum,
1687 .set_rx_csum = mv643xx_eth_set_rx_csum,
1688 .set_tx_csum = ethtool_op_set_tx_csum,
1689 .set_sg = ethtool_op_set_sg,
1690 .get_strings = mv643xx_eth_get_strings,
1691 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1692 .get_flags = ethtool_op_get_flags,
1693 .set_flags = ethtool_op_set_flags,
1694 .get_sset_count = mv643xx_eth_get_sset_count,
1698 /* address handling *********************************************************/
1699 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1701 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1702 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1704 addr[0] = (mac_h >> 24) & 0xff;
1705 addr[1] = (mac_h >> 16) & 0xff;
1706 addr[2] = (mac_h >> 8) & 0xff;
1707 addr[3] = mac_h & 0xff;
1708 addr[4] = (mac_l >> 8) & 0xff;
1709 addr[5] = mac_l & 0xff;
1712 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1714 wrlp(mp, MAC_ADDR_HIGH,
1715 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1716 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1719 static u32 uc_addr_filter_mask(struct net_device *dev)
1721 struct dev_addr_list *uc_ptr;
1724 if (dev->flags & IFF_PROMISC)
1727 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1728 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1729 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1731 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1734 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1740 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1742 struct mv643xx_eth_private *mp = netdev_priv(dev);
1747 uc_addr_set(mp, dev->dev_addr);
1749 port_config = rdlp(mp, PORT_CONFIG);
1750 nibbles = uc_addr_filter_mask(dev);
1752 port_config |= UNICAST_PROMISCUOUS_MODE;
1753 wrlp(mp, PORT_CONFIG, port_config);
1757 for (i = 0; i < 16; i += 4) {
1758 int off = UNICAST_TABLE(mp->port_num) + i;
1775 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1776 wrlp(mp, PORT_CONFIG, port_config);
1779 static int addr_crc(unsigned char *addr)
1784 for (i = 0; i < 6; i++) {
1787 crc = (crc ^ addr[i]) << 8;
1788 for (j = 7; j >= 0; j--) {
1789 if (crc & (0x100 << j))
1797 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1799 struct mv643xx_eth_private *mp = netdev_priv(dev);
1802 struct dev_addr_list *addr;
1805 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1810 port_num = mp->port_num;
1811 accept = 0x01010101;
1812 for (i = 0; i < 0x100; i += 4) {
1813 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1814 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1819 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1820 if (mc_spec == NULL)
1822 mc_other = mc_spec + (0x100 >> 2);
1824 memset(mc_spec, 0, 0x100);
1825 memset(mc_other, 0, 0x100);
1827 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1828 u8 *a = addr->da_addr;
1832 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1837 entry = addr_crc(a);
1840 table[entry >> 2] |= 1 << (8 * (entry & 3));
1843 for (i = 0; i < 0x100; i += 4) {
1844 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1845 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1851 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1853 mv643xx_eth_program_unicast_filter(dev);
1854 mv643xx_eth_program_multicast_filter(dev);
1857 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1859 struct sockaddr *sa = addr;
1861 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1863 netif_addr_lock_bh(dev);
1864 mv643xx_eth_program_unicast_filter(dev);
1865 netif_addr_unlock_bh(dev);
1871 /* rx/tx queue initialisation ***********************************************/
1872 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1874 struct rx_queue *rxq = mp->rxq + index;
1875 struct rx_desc *rx_desc;
1881 rxq->rx_ring_size = mp->rx_ring_size;
1883 rxq->rx_desc_count = 0;
1884 rxq->rx_curr_desc = 0;
1885 rxq->rx_used_desc = 0;
1887 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1889 if (index == 0 && size <= mp->rx_desc_sram_size) {
1890 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1891 mp->rx_desc_sram_size);
1892 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1894 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1899 if (rxq->rx_desc_area == NULL) {
1900 dev_printk(KERN_ERR, &mp->dev->dev,
1901 "can't allocate rx ring (%d bytes)\n", size);
1904 memset(rxq->rx_desc_area, 0, size);
1906 rxq->rx_desc_area_size = size;
1907 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1909 if (rxq->rx_skb == NULL) {
1910 dev_printk(KERN_ERR, &mp->dev->dev,
1911 "can't allocate rx skb ring\n");
1915 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1916 for (i = 0; i < rxq->rx_ring_size; i++) {
1920 if (nexti == rxq->rx_ring_size)
1923 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1924 nexti * sizeof(struct rx_desc);
1927 rxq->lro_mgr.dev = mp->dev;
1928 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1929 rxq->lro_mgr.features = LRO_F_NAPI;
1930 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1931 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1932 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1933 rxq->lro_mgr.max_aggr = 32;
1934 rxq->lro_mgr.frag_align_pad = 0;
1935 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1936 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1938 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1944 if (index == 0 && size <= mp->rx_desc_sram_size)
1945 iounmap(rxq->rx_desc_area);
1947 dma_free_coherent(NULL, size,
1955 static void rxq_deinit(struct rx_queue *rxq)
1957 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1962 for (i = 0; i < rxq->rx_ring_size; i++) {
1963 if (rxq->rx_skb[i]) {
1964 dev_kfree_skb(rxq->rx_skb[i]);
1965 rxq->rx_desc_count--;
1969 if (rxq->rx_desc_count) {
1970 dev_printk(KERN_ERR, &mp->dev->dev,
1971 "error freeing rx ring -- %d skbs stuck\n",
1972 rxq->rx_desc_count);
1975 if (rxq->index == 0 &&
1976 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1977 iounmap(rxq->rx_desc_area);
1979 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1980 rxq->rx_desc_area, rxq->rx_desc_dma);
1985 static int txq_init(struct mv643xx_eth_private *mp, int index)
1987 struct tx_queue *txq = mp->txq + index;
1988 struct tx_desc *tx_desc;
1994 txq->tx_ring_size = mp->tx_ring_size;
1996 txq->tx_desc_count = 0;
1997 txq->tx_curr_desc = 0;
1998 txq->tx_used_desc = 0;
2000 size = txq->tx_ring_size * sizeof(struct tx_desc);
2002 if (index == 0 && size <= mp->tx_desc_sram_size) {
2003 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2004 mp->tx_desc_sram_size);
2005 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2007 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
2012 if (txq->tx_desc_area == NULL) {
2013 dev_printk(KERN_ERR, &mp->dev->dev,
2014 "can't allocate tx ring (%d bytes)\n", size);
2017 memset(txq->tx_desc_area, 0, size);
2019 txq->tx_desc_area_size = size;
2021 tx_desc = (struct tx_desc *)txq->tx_desc_area;
2022 for (i = 0; i < txq->tx_ring_size; i++) {
2023 struct tx_desc *txd = tx_desc + i;
2027 if (nexti == txq->tx_ring_size)
2031 txd->next_desc_ptr = txq->tx_desc_dma +
2032 nexti * sizeof(struct tx_desc);
2035 skb_queue_head_init(&txq->tx_skb);
2040 static void txq_deinit(struct tx_queue *txq)
2042 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2045 txq_reclaim(txq, txq->tx_ring_size, 1);
2047 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2049 if (txq->index == 0 &&
2050 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2051 iounmap(txq->tx_desc_area);
2053 dma_free_coherent(NULL, txq->tx_desc_area_size,
2054 txq->tx_desc_area, txq->tx_desc_dma);
2058 /* netdev ops and related ***************************************************/
2059 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2064 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
2069 if (int_cause & INT_EXT)
2070 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2072 int_cause &= INT_TX_END | INT_RX;
2074 wrlp(mp, INT_CAUSE, ~int_cause);
2075 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2076 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2077 mp->work_rx |= (int_cause & INT_RX) >> 2;
2080 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2081 if (int_cause_ext) {
2082 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2083 if (int_cause_ext & INT_EXT_LINK_PHY)
2085 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2091 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2093 struct net_device *dev = (struct net_device *)dev_id;
2094 struct mv643xx_eth_private *mp = netdev_priv(dev);
2096 if (unlikely(!mv643xx_eth_collect_events(mp)))
2099 wrlp(mp, INT_MASK, 0);
2100 napi_schedule(&mp->napi);
2105 static void handle_link_event(struct mv643xx_eth_private *mp)
2107 struct net_device *dev = mp->dev;
2113 port_status = rdlp(mp, PORT_STATUS);
2114 if (!(port_status & LINK_UP)) {
2115 if (netif_carrier_ok(dev)) {
2118 printk(KERN_INFO "%s: link down\n", dev->name);
2120 netif_carrier_off(dev);
2122 for (i = 0; i < mp->txq_count; i++) {
2123 struct tx_queue *txq = mp->txq + i;
2125 txq_reclaim(txq, txq->tx_ring_size, 1);
2126 txq_reset_hw_ptr(txq);
2132 switch (port_status & PORT_SPEED_MASK) {
2136 case PORT_SPEED_100:
2139 case PORT_SPEED_1000:
2146 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2147 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2149 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2150 "flow control %sabled\n", dev->name,
2151 speed, duplex ? "full" : "half",
2154 if (!netif_carrier_ok(dev))
2155 netif_carrier_on(dev);
2158 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2160 struct mv643xx_eth_private *mp;
2163 mp = container_of(napi, struct mv643xx_eth_private, napi);
2165 if (unlikely(mp->oom)) {
2167 del_timer(&mp->rx_oom);
2171 while (work_done < budget) {
2176 if (mp->work_link) {
2178 handle_link_event(mp);
2183 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2184 if (likely(!mp->oom))
2185 queue_mask |= mp->work_rx_refill;
2188 if (mv643xx_eth_collect_events(mp))
2193 queue = fls(queue_mask) - 1;
2194 queue_mask = 1 << queue;
2196 work_tbd = budget - work_done;
2200 if (mp->work_tx_end & queue_mask) {
2201 txq_kick(mp->txq + queue);
2202 } else if (mp->work_tx & queue_mask) {
2203 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2204 txq_maybe_wake(mp->txq + queue);
2205 } else if (mp->work_rx & queue_mask) {
2206 work_done += rxq_process(mp->rxq + queue, work_tbd);
2207 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2208 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2214 if (work_done < budget) {
2216 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2217 napi_complete(napi);
2218 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2224 static inline void oom_timer_wrapper(unsigned long data)
2226 struct mv643xx_eth_private *mp = (void *)data;
2228 napi_schedule(&mp->napi);
2231 static void phy_reset(struct mv643xx_eth_private *mp)
2235 data = phy_read(mp->phy, MII_BMCR);
2240 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2244 data = phy_read(mp->phy, MII_BMCR);
2245 } while (data >= 0 && data & BMCR_RESET);
2248 static void port_start(struct mv643xx_eth_private *mp)
2254 * Perform PHY reset, if there is a PHY.
2256 if (mp->phy != NULL) {
2257 struct ethtool_cmd cmd;
2259 mv643xx_eth_get_settings(mp->dev, &cmd);
2261 mv643xx_eth_set_settings(mp->dev, &cmd);
2265 * Configure basic link parameters.
2267 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2269 pscr |= SERIAL_PORT_ENABLE;
2270 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2272 pscr |= DO_NOT_FORCE_LINK_FAIL;
2273 if (mp->phy == NULL)
2274 pscr |= FORCE_LINK_PASS;
2275 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2278 * Configure TX path and queues.
2280 tx_set_rate(mp, 1000000000, 16777216);
2281 for (i = 0; i < mp->txq_count; i++) {
2282 struct tx_queue *txq = mp->txq + i;
2284 txq_reset_hw_ptr(txq);
2285 txq_set_rate(txq, 1000000000, 16777216);
2286 txq_set_fixed_prio_mode(txq);
2290 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2291 * frames to RX queue #0, and include the pseudo-header when
2292 * calculating receive checksums.
2294 wrlp(mp, PORT_CONFIG, 0x02000000);
2297 * Treat BPDUs as normal multicasts, and disable partition mode.
2299 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2302 * Add configured unicast addresses to address filter table.
2304 mv643xx_eth_program_unicast_filter(mp->dev);
2307 * Enable the receive queues.
2309 for (i = 0; i < mp->rxq_count; i++) {
2310 struct rx_queue *rxq = mp->rxq + i;
2313 addr = (u32)rxq->rx_desc_dma;
2314 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2315 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2321 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2326 * Reserve 2+14 bytes for an ethernet header (the hardware
2327 * automatically prepends 2 bytes of dummy data to each
2328 * received packet), 16 bytes for up to four VLAN tags, and
2329 * 4 bytes for the trailing FCS -- 36 bytes total.
2331 skb_size = mp->dev->mtu + 36;
2334 * Make sure that the skb size is a multiple of 8 bytes, as
2335 * the lower three bits of the receive descriptor's buffer
2336 * size field are ignored by the hardware.
2338 mp->skb_size = (skb_size + 7) & ~7;
2341 static int mv643xx_eth_open(struct net_device *dev)
2343 struct mv643xx_eth_private *mp = netdev_priv(dev);
2347 wrlp(mp, INT_CAUSE, 0);
2348 wrlp(mp, INT_CAUSE_EXT, 0);
2349 rdlp(mp, INT_CAUSE_EXT);
2351 err = request_irq(dev->irq, mv643xx_eth_irq,
2352 IRQF_SHARED, dev->name, dev);
2354 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2358 mv643xx_eth_recalc_skb_size(mp);
2360 napi_enable(&mp->napi);
2362 skb_queue_head_init(&mp->rx_recycle);
2364 for (i = 0; i < mp->rxq_count; i++) {
2365 err = rxq_init(mp, i);
2368 rxq_deinit(mp->rxq + i);
2372 rxq_refill(mp->rxq + i, INT_MAX);
2376 mp->rx_oom.expires = jiffies + (HZ / 10);
2377 add_timer(&mp->rx_oom);
2380 for (i = 0; i < mp->txq_count; i++) {
2381 err = txq_init(mp, i);
2384 txq_deinit(mp->txq + i);
2391 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2392 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2398 for (i = 0; i < mp->rxq_count; i++)
2399 rxq_deinit(mp->rxq + i);
2401 free_irq(dev->irq, dev);
2406 static void port_reset(struct mv643xx_eth_private *mp)
2411 for (i = 0; i < mp->rxq_count; i++)
2412 rxq_disable(mp->rxq + i);
2413 for (i = 0; i < mp->txq_count; i++)
2414 txq_disable(mp->txq + i);
2417 u32 ps = rdlp(mp, PORT_STATUS);
2419 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2424 /* Reset the Enable bit in the Configuration Register */
2425 data = rdlp(mp, PORT_SERIAL_CONTROL);
2426 data &= ~(SERIAL_PORT_ENABLE |
2427 DO_NOT_FORCE_LINK_FAIL |
2429 wrlp(mp, PORT_SERIAL_CONTROL, data);
2432 static int mv643xx_eth_stop(struct net_device *dev)
2434 struct mv643xx_eth_private *mp = netdev_priv(dev);
2437 wrlp(mp, INT_MASK_EXT, 0x00000000);
2438 wrlp(mp, INT_MASK, 0x00000000);
2441 napi_disable(&mp->napi);
2443 del_timer_sync(&mp->rx_oom);
2445 netif_carrier_off(dev);
2447 free_irq(dev->irq, dev);
2450 mv643xx_eth_get_stats(dev);
2451 mib_counters_update(mp);
2452 del_timer_sync(&mp->mib_counters_timer);
2454 skb_queue_purge(&mp->rx_recycle);
2456 for (i = 0; i < mp->rxq_count; i++)
2457 rxq_deinit(mp->rxq + i);
2458 for (i = 0; i < mp->txq_count; i++)
2459 txq_deinit(mp->txq + i);
2464 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2466 struct mv643xx_eth_private *mp = netdev_priv(dev);
2468 if (mp->phy != NULL)
2469 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2474 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2476 struct mv643xx_eth_private *mp = netdev_priv(dev);
2478 if (new_mtu < 64 || new_mtu > 9500)
2482 mv643xx_eth_recalc_skb_size(mp);
2483 tx_set_rate(mp, 1000000000, 16777216);
2485 if (!netif_running(dev))
2489 * Stop and then re-open the interface. This will allocate RX
2490 * skbs of the new MTU.
2491 * There is a possible danger that the open will not succeed,
2492 * due to memory being full.
2494 mv643xx_eth_stop(dev);
2495 if (mv643xx_eth_open(dev)) {
2496 dev_printk(KERN_ERR, &dev->dev,
2497 "fatal error on re-opening device after "
2504 static void tx_timeout_task(struct work_struct *ugly)
2506 struct mv643xx_eth_private *mp;
2508 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2509 if (netif_running(mp->dev)) {
2510 netif_tx_stop_all_queues(mp->dev);
2513 netif_tx_wake_all_queues(mp->dev);
2517 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2519 struct mv643xx_eth_private *mp = netdev_priv(dev);
2521 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2523 schedule_work(&mp->tx_timeout_task);
2526 #ifdef CONFIG_NET_POLL_CONTROLLER
2527 static void mv643xx_eth_netpoll(struct net_device *dev)
2529 struct mv643xx_eth_private *mp = netdev_priv(dev);
2531 wrlp(mp, INT_MASK, 0x00000000);
2534 mv643xx_eth_irq(dev->irq, dev);
2536 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2541 /* platform glue ************************************************************/
2543 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2544 struct mbus_dram_target_info *dram)
2546 void __iomem *base = msp->base;
2551 for (i = 0; i < 6; i++) {
2552 writel(0, base + WINDOW_BASE(i));
2553 writel(0, base + WINDOW_SIZE(i));
2555 writel(0, base + WINDOW_REMAP_HIGH(i));
2561 for (i = 0; i < dram->num_cs; i++) {
2562 struct mbus_dram_window *cs = dram->cs + i;
2564 writel((cs->base & 0xffff0000) |
2565 (cs->mbus_attr << 8) |
2566 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2567 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2569 win_enable &= ~(1 << i);
2570 win_protect |= 3 << (2 * i);
2573 writel(win_enable, base + WINDOW_BAR_ENABLE);
2574 msp->win_protect = win_protect;
2577 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2580 * Check whether we have a 14-bit coal limit field in bits
2581 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2582 * SDMA config register.
2584 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2585 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2586 msp->extended_rx_coal_limit = 1;
2588 msp->extended_rx_coal_limit = 0;
2591 * Check whether the MAC supports TX rate control, and if
2592 * yes, whether its associated registers are in the old or
2595 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2596 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2597 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2599 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2600 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2601 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2603 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2607 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2609 static int mv643xx_eth_version_printed;
2610 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2611 struct mv643xx_eth_shared_private *msp;
2612 struct resource *res;
2615 if (!mv643xx_eth_version_printed++)
2616 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2617 "driver version %s\n", mv643xx_eth_driver_version);
2620 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2625 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2628 memset(msp, 0, sizeof(*msp));
2630 msp->base = ioremap(res->start, res->end - res->start + 1);
2631 if (msp->base == NULL)
2635 * Set up and register SMI bus.
2637 if (pd == NULL || pd->shared_smi == NULL) {
2638 msp->smi_bus = mdiobus_alloc();
2639 if (msp->smi_bus == NULL)
2642 msp->smi_bus->priv = msp;
2643 msp->smi_bus->name = "mv643xx_eth smi";
2644 msp->smi_bus->read = smi_bus_read;
2645 msp->smi_bus->write = smi_bus_write,
2646 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2647 msp->smi_bus->parent = &pdev->dev;
2648 msp->smi_bus->phy_mask = 0xffffffff;
2649 if (mdiobus_register(msp->smi_bus) < 0)
2650 goto out_free_mii_bus;
2653 msp->smi = platform_get_drvdata(pd->shared_smi);
2656 msp->err_interrupt = NO_IRQ;
2657 init_waitqueue_head(&msp->smi_busy_wait);
2660 * Check whether the error interrupt is hooked up.
2662 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2666 err = request_irq(res->start, mv643xx_eth_err_irq,
2667 IRQF_SHARED, "mv643xx_eth", msp);
2669 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2670 msp->err_interrupt = res->start;
2675 * (Re-)program MBUS remapping windows if we are asked to.
2677 if (pd != NULL && pd->dram != NULL)
2678 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2681 * Detect hardware parameters.
2683 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2684 infer_hw_params(msp);
2686 platform_set_drvdata(pdev, msp);
2691 mdiobus_free(msp->smi_bus);
2700 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2702 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2703 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2705 if (pd == NULL || pd->shared_smi == NULL) {
2706 mdiobus_unregister(msp->smi_bus);
2707 mdiobus_free(msp->smi_bus);
2709 if (msp->err_interrupt != NO_IRQ)
2710 free_irq(msp->err_interrupt, msp);
2717 static struct platform_driver mv643xx_eth_shared_driver = {
2718 .probe = mv643xx_eth_shared_probe,
2719 .remove = mv643xx_eth_shared_remove,
2721 .name = MV643XX_ETH_SHARED_NAME,
2722 .owner = THIS_MODULE,
2726 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2728 int addr_shift = 5 * mp->port_num;
2731 data = rdl(mp, PHY_ADDR);
2732 data &= ~(0x1f << addr_shift);
2733 data |= (phy_addr & 0x1f) << addr_shift;
2734 wrl(mp, PHY_ADDR, data);
2737 static int phy_addr_get(struct mv643xx_eth_private *mp)
2741 data = rdl(mp, PHY_ADDR);
2743 return (data >> (5 * mp->port_num)) & 0x1f;
2746 static void set_params(struct mv643xx_eth_private *mp,
2747 struct mv643xx_eth_platform_data *pd)
2749 struct net_device *dev = mp->dev;
2751 if (is_valid_ether_addr(pd->mac_addr))
2752 memcpy(dev->dev_addr, pd->mac_addr, 6);
2754 uc_addr_get(mp, dev->dev_addr);
2756 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2757 if (pd->rx_queue_size)
2758 mp->rx_ring_size = pd->rx_queue_size;
2759 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2760 mp->rx_desc_sram_size = pd->rx_sram_size;
2762 mp->rxq_count = pd->rx_queue_count ? : 1;
2764 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2765 if (pd->tx_queue_size)
2766 mp->tx_ring_size = pd->tx_queue_size;
2767 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2768 mp->tx_desc_sram_size = pd->tx_sram_size;
2770 mp->txq_count = pd->tx_queue_count ? : 1;
2773 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2776 struct mii_bus *bus = mp->shared->smi->smi_bus;
2777 struct phy_device *phydev;
2782 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2783 start = phy_addr_get(mp) & 0x1f;
2786 start = phy_addr & 0x1f;
2791 for (i = 0; i < num; i++) {
2792 int addr = (start + i) & 0x1f;
2794 if (bus->phy_map[addr] == NULL)
2795 mdiobus_scan(bus, addr);
2797 if (phydev == NULL) {
2798 phydev = bus->phy_map[addr];
2800 phy_addr_set(mp, addr);
2807 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2809 struct phy_device *phy = mp->phy;
2813 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2816 phy->autoneg = AUTONEG_ENABLE;
2819 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2821 phy->autoneg = AUTONEG_DISABLE;
2822 phy->advertising = 0;
2824 phy->duplex = duplex;
2826 phy_start_aneg(phy);
2829 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2833 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2834 if (pscr & SERIAL_PORT_ENABLE) {
2835 pscr &= ~SERIAL_PORT_ENABLE;
2836 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2839 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2840 if (mp->phy == NULL) {
2841 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2842 if (speed == SPEED_1000)
2843 pscr |= SET_GMII_SPEED_TO_1000;
2844 else if (speed == SPEED_100)
2845 pscr |= SET_MII_SPEED_TO_100;
2847 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2849 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2850 if (duplex == DUPLEX_FULL)
2851 pscr |= SET_FULL_DUPLEX_MODE;
2854 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2857 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2858 .ndo_open = mv643xx_eth_open,
2859 .ndo_stop = mv643xx_eth_stop,
2860 .ndo_start_xmit = mv643xx_eth_xmit,
2861 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2862 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2863 .ndo_do_ioctl = mv643xx_eth_ioctl,
2864 .ndo_change_mtu = mv643xx_eth_change_mtu,
2865 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2866 .ndo_get_stats = mv643xx_eth_get_stats,
2867 #ifdef CONFIG_NET_POLL_CONTROLLER
2868 .ndo_poll_controller = mv643xx_eth_netpoll,
2872 static int mv643xx_eth_probe(struct platform_device *pdev)
2874 struct mv643xx_eth_platform_data *pd;
2875 struct mv643xx_eth_private *mp;
2876 struct net_device *dev;
2877 struct resource *res;
2880 pd = pdev->dev.platform_data;
2882 dev_printk(KERN_ERR, &pdev->dev,
2883 "no mv643xx_eth_platform_data\n");
2887 if (pd->shared == NULL) {
2888 dev_printk(KERN_ERR, &pdev->dev,
2889 "no mv643xx_eth_platform_data->shared\n");
2893 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2897 mp = netdev_priv(dev);
2898 platform_set_drvdata(pdev, mp);
2900 mp->shared = platform_get_drvdata(pd->shared);
2901 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2902 mp->port_num = pd->port_number;
2907 dev->real_num_tx_queues = mp->txq_count;
2909 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2910 mp->phy = phy_scan(mp, pd->phy_addr);
2912 if (mp->phy != NULL)
2913 phy_init(mp, pd->speed, pd->duplex);
2915 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2917 init_pscr(mp, pd->speed, pd->duplex);
2920 mib_counters_clear(mp);
2922 init_timer(&mp->mib_counters_timer);
2923 mp->mib_counters_timer.data = (unsigned long)mp;
2924 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2925 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2926 add_timer(&mp->mib_counters_timer);
2928 spin_lock_init(&mp->mib_counters_lock);
2930 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2932 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2934 init_timer(&mp->rx_oom);
2935 mp->rx_oom.data = (unsigned long)mp;
2936 mp->rx_oom.function = oom_timer_wrapper;
2939 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2941 dev->irq = res->start;
2943 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2945 dev->watchdog_timeo = 2 * HZ;
2948 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2949 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2951 SET_NETDEV_DEV(dev, &pdev->dev);
2953 if (mp->shared->win_protect)
2954 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2956 netif_carrier_off(dev);
2958 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2960 set_rx_coal(mp, 250);
2963 err = register_netdev(dev);
2967 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2968 mp->port_num, dev->dev_addr);
2970 if (mp->tx_desc_sram_size > 0)
2971 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2981 static int mv643xx_eth_remove(struct platform_device *pdev)
2983 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2985 unregister_netdev(mp->dev);
2986 if (mp->phy != NULL)
2987 phy_detach(mp->phy);
2988 flush_scheduled_work();
2989 free_netdev(mp->dev);
2991 platform_set_drvdata(pdev, NULL);
2996 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2998 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3000 /* Mask all interrupts on ethernet port */
3001 wrlp(mp, INT_MASK, 0);
3004 if (netif_running(mp->dev))
3008 static struct platform_driver mv643xx_eth_driver = {
3009 .probe = mv643xx_eth_probe,
3010 .remove = mv643xx_eth_remove,
3011 .shutdown = mv643xx_eth_shutdown,
3013 .name = MV643XX_ETH_NAME,
3014 .owner = THIS_MODULE,
3018 static int __init mv643xx_eth_init_module(void)
3022 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3024 rc = platform_driver_register(&mv643xx_eth_driver);
3026 platform_driver_unregister(&mv643xx_eth_shared_driver);
3031 module_init(mv643xx_eth_init_module);
3033 static void __exit mv643xx_eth_cleanup_module(void)
3035 platform_driver_unregister(&mv643xx_eth_driver);
3036 platform_driver_unregister(&mv643xx_eth_shared_driver);
3038 module_exit(mv643xx_eth_cleanup_module);
3040 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3041 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3042 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3043 MODULE_LICENSE("GPL");
3044 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3045 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);