2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.0";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
63 #undef MV643XX_ETH_COAL
65 #define MV643XX_ETH_TX_COAL 100
66 #ifdef MV643XX_ETH_COAL
67 #define MV643XX_ETH_RX_COAL 100
70 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_HW_IP_ALIGN 2
79 * Registers shared between all ports.
81 #define PHY_ADDR 0x0000
82 #define SMI_REG 0x0004
83 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
84 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
85 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
86 #define WINDOW_BAR_ENABLE 0x0290
87 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
92 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
93 #define UNICAST_PROMISCUOUS_MODE 0x00000001
94 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
95 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
96 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
97 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
98 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
99 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
100 #define TX_FIFO_EMPTY 0x00000400
101 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
102 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
103 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
104 #define INT_RX 0x00000804
105 #define INT_EXT 0x00000002
106 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
107 #define INT_EXT_LINK 0x00100000
108 #define INT_EXT_PHY 0x00010000
109 #define INT_EXT_TX_ERROR_0 0x00000100
110 #define INT_EXT_TX_0 0x00000001
111 #define INT_EXT_TX 0x00000101
112 #define INT_MASK(p) (0x0468 + ((p) << 10))
113 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
114 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
115 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
116 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
117 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
118 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
119 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
120 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
121 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
125 * SDMA configuration register.
127 #define RX_BURST_SIZE_4_64BIT (2 << 1)
128 #define BLM_RX_NO_SWAP (1 << 4)
129 #define BLM_TX_NO_SWAP (1 << 5)
130 #define TX_BURST_SIZE_4_64BIT (2 << 22)
132 #if defined(__BIG_ENDIAN)
133 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
134 RX_BURST_SIZE_4_64BIT | \
135 TX_BURST_SIZE_4_64BIT
136 #elif defined(__LITTLE_ENDIAN)
137 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
138 RX_BURST_SIZE_4_64BIT | \
141 TX_BURST_SIZE_4_64BIT
143 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
148 * Port serial control register.
150 #define SET_MII_SPEED_TO_100 (1 << 24)
151 #define SET_GMII_SPEED_TO_1000 (1 << 23)
152 #define SET_FULL_DUPLEX_MODE (1 << 21)
153 #define MAX_RX_PACKET_1522BYTE (1 << 17)
154 #define MAX_RX_PACKET_9700BYTE (5 << 17)
155 #define MAX_RX_PACKET_MASK (7 << 17)
156 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
157 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
158 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
159 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
160 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
161 #define FORCE_LINK_PASS (1 << 1)
162 #define SERIAL_PORT_ENABLE (1 << 0)
164 #define DEFAULT_RX_QUEUE_SIZE 400
165 #define DEFAULT_TX_QUEUE_SIZE 800
168 #define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
169 #define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
170 #define SMI_OPCODE_WRITE 0 /* Completion of Read */
171 #define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
177 #if defined(__BIG_ENDIAN)
179 u16 byte_cnt; /* Descriptor buffer byte count */
180 u16 buf_size; /* Buffer size */
181 u32 cmd_sts; /* Descriptor command status */
182 u32 next_desc_ptr; /* Next descriptor pointer */
183 u32 buf_ptr; /* Descriptor buffer pointer */
187 u16 byte_cnt; /* buffer byte count */
188 u16 l4i_chk; /* CPU provided TCP checksum */
189 u32 cmd_sts; /* Command/status field */
190 u32 next_desc_ptr; /* Pointer to next descriptor */
191 u32 buf_ptr; /* pointer to buffer for this descriptor*/
193 #elif defined(__LITTLE_ENDIAN)
195 u32 cmd_sts; /* Descriptor command status */
196 u16 buf_size; /* Buffer size */
197 u16 byte_cnt; /* Descriptor buffer byte count */
198 u32 buf_ptr; /* Descriptor buffer pointer */
199 u32 next_desc_ptr; /* Next descriptor pointer */
203 u32 cmd_sts; /* Command/status field */
204 u16 l4i_chk; /* CPU provided TCP checksum */
205 u16 byte_cnt; /* buffer byte count */
206 u32 buf_ptr; /* pointer to buffer for this descriptor*/
207 u32 next_desc_ptr; /* Pointer to next descriptor */
210 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
213 /* RX & TX descriptor command */
214 #define BUFFER_OWNED_BY_DMA 0x80000000
216 /* RX & TX descriptor status */
217 #define ERROR_SUMMARY 0x00000001
219 /* RX descriptor status */
220 #define LAYER_4_CHECKSUM_OK 0x40000000
221 #define RX_ENABLE_INTERRUPT 0x20000000
222 #define RX_FIRST_DESC 0x08000000
223 #define RX_LAST_DESC 0x04000000
225 /* TX descriptor command */
226 #define TX_ENABLE_INTERRUPT 0x00800000
227 #define GEN_CRC 0x00400000
228 #define TX_FIRST_DESC 0x00200000
229 #define TX_LAST_DESC 0x00100000
230 #define ZERO_PADDING 0x00080000
231 #define GEN_IP_V4_CHECKSUM 0x00040000
232 #define GEN_TCP_UDP_CHECKSUM 0x00020000
233 #define UDP_FRAME 0x00010000
235 #define TX_IHL_SHIFT 11
238 /* global *******************************************************************/
239 struct mv643xx_eth_shared_private {
242 /* used to protect SMI_REG, which is shared across ports */
251 /* per-port *****************************************************************/
252 struct mib_counters {
253 u64 good_octets_received;
254 u32 bad_octets_received;
255 u32 internal_mac_transmit_err;
256 u32 good_frames_received;
257 u32 bad_frames_received;
258 u32 broadcast_frames_received;
259 u32 multicast_frames_received;
260 u32 frames_64_octets;
261 u32 frames_65_to_127_octets;
262 u32 frames_128_to_255_octets;
263 u32 frames_256_to_511_octets;
264 u32 frames_512_to_1023_octets;
265 u32 frames_1024_to_max_octets;
266 u64 good_octets_sent;
267 u32 good_frames_sent;
268 u32 excessive_collision;
269 u32 multicast_frames_sent;
270 u32 broadcast_frames_sent;
271 u32 unrec_mac_control_received;
273 u32 good_fc_received;
275 u32 undersize_received;
276 u32 fragments_received;
277 u32 oversize_received;
279 u32 mac_receive_error;
292 struct rx_desc *rx_desc_area;
293 dma_addr_t rx_desc_dma;
294 int rx_desc_area_size;
295 struct sk_buff **rx_skb;
297 struct timer_list rx_oom;
300 struct mv643xx_eth_private {
301 struct mv643xx_eth_shared_private *shared;
302 int port_num; /* User Ethernet port number */
304 struct mv643xx_eth_shared_private *shared_smi;
306 u32 tx_sram_addr; /* Base address of tx sram area */
307 u32 tx_sram_size; /* Size of tx sram area */
309 /* Tx/Rx rings managment indexes fields. For driver use */
311 /* Next available and first returning Tx resource */
312 int tx_curr_desc, tx_used_desc;
314 #ifdef MV643XX_ETH_TX_FAST_REFILL
315 u32 tx_clean_threshold;
318 struct tx_desc *tx_desc_area;
319 dma_addr_t tx_desc_dma;
320 int tx_desc_area_size;
321 struct sk_buff **tx_skb;
323 struct work_struct tx_timeout_task;
325 struct net_device *dev;
326 struct mib_counters mib_counters;
328 /* Size of Tx Ring per queue */
330 /* Number of tx descriptors in use */
335 struct mii_if_info mii;
340 int default_rx_ring_size;
341 unsigned long rx_desc_sram_addr;
342 int rx_desc_sram_size;
343 struct napi_struct napi;
344 struct rx_queue rxq[1];
348 /* port register accessors **************************************************/
349 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
351 return readl(mp->shared->base + offset);
354 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
356 writel(data, mp->shared->base + offset);
360 /* rxq/txq helper functions *************************************************/
361 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
363 return container_of(rxq, struct mv643xx_eth_private, rxq[0]);
366 static void rxq_enable(struct rx_queue *rxq)
368 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
369 wrl(mp, RXQ_COMMAND(mp->port_num), 1);
372 static void rxq_disable(struct rx_queue *rxq)
374 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
377 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
378 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
382 static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
385 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
388 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
390 unsigned int port_num = mp->port_num;
393 /* Stop Tx port activity. Check port Tx activity. */
394 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
396 /* Issue stop command for active queues only */
397 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
399 /* Wait for all Tx activity to terminate. */
400 /* Check port cause register that all Tx queues are stopped */
401 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
404 /* Wait for Tx FIFO to empty */
405 while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
413 /* rx ***********************************************************************/
414 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
416 static void rxq_refill(struct rx_queue *rxq)
418 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
421 spin_lock_irqsave(&mp->lock, flags);
423 while (rxq->rx_desc_count < rxq->rx_ring_size) {
430 * Reserve 2+14 bytes for an ethernet header (the
431 * hardware automatically prepends 2 bytes of dummy
432 * data to each received packet), 4 bytes for a VLAN
433 * header, and 4 bytes for the trailing FCS -- 24
436 skb_size = mp->dev->mtu + 24;
438 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
442 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
444 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
446 rxq->rx_desc_count++;
447 rx = rxq->rx_used_desc;
448 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
450 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
451 skb_size, DMA_FROM_DEVICE);
452 rxq->rx_desc_area[rx].buf_size = skb_size;
453 rxq->rx_skb[rx] = skb;
455 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
459 skb_reserve(skb, ETH_HW_IP_ALIGN);
462 if (rxq->rx_desc_count == 0) {
463 rxq->rx_oom.expires = jiffies + (HZ / 10);
464 add_timer(&rxq->rx_oom);
467 spin_unlock_irqrestore(&mp->lock, flags);
470 static inline void rxq_refill_timer_wrapper(unsigned long data)
472 rxq_refill((struct rx_queue *)data);
475 static int rxq_process(struct rx_queue *rxq, int budget)
477 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
478 struct net_device_stats *stats = &mp->dev->stats;
482 while (rx < budget) {
484 volatile struct rx_desc *rx_desc;
485 unsigned int cmd_sts;
488 spin_lock_irqsave(&mp->lock, flags);
490 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
492 cmd_sts = rx_desc->cmd_sts;
493 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
494 spin_unlock_irqrestore(&mp->lock, flags);
499 skb = rxq->rx_skb[rxq->rx_curr_desc];
500 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
502 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
504 spin_unlock_irqrestore(&mp->lock, flags);
506 dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN,
507 mp->dev->mtu + 24, DMA_FROM_DEVICE);
508 rxq->rx_desc_count--;
513 * Note byte count includes 4 byte CRC count
516 stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
519 * In case received a packet without first / last bits on OR
520 * the error summary bit is on, the packets needs to be dropeed.
522 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
523 (RX_FIRST_DESC | RX_LAST_DESC))
524 || (cmd_sts & ERROR_SUMMARY)) {
526 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
527 (RX_FIRST_DESC | RX_LAST_DESC)) {
530 "%s: Received packet spread "
531 "on multiple descriptors\n",
534 if (cmd_sts & ERROR_SUMMARY)
537 dev_kfree_skb_irq(skb);
540 * The -4 is for the CRC in the trailer of the
543 skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4);
545 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
546 skb->ip_summed = CHECKSUM_UNNECESSARY;
548 (cmd_sts & 0x0007fff8) >> 3);
550 skb->protocol = eth_type_trans(skb, mp->dev);
551 #ifdef MV643XX_ETH_NAPI
552 netif_receive_skb(skb);
557 mp->dev->last_rx = jiffies;
564 #ifdef MV643XX_ETH_NAPI
565 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
567 struct mv643xx_eth_private *mp;
570 mp = container_of(napi, struct mv643xx_eth_private, napi);
572 #ifdef MV643XX_ETH_TX_FAST_REFILL
573 if (++mp->tx_clean_threshold > 5) {
574 mv643xx_eth_free_completed_tx_descs(mp->dev);
575 mp->tx_clean_threshold = 0;
579 rx = rxq_process(mp->rxq, budget);
582 netif_rx_complete(mp->dev, napi);
583 wrl(mp, INT_CAUSE(mp->port_num), 0);
584 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
585 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
593 /* tx ***********************************************************************/
594 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
599 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
600 fragp = &skb_shinfo(skb)->frags[frag];
601 if (fragp->size <= 8 && fragp->page_offset & 0x7)
607 static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
611 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
613 tx_desc_curr = mp->tx_curr_desc;
614 mp->tx_curr_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
616 BUG_ON(mp->tx_curr_desc == mp->tx_used_desc);
621 static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
626 struct tx_desc *desc;
628 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
629 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
631 tx_index = alloc_tx_desc_index(mp);
632 desc = &mp->tx_desc_area[tx_index];
634 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
635 /* Last Frag enables interrupt and frees the skb */
636 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
637 desc->cmd_sts |= ZERO_PADDING |
640 mp->tx_skb[tx_index] = skb;
642 mp->tx_skb[tx_index] = NULL;
644 desc = &mp->tx_desc_area[tx_index];
646 desc->byte_cnt = this_frag->size;
647 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
648 this_frag->page_offset,
654 static inline __be16 sum16_as_be(__sum16 sum)
656 return (__force __be16)sum;
659 static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
663 struct tx_desc *desc;
666 int nr_frags = skb_shinfo(skb)->nr_frags;
668 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
670 tx_index = alloc_tx_desc_index(mp);
671 desc = &mp->tx_desc_area[tx_index];
674 tx_fill_frag_descs(mp, skb);
676 length = skb_headlen(skb);
677 mp->tx_skb[tx_index] = NULL;
679 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
681 mp->tx_skb[tx_index] = skb;
684 desc->byte_cnt = length;
685 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
687 if (skb->ip_summed == CHECKSUM_PARTIAL) {
688 BUG_ON(skb->protocol != htons(ETH_P_IP));
690 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
692 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
694 switch (ip_hdr(skb)->protocol) {
696 cmd_sts |= UDP_FRAME;
697 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
700 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
706 /* Errata BTS #50, IHL must be 5 if no HW checksum */
707 cmd_sts |= 5 << TX_IHL_SHIFT;
711 /* ensure all other descriptors are written before first cmd_sts */
713 desc->cmd_sts = cmd_sts;
715 /* ensure all descriptors are written before poking hardware */
717 mv643xx_eth_port_enable_tx(mp, 1);
719 mp->tx_desc_count += nr_frags + 1;
722 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
724 struct mv643xx_eth_private *mp = netdev_priv(dev);
725 struct net_device_stats *stats = &dev->stats;
728 BUG_ON(netif_queue_stopped(dev));
730 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
732 printk(KERN_DEBUG "%s: failed to linearize tiny "
733 "unaligned fragment\n", dev->name);
734 return NETDEV_TX_BUSY;
737 spin_lock_irqsave(&mp->lock, flags);
739 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
740 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
741 netif_stop_queue(dev);
742 spin_unlock_irqrestore(&mp->lock, flags);
743 return NETDEV_TX_BUSY;
746 tx_submit_descs_for_skb(mp, skb);
747 stats->tx_bytes += skb->len;
749 dev->trans_start = jiffies;
751 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
752 netif_stop_queue(dev);
754 spin_unlock_irqrestore(&mp->lock, flags);
760 /* mii management interface *************************************************/
761 static int phy_addr_get(struct mv643xx_eth_private *mp);
763 static void read_smi_reg(struct mv643xx_eth_private *mp,
764 unsigned int phy_reg, unsigned int *value)
766 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
767 int phy_addr = phy_addr_get(mp);
771 /* the SMI register is a shared resource */
772 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
774 /* wait for the SMI register to become available */
775 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
777 printk("%s: PHY busy timeout\n", mp->dev->name);
783 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
785 /* now wait for the data to be valid */
786 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
788 printk("%s: PHY read timeout\n", mp->dev->name);
794 *value = readl(smi_reg) & 0xffff;
796 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
799 static void write_smi_reg(struct mv643xx_eth_private *mp,
800 unsigned int phy_reg, unsigned int value)
802 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
803 int phy_addr = phy_addr_get(mp);
807 /* the SMI register is a shared resource */
808 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
810 /* wait for the SMI register to become available */
811 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
813 printk("%s: PHY busy timeout\n", mp->dev->name);
819 writel((phy_addr << 16) | (phy_reg << 21) |
820 SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
822 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
826 /* mib counters *************************************************************/
827 static void clear_mib_counters(struct mv643xx_eth_private *mp)
829 unsigned int port_num = mp->port_num;
832 /* Perform dummy reads from MIB counters */
833 for (i = 0; i < 0x80; i += 4)
834 rdl(mp, MIB_COUNTERS(port_num) + i);
837 static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
839 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
842 static void update_mib_counters(struct mv643xx_eth_private *mp)
844 struct mib_counters *p = &mp->mib_counters;
846 p->good_octets_received += read_mib(mp, 0x00);
847 p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
848 p->bad_octets_received += read_mib(mp, 0x08);
849 p->internal_mac_transmit_err += read_mib(mp, 0x0c);
850 p->good_frames_received += read_mib(mp, 0x10);
851 p->bad_frames_received += read_mib(mp, 0x14);
852 p->broadcast_frames_received += read_mib(mp, 0x18);
853 p->multicast_frames_received += read_mib(mp, 0x1c);
854 p->frames_64_octets += read_mib(mp, 0x20);
855 p->frames_65_to_127_octets += read_mib(mp, 0x24);
856 p->frames_128_to_255_octets += read_mib(mp, 0x28);
857 p->frames_256_to_511_octets += read_mib(mp, 0x2c);
858 p->frames_512_to_1023_octets += read_mib(mp, 0x30);
859 p->frames_1024_to_max_octets += read_mib(mp, 0x34);
860 p->good_octets_sent += read_mib(mp, 0x38);
861 p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
862 p->good_frames_sent += read_mib(mp, 0x40);
863 p->excessive_collision += read_mib(mp, 0x44);
864 p->multicast_frames_sent += read_mib(mp, 0x48);
865 p->broadcast_frames_sent += read_mib(mp, 0x4c);
866 p->unrec_mac_control_received += read_mib(mp, 0x50);
867 p->fc_sent += read_mib(mp, 0x54);
868 p->good_fc_received += read_mib(mp, 0x58);
869 p->bad_fc_received += read_mib(mp, 0x5c);
870 p->undersize_received += read_mib(mp, 0x60);
871 p->fragments_received += read_mib(mp, 0x64);
872 p->oversize_received += read_mib(mp, 0x68);
873 p->jabber_received += read_mib(mp, 0x6c);
874 p->mac_receive_error += read_mib(mp, 0x70);
875 p->bad_crc_event += read_mib(mp, 0x74);
876 p->collision += read_mib(mp, 0x78);
877 p->late_collision += read_mib(mp, 0x7c);
881 /* ethtool ******************************************************************/
882 struct mv643xx_eth_stats {
883 char stat_string[ETH_GSTRING_LEN];
890 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
891 offsetof(struct net_device, stats.m), -1 }
894 { #m, FIELD_SIZEOF(struct mib_counters, m), \
895 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
897 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
906 MIBSTAT(good_octets_received),
907 MIBSTAT(bad_octets_received),
908 MIBSTAT(internal_mac_transmit_err),
909 MIBSTAT(good_frames_received),
910 MIBSTAT(bad_frames_received),
911 MIBSTAT(broadcast_frames_received),
912 MIBSTAT(multicast_frames_received),
913 MIBSTAT(frames_64_octets),
914 MIBSTAT(frames_65_to_127_octets),
915 MIBSTAT(frames_128_to_255_octets),
916 MIBSTAT(frames_256_to_511_octets),
917 MIBSTAT(frames_512_to_1023_octets),
918 MIBSTAT(frames_1024_to_max_octets),
919 MIBSTAT(good_octets_sent),
920 MIBSTAT(good_frames_sent),
921 MIBSTAT(excessive_collision),
922 MIBSTAT(multicast_frames_sent),
923 MIBSTAT(broadcast_frames_sent),
924 MIBSTAT(unrec_mac_control_received),
926 MIBSTAT(good_fc_received),
927 MIBSTAT(bad_fc_received),
928 MIBSTAT(undersize_received),
929 MIBSTAT(fragments_received),
930 MIBSTAT(oversize_received),
931 MIBSTAT(jabber_received),
932 MIBSTAT(mac_receive_error),
933 MIBSTAT(bad_crc_event),
935 MIBSTAT(late_collision),
938 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
940 struct mv643xx_eth_private *mp = netdev_priv(dev);
943 spin_lock_irq(&mp->lock);
944 err = mii_ethtool_gset(&mp->mii, cmd);
945 spin_unlock_irq(&mp->lock);
947 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
948 cmd->supported &= ~SUPPORTED_1000baseT_Half;
949 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
954 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
956 struct mv643xx_eth_private *mp = netdev_priv(dev);
959 spin_lock_irq(&mp->lock);
960 err = mii_ethtool_sset(&mp->mii, cmd);
961 spin_unlock_irq(&mp->lock);
966 static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
967 struct ethtool_drvinfo *drvinfo)
969 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
970 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
971 strncpy(drvinfo->fw_version, "N/A", 32);
972 strncpy(drvinfo->bus_info, "mv643xx", 32);
973 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
976 static int mv643xx_eth_nway_restart(struct net_device *dev)
978 struct mv643xx_eth_private *mp = netdev_priv(dev);
980 return mii_nway_restart(&mp->mii);
983 static u32 mv643xx_eth_get_link(struct net_device *dev)
985 struct mv643xx_eth_private *mp = netdev_priv(dev);
987 return mii_link_ok(&mp->mii);
990 static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
997 for (i=0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
998 memcpy(data + i * ETH_GSTRING_LEN,
999 mv643xx_eth_stats[i].stat_string,
1006 static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
1007 struct ethtool_stats *stats, uint64_t *data)
1009 struct mv643xx_eth_private *mp = netdev->priv;
1012 update_mib_counters(mp);
1014 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1015 const struct mv643xx_eth_stats *stat;
1018 stat = mv643xx_eth_stats + i;
1020 if (stat->netdev_off >= 0)
1021 p = ((void *)mp->dev) + stat->netdev_off;
1023 p = ((void *)mp) + stat->mp_off;
1025 data[i] = (stat->sizeof_stat == 8) ?
1026 *(uint64_t *)p : *(uint32_t *)p;
1030 static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
1034 return ARRAY_SIZE(mv643xx_eth_stats);
1040 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1041 .get_settings = mv643xx_eth_get_settings,
1042 .set_settings = mv643xx_eth_set_settings,
1043 .get_drvinfo = mv643xx_eth_get_drvinfo,
1044 .get_link = mv643xx_eth_get_link,
1045 .set_sg = ethtool_op_set_sg,
1046 .get_sset_count = mv643xx_eth_get_sset_count,
1047 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1048 .get_strings = mv643xx_eth_get_strings,
1049 .nway_reset = mv643xx_eth_nway_restart,
1053 /* address handling *********************************************************/
1054 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1056 unsigned int port_num = mp->port_num;
1060 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1061 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1063 addr[0] = (mac_h >> 24) & 0xff;
1064 addr[1] = (mac_h >> 16) & 0xff;
1065 addr[2] = (mac_h >> 8) & 0xff;
1066 addr[3] = mac_h & 0xff;
1067 addr[4] = (mac_l >> 8) & 0xff;
1068 addr[5] = mac_l & 0xff;
1071 static void init_mac_tables(struct mv643xx_eth_private *mp)
1073 unsigned int port_num = mp->port_num;
1076 /* Clear DA filter unicast table (Ex_dFUT) */
1077 for (table_index = 0; table_index <= 0xC; table_index += 4)
1078 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1080 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1081 /* Clear DA filter special multicast table (Ex_dFSMT) */
1082 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1083 /* Clear DA filter other multicast table (Ex_dFOMT) */
1084 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1088 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1089 int table, unsigned char entry)
1091 unsigned int table_reg;
1092 unsigned int tbl_offset;
1093 unsigned int reg_offset;
1095 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1096 reg_offset = entry % 4; /* Entry offset within the register */
1098 /* Set "accepts frame bit" at specified table entry */
1099 table_reg = rdl(mp, table + tbl_offset);
1100 table_reg |= 0x01 << (8 * reg_offset);
1101 wrl(mp, table + tbl_offset, table_reg);
1104 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1106 unsigned int port_num = mp->port_num;
1111 mac_l = (addr[4] << 8) | (addr[5]);
1112 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1115 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1116 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1118 /* Accept frames with this address */
1119 table = UNICAST_TABLE(port_num);
1120 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1123 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1125 struct mv643xx_eth_private *mp = netdev_priv(dev);
1127 init_mac_tables(mp);
1128 uc_addr_set(mp, dev->dev_addr);
1131 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1135 for (i = 0; i < 6; i++)
1136 /* +2 is for the offset of the HW addr type */
1137 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1138 mv643xx_eth_update_mac_address(dev);
1142 static int addr_crc(unsigned char *addr)
1147 for (i = 0; i < 6; i++) {
1150 crc = (crc ^ addr[i]) << 8;
1151 for (j = 7; j >= 0; j--) {
1152 if (crc & (0x100 << j))
1160 static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr)
1162 unsigned int port_num = mp->port_num;
1166 if ((addr[0] == 0x01) && (addr[1] == 0x00) &&
1167 (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) {
1168 table = SPECIAL_MCAST_TABLE(port_num);
1169 set_filter_table_entry(mp, table, addr[5]);
1173 crc = addr_crc(addr);
1175 table = OTHER_MCAST_TABLE(port_num);
1176 set_filter_table_entry(mp, table, crc);
1179 static void set_multicast_list(struct net_device *dev)
1182 struct dev_mc_list *mc_list;
1185 struct mv643xx_eth_private *mp = netdev_priv(dev);
1186 unsigned int port_num = mp->port_num;
1188 /* If the device is in promiscuous mode or in all multicast mode,
1189 * we will fully populate both multicast tables with accept.
1190 * This is guaranteed to yield a match on all multicast addresses...
1192 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1193 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1194 /* Set all entries in DA filter special multicast
1196 * Set for ETH_Q0 for now
1198 * 0 Accept=1, Drop=0
1199 * 3-1 Queue ETH_Q0=0
1202 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
1204 /* Set all entries in DA filter other multicast
1206 * Set for ETH_Q0 for now
1208 * 0 Accept=1, Drop=0
1209 * 3-1 Queue ETH_Q0=0
1212 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
1217 /* We will clear out multicast tables every time we get the list.
1218 * Then add the entire new list...
1220 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1221 /* Clear DA filter special multicast table (Ex_dFSMT) */
1222 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1224 /* Clear DA filter other multicast table (Ex_dFOMT) */
1225 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1228 /* Get pointer to net_device multicast list and add each one... */
1229 for (i = 0, mc_list = dev->mc_list;
1230 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1231 i++, mc_list = mc_list->next)
1232 if (mc_list->dmi_addrlen == 6)
1233 mc_addr(mp, mc_list->dmi_addr);
1236 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1238 struct mv643xx_eth_private *mp = netdev_priv(dev);
1241 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1242 if (dev->flags & IFF_PROMISC)
1243 config_reg |= UNICAST_PROMISCUOUS_MODE;
1245 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1246 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1248 set_multicast_list(dev);
1252 /* rx/tx queue initialisation ***********************************************/
1253 static int rxq_init(struct mv643xx_eth_private *mp)
1255 struct rx_queue *rxq = mp->rxq;
1256 struct rx_desc *rx_desc;
1260 rxq->rx_ring_size = mp->default_rx_ring_size;
1262 rxq->rx_desc_count = 0;
1263 rxq->rx_curr_desc = 0;
1264 rxq->rx_used_desc = 0;
1266 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1268 if (size <= mp->rx_desc_sram_size) {
1269 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1270 mp->rx_desc_sram_size);
1271 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1273 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1278 if (rxq->rx_desc_area == NULL) {
1279 dev_printk(KERN_ERR, &mp->dev->dev,
1280 "can't allocate rx ring (%d bytes)\n", size);
1283 memset(rxq->rx_desc_area, 0, size);
1285 rxq->rx_desc_area_size = size;
1286 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1288 if (rxq->rx_skb == NULL) {
1289 dev_printk(KERN_ERR, &mp->dev->dev,
1290 "can't allocate rx skb ring\n");
1294 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1295 for (i = 0; i < rxq->rx_ring_size; i++) {
1296 int nexti = (i + 1) % rxq->rx_ring_size;
1297 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1298 nexti * sizeof(struct rx_desc);
1301 init_timer(&rxq->rx_oom);
1302 rxq->rx_oom.data = (unsigned long)rxq;
1303 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1309 if (size <= mp->rx_desc_sram_size)
1310 iounmap(rxq->rx_desc_area);
1312 dma_free_coherent(NULL, size,
1320 static void rxq_deinit(struct rx_queue *rxq)
1322 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1327 del_timer_sync(&rxq->rx_oom);
1329 for (i = 0; i < rxq->rx_ring_size; i++) {
1330 if (rxq->rx_skb[i]) {
1331 dev_kfree_skb(rxq->rx_skb[i]);
1332 rxq->rx_desc_count--;
1336 if (rxq->rx_desc_count) {
1337 dev_printk(KERN_ERR, &mp->dev->dev,
1338 "error freeing rx ring -- %d skbs stuck\n",
1339 rxq->rx_desc_count);
1342 if (rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1343 iounmap(rxq->rx_desc_area);
1345 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1346 rxq->rx_desc_area, rxq->rx_desc_dma);
1351 static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
1353 int tx_desc_num = mp->tx_ring_size;
1354 struct tx_desc *p_tx_desc;
1357 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1358 p_tx_desc = (struct tx_desc *)mp->tx_desc_area;
1359 for (i = 0; i < tx_desc_num; i++) {
1360 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1361 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1364 mp->tx_curr_desc = 0;
1365 mp->tx_used_desc = 0;
1367 mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1370 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1372 struct mv643xx_eth_private *mp = netdev_priv(dev);
1373 struct tx_desc *desc;
1375 struct sk_buff *skb;
1376 unsigned long flags;
1382 while (mp->tx_desc_count > 0) {
1383 spin_lock_irqsave(&mp->lock, flags);
1385 /* tx_desc_count might have changed before acquiring the lock */
1386 if (mp->tx_desc_count <= 0) {
1387 spin_unlock_irqrestore(&mp->lock, flags);
1391 tx_index = mp->tx_used_desc;
1392 desc = &mp->tx_desc_area[tx_index];
1393 cmd_sts = desc->cmd_sts;
1395 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
1396 spin_unlock_irqrestore(&mp->lock, flags);
1400 mp->tx_used_desc = (tx_index + 1) % mp->tx_ring_size;
1401 mp->tx_desc_count--;
1403 addr = desc->buf_ptr;
1404 count = desc->byte_cnt;
1405 skb = mp->tx_skb[tx_index];
1407 mp->tx_skb[tx_index] = NULL;
1409 if (cmd_sts & ERROR_SUMMARY) {
1410 printk("%s: Error in TX\n", dev->name);
1411 dev->stats.tx_errors++;
1414 spin_unlock_irqrestore(&mp->lock, flags);
1416 if (cmd_sts & TX_FIRST_DESC)
1417 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1419 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1422 dev_kfree_skb_irq(skb);
1430 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1432 struct mv643xx_eth_private *mp = netdev_priv(dev);
1434 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1435 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1436 netif_wake_queue(dev);
1439 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1441 mv643xx_eth_free_tx_descs(dev, 1);
1444 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1446 struct mv643xx_eth_private *mp = netdev_priv(dev);
1448 /* Stop Tx Queues */
1449 mv643xx_eth_port_disable_tx(mp);
1451 /* Free outstanding skb's on TX ring */
1452 mv643xx_eth_free_all_tx_descs(dev);
1454 BUG_ON(mp->tx_used_desc != mp->tx_curr_desc);
1457 if (mp->tx_sram_size)
1458 iounmap(mp->tx_desc_area);
1460 dma_free_coherent(NULL, mp->tx_desc_area_size,
1461 mp->tx_desc_area, mp->tx_desc_dma);
1465 /* netdev ops and related ***************************************************/
1466 static void port_reset(struct mv643xx_eth_private *mp);
1468 static void mv643xx_eth_update_pscr(struct net_device *dev,
1469 struct ethtool_cmd *ecmd)
1471 struct mv643xx_eth_private *mp = netdev_priv(dev);
1472 int port_num = mp->port_num;
1474 unsigned int queues;
1476 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1479 /* clear speed, duplex and rx buffer size fields */
1480 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1481 SET_GMII_SPEED_TO_1000 |
1482 SET_FULL_DUPLEX_MODE |
1483 MAX_RX_PACKET_MASK);
1485 if (ecmd->duplex == DUPLEX_FULL)
1486 n_pscr |= SET_FULL_DUPLEX_MODE;
1488 if (ecmd->speed == SPEED_1000)
1489 n_pscr |= SET_GMII_SPEED_TO_1000 |
1490 MAX_RX_PACKET_9700BYTE;
1492 if (ecmd->speed == SPEED_100)
1493 n_pscr |= SET_MII_SPEED_TO_100;
1494 n_pscr |= MAX_RX_PACKET_1522BYTE;
1497 if (n_pscr != o_pscr) {
1498 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1499 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1501 queues = mv643xx_eth_port_disable_tx(mp);
1503 o_pscr &= ~SERIAL_PORT_ENABLE;
1504 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1505 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1506 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1508 mv643xx_eth_port_enable_tx(mp, queues);
1513 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1515 struct net_device *dev = (struct net_device *)dev_id;
1516 struct mv643xx_eth_private *mp = netdev_priv(dev);
1517 u32 int_cause, int_cause_ext = 0;
1518 unsigned int port_num = mp->port_num;
1520 /* Read interrupt cause registers */
1521 int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1522 if (int_cause & INT_EXT) {
1523 int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
1524 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1525 wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
1528 /* PHY status changed */
1529 if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
1530 struct ethtool_cmd cmd;
1532 if (mii_link_ok(&mp->mii)) {
1533 mii_ethtool_gset(&mp->mii, &cmd);
1534 mv643xx_eth_update_pscr(dev, &cmd);
1535 mv643xx_eth_port_enable_tx(mp, 1);
1536 if (!netif_carrier_ok(dev)) {
1537 netif_carrier_on(dev);
1538 if (mp->tx_ring_size - mp->tx_desc_count >=
1540 netif_wake_queue(dev);
1542 } else if (netif_carrier_ok(dev)) {
1543 netif_stop_queue(dev);
1544 netif_carrier_off(dev);
1548 #ifdef MV643XX_ETH_NAPI
1549 if (int_cause & INT_RX) {
1550 /* schedule the NAPI poll routine to maintain port */
1551 wrl(mp, INT_MASK(port_num), 0x00000000);
1553 /* wait for previous write to complete */
1554 rdl(mp, INT_MASK(port_num));
1556 netif_rx_schedule(dev, &mp->napi);
1559 if (int_cause & INT_RX)
1560 rxq_process(mp->rxq, INT_MAX);
1562 if (int_cause_ext & INT_EXT_TX)
1563 mv643xx_eth_free_completed_tx_descs(dev);
1566 * If no real interrupt occured, exit.
1567 * This can happen when using gigE interrupt coalescing mechanism.
1569 if ((int_cause == 0x0) && (int_cause_ext == 0x0))
1575 static void phy_reset(struct mv643xx_eth_private *mp)
1577 unsigned int phy_reg_data;
1580 read_smi_reg(mp, 0, &phy_reg_data);
1581 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
1582 write_smi_reg(mp, 0, phy_reg_data);
1584 /* wait for PHY to come out of reset */
1587 read_smi_reg(mp, 0, &phy_reg_data);
1588 } while (phy_reg_data & 0x8000);
1591 static void port_start(struct net_device *dev)
1593 struct mv643xx_eth_private *mp = netdev_priv(dev);
1595 struct ethtool_cmd ethtool_cmd;
1599 * Configure basic link parameters.
1601 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1602 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1603 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1604 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1605 DISABLE_AUTO_NEG_SPEED_GMII |
1606 DISABLE_AUTO_NEG_FOR_DUPLEX |
1607 DO_NOT_FORCE_LINK_FAIL |
1608 SERIAL_PORT_CONTROL_RESERVED;
1609 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1610 pscr |= SERIAL_PORT_ENABLE;
1611 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1613 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1615 mv643xx_eth_get_settings(dev, ðtool_cmd);
1617 mv643xx_eth_set_settings(dev, ðtool_cmd);
1619 /* Add the assigned Ethernet address to the port's address table */
1620 uc_addr_set(mp, dev->dev_addr);
1623 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1624 * frames to RX queue #0.
1626 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1629 * Treat BPDUs as normal multicasts, and disable partition mode.
1631 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1634 * Enable the receive queue.
1636 for (i = 0; i < 1; i++) {
1637 struct rx_queue *rxq = mp->rxq;
1638 int off = RXQ_CURRENT_DESC_PTR(mp->port_num);
1641 addr = (u32)rxq->rx_desc_dma;
1642 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1649 wrl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num),
1650 (u32)((struct tx_desc *)mp->tx_desc_dma + mp->tx_curr_desc));
1652 /* Disable port bandwidth limits by clearing MTU register */
1653 wrl(mp, TX_BW_MTU(mp->port_num), 0);
1656 #ifdef MV643XX_ETH_COAL
1657 static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
1660 unsigned int port_num = mp->port_num;
1661 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1663 /* Set RX Coalescing mechanism */
1664 wrl(mp, SDMA_CONFIG(port_num),
1665 ((coal & 0x3fff) << 8) |
1666 (rdl(mp, SDMA_CONFIG(port_num))
1673 static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
1676 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1678 /* Set TX Coalescing mechanism */
1679 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
1684 static void port_init(struct mv643xx_eth_private *mp)
1688 init_mac_tables(mp);
1691 static int mv643xx_eth_open(struct net_device *dev)
1693 struct mv643xx_eth_private *mp = netdev_priv(dev);
1694 unsigned int port_num = mp->port_num;
1698 /* Clear any pending ethernet port interrupts */
1699 wrl(mp, INT_CAUSE(port_num), 0);
1700 wrl(mp, INT_CAUSE_EXT(port_num), 0);
1701 /* wait for previous write to complete */
1702 rdl(mp, INT_CAUSE_EXT(port_num));
1704 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1705 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1707 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1716 rxq_refill(mp->rxq);
1718 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1721 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1723 goto out_free_rx_skb;
1726 /* Allocate TX ring */
1727 mp->tx_desc_count = 0;
1728 size = mp->tx_ring_size * sizeof(struct tx_desc);
1729 mp->tx_desc_area_size = size;
1731 if (mp->tx_sram_size) {
1732 mp->tx_desc_area = ioremap(mp->tx_sram_addr,
1734 mp->tx_desc_dma = mp->tx_sram_addr;
1736 mp->tx_desc_area = dma_alloc_coherent(NULL, size,
1740 if (!mp->tx_desc_area) {
1741 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1744 goto out_free_tx_skb;
1746 BUG_ON((u32) mp->tx_desc_area & 0xf); /* check 16-byte alignment */
1747 memset((void *)mp->tx_desc_area, 0, mp->tx_desc_area_size);
1749 ether_init_tx_desc_ring(mp);
1751 #ifdef MV643XX_ETH_NAPI
1752 napi_enable(&mp->napi);
1757 /* Interrupt Coalescing */
1759 #ifdef MV643XX_ETH_COAL
1760 mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
1763 mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
1765 /* Unmask phy and link status changes interrupts */
1766 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1768 /* Unmask RX buffer and TX end interrupt */
1769 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
1776 rxq_deinit(mp->rxq);
1778 free_irq(dev->irq, dev);
1783 static void port_reset(struct mv643xx_eth_private *mp)
1785 unsigned int port_num = mp->port_num;
1786 unsigned int reg_data;
1788 mv643xx_eth_port_disable_tx(mp);
1789 rxq_disable(mp->rxq);
1791 /* Clear all MIB counters */
1792 clear_mib_counters(mp);
1794 /* Reset the Enable bit in the Configuration Register */
1795 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1796 reg_data &= ~(SERIAL_PORT_ENABLE |
1797 DO_NOT_FORCE_LINK_FAIL |
1799 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
1802 static int mv643xx_eth_stop(struct net_device *dev)
1804 struct mv643xx_eth_private *mp = netdev_priv(dev);
1805 unsigned int port_num = mp->port_num;
1807 /* Mask all interrupts on ethernet port */
1808 wrl(mp, INT_MASK(port_num), 0x00000000);
1809 /* wait for previous write to complete */
1810 rdl(mp, INT_MASK(port_num));
1812 #ifdef MV643XX_ETH_NAPI
1813 napi_disable(&mp->napi);
1815 netif_carrier_off(dev);
1816 netif_stop_queue(dev);
1820 mv643xx_eth_free_tx_rings(dev);
1821 rxq_deinit(mp->rxq);
1823 free_irq(dev->irq, dev);
1828 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1830 struct mv643xx_eth_private *mp = netdev_priv(dev);
1832 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1835 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1837 if ((new_mtu > 9500) || (new_mtu < 64))
1841 if (!netif_running(dev))
1845 * Stop and then re-open the interface. This will allocate RX
1846 * skbs of the new MTU.
1847 * There is a possible danger that the open will not succeed,
1848 * due to memory being full, which might fail the open function.
1850 mv643xx_eth_stop(dev);
1851 if (mv643xx_eth_open(dev)) {
1852 printk(KERN_ERR "%s: Fatal error on opening device\n",
1859 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1861 struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
1863 struct net_device *dev = mp->dev;
1865 if (!netif_running(dev))
1868 netif_stop_queue(dev);
1873 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1874 netif_wake_queue(dev);
1877 static void mv643xx_eth_tx_timeout(struct net_device *dev)
1879 struct mv643xx_eth_private *mp = netdev_priv(dev);
1881 printk(KERN_INFO "%s: TX timeout ", dev->name);
1883 /* Do the reset outside of interrupt context */
1884 schedule_work(&mp->tx_timeout_task);
1887 #ifdef CONFIG_NET_POLL_CONTROLLER
1888 static void mv643xx_eth_netpoll(struct net_device *netdev)
1890 struct mv643xx_eth_private *mp = netdev_priv(netdev);
1891 int port_num = mp->port_num;
1893 wrl(mp, INT_MASK(port_num), 0x00000000);
1894 /* wait for previous write to complete */
1895 rdl(mp, INT_MASK(port_num));
1897 mv643xx_eth_int_handler(netdev->irq, netdev);
1899 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
1903 static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
1905 struct mv643xx_eth_private *mp = netdev_priv(dev);
1908 read_smi_reg(mp, location, &val);
1912 static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
1914 struct mv643xx_eth_private *mp = netdev_priv(dev);
1915 write_smi_reg(mp, location, val);
1919 /* platform glue ************************************************************/
1921 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1922 struct mbus_dram_target_info *dram)
1924 void __iomem *base = msp->base;
1929 for (i = 0; i < 6; i++) {
1930 writel(0, base + WINDOW_BASE(i));
1931 writel(0, base + WINDOW_SIZE(i));
1933 writel(0, base + WINDOW_REMAP_HIGH(i));
1939 for (i = 0; i < dram->num_cs; i++) {
1940 struct mbus_dram_window *cs = dram->cs + i;
1942 writel((cs->base & 0xffff0000) |
1943 (cs->mbus_attr << 8) |
1944 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1945 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1947 win_enable &= ~(1 << i);
1948 win_protect |= 3 << (2 * i);
1951 writel(win_enable, base + WINDOW_BAR_ENABLE);
1952 msp->win_protect = win_protect;
1955 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1957 static int mv643xx_eth_version_printed = 0;
1958 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
1959 struct mv643xx_eth_shared_private *msp;
1960 struct resource *res;
1963 if (!mv643xx_eth_version_printed++)
1964 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1967 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1972 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
1975 memset(msp, 0, sizeof(*msp));
1977 msp->base = ioremap(res->start, res->end - res->start + 1);
1978 if (msp->base == NULL)
1981 spin_lock_init(&msp->phy_lock);
1982 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
1984 platform_set_drvdata(pdev, msp);
1987 * (Re-)program MBUS remapping windows if we are asked to.
1989 if (pd != NULL && pd->dram != NULL)
1990 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2000 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2002 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2010 static struct platform_driver mv643xx_eth_shared_driver = {
2011 .probe = mv643xx_eth_shared_probe,
2012 .remove = mv643xx_eth_shared_remove,
2014 .name = MV643XX_ETH_SHARED_NAME,
2015 .owner = THIS_MODULE,
2019 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2022 int addr_shift = 5 * mp->port_num;
2024 reg_data = rdl(mp, PHY_ADDR);
2025 reg_data &= ~(0x1f << addr_shift);
2026 reg_data |= (phy_addr & 0x1f) << addr_shift;
2027 wrl(mp, PHY_ADDR, reg_data);
2030 static int phy_addr_get(struct mv643xx_eth_private *mp)
2032 unsigned int reg_data;
2034 reg_data = rdl(mp, PHY_ADDR);
2036 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2039 static int phy_detect(struct mv643xx_eth_private *mp)
2041 unsigned int phy_reg_data0;
2044 read_smi_reg(mp, 0, &phy_reg_data0);
2045 auto_neg = phy_reg_data0 & 0x1000;
2046 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2047 write_smi_reg(mp, 0, phy_reg_data0);
2049 read_smi_reg(mp, 0, &phy_reg_data0);
2050 if ((phy_reg_data0 & 0x1000) == auto_neg)
2051 return -ENODEV; /* change didn't take */
2053 phy_reg_data0 ^= 0x1000;
2054 write_smi_reg(mp, 0, phy_reg_data0);
2058 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2059 int speed, int duplex,
2060 struct ethtool_cmd *cmd)
2062 struct mv643xx_eth_private *mp = netdev_priv(dev);
2064 memset(cmd, 0, sizeof(*cmd));
2066 cmd->port = PORT_MII;
2067 cmd->transceiver = XCVR_INTERNAL;
2068 cmd->phy_address = phy_address;
2071 cmd->autoneg = AUTONEG_ENABLE;
2072 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2073 cmd->speed = SPEED_100;
2074 cmd->advertising = ADVERTISED_10baseT_Half |
2075 ADVERTISED_10baseT_Full |
2076 ADVERTISED_100baseT_Half |
2077 ADVERTISED_100baseT_Full;
2078 if (mp->mii.supports_gmii)
2079 cmd->advertising |= ADVERTISED_1000baseT_Full;
2081 cmd->autoneg = AUTONEG_DISABLE;
2083 cmd->duplex = duplex;
2087 static int mv643xx_eth_probe(struct platform_device *pdev)
2089 struct mv643xx_eth_platform_data *pd;
2091 struct mv643xx_eth_private *mp;
2092 struct net_device *dev;
2094 struct resource *res;
2096 struct ethtool_cmd cmd;
2097 int duplex = DUPLEX_HALF;
2098 int speed = 0; /* default to auto-negotiation */
2099 DECLARE_MAC_BUF(mac);
2101 pd = pdev->dev.platform_data;
2103 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2107 if (pd->shared == NULL) {
2108 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2112 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2116 platform_set_drvdata(pdev, dev);
2118 mp = netdev_priv(dev);
2120 #ifdef MV643XX_ETH_NAPI
2121 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2124 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2126 dev->irq = res->start;
2128 dev->open = mv643xx_eth_open;
2129 dev->stop = mv643xx_eth_stop;
2130 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2131 dev->set_mac_address = mv643xx_eth_set_mac_address;
2132 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2134 /* No need to Tx Timeout */
2135 dev->tx_timeout = mv643xx_eth_tx_timeout;
2137 #ifdef CONFIG_NET_POLL_CONTROLLER
2138 dev->poll_controller = mv643xx_eth_netpoll;
2141 dev->watchdog_timeo = 2 * HZ;
2143 dev->change_mtu = mv643xx_eth_change_mtu;
2144 dev->do_ioctl = mv643xx_eth_do_ioctl;
2145 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2147 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2148 #ifdef MAX_SKB_FRAGS
2150 * Zero copy can only work if we use Discovery II memory. Else, we will
2151 * have to map the buffers to ISA memory which is only 16 MB
2153 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2157 /* Configure the timeout task */
2158 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2160 spin_lock_init(&mp->lock);
2162 mp->shared = platform_get_drvdata(pd->shared);
2163 port_num = mp->port_num = pd->port_number;
2165 if (mp->shared->win_protect)
2166 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2168 mp->shared_smi = mp->shared;
2169 if (pd->shared_smi != NULL)
2170 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2172 /* set default config values */
2173 uc_addr_get(mp, dev->dev_addr);
2174 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2176 if (is_valid_ether_addr(pd->mac_addr))
2177 memcpy(dev->dev_addr, pd->mac_addr, 6);
2179 if (pd->phy_addr || pd->force_phy_addr)
2180 phy_addr_set(mp, pd->phy_addr);
2182 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2183 if (pd->rx_queue_size)
2184 mp->default_rx_ring_size = pd->rx_queue_size;
2186 if (pd->tx_queue_size)
2187 mp->tx_ring_size = pd->tx_queue_size;
2189 if (pd->tx_sram_size) {
2190 mp->tx_sram_size = pd->tx_sram_size;
2191 mp->tx_sram_addr = pd->tx_sram_addr;
2194 if (pd->rx_sram_size) {
2195 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2196 mp->rx_desc_sram_size = pd->rx_sram_size;
2199 duplex = pd->duplex;
2202 /* Hook up MII support for ethtool */
2204 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2205 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2206 mp->mii.phy_id = phy_addr_get(mp);
2207 mp->mii.phy_id_mask = 0x3f;
2208 mp->mii.reg_num_mask = 0x1f;
2210 err = phy_detect(mp);
2212 pr_debug("%s: No PHY detected at addr %d\n",
2213 dev->name, phy_addr_get(mp));
2218 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2219 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2220 mv643xx_eth_update_pscr(dev, &cmd);
2221 mv643xx_eth_set_settings(dev, &cmd);
2223 SET_NETDEV_DEV(dev, &pdev->dev);
2224 err = register_netdev(dev);
2230 "%s: port %d with MAC address %s\n",
2231 dev->name, port_num, print_mac(mac, p));
2233 if (dev->features & NETIF_F_SG)
2234 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
2236 if (dev->features & NETIF_F_IP_CSUM)
2237 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2240 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2241 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2244 #ifdef MV643XX_ETH_COAL
2245 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2249 #ifdef MV643XX_ETH_NAPI
2250 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2253 if (mp->tx_sram_size > 0)
2254 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
2264 static int mv643xx_eth_remove(struct platform_device *pdev)
2266 struct net_device *dev = platform_get_drvdata(pdev);
2268 unregister_netdev(dev);
2269 flush_scheduled_work();
2272 platform_set_drvdata(pdev, NULL);
2276 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2278 struct net_device *dev = platform_get_drvdata(pdev);
2279 struct mv643xx_eth_private *mp = netdev_priv(dev);
2280 unsigned int port_num = mp->port_num;
2282 /* Mask all interrupts on ethernet port */
2283 wrl(mp, INT_MASK(port_num), 0);
2284 rdl(mp, INT_MASK(port_num));
2289 static struct platform_driver mv643xx_eth_driver = {
2290 .probe = mv643xx_eth_probe,
2291 .remove = mv643xx_eth_remove,
2292 .shutdown = mv643xx_eth_shutdown,
2294 .name = MV643XX_ETH_NAME,
2295 .owner = THIS_MODULE,
2299 static int __init mv643xx_eth_init_module(void)
2303 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2305 rc = platform_driver_register(&mv643xx_eth_driver);
2307 platform_driver_unregister(&mv643xx_eth_shared_driver);
2312 static void __exit mv643xx_eth_cleanup_module(void)
2314 platform_driver_unregister(&mv643xx_eth_driver);
2315 platform_driver_unregister(&mv643xx_eth_shared_driver);
2318 module_init(mv643xx_eth_init_module);
2319 module_exit(mv643xx_eth_cleanup_module);
2321 MODULE_LICENSE("GPL");
2322 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2323 " and Dale Farnsworth");
2324 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2325 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
2326 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);