2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
62 * Registers shared between all ports.
64 #define PHY_ADDR 0x0000
65 #define SMI_REG 0x0004
66 #define SMI_BUSY 0x10000000
67 #define SMI_READ_VALID 0x08000000
68 #define SMI_OPCODE_READ 0x04000000
69 #define SMI_OPCODE_WRITE 0x00000000
70 #define ERR_INT_CAUSE 0x0080
71 #define ERR_INT_SMI_DONE 0x00000010
72 #define ERR_INT_MASK 0x0084
73 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76 #define WINDOW_BAR_ENABLE 0x0290
77 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
90 #define TX_FIFO_EMPTY 0x00000400
91 #define TX_IN_PROGRESS 0x00000080
92 #define PORT_SPEED_MASK 0x00000030
93 #define PORT_SPEED_1000 0x00000010
94 #define PORT_SPEED_100 0x00000020
95 #define PORT_SPEED_10 0x00000000
96 #define FLOW_CONTROL_ENABLED 0x00000008
97 #define FULL_DUPLEX 0x00000004
98 #define LINK_UP 0x00000002
99 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
100 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
102 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
103 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
104 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
105 #define INT_TX_END 0x07f80000
106 #define INT_RX 0x000003fc
107 #define INT_EXT 0x00000002
108 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
109 #define INT_EXT_LINK_PHY 0x00110000
110 #define INT_EXT_TX 0x000000ff
111 #define INT_MASK(p) (0x0468 + ((p) << 10))
112 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
114 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
118 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
119 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
120 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_16_64BIT (4 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_16_64BIT (4 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 128
169 #define DEFAULT_TX_QUEUE_SIZE 256
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
232 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
233 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
235 #define TX_IHL_SHIFT 11
238 /* global *******************************************************************/
239 struct mv643xx_eth_shared_private {
241 * Ethernet controller base address.
246 * Points at the right SMI instance to use.
248 struct mv643xx_eth_shared_private *smi;
251 * Protects access to SMI_REG, which is shared between ports.
253 struct mutex phy_lock;
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
262 wait_queue_head_t smi_busy_wait;
265 * Per-port MBUS window access register value.
270 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
277 #define TX_BW_CONTROL_ABSENT 0
278 #define TX_BW_CONTROL_OLD_LAYOUT 1
279 #define TX_BW_CONTROL_NEW_LAYOUT 2
282 /* per-port *****************************************************************/
283 struct mib_counters {
284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
304 u32 good_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
310 u32 mac_receive_error;
325 struct rx_desc *rx_desc_area;
326 dma_addr_t rx_desc_dma;
327 int rx_desc_area_size;
328 struct sk_buff **rx_skb;
340 struct tx_desc *tx_desc_area;
341 dma_addr_t tx_desc_dma;
342 int tx_desc_area_size;
344 struct sk_buff_head tx_skb;
346 unsigned long tx_packets;
347 unsigned long tx_bytes;
348 unsigned long tx_dropped;
351 struct mv643xx_eth_private {
352 struct mv643xx_eth_shared_private *shared;
355 struct net_device *dev;
359 struct mib_counters mib_counters;
360 struct work_struct tx_timeout_task;
361 struct mii_if_info mii;
363 struct napi_struct napi;
374 int default_rx_ring_size;
375 unsigned long rx_desc_sram_addr;
376 int rx_desc_sram_size;
378 struct timer_list rx_oom;
379 struct rx_queue rxq[8];
384 int default_tx_ring_size;
385 unsigned long tx_desc_sram_addr;
386 int tx_desc_sram_size;
388 struct tx_queue txq[8];
392 /* port register accessors **************************************************/
393 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
395 return readl(mp->shared->base + offset);
398 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
400 writel(data, mp->shared->base + offset);
404 /* rxq/txq helper functions *************************************************/
405 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
407 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
410 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
412 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
415 static void rxq_enable(struct rx_queue *rxq)
417 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
418 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
421 static void rxq_disable(struct rx_queue *rxq)
423 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
424 u8 mask = 1 << rxq->index;
426 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
427 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
431 static void txq_reset_hw_ptr(struct tx_queue *txq)
433 struct mv643xx_eth_private *mp = txq_to_mp(txq);
434 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
437 addr = (u32)txq->tx_desc_dma;
438 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
442 static void txq_enable(struct tx_queue *txq)
444 struct mv643xx_eth_private *mp = txq_to_mp(txq);
445 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
448 static void txq_disable(struct tx_queue *txq)
450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
451 u8 mask = 1 << txq->index;
453 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
454 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
458 static void txq_maybe_wake(struct tx_queue *txq)
460 struct mv643xx_eth_private *mp = txq_to_mp(txq);
461 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
463 if (netif_tx_queue_stopped(nq)) {
464 __netif_tx_lock(nq, smp_processor_id());
465 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
466 netif_tx_wake_queue(nq);
467 __netif_tx_unlock(nq);
472 /* rx napi ******************************************************************/
473 static int rxq_process(struct rx_queue *rxq, int budget)
475 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
476 struct net_device_stats *stats = &mp->dev->stats;
480 while (rx < budget && rxq->rx_desc_count) {
481 struct rx_desc *rx_desc;
482 unsigned int cmd_sts;
486 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
488 cmd_sts = rx_desc->cmd_sts;
489 if (cmd_sts & BUFFER_OWNED_BY_DMA)
493 skb = rxq->rx_skb[rxq->rx_curr_desc];
494 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
497 if (rxq->rx_curr_desc == rxq->rx_ring_size)
498 rxq->rx_curr_desc = 0;
500 dma_unmap_single(NULL, rx_desc->buf_ptr,
501 rx_desc->buf_size, DMA_FROM_DEVICE);
502 rxq->rx_desc_count--;
505 mp->work_rx_refill |= 1 << rxq->index;
507 byte_cnt = rx_desc->byte_cnt;
512 * Note that the descriptor byte count includes 2 dummy
513 * bytes automatically inserted by the hardware at the
514 * start of the packet (which we don't count), and a 4
515 * byte CRC at the end of the packet (which we do count).
518 stats->rx_bytes += byte_cnt - 2;
521 * In case we received a packet without first / last bits
522 * on, or the error summary bit is set, the packet needs
525 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
526 (RX_FIRST_DESC | RX_LAST_DESC))
527 || (cmd_sts & ERROR_SUMMARY)) {
530 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
531 (RX_FIRST_DESC | RX_LAST_DESC)) {
533 dev_printk(KERN_ERR, &mp->dev->dev,
534 "received packet spanning "
535 "multiple descriptors\n");
538 if (cmd_sts & ERROR_SUMMARY)
544 * The -4 is for the CRC in the trailer of the
547 skb_put(skb, byte_cnt - 2 - 4);
549 if (cmd_sts & LAYER_4_CHECKSUM_OK)
550 skb->ip_summed = CHECKSUM_UNNECESSARY;
551 skb->protocol = eth_type_trans(skb, mp->dev);
552 netif_receive_skb(skb);
555 mp->dev->last_rx = jiffies;
559 mp->work_rx &= ~(1 << rxq->index);
564 static int rxq_refill(struct rx_queue *rxq, int budget)
566 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
571 * Reserve 2+14 bytes for an ethernet header (the hardware
572 * automatically prepends 2 bytes of dummy data to each
573 * received packet), 16 bytes for up to four VLAN tags, and
574 * 4 bytes for the trailing FCS -- 36 bytes total.
576 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
579 * Make sure that the skb size is a multiple of 8 bytes, as
580 * the lower three bits of the receive descriptor's buffer
581 * size field are ignored by the hardware.
583 skb_size = (skb_size + 7) & ~7;
586 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
591 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
593 mp->work_rx_oom |= 1 << rxq->index;
597 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
599 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
602 rxq->rx_desc_count++;
604 rx = rxq->rx_used_desc++;
605 if (rxq->rx_used_desc == rxq->rx_ring_size)
606 rxq->rx_used_desc = 0;
608 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
609 skb_size, DMA_FROM_DEVICE);
610 rxq->rx_desc_area[rx].buf_size = skb_size;
611 rxq->rx_skb[rx] = skb;
613 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
618 * The hardware automatically prepends 2 bytes of
619 * dummy data to each received packet, so that the
620 * IP header ends up 16-byte aligned.
625 if (refilled < budget)
626 mp->work_rx_refill &= ~(1 << rxq->index);
633 /* tx ***********************************************************************/
634 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
638 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
639 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
640 if (fragp->size <= 8 && fragp->page_offset & 7)
647 static int txq_alloc_desc_index(struct tx_queue *txq)
651 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
653 tx_desc_curr = txq->tx_curr_desc++;
654 if (txq->tx_curr_desc == txq->tx_ring_size)
655 txq->tx_curr_desc = 0;
657 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
662 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
664 int nr_frags = skb_shinfo(skb)->nr_frags;
667 for (frag = 0; frag < nr_frags; frag++) {
668 skb_frag_t *this_frag;
670 struct tx_desc *desc;
672 this_frag = &skb_shinfo(skb)->frags[frag];
673 tx_index = txq_alloc_desc_index(txq);
674 desc = &txq->tx_desc_area[tx_index];
677 * The last fragment will generate an interrupt
678 * which will free the skb on TX completion.
680 if (frag == nr_frags - 1) {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
682 ZERO_PADDING | TX_LAST_DESC |
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
689 desc->byte_cnt = this_frag->size;
690 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
691 this_frag->page_offset,
697 static inline __be16 sum16_as_be(__sum16 sum)
699 return (__force __be16)sum;
702 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
704 struct mv643xx_eth_private *mp = txq_to_mp(txq);
705 int nr_frags = skb_shinfo(skb)->nr_frags;
707 struct tx_desc *desc;
712 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
715 if (skb->ip_summed == CHECKSUM_PARTIAL) {
718 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
719 skb->protocol != htons(ETH_P_8021Q));
721 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
722 if (unlikely(tag_bytes & ~12)) {
723 if (skb_checksum_help(skb) == 0)
730 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
732 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
734 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
736 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
738 switch (ip_hdr(skb)->protocol) {
740 cmd_sts |= UDP_FRAME;
741 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
744 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
751 /* Errata BTS #50, IHL must be 5 if no HW checksum */
752 cmd_sts |= 5 << TX_IHL_SHIFT;
755 tx_index = txq_alloc_desc_index(txq);
756 desc = &txq->tx_desc_area[tx_index];
759 txq_submit_frag_skb(txq, skb);
760 length = skb_headlen(skb);
762 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
766 desc->l4i_chk = l4i_chk;
767 desc->byte_cnt = length;
768 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
770 __skb_queue_tail(&txq->tx_skb, skb);
772 /* ensure all other descriptors are written before first cmd_sts */
774 desc->cmd_sts = cmd_sts;
776 /* clear TX_END status */
777 mp->work_tx_end &= ~(1 << txq->index);
779 /* ensure all descriptors are written before poking hardware */
783 txq->tx_desc_count += nr_frags + 1;
788 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
790 struct mv643xx_eth_private *mp = netdev_priv(dev);
792 struct tx_queue *txq;
793 struct netdev_queue *nq;
795 queue = skb_get_queue_mapping(skb);
796 txq = mp->txq + queue;
797 nq = netdev_get_tx_queue(dev, queue);
799 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
801 dev_printk(KERN_DEBUG, &dev->dev,
802 "failed to linearize skb with tiny "
803 "unaligned fragment\n");
804 return NETDEV_TX_BUSY;
807 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
809 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
814 if (!txq_submit_skb(txq, skb)) {
817 txq->tx_bytes += skb->len;
819 dev->trans_start = jiffies;
821 entries_left = txq->tx_ring_size - txq->tx_desc_count;
822 if (entries_left < MAX_SKB_FRAGS + 1)
823 netif_tx_stop_queue(nq);
830 /* tx napi ******************************************************************/
831 static void txq_kick(struct tx_queue *txq)
833 struct mv643xx_eth_private *mp = txq_to_mp(txq);
834 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
838 __netif_tx_lock(nq, smp_processor_id());
840 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
843 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
844 expected_ptr = (u32)txq->tx_desc_dma +
845 txq->tx_curr_desc * sizeof(struct tx_desc);
847 if (hw_desc_ptr != expected_ptr)
851 __netif_tx_unlock(nq);
853 mp->work_tx_end &= ~(1 << txq->index);
856 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
858 struct mv643xx_eth_private *mp = txq_to_mp(txq);
859 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
862 __netif_tx_lock(nq, smp_processor_id());
865 while (reclaimed < budget && txq->tx_desc_count > 0) {
867 struct tx_desc *desc;
871 tx_index = txq->tx_used_desc;
872 desc = &txq->tx_desc_area[tx_index];
873 cmd_sts = desc->cmd_sts;
875 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
878 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
881 txq->tx_used_desc = tx_index + 1;
882 if (txq->tx_used_desc == txq->tx_ring_size)
883 txq->tx_used_desc = 0;
886 txq->tx_desc_count--;
889 if (cmd_sts & TX_LAST_DESC)
890 skb = __skb_dequeue(&txq->tx_skb);
892 if (cmd_sts & ERROR_SUMMARY) {
893 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
894 mp->dev->stats.tx_errors++;
897 if (cmd_sts & TX_FIRST_DESC) {
898 dma_unmap_single(NULL, desc->buf_ptr,
899 desc->byte_cnt, DMA_TO_DEVICE);
901 dma_unmap_page(NULL, desc->buf_ptr,
902 desc->byte_cnt, DMA_TO_DEVICE);
909 __netif_tx_unlock(nq);
911 if (reclaimed < budget)
912 mp->work_tx &= ~(1 << txq->index);
918 /* tx rate control **********************************************************/
920 * Set total maximum TX rate (shared by all TX queues for this port)
921 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
923 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
929 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
930 if (token_rate > 1023)
933 mtu = (mp->dev->mtu + 255) >> 8;
937 bucket_size = (burst + 255) >> 8;
938 if (bucket_size > 65535)
941 switch (mp->shared->tx_bw_control) {
942 case TX_BW_CONTROL_OLD_LAYOUT:
943 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
944 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
945 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
947 case TX_BW_CONTROL_NEW_LAYOUT:
948 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
949 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
950 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
955 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
957 struct mv643xx_eth_private *mp = txq_to_mp(txq);
961 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
962 if (token_rate > 1023)
965 bucket_size = (burst + 255) >> 8;
966 if (bucket_size > 65535)
969 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
970 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
971 (bucket_size << 10) | token_rate);
974 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
976 struct mv643xx_eth_private *mp = txq_to_mp(txq);
981 * Turn on fixed priority mode.
984 switch (mp->shared->tx_bw_control) {
985 case TX_BW_CONTROL_OLD_LAYOUT:
986 off = TXQ_FIX_PRIO_CONF(mp->port_num);
988 case TX_BW_CONTROL_NEW_LAYOUT:
989 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
995 val |= 1 << txq->index;
1000 static void txq_set_wrr(struct tx_queue *txq, int weight)
1002 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1007 * Turn off fixed priority mode.
1010 switch (mp->shared->tx_bw_control) {
1011 case TX_BW_CONTROL_OLD_LAYOUT:
1012 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1014 case TX_BW_CONTROL_NEW_LAYOUT:
1015 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1021 val &= ~(1 << txq->index);
1025 * Configure WRR weight for this queue.
1027 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1030 val = (val & ~0xff) | (weight & 0xff);
1036 /* mii management interface *************************************************/
1037 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1039 struct mv643xx_eth_shared_private *msp = dev_id;
1041 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1042 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1043 wake_up(&msp->smi_busy_wait);
1050 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1052 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1055 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1057 if (msp->err_interrupt == NO_IRQ) {
1060 for (i = 0; !smi_is_done(msp); i++) {
1069 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1070 msecs_to_jiffies(100)))
1076 static int smi_reg_read(struct mv643xx_eth_private *mp,
1077 unsigned int addr, unsigned int reg)
1079 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1080 void __iomem *smi_reg = msp->base + SMI_REG;
1083 mutex_lock(&msp->phy_lock);
1085 if (smi_wait_ready(msp)) {
1086 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1091 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1093 if (smi_wait_ready(msp)) {
1094 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1099 ret = readl(smi_reg);
1100 if (!(ret & SMI_READ_VALID)) {
1101 printk("%s: SMI bus read not valid\n", mp->dev->name);
1109 mutex_unlock(&msp->phy_lock);
1114 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1115 unsigned int reg, unsigned int value)
1117 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1118 void __iomem *smi_reg = msp->base + SMI_REG;
1120 mutex_lock(&msp->phy_lock);
1122 if (smi_wait_ready(msp)) {
1123 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1124 mutex_unlock(&msp->phy_lock);
1128 writel(SMI_OPCODE_WRITE | (reg << 21) |
1129 (addr << 16) | (value & 0xffff), smi_reg);
1131 mutex_unlock(&msp->phy_lock);
1137 /* statistics ***************************************************************/
1138 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1140 struct mv643xx_eth_private *mp = netdev_priv(dev);
1141 struct net_device_stats *stats = &dev->stats;
1142 unsigned long tx_packets = 0;
1143 unsigned long tx_bytes = 0;
1144 unsigned long tx_dropped = 0;
1147 for (i = 0; i < mp->txq_count; i++) {
1148 struct tx_queue *txq = mp->txq + i;
1150 tx_packets += txq->tx_packets;
1151 tx_bytes += txq->tx_bytes;
1152 tx_dropped += txq->tx_dropped;
1155 stats->tx_packets = tx_packets;
1156 stats->tx_bytes = tx_bytes;
1157 stats->tx_dropped = tx_dropped;
1162 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1164 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1167 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1171 for (i = 0; i < 0x80; i += 4)
1175 static void mib_counters_update(struct mv643xx_eth_private *mp)
1177 struct mib_counters *p = &mp->mib_counters;
1179 p->good_octets_received += mib_read(mp, 0x00);
1180 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1181 p->bad_octets_received += mib_read(mp, 0x08);
1182 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1183 p->good_frames_received += mib_read(mp, 0x10);
1184 p->bad_frames_received += mib_read(mp, 0x14);
1185 p->broadcast_frames_received += mib_read(mp, 0x18);
1186 p->multicast_frames_received += mib_read(mp, 0x1c);
1187 p->frames_64_octets += mib_read(mp, 0x20);
1188 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1189 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1190 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1191 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1192 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1193 p->good_octets_sent += mib_read(mp, 0x38);
1194 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1195 p->good_frames_sent += mib_read(mp, 0x40);
1196 p->excessive_collision += mib_read(mp, 0x44);
1197 p->multicast_frames_sent += mib_read(mp, 0x48);
1198 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1199 p->unrec_mac_control_received += mib_read(mp, 0x50);
1200 p->fc_sent += mib_read(mp, 0x54);
1201 p->good_fc_received += mib_read(mp, 0x58);
1202 p->bad_fc_received += mib_read(mp, 0x5c);
1203 p->undersize_received += mib_read(mp, 0x60);
1204 p->fragments_received += mib_read(mp, 0x64);
1205 p->oversize_received += mib_read(mp, 0x68);
1206 p->jabber_received += mib_read(mp, 0x6c);
1207 p->mac_receive_error += mib_read(mp, 0x70);
1208 p->bad_crc_event += mib_read(mp, 0x74);
1209 p->collision += mib_read(mp, 0x78);
1210 p->late_collision += mib_read(mp, 0x7c);
1214 /* ethtool ******************************************************************/
1215 struct mv643xx_eth_stats {
1216 char stat_string[ETH_GSTRING_LEN];
1223 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1224 offsetof(struct net_device, stats.m), -1 }
1226 #define MIBSTAT(m) \
1227 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1228 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1230 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1239 MIBSTAT(good_octets_received),
1240 MIBSTAT(bad_octets_received),
1241 MIBSTAT(internal_mac_transmit_err),
1242 MIBSTAT(good_frames_received),
1243 MIBSTAT(bad_frames_received),
1244 MIBSTAT(broadcast_frames_received),
1245 MIBSTAT(multicast_frames_received),
1246 MIBSTAT(frames_64_octets),
1247 MIBSTAT(frames_65_to_127_octets),
1248 MIBSTAT(frames_128_to_255_octets),
1249 MIBSTAT(frames_256_to_511_octets),
1250 MIBSTAT(frames_512_to_1023_octets),
1251 MIBSTAT(frames_1024_to_max_octets),
1252 MIBSTAT(good_octets_sent),
1253 MIBSTAT(good_frames_sent),
1254 MIBSTAT(excessive_collision),
1255 MIBSTAT(multicast_frames_sent),
1256 MIBSTAT(broadcast_frames_sent),
1257 MIBSTAT(unrec_mac_control_received),
1259 MIBSTAT(good_fc_received),
1260 MIBSTAT(bad_fc_received),
1261 MIBSTAT(undersize_received),
1262 MIBSTAT(fragments_received),
1263 MIBSTAT(oversize_received),
1264 MIBSTAT(jabber_received),
1265 MIBSTAT(mac_receive_error),
1266 MIBSTAT(bad_crc_event),
1268 MIBSTAT(late_collision),
1271 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1273 struct mv643xx_eth_private *mp = netdev_priv(dev);
1276 err = mii_ethtool_gset(&mp->mii, cmd);
1279 * The MAC does not support 1000baseT_Half.
1281 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1282 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1287 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1289 struct mv643xx_eth_private *mp = netdev_priv(dev);
1292 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1294 cmd->supported = SUPPORTED_MII;
1295 cmd->advertising = ADVERTISED_MII;
1296 switch (port_status & PORT_SPEED_MASK) {
1298 cmd->speed = SPEED_10;
1300 case PORT_SPEED_100:
1301 cmd->speed = SPEED_100;
1303 case PORT_SPEED_1000:
1304 cmd->speed = SPEED_1000;
1310 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1311 cmd->port = PORT_MII;
1312 cmd->phy_address = 0;
1313 cmd->transceiver = XCVR_INTERNAL;
1314 cmd->autoneg = AUTONEG_DISABLE;
1321 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1323 struct mv643xx_eth_private *mp = netdev_priv(dev);
1326 * The MAC does not support 1000baseT_Half.
1328 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1330 return mii_ethtool_sset(&mp->mii, cmd);
1333 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1338 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1339 struct ethtool_drvinfo *drvinfo)
1341 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1342 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1343 strncpy(drvinfo->fw_version, "N/A", 32);
1344 strncpy(drvinfo->bus_info, "platform", 32);
1345 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1348 static int mv643xx_eth_nway_reset(struct net_device *dev)
1350 struct mv643xx_eth_private *mp = netdev_priv(dev);
1352 return mii_nway_restart(&mp->mii);
1355 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1360 static u32 mv643xx_eth_get_link(struct net_device *dev)
1362 struct mv643xx_eth_private *mp = netdev_priv(dev);
1364 return mii_link_ok(&mp->mii);
1367 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1372 static void mv643xx_eth_get_strings(struct net_device *dev,
1373 uint32_t stringset, uint8_t *data)
1377 if (stringset == ETH_SS_STATS) {
1378 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1379 memcpy(data + i * ETH_GSTRING_LEN,
1380 mv643xx_eth_stats[i].stat_string,
1386 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1387 struct ethtool_stats *stats,
1390 struct mv643xx_eth_private *mp = netdev_priv(dev);
1393 mv643xx_eth_get_stats(dev);
1394 mib_counters_update(mp);
1396 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1397 const struct mv643xx_eth_stats *stat;
1400 stat = mv643xx_eth_stats + i;
1402 if (stat->netdev_off >= 0)
1403 p = ((void *)mp->dev) + stat->netdev_off;
1405 p = ((void *)mp) + stat->mp_off;
1407 data[i] = (stat->sizeof_stat == 8) ?
1408 *(uint64_t *)p : *(uint32_t *)p;
1412 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1414 if (sset == ETH_SS_STATS)
1415 return ARRAY_SIZE(mv643xx_eth_stats);
1420 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1421 .get_settings = mv643xx_eth_get_settings,
1422 .set_settings = mv643xx_eth_set_settings,
1423 .get_drvinfo = mv643xx_eth_get_drvinfo,
1424 .nway_reset = mv643xx_eth_nway_reset,
1425 .get_link = mv643xx_eth_get_link,
1426 .set_sg = ethtool_op_set_sg,
1427 .get_strings = mv643xx_eth_get_strings,
1428 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1429 .get_sset_count = mv643xx_eth_get_sset_count,
1432 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1433 .get_settings = mv643xx_eth_get_settings_phyless,
1434 .set_settings = mv643xx_eth_set_settings_phyless,
1435 .get_drvinfo = mv643xx_eth_get_drvinfo,
1436 .nway_reset = mv643xx_eth_nway_reset_phyless,
1437 .get_link = mv643xx_eth_get_link_phyless,
1438 .set_sg = ethtool_op_set_sg,
1439 .get_strings = mv643xx_eth_get_strings,
1440 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1441 .get_sset_count = mv643xx_eth_get_sset_count,
1445 /* address handling *********************************************************/
1446 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1451 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1452 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1454 addr[0] = (mac_h >> 24) & 0xff;
1455 addr[1] = (mac_h >> 16) & 0xff;
1456 addr[2] = (mac_h >> 8) & 0xff;
1457 addr[3] = mac_h & 0xff;
1458 addr[4] = (mac_l >> 8) & 0xff;
1459 addr[5] = mac_l & 0xff;
1462 static void init_mac_tables(struct mv643xx_eth_private *mp)
1466 for (i = 0; i < 0x100; i += 4) {
1467 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1468 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1471 for (i = 0; i < 0x10; i += 4)
1472 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1475 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1476 int table, unsigned char entry)
1478 unsigned int table_reg;
1480 /* Set "accepts frame bit" at specified table entry */
1481 table_reg = rdl(mp, table + (entry & 0xfc));
1482 table_reg |= 0x01 << (8 * (entry & 3));
1483 wrl(mp, table + (entry & 0xfc), table_reg);
1486 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1492 mac_l = (addr[4] << 8) | addr[5];
1493 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1495 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1496 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1498 table = UNICAST_TABLE(mp->port_num);
1499 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1502 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1504 struct mv643xx_eth_private *mp = netdev_priv(dev);
1506 /* +2 is for the offset of the HW addr type */
1507 memcpy(dev->dev_addr, addr + 2, 6);
1509 init_mac_tables(mp);
1510 uc_addr_set(mp, dev->dev_addr);
1515 static int addr_crc(unsigned char *addr)
1520 for (i = 0; i < 6; i++) {
1523 crc = (crc ^ addr[i]) << 8;
1524 for (j = 7; j >= 0; j--) {
1525 if (crc & (0x100 << j))
1533 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1535 struct mv643xx_eth_private *mp = netdev_priv(dev);
1537 struct dev_addr_list *addr;
1540 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1541 if (dev->flags & IFF_PROMISC)
1542 port_config |= UNICAST_PROMISCUOUS_MODE;
1544 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1545 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1547 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1548 int port_num = mp->port_num;
1549 u32 accept = 0x01010101;
1551 for (i = 0; i < 0x100; i += 4) {
1552 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1553 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1558 for (i = 0; i < 0x100; i += 4) {
1559 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1560 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1563 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1564 u8 *a = addr->da_addr;
1567 if (addr->da_addrlen != 6)
1570 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1571 table = SPECIAL_MCAST_TABLE(mp->port_num);
1572 set_filter_table_entry(mp, table, a[5]);
1574 int crc = addr_crc(a);
1576 table = OTHER_MCAST_TABLE(mp->port_num);
1577 set_filter_table_entry(mp, table, crc);
1583 /* rx/tx queue initialisation ***********************************************/
1584 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1586 struct rx_queue *rxq = mp->rxq + index;
1587 struct rx_desc *rx_desc;
1593 rxq->rx_ring_size = mp->default_rx_ring_size;
1595 rxq->rx_desc_count = 0;
1596 rxq->rx_curr_desc = 0;
1597 rxq->rx_used_desc = 0;
1599 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1601 if (index == 0 && size <= mp->rx_desc_sram_size) {
1602 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1603 mp->rx_desc_sram_size);
1604 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1606 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1611 if (rxq->rx_desc_area == NULL) {
1612 dev_printk(KERN_ERR, &mp->dev->dev,
1613 "can't allocate rx ring (%d bytes)\n", size);
1616 memset(rxq->rx_desc_area, 0, size);
1618 rxq->rx_desc_area_size = size;
1619 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1621 if (rxq->rx_skb == NULL) {
1622 dev_printk(KERN_ERR, &mp->dev->dev,
1623 "can't allocate rx skb ring\n");
1627 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1628 for (i = 0; i < rxq->rx_ring_size; i++) {
1632 if (nexti == rxq->rx_ring_size)
1635 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1636 nexti * sizeof(struct rx_desc);
1643 if (index == 0 && size <= mp->rx_desc_sram_size)
1644 iounmap(rxq->rx_desc_area);
1646 dma_free_coherent(NULL, size,
1654 static void rxq_deinit(struct rx_queue *rxq)
1656 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1661 for (i = 0; i < rxq->rx_ring_size; i++) {
1662 if (rxq->rx_skb[i]) {
1663 dev_kfree_skb(rxq->rx_skb[i]);
1664 rxq->rx_desc_count--;
1668 if (rxq->rx_desc_count) {
1669 dev_printk(KERN_ERR, &mp->dev->dev,
1670 "error freeing rx ring -- %d skbs stuck\n",
1671 rxq->rx_desc_count);
1674 if (rxq->index == 0 &&
1675 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1676 iounmap(rxq->rx_desc_area);
1678 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1679 rxq->rx_desc_area, rxq->rx_desc_dma);
1684 static int txq_init(struct mv643xx_eth_private *mp, int index)
1686 struct tx_queue *txq = mp->txq + index;
1687 struct tx_desc *tx_desc;
1693 txq->tx_ring_size = mp->default_tx_ring_size;
1695 txq->tx_desc_count = 0;
1696 txq->tx_curr_desc = 0;
1697 txq->tx_used_desc = 0;
1699 size = txq->tx_ring_size * sizeof(struct tx_desc);
1701 if (index == 0 && size <= mp->tx_desc_sram_size) {
1702 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1703 mp->tx_desc_sram_size);
1704 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1706 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1711 if (txq->tx_desc_area == NULL) {
1712 dev_printk(KERN_ERR, &mp->dev->dev,
1713 "can't allocate tx ring (%d bytes)\n", size);
1716 memset(txq->tx_desc_area, 0, size);
1718 txq->tx_desc_area_size = size;
1720 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1721 for (i = 0; i < txq->tx_ring_size; i++) {
1722 struct tx_desc *txd = tx_desc + i;
1726 if (nexti == txq->tx_ring_size)
1730 txd->next_desc_ptr = txq->tx_desc_dma +
1731 nexti * sizeof(struct tx_desc);
1734 skb_queue_head_init(&txq->tx_skb);
1739 static void txq_deinit(struct tx_queue *txq)
1741 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1744 txq_reclaim(txq, txq->tx_ring_size, 1);
1746 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1748 if (txq->index == 0 &&
1749 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1750 iounmap(txq->tx_desc_area);
1752 dma_free_coherent(NULL, txq->tx_desc_area_size,
1753 txq->tx_desc_area, txq->tx_desc_dma);
1757 /* netdev ops and related ***************************************************/
1758 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1763 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1764 (INT_TX_END | INT_RX | INT_EXT);
1769 if (int_cause & INT_EXT)
1770 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1772 int_cause &= INT_TX_END | INT_RX;
1774 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1775 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1776 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1777 mp->work_rx |= (int_cause & INT_RX) >> 2;
1780 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1781 if (int_cause_ext) {
1782 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1783 if (int_cause_ext & INT_EXT_LINK_PHY)
1785 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1791 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1793 struct net_device *dev = (struct net_device *)dev_id;
1794 struct mv643xx_eth_private *mp = netdev_priv(dev);
1796 if (unlikely(!mv643xx_eth_collect_events(mp)))
1799 wrl(mp, INT_MASK(mp->port_num), 0);
1800 napi_schedule(&mp->napi);
1805 static void handle_link_event(struct mv643xx_eth_private *mp)
1807 struct net_device *dev = mp->dev;
1813 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1814 if (!(port_status & LINK_UP)) {
1815 if (netif_carrier_ok(dev)) {
1818 printk(KERN_INFO "%s: link down\n", dev->name);
1820 netif_carrier_off(dev);
1822 for (i = 0; i < mp->txq_count; i++) {
1823 struct tx_queue *txq = mp->txq + i;
1825 txq_reclaim(txq, txq->tx_ring_size, 1);
1826 txq_reset_hw_ptr(txq);
1832 switch (port_status & PORT_SPEED_MASK) {
1836 case PORT_SPEED_100:
1839 case PORT_SPEED_1000:
1846 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1847 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1849 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1850 "flow control %sabled\n", dev->name,
1851 speed, duplex ? "full" : "half",
1854 if (!netif_carrier_ok(dev))
1855 netif_carrier_on(dev);
1858 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1860 struct mv643xx_eth_private *mp;
1863 mp = container_of(napi, struct mv643xx_eth_private, napi);
1865 mp->work_rx_refill |= mp->work_rx_oom;
1866 mp->work_rx_oom = 0;
1869 while (work_done < budget) {
1874 if (mp->work_link) {
1876 handle_link_event(mp);
1880 queue_mask = mp->work_tx | mp->work_tx_end |
1881 mp->work_rx | mp->work_rx_refill;
1883 if (mv643xx_eth_collect_events(mp))
1888 queue = fls(queue_mask) - 1;
1889 queue_mask = 1 << queue;
1891 work_tbd = budget - work_done;
1895 if (mp->work_tx_end & queue_mask) {
1896 txq_kick(mp->txq + queue);
1897 } else if (mp->work_tx & queue_mask) {
1898 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1899 txq_maybe_wake(mp->txq + queue);
1900 } else if (mp->work_rx & queue_mask) {
1901 work_done += rxq_process(mp->rxq + queue, work_tbd);
1902 } else if (mp->work_rx_refill & queue_mask) {
1903 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1909 if (work_done < budget) {
1910 if (mp->work_rx_oom)
1911 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1912 napi_complete(napi);
1913 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1919 static inline void oom_timer_wrapper(unsigned long data)
1921 struct mv643xx_eth_private *mp = (void *)data;
1923 napi_schedule(&mp->napi);
1926 static void phy_reset(struct mv643xx_eth_private *mp)
1930 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1935 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1939 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1940 } while (data >= 0 && data & BMCR_RESET);
1943 static void port_start(struct mv643xx_eth_private *mp)
1949 * Perform PHY reset, if there is a PHY.
1951 if (mp->phy_addr != -1) {
1952 struct ethtool_cmd cmd;
1954 mv643xx_eth_get_settings(mp->dev, &cmd);
1956 mv643xx_eth_set_settings(mp->dev, &cmd);
1960 * Configure basic link parameters.
1962 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1964 pscr |= SERIAL_PORT_ENABLE;
1965 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1967 pscr |= DO_NOT_FORCE_LINK_FAIL;
1968 if (mp->phy_addr == -1)
1969 pscr |= FORCE_LINK_PASS;
1970 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1972 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1975 * Configure TX path and queues.
1977 tx_set_rate(mp, 1000000000, 16777216);
1978 for (i = 0; i < mp->txq_count; i++) {
1979 struct tx_queue *txq = mp->txq + i;
1981 txq_reset_hw_ptr(txq);
1982 txq_set_rate(txq, 1000000000, 16777216);
1983 txq_set_fixed_prio_mode(txq);
1987 * Add configured unicast address to address filter table.
1989 uc_addr_set(mp, mp->dev->dev_addr);
1992 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1993 * frames to RX queue #0, and include the pseudo-header when
1994 * calculating receive checksums.
1996 wrl(mp, PORT_CONFIG(mp->port_num), 0x02000000);
1999 * Treat BPDUs as normal multicasts, and disable partition mode.
2001 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2004 * Enable the receive queues.
2006 for (i = 0; i < mp->rxq_count; i++) {
2007 struct rx_queue *rxq = mp->rxq + i;
2008 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2011 addr = (u32)rxq->rx_desc_dma;
2012 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2019 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2021 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2024 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2025 if (mp->shared->extended_rx_coal_limit) {
2029 val |= (coal & 0x8000) << 10;
2030 val |= (coal & 0x7fff) << 7;
2035 val |= (coal & 0x3fff) << 8;
2037 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2040 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2042 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2046 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2049 static int mv643xx_eth_open(struct net_device *dev)
2051 struct mv643xx_eth_private *mp = netdev_priv(dev);
2055 wrl(mp, INT_CAUSE(mp->port_num), 0);
2056 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2057 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2059 err = request_irq(dev->irq, mv643xx_eth_irq,
2060 IRQF_SHARED, dev->name, dev);
2062 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2066 init_mac_tables(mp);
2068 napi_enable(&mp->napi);
2070 for (i = 0; i < mp->rxq_count; i++) {
2071 err = rxq_init(mp, i);
2074 rxq_deinit(mp->rxq + i);
2078 rxq_refill(mp->rxq + i, INT_MAX);
2081 if (mp->work_rx_oom) {
2082 mp->rx_oom.expires = jiffies + (HZ / 10);
2083 add_timer(&mp->rx_oom);
2086 for (i = 0; i < mp->txq_count; i++) {
2087 err = txq_init(mp, i);
2090 txq_deinit(mp->txq + i);
2095 netif_carrier_off(dev);
2102 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2103 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2109 for (i = 0; i < mp->rxq_count; i++)
2110 rxq_deinit(mp->rxq + i);
2112 free_irq(dev->irq, dev);
2117 static void port_reset(struct mv643xx_eth_private *mp)
2122 for (i = 0; i < mp->rxq_count; i++)
2123 rxq_disable(mp->rxq + i);
2124 for (i = 0; i < mp->txq_count; i++)
2125 txq_disable(mp->txq + i);
2128 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2130 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2135 /* Reset the Enable bit in the Configuration Register */
2136 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2137 data &= ~(SERIAL_PORT_ENABLE |
2138 DO_NOT_FORCE_LINK_FAIL |
2140 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2143 static int mv643xx_eth_stop(struct net_device *dev)
2145 struct mv643xx_eth_private *mp = netdev_priv(dev);
2148 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2149 rdl(mp, INT_MASK(mp->port_num));
2151 napi_disable(&mp->napi);
2153 del_timer_sync(&mp->rx_oom);
2155 netif_carrier_off(dev);
2157 free_irq(dev->irq, dev);
2160 mv643xx_eth_get_stats(dev);
2161 mib_counters_update(mp);
2163 for (i = 0; i < mp->rxq_count; i++)
2164 rxq_deinit(mp->rxq + i);
2165 for (i = 0; i < mp->txq_count; i++)
2166 txq_deinit(mp->txq + i);
2171 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2173 struct mv643xx_eth_private *mp = netdev_priv(dev);
2175 if (mp->phy_addr != -1)
2176 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2181 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2183 struct mv643xx_eth_private *mp = netdev_priv(dev);
2185 if (new_mtu < 64 || new_mtu > 9500)
2189 tx_set_rate(mp, 1000000000, 16777216);
2191 if (!netif_running(dev))
2195 * Stop and then re-open the interface. This will allocate RX
2196 * skbs of the new MTU.
2197 * There is a possible danger that the open will not succeed,
2198 * due to memory being full.
2200 mv643xx_eth_stop(dev);
2201 if (mv643xx_eth_open(dev)) {
2202 dev_printk(KERN_ERR, &dev->dev,
2203 "fatal error on re-opening device after "
2210 static void tx_timeout_task(struct work_struct *ugly)
2212 struct mv643xx_eth_private *mp;
2214 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2215 if (netif_running(mp->dev)) {
2216 netif_tx_stop_all_queues(mp->dev);
2219 netif_tx_wake_all_queues(mp->dev);
2223 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2225 struct mv643xx_eth_private *mp = netdev_priv(dev);
2227 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2229 schedule_work(&mp->tx_timeout_task);
2232 #ifdef CONFIG_NET_POLL_CONTROLLER
2233 static void mv643xx_eth_netpoll(struct net_device *dev)
2235 struct mv643xx_eth_private *mp = netdev_priv(dev);
2237 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2238 rdl(mp, INT_MASK(mp->port_num));
2240 mv643xx_eth_irq(dev->irq, dev);
2242 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2246 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2248 struct mv643xx_eth_private *mp = netdev_priv(dev);
2249 return smi_reg_read(mp, addr, reg);
2252 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2254 struct mv643xx_eth_private *mp = netdev_priv(dev);
2255 smi_reg_write(mp, addr, reg, val);
2259 /* platform glue ************************************************************/
2261 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2262 struct mbus_dram_target_info *dram)
2264 void __iomem *base = msp->base;
2269 for (i = 0; i < 6; i++) {
2270 writel(0, base + WINDOW_BASE(i));
2271 writel(0, base + WINDOW_SIZE(i));
2273 writel(0, base + WINDOW_REMAP_HIGH(i));
2279 for (i = 0; i < dram->num_cs; i++) {
2280 struct mbus_dram_window *cs = dram->cs + i;
2282 writel((cs->base & 0xffff0000) |
2283 (cs->mbus_attr << 8) |
2284 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2285 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2287 win_enable &= ~(1 << i);
2288 win_protect |= 3 << (2 * i);
2291 writel(win_enable, base + WINDOW_BAR_ENABLE);
2292 msp->win_protect = win_protect;
2295 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2298 * Check whether we have a 14-bit coal limit field in bits
2299 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2300 * SDMA config register.
2302 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2303 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2304 msp->extended_rx_coal_limit = 1;
2306 msp->extended_rx_coal_limit = 0;
2309 * Check whether the MAC supports TX rate control, and if
2310 * yes, whether its associated registers are in the old or
2313 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2314 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) {
2315 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2317 writel(7, msp->base + TX_BW_RATE(0));
2318 if (readl(msp->base + TX_BW_RATE(0)) & 7)
2319 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2321 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2325 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2327 static int mv643xx_eth_version_printed = 0;
2328 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2329 struct mv643xx_eth_shared_private *msp;
2330 struct resource *res;
2333 if (!mv643xx_eth_version_printed++)
2334 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2335 "driver version %s\n", mv643xx_eth_driver_version);
2338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2343 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2346 memset(msp, 0, sizeof(*msp));
2348 msp->base = ioremap(res->start, res->end - res->start + 1);
2349 if (msp->base == NULL)
2353 if (pd != NULL && pd->shared_smi != NULL)
2354 msp->smi = platform_get_drvdata(pd->shared_smi);
2356 mutex_init(&msp->phy_lock);
2358 msp->err_interrupt = NO_IRQ;
2359 init_waitqueue_head(&msp->smi_busy_wait);
2362 * Check whether the error interrupt is hooked up.
2364 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2368 err = request_irq(res->start, mv643xx_eth_err_irq,
2369 IRQF_SHARED, "mv643xx_eth", msp);
2371 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2372 msp->err_interrupt = res->start;
2377 * (Re-)program MBUS remapping windows if we are asked to.
2379 if (pd != NULL && pd->dram != NULL)
2380 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2383 * Detect hardware parameters.
2385 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2386 infer_hw_params(msp);
2388 platform_set_drvdata(pdev, msp);
2398 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2400 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2402 if (msp->err_interrupt != NO_IRQ)
2403 free_irq(msp->err_interrupt, msp);
2410 static struct platform_driver mv643xx_eth_shared_driver = {
2411 .probe = mv643xx_eth_shared_probe,
2412 .remove = mv643xx_eth_shared_remove,
2414 .name = MV643XX_ETH_SHARED_NAME,
2415 .owner = THIS_MODULE,
2419 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2421 int addr_shift = 5 * mp->port_num;
2424 data = rdl(mp, PHY_ADDR);
2425 data &= ~(0x1f << addr_shift);
2426 data |= (phy_addr & 0x1f) << addr_shift;
2427 wrl(mp, PHY_ADDR, data);
2430 static int phy_addr_get(struct mv643xx_eth_private *mp)
2434 data = rdl(mp, PHY_ADDR);
2436 return (data >> (5 * mp->port_num)) & 0x1f;
2439 static void set_params(struct mv643xx_eth_private *mp,
2440 struct mv643xx_eth_platform_data *pd)
2442 struct net_device *dev = mp->dev;
2444 if (is_valid_ether_addr(pd->mac_addr))
2445 memcpy(dev->dev_addr, pd->mac_addr, 6);
2447 uc_addr_get(mp, dev->dev_addr);
2449 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
2452 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
2453 mp->phy_addr = pd->phy_addr & 0x3f;
2454 phy_addr_set(mp, mp->phy_addr);
2456 mp->phy_addr = phy_addr_get(mp);
2460 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2461 if (pd->rx_queue_size)
2462 mp->default_rx_ring_size = pd->rx_queue_size;
2463 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2464 mp->rx_desc_sram_size = pd->rx_sram_size;
2466 mp->rxq_count = pd->rx_queue_count ? : 1;
2468 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2469 if (pd->tx_queue_size)
2470 mp->default_tx_ring_size = pd->tx_queue_size;
2471 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2472 mp->tx_desc_sram_size = pd->tx_sram_size;
2474 mp->txq_count = pd->tx_queue_count ? : 1;
2477 static int phy_detect(struct mv643xx_eth_private *mp)
2482 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2486 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2489 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2493 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2496 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2501 static int phy_init(struct mv643xx_eth_private *mp,
2502 struct mv643xx_eth_platform_data *pd)
2504 struct ethtool_cmd cmd;
2507 err = phy_detect(mp);
2509 dev_printk(KERN_INFO, &mp->dev->dev,
2510 "no PHY detected at addr %d\n", mp->phy_addr);
2515 mp->mii.phy_id = mp->phy_addr;
2516 mp->mii.phy_id_mask = 0x3f;
2517 mp->mii.reg_num_mask = 0x1f;
2518 mp->mii.dev = mp->dev;
2519 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2520 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2522 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2524 memset(&cmd, 0, sizeof(cmd));
2526 cmd.port = PORT_MII;
2527 cmd.transceiver = XCVR_INTERNAL;
2528 cmd.phy_address = mp->phy_addr;
2529 if (pd->speed == 0) {
2530 cmd.autoneg = AUTONEG_ENABLE;
2531 cmd.speed = SPEED_100;
2532 cmd.advertising = ADVERTISED_10baseT_Half |
2533 ADVERTISED_10baseT_Full |
2534 ADVERTISED_100baseT_Half |
2535 ADVERTISED_100baseT_Full;
2536 if (mp->mii.supports_gmii)
2537 cmd.advertising |= ADVERTISED_1000baseT_Full;
2539 cmd.autoneg = AUTONEG_DISABLE;
2540 cmd.speed = pd->speed;
2541 cmd.duplex = pd->duplex;
2544 mv643xx_eth_set_settings(mp->dev, &cmd);
2549 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2553 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2554 if (pscr & SERIAL_PORT_ENABLE) {
2555 pscr &= ~SERIAL_PORT_ENABLE;
2556 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2559 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2560 if (mp->phy_addr == -1) {
2561 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2562 if (speed == SPEED_1000)
2563 pscr |= SET_GMII_SPEED_TO_1000;
2564 else if (speed == SPEED_100)
2565 pscr |= SET_MII_SPEED_TO_100;
2567 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2569 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2570 if (duplex == DUPLEX_FULL)
2571 pscr |= SET_FULL_DUPLEX_MODE;
2574 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2577 static int mv643xx_eth_probe(struct platform_device *pdev)
2579 struct mv643xx_eth_platform_data *pd;
2580 struct mv643xx_eth_private *mp;
2581 struct net_device *dev;
2582 struct resource *res;
2583 DECLARE_MAC_BUF(mac);
2586 pd = pdev->dev.platform_data;
2588 dev_printk(KERN_ERR, &pdev->dev,
2589 "no mv643xx_eth_platform_data\n");
2593 if (pd->shared == NULL) {
2594 dev_printk(KERN_ERR, &pdev->dev,
2595 "no mv643xx_eth_platform_data->shared\n");
2599 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2603 mp = netdev_priv(dev);
2604 platform_set_drvdata(pdev, mp);
2606 mp->shared = platform_get_drvdata(pd->shared);
2607 mp->port_num = pd->port_number;
2612 dev->real_num_tx_queues = mp->txq_count;
2614 mib_counters_clear(mp);
2615 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2617 if (mp->phy_addr != -1) {
2618 err = phy_init(mp, pd);
2622 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2624 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2626 init_pscr(mp, pd->speed, pd->duplex);
2628 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2630 init_timer(&mp->rx_oom);
2631 mp->rx_oom.data = (unsigned long)mp;
2632 mp->rx_oom.function = oom_timer_wrapper;
2635 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2637 dev->irq = res->start;
2639 dev->get_stats = mv643xx_eth_get_stats;
2640 dev->hard_start_xmit = mv643xx_eth_xmit;
2641 dev->open = mv643xx_eth_open;
2642 dev->stop = mv643xx_eth_stop;
2643 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2644 dev->set_mac_address = mv643xx_eth_set_mac_address;
2645 dev->do_ioctl = mv643xx_eth_ioctl;
2646 dev->change_mtu = mv643xx_eth_change_mtu;
2647 dev->tx_timeout = mv643xx_eth_tx_timeout;
2648 #ifdef CONFIG_NET_POLL_CONTROLLER
2649 dev->poll_controller = mv643xx_eth_netpoll;
2651 dev->watchdog_timeo = 2 * HZ;
2654 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2655 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2657 SET_NETDEV_DEV(dev, &pdev->dev);
2659 if (mp->shared->win_protect)
2660 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2662 err = register_netdev(dev);
2666 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2667 mp->port_num, print_mac(mac, dev->dev_addr));
2669 if (mp->tx_desc_sram_size > 0)
2670 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2680 static int mv643xx_eth_remove(struct platform_device *pdev)
2682 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2684 unregister_netdev(mp->dev);
2685 flush_scheduled_work();
2686 free_netdev(mp->dev);
2688 platform_set_drvdata(pdev, NULL);
2693 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2695 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2697 /* Mask all interrupts on ethernet port */
2698 wrl(mp, INT_MASK(mp->port_num), 0);
2699 rdl(mp, INT_MASK(mp->port_num));
2701 if (netif_running(mp->dev))
2705 static struct platform_driver mv643xx_eth_driver = {
2706 .probe = mv643xx_eth_probe,
2707 .remove = mv643xx_eth_remove,
2708 .shutdown = mv643xx_eth_shutdown,
2710 .name = MV643XX_ETH_NAME,
2711 .owner = THIS_MODULE,
2715 static int __init mv643xx_eth_init_module(void)
2719 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2721 rc = platform_driver_register(&mv643xx_eth_driver);
2723 platform_driver_unregister(&mv643xx_eth_shared_driver);
2728 module_init(mv643xx_eth_init_module);
2730 static void __exit mv643xx_eth_cleanup_module(void)
2732 platform_driver_unregister(&mv643xx_eth_driver);
2733 platform_driver_unregister(&mv643xx_eth_shared_driver);
2735 module_exit(mv643xx_eth_cleanup_module);
2737 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2738 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2739 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2740 MODULE_LICENSE("GPL");
2741 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2742 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);