2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
55 #include <linux/types.h>
56 #include <asm/system.h>
58 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
59 static char mv643xx_eth_driver_version[] = "1.4";
63 * Registers shared between all ports.
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
84 #define PORT_CONFIG 0x0000
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT 0x0004
87 #define MAC_ADDR_LOW 0x0014
88 #define MAC_ADDR_HIGH 0x0018
89 #define SDMA_CONFIG 0x001c
90 #define PORT_SERIAL_CONTROL 0x003c
91 #define PORT_STATUS 0x0044
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND 0x0048
102 #define TXQ_FIX_PRIO_CONF 0x004c
103 #define TX_BW_RATE 0x0050
104 #define TX_BW_MTU 0x0058
105 #define TX_BW_BURST 0x005c
106 #define INT_CAUSE 0x0060
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x000003fc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT 0x0064
111 #define INT_EXT_LINK_PHY 0x00110000
112 #define INT_EXT_TX 0x000000ff
113 #define INT_MASK 0x0068
114 #define INT_MASK_EXT 0x006c
115 #define TX_FIFO_URGENT_THRESHOLD 0x0074
116 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117 #define TX_BW_RATE_MOVED 0x00e0
118 #define TX_BW_MTU_MOVED 0x00e8
119 #define TX_BW_BURST_MOVED 0x00ec
120 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121 #define RXQ_COMMAND 0x0280
122 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
128 * Misc per-port registers.
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
137 * SDMA configuration register.
139 #define RX_BURST_SIZE_4_64BIT (2 << 1)
140 #define RX_BURST_SIZE_16_64BIT (4 << 1)
141 #define BLM_RX_NO_SWAP (1 << 4)
142 #define BLM_TX_NO_SWAP (1 << 5)
143 #define TX_BURST_SIZE_4_64BIT (2 << 22)
144 #define TX_BURST_SIZE_16_64BIT (4 << 22)
146 #if defined(__BIG_ENDIAN)
147 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
148 (RX_BURST_SIZE_4_64BIT | \
149 TX_BURST_SIZE_4_64BIT)
150 #elif defined(__LITTLE_ENDIAN)
151 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
152 (RX_BURST_SIZE_4_64BIT | \
155 TX_BURST_SIZE_4_64BIT)
157 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
162 * Port serial control register.
164 #define SET_MII_SPEED_TO_100 (1 << 24)
165 #define SET_GMII_SPEED_TO_1000 (1 << 23)
166 #define SET_FULL_DUPLEX_MODE (1 << 21)
167 #define MAX_RX_PACKET_9700BYTE (5 << 17)
168 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
169 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
170 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
171 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
172 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
173 #define FORCE_LINK_PASS (1 << 1)
174 #define SERIAL_PORT_ENABLE (1 << 0)
176 #define DEFAULT_RX_QUEUE_SIZE 128
177 #define DEFAULT_TX_QUEUE_SIZE 256
183 #if defined(__BIG_ENDIAN)
185 u16 byte_cnt; /* Descriptor buffer byte count */
186 u16 buf_size; /* Buffer size */
187 u32 cmd_sts; /* Descriptor command status */
188 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 buf_ptr; /* Descriptor buffer pointer */
193 u16 byte_cnt; /* buffer byte count */
194 u16 l4i_chk; /* CPU provided TCP checksum */
195 u32 cmd_sts; /* Command/status field */
196 u32 next_desc_ptr; /* Pointer to next descriptor */
197 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 #elif defined(__LITTLE_ENDIAN)
201 u32 cmd_sts; /* Descriptor command status */
202 u16 buf_size; /* Buffer size */
203 u16 byte_cnt; /* Descriptor buffer byte count */
204 u32 buf_ptr; /* Descriptor buffer pointer */
205 u32 next_desc_ptr; /* Next descriptor pointer */
209 u32 cmd_sts; /* Command/status field */
210 u16 l4i_chk; /* CPU provided TCP checksum */
211 u16 byte_cnt; /* buffer byte count */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr; /* Pointer to next descriptor */
216 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
219 /* RX & TX descriptor command */
220 #define BUFFER_OWNED_BY_DMA 0x80000000
222 /* RX & TX descriptor status */
223 #define ERROR_SUMMARY 0x00000001
225 /* RX descriptor status */
226 #define LAYER_4_CHECKSUM_OK 0x40000000
227 #define RX_ENABLE_INTERRUPT 0x20000000
228 #define RX_FIRST_DESC 0x08000000
229 #define RX_LAST_DESC 0x04000000
231 /* TX descriptor command */
232 #define TX_ENABLE_INTERRUPT 0x00800000
233 #define GEN_CRC 0x00400000
234 #define TX_FIRST_DESC 0x00200000
235 #define TX_LAST_DESC 0x00100000
236 #define ZERO_PADDING 0x00080000
237 #define GEN_IP_V4_CHECKSUM 0x00040000
238 #define GEN_TCP_UDP_CHECKSUM 0x00020000
239 #define UDP_FRAME 0x00010000
240 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
241 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
243 #define TX_IHL_SHIFT 11
246 /* global *******************************************************************/
247 struct mv643xx_eth_shared_private {
249 * Ethernet controller base address.
254 * Points at the right SMI instance to use.
256 struct mv643xx_eth_shared_private *smi;
259 * Provides access to local SMI interface.
261 struct mii_bus *smi_bus;
264 * If we have access to the error interrupt pin (which is
265 * somewhat misnamed as it not only reflects internal errors
266 * but also reflects SMI completion), use that to wait for
267 * SMI access completion instead of polling the SMI busy bit.
270 wait_queue_head_t smi_busy_wait;
273 * Per-port MBUS window access register value.
278 * Hardware-specific parameters.
281 int extended_rx_coal_limit;
285 #define TX_BW_CONTROL_ABSENT 0
286 #define TX_BW_CONTROL_OLD_LAYOUT 1
287 #define TX_BW_CONTROL_NEW_LAYOUT 2
290 /* per-port *****************************************************************/
291 struct mib_counters {
292 u64 good_octets_received;
293 u32 bad_octets_received;
294 u32 internal_mac_transmit_err;
295 u32 good_frames_received;
296 u32 bad_frames_received;
297 u32 broadcast_frames_received;
298 u32 multicast_frames_received;
299 u32 frames_64_octets;
300 u32 frames_65_to_127_octets;
301 u32 frames_128_to_255_octets;
302 u32 frames_256_to_511_octets;
303 u32 frames_512_to_1023_octets;
304 u32 frames_1024_to_max_octets;
305 u64 good_octets_sent;
306 u32 good_frames_sent;
307 u32 excessive_collision;
308 u32 multicast_frames_sent;
309 u32 broadcast_frames_sent;
310 u32 unrec_mac_control_received;
312 u32 good_fc_received;
314 u32 undersize_received;
315 u32 fragments_received;
316 u32 oversize_received;
318 u32 mac_receive_error;
333 struct rx_desc *rx_desc_area;
334 dma_addr_t rx_desc_dma;
335 int rx_desc_area_size;
336 struct sk_buff **rx_skb;
348 struct tx_desc *tx_desc_area;
349 dma_addr_t tx_desc_dma;
350 int tx_desc_area_size;
352 struct sk_buff_head tx_skb;
354 unsigned long tx_packets;
355 unsigned long tx_bytes;
356 unsigned long tx_dropped;
359 struct mv643xx_eth_private {
360 struct mv643xx_eth_shared_private *shared;
364 struct net_device *dev;
366 struct phy_device *phy;
368 struct timer_list mib_counters_timer;
369 spinlock_t mib_counters_lock;
370 struct mib_counters mib_counters;
372 struct work_struct tx_timeout_task;
374 struct napi_struct napi;
383 struct sk_buff_head rx_recycle;
388 int default_rx_ring_size;
389 unsigned long rx_desc_sram_addr;
390 int rx_desc_sram_size;
392 struct timer_list rx_oom;
393 struct rx_queue rxq[8];
398 int default_tx_ring_size;
399 unsigned long tx_desc_sram_addr;
400 int tx_desc_sram_size;
402 struct tx_queue txq[8];
406 /* port register accessors **************************************************/
407 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
409 return readl(mp->shared->base + offset);
412 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
414 return readl(mp->base + offset);
417 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
419 writel(data, mp->shared->base + offset);
422 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
424 writel(data, mp->base + offset);
428 /* rxq/txq helper functions *************************************************/
429 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
431 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
434 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
436 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
439 static void rxq_enable(struct rx_queue *rxq)
441 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
442 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
445 static void rxq_disable(struct rx_queue *rxq)
447 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
448 u8 mask = 1 << rxq->index;
450 wrlp(mp, RXQ_COMMAND, mask << 8);
451 while (rdlp(mp, RXQ_COMMAND) & mask)
455 static void txq_reset_hw_ptr(struct tx_queue *txq)
457 struct mv643xx_eth_private *mp = txq_to_mp(txq);
460 addr = (u32)txq->tx_desc_dma;
461 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
462 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
465 static void txq_enable(struct tx_queue *txq)
467 struct mv643xx_eth_private *mp = txq_to_mp(txq);
468 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
471 static void txq_disable(struct tx_queue *txq)
473 struct mv643xx_eth_private *mp = txq_to_mp(txq);
474 u8 mask = 1 << txq->index;
476 wrlp(mp, TXQ_COMMAND, mask << 8);
477 while (rdlp(mp, TXQ_COMMAND) & mask)
481 static void txq_maybe_wake(struct tx_queue *txq)
483 struct mv643xx_eth_private *mp = txq_to_mp(txq);
484 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
486 if (netif_tx_queue_stopped(nq)) {
487 __netif_tx_lock(nq, smp_processor_id());
488 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
489 netif_tx_wake_queue(nq);
490 __netif_tx_unlock(nq);
495 /* rx napi ******************************************************************/
496 static int rxq_process(struct rx_queue *rxq, int budget)
498 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
499 struct net_device_stats *stats = &mp->dev->stats;
503 while (rx < budget && rxq->rx_desc_count) {
504 struct rx_desc *rx_desc;
505 unsigned int cmd_sts;
509 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
511 cmd_sts = rx_desc->cmd_sts;
512 if (cmd_sts & BUFFER_OWNED_BY_DMA)
516 skb = rxq->rx_skb[rxq->rx_curr_desc];
517 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
520 if (rxq->rx_curr_desc == rxq->rx_ring_size)
521 rxq->rx_curr_desc = 0;
523 dma_unmap_single(NULL, rx_desc->buf_ptr,
524 rx_desc->buf_size, DMA_FROM_DEVICE);
525 rxq->rx_desc_count--;
528 mp->work_rx_refill |= 1 << rxq->index;
530 byte_cnt = rx_desc->byte_cnt;
535 * Note that the descriptor byte count includes 2 dummy
536 * bytes automatically inserted by the hardware at the
537 * start of the packet (which we don't count), and a 4
538 * byte CRC at the end of the packet (which we do count).
541 stats->rx_bytes += byte_cnt - 2;
544 * In case we received a packet without first / last bits
545 * on, or the error summary bit is set, the packet needs
548 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
549 != (RX_FIRST_DESC | RX_LAST_DESC))
553 * The -4 is for the CRC in the trailer of the
556 skb_put(skb, byte_cnt - 2 - 4);
558 if (cmd_sts & LAYER_4_CHECKSUM_OK)
559 skb->ip_summed = CHECKSUM_UNNECESSARY;
560 skb->protocol = eth_type_trans(skb, mp->dev);
561 netif_receive_skb(skb);
568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
569 (RX_FIRST_DESC | RX_LAST_DESC)) {
571 dev_printk(KERN_ERR, &mp->dev->dev,
572 "received packet spanning "
573 "multiple descriptors\n");
576 if (cmd_sts & ERROR_SUMMARY)
583 mp->work_rx &= ~(1 << rxq->index);
588 static int rxq_refill(struct rx_queue *rxq, int budget)
590 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
594 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
598 struct rx_desc *rx_desc;
600 skb = __skb_dequeue(&mp->rx_recycle);
602 skb = dev_alloc_skb(mp->skb_size +
603 dma_get_cache_alignment() - 1);
606 mp->work_rx_oom |= 1 << rxq->index;
610 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
612 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
615 rxq->rx_desc_count++;
617 rx = rxq->rx_used_desc++;
618 if (rxq->rx_used_desc == rxq->rx_ring_size)
619 rxq->rx_used_desc = 0;
621 rx_desc = rxq->rx_desc_area + rx;
623 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
624 mp->skb_size, DMA_FROM_DEVICE);
625 rx_desc->buf_size = mp->skb_size;
626 rxq->rx_skb[rx] = skb;
628 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
632 * The hardware automatically prepends 2 bytes of
633 * dummy data to each received packet, so that the
634 * IP header ends up 16-byte aligned.
639 if (refilled < budget)
640 mp->work_rx_refill &= ~(1 << rxq->index);
647 /* tx ***********************************************************************/
648 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
652 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
653 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
654 if (fragp->size <= 8 && fragp->page_offset & 7)
661 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
663 int nr_frags = skb_shinfo(skb)->nr_frags;
666 for (frag = 0; frag < nr_frags; frag++) {
667 skb_frag_t *this_frag;
669 struct tx_desc *desc;
671 this_frag = &skb_shinfo(skb)->frags[frag];
672 tx_index = txq->tx_curr_desc++;
673 if (txq->tx_curr_desc == txq->tx_ring_size)
674 txq->tx_curr_desc = 0;
675 desc = &txq->tx_desc_area[tx_index];
678 * The last fragment will generate an interrupt
679 * which will free the skb on TX completion.
681 if (frag == nr_frags - 1) {
682 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
683 ZERO_PADDING | TX_LAST_DESC |
686 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
690 desc->byte_cnt = this_frag->size;
691 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
692 this_frag->page_offset,
698 static inline __be16 sum16_as_be(__sum16 sum)
700 return (__force __be16)sum;
703 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
705 struct mv643xx_eth_private *mp = txq_to_mp(txq);
706 int nr_frags = skb_shinfo(skb)->nr_frags;
708 struct tx_desc *desc;
713 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
716 if (skb->ip_summed == CHECKSUM_PARTIAL) {
719 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
720 skb->protocol != htons(ETH_P_8021Q));
722 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
723 if (unlikely(tag_bytes & ~12)) {
724 if (skb_checksum_help(skb) == 0)
731 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
733 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
735 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
737 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
739 switch (ip_hdr(skb)->protocol) {
741 cmd_sts |= UDP_FRAME;
742 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
745 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
752 /* Errata BTS #50, IHL must be 5 if no HW checksum */
753 cmd_sts |= 5 << TX_IHL_SHIFT;
756 tx_index = txq->tx_curr_desc++;
757 if (txq->tx_curr_desc == txq->tx_ring_size)
758 txq->tx_curr_desc = 0;
759 desc = &txq->tx_desc_area[tx_index];
762 txq_submit_frag_skb(txq, skb);
763 length = skb_headlen(skb);
765 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
769 desc->l4i_chk = l4i_chk;
770 desc->byte_cnt = length;
771 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
773 __skb_queue_tail(&txq->tx_skb, skb);
775 /* ensure all other descriptors are written before first cmd_sts */
777 desc->cmd_sts = cmd_sts;
779 /* clear TX_END status */
780 mp->work_tx_end &= ~(1 << txq->index);
782 /* ensure all descriptors are written before poking hardware */
786 txq->tx_desc_count += nr_frags + 1;
791 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
793 struct mv643xx_eth_private *mp = netdev_priv(dev);
795 struct tx_queue *txq;
796 struct netdev_queue *nq;
798 queue = skb_get_queue_mapping(skb);
799 txq = mp->txq + queue;
800 nq = netdev_get_tx_queue(dev, queue);
802 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
804 dev_printk(KERN_DEBUG, &dev->dev,
805 "failed to linearize skb with tiny "
806 "unaligned fragment\n");
807 return NETDEV_TX_BUSY;
810 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
812 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
817 if (!txq_submit_skb(txq, skb)) {
820 txq->tx_bytes += skb->len;
822 dev->trans_start = jiffies;
824 entries_left = txq->tx_ring_size - txq->tx_desc_count;
825 if (entries_left < MAX_SKB_FRAGS + 1)
826 netif_tx_stop_queue(nq);
833 /* tx napi ******************************************************************/
834 static void txq_kick(struct tx_queue *txq)
836 struct mv643xx_eth_private *mp = txq_to_mp(txq);
837 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
841 __netif_tx_lock(nq, smp_processor_id());
843 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
846 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
847 expected_ptr = (u32)txq->tx_desc_dma +
848 txq->tx_curr_desc * sizeof(struct tx_desc);
850 if (hw_desc_ptr != expected_ptr)
854 __netif_tx_unlock(nq);
856 mp->work_tx_end &= ~(1 << txq->index);
859 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
861 struct mv643xx_eth_private *mp = txq_to_mp(txq);
862 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
865 __netif_tx_lock(nq, smp_processor_id());
868 while (reclaimed < budget && txq->tx_desc_count > 0) {
870 struct tx_desc *desc;
874 tx_index = txq->tx_used_desc;
875 desc = &txq->tx_desc_area[tx_index];
876 cmd_sts = desc->cmd_sts;
878 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
881 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
884 txq->tx_used_desc = tx_index + 1;
885 if (txq->tx_used_desc == txq->tx_ring_size)
886 txq->tx_used_desc = 0;
889 txq->tx_desc_count--;
892 if (cmd_sts & TX_LAST_DESC)
893 skb = __skb_dequeue(&txq->tx_skb);
895 if (cmd_sts & ERROR_SUMMARY) {
896 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
897 mp->dev->stats.tx_errors++;
900 if (cmd_sts & TX_FIRST_DESC) {
901 dma_unmap_single(NULL, desc->buf_ptr,
902 desc->byte_cnt, DMA_TO_DEVICE);
904 dma_unmap_page(NULL, desc->buf_ptr,
905 desc->byte_cnt, DMA_TO_DEVICE);
909 if (skb_queue_len(&mp->rx_recycle) <
910 mp->default_rx_ring_size &&
911 skb_recycle_check(skb, mp->skb_size +
912 dma_get_cache_alignment() - 1))
913 __skb_queue_head(&mp->rx_recycle, skb);
919 __netif_tx_unlock(nq);
921 if (reclaimed < budget)
922 mp->work_tx &= ~(1 << txq->index);
928 /* tx rate control **********************************************************/
930 * Set total maximum TX rate (shared by all TX queues for this port)
931 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
933 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
939 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
940 if (token_rate > 1023)
943 mtu = (mp->dev->mtu + 255) >> 8;
947 bucket_size = (burst + 255) >> 8;
948 if (bucket_size > 65535)
951 switch (mp->shared->tx_bw_control) {
952 case TX_BW_CONTROL_OLD_LAYOUT:
953 wrlp(mp, TX_BW_RATE, token_rate);
954 wrlp(mp, TX_BW_MTU, mtu);
955 wrlp(mp, TX_BW_BURST, bucket_size);
957 case TX_BW_CONTROL_NEW_LAYOUT:
958 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
959 wrlp(mp, TX_BW_MTU_MOVED, mtu);
960 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
965 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
967 struct mv643xx_eth_private *mp = txq_to_mp(txq);
971 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
972 if (token_rate > 1023)
975 bucket_size = (burst + 255) >> 8;
976 if (bucket_size > 65535)
979 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
980 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
983 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
985 struct mv643xx_eth_private *mp = txq_to_mp(txq);
990 * Turn on fixed priority mode.
993 switch (mp->shared->tx_bw_control) {
994 case TX_BW_CONTROL_OLD_LAYOUT:
995 off = TXQ_FIX_PRIO_CONF;
997 case TX_BW_CONTROL_NEW_LAYOUT:
998 off = TXQ_FIX_PRIO_CONF_MOVED;
1003 val = rdlp(mp, off);
1004 val |= 1 << txq->index;
1009 static void txq_set_wrr(struct tx_queue *txq, int weight)
1011 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1016 * Turn off fixed priority mode.
1019 switch (mp->shared->tx_bw_control) {
1020 case TX_BW_CONTROL_OLD_LAYOUT:
1021 off = TXQ_FIX_PRIO_CONF;
1023 case TX_BW_CONTROL_NEW_LAYOUT:
1024 off = TXQ_FIX_PRIO_CONF_MOVED;
1029 val = rdlp(mp, off);
1030 val &= ~(1 << txq->index);
1034 * Configure WRR weight for this queue.
1037 val = rdlp(mp, off);
1038 val = (val & ~0xff) | (weight & 0xff);
1039 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
1044 /* mii management interface *************************************************/
1045 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1047 struct mv643xx_eth_shared_private *msp = dev_id;
1049 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1050 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1051 wake_up(&msp->smi_busy_wait);
1058 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1060 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1063 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1065 if (msp->err_interrupt == NO_IRQ) {
1068 for (i = 0; !smi_is_done(msp); i++) {
1077 if (!smi_is_done(msp)) {
1078 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1079 msecs_to_jiffies(100));
1080 if (!smi_is_done(msp))
1087 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1089 struct mv643xx_eth_shared_private *msp = bus->priv;
1090 void __iomem *smi_reg = msp->base + SMI_REG;
1093 if (smi_wait_ready(msp)) {
1094 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1098 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1100 if (smi_wait_ready(msp)) {
1101 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1105 ret = readl(smi_reg);
1106 if (!(ret & SMI_READ_VALID)) {
1107 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1111 return ret & 0xffff;
1114 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1116 struct mv643xx_eth_shared_private *msp = bus->priv;
1117 void __iomem *smi_reg = msp->base + SMI_REG;
1119 if (smi_wait_ready(msp)) {
1120 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1124 writel(SMI_OPCODE_WRITE | (reg << 21) |
1125 (addr << 16) | (val & 0xffff), smi_reg);
1127 if (smi_wait_ready(msp)) {
1128 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1136 /* statistics ***************************************************************/
1137 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1139 struct mv643xx_eth_private *mp = netdev_priv(dev);
1140 struct net_device_stats *stats = &dev->stats;
1141 unsigned long tx_packets = 0;
1142 unsigned long tx_bytes = 0;
1143 unsigned long tx_dropped = 0;
1146 for (i = 0; i < mp->txq_count; i++) {
1147 struct tx_queue *txq = mp->txq + i;
1149 tx_packets += txq->tx_packets;
1150 tx_bytes += txq->tx_bytes;
1151 tx_dropped += txq->tx_dropped;
1154 stats->tx_packets = tx_packets;
1155 stats->tx_bytes = tx_bytes;
1156 stats->tx_dropped = tx_dropped;
1161 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1163 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1166 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1170 for (i = 0; i < 0x80; i += 4)
1174 static void mib_counters_update(struct mv643xx_eth_private *mp)
1176 struct mib_counters *p = &mp->mib_counters;
1178 spin_lock(&mp->mib_counters_lock);
1179 p->good_octets_received += mib_read(mp, 0x00);
1180 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1181 p->bad_octets_received += mib_read(mp, 0x08);
1182 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1183 p->good_frames_received += mib_read(mp, 0x10);
1184 p->bad_frames_received += mib_read(mp, 0x14);
1185 p->broadcast_frames_received += mib_read(mp, 0x18);
1186 p->multicast_frames_received += mib_read(mp, 0x1c);
1187 p->frames_64_octets += mib_read(mp, 0x20);
1188 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1189 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1190 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1191 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1192 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1193 p->good_octets_sent += mib_read(mp, 0x38);
1194 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1195 p->good_frames_sent += mib_read(mp, 0x40);
1196 p->excessive_collision += mib_read(mp, 0x44);
1197 p->multicast_frames_sent += mib_read(mp, 0x48);
1198 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1199 p->unrec_mac_control_received += mib_read(mp, 0x50);
1200 p->fc_sent += mib_read(mp, 0x54);
1201 p->good_fc_received += mib_read(mp, 0x58);
1202 p->bad_fc_received += mib_read(mp, 0x5c);
1203 p->undersize_received += mib_read(mp, 0x60);
1204 p->fragments_received += mib_read(mp, 0x64);
1205 p->oversize_received += mib_read(mp, 0x68);
1206 p->jabber_received += mib_read(mp, 0x6c);
1207 p->mac_receive_error += mib_read(mp, 0x70);
1208 p->bad_crc_event += mib_read(mp, 0x74);
1209 p->collision += mib_read(mp, 0x78);
1210 p->late_collision += mib_read(mp, 0x7c);
1211 spin_unlock(&mp->mib_counters_lock);
1213 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1216 static void mib_counters_timer_wrapper(unsigned long _mp)
1218 struct mv643xx_eth_private *mp = (void *)_mp;
1220 mib_counters_update(mp);
1224 /* interrupt coalescing *****************************************************/
1226 * Hardware coalescing parameters are set in units of 64 t_clk
1229 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1231 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1233 * In the ->set*() methods, we round the computed register value
1234 * to the nearest integer.
1236 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1238 u32 val = rdlp(mp, SDMA_CONFIG);
1241 if (mp->shared->extended_rx_coal_limit)
1242 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1244 temp = (val & 0x003fff00) >> 8;
1247 do_div(temp, mp->shared->t_clk);
1249 return (unsigned int)temp;
1252 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1257 temp = (u64)usec * mp->shared->t_clk;
1259 do_div(temp, 64000000);
1261 val = rdlp(mp, SDMA_CONFIG);
1262 if (mp->shared->extended_rx_coal_limit) {
1266 val |= (temp & 0x8000) << 10;
1267 val |= (temp & 0x7fff) << 7;
1272 val |= (temp & 0x3fff) << 8;
1274 wrlp(mp, SDMA_CONFIG, val);
1277 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1281 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1283 do_div(temp, mp->shared->t_clk);
1285 return (unsigned int)temp;
1288 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1292 temp = (u64)usec * mp->shared->t_clk;
1294 do_div(temp, 64000000);
1299 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1303 /* ethtool ******************************************************************/
1304 struct mv643xx_eth_stats {
1305 char stat_string[ETH_GSTRING_LEN];
1312 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1313 offsetof(struct net_device, stats.m), -1 }
1315 #define MIBSTAT(m) \
1316 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1317 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1319 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1328 MIBSTAT(good_octets_received),
1329 MIBSTAT(bad_octets_received),
1330 MIBSTAT(internal_mac_transmit_err),
1331 MIBSTAT(good_frames_received),
1332 MIBSTAT(bad_frames_received),
1333 MIBSTAT(broadcast_frames_received),
1334 MIBSTAT(multicast_frames_received),
1335 MIBSTAT(frames_64_octets),
1336 MIBSTAT(frames_65_to_127_octets),
1337 MIBSTAT(frames_128_to_255_octets),
1338 MIBSTAT(frames_256_to_511_octets),
1339 MIBSTAT(frames_512_to_1023_octets),
1340 MIBSTAT(frames_1024_to_max_octets),
1341 MIBSTAT(good_octets_sent),
1342 MIBSTAT(good_frames_sent),
1343 MIBSTAT(excessive_collision),
1344 MIBSTAT(multicast_frames_sent),
1345 MIBSTAT(broadcast_frames_sent),
1346 MIBSTAT(unrec_mac_control_received),
1348 MIBSTAT(good_fc_received),
1349 MIBSTAT(bad_fc_received),
1350 MIBSTAT(undersize_received),
1351 MIBSTAT(fragments_received),
1352 MIBSTAT(oversize_received),
1353 MIBSTAT(jabber_received),
1354 MIBSTAT(mac_receive_error),
1355 MIBSTAT(bad_crc_event),
1357 MIBSTAT(late_collision),
1361 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1362 struct ethtool_cmd *cmd)
1366 err = phy_read_status(mp->phy);
1368 err = phy_ethtool_gset(mp->phy, cmd);
1371 * The MAC does not support 1000baseT_Half.
1373 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1374 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1380 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1381 struct ethtool_cmd *cmd)
1385 port_status = rdlp(mp, PORT_STATUS);
1387 cmd->supported = SUPPORTED_MII;
1388 cmd->advertising = ADVERTISED_MII;
1389 switch (port_status & PORT_SPEED_MASK) {
1391 cmd->speed = SPEED_10;
1393 case PORT_SPEED_100:
1394 cmd->speed = SPEED_100;
1396 case PORT_SPEED_1000:
1397 cmd->speed = SPEED_1000;
1403 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1404 cmd->port = PORT_MII;
1405 cmd->phy_address = 0;
1406 cmd->transceiver = XCVR_INTERNAL;
1407 cmd->autoneg = AUTONEG_DISABLE;
1415 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1417 struct mv643xx_eth_private *mp = netdev_priv(dev);
1419 if (mp->phy != NULL)
1420 return mv643xx_eth_get_settings_phy(mp, cmd);
1422 return mv643xx_eth_get_settings_phyless(mp, cmd);
1426 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1428 struct mv643xx_eth_private *mp = netdev_priv(dev);
1430 if (mp->phy == NULL)
1434 * The MAC does not support 1000baseT_Half.
1436 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1438 return phy_ethtool_sset(mp->phy, cmd);
1441 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1442 struct ethtool_drvinfo *drvinfo)
1444 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1445 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1446 strncpy(drvinfo->fw_version, "N/A", 32);
1447 strncpy(drvinfo->bus_info, "platform", 32);
1448 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1451 static int mv643xx_eth_nway_reset(struct net_device *dev)
1453 struct mv643xx_eth_private *mp = netdev_priv(dev);
1455 if (mp->phy == NULL)
1458 return genphy_restart_aneg(mp->phy);
1461 static u32 mv643xx_eth_get_link(struct net_device *dev)
1463 return !!netif_carrier_ok(dev);
1467 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1469 struct mv643xx_eth_private *mp = netdev_priv(dev);
1471 ec->rx_coalesce_usecs = get_rx_coal(mp);
1472 ec->tx_coalesce_usecs = get_tx_coal(mp);
1478 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1480 struct mv643xx_eth_private *mp = netdev_priv(dev);
1482 set_rx_coal(mp, ec->rx_coalesce_usecs);
1483 set_tx_coal(mp, ec->tx_coalesce_usecs);
1488 static void mv643xx_eth_get_strings(struct net_device *dev,
1489 uint32_t stringset, uint8_t *data)
1493 if (stringset == ETH_SS_STATS) {
1494 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1495 memcpy(data + i * ETH_GSTRING_LEN,
1496 mv643xx_eth_stats[i].stat_string,
1502 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1503 struct ethtool_stats *stats,
1506 struct mv643xx_eth_private *mp = netdev_priv(dev);
1509 mv643xx_eth_get_stats(dev);
1510 mib_counters_update(mp);
1512 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1513 const struct mv643xx_eth_stats *stat;
1516 stat = mv643xx_eth_stats + i;
1518 if (stat->netdev_off >= 0)
1519 p = ((void *)mp->dev) + stat->netdev_off;
1521 p = ((void *)mp) + stat->mp_off;
1523 data[i] = (stat->sizeof_stat == 8) ?
1524 *(uint64_t *)p : *(uint32_t *)p;
1528 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1530 if (sset == ETH_SS_STATS)
1531 return ARRAY_SIZE(mv643xx_eth_stats);
1536 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1537 .get_settings = mv643xx_eth_get_settings,
1538 .set_settings = mv643xx_eth_set_settings,
1539 .get_drvinfo = mv643xx_eth_get_drvinfo,
1540 .nway_reset = mv643xx_eth_nway_reset,
1541 .get_link = mv643xx_eth_get_link,
1542 .get_coalesce = mv643xx_eth_get_coalesce,
1543 .set_coalesce = mv643xx_eth_set_coalesce,
1544 .set_sg = ethtool_op_set_sg,
1545 .get_strings = mv643xx_eth_get_strings,
1546 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1547 .get_sset_count = mv643xx_eth_get_sset_count,
1551 /* address handling *********************************************************/
1552 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1554 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1555 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1557 addr[0] = (mac_h >> 24) & 0xff;
1558 addr[1] = (mac_h >> 16) & 0xff;
1559 addr[2] = (mac_h >> 8) & 0xff;
1560 addr[3] = mac_h & 0xff;
1561 addr[4] = (mac_l >> 8) & 0xff;
1562 addr[5] = mac_l & 0xff;
1565 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1567 wrlp(mp, MAC_ADDR_HIGH,
1568 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1569 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1572 static u32 uc_addr_filter_mask(struct net_device *dev)
1574 struct dev_addr_list *uc_ptr;
1577 if (dev->flags & IFF_PROMISC)
1580 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1581 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1582 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1584 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1587 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1593 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1595 struct mv643xx_eth_private *mp = netdev_priv(dev);
1600 uc_addr_set(mp, dev->dev_addr);
1602 port_config = rdlp(mp, PORT_CONFIG);
1603 nibbles = uc_addr_filter_mask(dev);
1605 port_config |= UNICAST_PROMISCUOUS_MODE;
1606 wrlp(mp, PORT_CONFIG, port_config);
1610 for (i = 0; i < 16; i += 4) {
1611 int off = UNICAST_TABLE(mp->port_num) + i;
1628 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1629 wrlp(mp, PORT_CONFIG, port_config);
1632 static int addr_crc(unsigned char *addr)
1637 for (i = 0; i < 6; i++) {
1640 crc = (crc ^ addr[i]) << 8;
1641 for (j = 7; j >= 0; j--) {
1642 if (crc & (0x100 << j))
1650 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1652 struct mv643xx_eth_private *mp = netdev_priv(dev);
1655 struct dev_addr_list *addr;
1658 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1664 port_num = mp->port_num;
1665 accept = 0x01010101;
1666 for (i = 0; i < 0x100; i += 4) {
1667 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1668 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1673 mc_spec = kmalloc(0x200, GFP_KERNEL);
1674 if (mc_spec == NULL)
1676 mc_other = mc_spec + (0x100 >> 2);
1678 memset(mc_spec, 0, 0x100);
1679 memset(mc_other, 0, 0x100);
1681 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1682 u8 *a = addr->da_addr;
1686 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1691 entry = addr_crc(a);
1694 table[entry >> 2] |= 1 << (8 * (entry & 3));
1697 for (i = 0; i < 0x100; i += 4) {
1698 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1699 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1705 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1707 mv643xx_eth_program_unicast_filter(dev);
1708 mv643xx_eth_program_multicast_filter(dev);
1711 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1713 struct sockaddr *sa = addr;
1715 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1717 netif_addr_lock_bh(dev);
1718 mv643xx_eth_program_unicast_filter(dev);
1719 netif_addr_unlock_bh(dev);
1725 /* rx/tx queue initialisation ***********************************************/
1726 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1728 struct rx_queue *rxq = mp->rxq + index;
1729 struct rx_desc *rx_desc;
1735 rxq->rx_ring_size = mp->default_rx_ring_size;
1737 rxq->rx_desc_count = 0;
1738 rxq->rx_curr_desc = 0;
1739 rxq->rx_used_desc = 0;
1741 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1743 if (index == 0 && size <= mp->rx_desc_sram_size) {
1744 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1745 mp->rx_desc_sram_size);
1746 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1748 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1753 if (rxq->rx_desc_area == NULL) {
1754 dev_printk(KERN_ERR, &mp->dev->dev,
1755 "can't allocate rx ring (%d bytes)\n", size);
1758 memset(rxq->rx_desc_area, 0, size);
1760 rxq->rx_desc_area_size = size;
1761 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1763 if (rxq->rx_skb == NULL) {
1764 dev_printk(KERN_ERR, &mp->dev->dev,
1765 "can't allocate rx skb ring\n");
1769 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1770 for (i = 0; i < rxq->rx_ring_size; i++) {
1774 if (nexti == rxq->rx_ring_size)
1777 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1778 nexti * sizeof(struct rx_desc);
1785 if (index == 0 && size <= mp->rx_desc_sram_size)
1786 iounmap(rxq->rx_desc_area);
1788 dma_free_coherent(NULL, size,
1796 static void rxq_deinit(struct rx_queue *rxq)
1798 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1803 for (i = 0; i < rxq->rx_ring_size; i++) {
1804 if (rxq->rx_skb[i]) {
1805 dev_kfree_skb(rxq->rx_skb[i]);
1806 rxq->rx_desc_count--;
1810 if (rxq->rx_desc_count) {
1811 dev_printk(KERN_ERR, &mp->dev->dev,
1812 "error freeing rx ring -- %d skbs stuck\n",
1813 rxq->rx_desc_count);
1816 if (rxq->index == 0 &&
1817 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1818 iounmap(rxq->rx_desc_area);
1820 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1821 rxq->rx_desc_area, rxq->rx_desc_dma);
1826 static int txq_init(struct mv643xx_eth_private *mp, int index)
1828 struct tx_queue *txq = mp->txq + index;
1829 struct tx_desc *tx_desc;
1835 txq->tx_ring_size = mp->default_tx_ring_size;
1837 txq->tx_desc_count = 0;
1838 txq->tx_curr_desc = 0;
1839 txq->tx_used_desc = 0;
1841 size = txq->tx_ring_size * sizeof(struct tx_desc);
1843 if (index == 0 && size <= mp->tx_desc_sram_size) {
1844 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1845 mp->tx_desc_sram_size);
1846 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1848 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1853 if (txq->tx_desc_area == NULL) {
1854 dev_printk(KERN_ERR, &mp->dev->dev,
1855 "can't allocate tx ring (%d bytes)\n", size);
1858 memset(txq->tx_desc_area, 0, size);
1860 txq->tx_desc_area_size = size;
1862 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1863 for (i = 0; i < txq->tx_ring_size; i++) {
1864 struct tx_desc *txd = tx_desc + i;
1868 if (nexti == txq->tx_ring_size)
1872 txd->next_desc_ptr = txq->tx_desc_dma +
1873 nexti * sizeof(struct tx_desc);
1876 skb_queue_head_init(&txq->tx_skb);
1881 static void txq_deinit(struct tx_queue *txq)
1883 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1886 txq_reclaim(txq, txq->tx_ring_size, 1);
1888 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1890 if (txq->index == 0 &&
1891 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1892 iounmap(txq->tx_desc_area);
1894 dma_free_coherent(NULL, txq->tx_desc_area_size,
1895 txq->tx_desc_area, txq->tx_desc_dma);
1899 /* netdev ops and related ***************************************************/
1900 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1905 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1910 if (int_cause & INT_EXT)
1911 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1913 int_cause &= INT_TX_END | INT_RX;
1915 wrlp(mp, INT_CAUSE, ~int_cause);
1916 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1917 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1918 mp->work_rx |= (int_cause & INT_RX) >> 2;
1921 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1922 if (int_cause_ext) {
1923 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1924 if (int_cause_ext & INT_EXT_LINK_PHY)
1926 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1932 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1934 struct net_device *dev = (struct net_device *)dev_id;
1935 struct mv643xx_eth_private *mp = netdev_priv(dev);
1937 if (unlikely(!mv643xx_eth_collect_events(mp)))
1940 wrlp(mp, INT_MASK, 0);
1941 napi_schedule(&mp->napi);
1946 static void handle_link_event(struct mv643xx_eth_private *mp)
1948 struct net_device *dev = mp->dev;
1954 port_status = rdlp(mp, PORT_STATUS);
1955 if (!(port_status & LINK_UP)) {
1956 if (netif_carrier_ok(dev)) {
1959 printk(KERN_INFO "%s: link down\n", dev->name);
1961 netif_carrier_off(dev);
1963 for (i = 0; i < mp->txq_count; i++) {
1964 struct tx_queue *txq = mp->txq + i;
1966 txq_reclaim(txq, txq->tx_ring_size, 1);
1967 txq_reset_hw_ptr(txq);
1973 switch (port_status & PORT_SPEED_MASK) {
1977 case PORT_SPEED_100:
1980 case PORT_SPEED_1000:
1987 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1988 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1990 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1991 "flow control %sabled\n", dev->name,
1992 speed, duplex ? "full" : "half",
1995 if (!netif_carrier_ok(dev))
1996 netif_carrier_on(dev);
1999 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2001 struct mv643xx_eth_private *mp;
2004 mp = container_of(napi, struct mv643xx_eth_private, napi);
2006 mp->work_rx_refill |= mp->work_rx_oom;
2007 mp->work_rx_oom = 0;
2010 while (work_done < budget) {
2015 if (mp->work_link) {
2017 handle_link_event(mp);
2021 queue_mask = mp->work_tx | mp->work_tx_end |
2022 mp->work_rx | mp->work_rx_refill;
2024 if (mv643xx_eth_collect_events(mp))
2029 queue = fls(queue_mask) - 1;
2030 queue_mask = 1 << queue;
2032 work_tbd = budget - work_done;
2036 if (mp->work_tx_end & queue_mask) {
2037 txq_kick(mp->txq + queue);
2038 } else if (mp->work_tx & queue_mask) {
2039 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2040 txq_maybe_wake(mp->txq + queue);
2041 } else if (mp->work_rx & queue_mask) {
2042 work_done += rxq_process(mp->rxq + queue, work_tbd);
2043 } else if (mp->work_rx_refill & queue_mask) {
2044 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2050 if (work_done < budget) {
2051 if (mp->work_rx_oom)
2052 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2053 napi_complete(napi);
2054 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2060 static inline void oom_timer_wrapper(unsigned long data)
2062 struct mv643xx_eth_private *mp = (void *)data;
2064 napi_schedule(&mp->napi);
2067 static void phy_reset(struct mv643xx_eth_private *mp)
2071 data = phy_read(mp->phy, MII_BMCR);
2076 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2080 data = phy_read(mp->phy, MII_BMCR);
2081 } while (data >= 0 && data & BMCR_RESET);
2084 static void port_start(struct mv643xx_eth_private *mp)
2090 * Perform PHY reset, if there is a PHY.
2092 if (mp->phy != NULL) {
2093 struct ethtool_cmd cmd;
2095 mv643xx_eth_get_settings(mp->dev, &cmd);
2097 mv643xx_eth_set_settings(mp->dev, &cmd);
2101 * Configure basic link parameters.
2103 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2105 pscr |= SERIAL_PORT_ENABLE;
2106 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2108 pscr |= DO_NOT_FORCE_LINK_FAIL;
2109 if (mp->phy == NULL)
2110 pscr |= FORCE_LINK_PASS;
2111 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2113 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2116 * Configure TX path and queues.
2118 tx_set_rate(mp, 1000000000, 16777216);
2119 for (i = 0; i < mp->txq_count; i++) {
2120 struct tx_queue *txq = mp->txq + i;
2122 txq_reset_hw_ptr(txq);
2123 txq_set_rate(txq, 1000000000, 16777216);
2124 txq_set_fixed_prio_mode(txq);
2128 * Add configured unicast address to address filter table.
2130 mv643xx_eth_program_unicast_filter(mp->dev);
2133 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2134 * frames to RX queue #0, and include the pseudo-header when
2135 * calculating receive checksums.
2137 wrlp(mp, PORT_CONFIG, 0x02000000);
2140 * Treat BPDUs as normal multicasts, and disable partition mode.
2142 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2145 * Enable the receive queues.
2147 for (i = 0; i < mp->rxq_count; i++) {
2148 struct rx_queue *rxq = mp->rxq + i;
2151 addr = (u32)rxq->rx_desc_dma;
2152 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2153 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2159 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2164 * Reserve 2+14 bytes for an ethernet header (the hardware
2165 * automatically prepends 2 bytes of dummy data to each
2166 * received packet), 16 bytes for up to four VLAN tags, and
2167 * 4 bytes for the trailing FCS -- 36 bytes total.
2169 skb_size = mp->dev->mtu + 36;
2172 * Make sure that the skb size is a multiple of 8 bytes, as
2173 * the lower three bits of the receive descriptor's buffer
2174 * size field are ignored by the hardware.
2176 mp->skb_size = (skb_size + 7) & ~7;
2179 static int mv643xx_eth_open(struct net_device *dev)
2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
2185 wrlp(mp, INT_CAUSE, 0);
2186 wrlp(mp, INT_CAUSE_EXT, 0);
2187 rdlp(mp, INT_CAUSE_EXT);
2189 err = request_irq(dev->irq, mv643xx_eth_irq,
2190 IRQF_SHARED, dev->name, dev);
2192 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2196 mv643xx_eth_recalc_skb_size(mp);
2198 napi_enable(&mp->napi);
2200 skb_queue_head_init(&mp->rx_recycle);
2202 for (i = 0; i < mp->rxq_count; i++) {
2203 err = rxq_init(mp, i);
2206 rxq_deinit(mp->rxq + i);
2210 rxq_refill(mp->rxq + i, INT_MAX);
2213 if (mp->work_rx_oom) {
2214 mp->rx_oom.expires = jiffies + (HZ / 10);
2215 add_timer(&mp->rx_oom);
2218 for (i = 0; i < mp->txq_count; i++) {
2219 err = txq_init(mp, i);
2222 txq_deinit(mp->txq + i);
2227 netif_carrier_off(dev);
2234 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2235 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2241 for (i = 0; i < mp->rxq_count; i++)
2242 rxq_deinit(mp->rxq + i);
2244 free_irq(dev->irq, dev);
2249 static void port_reset(struct mv643xx_eth_private *mp)
2254 for (i = 0; i < mp->rxq_count; i++)
2255 rxq_disable(mp->rxq + i);
2256 for (i = 0; i < mp->txq_count; i++)
2257 txq_disable(mp->txq + i);
2260 u32 ps = rdlp(mp, PORT_STATUS);
2262 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2267 /* Reset the Enable bit in the Configuration Register */
2268 data = rdlp(mp, PORT_SERIAL_CONTROL);
2269 data &= ~(SERIAL_PORT_ENABLE |
2270 DO_NOT_FORCE_LINK_FAIL |
2272 wrlp(mp, PORT_SERIAL_CONTROL, data);
2275 static int mv643xx_eth_stop(struct net_device *dev)
2277 struct mv643xx_eth_private *mp = netdev_priv(dev);
2280 wrlp(mp, INT_MASK_EXT, 0x00000000);
2281 wrlp(mp, INT_MASK, 0x00000000);
2284 del_timer_sync(&mp->mib_counters_timer);
2286 napi_disable(&mp->napi);
2288 del_timer_sync(&mp->rx_oom);
2290 netif_carrier_off(dev);
2292 free_irq(dev->irq, dev);
2295 mv643xx_eth_get_stats(dev);
2296 mib_counters_update(mp);
2298 skb_queue_purge(&mp->rx_recycle);
2300 for (i = 0; i < mp->rxq_count; i++)
2301 rxq_deinit(mp->rxq + i);
2302 for (i = 0; i < mp->txq_count; i++)
2303 txq_deinit(mp->txq + i);
2308 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2310 struct mv643xx_eth_private *mp = netdev_priv(dev);
2312 if (mp->phy != NULL)
2313 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2318 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2320 struct mv643xx_eth_private *mp = netdev_priv(dev);
2322 if (new_mtu < 64 || new_mtu > 9500)
2326 mv643xx_eth_recalc_skb_size(mp);
2327 tx_set_rate(mp, 1000000000, 16777216);
2329 if (!netif_running(dev))
2333 * Stop and then re-open the interface. This will allocate RX
2334 * skbs of the new MTU.
2335 * There is a possible danger that the open will not succeed,
2336 * due to memory being full.
2338 mv643xx_eth_stop(dev);
2339 if (mv643xx_eth_open(dev)) {
2340 dev_printk(KERN_ERR, &dev->dev,
2341 "fatal error on re-opening device after "
2348 static void tx_timeout_task(struct work_struct *ugly)
2350 struct mv643xx_eth_private *mp;
2352 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2353 if (netif_running(mp->dev)) {
2354 netif_tx_stop_all_queues(mp->dev);
2357 netif_tx_wake_all_queues(mp->dev);
2361 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2363 struct mv643xx_eth_private *mp = netdev_priv(dev);
2365 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2367 schedule_work(&mp->tx_timeout_task);
2370 #ifdef CONFIG_NET_POLL_CONTROLLER
2371 static void mv643xx_eth_netpoll(struct net_device *dev)
2373 struct mv643xx_eth_private *mp = netdev_priv(dev);
2375 wrlp(mp, INT_MASK, 0x00000000);
2378 mv643xx_eth_irq(dev->irq, dev);
2380 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2385 /* platform glue ************************************************************/
2387 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2388 struct mbus_dram_target_info *dram)
2390 void __iomem *base = msp->base;
2395 for (i = 0; i < 6; i++) {
2396 writel(0, base + WINDOW_BASE(i));
2397 writel(0, base + WINDOW_SIZE(i));
2399 writel(0, base + WINDOW_REMAP_HIGH(i));
2405 for (i = 0; i < dram->num_cs; i++) {
2406 struct mbus_dram_window *cs = dram->cs + i;
2408 writel((cs->base & 0xffff0000) |
2409 (cs->mbus_attr << 8) |
2410 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2411 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2413 win_enable &= ~(1 << i);
2414 win_protect |= 3 << (2 * i);
2417 writel(win_enable, base + WINDOW_BAR_ENABLE);
2418 msp->win_protect = win_protect;
2421 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2424 * Check whether we have a 14-bit coal limit field in bits
2425 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2426 * SDMA config register.
2428 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2429 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2430 msp->extended_rx_coal_limit = 1;
2432 msp->extended_rx_coal_limit = 0;
2435 * Check whether the MAC supports TX rate control, and if
2436 * yes, whether its associated registers are in the old or
2439 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2440 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2441 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2443 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2444 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2445 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2447 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2451 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2453 static int mv643xx_eth_version_printed;
2454 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2455 struct mv643xx_eth_shared_private *msp;
2456 struct resource *res;
2459 if (!mv643xx_eth_version_printed++)
2460 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2461 "driver version %s\n", mv643xx_eth_driver_version);
2464 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2469 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2472 memset(msp, 0, sizeof(*msp));
2474 msp->base = ioremap(res->start, res->end - res->start + 1);
2475 if (msp->base == NULL)
2479 * Set up and register SMI bus.
2481 if (pd == NULL || pd->shared_smi == NULL) {
2482 msp->smi_bus = mdiobus_alloc();
2483 if (msp->smi_bus == NULL)
2486 msp->smi_bus->priv = msp;
2487 msp->smi_bus->name = "mv643xx_eth smi";
2488 msp->smi_bus->read = smi_bus_read;
2489 msp->smi_bus->write = smi_bus_write,
2490 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2491 msp->smi_bus->parent = &pdev->dev;
2492 msp->smi_bus->phy_mask = 0xffffffff;
2493 if (mdiobus_register(msp->smi_bus) < 0)
2494 goto out_free_mii_bus;
2497 msp->smi = platform_get_drvdata(pd->shared_smi);
2500 msp->err_interrupt = NO_IRQ;
2501 init_waitqueue_head(&msp->smi_busy_wait);
2504 * Check whether the error interrupt is hooked up.
2506 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2510 err = request_irq(res->start, mv643xx_eth_err_irq,
2511 IRQF_SHARED, "mv643xx_eth", msp);
2513 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2514 msp->err_interrupt = res->start;
2519 * (Re-)program MBUS remapping windows if we are asked to.
2521 if (pd != NULL && pd->dram != NULL)
2522 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2525 * Detect hardware parameters.
2527 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2528 infer_hw_params(msp);
2530 platform_set_drvdata(pdev, msp);
2535 mdiobus_free(msp->smi_bus);
2544 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2546 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2547 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2549 if (pd == NULL || pd->shared_smi == NULL) {
2550 mdiobus_unregister(msp->smi_bus);
2551 mdiobus_free(msp->smi_bus);
2553 if (msp->err_interrupt != NO_IRQ)
2554 free_irq(msp->err_interrupt, msp);
2561 static struct platform_driver mv643xx_eth_shared_driver = {
2562 .probe = mv643xx_eth_shared_probe,
2563 .remove = mv643xx_eth_shared_remove,
2565 .name = MV643XX_ETH_SHARED_NAME,
2566 .owner = THIS_MODULE,
2570 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2572 int addr_shift = 5 * mp->port_num;
2575 data = rdl(mp, PHY_ADDR);
2576 data &= ~(0x1f << addr_shift);
2577 data |= (phy_addr & 0x1f) << addr_shift;
2578 wrl(mp, PHY_ADDR, data);
2581 static int phy_addr_get(struct mv643xx_eth_private *mp)
2585 data = rdl(mp, PHY_ADDR);
2587 return (data >> (5 * mp->port_num)) & 0x1f;
2590 static void set_params(struct mv643xx_eth_private *mp,
2591 struct mv643xx_eth_platform_data *pd)
2593 struct net_device *dev = mp->dev;
2595 if (is_valid_ether_addr(pd->mac_addr))
2596 memcpy(dev->dev_addr, pd->mac_addr, 6);
2598 uc_addr_get(mp, dev->dev_addr);
2600 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2601 if (pd->rx_queue_size)
2602 mp->default_rx_ring_size = pd->rx_queue_size;
2603 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2604 mp->rx_desc_sram_size = pd->rx_sram_size;
2606 mp->rxq_count = pd->rx_queue_count ? : 1;
2608 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2609 if (pd->tx_queue_size)
2610 mp->default_tx_ring_size = pd->tx_queue_size;
2611 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2612 mp->tx_desc_sram_size = pd->tx_sram_size;
2614 mp->txq_count = pd->tx_queue_count ? : 1;
2617 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2620 struct mii_bus *bus = mp->shared->smi->smi_bus;
2621 struct phy_device *phydev;
2626 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2627 start = phy_addr_get(mp) & 0x1f;
2630 start = phy_addr & 0x1f;
2635 for (i = 0; i < num; i++) {
2636 int addr = (start + i) & 0x1f;
2638 if (bus->phy_map[addr] == NULL)
2639 mdiobus_scan(bus, addr);
2641 if (phydev == NULL) {
2642 phydev = bus->phy_map[addr];
2644 phy_addr_set(mp, addr);
2651 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2653 struct phy_device *phy = mp->phy;
2657 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2660 phy->autoneg = AUTONEG_ENABLE;
2663 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2665 phy->autoneg = AUTONEG_DISABLE;
2666 phy->advertising = 0;
2668 phy->duplex = duplex;
2670 phy_start_aneg(phy);
2673 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2677 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2678 if (pscr & SERIAL_PORT_ENABLE) {
2679 pscr &= ~SERIAL_PORT_ENABLE;
2680 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2683 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2684 if (mp->phy == NULL) {
2685 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2686 if (speed == SPEED_1000)
2687 pscr |= SET_GMII_SPEED_TO_1000;
2688 else if (speed == SPEED_100)
2689 pscr |= SET_MII_SPEED_TO_100;
2691 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2693 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2694 if (duplex == DUPLEX_FULL)
2695 pscr |= SET_FULL_DUPLEX_MODE;
2698 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2701 static int mv643xx_eth_probe(struct platform_device *pdev)
2703 struct mv643xx_eth_platform_data *pd;
2704 struct mv643xx_eth_private *mp;
2705 struct net_device *dev;
2706 struct resource *res;
2709 pd = pdev->dev.platform_data;
2711 dev_printk(KERN_ERR, &pdev->dev,
2712 "no mv643xx_eth_platform_data\n");
2716 if (pd->shared == NULL) {
2717 dev_printk(KERN_ERR, &pdev->dev,
2718 "no mv643xx_eth_platform_data->shared\n");
2722 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2726 mp = netdev_priv(dev);
2727 platform_set_drvdata(pdev, mp);
2729 mp->shared = platform_get_drvdata(pd->shared);
2730 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2731 mp->port_num = pd->port_number;
2736 dev->real_num_tx_queues = mp->txq_count;
2738 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2739 mp->phy = phy_scan(mp, pd->phy_addr);
2741 if (mp->phy != NULL)
2742 phy_init(mp, pd->speed, pd->duplex);
2744 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2746 init_pscr(mp, pd->speed, pd->duplex);
2749 mib_counters_clear(mp);
2751 init_timer(&mp->mib_counters_timer);
2752 mp->mib_counters_timer.data = (unsigned long)mp;
2753 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2754 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2755 add_timer(&mp->mib_counters_timer);
2757 spin_lock_init(&mp->mib_counters_lock);
2759 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2761 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2763 init_timer(&mp->rx_oom);
2764 mp->rx_oom.data = (unsigned long)mp;
2765 mp->rx_oom.function = oom_timer_wrapper;
2768 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2770 dev->irq = res->start;
2772 dev->get_stats = mv643xx_eth_get_stats;
2773 dev->hard_start_xmit = mv643xx_eth_xmit;
2774 dev->open = mv643xx_eth_open;
2775 dev->stop = mv643xx_eth_stop;
2776 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
2777 dev->set_mac_address = mv643xx_eth_set_mac_address;
2778 dev->do_ioctl = mv643xx_eth_ioctl;
2779 dev->change_mtu = mv643xx_eth_change_mtu;
2780 dev->tx_timeout = mv643xx_eth_tx_timeout;
2781 #ifdef CONFIG_NET_POLL_CONTROLLER
2782 dev->poll_controller = mv643xx_eth_netpoll;
2784 dev->watchdog_timeo = 2 * HZ;
2787 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2788 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2790 SET_NETDEV_DEV(dev, &pdev->dev);
2792 if (mp->shared->win_protect)
2793 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2795 err = register_netdev(dev);
2799 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2800 mp->port_num, dev->dev_addr);
2802 if (mp->tx_desc_sram_size > 0)
2803 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2813 static int mv643xx_eth_remove(struct platform_device *pdev)
2815 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2817 unregister_netdev(mp->dev);
2818 if (mp->phy != NULL)
2819 phy_detach(mp->phy);
2820 flush_scheduled_work();
2821 free_netdev(mp->dev);
2823 platform_set_drvdata(pdev, NULL);
2828 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2830 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2832 /* Mask all interrupts on ethernet port */
2833 wrlp(mp, INT_MASK, 0);
2836 if (netif_running(mp->dev))
2840 static struct platform_driver mv643xx_eth_driver = {
2841 .probe = mv643xx_eth_probe,
2842 .remove = mv643xx_eth_remove,
2843 .shutdown = mv643xx_eth_shutdown,
2845 .name = MV643XX_ETH_NAME,
2846 .owner = THIS_MODULE,
2850 static int __init mv643xx_eth_init_module(void)
2854 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2856 rc = platform_driver_register(&mv643xx_eth_driver);
2858 platform_driver_unregister(&mv643xx_eth_shared_driver);
2863 module_init(mv643xx_eth_init_module);
2865 static void __exit mv643xx_eth_cleanup_module(void)
2867 platform_driver_unregister(&mv643xx_eth_driver);
2868 platform_driver_unregister(&mv643xx_eth_shared_driver);
2870 module_exit(mv643xx_eth_cleanup_module);
2872 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2873 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2874 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2875 MODULE_LICENSE("GPL");
2876 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2877 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);