2 * drivers/net/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
4 * Copyright (c) 2009-2010 Micrel, Inc.
5 * Tristram Ha <Tristram.Ha@micrel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/ioport.h>
23 #include <linux/pci.h>
24 #include <linux/proc_fs.h>
25 #include <linux/mii.h>
26 #include <linux/platform_device.h>
27 #include <linux/ethtool.h>
28 #include <linux/etherdevice.h>
31 #include <linux/if_vlan.h>
32 #include <linux/crc32.h>
33 #include <linux/sched.h>
38 #define KS_DMA_TX_CTRL 0x0000
39 #define DMA_TX_ENABLE 0x00000001
40 #define DMA_TX_CRC_ENABLE 0x00000002
41 #define DMA_TX_PAD_ENABLE 0x00000004
42 #define DMA_TX_LOOPBACK 0x00000100
43 #define DMA_TX_FLOW_ENABLE 0x00000200
44 #define DMA_TX_CSUM_IP 0x00010000
45 #define DMA_TX_CSUM_TCP 0x00020000
46 #define DMA_TX_CSUM_UDP 0x00040000
47 #define DMA_TX_BURST_SIZE 0x3F000000
49 #define KS_DMA_RX_CTRL 0x0004
50 #define DMA_RX_ENABLE 0x00000001
51 #define KS884X_DMA_RX_MULTICAST 0x00000002
52 #define DMA_RX_PROMISCUOUS 0x00000004
53 #define DMA_RX_ERROR 0x00000008
54 #define DMA_RX_UNICAST 0x00000010
55 #define DMA_RX_ALL_MULTICAST 0x00000020
56 #define DMA_RX_BROADCAST 0x00000040
57 #define DMA_RX_FLOW_ENABLE 0x00000200
58 #define DMA_RX_CSUM_IP 0x00010000
59 #define DMA_RX_CSUM_TCP 0x00020000
60 #define DMA_RX_CSUM_UDP 0x00040000
61 #define DMA_RX_BURST_SIZE 0x3F000000
63 #define DMA_BURST_SHIFT 24
64 #define DMA_BURST_DEFAULT 8
66 #define KS_DMA_TX_START 0x0008
67 #define KS_DMA_RX_START 0x000C
68 #define DMA_START 0x00000001
70 #define KS_DMA_TX_ADDR 0x0010
71 #define KS_DMA_RX_ADDR 0x0014
73 #define DMA_ADDR_LIST_MASK 0xFFFFFFFC
74 #define DMA_ADDR_LIST_SHIFT 2
77 #define KS884X_MULTICAST_0_OFFSET 0x0020
78 #define KS884X_MULTICAST_1_OFFSET 0x0021
79 #define KS884X_MULTICAST_2_OFFSET 0x0022
80 #define KS884x_MULTICAST_3_OFFSET 0x0023
82 #define KS884X_MULTICAST_4_OFFSET 0x0024
83 #define KS884X_MULTICAST_5_OFFSET 0x0025
84 #define KS884X_MULTICAST_6_OFFSET 0x0026
85 #define KS884X_MULTICAST_7_OFFSET 0x0027
87 /* Interrupt Registers */
90 #define KS884X_INTERRUPTS_ENABLE 0x0028
92 #define KS884X_INTERRUPTS_STATUS 0x002C
94 #define KS884X_INT_RX_STOPPED 0x02000000
95 #define KS884X_INT_TX_STOPPED 0x04000000
96 #define KS884X_INT_RX_OVERRUN 0x08000000
97 #define KS884X_INT_TX_EMPTY 0x10000000
98 #define KS884X_INT_RX 0x20000000
99 #define KS884X_INT_TX 0x40000000
100 #define KS884X_INT_PHY 0x80000000
102 #define KS884X_INT_RX_MASK \
103 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
104 #define KS884X_INT_TX_MASK \
105 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
106 #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
108 /* MAC Additional Station Address */
111 #define KS_ADD_ADDR_0_LO 0x0080
113 #define KS_ADD_ADDR_0_HI 0x0084
115 #define KS_ADD_ADDR_1_LO 0x0088
117 #define KS_ADD_ADDR_1_HI 0x008C
119 #define KS_ADD_ADDR_2_LO 0x0090
121 #define KS_ADD_ADDR_2_HI 0x0094
123 #define KS_ADD_ADDR_3_LO 0x0098
125 #define KS_ADD_ADDR_3_HI 0x009C
127 #define KS_ADD_ADDR_4_LO 0x00A0
129 #define KS_ADD_ADDR_4_HI 0x00A4
131 #define KS_ADD_ADDR_5_LO 0x00A8
133 #define KS_ADD_ADDR_5_HI 0x00AC
135 #define KS_ADD_ADDR_6_LO 0x00B0
137 #define KS_ADD_ADDR_6_HI 0x00B4
139 #define KS_ADD_ADDR_7_LO 0x00B8
141 #define KS_ADD_ADDR_7_HI 0x00BC
143 #define KS_ADD_ADDR_8_LO 0x00C0
145 #define KS_ADD_ADDR_8_HI 0x00C4
147 #define KS_ADD_ADDR_9_LO 0x00C8
149 #define KS_ADD_ADDR_9_HI 0x00CC
151 #define KS_ADD_ADDR_A_LO 0x00D0
153 #define KS_ADD_ADDR_A_HI 0x00D4
155 #define KS_ADD_ADDR_B_LO 0x00D8
157 #define KS_ADD_ADDR_B_HI 0x00DC
159 #define KS_ADD_ADDR_C_LO 0x00E0
161 #define KS_ADD_ADDR_C_HI 0x00E4
163 #define KS_ADD_ADDR_D_LO 0x00E8
165 #define KS_ADD_ADDR_D_HI 0x00EC
167 #define KS_ADD_ADDR_E_LO 0x00F0
169 #define KS_ADD_ADDR_E_HI 0x00F4
171 #define KS_ADD_ADDR_F_LO 0x00F8
173 #define KS_ADD_ADDR_F_HI 0x00FC
175 #define ADD_ADDR_HI_MASK 0x0000FFFF
176 #define ADD_ADDR_ENABLE 0x80000000
177 #define ADD_ADDR_INCR 8
179 /* Miscellaneous Registers */
182 #define KS884X_ADDR_0_OFFSET 0x0200
183 #define KS884X_ADDR_1_OFFSET 0x0201
185 #define KS884X_ADDR_2_OFFSET 0x0202
186 #define KS884X_ADDR_3_OFFSET 0x0203
188 #define KS884X_ADDR_4_OFFSET 0x0204
189 #define KS884X_ADDR_5_OFFSET 0x0205
192 #define KS884X_BUS_CTRL_OFFSET 0x0210
194 #define BUS_SPEED_125_MHZ 0x0000
195 #define BUS_SPEED_62_5_MHZ 0x0001
196 #define BUS_SPEED_41_66_MHZ 0x0002
197 #define BUS_SPEED_25_MHZ 0x0003
200 #define KS884X_EEPROM_CTRL_OFFSET 0x0212
202 #define EEPROM_CHIP_SELECT 0x0001
203 #define EEPROM_SERIAL_CLOCK 0x0002
204 #define EEPROM_DATA_OUT 0x0004
205 #define EEPROM_DATA_IN 0x0008
206 #define EEPROM_ACCESS_ENABLE 0x0010
209 #define KS884X_MEM_INFO_OFFSET 0x0214
211 #define RX_MEM_TEST_FAILED 0x0008
212 #define RX_MEM_TEST_FINISHED 0x0010
213 #define TX_MEM_TEST_FAILED 0x0800
214 #define TX_MEM_TEST_FINISHED 0x1000
217 #define KS884X_GLOBAL_CTRL_OFFSET 0x0216
218 #define GLOBAL_SOFTWARE_RESET 0x0001
220 #define KS8841_POWER_MANAGE_OFFSET 0x0218
223 #define KS8841_WOL_CTRL_OFFSET 0x021A
224 #define KS8841_WOL_MAGIC_ENABLE 0x0080
225 #define KS8841_WOL_FRAME3_ENABLE 0x0008
226 #define KS8841_WOL_FRAME2_ENABLE 0x0004
227 #define KS8841_WOL_FRAME1_ENABLE 0x0002
228 #define KS8841_WOL_FRAME0_ENABLE 0x0001
231 #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
232 #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
233 #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
236 #define KS884X_IACR_P 0x04A0
237 #define KS884X_IACR_OFFSET KS884X_IACR_P
240 #define KS884X_IADR1_P 0x04A2
241 #define KS884X_IADR2_P 0x04A4
242 #define KS884X_IADR3_P 0x04A6
243 #define KS884X_IADR4_P 0x04A8
244 #define KS884X_IADR5_P 0x04AA
246 #define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
247 #define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
249 #define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
250 #define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
251 #define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
252 #define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
253 #define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
254 #define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
255 #define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
256 #define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
257 #define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
260 #define KS884X_P1MBCR_P 0x04D0
261 #define KS884X_P1MBSR_P 0x04D2
262 #define KS884X_PHY1ILR_P 0x04D4
263 #define KS884X_PHY1IHR_P 0x04D6
264 #define KS884X_P1ANAR_P 0x04D8
265 #define KS884X_P1ANLPR_P 0x04DA
268 #define KS884X_P2MBCR_P 0x04E0
269 #define KS884X_P2MBSR_P 0x04E2
270 #define KS884X_PHY2ILR_P 0x04E4
271 #define KS884X_PHY2IHR_P 0x04E6
272 #define KS884X_P2ANAR_P 0x04E8
273 #define KS884X_P2ANLPR_P 0x04EA
275 #define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
276 #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
278 #define KS884X_PHY_CTRL_OFFSET 0x00
280 /* Mode Control Register */
281 #define PHY_REG_CTRL 0
283 #define PHY_RESET 0x8000
284 #define PHY_LOOPBACK 0x4000
285 #define PHY_SPEED_100MBIT 0x2000
286 #define PHY_AUTO_NEG_ENABLE 0x1000
287 #define PHY_POWER_DOWN 0x0800
288 #define PHY_MII_DISABLE 0x0400
289 #define PHY_AUTO_NEG_RESTART 0x0200
290 #define PHY_FULL_DUPLEX 0x0100
291 #define PHY_COLLISION_TEST 0x0080
292 #define PHY_HP_MDIX 0x0020
293 #define PHY_FORCE_MDIX 0x0010
294 #define PHY_AUTO_MDIX_DISABLE 0x0008
295 #define PHY_REMOTE_FAULT_DISABLE 0x0004
296 #define PHY_TRANSMIT_DISABLE 0x0002
297 #define PHY_LED_DISABLE 0x0001
299 #define KS884X_PHY_STATUS_OFFSET 0x02
301 /* Mode Status Register */
302 #define PHY_REG_STATUS 1
304 #define PHY_100BT4_CAPABLE 0x8000
305 #define PHY_100BTX_FD_CAPABLE 0x4000
306 #define PHY_100BTX_CAPABLE 0x2000
307 #define PHY_10BT_FD_CAPABLE 0x1000
308 #define PHY_10BT_CAPABLE 0x0800
309 #define PHY_MII_SUPPRESS_CAPABLE 0x0040
310 #define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
311 #define PHY_REMOTE_FAULT 0x0010
312 #define PHY_AUTO_NEG_CAPABLE 0x0008
313 #define PHY_LINK_STATUS 0x0004
314 #define PHY_JABBER_DETECT 0x0002
315 #define PHY_EXTENDED_CAPABILITY 0x0001
317 #define KS884X_PHY_ID_1_OFFSET 0x04
318 #define KS884X_PHY_ID_2_OFFSET 0x06
320 /* PHY Identifier Registers */
321 #define PHY_REG_ID_1 2
322 #define PHY_REG_ID_2 3
324 #define KS884X_PHY_AUTO_NEG_OFFSET 0x08
326 /* Auto-Negotiation Advertisement Register */
327 #define PHY_REG_AUTO_NEGOTIATION 4
329 #define PHY_AUTO_NEG_NEXT_PAGE 0x8000
330 #define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
332 #define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
333 #define PHY_AUTO_NEG_SYM_PAUSE 0x0400
334 #define PHY_AUTO_NEG_100BT4 0x0200
335 #define PHY_AUTO_NEG_100BTX_FD 0x0100
336 #define PHY_AUTO_NEG_100BTX 0x0080
337 #define PHY_AUTO_NEG_10BT_FD 0x0040
338 #define PHY_AUTO_NEG_10BT 0x0020
339 #define PHY_AUTO_NEG_SELECTOR 0x001F
340 #define PHY_AUTO_NEG_802_3 0x0001
342 #define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
344 #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
346 /* Auto-Negotiation Link Partner Ability Register */
347 #define PHY_REG_REMOTE_CAPABILITY 5
349 #define PHY_REMOTE_NEXT_PAGE 0x8000
350 #define PHY_REMOTE_ACKNOWLEDGE 0x4000
351 #define PHY_REMOTE_REMOTE_FAULT 0x2000
352 #define PHY_REMOTE_SYM_PAUSE 0x0400
353 #define PHY_REMOTE_100BTX_FD 0x0100
354 #define PHY_REMOTE_100BTX 0x0080
355 #define PHY_REMOTE_10BT_FD 0x0040
356 #define PHY_REMOTE_10BT 0x0020
359 #define KS884X_P1VCT_P 0x04F0
360 #define KS884X_P1PHYCTRL_P 0x04F2
363 #define KS884X_P2VCT_P 0x04F4
364 #define KS884X_P2PHYCTRL_P 0x04F6
366 #define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
367 #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
369 #define KS884X_PHY_LINK_MD_OFFSET 0x00
371 #define PHY_START_CABLE_DIAG 0x8000
372 #define PHY_CABLE_DIAG_RESULT 0x6000
373 #define PHY_CABLE_STAT_NORMAL 0x0000
374 #define PHY_CABLE_STAT_OPEN 0x2000
375 #define PHY_CABLE_STAT_SHORT 0x4000
376 #define PHY_CABLE_STAT_FAILED 0x6000
377 #define PHY_CABLE_10M_SHORT 0x1000
378 #define PHY_CABLE_FAULT_COUNTER 0x01FF
380 #define KS884X_PHY_PHY_CTRL_OFFSET 0x02
382 #define PHY_STAT_REVERSED_POLARITY 0x0020
383 #define PHY_STAT_MDIX 0x0010
384 #define PHY_FORCE_LINK 0x0008
385 #define PHY_POWER_SAVING_DISABLE 0x0004
386 #define PHY_REMOTE_LOOPBACK 0x0002
389 #define KS884X_SIDER_P 0x0400
390 #define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
391 #define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
393 #define REG_FAMILY_ID 0x88
395 #define REG_CHIP_ID_41 0x8810
396 #define REG_CHIP_ID_42 0x8800
398 #define KS884X_CHIP_ID_MASK_41 0xFF10
399 #define KS884X_CHIP_ID_MASK 0xFFF0
400 #define KS884X_CHIP_ID_SHIFT 4
401 #define KS884X_REVISION_MASK 0x000E
402 #define KS884X_REVISION_SHIFT 1
403 #define KS8842_START 0x0001
405 #define CHIP_IP_41_M 0x8810
406 #define CHIP_IP_42_M 0x8800
407 #define CHIP_IP_61_M 0x8890
408 #define CHIP_IP_62_M 0x8880
410 #define CHIP_IP_41_P 0x8850
411 #define CHIP_IP_42_P 0x8840
412 #define CHIP_IP_61_P 0x88D0
413 #define CHIP_IP_62_P 0x88C0
416 #define KS8842_SGCR1_P 0x0402
417 #define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
419 #define SWITCH_PASS_ALL 0x8000
420 #define SWITCH_TX_FLOW_CTRL 0x2000
421 #define SWITCH_RX_FLOW_CTRL 0x1000
422 #define SWITCH_CHECK_LENGTH 0x0800
423 #define SWITCH_AGING_ENABLE 0x0400
424 #define SWITCH_FAST_AGING 0x0200
425 #define SWITCH_AGGR_BACKOFF 0x0100
426 #define SWITCH_PASS_PAUSE 0x0008
427 #define SWITCH_LINK_AUTO_AGING 0x0001
430 #define KS8842_SGCR2_P 0x0404
431 #define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
433 #define SWITCH_VLAN_ENABLE 0x8000
434 #define SWITCH_IGMP_SNOOP 0x4000
435 #define IPV6_MLD_SNOOP_ENABLE 0x2000
436 #define IPV6_MLD_SNOOP_OPTION 0x1000
437 #define PRIORITY_SCHEME_SELECT 0x0800
438 #define SWITCH_MIRROR_RX_TX 0x0100
439 #define UNICAST_VLAN_BOUNDARY 0x0080
440 #define MULTICAST_STORM_DISABLE 0x0040
441 #define SWITCH_BACK_PRESSURE 0x0020
442 #define FAIR_FLOW_CTRL 0x0010
443 #define NO_EXC_COLLISION_DROP 0x0008
444 #define SWITCH_HUGE_PACKET 0x0004
445 #define SWITCH_LEGAL_PACKET 0x0002
446 #define SWITCH_BUF_RESERVE 0x0001
449 #define KS8842_SGCR3_P 0x0406
450 #define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
452 #define BROADCAST_STORM_RATE_LO 0xFF00
453 #define SWITCH_REPEATER 0x0080
454 #define SWITCH_HALF_DUPLEX 0x0040
455 #define SWITCH_FLOW_CTRL 0x0020
456 #define SWITCH_10_MBIT 0x0010
457 #define SWITCH_REPLACE_NULL_VID 0x0008
458 #define BROADCAST_STORM_RATE_HI 0x0007
460 #define BROADCAST_STORM_RATE 0x07FF
463 #define KS8842_SGCR4_P 0x0408
466 #define KS8842_SGCR5_P 0x040A
467 #define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
469 #define LED_MODE 0x8200
470 #define LED_SPEED_DUPLEX_ACT 0x0000
471 #define LED_SPEED_DUPLEX_LINK_ACT 0x8000
472 #define LED_DUPLEX_10_100 0x0200
475 #define KS8842_SGCR6_P 0x0410
476 #define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
478 #define KS8842_PRIORITY_MASK 3
479 #define KS8842_PRIORITY_SHIFT 2
482 #define KS8842_SGCR7_P 0x0412
483 #define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
485 #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
486 #define SWITCH_UNK_DEF_PORT_3 0x0004
487 #define SWITCH_UNK_DEF_PORT_2 0x0002
488 #define SWITCH_UNK_DEF_PORT_1 0x0001
491 #define KS8842_MACAR1_P 0x0470
492 #define KS8842_MACAR2_P 0x0472
493 #define KS8842_MACAR3_P 0x0474
494 #define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
495 #define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
496 #define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
497 #define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
498 #define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
499 #define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
502 #define KS8842_TOSR1_P 0x0480
503 #define KS8842_TOSR2_P 0x0482
504 #define KS8842_TOSR3_P 0x0484
505 #define KS8842_TOSR4_P 0x0486
506 #define KS8842_TOSR5_P 0x0488
507 #define KS8842_TOSR6_P 0x048A
508 #define KS8842_TOSR7_P 0x0490
509 #define KS8842_TOSR8_P 0x0492
510 #define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
511 #define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
512 #define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
513 #define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
514 #define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
515 #define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
517 #define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
518 #define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
521 #define KS8842_P1CR1_P 0x0500
522 #define KS8842_P1CR2_P 0x0502
523 #define KS8842_P1VIDR_P 0x0504
524 #define KS8842_P1CR3_P 0x0506
525 #define KS8842_P1IRCR_P 0x0508
526 #define KS8842_P1ERCR_P 0x050A
527 #define KS884X_P1SCSLMD_P 0x0510
528 #define KS884X_P1CR4_P 0x0512
529 #define KS884X_P1SR_P 0x0514
532 #define KS8842_P2CR1_P 0x0520
533 #define KS8842_P2CR2_P 0x0522
534 #define KS8842_P2VIDR_P 0x0524
535 #define KS8842_P2CR3_P 0x0526
536 #define KS8842_P2IRCR_P 0x0528
537 #define KS8842_P2ERCR_P 0x052A
538 #define KS884X_P2SCSLMD_P 0x0530
539 #define KS884X_P2CR4_P 0x0532
540 #define KS884X_P2SR_P 0x0534
543 #define KS8842_P3CR1_P 0x0540
544 #define KS8842_P3CR2_P 0x0542
545 #define KS8842_P3VIDR_P 0x0544
546 #define KS8842_P3CR3_P 0x0546
547 #define KS8842_P3IRCR_P 0x0548
548 #define KS8842_P3ERCR_P 0x054A
550 #define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
551 #define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
552 #define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
554 #define PORT_CTRL_ADDR(port, addr) \
555 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
556 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
558 #define KS8842_PORT_CTRL_1_OFFSET 0x00
560 #define PORT_BROADCAST_STORM 0x0080
561 #define PORT_DIFFSERV_ENABLE 0x0040
562 #define PORT_802_1P_ENABLE 0x0020
563 #define PORT_BASED_PRIORITY_MASK 0x0018
564 #define PORT_BASED_PRIORITY_BASE 0x0003
565 #define PORT_BASED_PRIORITY_SHIFT 3
566 #define PORT_BASED_PRIORITY_0 0x0000
567 #define PORT_BASED_PRIORITY_1 0x0008
568 #define PORT_BASED_PRIORITY_2 0x0010
569 #define PORT_BASED_PRIORITY_3 0x0018
570 #define PORT_INSERT_TAG 0x0004
571 #define PORT_REMOVE_TAG 0x0002
572 #define PORT_PRIO_QUEUE_ENABLE 0x0001
574 #define KS8842_PORT_CTRL_2_OFFSET 0x02
576 #define PORT_INGRESS_VLAN_FILTER 0x4000
577 #define PORT_DISCARD_NON_VID 0x2000
578 #define PORT_FORCE_FLOW_CTRL 0x1000
579 #define PORT_BACK_PRESSURE 0x0800
580 #define PORT_TX_ENABLE 0x0400
581 #define PORT_RX_ENABLE 0x0200
582 #define PORT_LEARN_DISABLE 0x0100
583 #define PORT_MIRROR_SNIFFER 0x0080
584 #define PORT_MIRROR_RX 0x0040
585 #define PORT_MIRROR_TX 0x0020
586 #define PORT_USER_PRIORITY_CEILING 0x0008
587 #define PORT_VLAN_MEMBERSHIP 0x0007
589 #define KS8842_PORT_CTRL_VID_OFFSET 0x04
591 #define PORT_DEFAULT_VID 0x0001
593 #define KS8842_PORT_CTRL_3_OFFSET 0x06
595 #define PORT_INGRESS_LIMIT_MODE 0x000C
596 #define PORT_INGRESS_ALL 0x0000
597 #define PORT_INGRESS_UNICAST 0x0004
598 #define PORT_INGRESS_MULTICAST 0x0008
599 #define PORT_INGRESS_BROADCAST 0x000C
600 #define PORT_COUNT_IFG 0x0002
601 #define PORT_COUNT_PREAMBLE 0x0001
603 #define KS8842_PORT_IN_RATE_OFFSET 0x08
604 #define KS8842_PORT_OUT_RATE_OFFSET 0x0A
606 #define PORT_PRIORITY_RATE 0x0F
607 #define PORT_PRIORITY_RATE_SHIFT 4
609 #define KS884X_PORT_LINK_MD 0x10
611 #define PORT_CABLE_10M_SHORT 0x8000
612 #define PORT_CABLE_DIAG_RESULT 0x6000
613 #define PORT_CABLE_STAT_NORMAL 0x0000
614 #define PORT_CABLE_STAT_OPEN 0x2000
615 #define PORT_CABLE_STAT_SHORT 0x4000
616 #define PORT_CABLE_STAT_FAILED 0x6000
617 #define PORT_START_CABLE_DIAG 0x1000
618 #define PORT_FORCE_LINK 0x0800
619 #define PORT_POWER_SAVING_DISABLE 0x0400
620 #define PORT_PHY_REMOTE_LOOPBACK 0x0200
621 #define PORT_CABLE_FAULT_COUNTER 0x01FF
623 #define KS884X_PORT_CTRL_4_OFFSET 0x12
625 #define PORT_LED_OFF 0x8000
626 #define PORT_TX_DISABLE 0x4000
627 #define PORT_AUTO_NEG_RESTART 0x2000
628 #define PORT_REMOTE_FAULT_DISABLE 0x1000
629 #define PORT_POWER_DOWN 0x0800
630 #define PORT_AUTO_MDIX_DISABLE 0x0400
631 #define PORT_FORCE_MDIX 0x0200
632 #define PORT_LOOPBACK 0x0100
633 #define PORT_AUTO_NEG_ENABLE 0x0080
634 #define PORT_FORCE_100_MBIT 0x0040
635 #define PORT_FORCE_FULL_DUPLEX 0x0020
636 #define PORT_AUTO_NEG_SYM_PAUSE 0x0010
637 #define PORT_AUTO_NEG_100BTX_FD 0x0008
638 #define PORT_AUTO_NEG_100BTX 0x0004
639 #define PORT_AUTO_NEG_10BT_FD 0x0002
640 #define PORT_AUTO_NEG_10BT 0x0001
642 #define KS884X_PORT_STATUS_OFFSET 0x14
644 #define PORT_HP_MDIX 0x8000
645 #define PORT_REVERSED_POLARITY 0x2000
646 #define PORT_RX_FLOW_CTRL 0x0800
647 #define PORT_TX_FLOW_CTRL 0x1000
648 #define PORT_STATUS_SPEED_100MBIT 0x0400
649 #define PORT_STATUS_FULL_DUPLEX 0x0200
650 #define PORT_REMOTE_FAULT 0x0100
651 #define PORT_MDIX_STATUS 0x0080
652 #define PORT_AUTO_NEG_COMPLETE 0x0040
653 #define PORT_STATUS_LINK_GOOD 0x0020
654 #define PORT_REMOTE_SYM_PAUSE 0x0010
655 #define PORT_REMOTE_100BTX_FD 0x0008
656 #define PORT_REMOTE_100BTX 0x0004
657 #define PORT_REMOTE_10BT_FD 0x0002
658 #define PORT_REMOTE_10BT 0x0001
661 #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
662 #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
663 #define STATIC_MAC_TABLE_VALID 00-00080000-00000000
664 #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
665 #define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
666 #define STATIC_MAC_TABLE_FID 00-03C00000-00000000
669 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF
670 #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
671 #define STATIC_MAC_TABLE_VALID 0x00080000
672 #define STATIC_MAC_TABLE_OVERRIDE 0x00100000
673 #define STATIC_MAC_TABLE_USE_FID 0x00200000
674 #define STATIC_MAC_TABLE_FID 0x03C00000
676 #define STATIC_MAC_FWD_PORTS_SHIFT 16
677 #define STATIC_MAC_FID_SHIFT 22
680 #define VLAN_TABLE_VID 00-00000000-00000FFF
681 #define VLAN_TABLE_FID 00-00000000-0000F000
682 #define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
683 #define VLAN_TABLE_VALID 00-00000000-00080000
686 #define VLAN_TABLE_VID 0x00000FFF
687 #define VLAN_TABLE_FID 0x0000F000
688 #define VLAN_TABLE_MEMBERSHIP 0x00070000
689 #define VLAN_TABLE_VALID 0x00080000
691 #define VLAN_TABLE_FID_SHIFT 12
692 #define VLAN_TABLE_MEMBERSHIP_SHIFT 16
695 #define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
696 #define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
697 #define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
698 #define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
699 #define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
700 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
701 #define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
702 #define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
705 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
706 #define DYNAMIC_MAC_TABLE_FID 0x000F0000
707 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
708 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
709 #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
711 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
712 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
713 #define DYNAMIC_MAC_TABLE_RESERVED 0x78
714 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80
716 #define DYNAMIC_MAC_FID_SHIFT 16
717 #define DYNAMIC_MAC_SRC_PORT_SHIFT 20
718 #define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
719 #define DYNAMIC_MAC_ENTRIES_SHIFT 24
720 #define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
723 #define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
724 #define MIB_COUNTER_VALID 00-00000000-40000000
725 #define MIB_COUNTER_OVERFLOW 00-00000000-80000000
728 #define MIB_COUNTER_VALUE 0x3FFFFFFF
729 #define MIB_COUNTER_VALID 0x40000000
730 #define MIB_COUNTER_OVERFLOW 0x80000000
732 #define MIB_PACKET_DROPPED 0x0000FFFF
734 #define KS_MIB_PACKET_DROPPED_TX_0 0x100
735 #define KS_MIB_PACKET_DROPPED_TX_1 0x101
736 #define KS_MIB_PACKET_DROPPED_TX 0x102
737 #define KS_MIB_PACKET_DROPPED_RX_0 0x103
738 #define KS_MIB_PACKET_DROPPED_RX_1 0x104
739 #define KS_MIB_PACKET_DROPPED_RX 0x105
741 /* Change default LED mode. */
742 #define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
744 #define MAC_ADDR_LEN 6
745 #define MAC_ADDR_ORDER(i) (MAC_ADDR_LEN - 1 - (i))
747 #define MAX_ETHERNET_BODY_SIZE 1500
748 #define ETHERNET_HEADER_SIZE 14
750 #define MAX_ETHERNET_PACKET_SIZE \
751 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
753 #define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
754 #define MAX_RX_BUF_SIZE (1912 + 4)
756 #define ADDITIONAL_ENTRIES 16
757 #define MAX_MULTICAST_LIST 32
759 #define HW_MULTICAST_SIZE 8
761 #define HW_TO_DEV_PORT(port) (port - 1)
773 /* total transmit errors */
774 OID_COUNTER_XMIT_ERROR,
776 /* total receive errors */
777 OID_COUNTER_RCV_ERROR,
783 * Hardware descriptor definitions
786 #define DESC_ALIGNMENT 16
787 #define BUFFER_ALIGNMENT 8
789 #define NUM_OF_RX_DESC 64
790 #define NUM_OF_TX_DESC 64
792 #define KS_DESC_RX_FRAME_LEN 0x000007FF
793 #define KS_DESC_RX_FRAME_TYPE 0x00008000
794 #define KS_DESC_RX_ERROR_CRC 0x00010000
795 #define KS_DESC_RX_ERROR_RUNT 0x00020000
796 #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
797 #define KS_DESC_RX_ERROR_PHY 0x00080000
798 #define KS884X_DESC_RX_PORT_MASK 0x00300000
799 #define KS_DESC_RX_MULTICAST 0x01000000
800 #define KS_DESC_RX_ERROR 0x02000000
801 #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
802 #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
803 #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
804 #define KS_DESC_RX_LAST 0x20000000
805 #define KS_DESC_RX_FIRST 0x40000000
806 #define KS_DESC_RX_ERROR_COND \
807 (KS_DESC_RX_ERROR_CRC | \
808 KS_DESC_RX_ERROR_RUNT | \
809 KS_DESC_RX_ERROR_PHY | \
810 KS_DESC_RX_ERROR_TOO_LONG)
812 #define KS_DESC_HW_OWNED 0x80000000
814 #define KS_DESC_BUF_SIZE 0x000007FF
815 #define KS884X_DESC_TX_PORT_MASK 0x00300000
816 #define KS_DESC_END_OF_RING 0x02000000
817 #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
818 #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
819 #define KS_DESC_TX_CSUM_GEN_IP 0x10000000
820 #define KS_DESC_TX_LAST 0x20000000
821 #define KS_DESC_TX_FIRST 0x40000000
822 #define KS_DESC_TX_INTERRUPT 0x80000000
824 #define KS_DESC_PORT_SHIFT 20
826 #define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
828 #define KS_DESC_TX_MASK \
829 (KS_DESC_TX_INTERRUPT | \
832 KS_DESC_TX_CSUM_GEN_IP | \
833 KS_DESC_TX_CSUM_GEN_TCP | \
834 KS_DESC_TX_CSUM_GEN_UDP | \
837 struct ksz_desc_rx_stat {
838 #ifdef __BIG_ENDIAN_BITFIELD
875 struct ksz_desc_tx_stat {
876 #ifdef __BIG_ENDIAN_BITFIELD
885 struct ksz_desc_rx_buf {
886 #ifdef __BIG_ENDIAN_BITFIELD
899 struct ksz_desc_tx_buf {
900 #ifdef __BIG_ENDIAN_BITFIELD
928 struct ksz_desc_rx_stat rx;
929 struct ksz_desc_tx_stat tx;
934 struct ksz_desc_rx_buf rx;
935 struct ksz_desc_tx_buf tx;
940 * struct ksz_hw_desc - Hardware descriptor data structure
941 * @ctrl: Descriptor control value.
942 * @buf: Descriptor buffer value.
943 * @addr: Physical address of memory buffer.
944 * @next: Pointer to next hardware descriptor.
947 union desc_stat ctrl;
954 * struct ksz_sw_desc - Software descriptor data structure
955 * @ctrl: Descriptor control value.
956 * @buf: Descriptor buffer value.
957 * @buf_size: Current buffers size value in hardware descriptor.
960 union desc_stat ctrl;
966 * struct ksz_dma_buf - OS dependent DMA buffer data structure
967 * @skb: Associated socket buffer.
968 * @dma: Associated physical DMA address.
969 * len: Actual len used.
978 * struct ksz_desc - Descriptor structure
979 * @phw: Hardware descriptor pointer to uncached physical memory.
980 * @sw: Cached memory to hold hardware descriptor values for
982 * @dma_buf: Operating system dependent data structure to hold physical
983 * memory buffer allocation information.
986 struct ksz_hw_desc *phw;
987 struct ksz_sw_desc sw;
988 struct ksz_dma_buf dma_buf;
991 #define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
994 * struct ksz_desc_info - Descriptor information data structure
995 * @ring: First descriptor in the ring.
996 * @cur: Current descriptor being manipulated.
997 * @ring_virt: First hardware descriptor in the ring.
998 * @ring_phys: The physical address of the first descriptor of the ring.
999 * @size: Size of hardware descriptor.
1000 * @alloc: Number of descriptors allocated.
1001 * @avail: Number of descriptors available for use.
1002 * @last: Index for last descriptor released to hardware.
1003 * @next: Index for next descriptor available for use.
1004 * @mask: Mask for index wrapping.
1006 struct ksz_desc_info {
1007 struct ksz_desc *ring;
1008 struct ksz_desc *cur;
1009 struct ksz_hw_desc *ring_virt;
1020 * KSZ8842 switch definitions
1024 TABLE_STATIC_MAC = 0,
1030 #define LEARNED_MAC_TABLE_ENTRIES 1024
1031 #define STATIC_MAC_TABLE_ENTRIES 8
1034 * struct ksz_mac_table - Static MAC table data structure
1035 * @mac_addr: MAC address to filter.
1038 * @ports: Port membership.
1039 * @override: Override setting.
1040 * @use_fid: FID use setting.
1041 * @valid: Valid setting indicating the entry is being used.
1043 struct ksz_mac_table {
1044 u8 mac_addr[MAC_ADDR_LEN];
1053 #define VLAN_TABLE_ENTRIES 16
1056 * struct ksz_vlan_table - VLAN table data structure
1059 * @member: Port membership.
1061 struct ksz_vlan_table {
1067 #define DIFFSERV_ENTRIES 64
1068 #define PRIO_802_1P_ENTRIES 8
1069 #define PRIO_QUEUES 4
1071 #define SWITCH_PORT_NUM 2
1072 #define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
1073 #define HOST_MASK (1 << SWITCH_PORT_NUM)
1077 #define OTHER_PORT 1
1078 #define HOST_PORT SWITCH_PORT_NUM
1080 #define PORT_COUNTER_NUM 0x20
1081 #define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1083 #define MIB_COUNTER_RX_LO_PRIORITY 0x00
1084 #define MIB_COUNTER_RX_HI_PRIORITY 0x01
1085 #define MIB_COUNTER_RX_UNDERSIZE 0x02
1086 #define MIB_COUNTER_RX_FRAGMENT 0x03
1087 #define MIB_COUNTER_RX_OVERSIZE 0x04
1088 #define MIB_COUNTER_RX_JABBER 0x05
1089 #define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1090 #define MIB_COUNTER_RX_CRC_ERR 0x07
1091 #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1092 #define MIB_COUNTER_RX_CTRL_8808 0x09
1093 #define MIB_COUNTER_RX_PAUSE 0x0A
1094 #define MIB_COUNTER_RX_BROADCAST 0x0B
1095 #define MIB_COUNTER_RX_MULTICAST 0x0C
1096 #define MIB_COUNTER_RX_UNICAST 0x0D
1097 #define MIB_COUNTER_RX_OCTET_64 0x0E
1098 #define MIB_COUNTER_RX_OCTET_65_127 0x0F
1099 #define MIB_COUNTER_RX_OCTET_128_255 0x10
1100 #define MIB_COUNTER_RX_OCTET_256_511 0x11
1101 #define MIB_COUNTER_RX_OCTET_512_1023 0x12
1102 #define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1103 #define MIB_COUNTER_TX_LO_PRIORITY 0x14
1104 #define MIB_COUNTER_TX_HI_PRIORITY 0x15
1105 #define MIB_COUNTER_TX_LATE_COLLISION 0x16
1106 #define MIB_COUNTER_TX_PAUSE 0x17
1107 #define MIB_COUNTER_TX_BROADCAST 0x18
1108 #define MIB_COUNTER_TX_MULTICAST 0x19
1109 #define MIB_COUNTER_TX_UNICAST 0x1A
1110 #define MIB_COUNTER_TX_DEFERRED 0x1B
1111 #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1112 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1113 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1114 #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1116 #define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1117 #define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1120 * struct ksz_port_mib - Port MIB data structure
1121 * @cnt_ptr: Current pointer to MIB counter index.
1122 * @link_down: Indication the link has just gone down.
1123 * @state: Connection status of the port.
1124 * @mib_start: The starting counter index. Some ports do not start at 0.
1125 * @counter: 64-bit MIB counter value.
1126 * @dropped: Temporary buffer to remember last read packet dropped values.
1128 * MIB counters needs to be read periodically so that counters do not get
1129 * overflowed and give incorrect values. A right balance is needed to
1130 * satisfy this condition and not waste too much CPU time.
1132 * It is pointless to read MIB counters when the port is disconnected. The
1133 * @state provides the connection status so that MIB counters are read only
1134 * when the port is connected. The @link_down indicates the port is just
1135 * disconnected so that all MIB counters are read one last time to update the
1138 struct ksz_port_mib {
1144 u64 counter[TOTAL_PORT_COUNTER_NUM];
1149 * struct ksz_port_cfg - Port configuration data structure
1151 * @member: Port membership.
1152 * @port_prio: Port priority.
1153 * @rx_rate: Receive priority rate.
1154 * @tx_rate: Transmit priority rate.
1155 * @stp_state: Current Spanning Tree Protocol state.
1157 struct ksz_port_cfg {
1161 u32 rx_rate[PRIO_QUEUES];
1162 u32 tx_rate[PRIO_QUEUES];
1167 * struct ksz_switch - KSZ8842 switch data structure
1168 * @mac_table: MAC table entries information.
1169 * @vlan_table: VLAN table entries information.
1170 * @port_cfg: Port configuration information.
1171 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1172 * (bit7 ~ bit2) field.
1173 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1174 * Tag priority field.
1175 * @br_addr: Bridge address. Used for STP.
1176 * @other_addr: Other MAC address. Used for multiple network device mode.
1177 * @broad_per: Broadcast storm percentage.
1178 * @member: Current port membership. Used for STP.
1181 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1182 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1183 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1185 u8 diffserv[DIFFSERV_ENTRIES];
1186 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1188 u8 br_addr[MAC_ADDR_LEN];
1189 u8 other_addr[MAC_ADDR_LEN];
1195 #define TX_RATE_UNIT 10000
1198 * struct ksz_port_info - Port information data structure
1199 * @state: Connection status of the port.
1200 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1201 * @duplex: Duplex mode.
1202 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1203 * @partner: Auto-negotiation partner setting. Used to determine link.
1204 * @port_id: Port index to access actual hardware register.
1205 * @pdev: Pointer to OS dependent network device.
1207 struct ksz_port_info {
1217 #define MAX_TX_HELD_SIZE 52000
1219 /* Hardware features and bug fixes. */
1220 #define LINK_INT_WORKING (1 << 0)
1221 #define SMALL_PACKET_TX_BUG (1 << 1)
1222 #define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1223 #define IPV6_CSUM_GEN_HACK (1 << 3)
1224 #define RX_HUGE_FRAME (1 << 4)
1225 #define STP_SUPPORT (1 << 8)
1227 /* Software overrides. */
1228 #define PAUSE_FLOW_CTRL (1 << 0)
1229 #define FAST_AGING (1 << 1)
1232 * struct ksz_hw - KSZ884X hardware data structure
1233 * @io: Virtual address assigned.
1234 * @ksz_switch: Pointer to KSZ8842 switch.
1235 * @port_info: Port information.
1236 * @port_mib: Port MIB information.
1237 * @dev_count: Number of network devices this hardware supports.
1238 * @dst_ports: Destination ports in switch for transmission.
1239 * @id: Hardware ID. Used for display only.
1240 * @mib_cnt: Number of MIB counters this hardware has.
1241 * @mib_port_cnt: Number of ports with MIB counters.
1242 * @tx_cfg: Cached transmit control settings.
1243 * @rx_cfg: Cached receive control settings.
1244 * @intr_mask: Current interrupt mask.
1245 * @intr_set: Current interrup set.
1246 * @intr_blocked: Interrupt blocked.
1247 * @rx_desc_info: Receive descriptor information.
1248 * @tx_desc_info: Transmit descriptor information.
1249 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1250 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1251 * @tx_size: Transmit data size. Used for TX optimization.
1252 * The maximum is defined by MAX_TX_HELD_SIZE.
1253 * @perm_addr: Permanent MAC address.
1254 * @override_addr: Overrided MAC address.
1255 * @address: Additional MAC address entries.
1256 * @addr_list_size: Additional MAC address list size.
1257 * @mac_override: Indication of MAC address overrided.
1258 * @promiscuous: Counter to keep track of promiscuous mode set.
1259 * @all_multi: Counter to keep track of all multicast mode set.
1260 * @multi_list: Multicast address entries.
1261 * @multi_bits: Cached multicast hash table settings.
1262 * @multi_list_size: Multicast address list size.
1263 * @enabled: Indication of hardware enabled.
1264 * @rx_stop: Indication of receive process stop.
1265 * @features: Hardware features to enable.
1266 * @overrides: Hardware features to override.
1267 * @parent: Pointer to parent, network device private structure.
1272 struct ksz_switch *ksz_switch;
1273 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1274 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1287 struct ksz_desc_info rx_desc_info;
1288 struct ksz_desc_info tx_desc_info;
1294 u8 perm_addr[MAC_ADDR_LEN];
1295 u8 override_addr[MAC_ADDR_LEN];
1296 u8 address[ADDITIONAL_ENTRIES][MAC_ADDR_LEN];
1301 u8 multi_list[MAX_MULTICAST_LIST][MAC_ADDR_LEN];
1302 u8 multi_bits[HW_MULTICAST_SIZE];
1323 * struct ksz_port - Virtual port data structure
1324 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1325 * duplex, and 0 for auto, which normally results in full
1327 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1328 * 0 for auto, which normally results in 100 Mbit.
1329 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1331 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1332 * control, and PHY_FLOW_CTRL for flow control.
1333 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1335 * @first_port: Index of first port this port supports.
1336 * @mib_port_cnt: Number of ports with MIB counters.
1337 * @port_cnt: Number of ports this port supports.
1338 * @counter: Port statistics counter.
1339 * @hw: Pointer to hardware structure.
1340 * @linked: Pointer to port information linked to this port.
1351 u64 counter[OID_COUNTER_LAST];
1354 struct ksz_port_info *linked;
1358 * struct ksz_timer_info - Timer information data structure
1359 * @timer: Kernel timer.
1360 * @cnt: Running timer counter.
1361 * @max: Number of times to run timer; -1 for infinity.
1362 * @period: Timer period in jiffies.
1364 struct ksz_timer_info {
1365 struct timer_list timer;
1372 * struct ksz_shared_mem - OS dependent shared memory data structure
1373 * @dma_addr: Physical DMA address allocated.
1374 * @alloc_size: Allocation size.
1375 * @phys: Actual physical address used.
1376 * @alloc_virt: Virtual address allocated.
1377 * @virt: Actual virtual address used.
1379 struct ksz_shared_mem {
1380 dma_addr_t dma_addr;
1388 * struct ksz_counter_info - OS dependent counter information data structure
1389 * @counter: Wait queue to wakeup after counters are read.
1390 * @time: Next time in jiffies to read counter.
1391 * @read: Indication of counters read in full or not.
1393 struct ksz_counter_info {
1394 wait_queue_head_t counter;
1400 * struct dev_info - Network device information data structure
1401 * @dev: Pointer to network device.
1402 * @pdev: Pointer to PCI device.
1403 * @hw: Hardware structure.
1404 * @desc_pool: Physical memory used for descriptor pool.
1405 * @hwlock: Spinlock to prevent hardware from accessing.
1406 * @lock: Mutex lock to prevent device from accessing.
1407 * @dev_rcv: Receive process function used.
1408 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1409 * @skb_index: Buffer index for receiving fragments.
1410 * @skb_len: Buffer length for receiving fragments.
1411 * @mib_read: Workqueue to read MIB counters.
1412 * @mib_timer_info: Timer to read MIB counters.
1413 * @counter: Used for MIB reading.
1414 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1415 * the maximum is MAX_RX_BUF_SIZE.
1416 * @opened: Counter to keep track of device open.
1417 * @rx_tasklet: Receive processing tasklet.
1418 * @tx_tasklet: Transmit processing tasklet.
1419 * @wol_enable: Wake-on-LAN enable set by ethtool.
1420 * @wol_support: Wake-on-LAN support used by ethtool.
1421 * @pme_wait: Used for KSZ8841 power management.
1424 struct net_device *dev;
1425 struct pci_dev *pdev;
1428 struct ksz_shared_mem desc_pool;
1433 int (*dev_rcv)(struct dev_info *);
1435 struct sk_buff *last_skb;
1439 struct work_struct mib_read;
1440 struct ksz_timer_info mib_timer_info;
1441 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1446 struct tasklet_struct rx_tasklet;
1447 struct tasklet_struct tx_tasklet;
1451 unsigned long pme_wait;
1455 * struct dev_priv - Network device private data structure
1456 * @adapter: Adapter device information.
1457 * @port: Port information.
1458 * @monitor_time_info: Timer to monitor ports.
1459 * @stats: Network statistics.
1460 * @proc_sem: Semaphore for proc accessing.
1462 * @mii_if: MII interface information.
1463 * @advertising: Temporary variable to store advertised settings.
1464 * @msg_enable: The message flags controlling driver output.
1465 * @media_state: The connection status of the device.
1466 * @multicast: The all multicast state of the device.
1467 * @promiscuous: The promiscuous state of the device.
1470 struct dev_info *adapter;
1471 struct ksz_port port;
1472 struct ksz_timer_info monitor_timer_info;
1473 struct net_device_stats stats;
1475 struct semaphore proc_sem;
1478 struct mii_if_info mii_if;
1487 #define DRV_NAME "KSZ884X PCI"
1488 #define DEVICE_NAME "KSZ884x PCI"
1489 #define DRV_VERSION "1.0.0"
1490 #define DRV_RELDATE "Feb 8, 2010"
1492 static char version[] __devinitdata =
1493 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1495 static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1498 * Interrupt processing primary routines
1501 static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1503 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1506 static inline void hw_dis_intr(struct ksz_hw *hw)
1508 hw->intr_blocked = hw->intr_mask;
1509 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1510 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1513 static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1515 hw->intr_set = interrupt;
1516 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1519 static inline void hw_ena_intr(struct ksz_hw *hw)
1521 hw->intr_blocked = 0;
1522 hw_set_intr(hw, hw->intr_mask);
1525 static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1527 hw->intr_mask &= ~(bit);
1530 static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1534 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1535 hw->intr_set = read_intr & ~interrupt;
1536 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1537 hw_dis_intr_bit(hw, interrupt);
1541 * hw_turn_on_intr - turn on specified interrupts
1542 * @hw: The hardware instance.
1543 * @bit: The interrupt bits to be on.
1545 * This routine turns on the specified interrupts in the interrupt mask so that
1546 * those interrupts will be enabled.
1548 static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1550 hw->intr_mask |= bit;
1552 if (!hw->intr_blocked)
1553 hw_set_intr(hw, hw->intr_mask);
1556 static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1560 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1561 hw->intr_set = read_intr | interrupt;
1562 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1565 static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1567 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1568 *status = *status & hw->intr_set;
1571 static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1578 * hw_block_intr - block hardware interrupts
1580 * This function blocks all interrupts of the hardware and returns the current
1581 * interrupt enable mask so that interrupts can be restored later.
1583 * Return the current interrupt enable mask.
1585 static uint hw_block_intr(struct ksz_hw *hw)
1589 if (!hw->intr_blocked) {
1591 interrupt = hw->intr_blocked;
1597 * Hardware descriptor routines
1600 static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1602 status.rx.hw_owned = 0;
1603 desc->phw->ctrl.data = cpu_to_le32(status.data);
1606 static inline void release_desc(struct ksz_desc *desc)
1608 desc->sw.ctrl.tx.hw_owned = 1;
1609 if (desc->sw.buf_size != desc->sw.buf.data) {
1610 desc->sw.buf_size = desc->sw.buf.data;
1611 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1613 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1616 static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1618 *desc = &info->ring[info->last];
1620 info->last &= info->mask;
1622 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1625 static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1627 desc->phw->addr = cpu_to_le32(addr);
1630 static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1632 desc->sw.buf.rx.buf_size = len;
1635 static inline void get_tx_pkt(struct ksz_desc_info *info,
1636 struct ksz_desc **desc)
1638 *desc = &info->ring[info->next];
1640 info->next &= info->mask;
1642 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1645 static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1647 desc->phw->addr = cpu_to_le32(addr);
1650 static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1652 desc->sw.buf.tx.buf_size = len;
1655 /* Switch functions */
1657 #define TABLE_READ 0x10
1658 #define TABLE_SEL_SHIFT 2
1660 #define HW_DELAY(hw, reg) \
1663 dummy = readw(hw->io + reg); \
1667 * sw_r_table - read 4 bytes of data from switch table
1668 * @hw: The hardware instance.
1669 * @table: The table selector.
1670 * @addr: The address of the table entry.
1671 * @data: Buffer to store the read data.
1673 * This routine reads 4 bytes of data from the table of the switch.
1674 * Hardware interrupts are disabled to minimize corruption of read data.
1676 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1681 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1683 interrupt = hw_block_intr(hw);
1685 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1686 HW_DELAY(hw, KS884X_IACR_OFFSET);
1687 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1689 hw_restore_intr(hw, interrupt);
1693 * sw_w_table_64 - write 8 bytes of data to the switch table
1694 * @hw: The hardware instance.
1695 * @table: The table selector.
1696 * @addr: The address of the table entry.
1697 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1698 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1700 * This routine writes 8 bytes of data to the table of the switch.
1701 * Hardware interrupts are disabled to minimize corruption of written data.
1703 static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1709 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1711 interrupt = hw_block_intr(hw);
1713 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1714 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1716 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1717 HW_DELAY(hw, KS884X_IACR_OFFSET);
1719 hw_restore_intr(hw, interrupt);
1723 * sw_w_sta_mac_table - write to the static MAC table
1724 * @hw: The hardware instance.
1725 * @addr: The address of the table entry.
1726 * @mac_addr: The MAC address.
1727 * @ports: The port members.
1728 * @override: The flag to override the port receive/transmit settings.
1729 * @valid: The flag to indicate entry is valid.
1730 * @use_fid: The flag to indicate the FID is valid.
1731 * @fid: The FID value.
1733 * This routine writes an entry of the static MAC table of the switch. It
1734 * calls sw_w_table_64() to write the data.
1736 static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1737 u8 ports, int override, int valid, int use_fid, u8 fid)
1742 data_lo = ((u32) mac_addr[2] << 24) |
1743 ((u32) mac_addr[3] << 16) |
1744 ((u32) mac_addr[4] << 8) | mac_addr[5];
1745 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1746 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1749 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1751 data_hi |= STATIC_MAC_TABLE_USE_FID;
1752 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1755 data_hi |= STATIC_MAC_TABLE_VALID;
1757 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1761 * sw_r_vlan_table - read from the VLAN table
1762 * @hw: The hardware instance.
1763 * @addr: The address of the table entry.
1764 * @vid: Buffer to store the VID.
1765 * @fid: Buffer to store the VID.
1766 * @member: Buffer to store the port membership.
1768 * This function reads an entry of the VLAN table of the switch. It calls
1769 * sw_r_table() to get the data.
1771 * Return 0 if the entry is valid; otherwise -1.
1773 static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1778 sw_r_table(hw, TABLE_VLAN, addr, &data);
1779 if (data & VLAN_TABLE_VALID) {
1780 *vid = (u16)(data & VLAN_TABLE_VID);
1781 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1782 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1783 VLAN_TABLE_MEMBERSHIP_SHIFT);
1790 * port_r_mib_cnt - read MIB counter
1791 * @hw: The hardware instance.
1792 * @port: The port index.
1793 * @addr: The address of the counter.
1794 * @cnt: Buffer to store the counter.
1796 * This routine reads a MIB counter of the port.
1797 * Hardware interrupts are disabled to minimize corruption of read data.
1799 static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1806 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1808 interrupt = hw_block_intr(hw);
1810 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1811 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1812 HW_DELAY(hw, KS884X_IACR_OFFSET);
1814 for (timeout = 100; timeout > 0; timeout--) {
1815 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1817 if (data & MIB_COUNTER_VALID) {
1818 if (data & MIB_COUNTER_OVERFLOW)
1819 *cnt += MIB_COUNTER_VALUE + 1;
1820 *cnt += data & MIB_COUNTER_VALUE;
1825 hw_restore_intr(hw, interrupt);
1829 * port_r_mib_pkt - read dropped packet counts
1830 * @hw: The hardware instance.
1831 * @port: The port index.
1832 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1834 * This routine reads the dropped packet counts of the port.
1835 * Hardware interrupts are disabled to minimize corruption of read data.
1837 static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1845 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1847 interrupt = hw_block_intr(hw);
1849 ctrl_addr = (u16) index;
1850 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1852 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1853 HW_DELAY(hw, KS884X_IACR_OFFSET);
1854 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1856 hw_restore_intr(hw, interrupt);
1858 data &= MIB_PACKET_DROPPED;
1863 data += MIB_PACKET_DROPPED + 1;
1869 index -= KS_MIB_PACKET_DROPPED_TX -
1870 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1871 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1875 * port_r_cnt - read MIB counters periodically
1876 * @hw: The hardware instance.
1877 * @port: The port index.
1879 * This routine is used to read the counters of the port periodically to avoid
1880 * counter overflow. The hardware should be acquired first before calling this
1883 * Return non-zero when not all counters not read.
1885 static int port_r_cnt(struct ksz_hw *hw, int port)
1887 struct ksz_port_mib *mib = &hw->port_mib[port];
1889 if (mib->mib_start < PORT_COUNTER_NUM)
1890 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1891 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1892 &mib->counter[mib->cnt_ptr]);
1895 if (hw->mib_cnt > PORT_COUNTER_NUM)
1896 port_r_mib_pkt(hw, port, mib->dropped,
1897 &mib->counter[PORT_COUNTER_NUM]);
1903 * port_init_cnt - initialize MIB counter values
1904 * @hw: The hardware instance.
1905 * @port: The port index.
1907 * This routine is used to initialize all counters to zero if the hardware
1908 * cannot do it after reset.
1910 static void port_init_cnt(struct ksz_hw *hw, int port)
1912 struct ksz_port_mib *mib = &hw->port_mib[port];
1915 if (mib->mib_start < PORT_COUNTER_NUM)
1917 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1918 &mib->counter[mib->cnt_ptr]);
1920 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1921 if (hw->mib_cnt > PORT_COUNTER_NUM)
1922 port_r_mib_pkt(hw, port, mib->dropped,
1923 &mib->counter[PORT_COUNTER_NUM]);
1924 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1933 * port_chk - check port register bits
1934 * @hw: The hardware instance.
1935 * @port: The port index.
1936 * @offset: The offset of the port register.
1937 * @bits: The data bits to check.
1939 * This function checks whether the specified bits of the port register are set
1942 * Return 0 if the bits are not set.
1944 static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1949 PORT_CTRL_ADDR(port, addr);
1951 data = readw(hw->io + addr);
1952 return (data & bits) == bits;
1956 * port_cfg - set port register bits
1957 * @hw: The hardware instance.
1958 * @port: The port index.
1959 * @offset: The offset of the port register.
1960 * @bits: The data bits to set.
1961 * @set: The flag indicating whether the bits are to be set or not.
1963 * This routine sets or resets the specified bits of the port register.
1965 static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1971 PORT_CTRL_ADDR(port, addr);
1973 data = readw(hw->io + addr);
1978 writew(data, hw->io + addr);
1982 * port_chk_shift - check port bit
1983 * @hw: The hardware instance.
1984 * @port: The port index.
1985 * @offset: The offset of the register.
1986 * @shift: Number of bits to shift.
1988 * This function checks whether the specified port is set in the register or
1991 * Return 0 if the port is not set.
1993 static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1996 u16 bit = 1 << port;
1998 data = readw(hw->io + addr);
2000 return (data & bit) == bit;
2004 * port_cfg_shift - set port bit
2005 * @hw: The hardware instance.
2006 * @port: The port index.
2007 * @offset: The offset of the register.
2008 * @shift: Number of bits to shift.
2009 * @set: The flag indicating whether the port is to be set or not.
2011 * This routine sets or resets the specified port in the register.
2013 static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2017 u16 bits = 1 << port;
2019 data = readw(hw->io + addr);
2025 writew(data, hw->io + addr);
2029 * port_r8 - read byte from port register
2030 * @hw: The hardware instance.
2031 * @port: The port index.
2032 * @offset: The offset of the port register.
2033 * @data: Buffer to store the data.
2035 * This routine reads a byte from the port register.
2037 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2041 PORT_CTRL_ADDR(port, addr);
2043 *data = readb(hw->io + addr);
2047 * port_r16 - read word from port register.
2048 * @hw: The hardware instance.
2049 * @port: The port index.
2050 * @offset: The offset of the port register.
2051 * @data: Buffer to store the data.
2053 * This routine reads a word from the port register.
2055 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2059 PORT_CTRL_ADDR(port, addr);
2061 *data = readw(hw->io + addr);
2065 * port_w16 - write word to port register.
2066 * @hw: The hardware instance.
2067 * @port: The port index.
2068 * @offset: The offset of the port register.
2069 * @data: Data to write.
2071 * This routine writes a word to the port register.
2073 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2077 PORT_CTRL_ADDR(port, addr);
2079 writew(data, hw->io + addr);
2083 * sw_chk - check switch register bits
2084 * @hw: The hardware instance.
2085 * @addr: The address of the switch register.
2086 * @bits: The data bits to check.
2088 * This function checks whether the specified bits of the switch register are
2091 * Return 0 if the bits are not set.
2093 static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2097 data = readw(hw->io + addr);
2098 return (data & bits) == bits;
2102 * sw_cfg - set switch register bits
2103 * @hw: The hardware instance.
2104 * @addr: The address of the switch register.
2105 * @bits: The data bits to set.
2106 * @set: The flag indicating whether the bits are to be set or not.
2108 * This function sets or resets the specified bits of the switch register.
2110 static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2114 data = readw(hw->io + addr);
2119 writew(data, hw->io + addr);
2124 static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2127 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2130 static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2132 return port_chk(hw, p,
2133 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2136 /* Driver set switch broadcast storm protection at 10% rate. */
2137 #define BROADCAST_STORM_PROTECTION_RATE 10
2139 /* 148,800 frames * 67 ms / 100 */
2140 #define BROADCAST_STORM_VALUE 9969
2143 * sw_cfg_broad_storm - configure broadcast storm threshold
2144 * @hw: The hardware instance.
2145 * @percent: Broadcast storm threshold in percent of transmit rate.
2147 * This routine configures the broadcast storm threshold of the switch.
2149 static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2152 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2154 if (value > BROADCAST_STORM_RATE)
2155 value = BROADCAST_STORM_RATE;
2157 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2158 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2159 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2160 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2164 * sw_get_board_storm - get broadcast storm threshold
2165 * @hw: The hardware instance.
2166 * @percent: Buffer to store the broadcast storm threshold percentage.
2168 * This routine retrieves the broadcast storm threshold of the switch.
2170 static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2175 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2176 num = (data & BROADCAST_STORM_RATE_HI);
2178 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2179 num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE;
2180 *percent = (u8) num;
2184 * sw_dis_broad_storm - disable broadstorm
2185 * @hw: The hardware instance.
2186 * @port: The port index.
2188 * This routine disables the broadcast storm limit function of the switch.
2190 static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2192 port_cfg_broad_storm(hw, port, 0);
2196 * sw_ena_broad_storm - enable broadcast storm
2197 * @hw: The hardware instance.
2198 * @port: The port index.
2200 * This routine enables the broadcast storm limit function of the switch.
2202 static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2204 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2205 port_cfg_broad_storm(hw, port, 1);
2209 * sw_init_broad_storm - initialize broadcast storm
2210 * @hw: The hardware instance.
2212 * This routine initializes the broadcast storm limit function of the switch.
2214 static void sw_init_broad_storm(struct ksz_hw *hw)
2218 hw->ksz_switch->broad_per = 1;
2219 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2220 for (port = 0; port < TOTAL_PORT_NUM; port++)
2221 sw_dis_broad_storm(hw, port);
2222 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2226 * hw_cfg_broad_storm - configure broadcast storm
2227 * @hw: The hardware instance.
2228 * @percent: Broadcast storm threshold in percent of transmit rate.
2230 * This routine configures the broadcast storm threshold of the switch.
2231 * It is called by user functions. The hardware should be acquired first.
2233 static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2238 sw_cfg_broad_storm(hw, percent);
2239 sw_get_broad_storm(hw, &percent);
2240 hw->ksz_switch->broad_per = percent;
2244 * sw_dis_prio_rate - disable switch priority rate
2245 * @hw: The hardware instance.
2246 * @port: The port index.
2248 * This routine disables the priority rate function of the switch.
2250 static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2254 PORT_CTRL_ADDR(port, addr);
2255 addr += KS8842_PORT_IN_RATE_OFFSET;
2256 writel(0, hw->io + addr);
2260 * sw_init_prio_rate - initialize switch prioirty rate
2261 * @hw: The hardware instance.
2263 * This routine initializes the priority rate function of the switch.
2265 static void sw_init_prio_rate(struct ksz_hw *hw)
2269 struct ksz_switch *sw = hw->ksz_switch;
2271 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2272 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2273 sw->port_cfg[port].rx_rate[prio] =
2274 sw->port_cfg[port].tx_rate[prio] = 0;
2276 sw_dis_prio_rate(hw, port);
2282 static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2285 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2288 static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2291 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2294 static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2296 return port_chk(hw, p,
2297 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2300 static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2302 return port_chk(hw, p,
2303 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2308 static inline void port_cfg_dis_learn(struct ksz_hw *hw, int p, int set)
2311 KS8842_PORT_CTRL_2_OFFSET, PORT_LEARN_DISABLE, set);
2314 static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2317 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2320 static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2323 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2326 static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2328 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2331 static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2333 if (!(hw->overrides & FAST_AGING)) {
2334 sw_cfg_fast_aging(hw, 1);
2336 sw_cfg_fast_aging(hw, 0);
2342 static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2345 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2348 static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2351 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2354 static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2356 return port_chk(hw, p,
2357 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2360 static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2362 return port_chk(hw, p,
2363 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2366 static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2369 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2372 static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2375 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2378 static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2380 return port_chk(hw, p,
2381 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2384 static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2386 return port_chk(hw, p,
2387 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2392 static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2395 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2398 static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2401 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2404 static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2407 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2410 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2412 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2415 static void sw_init_mirror(struct ksz_hw *hw)
2419 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2420 port_cfg_mirror_sniffer(hw, port, 0);
2421 port_cfg_mirror_rx(hw, port, 0);
2422 port_cfg_mirror_tx(hw, port, 0);
2424 sw_cfg_mirror_rx_tx(hw, 0);
2427 static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2429 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2430 SWITCH_UNK_DEF_PORT_ENABLE, set);
2433 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2435 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2436 SWITCH_UNK_DEF_PORT_ENABLE);
2439 static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2441 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2444 static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2446 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2451 static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2454 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2457 static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2460 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2463 static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2466 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2469 static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2472 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2475 static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2477 return port_chk(hw, p,
2478 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2481 static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2483 return port_chk(hw, p,
2484 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2487 static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2489 return port_chk(hw, p,
2490 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2493 static inline int port_chk_prio(struct ksz_hw *hw, int p)
2495 return port_chk(hw, p,
2496 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2500 * sw_dis_diffserv - disable switch DiffServ priority
2501 * @hw: The hardware instance.
2502 * @port: The port index.
2504 * This routine disables the DiffServ priority function of the switch.
2506 static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2508 port_cfg_diffserv(hw, port, 0);
2512 * sw_dis_802_1p - disable switch 802.1p priority
2513 * @hw: The hardware instance.
2514 * @port: The port index.
2516 * This routine disables the 802.1p priority function of the switch.
2518 static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2520 port_cfg_802_1p(hw, port, 0);
2524 * sw_cfg_replace_null_vid -
2525 * @hw: The hardware instance.
2526 * @set: The flag to disable or enable.
2529 static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2531 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2535 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2536 * @hw: The hardware instance.
2537 * @port: The port index.
2538 * @set: The flag to disable or enable.
2540 * This routine enables the 802.1p priority re-mapping function of the switch.
2541 * That allows 802.1p priority field to be replaced with the port's default
2542 * tag's priority value if the ingress packet's 802.1p priority has a higher
2543 * priority than port's default tag's priority.
2545 static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2547 port_cfg_replace_vid(hw, port, set);
2551 * sw_cfg_port_based - configure switch port based priority
2552 * @hw: The hardware instance.
2553 * @port: The port index.
2554 * @prio: The priority to set.
2556 * This routine configures the port based priority of the switch.
2558 static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2562 if (prio > PORT_BASED_PRIORITY_BASE)
2563 prio = PORT_BASED_PRIORITY_BASE;
2565 hw->ksz_switch->port_cfg[port].port_prio = prio;
2567 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2568 data &= ~PORT_BASED_PRIORITY_MASK;
2569 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2570 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2574 * sw_dis_multi_queue - disable transmit multiple queues
2575 * @hw: The hardware instance.
2576 * @port: The port index.
2578 * This routine disables the transmit multiple queues selection of the switch
2579 * port. Only single transmit queue on the port.
2581 static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2583 port_cfg_prio(hw, port, 0);
2587 * sw_init_prio - initialize switch priority
2588 * @hw: The hardware instance.
2590 * This routine initializes the switch QoS priority functions.
2592 static void sw_init_prio(struct ksz_hw *hw)
2596 struct ksz_switch *sw = hw->ksz_switch;
2599 * Init all the 802.1p tag priority value to be assigned to different
2602 sw->p_802_1p[0] = 0;
2603 sw->p_802_1p[1] = 0;
2604 sw->p_802_1p[2] = 1;
2605 sw->p_802_1p[3] = 1;
2606 sw->p_802_1p[4] = 2;
2607 sw->p_802_1p[5] = 2;
2608 sw->p_802_1p[6] = 3;
2609 sw->p_802_1p[7] = 3;
2612 * Init all the DiffServ priority value to be assigned to priority
2615 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2616 sw->diffserv[tos] = 0;
2618 /* All QoS functions disabled. */
2619 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2620 sw_dis_multi_queue(hw, port);
2621 sw_dis_diffserv(hw, port);
2622 sw_dis_802_1p(hw, port);
2623 sw_cfg_replace_vid(hw, port, 0);
2625 sw->port_cfg[port].port_prio = 0;
2626 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2628 sw_cfg_replace_null_vid(hw, 0);
2632 * port_get_def_vid - get port default VID.
2633 * @hw: The hardware instance.
2634 * @port: The port index.
2635 * @vid: Buffer to store the VID.
2637 * This routine retrieves the default VID of the port.
2639 static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2643 PORT_CTRL_ADDR(port, addr);
2644 addr += KS8842_PORT_CTRL_VID_OFFSET;
2645 *vid = readw(hw->io + addr);
2649 * sw_init_vlan - initialize switch VLAN
2650 * @hw: The hardware instance.
2652 * This routine initializes the VLAN function of the switch.
2654 static void sw_init_vlan(struct ksz_hw *hw)
2658 struct ksz_switch *sw = hw->ksz_switch;
2660 /* Read 16 VLAN entries from device's VLAN table. */
2661 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2662 sw_r_vlan_table(hw, entry,
2663 &sw->vlan_table[entry].vid,
2664 &sw->vlan_table[entry].fid,
2665 &sw->vlan_table[entry].member);
2668 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2669 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2670 sw->port_cfg[port].member = PORT_MASK;
2675 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2676 * @hw: The hardware instance.
2677 * @port: The port index.
2678 * @member: The port-based VLAN membership.
2680 * This routine configures the port-based VLAN membership of the port.
2682 static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2687 PORT_CTRL_ADDR(port, addr);
2688 addr += KS8842_PORT_CTRL_2_OFFSET;
2690 data = readb(hw->io + addr);
2691 data &= ~PORT_VLAN_MEMBERSHIP;
2692 data |= (member & PORT_MASK);
2693 writeb(data, hw->io + addr);
2695 hw->ksz_switch->port_cfg[port].member = member;
2699 * sw_get_addr - get the switch MAC address.
2700 * @hw: The hardware instance.
2701 * @mac_addr: Buffer to store the MAC address.
2703 * This function retrieves the MAC address of the switch.
2705 static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2709 for (i = 0; i < 6; i += 2) {
2710 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2711 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2716 * sw_set_addr - configure switch MAC address
2717 * @hw: The hardware instance.
2718 * @mac_addr: The MAC address.
2720 * This function configures the MAC address of the switch.
2722 static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2726 for (i = 0; i < 6; i += 2) {
2727 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2728 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2733 * sw_set_global_ctrl - set switch global control
2734 * @hw: The hardware instance.
2736 * This routine sets the global control of the switch function.
2738 static void sw_set_global_ctrl(struct ksz_hw *hw)
2742 /* Enable switch MII flow control. */
2743 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2744 data |= SWITCH_FLOW_CTRL;
2745 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2747 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2749 /* Enable aggressive back off algorithm in half duplex mode. */
2750 data |= SWITCH_AGGR_BACKOFF;
2752 /* Enable automatic fast aging when link changed detected. */
2753 data |= SWITCH_AGING_ENABLE;
2754 data |= SWITCH_LINK_AUTO_AGING;
2756 if (hw->overrides & FAST_AGING)
2757 data |= SWITCH_FAST_AGING;
2759 data &= ~SWITCH_FAST_AGING;
2760 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2762 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2764 /* Enable no excessive collision drop. */
2765 data |= NO_EXC_COLLISION_DROP;
2766 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2770 STP_STATE_DISABLED = 0,
2771 STP_STATE_LISTENING,
2773 STP_STATE_FORWARDING,
2779 * port_set_stp_state - configure port spanning tree state
2780 * @hw: The hardware instance.
2781 * @port: The port index.
2782 * @state: The spanning tree state.
2784 * This routine configures the spanning tree state of the port.
2786 static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2790 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2792 case STP_STATE_DISABLED:
2793 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2794 data |= PORT_LEARN_DISABLE;
2796 case STP_STATE_LISTENING:
2798 * No need to turn on transmit because of port direct mode.
2799 * Turning on receive is required if static MAC table is not setup.
2801 data &= ~PORT_TX_ENABLE;
2802 data |= PORT_RX_ENABLE;
2803 data |= PORT_LEARN_DISABLE;
2805 case STP_STATE_LEARNING:
2806 data &= ~PORT_TX_ENABLE;
2807 data |= PORT_RX_ENABLE;
2808 data &= ~PORT_LEARN_DISABLE;
2810 case STP_STATE_FORWARDING:
2811 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2812 data &= ~PORT_LEARN_DISABLE;
2814 case STP_STATE_BLOCKED:
2816 * Need to setup static MAC table with override to keep receiving BPDU
2817 * messages. See sw_init_stp routine.
2819 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2820 data |= PORT_LEARN_DISABLE;
2822 case STP_STATE_SIMPLE:
2823 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2824 data |= PORT_LEARN_DISABLE;
2827 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2828 hw->ksz_switch->port_cfg[port].stp_state = state;
2832 #define BROADCAST_ENTRY 1
2833 #define BRIDGE_ADDR_ENTRY 2
2834 #define IPV6_ADDR_ENTRY 3
2837 * sw_clr_sta_mac_table - clear static MAC table
2838 * @hw: The hardware instance.
2840 * This routine clears the static MAC table.
2842 static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2844 struct ksz_mac_table *entry;
2847 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2848 entry = &hw->ksz_switch->mac_table[i];
2849 sw_w_sta_mac_table(hw, i,
2850 entry->mac_addr, entry->ports,
2852 entry->use_fid, entry->fid);
2857 * sw_init_stp - initialize switch spanning tree support
2858 * @hw: The hardware instance.
2860 * This routine initializes the spanning tree support of the switch.
2862 static void sw_init_stp(struct ksz_hw *hw)
2864 struct ksz_mac_table *entry;
2866 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2867 entry->mac_addr[0] = 0x01;
2868 entry->mac_addr[1] = 0x80;
2869 entry->mac_addr[2] = 0xC2;
2870 entry->mac_addr[3] = 0x00;
2871 entry->mac_addr[4] = 0x00;
2872 entry->mac_addr[5] = 0x00;
2873 entry->ports = HOST_MASK;
2874 entry->override = 1;
2876 sw_w_sta_mac_table(hw, STP_ENTRY,
2877 entry->mac_addr, entry->ports,
2878 entry->override, entry->valid,
2879 entry->use_fid, entry->fid);
2883 * sw_block_addr - block certain packets from the host port
2884 * @hw: The hardware instance.
2886 * This routine blocks certain packets from reaching to the host port.
2888 static void sw_block_addr(struct ksz_hw *hw)
2890 struct ksz_mac_table *entry;
2893 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2894 entry = &hw->ksz_switch->mac_table[i];
2896 sw_w_sta_mac_table(hw, i,
2897 entry->mac_addr, entry->ports,
2898 entry->override, entry->valid,
2899 entry->use_fid, entry->fid);
2903 #define PHY_LINK_SUPPORT \
2904 (PHY_AUTO_NEG_ASYM_PAUSE | \
2905 PHY_AUTO_NEG_SYM_PAUSE | \
2906 PHY_AUTO_NEG_100BT4 | \
2907 PHY_AUTO_NEG_100BTX_FD | \
2908 PHY_AUTO_NEG_100BTX | \
2909 PHY_AUTO_NEG_10BT_FD | \
2912 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2914 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2917 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2919 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2922 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2924 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2927 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2929 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2932 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2934 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2937 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2939 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2942 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2944 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2947 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2949 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2952 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2954 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2957 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2959 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2962 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2964 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2967 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2969 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2973 * hw_r_phy - read data from PHY register
2974 * @hw: The hardware instance.
2975 * @port: Port to read.
2976 * @reg: PHY register to read.
2977 * @val: Buffer to store the read data.
2979 * This routine reads data from the PHY register.
2981 static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2985 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2986 *val = readw(hw->io + phy);
2990 * port_w_phy - write data to PHY register
2991 * @hw: The hardware instance.
2992 * @port: Port to write.
2993 * @reg: PHY register to write.
2994 * @val: Word data to write.
2996 * This routine writes data to the PHY register.
2998 static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
3002 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
3003 writew(val, hw->io + phy);
3007 * EEPROM access functions
3010 #define AT93C_CODE 0
3011 #define AT93C_WR_OFF 0x00
3012 #define AT93C_WR_ALL 0x10
3013 #define AT93C_ER_ALL 0x20
3014 #define AT93C_WR_ON 0x30
3016 #define AT93C_WRITE 1
3017 #define AT93C_READ 2
3018 #define AT93C_ERASE 3
3020 #define EEPROM_DELAY 4
3022 static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3026 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3028 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3031 static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3035 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3037 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3040 static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3044 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3045 return (u8)(data & gpio);
3048 static void eeprom_clk(struct ksz_hw *hw)
3050 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3051 udelay(EEPROM_DELAY);
3052 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3053 udelay(EEPROM_DELAY);
3056 static u16 spi_r(struct ksz_hw *hw)
3061 for (i = 15; i >= 0; i--) {
3062 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3063 udelay(EEPROM_DELAY);
3065 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3067 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3068 udelay(EEPROM_DELAY);
3073 static void spi_w(struct ksz_hw *hw, u16 data)
3077 for (i = 15; i >= 0; i--) {
3078 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3079 drop_gpio(hw, EEPROM_DATA_OUT);
3084 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3088 /* Initial start bit */
3089 raise_gpio(hw, EEPROM_DATA_OUT);
3092 /* AT93C operation */
3093 for (i = 1; i >= 0; i--) {
3094 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3095 drop_gpio(hw, EEPROM_DATA_OUT);
3099 /* Address location */
3100 for (i = 5; i >= 0; i--) {
3101 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3102 drop_gpio(hw, EEPROM_DATA_OUT);
3107 #define EEPROM_DATA_RESERVED 0
3108 #define EEPROM_DATA_MAC_ADDR_0 1
3109 #define EEPROM_DATA_MAC_ADDR_1 2
3110 #define EEPROM_DATA_MAC_ADDR_2 3
3111 #define EEPROM_DATA_SUBSYS_ID 4
3112 #define EEPROM_DATA_SUBSYS_VEN_ID 5
3113 #define EEPROM_DATA_PM_CAP 6
3115 /* User defined EEPROM data */
3116 #define EEPROM_DATA_OTHER_MAC_ADDR 9
3119 * eeprom_read - read from AT93C46 EEPROM
3120 * @hw: The hardware instance.
3121 * @reg: The register offset.
3123 * This function reads a word from the AT93C46 EEPROM.
3125 * Return the data value.
3127 static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3131 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3133 spi_reg(hw, AT93C_READ, reg);
3136 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3142 * eeprom_write - write to AT93C46 EEPROM
3143 * @hw: The hardware instance.
3144 * @reg: The register offset.
3145 * @data: The data value.
3147 * This procedure writes a word to the AT93C46 EEPROM.
3149 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3153 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3156 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3157 drop_gpio(hw, EEPROM_CHIP_SELECT);
3160 /* Erase the register. */
3161 raise_gpio(hw, EEPROM_CHIP_SELECT);
3162 spi_reg(hw, AT93C_ERASE, reg);
3163 drop_gpio(hw, EEPROM_CHIP_SELECT);
3166 /* Check operation complete. */
3167 raise_gpio(hw, EEPROM_CHIP_SELECT);
3172 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3173 drop_gpio(hw, EEPROM_CHIP_SELECT);
3176 /* Write the register. */
3177 raise_gpio(hw, EEPROM_CHIP_SELECT);
3178 spi_reg(hw, AT93C_WRITE, reg);
3180 drop_gpio(hw, EEPROM_CHIP_SELECT);
3183 /* Check operation complete. */
3184 raise_gpio(hw, EEPROM_CHIP_SELECT);
3189 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3190 drop_gpio(hw, EEPROM_CHIP_SELECT);
3193 /* Disable write. */
3194 raise_gpio(hw, EEPROM_CHIP_SELECT);
3195 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3197 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3201 * Link detection routines
3204 static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3206 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3207 switch (port->flow_ctrl) {
3209 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3211 /* Not supported. */
3220 static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3225 rx_cfg = hw->rx_cfg;
3226 tx_cfg = hw->tx_cfg;
3228 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3230 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3232 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3234 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3236 if (rx_cfg != hw->rx_cfg)
3237 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3238 if (tx_cfg != hw->tx_cfg)
3239 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3243 static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3244 u16 local, u16 remote)
3249 if (hw->overrides & PAUSE_FLOW_CTRL)
3253 if (port->force_link)
3255 if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
3256 if (local & PHY_AUTO_NEG_SYM_PAUSE) {
3258 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
3259 (local & PHY_AUTO_NEG_PAUSE) ==
3260 PHY_AUTO_NEG_ASYM_PAUSE) {
3263 } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
3264 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
3267 if (!hw->ksz_switch)
3268 set_flow_ctrl(hw, rx, tx);
3271 static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3272 struct ksz_port_info *info, u16 link_status)
3274 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3275 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3276 u32 cfg = hw->tx_cfg;
3278 /* Disable flow control in the half duplex mode. */
3279 if (1 == info->duplex)
3280 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3281 if (hw->enabled && cfg != hw->tx_cfg)
3282 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3287 * port_get_link_speed - get current link status
3288 * @port: The port instance.
3290 * This routine reads PHY registers to determine the current link status of the
3293 static void port_get_link_speed(struct ksz_port *port)
3296 struct ksz_port_info *info;
3297 struct ksz_port_info *linked = NULL;
3298 struct ksz_hw *hw = port->hw;
3307 interrupt = hw_block_intr(hw);
3309 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3310 info = &hw->port_info[p];
3311 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3312 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3315 * Link status is changing all the time even when there is no
3318 remote = status & (PORT_AUTO_NEG_COMPLETE |
3319 PORT_STATUS_LINK_GOOD);
3322 /* No change to status. */
3323 if (local == info->advertised && remote == info->partner)
3326 info->advertised = local;
3327 info->partner = remote;
3328 if (status & PORT_STATUS_LINK_GOOD) {
3330 /* Remember the first linked port. */
3334 info->tx_rate = 10 * TX_RATE_UNIT;
3335 if (status & PORT_STATUS_SPEED_100MBIT)
3336 info->tx_rate = 100 * TX_RATE_UNIT;
3339 if (status & PORT_STATUS_FULL_DUPLEX)
3342 if (media_connected != info->state) {
3343 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3345 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3347 determine_flow_ctrl(hw, port, data, status);
3348 if (hw->ksz_switch) {
3349 port_cfg_back_pressure(hw, p,
3350 (1 == info->duplex));
3353 port_cfg_change(hw, port, info, status);
3355 info->state = media_connected;
3357 if (media_disconnected != info->state) {
3360 /* Indicate the link just goes down. */
3361 hw->port_mib[p].link_down = 1;
3363 info->state = media_disconnected;
3365 hw->port_mib[p].state = (u8) info->state;
3368 if (linked && media_disconnected == port->linked->state)
3369 port->linked = linked;
3371 hw_restore_intr(hw, interrupt);
3374 #define PHY_RESET_TIMEOUT 10
3377 * port_set_link_speed - set port speed
3378 * @port: The port instance.
3380 * This routine sets the link speed of the switch ports.
3382 static void port_set_link_speed(struct ksz_port *port)
3384 struct ksz_port_info *info;
3385 struct ksz_hw *hw = port->hw;
3392 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3393 info = &hw->port_info[p];
3395 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3396 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3399 if (status & PORT_STATUS_LINK_GOOD)
3402 data |= PORT_AUTO_NEG_ENABLE;
3403 data = advertised_flow_ctrl(port, data);
3405 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3406 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3408 /* Check if manual configuration is specified by the user. */
3409 if (port->speed || port->duplex) {
3410 if (10 == port->speed)
3411 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3412 PORT_AUTO_NEG_100BTX);
3413 else if (100 == port->speed)
3414 data &= ~(PORT_AUTO_NEG_10BT_FD |
3415 PORT_AUTO_NEG_10BT);
3416 if (1 == port->duplex)
3417 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3418 PORT_AUTO_NEG_10BT_FD);
3419 else if (2 == port->duplex)
3420 data &= ~(PORT_AUTO_NEG_100BTX |
3421 PORT_AUTO_NEG_10BT);
3424 data |= PORT_AUTO_NEG_RESTART;
3425 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3431 * port_force_link_speed - force port speed
3432 * @port: The port instance.
3434 * This routine forces the link speed of the switch ports.
3436 static void port_force_link_speed(struct ksz_port *port)
3438 struct ksz_hw *hw = port->hw;
3444 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3445 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3446 hw_r_phy_ctrl(hw, phy, &data);
3448 data &= ~PHY_AUTO_NEG_ENABLE;
3450 if (10 == port->speed)
3451 data &= ~PHY_SPEED_100MBIT;
3452 else if (100 == port->speed)
3453 data |= PHY_SPEED_100MBIT;
3454 if (1 == port->duplex)
3455 data &= ~PHY_FULL_DUPLEX;
3456 else if (2 == port->duplex)
3457 data |= PHY_FULL_DUPLEX;
3458 hw_w_phy_ctrl(hw, phy, data);
3462 static void port_set_power_saving(struct ksz_port *port, int enable)
3464 struct ksz_hw *hw = port->hw;
3468 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3470 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3474 * KSZ8841 power management functions
3478 * hw_chk_wol_pme_status - check PMEN pin
3479 * @hw: The hardware instance.
3481 * This function is used to check PMEN pin is asserted.
3483 * Return 1 if PMEN pin is asserted; otherwise, 0.
3485 static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3487 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3488 struct pci_dev *pdev = hw_priv->pdev;
3493 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3494 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3498 * hw_clr_wol_pme_status - clear PMEN pin
3499 * @hw: The hardware instance.
3501 * This routine is used to clear PME_Status to deassert PMEN pin.
3503 static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3505 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3506 struct pci_dev *pdev = hw_priv->pdev;
3512 /* Clear PME_Status to deassert PMEN pin. */
3513 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3514 data |= PCI_PM_CTRL_PME_STATUS;
3515 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3519 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3520 * @hw: The hardware instance.
3521 * @set: The flag indicating whether to enable or disable.
3523 * This routine is used to enable or disable Wake-on-LAN.
3525 static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3527 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3528 struct pci_dev *pdev = hw_priv->pdev;
3533 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3534 data &= ~PCI_PM_CTRL_STATE_MASK;
3536 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3538 data &= ~PCI_PM_CTRL_PME_ENABLE;
3539 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3543 * hw_cfg_wol - configure Wake-on-LAN features
3544 * @hw: The hardware instance.
3545 * @frame: The pattern frame bit.
3546 * @set: The flag indicating whether to enable or disable.
3548 * This routine is used to enable or disable certain Wake-on-LAN features.
3550 static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3554 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3559 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3563 * hw_set_wol_frame - program Wake-on-LAN pattern
3564 * @hw: The hardware instance.
3565 * @i: The frame index.
3566 * @mask_size: The size of the mask.
3567 * @mask: Mask to ignore certain bytes in the pattern.
3568 * @frame_size: The size of the frame.
3569 * @pattern: The frame data.
3571 * This routine is used to program Wake-on-LAN pattern.
3573 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3574 u8 *mask, uint frame_size, u8 *pattern)
3584 if (frame_size > mask_size * 8)
3585 frame_size = mask_size * 8;
3586 if (frame_size > 64)
3590 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3591 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3593 bits = len = from = to = 0;
3597 data[to++] = pattern[from];
3603 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3611 } while (from < (int) frame_size);
3613 bits = mask[len - 1];
3616 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3619 crc = ether_crc(to, data);
3620 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3624 * hw_add_wol_arp - add ARP pattern
3625 * @hw: The hardware instance.
3626 * @ip_addr: The IPv4 address assigned to the device.
3628 * This routine is used to add ARP pattern for waking up the host.
3630 static void hw_add_wol_arp(struct ksz_hw *hw, u8 *ip_addr)
3632 u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3634 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3637 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3639 0x00, 0x00, 0x00, 0x00,
3640 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3641 0x00, 0x00, 0x00, 0x00 };
3643 memcpy(&pattern[38], ip_addr, 4);
3644 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3648 * hw_add_wol_bcast - add broadcast pattern
3649 * @hw: The hardware instance.
3651 * This routine is used to add broadcast pattern for waking up the host.
3653 static void hw_add_wol_bcast(struct ksz_hw *hw)
3655 u8 mask[] = { 0x3F };
3656 u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3658 hw_set_wol_frame(hw, 2, 1, mask, MAC_ADDR_LEN, pattern);
3662 * hw_add_wol_mcast - add multicast pattern
3663 * @hw: The hardware instance.
3665 * This routine is used to add multicast pattern for waking up the host.
3667 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3668 * by IPv6 ping command. Note that multicast packets are filtred through the
3669 * multicast hash table, so not all multicast packets can wake up the host.
3671 static void hw_add_wol_mcast(struct ksz_hw *hw)
3673 u8 mask[] = { 0x3F };
3674 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3676 memcpy(&pattern[3], &hw->override_addr[3], 3);
3677 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3681 * hw_add_wol_ucast - add unicast pattern
3682 * @hw: The hardware instance.
3684 * This routine is used to add unicast pattern to wakeup the host.
3686 * It is assumed the unicast packet is directed to the device, as the hardware
3687 * can only receive them in normal case.
3689 static void hw_add_wol_ucast(struct ksz_hw *hw)
3691 u8 mask[] = { 0x3F };
3693 hw_set_wol_frame(hw, 0, 1, mask, MAC_ADDR_LEN, hw->override_addr);
3697 * hw_enable_wol - enable Wake-on-LAN
3698 * @hw: The hardware instance.
3699 * @wol_enable: The Wake-on-LAN settings.
3700 * @net_addr: The IPv4 address assigned to the device.
3702 * This routine is used to enable Wake-on-LAN depending on driver settings.
3704 static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, u8 *net_addr)
3706 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3707 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3708 hw_add_wol_ucast(hw);
3709 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3710 hw_add_wol_mcast(hw);
3711 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3712 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3713 hw_add_wol_arp(hw, net_addr);
3717 * hw_init - check driver is correct for the hardware
3718 * @hw: The hardware instance.
3720 * This function checks the hardware is correct for this driver and sets the
3721 * hardware up for proper initialization.
3723 * Return number of ports or 0 if not right.
3725 static int hw_init(struct ksz_hw *hw)
3731 /* Set bus speed to 125MHz. */
3732 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3734 /* Check KSZ884x chip ID. */
3735 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3737 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3738 data &= KS884X_CHIP_ID_MASK_41;
3739 if (REG_CHIP_ID_41 == data)
3741 else if (REG_CHIP_ID_42 == data)
3746 /* Setup hardware features or bug workarounds. */
3747 if (revision <= 1) {
3748 hw->features |= SMALL_PACKET_TX_BUG;
3750 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3752 hw->features |= IPV6_CSUM_GEN_HACK;
3757 * hw_reset - reset the hardware
3758 * @hw: The hardware instance.
3760 * This routine resets the hardware.
3762 static void hw_reset(struct ksz_hw *hw)
3764 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3766 /* Wait for device to reset. */
3769 /* Write 0 to clear device reset. */
3770 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3774 * hw_setup - setup the hardware
3775 * @hw: The hardware instance.
3777 * This routine setup the hardware for proper operation.
3779 static void hw_setup(struct ksz_hw *hw)
3784 /* Change default LED mode. */
3785 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3787 data |= SET_DEFAULT_LED;
3788 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3791 /* Setup transmit control. */
3792 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3793 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3795 /* Setup receive control. */
3796 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3797 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3798 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3800 /* Hardware cannot handle UDP packet in IP fragments. */
3801 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3804 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3805 if (hw->promiscuous)
3806 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3810 * hw_setup_intr - setup interrupt mask
3811 * @hw: The hardware instance.
3813 * This routine setup the interrupt mask for proper operation.
3815 static void hw_setup_intr(struct ksz_hw *hw)
3817 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3820 static void ksz_check_desc_num(struct ksz_desc_info *info)
3822 #define MIN_DESC_SHIFT 2
3824 int alloc = info->alloc;
3828 while (!(alloc & 1)) {
3832 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3833 pr_alert("Hardware descriptor numbers not right!\n");
3838 if (shift < MIN_DESC_SHIFT)
3839 shift = MIN_DESC_SHIFT;
3841 info->alloc = alloc;
3843 info->mask = info->alloc - 1;
3846 static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3849 u32 phys = desc_info->ring_phys;
3850 struct ksz_hw_desc *desc = desc_info->ring_virt;
3851 struct ksz_desc *cur = desc_info->ring;
3852 struct ksz_desc *previous = NULL;
3854 for (i = 0; i < desc_info->alloc; i++) {
3856 phys += desc_info->size;
3858 previous->phw->next = cpu_to_le32(phys);
3860 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3861 previous->sw.buf.rx.end_of_ring = 1;
3862 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3864 desc_info->avail = desc_info->alloc;
3865 desc_info->last = desc_info->next = 0;
3867 desc_info->cur = desc_info->ring;
3871 * hw_set_desc_base - set descriptor base addresses
3872 * @hw: The hardware instance.
3873 * @tx_addr: The transmit descriptor base.
3874 * @rx_addr: The receive descriptor base.
3876 * This routine programs the descriptor base addresses after reset.
3878 static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3880 /* Set base address of Tx/Rx descriptors. */
3881 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3882 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3885 static void hw_reset_pkts(struct ksz_desc_info *info)
3887 info->cur = info->ring;
3888 info->avail = info->alloc;
3889 info->last = info->next = 0;
3892 static inline void hw_resume_rx(struct ksz_hw *hw)
3894 writel(DMA_START, hw->io + KS_DMA_RX_START);
3898 * hw_start_rx - start receiving
3899 * @hw: The hardware instance.
3901 * This routine starts the receive function of the hardware.
3903 static void hw_start_rx(struct ksz_hw *hw)
3905 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3907 /* Notify when the receive stops. */
3908 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3910 writel(DMA_START, hw->io + KS_DMA_RX_START);
3911 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3914 /* Variable overflows. */
3915 if (0 == hw->rx_stop)
3920 * hw_stop_rx - stop receiving
3921 * @hw: The hardware instance.
3923 * This routine stops the receive function of the hardware.
3925 static void hw_stop_rx(struct ksz_hw *hw)
3928 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3929 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3933 * hw_start_tx - start transmitting
3934 * @hw: The hardware instance.
3936 * This routine starts the transmit function of the hardware.
3938 static void hw_start_tx(struct ksz_hw *hw)
3940 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3944 * hw_stop_tx - stop transmitting
3945 * @hw: The hardware instance.
3947 * This routine stops the transmit function of the hardware.
3949 static void hw_stop_tx(struct ksz_hw *hw)
3951 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3955 * hw_disable - disable hardware
3956 * @hw: The hardware instance.
3958 * This routine disables the hardware.
3960 static void hw_disable(struct ksz_hw *hw)
3968 * hw_enable - enable hardware
3969 * @hw: The hardware instance.
3971 * This routine enables the hardware.
3973 static void hw_enable(struct ksz_hw *hw)
3981 * hw_alloc_pkt - allocate enough descriptors for transmission
3982 * @hw: The hardware instance.
3983 * @length: The length of the packet.
3984 * @physical: Number of descriptors required.
3986 * This function allocates descriptors for transmission.
3988 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3990 static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3992 /* Always leave one descriptor free. */
3993 if (hw->tx_desc_info.avail <= 1)
3996 /* Allocate a descriptor for transmission and mark it current. */
3997 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3998 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
4000 /* Keep track of number of transmit descriptors used so far. */
4002 hw->tx_size += length;
4004 /* Cannot hold on too much data. */
4005 if (hw->tx_size >= MAX_TX_HELD_SIZE)
4006 hw->tx_int_cnt = hw->tx_int_mask + 1;
4008 if (physical > hw->tx_desc_info.avail)
4011 return hw->tx_desc_info.avail;
4015 * hw_send_pkt - mark packet for transmission
4016 * @hw: The hardware instance.
4018 * This routine marks the packet for transmission in PCI version.
4020 static void hw_send_pkt(struct ksz_hw *hw)
4022 struct ksz_desc *cur = hw->tx_desc_info.cur;
4024 cur->sw.buf.tx.last_seg = 1;
4026 /* Interrupt only after specified number of descriptors used. */
4027 if (hw->tx_int_cnt > hw->tx_int_mask) {
4028 cur->sw.buf.tx.intr = 1;
4033 /* KSZ8842 supports port directed transmission. */
4034 cur->sw.buf.tx.dest_port = hw->dst_ports;
4038 writel(0, hw->io + KS_DMA_TX_START);
4041 static int empty_addr(u8 *addr)
4043 u32 *addr1 = (u32 *) addr;
4044 u16 *addr2 = (u16 *) &addr[4];
4046 return 0 == *addr1 && 0 == *addr2;
4050 * hw_set_addr - set MAC address
4051 * @hw: The hardware instance.
4053 * This routine programs the MAC address of the hardware when the address is
4056 static void hw_set_addr(struct ksz_hw *hw)
4060 for (i = 0; i < MAC_ADDR_LEN; i++)
4061 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4062 hw->io + KS884X_ADDR_0_OFFSET + i);
4064 sw_set_addr(hw, hw->override_addr);
4068 * hw_read_addr - read MAC address
4069 * @hw: The hardware instance.
4071 * This routine retrieves the MAC address of the hardware.
4073 static void hw_read_addr(struct ksz_hw *hw)
4077 for (i = 0; i < MAC_ADDR_LEN; i++)
4078 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4079 KS884X_ADDR_0_OFFSET + i);
4081 if (!hw->mac_override) {
4082 memcpy(hw->override_addr, hw->perm_addr, MAC_ADDR_LEN);
4083 if (empty_addr(hw->override_addr)) {
4084 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS,
4086 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4088 hw->override_addr[5] += hw->id;
4094 static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4101 for (i = 0; i < 2; i++) {
4103 mac_addr_hi |= mac_addr[i];
4105 mac_addr_hi |= ADD_ADDR_ENABLE;
4107 for (i = 2; i < 6; i++) {
4109 mac_addr_lo |= mac_addr[i];
4111 index *= ADD_ADDR_INCR;
4113 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4114 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4117 static void hw_set_add_addr(struct ksz_hw *hw)
4121 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4122 if (empty_addr(hw->address[i]))
4123 writel(0, hw->io + ADD_ADDR_INCR * i +
4126 hw_ena_add_addr(hw, i, hw->address[i]);
4130 static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4133 int j = ADDITIONAL_ENTRIES;
4135 if (!memcmp(hw->override_addr, mac_addr, MAC_ADDR_LEN))
4137 for (i = 0; i < hw->addr_list_size; i++) {
4138 if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN))
4140 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4143 if (j < ADDITIONAL_ENTRIES) {
4144 memcpy(hw->address[j], mac_addr, MAC_ADDR_LEN);
4145 hw_ena_add_addr(hw, j, hw->address[j]);
4151 static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4155 for (i = 0; i < hw->addr_list_size; i++) {
4156 if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN)) {
4157 memset(hw->address[i], 0, MAC_ADDR_LEN);
4158 writel(0, hw->io + ADD_ADDR_INCR * i +
4167 * hw_clr_multicast - clear multicast addresses
4168 * @hw: The hardware instance.
4170 * This routine removes all multicast addresses set in the hardware.
4172 static void hw_clr_multicast(struct ksz_hw *hw)
4176 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4177 hw->multi_bits[i] = 0;
4179 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4184 * hw_set_grp_addr - set multicast addresses
4185 * @hw: The hardware instance.
4187 * This routine programs multicast addresses for the hardware to accept those
4190 static void hw_set_grp_addr(struct ksz_hw *hw)
4197 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4199 for (i = 0; i < hw->multi_list_size; i++) {
4200 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4201 index = position >> 3;
4202 value = 1 << (position & 7);
4203 hw->multi_bits[index] |= (u8) value;
4206 for (i = 0; i < HW_MULTICAST_SIZE; i++)
4207 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4212 * hw_set_multicast - enable or disable all multicast receiving
4213 * @hw: The hardware instance.
4214 * @multicast: To turn on or off the all multicast feature.
4216 * This routine enables/disables the hardware to accept all multicast packets.
4218 static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4220 /* Stop receiving for reconfiguration. */
4224 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4226 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4233 * hw_set_promiscuous - enable or disable promiscuous receiving
4234 * @hw: The hardware instance.
4235 * @prom: To turn on or off the promiscuous feature.
4237 * This routine enables/disables the hardware to accept all packets.
4239 static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4241 /* Stop receiving for reconfiguration. */
4245 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4247 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4254 * sw_enable - enable the switch
4255 * @hw: The hardware instance.
4256 * @enable: The flag to enable or disable the switch
4258 * This routine is used to enable/disable the switch in KSZ8842.
4260 static void sw_enable(struct ksz_hw *hw, int enable)
4264 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4265 if (hw->dev_count > 1) {
4266 /* Set port-base vlan membership with host port. */
4267 sw_cfg_port_base_vlan(hw, port,
4268 HOST_MASK | (1 << port));
4269 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4271 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4272 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4275 if (hw->dev_count > 1)
4276 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4278 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4281 enable = KS8842_START;
4282 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4286 * sw_setup - setup the switch
4287 * @hw: The hardware instance.
4289 * This routine setup the hardware switch engine for default operation.
4291 static void sw_setup(struct ksz_hw *hw)
4295 sw_set_global_ctrl(hw);
4297 /* Enable switch broadcast storm protection at 10% percent rate. */
4298 sw_init_broad_storm(hw);
4299 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4300 for (port = 0; port < SWITCH_PORT_NUM; port++)
4301 sw_ena_broad_storm(hw, port);
4307 sw_init_prio_rate(hw);
4311 if (hw->features & STP_SUPPORT)
4313 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4314 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4315 hw->overrides |= PAUSE_FLOW_CTRL;
4320 * ksz_start_timer - start kernel timer
4321 * @info: Kernel timer information.
4322 * @time: The time tick.
4324 * This routine starts the kernel timer after the specified time tick.
4326 static void ksz_start_timer(struct ksz_timer_info *info, int time)
4329 info->timer.expires = jiffies + time;
4330 add_timer(&info->timer);
4337 * ksz_stop_timer - stop kernel timer
4338 * @info: Kernel timer information.
4340 * This routine stops the kernel timer.
4342 static void ksz_stop_timer(struct ksz_timer_info *info)
4346 del_timer_sync(&info->timer);
4350 static void ksz_init_timer(struct ksz_timer_info *info, int period,
4351 void (*function)(unsigned long), void *data)
4354 info->period = period;
4355 init_timer(&info->timer);
4356 info->timer.function = function;
4357 info->timer.data = (unsigned long) data;
4360 static void ksz_update_timer(struct ksz_timer_info *info)
4363 if (info->max > 0) {
4364 if (info->cnt < info->max) {
4365 info->timer.expires = jiffies + info->period;
4366 add_timer(&info->timer);
4369 } else if (info->max < 0) {
4370 info->timer.expires = jiffies + info->period;
4371 add_timer(&info->timer);
4376 * ksz_alloc_soft_desc - allocate software descriptors
4377 * @desc_info: Descriptor information structure.
4378 * @transmit: Indication that descriptors are for transmit.
4380 * This local function allocates software descriptors for manipulation in
4383 * Return 0 if successful.
4385 static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4387 desc_info->ring = kmalloc(sizeof(struct ksz_desc) * desc_info->alloc,
4389 if (!desc_info->ring)
4391 memset((void *) desc_info->ring, 0,
4392 sizeof(struct ksz_desc) * desc_info->alloc);
4393 hw_init_desc(desc_info, transmit);
4398 * ksz_alloc_desc - allocate hardware descriptors
4399 * @adapter: Adapter information structure.
4401 * This local function allocates hardware descriptors for receiving and
4404 * Return 0 if successful.
4406 static int ksz_alloc_desc(struct dev_info *adapter)
4408 struct ksz_hw *hw = &adapter->hw;
4411 /* Allocate memory for RX & TX descriptors. */
4412 adapter->desc_pool.alloc_size =
4413 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4414 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4417 adapter->desc_pool.alloc_virt =
4418 pci_alloc_consistent(
4419 adapter->pdev, adapter->desc_pool.alloc_size,
4420 &adapter->desc_pool.dma_addr);
4421 if (adapter->desc_pool.alloc_virt == NULL) {
4422 adapter->desc_pool.alloc_size = 0;
4425 memset(adapter->desc_pool.alloc_virt, 0, adapter->desc_pool.alloc_size);
4427 /* Align to the next cache line boundary. */
4428 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4430 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4431 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4432 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4434 /* Allocate receive/transmit descriptors. */
4435 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4436 adapter->desc_pool.virt;
4437 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4438 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4439 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4440 (adapter->desc_pool.virt + offset);
4441 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4443 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4445 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4452 * free_dma_buf - release DMA buffer resources
4453 * @adapter: Adapter information structure.
4455 * This routine is just a helper function to release the DMA buffer resources.
4457 static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4460 pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction);
4461 dev_kfree_skb(dma_buf->skb);
4462 dma_buf->skb = NULL;
4467 * ksz_init_rx_buffers - initialize receive descriptors
4468 * @adapter: Adapter information structure.
4470 * This routine initializes DMA buffers for receiving.
4472 static void ksz_init_rx_buffers(struct dev_info *adapter)
4475 struct ksz_desc *desc;
4476 struct ksz_dma_buf *dma_buf;
4477 struct ksz_hw *hw = &adapter->hw;
4478 struct ksz_desc_info *info = &hw->rx_desc_info;
4480 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4481 get_rx_pkt(info, &desc);
4483 dma_buf = DMA_BUFFER(desc);
4484 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4485 free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE);
4486 dma_buf->len = adapter->mtu;
4488 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4489 if (dma_buf->skb && !dma_buf->dma) {
4490 dma_buf->skb->dev = adapter->dev;
4491 dma_buf->dma = pci_map_single(
4493 skb_tail_pointer(dma_buf->skb),
4495 PCI_DMA_FROMDEVICE);
4498 /* Set descriptor. */
4499 set_rx_buf(desc, dma_buf->dma);
4500 set_rx_len(desc, dma_buf->len);
4506 * ksz_alloc_mem - allocate memory for hardware descriptors
4507 * @adapter: Adapter information structure.
4509 * This function allocates memory for use by hardware descriptors for receiving
4512 * Return 0 if successful.
4514 static int ksz_alloc_mem(struct dev_info *adapter)
4516 struct ksz_hw *hw = &adapter->hw;
4518 /* Determine the number of receive and transmit descriptors. */
4519 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4520 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4522 /* Determine how many descriptors to skip transmit interrupt. */
4524 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4525 if (hw->tx_int_mask > 8)
4526 hw->tx_int_mask = 8;
4527 while (hw->tx_int_mask) {
4529 hw->tx_int_mask >>= 1;
4531 if (hw->tx_int_cnt) {
4532 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4536 /* Determine the descriptor size. */
4537 hw->rx_desc_info.size =
4538 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4539 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4540 hw->tx_desc_info.size =
4541 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4542 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4543 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4544 pr_alert("Hardware descriptor size not right!\n");
4545 ksz_check_desc_num(&hw->rx_desc_info);
4546 ksz_check_desc_num(&hw->tx_desc_info);
4548 /* Allocate descriptors. */
4549 if (ksz_alloc_desc(adapter))
4556 * ksz_free_desc - free software and hardware descriptors
4557 * @adapter: Adapter information structure.
4559 * This local routine frees the software and hardware descriptors allocated by
4562 static void ksz_free_desc(struct dev_info *adapter)
4564 struct ksz_hw *hw = &adapter->hw;
4566 /* Reset descriptor. */
4567 hw->rx_desc_info.ring_virt = NULL;
4568 hw->tx_desc_info.ring_virt = NULL;
4569 hw->rx_desc_info.ring_phys = 0;
4570 hw->tx_desc_info.ring_phys = 0;
4573 if (adapter->desc_pool.alloc_virt)
4574 pci_free_consistent(
4576 adapter->desc_pool.alloc_size,
4577 adapter->desc_pool.alloc_virt,
4578 adapter->desc_pool.dma_addr);
4580 /* Reset resource pool. */
4581 adapter->desc_pool.alloc_size = 0;
4582 adapter->desc_pool.alloc_virt = NULL;
4584 kfree(hw->rx_desc_info.ring);
4585 hw->rx_desc_info.ring = NULL;
4586 kfree(hw->tx_desc_info.ring);
4587 hw->tx_desc_info.ring = NULL;
4591 * ksz_free_buffers - free buffers used in the descriptors
4592 * @adapter: Adapter information structure.
4593 * @desc_info: Descriptor information structure.
4595 * This local routine frees buffers used in the DMA buffers.
4597 static void ksz_free_buffers(struct dev_info *adapter,
4598 struct ksz_desc_info *desc_info, int direction)
4601 struct ksz_dma_buf *dma_buf;
4602 struct ksz_desc *desc = desc_info->ring;
4604 for (i = 0; i < desc_info->alloc; i++) {
4605 dma_buf = DMA_BUFFER(desc);
4607 free_dma_buf(adapter, dma_buf, direction);
4613 * ksz_free_mem - free all resources used by descriptors
4614 * @adapter: Adapter information structure.
4616 * This local routine frees all the resources allocated by ksz_alloc_mem().
4618 static void ksz_free_mem(struct dev_info *adapter)
4620 /* Free transmit buffers. */
4621 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4624 /* Free receive buffers. */
4625 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4626 PCI_DMA_FROMDEVICE);
4628 /* Free descriptors. */
4629 ksz_free_desc(adapter);
4632 static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4638 struct ksz_port_mib *port_mib;
4640 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4641 for (i = 0, port = first; i < cnt; i++, port++) {
4642 port_mib = &hw->port_mib[port];
4643 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4644 counter[mib] += port_mib->counter[mib];
4649 * send_packet - send packet
4650 * @skb: Socket buffer.
4651 * @dev: Network device.
4653 * This routine is used to send a packet out to the network.
4655 static void send_packet(struct sk_buff *skb, struct net_device *dev)
4657 struct ksz_desc *desc;
4658 struct ksz_desc *first;
4659 struct dev_priv *priv = netdev_priv(dev);
4660 struct dev_info *hw_priv = priv->adapter;
4661 struct ksz_hw *hw = &hw_priv->hw;
4662 struct ksz_desc_info *info = &hw->tx_desc_info;
4663 struct ksz_dma_buf *dma_buf;
4665 int last_frag = skb_shinfo(skb)->nr_frags;
4668 * KSZ8842 with multiple device interfaces needs to be told which port
4671 if (hw->dev_count > 1)
4672 hw->dst_ports = 1 << priv->port.first_port;
4674 /* Hardware will pad the length to 60. */
4677 /* Remember the very first descriptor. */
4681 dma_buf = DMA_BUFFER(desc);
4684 skb_frag_t *this_frag;
4686 dma_buf->len = skb->len - skb->data_len;
4688 dma_buf->dma = pci_map_single(
4689 hw_priv->pdev, skb->data, dma_buf->len,
4691 set_tx_buf(desc, dma_buf->dma);
4692 set_tx_len(desc, dma_buf->len);
4696 this_frag = &skb_shinfo(skb)->frags[frag];
4698 /* Get a new descriptor. */
4699 get_tx_pkt(info, &desc);
4701 /* Keep track of descriptors used so far. */
4704 dma_buf = DMA_BUFFER(desc);
4705 dma_buf->len = this_frag->size;
4707 dma_buf->dma = pci_map_single(
4709 page_address(this_frag->page) +
4710 this_frag->page_offset,
4713 set_tx_buf(desc, dma_buf->dma);
4714 set_tx_len(desc, dma_buf->len);
4717 if (frag == last_frag)
4720 /* Do not release the last descriptor here. */
4724 /* current points to the last descriptor. */
4727 /* Release the first descriptor. */
4728 release_desc(first);
4732 dma_buf->dma = pci_map_single(
4733 hw_priv->pdev, skb->data, dma_buf->len,
4735 set_tx_buf(desc, dma_buf->dma);
4736 set_tx_len(desc, dma_buf->len);
4739 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4740 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4741 (desc)->sw.buf.tx.csum_gen_udp = 1;
4745 * The last descriptor holds the packet so that it can be returned to
4746 * network subsystem after all descriptors are transmitted.
4752 /* Update transmit statistics. */
4753 priv->stats.tx_packets++;
4754 priv->stats.tx_bytes += len;
4758 * transmit_cleanup - clean up transmit descriptors
4759 * @dev: Network device.
4761 * This routine is called to clean up the transmitted buffers.
4763 static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4766 union desc_stat status;
4767 struct ksz_hw *hw = &hw_priv->hw;
4768 struct ksz_desc_info *info = &hw->tx_desc_info;
4769 struct ksz_desc *desc;
4770 struct ksz_dma_buf *dma_buf;
4771 struct net_device *dev = NULL;
4773 spin_lock(&hw_priv->hwlock);
4776 while (info->avail < info->alloc) {
4777 /* Get next descriptor which is not hardware owned. */
4778 desc = &info->ring[last];
4779 status.data = le32_to_cpu(desc->phw->ctrl.data);
4780 if (status.tx.hw_owned) {
4784 reset_desc(desc, status);
4787 dma_buf = DMA_BUFFER(desc);
4789 hw_priv->pdev, dma_buf->dma, dma_buf->len,
4792 /* This descriptor contains the last buffer in the packet. */
4794 dev = dma_buf->skb->dev;
4796 /* Release the packet back to network subsystem. */
4797 dev_kfree_skb_irq(dma_buf->skb);
4798 dma_buf->skb = NULL;
4801 /* Free the transmitted descriptor. */
4807 spin_unlock(&hw_priv->hwlock);
4809 /* Notify the network subsystem that the packet has been sent. */
4811 dev->trans_start = jiffies;
4815 * transmit_done - transmit done processing
4816 * @dev: Network device.
4818 * This routine is called when the transmit interrupt is triggered, indicating
4819 * either a packet is sent successfully or there are transmit errors.
4821 static void tx_done(struct dev_info *hw_priv)
4823 struct ksz_hw *hw = &hw_priv->hw;
4826 transmit_cleanup(hw_priv, 1);
4828 for (port = 0; port < hw->dev_count; port++) {
4829 struct net_device *dev = hw->port_info[port].pdev;
4831 if (netif_running(dev) && netif_queue_stopped(dev))
4832 netif_wake_queue(dev);
4836 static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4838 skb->dev = old->dev;
4839 skb->protocol = old->protocol;
4840 skb->ip_summed = old->ip_summed;
4841 skb->csum = old->csum;
4842 skb_set_network_header(skb, ETH_HLEN);
4848 * netdev_tx - send out packet
4849 * @skb: Socket buffer.
4850 * @dev: Network device.
4852 * This function is used by the upper network layer to send out a packet.
4854 * Return 0 if successful; otherwise an error code indicating failure.
4856 static int netdev_tx(struct sk_buff *skb, struct net_device *dev)
4858 struct dev_priv *priv = netdev_priv(dev);
4859 struct dev_info *hw_priv = priv->adapter;
4860 struct ksz_hw *hw = &hw_priv->hw;
4865 if (hw->features & SMALL_PACKET_TX_BUG) {
4866 struct sk_buff *org_skb = skb;
4868 if (skb->len <= 48) {
4869 if (skb_end_pointer(skb) - skb->data >= 50) {
4870 memset(&skb->data[skb->len], 0, 50 - skb->len);
4873 skb = dev_alloc_skb(50);
4875 return NETDEV_TX_BUSY;
4876 memcpy(skb->data, org_skb->data, org_skb->len);
4877 memset(&skb->data[org_skb->len], 0,
4880 copy_old_skb(org_skb, skb);
4885 spin_lock_irq(&hw_priv->hwlock);
4887 num = skb_shinfo(skb)->nr_frags + 1;
4888 left = hw_alloc_pkt(hw, skb->len, num);
4891 ((hw->features & IPV6_CSUM_GEN_HACK) &&
4892 (CHECKSUM_PARTIAL == skb->ip_summed) &&
4893 (ETH_P_IPV6 == htons(skb->protocol)))) {
4894 struct sk_buff *org_skb = skb;
4896 skb = dev_alloc_skb(org_skb->len);
4898 rc = NETDEV_TX_BUSY;
4901 skb_copy_and_csum_dev(org_skb, skb->data);
4902 org_skb->ip_summed = 0;
4903 skb->len = org_skb->len;
4904 copy_old_skb(org_skb, skb);
4906 send_packet(skb, dev);
4908 netif_stop_queue(dev);
4910 /* Stop the transmit queue until packet is allocated. */
4911 netif_stop_queue(dev);
4912 rc = NETDEV_TX_BUSY;
4915 spin_unlock_irq(&hw_priv->hwlock);
4921 * netdev_tx_timeout - transmit timeout processing
4922 * @dev: Network device.
4924 * This routine is called when the transmit timer expires. That indicates the
4925 * hardware is not running correctly because transmit interrupts are not
4926 * triggered to free up resources so that the transmit routine can continue
4927 * sending out packets. The hardware is reset to correct the problem.
4929 static void netdev_tx_timeout(struct net_device *dev)
4931 static unsigned long last_reset;
4933 struct dev_priv *priv = netdev_priv(dev);
4934 struct dev_info *hw_priv = priv->adapter;
4935 struct ksz_hw *hw = &hw_priv->hw;
4938 if (hw->dev_count > 1) {
4940 * Only reset the hardware if time between calls is long
4943 if (jiffies - last_reset <= dev->watchdog_timeo)
4947 last_reset = jiffies;
4952 transmit_cleanup(hw_priv, 0);
4953 hw_reset_pkts(&hw->rx_desc_info);
4954 hw_reset_pkts(&hw->tx_desc_info);
4955 ksz_init_rx_buffers(hw_priv);
4959 hw_set_desc_base(hw,
4960 hw->tx_desc_info.ring_phys,
4961 hw->rx_desc_info.ring_phys);
4964 hw_set_multicast(hw, hw->all_multi);
4965 else if (hw->multi_list_size)
4966 hw_set_grp_addr(hw);
4968 if (hw->dev_count > 1) {
4969 hw_set_add_addr(hw);
4970 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4971 struct net_device *port_dev;
4973 port_set_stp_state(hw, port,
4974 STP_STATE_DISABLED);
4976 port_dev = hw->port_info[port].pdev;
4977 if (netif_running(port_dev))
4978 port_set_stp_state(hw, port,
4987 dev->trans_start = jiffies;
4988 netif_wake_queue(dev);
4991 static inline void csum_verified(struct sk_buff *skb)
4993 unsigned short protocol;
4996 protocol = skb->protocol;
4997 skb_reset_network_header(skb);
4998 iph = (struct iphdr *) skb_network_header(skb);
4999 if (protocol == htons(ETH_P_8021Q)) {
5000 protocol = iph->tot_len;
5001 skb_set_network_header(skb, VLAN_HLEN);
5002 iph = (struct iphdr *) skb_network_header(skb);
5004 if (protocol == htons(ETH_P_IP)) {
5005 if (iph->protocol == IPPROTO_TCP)
5006 skb->ip_summed = CHECKSUM_UNNECESSARY;
5010 static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
5011 struct ksz_desc *desc, union desc_stat status)
5014 struct dev_priv *priv = netdev_priv(dev);
5015 struct dev_info *hw_priv = priv->adapter;
5016 struct ksz_dma_buf *dma_buf;
5017 struct sk_buff *skb;
5020 /* Received length includes 4-byte CRC. */
5021 packet_len = status.rx.frame_len - 4;
5023 dma_buf = DMA_BUFFER(desc);
5024 pci_dma_sync_single_for_cpu(
5025 hw_priv->pdev, dma_buf->dma, packet_len + 4,
5026 PCI_DMA_FROMDEVICE);
5029 /* skb->data != skb->head */
5030 skb = dev_alloc_skb(packet_len + 2);
5032 priv->stats.rx_dropped++;
5037 * Align socket buffer in 4-byte boundary for better
5040 skb_reserve(skb, 2);
5042 memcpy(skb_put(skb, packet_len),
5043 dma_buf->skb->data, packet_len);
5048 skb->protocol = eth_type_trans(skb, dev);
5050 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5053 /* Update receive statistics. */
5054 priv->stats.rx_packets++;
5055 priv->stats.rx_bytes += packet_len;
5057 /* Notify upper layer for received packet. */
5058 dev->last_rx = jiffies;
5060 rx_status = netif_rx(skb);
5065 static int dev_rcv_packets(struct dev_info *hw_priv)
5068 union desc_stat status;
5069 struct ksz_hw *hw = &hw_priv->hw;
5070 struct net_device *dev = hw->port_info[0].pdev;
5071 struct ksz_desc_info *info = &hw->rx_desc_info;
5072 int left = info->alloc;
5073 struct ksz_desc *desc;
5078 /* Get next descriptor which is not hardware owned. */
5079 desc = &info->ring[next];
5080 status.data = le32_to_cpu(desc->phw->ctrl.data);
5081 if (status.rx.hw_owned)
5084 /* Status valid only when last descriptor bit is set. */
5085 if (status.rx.last_desc && status.rx.first_desc) {
5086 if (rx_proc(dev, hw, desc, status))
5087 goto release_packet;
5101 static int port_rcv_packets(struct dev_info *hw_priv)
5104 union desc_stat status;
5105 struct ksz_hw *hw = &hw_priv->hw;
5106 struct net_device *dev = hw->port_info[0].pdev;
5107 struct ksz_desc_info *info = &hw->rx_desc_info;
5108 int left = info->alloc;
5109 struct ksz_desc *desc;
5114 /* Get next descriptor which is not hardware owned. */
5115 desc = &info->ring[next];
5116 status.data = le32_to_cpu(desc->phw->ctrl.data);
5117 if (status.rx.hw_owned)
5120 if (hw->dev_count > 1) {
5121 /* Get received port number. */
5122 int p = HW_TO_DEV_PORT(status.rx.src_port);
5124 dev = hw->port_info[p].pdev;
5125 if (!netif_running(dev))
5126 goto release_packet;
5129 /* Status valid only when last descriptor bit is set. */
5130 if (status.rx.last_desc && status.rx.first_desc) {
5131 if (rx_proc(dev, hw, desc, status))
5132 goto release_packet;
5146 static int dev_rcv_special(struct dev_info *hw_priv)
5149 union desc_stat status;
5150 struct ksz_hw *hw = &hw_priv->hw;
5151 struct net_device *dev = hw->port_info[0].pdev;
5152 struct ksz_desc_info *info = &hw->rx_desc_info;
5153 int left = info->alloc;
5154 struct ksz_desc *desc;
5159 /* Get next descriptor which is not hardware owned. */
5160 desc = &info->ring[next];
5161 status.data = le32_to_cpu(desc->phw->ctrl.data);
5162 if (status.rx.hw_owned)
5165 if (hw->dev_count > 1) {
5166 /* Get received port number. */
5167 int p = HW_TO_DEV_PORT(status.rx.src_port);
5169 dev = hw->port_info[p].pdev;
5170 if (!netif_running(dev))
5171 goto release_packet;
5174 /* Status valid only when last descriptor bit is set. */
5175 if (status.rx.last_desc && status.rx.first_desc) {
5177 * Receive without error. With receive errors
5178 * disabled, packets with receive errors will be
5179 * dropped, so no need to check the error bit.
5181 if (!status.rx.error || (status.data &
5182 KS_DESC_RX_ERROR_COND) ==
5183 KS_DESC_RX_ERROR_TOO_LONG) {
5184 if (rx_proc(dev, hw, desc, status))
5185 goto release_packet;
5188 struct dev_priv *priv = netdev_priv(dev);
5190 /* Update receive error statistics. */
5191 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5205 static void rx_proc_task(unsigned long data)
5207 struct dev_info *hw_priv = (struct dev_info *) data;
5208 struct ksz_hw *hw = &hw_priv->hw;
5212 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5214 /* In case receive process is suspended because of overrun. */
5217 /* tasklets are interruptible. */
5218 spin_lock_irq(&hw_priv->hwlock);
5219 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5220 spin_unlock_irq(&hw_priv->hwlock);
5222 hw_ack_intr(hw, KS884X_INT_RX);
5223 tasklet_schedule(&hw_priv->rx_tasklet);
5227 static void tx_proc_task(unsigned long data)
5229 struct dev_info *hw_priv = (struct dev_info *) data;
5230 struct ksz_hw *hw = &hw_priv->hw;
5232 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5236 /* tasklets are interruptible. */
5237 spin_lock_irq(&hw_priv->hwlock);
5238 hw_turn_on_intr(hw, KS884X_INT_TX);
5239 spin_unlock_irq(&hw_priv->hwlock);
5242 static inline void handle_rx_stop(struct ksz_hw *hw)
5244 /* Receive just has been stopped. */
5245 if (0 == hw->rx_stop)
5246 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5247 else if (hw->rx_stop > 1) {
5248 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5251 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5255 /* Receive just has been started. */
5260 * netdev_intr - interrupt handling
5261 * @irq: Interrupt number.
5262 * @dev_id: Network device.
5264 * This function is called by upper network layer to signal interrupt.
5266 * Return IRQ_HANDLED if interrupt is handled.
5268 static irqreturn_t netdev_intr(int irq, void *dev_id)
5270 uint int_enable = 0;
5271 struct net_device *dev = (struct net_device *) dev_id;
5272 struct dev_priv *priv = netdev_priv(dev);
5273 struct dev_info *hw_priv = priv->adapter;
5274 struct ksz_hw *hw = &hw_priv->hw;
5276 hw_read_intr(hw, &int_enable);
5278 /* Not our interrupt! */
5283 hw_ack_intr(hw, int_enable);
5284 int_enable &= hw->intr_mask;
5286 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5287 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5288 tasklet_schedule(&hw_priv->tx_tasklet);
5291 if (likely(int_enable & KS884X_INT_RX)) {
5292 hw_dis_intr_bit(hw, KS884X_INT_RX);
5293 tasklet_schedule(&hw_priv->rx_tasklet);
5296 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5297 priv->stats.rx_fifo_errors++;
5301 if (unlikely(int_enable & KS884X_INT_PHY)) {
5302 struct ksz_port *port = &priv->port;
5304 hw->features |= LINK_INT_WORKING;
5305 port_get_link_speed(port);
5308 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5313 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5316 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5317 pr_info("Tx stopped\n");
5318 data = readl(hw->io + KS_DMA_TX_CTRL);
5319 if (!(data & DMA_TX_ENABLE))
5320 pr_info("Tx disabled\n");
5331 * Linux network device functions
5334 static unsigned long next_jiffies;
5336 #ifdef CONFIG_NET_POLL_CONTROLLER
5337 static void netdev_netpoll(struct net_device *dev)
5339 struct dev_priv *priv = netdev_priv(dev);
5340 struct dev_info *hw_priv = priv->adapter;
5342 hw_dis_intr(&hw_priv->hw);
5343 netdev_intr(dev->irq, dev);
5347 static void bridge_change(struct ksz_hw *hw)
5351 struct ksz_switch *sw = hw->ksz_switch;
5353 /* No ports in forwarding state. */
5355 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5358 for (port = 0; port < SWITCH_PORT_NUM; port++) {
5359 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5360 member = HOST_MASK | sw->member;
5362 member = HOST_MASK | (1 << port);
5363 if (member != sw->port_cfg[port].member)
5364 sw_cfg_port_base_vlan(hw, port, member);
5369 * netdev_close - close network device
5370 * @dev: Network device.
5372 * This function process the close operation of network device. This is caused
5373 * by the user command "ifconfig ethX down."
5375 * Return 0 if successful; otherwise an error code indicating failure.
5377 static int netdev_close(struct net_device *dev)
5379 struct dev_priv *priv = netdev_priv(dev);
5380 struct dev_info *hw_priv = priv->adapter;
5381 struct ksz_port *port = &priv->port;
5382 struct ksz_hw *hw = &hw_priv->hw;
5385 netif_stop_queue(dev);
5387 ksz_stop_timer(&priv->monitor_timer_info);
5389 /* Need to shut the port manually in multiple device interfaces mode. */
5390 if (hw->dev_count > 1) {
5391 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5393 /* Port is closed. Need to change bridge setting. */
5394 if (hw->features & STP_SUPPORT) {
5395 pi = 1 << port->first_port;
5396 if (hw->ksz_switch->member & pi) {
5397 hw->ksz_switch->member &= ~pi;
5402 if (port->first_port > 0)
5403 hw_del_addr(hw, dev->dev_addr);
5404 if (!hw_priv->wol_enable)
5405 port_set_power_saving(port, true);
5407 if (priv->multicast)
5409 if (priv->promiscuous)
5413 if (!(hw_priv->opened)) {
5414 ksz_stop_timer(&hw_priv->mib_timer_info);
5415 flush_work(&hw_priv->mib_read);
5419 hw_clr_multicast(hw);
5421 /* Delay for receive task to stop scheduling itself. */
5424 tasklet_disable(&hw_priv->rx_tasklet);
5425 tasklet_disable(&hw_priv->tx_tasklet);
5426 free_irq(dev->irq, hw_priv->dev);
5428 transmit_cleanup(hw_priv, 0);
5429 hw_reset_pkts(&hw->rx_desc_info);
5430 hw_reset_pkts(&hw->tx_desc_info);
5432 /* Clean out static MAC table when the switch is shutdown. */
5433 if (hw->features & STP_SUPPORT)
5434 sw_clr_sta_mac_table(hw);
5440 static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5442 if (hw->ksz_switch) {
5445 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5446 if (hw->features & RX_HUGE_FRAME)
5447 data |= SWITCH_HUGE_PACKET;
5449 data &= ~SWITCH_HUGE_PACKET;
5450 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5452 if (hw->features & RX_HUGE_FRAME) {
5453 hw->rx_cfg |= DMA_RX_ERROR;
5454 hw_priv->dev_rcv = dev_rcv_special;
5456 hw->rx_cfg &= ~DMA_RX_ERROR;
5457 if (hw->dev_count > 1)
5458 hw_priv->dev_rcv = port_rcv_packets;
5460 hw_priv->dev_rcv = dev_rcv_packets;
5464 static int prepare_hardware(struct net_device *dev)
5466 struct dev_priv *priv = netdev_priv(dev);
5467 struct dev_info *hw_priv = priv->adapter;
5468 struct ksz_hw *hw = &hw_priv->hw;
5471 /* Remember the network device that requests interrupts. */
5473 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5476 tasklet_enable(&hw_priv->rx_tasklet);
5477 tasklet_enable(&hw_priv->tx_tasklet);
5479 hw->promiscuous = 0;
5481 hw->multi_list_size = 0;
5485 hw_set_desc_base(hw,
5486 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5488 hw_cfg_huge_frame(hw_priv, hw);
5489 ksz_init_rx_buffers(hw_priv);
5493 static void set_media_state(struct net_device *dev, int media_state)
5495 struct dev_priv *priv = netdev_priv(dev);
5497 if (media_state == priv->media_state)
5498 netif_carrier_on(dev);
5500 netif_carrier_off(dev);
5501 netif_info(priv, link, dev, "link %s\n",
5502 media_state == priv->media_state ? "on" : "off");
5506 * netdev_open - open network device
5507 * @dev: Network device.
5509 * This function process the open operation of network device. This is caused
5510 * by the user command "ifconfig ethX up."
5512 * Return 0 if successful; otherwise an error code indicating failure.
5514 static int netdev_open(struct net_device *dev)
5516 struct dev_priv *priv = netdev_priv(dev);
5517 struct dev_info *hw_priv = priv->adapter;
5518 struct ksz_hw *hw = &hw_priv->hw;
5519 struct ksz_port *port = &priv->port;
5524 priv->multicast = 0;
5525 priv->promiscuous = 0;
5527 /* Reset device statistics. */
5528 memset(&priv->stats, 0, sizeof(struct net_device_stats));
5529 memset((void *) port->counter, 0,
5530 (sizeof(u64) * OID_COUNTER_LAST));
5532 if (!(hw_priv->opened)) {
5533 rc = prepare_hardware(dev);
5536 for (i = 0; i < hw->mib_port_cnt; i++) {
5537 if (next_jiffies < jiffies)
5538 next_jiffies = jiffies + HZ * 2;
5540 next_jiffies += HZ * 1;
5541 hw_priv->counter[i].time = next_jiffies;
5542 hw->port_mib[i].state = media_disconnected;
5543 port_init_cnt(hw, i);
5546 hw->port_mib[HOST_PORT].state = media_connected;
5548 hw_add_wol_bcast(hw);
5549 hw_cfg_wol_pme(hw, 0);
5550 hw_clr_wol_pme_status(&hw_priv->hw);
5553 port_set_power_saving(port, false);
5555 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5557 * Initialize to invalid value so that link detection
5560 hw->port_info[p].partner = 0xFF;
5561 hw->port_info[p].state = media_disconnected;
5564 /* Need to open the port in multiple device interfaces mode. */
5565 if (hw->dev_count > 1) {
5566 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5567 if (port->first_port > 0)
5568 hw_add_addr(hw, dev->dev_addr);
5571 port_get_link_speed(port);
5572 if (port->force_link)
5573 port_force_link_speed(port);
5575 port_set_link_speed(port);
5577 if (!(hw_priv->opened)) {
5582 if (hw->mib_port_cnt)
5583 ksz_start_timer(&hw_priv->mib_timer_info,
5584 hw_priv->mib_timer_info.period);
5589 ksz_start_timer(&priv->monitor_timer_info,
5590 priv->monitor_timer_info.period);
5592 priv->media_state = port->linked->state;
5594 set_media_state(dev, media_connected);
5595 netif_start_queue(dev);
5600 /* RX errors = rx_errors */
5601 /* RX dropped = rx_dropped */
5602 /* RX overruns = rx_fifo_errors */
5603 /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5604 /* TX errors = tx_errors */
5605 /* TX dropped = tx_dropped */
5606 /* TX overruns = tx_fifo_errors */
5607 /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5608 /* collisions = collisions */
5611 * netdev_query_statistics - query network device statistics
5612 * @dev: Network device.
5614 * This function returns the statistics of the network device. The device
5615 * needs not be opened.
5617 * Return network device statistics.
5619 static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5621 struct dev_priv *priv = netdev_priv(dev);
5622 struct ksz_port *port = &priv->port;
5623 struct ksz_hw *hw = &priv->adapter->hw;
5624 struct ksz_port_mib *mib;
5628 priv->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5629 priv->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5631 /* Reset to zero to add count later. */
5632 priv->stats.multicast = 0;
5633 priv->stats.collisions = 0;
5634 priv->stats.rx_length_errors = 0;
5635 priv->stats.rx_crc_errors = 0;
5636 priv->stats.rx_frame_errors = 0;
5637 priv->stats.tx_window_errors = 0;
5639 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5640 mib = &hw->port_mib[p];
5642 priv->stats.multicast += (unsigned long)
5643 mib->counter[MIB_COUNTER_RX_MULTICAST];
5645 priv->stats.collisions += (unsigned long)
5646 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5648 priv->stats.rx_length_errors += (unsigned long)(
5649 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5650 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5651 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5652 mib->counter[MIB_COUNTER_RX_JABBER]);
5653 priv->stats.rx_crc_errors += (unsigned long)
5654 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5655 priv->stats.rx_frame_errors += (unsigned long)(
5656 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5657 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5659 priv->stats.tx_window_errors += (unsigned long)
5660 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5663 return &priv->stats;
5667 * netdev_set_mac_address - set network device MAC address
5668 * @dev: Network device.
5669 * @addr: Buffer of MAC address.
5671 * This function is used to set the MAC address of the network device.
5673 * Return 0 to indicate success.
5675 static int netdev_set_mac_address(struct net_device *dev, void *addr)
5677 struct dev_priv *priv = netdev_priv(dev);
5678 struct dev_info *hw_priv = priv->adapter;
5679 struct ksz_hw *hw = &hw_priv->hw;
5680 struct sockaddr *mac = addr;
5683 if (priv->port.first_port > 0)
5684 hw_del_addr(hw, dev->dev_addr);
5686 hw->mac_override = 1;
5687 memcpy(hw->override_addr, mac->sa_data, MAC_ADDR_LEN);
5690 memcpy(dev->dev_addr, mac->sa_data, MAX_ADDR_LEN);
5692 interrupt = hw_block_intr(hw);
5694 if (priv->port.first_port > 0)
5695 hw_add_addr(hw, dev->dev_addr);
5698 hw_restore_intr(hw, interrupt);
5703 static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5704 struct ksz_hw *hw, int promiscuous)
5706 if (promiscuous != priv->promiscuous) {
5707 u8 prev_state = hw->promiscuous;
5713 priv->promiscuous = promiscuous;
5715 /* Turn on/off promiscuous mode. */
5716 if (hw->promiscuous <= 1 && prev_state <= 1)
5717 hw_set_promiscuous(hw, hw->promiscuous);
5720 * Port is not in promiscuous mode, meaning it is released
5723 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5725 struct ksz_switch *sw = hw->ksz_switch;
5726 int port = priv->port.first_port;
5728 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5730 if (sw->member & port) {
5731 sw->member &= ~port;
5738 static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5741 if (multicast != priv->multicast) {
5742 u8 all_multi = hw->all_multi;
5748 priv->multicast = multicast;
5750 /* Turn on/off all multicast mode. */
5751 if (hw->all_multi <= 1 && all_multi <= 1)
5752 hw_set_multicast(hw, hw->all_multi);
5757 * netdev_set_rx_mode
5758 * @dev: Network device.
5760 * This routine is used to set multicast addresses or put the network device
5761 * into promiscuous mode.
5763 static void netdev_set_rx_mode(struct net_device *dev)
5765 struct dev_priv *priv = netdev_priv(dev);
5766 struct dev_info *hw_priv = priv->adapter;
5767 struct ksz_hw *hw = &hw_priv->hw;
5768 struct dev_mc_list *mc_ptr;
5769 int multicast = (dev->flags & IFF_ALLMULTI);
5771 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5773 if (hw_priv->hw.dev_count > 1)
5774 multicast |= (dev->flags & IFF_MULTICAST);
5775 dev_set_multicast(priv, hw, multicast);
5777 /* Cannot use different hashes in multiple device interfaces mode. */
5778 if (hw_priv->hw.dev_count > 1)
5781 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5784 /* List too big to support so turn on all multicast mode. */
5785 if (dev->mc_count > MAX_MULTICAST_LIST) {
5786 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5787 hw->multi_list_size = MAX_MULTICAST_LIST;
5789 hw_set_multicast(hw, hw->all_multi);
5794 netdev_for_each_mc_addr(mc_ptr, dev) {
5795 if (!(*mc_ptr->dmi_addr & 1))
5797 if (i >= MAX_MULTICAST_LIST)
5799 memcpy(hw->multi_list[i++], mc_ptr->dmi_addr,
5802 hw->multi_list_size = (u8) i;
5803 hw_set_grp_addr(hw);
5805 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5807 hw_set_multicast(hw, hw->all_multi);
5809 hw->multi_list_size = 0;
5810 hw_clr_multicast(hw);
5814 static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5816 struct dev_priv *priv = netdev_priv(dev);
5817 struct dev_info *hw_priv = priv->adapter;
5818 struct ksz_hw *hw = &hw_priv->hw;
5821 if (netif_running(dev))
5824 /* Cannot use different MTU in multiple device interfaces mode. */
5825 if (hw->dev_count > 1)
5826 if (dev != hw_priv->dev)
5831 if (dev->mtu != new_mtu) {
5832 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5833 if (hw_mtu > MAX_RX_BUF_SIZE)
5835 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5836 hw->features |= RX_HUGE_FRAME;
5837 hw_mtu = MAX_RX_BUF_SIZE;
5839 hw->features &= ~RX_HUGE_FRAME;
5840 hw_mtu = REGULAR_RX_BUF_SIZE;
5842 hw_mtu = (hw_mtu + 3) & ~3;
5843 hw_priv->mtu = hw_mtu;
5850 * netdev_ioctl - I/O control processing
5851 * @dev: Network device.
5852 * @ifr: Interface request structure.
5853 * @cmd: I/O control code.
5855 * This function is used to process I/O control calls.
5857 * Return 0 to indicate success.
5859 static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5861 struct dev_priv *priv = netdev_priv(dev);
5862 struct dev_info *hw_priv = priv->adapter;
5863 struct ksz_hw *hw = &hw_priv->hw;
5864 struct ksz_port *port = &priv->port;
5867 struct mii_ioctl_data *data = if_mii(ifr);
5869 if (down_interruptible(&priv->proc_sem))
5870 return -ERESTARTSYS;
5872 /* assume success */
5875 /* Get address of MII PHY in use. */
5877 data->phy_id = priv->id;
5879 /* Fallthrough... */
5881 /* Read MII PHY register. */
5883 if (data->phy_id != priv->id || data->reg_num >= 6)
5886 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5890 /* Write MII PHY register. */
5892 if (!capable(CAP_NET_ADMIN))
5894 else if (data->phy_id != priv->id || data->reg_num >= 6)
5897 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5902 result = -EOPNOTSUPP;
5905 up(&priv->proc_sem);
5915 * mdio_read - read PHY register
5916 * @dev: Network device.
5917 * @phy_id: The PHY id.
5918 * @reg_num: The register number.
5920 * This function returns the PHY register value.
5922 * Return the register value.
5924 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5926 struct dev_priv *priv = netdev_priv(dev);
5927 struct ksz_port *port = &priv->port;
5928 struct ksz_hw *hw = port->hw;
5931 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5936 * mdio_write - set PHY register
5937 * @dev: Network device.
5938 * @phy_id: The PHY id.
5939 * @reg_num: The register number.
5940 * @val: The register value.
5942 * This procedure sets the PHY register value.
5944 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5946 struct dev_priv *priv = netdev_priv(dev);
5947 struct ksz_port *port = &priv->port;
5948 struct ksz_hw *hw = port->hw;
5952 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5953 hw_w_phy(hw, pi, reg_num << 1, val);
5960 #define EEPROM_SIZE 0x40
5962 static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5964 #define ADVERTISED_ALL \
5965 (ADVERTISED_10baseT_Half | \
5966 ADVERTISED_10baseT_Full | \
5967 ADVERTISED_100baseT_Half | \
5968 ADVERTISED_100baseT_Full)
5970 /* These functions use the MII functions in mii.c. */
5973 * netdev_get_settings - get network device settings
5974 * @dev: Network device.
5975 * @cmd: Ethtool command.
5977 * This function queries the PHY and returns its state in the ethtool command.
5979 * Return 0 if successful; otherwise an error code.
5981 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5983 struct dev_priv *priv = netdev_priv(dev);
5984 struct dev_info *hw_priv = priv->adapter;
5986 mutex_lock(&hw_priv->lock);
5987 mii_ethtool_gset(&priv->mii_if, cmd);
5988 cmd->advertising |= SUPPORTED_TP;
5989 mutex_unlock(&hw_priv->lock);
5991 /* Save advertised settings for workaround in next function. */
5992 priv->advertising = cmd->advertising;
5997 * netdev_set_settings - set network device settings
5998 * @dev: Network device.
5999 * @cmd: Ethtool command.
6001 * This function sets the PHY according to the ethtool command.
6003 * Return 0 if successful; otherwise an error code.
6005 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6007 struct dev_priv *priv = netdev_priv(dev);
6008 struct dev_info *hw_priv = priv->adapter;
6009 struct ksz_port *port = &priv->port;
6013 * ethtool utility does not change advertised setting if auto
6014 * negotiation is not specified explicitly.
6016 if (cmd->autoneg && priv->advertising == cmd->advertising) {
6017 cmd->advertising |= ADVERTISED_ALL;
6018 if (10 == cmd->speed)
6020 ~(ADVERTISED_100baseT_Full |
6021 ADVERTISED_100baseT_Half);
6022 else if (100 == cmd->speed)
6024 ~(ADVERTISED_10baseT_Full |
6025 ADVERTISED_10baseT_Half);
6026 if (0 == cmd->duplex)
6028 ~(ADVERTISED_100baseT_Full |
6029 ADVERTISED_10baseT_Full);
6030 else if (1 == cmd->duplex)
6032 ~(ADVERTISED_100baseT_Half |
6033 ADVERTISED_10baseT_Half);
6035 mutex_lock(&hw_priv->lock);
6037 (cmd->advertising & ADVERTISED_ALL) ==
6041 port->force_link = 0;
6043 port->duplex = cmd->duplex + 1;
6044 if (cmd->speed != 1000)
6045 port->speed = cmd->speed;
6047 port->force_link = 0;
6049 port->force_link = 1;
6051 rc = mii_ethtool_sset(&priv->mii_if, cmd);
6052 mutex_unlock(&hw_priv->lock);
6057 * netdev_nway_reset - restart auto-negotiation
6058 * @dev: Network device.
6060 * This function restarts the PHY for auto-negotiation.
6062 * Return 0 if successful; otherwise an error code.
6064 static int netdev_nway_reset(struct net_device *dev)
6066 struct dev_priv *priv = netdev_priv(dev);
6067 struct dev_info *hw_priv = priv->adapter;
6070 mutex_lock(&hw_priv->lock);
6071 rc = mii_nway_restart(&priv->mii_if);
6072 mutex_unlock(&hw_priv->lock);
6077 * netdev_get_link - get network device link status
6078 * @dev: Network device.
6080 * This function gets the link status from the PHY.
6082 * Return true if PHY is linked and false otherwise.
6084 static u32 netdev_get_link(struct net_device *dev)
6086 struct dev_priv *priv = netdev_priv(dev);
6089 rc = mii_link_ok(&priv->mii_if);
6094 * netdev_get_drvinfo - get network driver information
6095 * @dev: Network device.
6096 * @info: Ethtool driver info data structure.
6098 * This procedure returns the driver information.
6100 static void netdev_get_drvinfo(struct net_device *dev,
6101 struct ethtool_drvinfo *info)
6103 struct dev_priv *priv = netdev_priv(dev);
6104 struct dev_info *hw_priv = priv->adapter;
6106 strcpy(info->driver, DRV_NAME);
6107 strcpy(info->version, DRV_VERSION);
6108 strcpy(info->bus_info, pci_name(hw_priv->pdev));
6112 * netdev_get_regs_len - get length of register dump
6113 * @dev: Network device.
6115 * This function returns the length of the register dump.
6117 * Return length of the register dump.
6119 static struct hw_regs {
6122 } hw_regs_range[] = {
6123 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
6124 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
6125 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6126 { KS884X_SIDER_P, KS8842_SGCR7_P },
6127 { KS8842_MACAR1_P, KS8842_TOSR8_P },
6128 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
6132 static int netdev_get_regs_len(struct net_device *dev)
6134 struct hw_regs *range = hw_regs_range;
6135 int regs_len = 0x10 * sizeof(u32);
6137 while (range->end > range->start) {
6138 regs_len += (range->end - range->start + 3) / 4 * 4;
6145 * netdev_get_regs - get register dump
6146 * @dev: Network device.
6147 * @regs: Ethtool registers data structure.
6148 * @ptr: Buffer to store the register values.
6150 * This procedure dumps the register values in the provided buffer.
6152 static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6155 struct dev_priv *priv = netdev_priv(dev);
6156 struct dev_info *hw_priv = priv->adapter;
6157 struct ksz_hw *hw = &hw_priv->hw;
6158 int *buf = (int *) ptr;
6159 struct hw_regs *range = hw_regs_range;
6162 mutex_lock(&hw_priv->lock);
6164 for (len = 0; len < 0x40; len += 4) {
6165 pci_read_config_dword(hw_priv->pdev, len, buf);
6168 while (range->end > range->start) {
6169 for (len = range->start; len < range->end; len += 4) {
6170 *buf = readl(hw->io + len);
6175 mutex_unlock(&hw_priv->lock);
6178 #define WOL_SUPPORT \
6179 (WAKE_PHY | WAKE_MAGIC | \
6180 WAKE_UCAST | WAKE_MCAST | \
6181 WAKE_BCAST | WAKE_ARP)
6184 * netdev_get_wol - get Wake-on-LAN support
6185 * @dev: Network device.
6186 * @wol: Ethtool Wake-on-LAN data structure.
6188 * This procedure returns Wake-on-LAN support.
6190 static void netdev_get_wol(struct net_device *dev,
6191 struct ethtool_wolinfo *wol)
6193 struct dev_priv *priv = netdev_priv(dev);
6194 struct dev_info *hw_priv = priv->adapter;
6196 wol->supported = hw_priv->wol_support;
6197 wol->wolopts = hw_priv->wol_enable;
6198 memset(&wol->sopass, 0, sizeof(wol->sopass));
6202 * netdev_set_wol - set Wake-on-LAN support
6203 * @dev: Network device.
6204 * @wol: Ethtool Wake-on-LAN data structure.
6206 * This function sets Wake-on-LAN support.
6208 * Return 0 if successful; otherwise an error code.
6210 static int netdev_set_wol(struct net_device *dev,
6211 struct ethtool_wolinfo *wol)
6213 struct dev_priv *priv = netdev_priv(dev);
6214 struct dev_info *hw_priv = priv->adapter;
6216 /* Need to find a way to retrieve the device IP address. */
6217 u8 net_addr[] = { 192, 168, 1, 1 };
6219 if (wol->wolopts & ~hw_priv->wol_support)
6222 hw_priv->wol_enable = wol->wolopts;
6224 /* Link wakeup cannot really be disabled. */
6226 hw_priv->wol_enable |= WAKE_PHY;
6227 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6232 * netdev_get_msglevel - get debug message level
6233 * @dev: Network device.
6235 * This function returns current debug message level.
6237 * Return current debug message flags.
6239 static u32 netdev_get_msglevel(struct net_device *dev)
6241 struct dev_priv *priv = netdev_priv(dev);
6243 return priv->msg_enable;
6247 * netdev_set_msglevel - set debug message level
6248 * @dev: Network device.
6249 * @value: Debug message flags.
6251 * This procedure sets debug message level.
6253 static void netdev_set_msglevel(struct net_device *dev, u32 value)
6255 struct dev_priv *priv = netdev_priv(dev);
6257 priv->msg_enable = value;
6261 * netdev_get_eeprom_len - get EEPROM length
6262 * @dev: Network device.
6264 * This function returns the length of the EEPROM.
6266 * Return length of the EEPROM.
6268 static int netdev_get_eeprom_len(struct net_device *dev)
6270 return EEPROM_SIZE * 2;
6274 * netdev_get_eeprom - get EEPROM data
6275 * @dev: Network device.
6276 * @eeprom: Ethtool EEPROM data structure.
6277 * @data: Buffer to store the EEPROM data.
6279 * This function dumps the EEPROM data in the provided buffer.
6281 * Return 0 if successful; otherwise an error code.
6283 #define EEPROM_MAGIC 0x10A18842
6285 static int netdev_get_eeprom(struct net_device *dev,
6286 struct ethtool_eeprom *eeprom, u8 *data)
6288 struct dev_priv *priv = netdev_priv(dev);
6289 struct dev_info *hw_priv = priv->adapter;
6290 u8 *eeprom_byte = (u8 *) eeprom_data;
6294 len = (eeprom->offset + eeprom->len + 1) / 2;
6295 for (i = eeprom->offset / 2; i < len; i++)
6296 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6297 eeprom->magic = EEPROM_MAGIC;
6298 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6304 * netdev_set_eeprom - write EEPROM data
6305 * @dev: Network device.
6306 * @eeprom: Ethtool EEPROM data structure.
6307 * @data: Data buffer.
6309 * This function modifies the EEPROM data one byte at a time.
6311 * Return 0 if successful; otherwise an error code.
6313 static int netdev_set_eeprom(struct net_device *dev,
6314 struct ethtool_eeprom *eeprom, u8 *data)
6316 struct dev_priv *priv = netdev_priv(dev);
6317 struct dev_info *hw_priv = priv->adapter;
6318 u16 eeprom_word[EEPROM_SIZE];
6319 u8 *eeprom_byte = (u8 *) eeprom_word;
6323 if (eeprom->magic != EEPROM_MAGIC)
6326 len = (eeprom->offset + eeprom->len + 1) / 2;
6327 for (i = eeprom->offset / 2; i < len; i++)
6328 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6329 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6330 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6331 for (i = 0; i < EEPROM_SIZE; i++)
6332 if (eeprom_word[i] != eeprom_data[i]) {
6333 eeprom_data[i] = eeprom_word[i];
6334 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6341 * netdev_get_pauseparam - get flow control parameters
6342 * @dev: Network device.
6343 * @pause: Ethtool PAUSE settings data structure.
6345 * This procedure returns the PAUSE control flow settings.
6347 static void netdev_get_pauseparam(struct net_device *dev,
6348 struct ethtool_pauseparam *pause)
6350 struct dev_priv *priv = netdev_priv(dev);
6351 struct dev_info *hw_priv = priv->adapter;
6352 struct ksz_hw *hw = &hw_priv->hw;
6354 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6355 if (!hw->ksz_switch) {
6357 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6359 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6362 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6363 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6365 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6366 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6371 * netdev_set_pauseparam - set flow control parameters
6372 * @dev: Network device.
6373 * @pause: Ethtool PAUSE settings data structure.
6375 * This function sets the PAUSE control flow settings.
6376 * Not implemented yet.
6378 * Return 0 if successful; otherwise an error code.
6380 static int netdev_set_pauseparam(struct net_device *dev,
6381 struct ethtool_pauseparam *pause)
6383 struct dev_priv *priv = netdev_priv(dev);
6384 struct dev_info *hw_priv = priv->adapter;
6385 struct ksz_hw *hw = &hw_priv->hw;
6386 struct ksz_port *port = &priv->port;
6388 mutex_lock(&hw_priv->lock);
6389 if (pause->autoneg) {
6390 if (!pause->rx_pause && !pause->tx_pause)
6391 port->flow_ctrl = PHY_NO_FLOW_CTRL;
6393 port->flow_ctrl = PHY_FLOW_CTRL;
6394 hw->overrides &= ~PAUSE_FLOW_CTRL;
6395 port->force_link = 0;
6396 if (hw->ksz_switch) {
6397 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6398 SWITCH_RX_FLOW_CTRL, 1);
6399 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6400 SWITCH_TX_FLOW_CTRL, 1);
6402 port_set_link_speed(port);
6404 hw->overrides |= PAUSE_FLOW_CTRL;
6405 if (hw->ksz_switch) {
6406 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6407 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6408 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6409 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6411 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6413 mutex_unlock(&hw_priv->lock);
6419 * netdev_get_ringparam - get tx/rx ring parameters
6420 * @dev: Network device.
6421 * @pause: Ethtool RING settings data structure.
6423 * This procedure returns the TX/RX ring settings.
6425 static void netdev_get_ringparam(struct net_device *dev,
6426 struct ethtool_ringparam *ring)
6428 struct dev_priv *priv = netdev_priv(dev);
6429 struct dev_info *hw_priv = priv->adapter;
6430 struct ksz_hw *hw = &hw_priv->hw;
6432 ring->tx_max_pending = (1 << 9);
6433 ring->tx_pending = hw->tx_desc_info.alloc;
6434 ring->rx_max_pending = (1 << 9);
6435 ring->rx_pending = hw->rx_desc_info.alloc;
6438 #define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6441 char string[ETH_GSTRING_LEN];
6442 } ethtool_stats_keys[STATS_LEN] = {
6443 { "rx_lo_priority_octets" },
6444 { "rx_hi_priority_octets" },
6445 { "rx_undersize_packets" },
6447 { "rx_oversize_packets" },
6449 { "rx_symbol_errors" },
6450 { "rx_crc_errors" },
6451 { "rx_align_errors" },
6452 { "rx_mac_ctrl_packets" },
6453 { "rx_pause_packets" },
6454 { "rx_bcast_packets" },
6455 { "rx_mcast_packets" },
6456 { "rx_ucast_packets" },
6457 { "rx_64_or_less_octet_packets" },
6458 { "rx_65_to_127_octet_packets" },
6459 { "rx_128_to_255_octet_packets" },
6460 { "rx_256_to_511_octet_packets" },
6461 { "rx_512_to_1023_octet_packets" },
6462 { "rx_1024_to_1522_octet_packets" },
6464 { "tx_lo_priority_octets" },
6465 { "tx_hi_priority_octets" },
6466 { "tx_late_collisions" },
6467 { "tx_pause_packets" },
6468 { "tx_bcast_packets" },
6469 { "tx_mcast_packets" },
6470 { "tx_ucast_packets" },
6472 { "tx_total_collisions" },
6473 { "tx_excessive_collisions" },
6474 { "tx_single_collisions" },
6475 { "tx_mult_collisions" },
6482 * netdev_get_strings - get statistics identity strings
6483 * @dev: Network device.
6484 * @stringset: String set identifier.
6485 * @buf: Buffer to store the strings.
6487 * This procedure returns the strings used to identify the statistics.
6489 static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6491 struct dev_priv *priv = netdev_priv(dev);
6492 struct dev_info *hw_priv = priv->adapter;
6493 struct ksz_hw *hw = &hw_priv->hw;
6495 if (ETH_SS_STATS == stringset)
6496 memcpy(buf, ðtool_stats_keys,
6497 ETH_GSTRING_LEN * hw->mib_cnt);
6501 * netdev_get_sset_count - get statistics size
6502 * @dev: Network device.
6503 * @sset: The statistics set number.
6505 * This function returns the size of the statistics to be reported.
6507 * Return size of the statistics to be reported.
6509 static int netdev_get_sset_count(struct net_device *dev, int sset)
6511 struct dev_priv *priv = netdev_priv(dev);
6512 struct dev_info *hw_priv = priv->adapter;
6513 struct ksz_hw *hw = &hw_priv->hw;
6524 * netdev_get_ethtool_stats - get network device statistics
6525 * @dev: Network device.
6526 * @stats: Ethtool statistics data structure.
6527 * @data: Buffer to store the statistics.
6529 * This procedure returns the statistics.
6531 static void netdev_get_ethtool_stats(struct net_device *dev,
6532 struct ethtool_stats *stats, u64 *data)
6534 struct dev_priv *priv = netdev_priv(dev);
6535 struct dev_info *hw_priv = priv->adapter;
6536 struct ksz_hw *hw = &hw_priv->hw;
6537 struct ksz_port *port = &priv->port;
6538 int n_stats = stats->n_stats;
6543 u64 counter[TOTAL_PORT_COUNTER_NUM];
6545 mutex_lock(&hw_priv->lock);
6546 n = SWITCH_PORT_NUM;
6547 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6548 if (media_connected == hw->port_mib[p].state) {
6549 hw_priv->counter[p].read = 1;
6551 /* Remember first port that requests read. */
6552 if (n == SWITCH_PORT_NUM)
6556 mutex_unlock(&hw_priv->lock);
6558 if (n < SWITCH_PORT_NUM)
6559 schedule_work(&hw_priv->mib_read);
6561 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6563 rc = wait_event_interruptible_timeout(
6564 hw_priv->counter[p].counter,
6565 2 == hw_priv->counter[p].read,
6568 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6570 rc = wait_event_interruptible_timeout(
6571 hw_priv->counter[p].counter,
6572 2 == hw_priv->counter[p].read,
6574 } else if (hw->port_mib[p].cnt_ptr) {
6575 rc = wait_event_interruptible_timeout(
6576 hw_priv->counter[p].counter,
6577 2 == hw_priv->counter[p].read,
6582 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6587 for (i = 0; i < n; i++)
6588 *data++ = counter[i];
6592 * netdev_get_rx_csum - get receive checksum support
6593 * @dev: Network device.
6595 * This function gets receive checksum support setting.
6597 * Return true if receive checksum is enabled; false otherwise.
6599 static u32 netdev_get_rx_csum(struct net_device *dev)
6601 struct dev_priv *priv = netdev_priv(dev);
6602 struct dev_info *hw_priv = priv->adapter;
6603 struct ksz_hw *hw = &hw_priv->hw;
6612 * netdev_set_rx_csum - set receive checksum support
6613 * @dev: Network device.
6614 * @data: Zero to disable receive checksum support.
6616 * This function sets receive checksum support setting.
6618 * Return 0 if successful; otherwise an error code.
6620 static int netdev_set_rx_csum(struct net_device *dev, u32 data)
6622 struct dev_priv *priv = netdev_priv(dev);
6623 struct dev_info *hw_priv = priv->adapter;
6624 struct ksz_hw *hw = &hw_priv->hw;
6625 u32 new_setting = hw->rx_cfg;
6629 (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP |
6633 ~(DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP |
6635 new_setting &= ~DMA_RX_CSUM_UDP;
6636 mutex_lock(&hw_priv->lock);
6637 if (new_setting != hw->rx_cfg) {
6638 hw->rx_cfg = new_setting;
6640 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6642 mutex_unlock(&hw_priv->lock);
6646 static struct ethtool_ops netdev_ethtool_ops = {
6647 .get_settings = netdev_get_settings,
6648 .set_settings = netdev_set_settings,
6649 .nway_reset = netdev_nway_reset,
6650 .get_link = netdev_get_link,
6651 .get_drvinfo = netdev_get_drvinfo,
6652 .get_regs_len = netdev_get_regs_len,
6653 .get_regs = netdev_get_regs,
6654 .get_wol = netdev_get_wol,
6655 .set_wol = netdev_set_wol,
6656 .get_msglevel = netdev_get_msglevel,
6657 .set_msglevel = netdev_set_msglevel,
6658 .get_eeprom_len = netdev_get_eeprom_len,
6659 .get_eeprom = netdev_get_eeprom,
6660 .set_eeprom = netdev_set_eeprom,
6661 .get_pauseparam = netdev_get_pauseparam,
6662 .set_pauseparam = netdev_set_pauseparam,
6663 .get_ringparam = netdev_get_ringparam,
6664 .get_strings = netdev_get_strings,
6665 .get_sset_count = netdev_get_sset_count,
6666 .get_ethtool_stats = netdev_get_ethtool_stats,
6667 .get_rx_csum = netdev_get_rx_csum,
6668 .set_rx_csum = netdev_set_rx_csum,
6669 .get_tx_csum = ethtool_op_get_tx_csum,
6670 .set_tx_csum = ethtool_op_set_tx_csum,
6671 .get_sg = ethtool_op_get_sg,
6672 .set_sg = ethtool_op_set_sg,
6676 * Hardware monitoring
6679 static void update_link(struct net_device *dev, struct dev_priv *priv,
6680 struct ksz_port *port)
6682 if (priv->media_state != port->linked->state) {
6683 priv->media_state = port->linked->state;
6684 if (netif_running(dev))
6685 set_media_state(dev, media_connected);
6689 static void mib_read_work(struct work_struct *work)
6691 struct dev_info *hw_priv =
6692 container_of(work, struct dev_info, mib_read);
6693 struct ksz_hw *hw = &hw_priv->hw;
6694 struct ksz_port_mib *mib;
6697 next_jiffies = jiffies;
6698 for (i = 0; i < hw->mib_port_cnt; i++) {
6699 mib = &hw->port_mib[i];
6701 /* Reading MIB counters or requested to read. */
6702 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6704 /* Need to process receive interrupt. */
6705 if (port_r_cnt(hw, i))
6707 hw_priv->counter[i].read = 0;
6709 /* Finish reading counters. */
6710 if (0 == mib->cnt_ptr) {
6711 hw_priv->counter[i].read = 2;
6712 wake_up_interruptible(
6713 &hw_priv->counter[i].counter);
6715 } else if (jiffies >= hw_priv->counter[i].time) {
6716 /* Only read MIB counters when the port is connected. */
6717 if (media_connected == mib->state)
6718 hw_priv->counter[i].read = 1;
6719 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6720 hw_priv->counter[i].time = next_jiffies;
6722 /* Port is just disconnected. */
6723 } else if (mib->link_down) {
6726 /* Read counters one last time after link is lost. */
6727 hw_priv->counter[i].read = 1;
6732 static void mib_monitor(unsigned long ptr)
6734 struct dev_info *hw_priv = (struct dev_info *) ptr;
6736 mib_read_work(&hw_priv->mib_read);
6738 /* This is used to verify Wake-on-LAN is working. */
6739 if (hw_priv->pme_wait) {
6740 if (hw_priv->pme_wait <= jiffies) {
6741 hw_clr_wol_pme_status(&hw_priv->hw);
6742 hw_priv->pme_wait = 0;
6744 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6746 /* PME is asserted. Wait 2 seconds to clear it. */
6747 hw_priv->pme_wait = jiffies + HZ * 2;
6750 ksz_update_timer(&hw_priv->mib_timer_info);
6754 * dev_monitor - periodic monitoring
6755 * @ptr: Network device pointer.
6757 * This routine is run in a kernel timer to monitor the network device.
6759 static void dev_monitor(unsigned long ptr)
6761 struct net_device *dev = (struct net_device *) ptr;
6762 struct dev_priv *priv = netdev_priv(dev);
6763 struct dev_info *hw_priv = priv->adapter;
6764 struct ksz_hw *hw = &hw_priv->hw;
6765 struct ksz_port *port = &priv->port;
6767 if (!(hw->features & LINK_INT_WORKING))
6768 port_get_link_speed(port);
6769 update_link(dev, priv, port);
6771 ksz_update_timer(&priv->monitor_timer_info);
6775 * Linux network device interface functions
6778 /* Driver exported variables */
6780 static int msg_enable;
6782 static char *macaddr = ":";
6783 static char *mac1addr = ":";
6786 * This enables multiple network device mode for KSZ8842, which contains a
6787 * switch with two physical ports. Some users like to take control of the
6788 * ports for running Spanning Tree Protocol. The driver will create an
6789 * additional eth? device for the other port.
6791 * Some limitations are the network devices cannot have different MTU and
6792 * multicast hash tables.
6794 static int multi_dev;
6797 * As most users select multiple network device mode to use Spanning Tree
6798 * Protocol, this enables a feature in which most unicast and multicast packets
6799 * are forwarded inside the switch and not passed to the host. Only packets
6800 * that need the host's attention are passed to it. This prevents the host
6801 * wasting CPU time to examine each and every incoming packets and do the
6802 * forwarding itself.
6804 * As the hack requires the private bridge header, the driver cannot compile
6805 * with just the kernel headers.
6807 * Enabling STP support also turns on multiple network device mode.
6812 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6813 * needs that. However, fast aging is used to flush the dynamic MAC table when
6814 * STP suport is enabled.
6816 static int fast_aging;
6819 * netdev_init - initalize network device.
6820 * @dev: Network device.
6822 * This function initializes the network device.
6824 * Return 0 if successful; otherwise an error code indicating failure.
6826 static int __init netdev_init(struct net_device *dev)
6828 struct dev_priv *priv = netdev_priv(dev);
6830 /* 500 ms timeout */
6831 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6834 /* 500 ms timeout */
6835 dev->watchdog_timeo = HZ / 2;
6837 dev->features |= NETIF_F_IP_CSUM;
6840 * Hardware does not really support IPv6 checksum generation, but
6841 * driver actually runs faster with this on. Refer IPV6_CSUM_GEN_HACK.
6843 dev->features |= NETIF_F_IPV6_CSUM;
6844 dev->features |= NETIF_F_SG;
6846 sema_init(&priv->proc_sem, 1);
6848 priv->mii_if.phy_id_mask = 0x1;
6849 priv->mii_if.reg_num_mask = 0x7;
6850 priv->mii_if.dev = dev;
6851 priv->mii_if.mdio_read = mdio_read;
6852 priv->mii_if.mdio_write = mdio_write;
6853 priv->mii_if.phy_id = priv->port.first_port + 1;
6855 priv->msg_enable = netif_msg_init(msg_enable,
6856 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6861 static const struct net_device_ops netdev_ops = {
6862 .ndo_init = netdev_init,
6863 .ndo_open = netdev_open,
6864 .ndo_stop = netdev_close,
6865 .ndo_get_stats = netdev_query_statistics,
6866 .ndo_start_xmit = netdev_tx,
6867 .ndo_tx_timeout = netdev_tx_timeout,
6868 .ndo_change_mtu = netdev_change_mtu,
6869 .ndo_set_mac_address = netdev_set_mac_address,
6870 .ndo_do_ioctl = netdev_ioctl,
6871 .ndo_set_rx_mode = netdev_set_rx_mode,
6872 #ifdef CONFIG_NET_POLL_CONTROLLER
6873 .ndo_poll_controller = netdev_netpoll,
6877 static void netdev_free(struct net_device *dev)
6879 if (dev->watchdog_timeo)
6880 unregister_netdev(dev);
6885 struct platform_info {
6886 struct dev_info dev_info;
6887 struct net_device *netdev[SWITCH_PORT_NUM];
6890 static int net_device_present;
6892 static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6899 i = j = num = got_num = 0;
6900 while (j < MAC_ADDR_LEN) {
6903 if ('0' <= macaddr[i] && macaddr[i] <= '9')
6904 num = num * 16 + macaddr[i] - '0';
6905 else if ('A' <= macaddr[i] && macaddr[i] <= 'F')
6906 num = num * 16 + 10 + macaddr[i] - 'A';
6907 else if ('a' <= macaddr[i] && macaddr[i] <= 'f')
6908 num = num * 16 + 10 + macaddr[i] - 'a';
6909 else if (':' == macaddr[i])
6918 if (MAIN_PORT == port) {
6919 hw_priv->hw.override_addr[j++] = (u8) num;
6920 hw_priv->hw.override_addr[5] +=
6923 hw_priv->hw.ksz_switch->other_addr[j++] =
6925 hw_priv->hw.ksz_switch->other_addr[5] +=
6932 if (MAC_ADDR_LEN == j) {
6933 if (MAIN_PORT == port)
6934 hw_priv->hw.mac_override = 1;
6938 #define KS884X_DMA_MASK (~0x0UL)
6940 static void read_other_addr(struct ksz_hw *hw)
6944 struct ksz_switch *sw = hw->ksz_switch;
6946 for (i = 0; i < 3; i++)
6947 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6948 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6949 sw->other_addr[5] = (u8) data[0];
6950 sw->other_addr[4] = (u8)(data[0] >> 8);
6951 sw->other_addr[3] = (u8) data[1];
6952 sw->other_addr[2] = (u8)(data[1] >> 8);
6953 sw->other_addr[1] = (u8) data[2];
6954 sw->other_addr[0] = (u8)(data[2] >> 8);
6958 #ifndef PCI_VENDOR_ID_MICREL_KS
6959 #define PCI_VENDOR_ID_MICREL_KS 0x16c6
6962 static int __init pcidev_init(struct pci_dev *pdev,
6963 const struct pci_device_id *id)
6965 struct net_device *dev;
6966 struct dev_priv *priv;
6967 struct dev_info *hw_priv;
6969 struct platform_info *info;
6970 struct ksz_port *port;
6971 unsigned long reg_base;
6972 unsigned long reg_len;
6979 char banner[sizeof(version)];
6980 struct ksz_switch *sw = NULL;
6982 result = pci_enable_device(pdev);
6988 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
6989 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
6992 reg_base = pci_resource_start(pdev, 0);
6993 reg_len = pci_resource_len(pdev, 0);
6994 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6997 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6999 pci_set_master(pdev);
7003 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
7005 goto pcidev_init_dev_err;
7007 hw_priv = &info->dev_info;
7008 hw_priv->pdev = pdev;
7012 hw->io = ioremap(reg_base, reg_len);
7014 goto pcidev_init_io_err;
7018 if (msg_enable & NETIF_MSG_PROBE)
7019 pr_alert("chip not detected\n");
7021 goto pcidev_init_alloc_err;
7024 snprintf(banner, sizeof(banner), "%s", version);
7025 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
7026 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
7027 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
7029 /* Assume device is KSZ8841. */
7033 hw->addr_list_size = 0;
7034 hw->mib_cnt = PORT_COUNTER_NUM;
7035 hw->mib_port_cnt = 1;
7037 /* KSZ8842 has a switch with multiple ports. */
7040 hw->overrides |= FAST_AGING;
7042 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
7044 /* Multiple network device interfaces are required. */
7046 hw->dev_count = SWITCH_PORT_NUM;
7047 hw->addr_list_size = SWITCH_PORT_NUM - 1;
7050 /* Single network device has multiple ports. */
7051 if (1 == hw->dev_count) {
7052 port_count = SWITCH_PORT_NUM;
7053 mib_port_count = SWITCH_PORT_NUM;
7055 hw->mib_port_cnt = TOTAL_PORT_NUM;
7056 hw->ksz_switch = kmalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7057 if (!hw->ksz_switch)
7058 goto pcidev_init_alloc_err;
7059 memset(hw->ksz_switch, 0, sizeof(struct ksz_switch));
7061 sw = hw->ksz_switch;
7063 for (i = 0; i < hw->mib_port_cnt; i++)
7064 hw->port_mib[i].mib_start = 0;
7066 hw->parent = hw_priv;
7068 /* Default MTU is 1500. */
7069 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
7071 if (ksz_alloc_mem(hw_priv))
7072 goto pcidev_init_mem_err;
7074 hw_priv->hw.id = net_device_present;
7076 spin_lock_init(&hw_priv->hwlock);
7077 mutex_init(&hw_priv->lock);
7079 /* tasklet is enabled. */
7080 tasklet_init(&hw_priv->rx_tasklet, rx_proc_task,
7081 (unsigned long) hw_priv);
7082 tasklet_init(&hw_priv->tx_tasklet, tx_proc_task,
7083 (unsigned long) hw_priv);
7085 /* tasklet_enable will decrement the atomic counter. */
7086 tasklet_disable(&hw_priv->rx_tasklet);
7087 tasklet_disable(&hw_priv->tx_tasklet);
7089 for (i = 0; i < TOTAL_PORT_NUM; i++)
7090 init_waitqueue_head(&hw_priv->counter[i].counter);
7092 if (macaddr[0] != ':')
7093 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
7095 /* Read MAC address and initialize override address if not overrided. */
7098 /* Multiple device interfaces mode requires a second MAC address. */
7099 if (hw->dev_count > 1) {
7100 memcpy(sw->other_addr, hw->override_addr, MAC_ADDR_LEN);
7101 read_other_addr(hw);
7102 if (mac1addr[0] != ':')
7103 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
7110 hw_priv->wol_support = WOL_SUPPORT;
7111 hw_priv->wol_enable = 0;
7114 INIT_WORK(&hw_priv->mib_read, mib_read_work);
7116 /* 500 ms timeout */
7117 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
7118 mib_monitor, hw_priv);
7120 for (i = 0; i < hw->dev_count; i++) {
7121 dev = alloc_etherdev(sizeof(struct dev_priv));
7123 goto pcidev_init_reg_err;
7124 info->netdev[i] = dev;
7126 priv = netdev_priv(dev);
7127 priv->adapter = hw_priv;
7128 priv->id = net_device_present++;
7131 port->port_cnt = port_count;
7132 port->mib_port_cnt = mib_port_count;
7133 port->first_port = i;
7134 port->flow_ctrl = PHY_FLOW_CTRL;
7137 port->linked = &hw->port_info[port->first_port];
7139 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7140 hw->port_info[pi].port_id = pi;
7141 hw->port_info[pi].pdev = dev;
7142 hw->port_info[pi].state = media_disconnected;
7145 dev->mem_start = (unsigned long) hw->io;
7146 dev->mem_end = dev->mem_start + reg_len - 1;
7147 dev->irq = pdev->irq;
7149 memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7152 memcpy(dev->dev_addr, sw->other_addr,
7154 if (!memcmp(sw->other_addr, hw->override_addr,
7156 dev->dev_addr[5] += port->first_port;
7159 dev->netdev_ops = &netdev_ops;
7160 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7161 if (register_netdev(dev))
7162 goto pcidev_init_reg_err;
7163 port_set_power_saving(port, true);
7166 pci_dev_get(hw_priv->pdev);
7167 pci_set_drvdata(pdev, info);
7170 pcidev_init_reg_err:
7171 for (i = 0; i < hw->dev_count; i++) {
7172 if (info->netdev[i]) {
7173 netdev_free(info->netdev[i]);
7174 info->netdev[i] = NULL;
7178 pcidev_init_mem_err:
7179 ksz_free_mem(hw_priv);
7180 kfree(hw->ksz_switch);
7182 pcidev_init_alloc_err:
7188 pcidev_init_dev_err:
7189 release_mem_region(reg_base, reg_len);
7194 static void pcidev_exit(struct pci_dev *pdev)
7197 struct platform_info *info = pci_get_drvdata(pdev);
7198 struct dev_info *hw_priv = &info->dev_info;
7200 pci_set_drvdata(pdev, NULL);
7202 release_mem_region(pci_resource_start(pdev, 0),
7203 pci_resource_len(pdev, 0));
7204 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7205 if (info->netdev[i])
7206 netdev_free(info->netdev[i]);
7209 iounmap(hw_priv->hw.io);
7210 ksz_free_mem(hw_priv);
7211 kfree(hw_priv->hw.ksz_switch);
7212 pci_dev_put(hw_priv->pdev);
7217 static int pcidev_resume(struct pci_dev *pdev)
7220 struct platform_info *info = pci_get_drvdata(pdev);
7221 struct dev_info *hw_priv = &info->dev_info;
7222 struct ksz_hw *hw = &hw_priv->hw;
7224 pci_set_power_state(pdev, PCI_D0);
7225 pci_restore_state(pdev);
7226 pci_enable_wake(pdev, PCI_D0, 0);
7228 if (hw_priv->wol_enable)
7229 hw_cfg_wol_pme(hw, 0);
7230 for (i = 0; i < hw->dev_count; i++) {
7231 if (info->netdev[i]) {
7232 struct net_device *dev = info->netdev[i];
7234 if (netif_running(dev)) {
7236 netif_device_attach(dev);
7243 static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
7246 struct platform_info *info = pci_get_drvdata(pdev);
7247 struct dev_info *hw_priv = &info->dev_info;
7248 struct ksz_hw *hw = &hw_priv->hw;
7250 /* Need to find a way to retrieve the device IP address. */
7251 u8 net_addr[] = { 192, 168, 1, 1 };
7253 for (i = 0; i < hw->dev_count; i++) {
7254 if (info->netdev[i]) {
7255 struct net_device *dev = info->netdev[i];
7257 if (netif_running(dev)) {
7258 netif_device_detach(dev);
7263 if (hw_priv->wol_enable) {
7264 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7265 hw_cfg_wol_pme(hw, 1);
7268 pci_save_state(pdev);
7269 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
7270 pci_set_power_state(pdev, pci_choose_state(pdev, state));
7275 static char pcidev_name[] = "ksz884xp";
7277 static struct pci_device_id pcidev_table[] = {
7278 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7280 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7285 MODULE_DEVICE_TABLE(pci, pcidev_table);
7287 static struct pci_driver pci_device_driver = {
7289 .suspend = pcidev_suspend,
7290 .resume = pcidev_resume,
7292 .name = pcidev_name,
7293 .id_table = pcidev_table,
7294 .probe = pcidev_init,
7295 .remove = pcidev_exit
7298 static int __init ksz884x_init_module(void)
7300 return pci_register_driver(&pci_device_driver);
7303 static void __exit ksz884x_cleanup_module(void)
7305 pci_unregister_driver(&pci_device_driver);
7308 module_init(ksz884x_init_module);
7309 module_exit(ksz884x_cleanup_module);
7311 MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7312 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7313 MODULE_LICENSE("GPL");
7315 module_param_named(message, msg_enable, int, 0);
7316 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7318 module_param(macaddr, charp, 0);
7319 module_param(mac1addr, charp, 0);
7320 module_param(fast_aging, int, 0);
7321 module_param(multi_dev, int, 0);
7322 module_param(stp, int, 0);
7323 MODULE_PARM_DESC(macaddr, "MAC address");
7324 MODULE_PARM_DESC(mac1addr, "Second MAC address");
7325 MODULE_PARM_DESC(fast_aging, "Fast aging");
7326 MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7327 MODULE_PARM_DESC(stp, "STP support");