1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #ifndef _IXGBE_TYPE_H_
30 #define _IXGBE_TYPE_H_
32 #include <linux/types.h>
35 #define IXGBE_INTEL_VENDOR_ID 0x8086
38 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
39 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
40 #define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8
41 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
42 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
43 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
45 /* General Registers */
46 #define IXGBE_CTRL 0x00000
47 #define IXGBE_STATUS 0x00008
48 #define IXGBE_CTRL_EXT 0x00018
49 #define IXGBE_ESDP 0x00020
50 #define IXGBE_EODSDP 0x00028
51 #define IXGBE_LEDCTL 0x00200
52 #define IXGBE_FRTIMER 0x00048
53 #define IXGBE_TCPTIMER 0x0004C
56 #define IXGBE_EEC 0x10010
57 #define IXGBE_EERD 0x10014
58 #define IXGBE_FLA 0x1001C
59 #define IXGBE_EEMNGCTL 0x10110
60 #define IXGBE_EEMNGDATA 0x10114
61 #define IXGBE_FLMNGCTL 0x10118
62 #define IXGBE_FLMNGDATA 0x1011C
63 #define IXGBE_FLMNGCNT 0x10120
64 #define IXGBE_FLOP 0x1013C
65 #define IXGBE_GRC 0x10200
67 /* Interrupt Registers */
68 #define IXGBE_EICR 0x00800
69 #define IXGBE_EICS 0x00808
70 #define IXGBE_EIMS 0x00880
71 #define IXGBE_EIMC 0x00888
72 #define IXGBE_EIAC 0x00810
73 #define IXGBE_EIAM 0x00890
74 #define IXGBE_EITR(_i) (0x00820 + ((_i) * 4)) /* 0x820-0x86c */
75 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
76 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
77 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
78 #define IXGBE_PBACL 0x11068
79 #define IXGBE_GPIE 0x00898
81 /* Flow Control Registers */
82 #define IXGBE_PFCTOP 0x03008
83 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
84 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
85 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
86 #define IXGBE_FCRTV 0x032A0
87 #define IXGBE_TFCS 0x0CE00
89 /* Receive DMA Registers */
90 #define IXGBE_RDBAL(_i) (0x01000 + ((_i) * 0x40)) /* 64 of each (0-63)*/
91 #define IXGBE_RDBAH(_i) (0x01004 + ((_i) * 0x40))
92 #define IXGBE_RDLEN(_i) (0x01008 + ((_i) * 0x40))
93 #define IXGBE_RDH(_i) (0x01010 + ((_i) * 0x40))
94 #define IXGBE_RDT(_i) (0x01018 + ((_i) * 0x40))
95 #define IXGBE_RXDCTL(_i) (0x01028 + ((_i) * 0x40))
96 #define IXGBE_RSCCTL(_i) (0x0102C + ((_i) * 0x40))
97 #define IXGBE_SRRCTL(_i) (0x02100 + ((_i) * 4))
98 /* array of 16 (0x02100-0x0213C) */
99 #define IXGBE_DCA_RXCTRL(_i) (0x02200 + ((_i) * 4))
100 /* array of 16 (0x02200-0x0223C) */
101 #define IXGBE_RDRXCTL 0x02F00
102 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
103 /* 8 of these 0x03C00 - 0x03C1C */
104 #define IXGBE_RXCTRL 0x03000
105 #define IXGBE_DROPEN 0x03D04
106 #define IXGBE_RXPBSIZE_SHIFT 10
108 /* Receive Registers */
109 #define IXGBE_RXCSUM 0x05000
110 #define IXGBE_RFCTL 0x05008
111 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
112 /* Multicast Table Array - 128 entries */
113 #define IXGBE_RAL(_i) (0x05400 + ((_i) * 8)) /* 16 of these (0-15) */
114 #define IXGBE_RAH(_i) (0x05404 + ((_i) * 8)) /* 16 of these (0-15) */
115 #define IXGBE_PSRTYPE 0x05480
116 /* 0x5480-0x54BC Packet split receive type */
117 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
118 /* array of 4096 1-bit vlan filters */
119 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
120 /*array of 4096 4-bit vlan vmdq indicies */
121 #define IXGBE_FCTRL 0x05080
122 #define IXGBE_VLNCTRL 0x05088
123 #define IXGBE_MCSTCTRL 0x05090
124 #define IXGBE_MRQC 0x05818
125 #define IXGBE_VMD_CTL 0x0581C
126 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
127 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
128 #define IXGBE_IMIRVP 0x05AC0
129 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
130 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
132 /* Transmit DMA registers */
133 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))/* 32 of these (0-31)*/
134 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
135 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
136 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
137 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
138 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
139 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
140 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
141 #define IXGBE_DTXCTL 0x07E00
142 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
143 /* there are 16 of these (0-15) */
144 #define IXGBE_TIPG 0x0CB00
145 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04))
146 /* there are 8 of these */
147 #define IXGBE_MNGTXMAP 0x0CD10
148 #define IXGBE_TIPG_FIBER_DEFAULT 3
149 #define IXGBE_TXPBSIZE_SHIFT 10
151 /* Wake up registers */
152 #define IXGBE_WUC 0x05800
153 #define IXGBE_WUFC 0x05808
154 #define IXGBE_WUS 0x05810
155 #define IXGBE_IPAV 0x05838
156 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
157 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
158 #define IXGBE_WUPL 0x05900
159 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
160 #define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
162 /* Music registers */
163 #define IXGBE_RMCS 0x03D00
164 #define IXGBE_DPMCS 0x07F40
165 #define IXGBE_PDPMCS 0x0CD00
166 #define IXGBE_RUPPBMR 0x050A0
167 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
168 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
169 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
170 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
171 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
172 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
174 /* Stats registers */
175 #define IXGBE_CRCERRS 0x04000
176 #define IXGBE_ILLERRC 0x04004
177 #define IXGBE_ERRBC 0x04008
178 #define IXGBE_MSPDC 0x04010
179 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
180 #define IXGBE_MLFC 0x04034
181 #define IXGBE_MRFC 0x04038
182 #define IXGBE_RLEC 0x04040
183 #define IXGBE_LXONTXC 0x03F60
184 #define IXGBE_LXONRXC 0x0CF60
185 #define IXGBE_LXOFFTXC 0x03F68
186 #define IXGBE_LXOFFRXC 0x0CF68
187 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
188 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
189 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
190 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
191 #define IXGBE_PRC64 0x0405C
192 #define IXGBE_PRC127 0x04060
193 #define IXGBE_PRC255 0x04064
194 #define IXGBE_PRC511 0x04068
195 #define IXGBE_PRC1023 0x0406C
196 #define IXGBE_PRC1522 0x04070
197 #define IXGBE_GPRC 0x04074
198 #define IXGBE_BPRC 0x04078
199 #define IXGBE_MPRC 0x0407C
200 #define IXGBE_GPTC 0x04080
201 #define IXGBE_GORCL 0x04088
202 #define IXGBE_GORCH 0x0408C
203 #define IXGBE_GOTCL 0x04090
204 #define IXGBE_GOTCH 0x04094
205 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
206 #define IXGBE_RUC 0x040A4
207 #define IXGBE_RFC 0x040A8
208 #define IXGBE_ROC 0x040AC
209 #define IXGBE_RJC 0x040B0
210 #define IXGBE_MNGPRC 0x040B4
211 #define IXGBE_MNGPDC 0x040B8
212 #define IXGBE_MNGPTC 0x0CF90
213 #define IXGBE_TORL 0x040C0
214 #define IXGBE_TORH 0x040C4
215 #define IXGBE_TPR 0x040D0
216 #define IXGBE_TPT 0x040D4
217 #define IXGBE_PTC64 0x040D8
218 #define IXGBE_PTC127 0x040DC
219 #define IXGBE_PTC255 0x040E0
220 #define IXGBE_PTC511 0x040E4
221 #define IXGBE_PTC1023 0x040E8
222 #define IXGBE_PTC1522 0x040EC
223 #define IXGBE_MPTC 0x040F0
224 #define IXGBE_BPTC 0x040F4
225 #define IXGBE_XEC 0x04120
227 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
228 #define IXGBE_TQSMR(_i) (0x07300 + ((_i) * 4)) /* 8 of these */
230 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
231 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
232 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
233 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
236 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
237 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
238 #define IXGBE_MANC 0x05820
239 #define IXGBE_MFVAL 0x05824
240 #define IXGBE_MANC2H 0x05860
241 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
242 #define IXGBE_MIPAF 0x058B0
243 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
244 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
245 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
247 /* ARC Subsystem registers */
248 #define IXGBE_HICR 0x15F00
249 #define IXGBE_FWSTS 0x15F0C
250 #define IXGBE_HSMC0R 0x15F04
251 #define IXGBE_HSMC1R 0x15F08
252 #define IXGBE_SWSR 0x15F10
253 #define IXGBE_HFDR 0x15FE8
254 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
256 /* PCI-E registers */
257 #define IXGBE_GCR 0x11000
258 #define IXGBE_GTV 0x11004
259 #define IXGBE_FUNCTAG 0x11008
260 #define IXGBE_GLT 0x1100C
261 #define IXGBE_GSCL_1 0x11010
262 #define IXGBE_GSCL_2 0x11014
263 #define IXGBE_GSCL_3 0x11018
264 #define IXGBE_GSCL_4 0x1101C
265 #define IXGBE_GSCN_0 0x11020
266 #define IXGBE_GSCN_1 0x11024
267 #define IXGBE_GSCN_2 0x11028
268 #define IXGBE_GSCN_3 0x1102C
269 #define IXGBE_FACTPS 0x10150
270 #define IXGBE_PCIEANACTL 0x11040
271 #define IXGBE_SWSM 0x10140
272 #define IXGBE_FWSM 0x10148
273 #define IXGBE_GSSR 0x10160
274 #define IXGBE_MREVID 0x11064
275 #define IXGBE_DCA_ID 0x11070
276 #define IXGBE_DCA_CTRL 0x11074
278 /* Diagnostic Registers */
279 #define IXGBE_RDSTATCTL 0x02C20
280 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
281 #define IXGBE_RDHMPN 0x02F08
282 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
283 #define IXGBE_RDPROBE 0x02F20
284 #define IXGBE_TDSTATCTL 0x07C20
285 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
286 #define IXGBE_TDHMPN 0x07F08
287 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
288 #define IXGBE_TDPROBE 0x07F20
289 #define IXGBE_TXBUFCTRL 0x0C600
290 #define IXGBE_TXBUFDATA0 0x0C610
291 #define IXGBE_TXBUFDATA1 0x0C614
292 #define IXGBE_TXBUFDATA2 0x0C618
293 #define IXGBE_TXBUFDATA3 0x0C61C
294 #define IXGBE_RXBUFCTRL 0x03600
295 #define IXGBE_RXBUFDATA0 0x03610
296 #define IXGBE_RXBUFDATA1 0x03614
297 #define IXGBE_RXBUFDATA2 0x03618
298 #define IXGBE_RXBUFDATA3 0x0361C
299 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
300 #define IXGBE_RFVAL 0x050A4
301 #define IXGBE_MDFTC1 0x042B8
302 #define IXGBE_MDFTC2 0x042C0
303 #define IXGBE_MDFTFIFO1 0x042C4
304 #define IXGBE_MDFTFIFO2 0x042C8
305 #define IXGBE_MDFTS 0x042CC
306 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
307 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
308 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
309 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
310 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
311 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
312 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
313 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
314 #define IXGBE_PCIEECCCTL 0x1106C
315 #define IXGBE_PBTXECC 0x0C300
316 #define IXGBE_PBRXECC 0x03300
317 #define IXGBE_GHECCR 0x110B0
320 #define IXGBE_PCS1GCFIG 0x04200
321 #define IXGBE_PCS1GLCTL 0x04208
322 #define IXGBE_PCS1GLSTA 0x0420C
323 #define IXGBE_PCS1GDBG0 0x04210
324 #define IXGBE_PCS1GDBG1 0x04214
325 #define IXGBE_PCS1GANA 0x04218
326 #define IXGBE_PCS1GANLP 0x0421C
327 #define IXGBE_PCS1GANNP 0x04220
328 #define IXGBE_PCS1GANLPNP 0x04224
329 #define IXGBE_HLREG0 0x04240
330 #define IXGBE_HLREG1 0x04244
331 #define IXGBE_PAP 0x04248
332 #define IXGBE_MACA 0x0424C
333 #define IXGBE_APAE 0x04250
334 #define IXGBE_ARD 0x04254
335 #define IXGBE_AIS 0x04258
336 #define IXGBE_MSCA 0x0425C
337 #define IXGBE_MSRWD 0x04260
338 #define IXGBE_MLADD 0x04264
339 #define IXGBE_MHADD 0x04268
340 #define IXGBE_TREG 0x0426C
341 #define IXGBE_PCSS1 0x04288
342 #define IXGBE_PCSS2 0x0428C
343 #define IXGBE_XPCSS 0x04290
344 #define IXGBE_SERDESC 0x04298
345 #define IXGBE_MACS 0x0429C
346 #define IXGBE_AUTOC 0x042A0
347 #define IXGBE_LINKS 0x042A4
348 #define IXGBE_AUTOC2 0x042A8
349 #define IXGBE_AUTOC3 0x042AC
350 #define IXGBE_ANLP1 0x042B0
351 #define IXGBE_ANLP2 0x042B4
352 #define IXGBE_ATLASCTL 0x04800
354 /* RDRXCTL Bit Masks */
355 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
356 #define IXGBE_RDRXCTL_MVMEN 0x00000020
357 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
360 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
361 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
362 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
365 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
367 /* MHADD Bit Masks */
368 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
369 #define IXGBE_MHADD_MFS_SHIFT 16
371 /* Extended Device Control */
372 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
373 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
374 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
376 /* Direct Cache Access (DCA) definitions */
377 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
378 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
380 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
381 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
383 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
384 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
385 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
386 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
388 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
389 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
390 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */
391 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
394 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
395 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
396 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
397 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
398 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
399 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
400 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
401 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
402 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
403 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
404 #define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
405 #define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
406 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
407 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
408 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
409 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
410 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
411 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
413 /* MSRWD bit masks */
414 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
415 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
416 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
417 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
419 /* Atlas registers */
420 #define IXGBE_ATLAS_PDN_LPBK 0x24
421 #define IXGBE_ATLAS_PDN_10G 0xB
422 #define IXGBE_ATLAS_PDN_1G 0xC
423 #define IXGBE_ATLAS_PDN_AN 0xD
425 /* Atlas bit masks */
426 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
427 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
428 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
429 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
430 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
432 /* Device Type definitions for new protocol MDIO commands */
433 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
434 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
435 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
436 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
437 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
439 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
440 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
441 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
442 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
443 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
444 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
446 #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
447 #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
448 #define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
449 #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
450 #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
451 #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
452 #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Abilty Reg */
453 #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
454 #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
456 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
457 #define IXGBE_MAX_PHY_ADDR 32
460 #define TN1010_PHY_ID 0x00A19410
461 #define QT2022_PHY_ID 0x0043A400
463 /* General purpose Interrupt Enable */
464 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
465 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
466 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
467 #define IXGBE_GPIE_EIAME 0x40000000
468 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
470 /* Transmit Flow Control status */
471 #define IXGBE_TFCS_TXOFF 0x00000001
472 #define IXGBE_TFCS_TXOFF0 0x00000100
473 #define IXGBE_TFCS_TXOFF1 0x00000200
474 #define IXGBE_TFCS_TXOFF2 0x00000400
475 #define IXGBE_TFCS_TXOFF3 0x00000800
476 #define IXGBE_TFCS_TXOFF4 0x00001000
477 #define IXGBE_TFCS_TXOFF5 0x00002000
478 #define IXGBE_TFCS_TXOFF6 0x00004000
479 #define IXGBE_TFCS_TXOFF7 0x00008000
482 #define IXGBE_TCPTIMER_KS 0x00000100
483 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
484 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
485 #define IXGBE_TCPTIMER_LOOP 0x00000800
486 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
488 /* HLREG0 Bit Masks */
489 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
490 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
491 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
492 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
493 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
494 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
495 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
496 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
497 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
498 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
499 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
500 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
501 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
502 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
503 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
505 /* VMD_CTL bitmasks */
506 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
507 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
509 /* RDHMPN and TDHMPN bitmasks */
510 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
511 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
512 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
513 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
514 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
515 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
517 /* Receive Checksum Control */
518 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
519 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
521 /* FCRTL Bit Masks */
522 #define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
523 #define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
526 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
529 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recylce Mode enable */
530 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
531 #define IXGBE_RMCS_RAC 0x00000004
532 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
533 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
534 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
535 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
537 /* Interrupt register bitmasks */
539 /* Extended Interrupt Cause Read */
540 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
541 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
542 #define IXGBE_EICR_MNG 0x00400000 /* Managability Event Interrupt */
543 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
544 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
545 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
546 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
548 /* Extended Interrupt Cause Set */
549 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
550 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
551 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
552 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
553 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
554 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
555 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
556 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
558 /* Extended Interrupt Mask Set */
559 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
560 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
561 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
562 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
563 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
564 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
565 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
567 /* Extended Interrupt Mask Clear */
568 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
569 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
570 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
571 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
572 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */
573 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
574 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
576 #define IXGBE_EIMS_ENABLE_MASK (\
577 IXGBE_EIMS_RTX_QUEUE | \
579 IXGBE_EIMS_TCP_TIMER | \
582 /* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */
583 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
584 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
585 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
586 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
587 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
588 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
589 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
590 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
591 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
592 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
594 /* Interrupt clear mask */
595 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
597 /* Interrupt Vector Allocation Registers */
598 #define IXGBE_IVAR_REG_NUM 25
599 #define IXGBE_IVAR_TXRX_ENTRY 96
600 #define IXGBE_IVAR_RX_ENTRY 64
601 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
602 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
603 #define IXGBE_IVAR_TX_ENTRY 32
605 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
606 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
608 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
610 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
612 /* VLAN Control Bit Masks */
613 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
614 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
615 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
616 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
617 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
619 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
621 /* STATUS Bit Masks */
622 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
623 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
625 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
626 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
629 #define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
630 #define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
631 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
632 #define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
634 /* LEDCTL Bit Masks */
635 #define IXGBE_LED_IVRT_BASE 0x00000040
636 #define IXGBE_LED_BLINK_BASE 0x00000080
637 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
638 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
639 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
640 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
641 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
642 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
645 #define IXGBE_LED_LINK_UP 0x0
646 #define IXGBE_LED_LINK_10G 0x1
647 #define IXGBE_LED_MAC 0x2
648 #define IXGBE_LED_FILTER 0x3
649 #define IXGBE_LED_LINK_ACTIVE 0x4
650 #define IXGBE_LED_LINK_1G 0x5
651 #define IXGBE_LED_ON 0xE
652 #define IXGBE_LED_OFF 0xF
654 /* AUTOC Bit Masks */
655 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
656 #define IXGBE_AUTOC_KX_SUPP 0x40000000
657 #define IXGBE_AUTOC_PAUSE 0x30000000
658 #define IXGBE_AUTOC_RF 0x08000000
659 #define IXGBE_AUTOC_PD_TMR 0x06000000
660 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
661 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
662 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
663 #define IXGBE_AUTOC_AN_RESTART 0x00001000
664 #define IXGBE_AUTOC_FLU 0x00000001
665 #define IXGBE_AUTOC_LMS_SHIFT 13
666 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
667 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
668 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
669 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
670 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
671 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
672 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
674 #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
675 #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
676 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
677 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
678 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
679 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
680 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
681 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
682 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
684 /* LINKS Bit Masks */
685 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
686 #define IXGBE_LINKS_UP 0x40000000
687 #define IXGBE_LINKS_SPEED 0x20000000
688 #define IXGBE_LINKS_MODE 0x18000000
689 #define IXGBE_LINKS_RX_MODE 0x06000000
690 #define IXGBE_LINKS_TX_MODE 0x01800000
691 #define IXGBE_LINKS_XGXS_EN 0x00400000
692 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
693 #define IXGBE_LINKS_1G_AN_EN 0x00100000
694 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
695 #define IXGBE_LINKS_1G_SYNC 0x00040000
696 #define IXGBE_LINKS_10G_ALIGN 0x00020000
697 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
698 #define IXGBE_LINKS_TL_FAULT 0x00001000
699 #define IXGBE_LINKS_SIGNAL 0x00000F00
701 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
702 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
704 /* SW Semaphore Register bitmasks */
705 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
706 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
707 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
709 /* GSSR definitions */
710 #define IXGBE_GSSR_EEP_SM 0x0001
711 #define IXGBE_GSSR_PHY0_SM 0x0002
712 #define IXGBE_GSSR_PHY1_SM 0x0004
713 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
714 #define IXGBE_GSSR_FLASH_SM 0x0010
717 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
718 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
719 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
720 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
721 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
722 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
723 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
724 #define IXGBE_EEC_FWE_SHIFT 4
725 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
726 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
727 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
728 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
729 /* EEPROM Addressing bits based on type (0-small, 1-large) */
730 #define IXGBE_EEC_ADDR_SIZE 0x00000400
731 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
733 #define IXGBE_EEC_SIZE_SHIFT 11
734 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
735 #define IXGBE_EEPROM_OPCODE_BITS 8
737 /* Checksum and EEPROM pointers */
738 #define IXGBE_EEPROM_CHECKSUM 0x3F
739 #define IXGBE_EEPROM_SUM 0xBABA
740 #define IXGBE_PCIE_ANALOG_PTR 0x03
741 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
742 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
743 #define IXGBE_PCIE_GENERAL_PTR 0x06
744 #define IXGBE_PCIE_CONFIG0_PTR 0x07
745 #define IXGBE_PCIE_CONFIG1_PTR 0x08
746 #define IXGBE_CORE0_PTR 0x09
747 #define IXGBE_CORE1_PTR 0x0A
748 #define IXGBE_MAC0_PTR 0x0B
749 #define IXGBE_MAC1_PTR 0x0C
750 #define IXGBE_CSR0_CONFIG_PTR 0x0D
751 #define IXGBE_CSR1_CONFIG_PTR 0x0E
752 #define IXGBE_FW_PTR 0x0F
753 #define IXGBE_PBANUM0_PTR 0x15
754 #define IXGBE_PBANUM1_PTR 0x16
756 /* EEPROM Commands - SPI */
757 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
758 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
759 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
760 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
761 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
762 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
763 /* EEPROM reset Write Enbale latch */
764 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
765 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
766 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
767 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
768 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
769 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
771 /* EEPROM Read Register */
772 #define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */
773 #define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */
774 #define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */
775 #define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */
777 #define IXGBE_ETH_LENGTH_OF_ADDRESS 6
779 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
780 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
783 #ifndef IXGBE_EERD_ATTEMPTS
784 /* Number of 5 microseconds we wait for EERD read to complete */
785 #define IXGBE_EERD_ATTEMPTS 100000
789 #define IXGBE_PCI_LINK_STATUS 0xB2
790 #define IXGBE_PCI_LINK_WIDTH 0x3F0
791 #define IXGBE_PCI_LINK_WIDTH_1 0x10
792 #define IXGBE_PCI_LINK_WIDTH_2 0x20
793 #define IXGBE_PCI_LINK_WIDTH_4 0x40
794 #define IXGBE_PCI_LINK_WIDTH_8 0x80
795 #define IXGBE_PCI_LINK_SPEED 0xF
796 #define IXGBE_PCI_LINK_SPEED_2500 0x1
797 #define IXGBE_PCI_LINK_SPEED_5000 0x2
799 /* Number of 100 microseconds we wait for PCI Express master disable */
800 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
803 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
805 /* Check whether address is multicast. This is little-endian specific check.*/
806 #define IXGBE_IS_MULTICAST(Address) \
807 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
809 /* Check whether an address is broadcast. */
810 #define IXGBE_IS_BROADCAST(Address) \
811 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
812 (((u8 *)(Address))[1] == ((u8)0xff)))
815 #define IXGBE_RAH_VIND_MASK 0x003C0000
816 #define IXGBE_RAH_VIND_SHIFT 18
817 #define IXGBE_RAH_AV 0x80000000
819 /* Header split receive */
820 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
821 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
822 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
823 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
824 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
825 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
826 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
827 #define IXGBE_RFCTL_NFS_VER_2 0
828 #define IXGBE_RFCTL_NFS_VER_3 1
829 #define IXGBE_RFCTL_NFS_VER_4 2
830 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
831 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
832 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
833 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
834 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
836 /* Transmit Config masks */
837 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
838 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
839 /* Enable short packet padding to 64 bytes */
840 #define IXGBE_TX_PAD_ENABLE 0x00000400
841 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
842 /* This allows for 16K packets + 4k for vlan */
843 #define IXGBE_MAX_FRAME_SZ 0x40040000
845 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
846 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq. # write-back enable */
848 /* Receive Config masks */
849 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
850 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
851 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
853 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
854 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
855 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
856 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
857 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
858 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
859 /* Receive Priority Flow Control Enbale */
860 #define IXGBE_FCTRL_RPFCE 0x00004000
861 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
863 /* Multiple Receive Queue Control */
864 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
865 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
866 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
867 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
868 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
869 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
870 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
871 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
872 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
873 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
874 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
876 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
877 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
878 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
879 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
880 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
881 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
882 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
883 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
884 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
886 /* Receive Descriptor bit definitions */
887 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
888 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
889 #define IXGBE_RXD_STAT_IXSM 0x04 /* Ignore checksum */
890 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
891 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
892 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
893 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
894 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
895 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
896 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
897 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
898 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
899 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
900 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
901 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
902 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
903 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
904 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
905 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
906 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
907 #define IXGBE_RXDADV_HBO 0x00800000
908 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
909 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
910 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
911 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
912 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
913 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
914 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
915 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
916 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
917 #define IXGBE_RXD_PRI_SHIFT 13
918 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
919 #define IXGBE_RXD_CFI_SHIFT 12
921 /* SRRCTL bit definitions */
922 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
923 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
924 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
925 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
926 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
927 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
928 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
929 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
931 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
932 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
934 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
935 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
936 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
937 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
938 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
939 #define IXGBE_RXDADV_SPH 0x8000
941 /* RSS Hash results */
942 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
943 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
944 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
945 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
946 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
947 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
948 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
949 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
950 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
951 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
953 /* RSS Packet Types as indicated in the receive descriptor. */
954 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
955 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
956 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
957 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
958 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
959 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
960 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
961 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
962 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
964 /* Masks to determine if packets should be dropped due to frame errors */
965 #define IXGBE_RXD_ERR_FRAME_ERR_MASK (\
969 IXGBE_RXD_ERR_OSE | \
972 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK (\
973 IXGBE_RXDADV_ERR_CE | \
974 IXGBE_RXDADV_ERR_LE | \
975 IXGBE_RXDADV_ERR_PE | \
976 IXGBE_RXDADV_ERR_OSE | \
977 IXGBE_RXDADV_ERR_USE)
979 /* Multicast bit mask */
980 #define IXGBE_MCSTCTRL_MFE 0x4
982 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
983 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
984 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
985 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
987 /* Vlan-specific macros */
988 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
989 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
990 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
991 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
993 /* Transmit Descriptor - Legacy */
994 struct ixgbe_legacy_tx_desc {
995 u64 buffer_addr; /* Address of the descriptor's data buffer */
999 __le16 length; /* Data buffer length */
1000 u8 cso; /* Checksum offset */
1001 u8 cmd; /* Descriptor control */
1007 u8 status; /* Descriptor status */
1008 u8 css; /* Checksum start */
1014 /* Transmit Descriptor - Advanced */
1015 union ixgbe_adv_tx_desc {
1017 __le64 buffer_addr; /* Address of descriptor's data buf */
1018 __le32 cmd_type_len;
1019 __le32 olinfo_status;
1022 __le64 rsvd; /* Reserved */
1028 /* Receive Descriptor - Legacy */
1029 struct ixgbe_legacy_rx_desc {
1030 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1031 __le16 length; /* Length of data DMAed into data buffer */
1032 __le16 csum; /* Packet checksum */
1033 u8 status; /* Descriptor status */
1034 u8 errors; /* Descriptor Errors */
1038 /* Receive Descriptor - Advanced */
1039 union ixgbe_adv_rx_desc {
1041 __le64 pkt_addr; /* Packet buffer address */
1042 __le64 hdr_addr; /* Header buffer address */
1049 __le16 pkt_info; /* RSS type, Packet type */
1050 __le16 hdr_info; /* Split Header, header len */
1054 __le32 rss; /* RSS Hash */
1056 __le16 ip_id; /* IP id */
1057 __le16 csum; /* Packet Checksum */
1062 __le32 status_error; /* ext status/error */
1063 __le16 length; /* Packet length */
1064 __le16 vlan; /* VLAN tag */
1066 } wb; /* writeback */
1069 /* Context descriptors */
1070 struct ixgbe_adv_tx_context_desc {
1071 __le32 vlan_macip_lens;
1073 __le32 type_tucmd_mlhl;
1074 __le32 mss_l4len_idx;
1077 /* Adv Transmit Descriptor Config Masks */
1078 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */
1079 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1080 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1081 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1082 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1083 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
1084 #define IXGBE_ADVTXD_DCMD_RDMA 0x04000000 /* RDMA */
1085 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
1086 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
1087 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1088 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1089 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1090 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
1091 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */
1092 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1093 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
1094 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1095 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
1096 IXGBE_ADVTXD_POPTS_SHIFT)
1097 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
1098 IXGBE_ADVTXD_POPTS_SHIFT)
1099 #define IXGBE_ADVTXD_POPTS_EOM 0x00000400 /* Enable L bit-RDMA DDP hdr */
1100 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1101 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1102 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1103 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
1104 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1105 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1106 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1107 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1108 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1109 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1110 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1111 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1112 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
1113 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1114 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1117 #define IXGBE_LINK_SPEED_UNKNOWN 0
1118 #define IXGBE_LINK_SPEED_100_FULL 0x0008
1119 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1120 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1123 enum ixgbe_eeprom_type {
1124 ixgbe_eeprom_uninitialized = 0,
1126 ixgbe_eeprom_none /* No NVM support */
1129 enum ixgbe_mac_type {
1130 ixgbe_mac_unknown = 0,
1135 enum ixgbe_phy_type {
1136 ixgbe_phy_unknown = 0,
1142 enum ixgbe_media_type {
1143 ixgbe_media_type_unknown = 0,
1144 ixgbe_media_type_fiber,
1145 ixgbe_media_type_copper,
1146 ixgbe_media_type_backplane
1149 /* Flow Control Settings */
1150 enum ixgbe_fc_type {
1158 struct ixgbe_addr_filter_info {
1161 u32 mc_addr_in_rar_count;
1163 u32 overflow_promisc;
1164 bool user_set_promisc;
1167 /* Flow control parameters */
1168 struct ixgbe_fc_info {
1169 u32 high_water; /* Flow Control High-water */
1170 u32 low_water; /* Flow Control Low-water */
1171 u16 pause_time; /* Flow Control Pause timer */
1172 bool send_xon; /* Flow control send XON */
1173 bool strict_ieee; /* Strict IEEE mode */
1174 enum ixgbe_fc_type type; /* Type of flow control */
1175 enum ixgbe_fc_type original_type;
1178 /* Statistics counters collected by the MAC */
1179 struct ixgbe_hw_stats {
1237 /* forward declaration */
1240 /* iterator type for walking multicast address lists */
1241 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
1244 struct ixgbe_mac_operations {
1245 s32 (*reset)(struct ixgbe_hw *);
1246 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1247 s32 (*setup_link)(struct ixgbe_hw *);
1248 s32 (*check_link)(struct ixgbe_hw *, u32 *, bool *, bool);
1249 s32 (*setup_link_speed)(struct ixgbe_hw *, u32, bool, bool);
1250 s32 (*get_link_settings)(struct ixgbe_hw *, u32 *, bool *);
1253 struct ixgbe_phy_operations {
1254 s32 (*setup_link)(struct ixgbe_hw *);
1255 s32 (*check_link)(struct ixgbe_hw *, u32 *, bool *);
1256 s32 (*setup_link_speed)(struct ixgbe_hw *, u32, bool, bool);
1259 struct ixgbe_mac_info {
1260 struct ixgbe_mac_operations ops;
1261 enum ixgbe_mac_type type;
1262 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1263 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1267 u32 num_rar_entries;
1270 u32 link_attach_type;
1271 u32 link_mode_select;
1272 bool link_settings_loaded;
1275 struct ixgbe_eeprom_info {
1276 enum ixgbe_eeprom_type type;
1281 struct ixgbe_phy_info {
1282 struct ixgbe_phy_operations ops;
1284 enum ixgbe_phy_type type;
1288 enum ixgbe_media_type media_type;
1289 u32 autoneg_advertised;
1290 bool autoneg_wait_to_complete;
1294 enum ixgbe_mac_type mac;
1295 s32 (*get_invariants)(struct ixgbe_hw *);
1296 struct ixgbe_mac_operations *mac_ops;
1300 u8 __iomem *hw_addr;
1302 struct ixgbe_mac_info mac;
1303 struct ixgbe_addr_filter_info addr_ctrl;
1304 struct ixgbe_fc_info fc;
1305 struct ixgbe_phy_info phy;
1306 struct ixgbe_eeprom_info eeprom;
1309 u16 subsystem_device_id;
1310 u16 subsystem_vendor_id;
1312 bool adapter_stopped;
1316 #define IXGBE_ERR_EEPROM -1
1317 #define IXGBE_ERR_EEPROM_CHECKSUM -2
1318 #define IXGBE_ERR_PHY -3
1319 #define IXGBE_ERR_CONFIG -4
1320 #define IXGBE_ERR_PARAM -5
1321 #define IXGBE_ERR_MAC_TYPE -6
1322 #define IXGBE_ERR_UNKNOWN_PHY -7
1323 #define IXGBE_ERR_LINK_SETUP -8
1324 #define IXGBE_ERR_ADAPTER_STOPPED -9
1325 #define IXGBE_ERR_INVALID_MAC_ADDR -10
1326 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
1327 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1328 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1329 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1330 #define IXGBE_ERR_RESET_FAILED -15
1331 #define IXGBE_ERR_SWFW_SYNC -16
1332 #define IXGBE_ERR_PHY_ADDR_INVALID -17
1333 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1335 #endif /* _IXGBE_TYPE_H_ */