SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/types.h>
  30 #include <linux/module.h>
  31 #include <linux/pci.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/vmalloc.h>
  34 #include <linux/string.h>
  35 #include <linux/in.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43
  44 #include "ixgbe.h"
  45 #include "ixgbe_common.h"
  46
  47 char ixgbe_driver_name[] = "ixgbe";
  48 static const char ixgbe_driver_string[] =
  49         "Intel(R) 10 Gigabit PCI Express Network Driver";
  50
  51 #define DRV_VERSION "1.3.18-k4"
  52 const char ixgbe_driver_version[] = DRV_VERSION;
  53 static const char ixgbe_copyright[] =
  54          "Copyright (c) 1999-2007 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598]                   = &ixgbe_82598_info,
  58 };
  59
  60 /* ixgbe_pci_tbl - PCI Device ID Table
  61  *
  62  * Wildcard entries (PCI_ANY_ID) should come last
  63  * Last entry must be all 0s
  64  *
  65  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  66  *   Class, Class Mask, private data (not used) }
  67  */
  68 static struct pci_device_id ixgbe_pci_tbl[] = {
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  78          board_82598 },
  79
  80         /* required last entry */
  81         {0, }
  82 };
  83 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
  84
  85 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
  86 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
  87                             void *p);
  88 static struct notifier_block dca_notifier = {
  89         .notifier_call = ixgbe_notify_dca,
  90         .next          = NULL,
  91         .priority      = 0
  92 };
  93 #endif
  94
  95 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  96 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
  97 MODULE_LICENSE("GPL");
  98 MODULE_VERSION(DRV_VERSION);
  99
 100 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 101
 102 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 103 {
 104         u32 ctrl_ext;
 105
 106         /* Let firmware take over control of h/w */
 107         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 108         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 109                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 110 }
 111
 112 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 113 {
 114         u32 ctrl_ext;
 115
 116         /* Let firmware know the driver has taken over */
 117         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 118         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 119                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 120 }
 121
 122 #ifdef DEBUG
 123 /**
 124  * ixgbe_get_hw_dev_name - return device name string
 125  * used by hardware layer to print debugging information
 126  **/
 127 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
 128 {
 129         struct ixgbe_adapter *adapter = hw->back;
 130         struct net_device *netdev = adapter->netdev;
 131         return netdev->name;
 132 }
 133 #endif
 134
 135 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
 136                            u8 msix_vector)
 137 {
 138         u32 ivar, index;
 139
 140         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 141         index = (int_alloc_entry >> 2) & 0x1F;
 142         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
 143         ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
 144         ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
 145         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
 146 }
 147
 148 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 149                                              struct ixgbe_tx_buffer
 150                                              *tx_buffer_info)
 151 {
 152         if (tx_buffer_info->dma) {
 153                 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
 154                                tx_buffer_info->length, PCI_DMA_TODEVICE);
 155                 tx_buffer_info->dma = 0;
 156         }
 157         if (tx_buffer_info->skb) {
 158                 dev_kfree_skb_any(tx_buffer_info->skb);
 159                 tx_buffer_info->skb = NULL;
 160         }
 161         /* tx_buffer_info must be completely set up in the transmit path */
 162 }
 163
 164 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 165                                        struct ixgbe_ring *tx_ring,
 166                                        unsigned int eop)
 167 {
 168         struct ixgbe_hw *hw = &adapter->hw;
 169         u32 head, tail;
 170
 171         /* Detect a transmit hang in hardware, this serializes the
 172          * check with the clearing of time_stamp and movement of eop */
 173         head = IXGBE_READ_REG(hw, tx_ring->head);
 174         tail = IXGBE_READ_REG(hw, tx_ring->tail);
 175         adapter->detect_tx_hung = false;
 176         if ((head != tail) &&
 177             tx_ring->tx_buffer_info[eop].time_stamp &&
 178             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 179             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 180                 /* detected Tx unit hang */
 181                 union ixgbe_adv_tx_desc *tx_desc;
 182                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 183                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 184                         "  Tx Queue             <%d>\n"
 185                         "  TDH, TDT             <%x>, <%x>\n"
 186                         "  next_to_use          <%x>\n"
 187                         "  next_to_clean        <%x>\n"
 188                         "tx_buffer_info[next_to_clean]\n"
 189                         "  time_stamp           <%lx>\n"
 190                         "  jiffies              <%lx>\n",
 191                         tx_ring->queue_index,
 192                         head, tail,
 193                         tx_ring->next_to_use, eop,
 194                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 195                 return true;
 196         }
 197
 198         return false;
 199 }
 200
 201 #define IXGBE_MAX_TXD_PWR       14
 202 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 203
 204 /* Tx Descriptors needed, worst case */
 205 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 206                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 207 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 208         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1)   /* for context */
 209
 210 #define GET_TX_HEAD_FROM_RING(ring) (\
 211         *(volatile u32 *) \
 212         ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
 213 static void ixgbe_tx_timeout(struct net_device *netdev);
 214
 215 /**
 216  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 217  * @adapter: board private structure
 218  * @tx_ring: tx ring to clean
 219  **/
 220 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 221                                struct ixgbe_ring *tx_ring)
 222 {
 223         union ixgbe_adv_tx_desc *tx_desc;
 224         struct ixgbe_tx_buffer *tx_buffer_info;
 225         struct net_device *netdev = adapter->netdev;
 226         struct sk_buff *skb;
 227         unsigned int i;
 228         u32 head, oldhead;
 229         unsigned int count = 0;
 230         unsigned int total_bytes = 0, total_packets = 0;
 231
 232         rmb();
 233         head = GET_TX_HEAD_FROM_RING(tx_ring);
 234         head = le32_to_cpu(head);
 235         i = tx_ring->next_to_clean;
 236         while (1) {
 237                 while (i != head) {
 238                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 239                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 240                         skb = tx_buffer_info->skb;
 241
 242                         if (skb) {
 243                                 unsigned int segs, bytecount;
 244
 245                                 /* gso_segs is currently only valid for tcp */
 246                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 247                                 /* multiply data chunks by size of headers */
 248                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 249                                             skb->len;
 250                                 total_packets += segs;
 251                                 total_bytes += bytecount;
 252                         }
 253
 254                         ixgbe_unmap_and_free_tx_resource(adapter,
 255                                                          tx_buffer_info);
 256
 257                         i++;
 258                         if (i == tx_ring->count)
 259                                 i = 0;
 260
 261                         count++;
 262                         if (count == tx_ring->count)
 263                                 goto done_cleaning;
 264                 }
 265                 oldhead = head;
 266                 rmb();
 267                 head = GET_TX_HEAD_FROM_RING(tx_ring);
 268                 head = le32_to_cpu(head);
 269                 if (head == oldhead)
 270                         goto done_cleaning;
 271         } /* while (1) */
 272
 273 done_cleaning:
 274         tx_ring->next_to_clean = i;
 275
 276 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 277         if (unlikely(count && netif_carrier_ok(netdev) &&
 278                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 279                 /* Make sure that anybody stopping the queue after this
 280                  * sees the new next_to_clean.
 281                  */
 282                 smp_mb();
 283                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 284                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 285                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 286                         ++adapter->restart_queue;
 287                 }
 288         }
 289
 290         if (adapter->detect_tx_hung) {
 291                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 292                         /* schedule immediate reset if we believe we hung */
 293                         DPRINTK(PROBE, INFO,
 294                                 "tx hang %d detected, resetting adapter\n",
 295                                 adapter->tx_timeout_count + 1);
 296                         ixgbe_tx_timeout(adapter->netdev);
 297                 }
 298         }
 299
 300         /* re-arm the interrupt */
 301         if ((total_packets >= tx_ring->work_limit) ||
 302             (count == tx_ring->count))
 303                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
 304
 305         tx_ring->total_bytes += total_bytes;
 306         tx_ring->total_packets += total_packets;
 307         tx_ring->stats.bytes += total_bytes;
 308         tx_ring->stats.packets += total_packets;
 309         adapter->net_stats.tx_bytes += total_bytes;
 310         adapter->net_stats.tx_packets += total_packets;
 311         return (total_packets ? true : false);
 312 }
 313
 314 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
 315 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 316                                 struct ixgbe_ring *rx_ring)
 317 {
 318         u32 rxctrl;
 319         int cpu = get_cpu();
 320         int q = rx_ring - adapter->rx_ring;
 321
 322         if (rx_ring->cpu != cpu) {
 323                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 324                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 325                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 326                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 327                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 328                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 329                 rx_ring->cpu = cpu;
 330         }
 331         put_cpu();
 332 }
 333
 334 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 335                                 struct ixgbe_ring *tx_ring)
 336 {
 337         u32 txctrl;
 338         int cpu = get_cpu();
 339         int q = tx_ring - adapter->tx_ring;
 340
 341         if (tx_ring->cpu != cpu) {
 342                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 343                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 344                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 345                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 346                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 347                 tx_ring->cpu = cpu;
 348         }
 349         put_cpu();
 350 }
 351
 352 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 353 {
 354         int i;
 355
 356         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 357                 return;
 358
 359         for (i = 0; i < adapter->num_tx_queues; i++) {
 360                 adapter->tx_ring[i].cpu = -1;
 361                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 362         }
 363         for (i = 0; i < adapter->num_rx_queues; i++) {
 364                 adapter->rx_ring[i].cpu = -1;
 365                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 366         }
 367 }
 368
 369 static int __ixgbe_notify_dca(struct device *dev, void *data)
 370 {
 371         struct net_device *netdev = dev_get_drvdata(dev);
 372         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 373         unsigned long event = *(unsigned long *)data;
 374
 375         switch (event) {
 376         case DCA_PROVIDER_ADD:
 377                 /* if we're already enabled, don't do it again */
 378                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 379                         break;
 380                 /* Always use CB2 mode, difference is masked
 381                  * in the CB driver. */
 382                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 383                 if (dca_add_requester(dev) == 0) {
 384                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 385                         ixgbe_setup_dca(adapter);
 386                         break;
 387                 }
 388                 /* Fall Through since DCA is disabled. */
 389         case DCA_PROVIDER_REMOVE:
 390                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 391                         dca_remove_requester(dev);
 392                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 393                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 394                 }
 395                 break;
 396         }
 397
 398         return 0;
 399 }
 400
 401 #endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
 402 /**
 403  * ixgbe_receive_skb - Send a completed packet up the stack
 404  * @adapter: board private structure
 405  * @skb: packet to send up
 406  * @status: hardware indication of status of receive
 407  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 408  * @rx_desc: rx descriptor
 409  **/
 410 static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
 411                               struct sk_buff *skb, u8 status,
 412                               struct ixgbe_ring *ring,
 413                               union ixgbe_adv_rx_desc *rx_desc)
 414 {
 415         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 416         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 417
 418         if (adapter->netdev->features & NETIF_F_LRO &&
 419             skb->ip_summed == CHECKSUM_UNNECESSARY) {
 420                 if (adapter->vlgrp && is_vlan)
 421                         lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
 422                                                      adapter->vlgrp, tag,
 423                                                      rx_desc);
 424                 else
 425                         lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
 426                 ring->lro_used = true;
 427         } else {
 428                 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 429                         if (adapter->vlgrp && is_vlan)
 430                                 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
 431                         else
 432                                 netif_receive_skb(skb);
 433                 } else {
 434                         if (adapter->vlgrp && is_vlan)
 435                                 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 436                         else
 437                                 netif_rx(skb);
 438                 }
 439         }
 440 }
 441
 442 /**
 443  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 444  * @adapter: address of board private structure
 445  * @status_err: hardware indication of status of receive
 446  * @skb: skb currently being received and modified
 447  **/
 448 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 449                                      u32 status_err, struct sk_buff *skb)
 450 {
 451         skb->ip_summed = CHECKSUM_NONE;
 452
 453         /* Rx csum disabled */
 454         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 455                 return;
 456
 457         /* if IP and error */
 458         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 459             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 460                 adapter->hw_csum_rx_error++;
 461                 return;
 462         }
 463
 464         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 465                 return;
 466
 467         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 468                 adapter->hw_csum_rx_error++;
 469                 return;
 470         }
 471
 472         /* It must be a TCP or UDP packet with a valid checksum */
 473         skb->ip_summed = CHECKSUM_UNNECESSARY;
 474         adapter->hw_csum_rx_good++;
 475 }
 476
 477 /**
 478  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 479  * @adapter: address of board private structure
 480  **/
 481 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 482                                    struct ixgbe_ring *rx_ring,
 483                                    int cleaned_count)
 484 {
 485         struct net_device *netdev = adapter->netdev;
 486         struct pci_dev *pdev = adapter->pdev;
 487         union ixgbe_adv_rx_desc *rx_desc;
 488         struct ixgbe_rx_buffer *bi;
 489         unsigned int i;
 490         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 491
 492         i = rx_ring->next_to_use;
 493         bi = &rx_ring->rx_buffer_info[i];
 494
 495         while (cleaned_count--) {
 496                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 497
 498                 if (!bi->page_dma &&
 499                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 500                         if (!bi->page) {
 501                                 bi->page = alloc_page(GFP_ATOMIC);
 502                                 if (!bi->page) {
 503                                         adapter->alloc_rx_page_failed++;
 504                                         goto no_buffers;
 505                                 }
 506                                 bi->page_offset = 0;
 507                         } else {
 508                                 /* use a half page if we're re-using */
 509                                 bi->page_offset ^= (PAGE_SIZE / 2);
 510                         }
 511
 512                         bi->page_dma = pci_map_page(pdev, bi->page,
 513                                                     bi->page_offset,
 514                                                     (PAGE_SIZE / 2),
 515                                                     PCI_DMA_FROMDEVICE);
 516                 }
 517
 518                 if (!bi->skb) {
 519                         struct sk_buff *skb = netdev_alloc_skb(netdev, bufsz);
 520
 521                         if (!skb) {
 522                                 adapter->alloc_rx_buff_failed++;
 523                                 goto no_buffers;
 524                         }
 525
 526                         /*
 527                          * Make buffer alignment 2 beyond a 16 byte boundary
 528                          * this will result in a 16 byte aligned IP header after
 529                          * the 14 byte MAC header is removed
 530                          */
 531                         skb_reserve(skb, NET_IP_ALIGN);
 532
 533                         bi->skb = skb;
 534                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 535                                                  PCI_DMA_FROMDEVICE);
 536                 }
 537                 /* Refresh the desc even if buffer_addrs didn't change because
 538                  * each write-back erases this info. */
 539                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 540                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 541                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 542                 } else {
 543                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 544                 }
 545
 546                 i++;
 547                 if (i == rx_ring->count)
 548                         i = 0;
 549                 bi = &rx_ring->rx_buffer_info[i];
 550         }
 551
 552 no_buffers:
 553         if (rx_ring->next_to_use != i) {
 554                 rx_ring->next_to_use = i;
 555                 if (i-- == 0)
 556                         i = (rx_ring->count - 1);
 557
 558                 /*
 559                  * Force memory writes to complete before letting h/w
 560                  * know there are new descriptors to fetch.  (Only
 561                  * applicable for weak-ordered memory model archs,
 562                  * such as IA-64).
 563                  */
 564                 wmb();
 565                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
 566         }
 567 }
 568
 569 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 570 {
 571         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 572 }
 573
 574 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 575 {
 576         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 577 }
 578
 579 static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
 580                                struct ixgbe_ring *rx_ring,
 581                                int *work_done, int work_to_do)
 582 {
 583         struct net_device *netdev = adapter->netdev;
 584         struct pci_dev *pdev = adapter->pdev;
 585         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 586         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 587         struct sk_buff *skb;
 588         unsigned int i;
 589         u32 len, staterr;
 590         u16 hdr_info;
 591         bool cleaned = false;
 592         int cleaned_count = 0;
 593         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 594
 595         i = rx_ring->next_to_clean;
 596         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 597         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 598         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 599
 600         while (staterr & IXGBE_RXD_STAT_DD) {
 601                 u32 upper_len = 0;
 602                 if (*work_done >= work_to_do)
 603                         break;
 604                 (*work_done)++;
 605
 606                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 607                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 608                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 609                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 610                         if (hdr_info & IXGBE_RXDADV_SPH)
 611                                 adapter->rx_hdr_split++;
 612                         if (len > IXGBE_RX_HDR_SIZE)
 613                                 len = IXGBE_RX_HDR_SIZE;
 614                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 615                 } else {
 616                         len = le16_to_cpu(rx_desc->wb.upper.length);
 617                 }
 618
 619                 cleaned = true;
 620                 skb = rx_buffer_info->skb;
 621                 prefetch(skb->data - NET_IP_ALIGN);
 622                 rx_buffer_info->skb = NULL;
 623
 624                 if (len && !skb_shinfo(skb)->nr_frags) {
 625                         pci_unmap_single(pdev, rx_buffer_info->dma,
 626                                          rx_ring->rx_buf_len + NET_IP_ALIGN,
 627                                          PCI_DMA_FROMDEVICE);
 628                         skb_put(skb, len);
 629                 }
 630
 631                 if (upper_len) {
 632                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 633                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 634                         rx_buffer_info->page_dma = 0;
 635                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 636                                            rx_buffer_info->page,
 637                                            rx_buffer_info->page_offset,
 638                                            upper_len);
 639
 640                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 641                             (page_count(rx_buffer_info->page) != 1))
 642                                 rx_buffer_info->page = NULL;
 643                         else
 644                                 get_page(rx_buffer_info->page);
 645
 646                         skb->len += upper_len;
 647                         skb->data_len += upper_len;
 648                         skb->truesize += upper_len;
 649                 }
 650
 651                 i++;
 652                 if (i == rx_ring->count)
 653                         i = 0;
 654                 next_buffer = &rx_ring->rx_buffer_info[i];
 655
 656                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 657                 prefetch(next_rxd);
 658
 659                 cleaned_count++;
 660                 if (staterr & IXGBE_RXD_STAT_EOP) {
 661                         rx_ring->stats.packets++;
 662                         rx_ring->stats.bytes += skb->len;
 663                 } else {
 664                         rx_buffer_info->skb = next_buffer->skb;
 665                         rx_buffer_info->dma = next_buffer->dma;
 666                         next_buffer->skb = skb;
 667                         next_buffer->dma = 0;
 668                         adapter->non_eop_descs++;
 669                         goto next_desc;
 670                 }
 671
 672                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 673                         dev_kfree_skb_irq(skb);
 674                         goto next_desc;
 675                 }
 676
 677                 ixgbe_rx_checksum(adapter, staterr, skb);
 678
 679                 /* probably a little skewed due to removing CRC */
 680                 total_rx_bytes += skb->len;
 681                 total_rx_packets++;
 682
 683                 skb->protocol = eth_type_trans(skb, netdev);
 684                 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
 685                 netdev->last_rx = jiffies;
 686
 687 next_desc:
 688                 rx_desc->wb.upper.status_error = 0;
 689
 690                 /* return some buffers to hardware, one at a time is too slow */
 691                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 692                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 693                         cleaned_count = 0;
 694                 }
 695
 696                 /* use prefetched values */
 697                 rx_desc = next_rxd;
 698                 rx_buffer_info = next_buffer;
 699
 700                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 701         }
 702
 703         if (rx_ring->lro_used) {
 704                 lro_flush_all(&rx_ring->lro_mgr);
 705                 rx_ring->lro_used = false;
 706         }
 707
 708         rx_ring->next_to_clean = i;
 709         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 710
 711         if (cleaned_count)
 712                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 713
 714         rx_ring->total_packets += total_rx_packets;
 715         rx_ring->total_bytes += total_rx_bytes;
 716         adapter->net_stats.rx_bytes += total_rx_bytes;
 717         adapter->net_stats.rx_packets += total_rx_packets;
 718
 719         return cleaned;
 720 }
 721
 722 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 723 /**
 724  * ixgbe_configure_msix - Configure MSI-X hardware
 725  * @adapter: board private structure
 726  *
 727  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 728  * interrupts.
 729  **/
 730 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 731 {
 732         struct ixgbe_q_vector *q_vector;
 733         int i, j, q_vectors, v_idx, r_idx;
 734         u32 mask;
 735
 736         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 737
 738         /* Populate the IVAR table and set the ITR values to the
 739          * corresponding register.
 740          */
 741         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 742                 q_vector = &adapter->q_vector[v_idx];
 743                 /* XXX for_each_bit(...) */
 744                 r_idx = find_first_bit(q_vector->rxr_idx,
 745                                       adapter->num_rx_queues);
 746
 747                 for (i = 0; i < q_vector->rxr_count; i++) {
 748                         j = adapter->rx_ring[r_idx].reg_idx;
 749                         ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
 750                         r_idx = find_next_bit(q_vector->rxr_idx,
 751                                               adapter->num_rx_queues,
 752                                               r_idx + 1);
 753                 }
 754                 r_idx = find_first_bit(q_vector->txr_idx,
 755                                        adapter->num_tx_queues);
 756
 757                 for (i = 0; i < q_vector->txr_count; i++) {
 758                         j = adapter->tx_ring[r_idx].reg_idx;
 759                         ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
 760                         r_idx = find_next_bit(q_vector->txr_idx,
 761                                               adapter->num_tx_queues,
 762                                               r_idx + 1);
 763                 }
 764
 765                 /* if this is a tx only vector halve the interrupt rate */
 766                 if (q_vector->txr_count && !q_vector->rxr_count)
 767                         q_vector->eitr = (adapter->eitr_param >> 1);
 768                 else
 769                         /* rx only */
 770                         q_vector->eitr = adapter->eitr_param;
 771
 772                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 773                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 774         }
 775
 776         ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
 777         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 778
 779         /* set up to autoclear timer, and the vectors */
 780         mask = IXGBE_EIMS_ENABLE_MASK;
 781         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 782         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 783 }
 784
 785 enum latency_range {
 786         lowest_latency = 0,
 787         low_latency = 1,
 788         bulk_latency = 2,
 789         latency_invalid = 255
 790 };
 791
 792 /**
 793  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 794  * @adapter: pointer to adapter
 795  * @eitr: eitr setting (ints per sec) to give last timeslice
 796  * @itr_setting: current throttle rate in ints/second
 797  * @packets: the number of packets during this measurement interval
 798  * @bytes: the number of bytes during this measurement interval
 799  *
 800  *      Stores a new ITR value based on packets and byte
 801  *      counts during the last interrupt.  The advantage of per interrupt
 802  *      computation is faster updates and more accurate ITR for the current
 803  *      traffic pattern.  Constants in this function were computed
 804  *      based on theoretical maximum wire speed and thresholds were set based
 805  *      on testing data as well as attempting to minimize response time
 806  *      while increasing bulk throughput.
 807  *      this functionality is controlled by the InterruptThrottleRate module
 808  *      parameter (see ixgbe_param.c)
 809  **/
 810 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 811                            u32 eitr, u8 itr_setting,
 812                            int packets, int bytes)
 813 {
 814         unsigned int retval = itr_setting;
 815         u32 timepassed_us;
 816         u64 bytes_perint;
 817
 818         if (packets == 0)
 819                 goto update_itr_done;
 820
 821
 822         /* simple throttlerate management
 823          *    0-20MB/s lowest (100000 ints/s)
 824          *   20-100MB/s low   (20000 ints/s)
 825          *  100-1249MB/s bulk (8000 ints/s)
 826          */
 827         /* what was last interrupt timeslice? */
 828         timepassed_us = 1000000/eitr;
 829         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 830
 831         switch (itr_setting) {
 832         case lowest_latency:
 833                 if (bytes_perint > adapter->eitr_low)
 834                         retval = low_latency;
 835                 break;
 836         case low_latency:
 837                 if (bytes_perint > adapter->eitr_high)
 838                         retval = bulk_latency;
 839                 else if (bytes_perint <= adapter->eitr_low)
 840                         retval = lowest_latency;
 841                 break;
 842         case bulk_latency:
 843                 if (bytes_perint <= adapter->eitr_high)
 844                         retval = low_latency;
 845                 break;
 846         }
 847
 848 update_itr_done:
 849         return retval;
 850 }
 851
 852 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 853 {
 854         struct ixgbe_adapter *adapter = q_vector->adapter;
 855         struct ixgbe_hw *hw = &adapter->hw;
 856         u32 new_itr;
 857         u8 current_itr, ret_itr;
 858         int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
 859                               sizeof(struct ixgbe_q_vector);
 860         struct ixgbe_ring *rx_ring, *tx_ring;
 861
 862         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 863         for (i = 0; i < q_vector->txr_count; i++) {
 864                 tx_ring = &(adapter->tx_ring[r_idx]);
 865                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 866                                            q_vector->tx_itr,
 867                                            tx_ring->total_packets,
 868                                            tx_ring->total_bytes);
 869                 /* if the result for this queue would decrease interrupt
 870                  * rate for this vector then use that result */
 871                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
 872                                     q_vector->tx_itr - 1 : ret_itr);
 873                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 874                                       r_idx + 1);
 875         }
 876
 877         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 878         for (i = 0; i < q_vector->rxr_count; i++) {
 879                 rx_ring = &(adapter->rx_ring[r_idx]);
 880                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 881                                            q_vector->rx_itr,
 882                                            rx_ring->total_packets,
 883                                            rx_ring->total_bytes);
 884                 /* if the result for this queue would decrease interrupt
 885                  * rate for this vector then use that result */
 886                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
 887                                     q_vector->rx_itr - 1 : ret_itr);
 888                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 889                                       r_idx + 1);
 890         }
 891
 892         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
 893
 894         switch (current_itr) {
 895         /* counts and packets in update_itr are dependent on these numbers */
 896         case lowest_latency:
 897                 new_itr = 100000;
 898                 break;
 899         case low_latency:
 900                 new_itr = 20000; /* aka hwitr = ~200 */
 901                 break;
 902         case bulk_latency:
 903         default:
 904                 new_itr = 8000;
 905                 break;
 906         }
 907
 908         if (new_itr != q_vector->eitr) {
 909                 u32 itr_reg;
 910                 /* do an exponential smoothing */
 911                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
 912                 q_vector->eitr = new_itr;
 913                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
 914                 /* must write high and low 16 bits to reset counter */
 915                 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
 916                         itr_reg);
 917                 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
 918         }
 919
 920         return;
 921 }
 922
 923
 924 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
 925 {
 926         struct ixgbe_hw *hw = &adapter->hw;
 927
 928         adapter->lsc_int++;
 929         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
 930         adapter->link_check_timeout = jiffies;
 931         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 932                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
 933                 schedule_work(&adapter->watchdog_task);
 934         }
 935 }
 936
 937 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
 938 {
 939         struct net_device *netdev = data;
 940         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 941         struct ixgbe_hw *hw = &adapter->hw;
 942         u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
 943
 944         if (eicr & IXGBE_EICR_LSC)
 945                 ixgbe_check_lsc(adapter);
 946
 947         if (!test_bit(__IXGBE_DOWN, &adapter->state))
 948                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
 949
 950         return IRQ_HANDLED;
 951 }
 952
 953 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
 954 {
 955         struct ixgbe_q_vector *q_vector = data;
 956         struct ixgbe_adapter  *adapter = q_vector->adapter;
 957         struct ixgbe_ring     *tx_ring;
 958         int i, r_idx;
 959
 960         if (!q_vector->txr_count)
 961                 return IRQ_HANDLED;
 962
 963         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 964         for (i = 0; i < q_vector->txr_count; i++) {
 965                 tx_ring = &(adapter->tx_ring[r_idx]);
 966 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
 967                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 968                         ixgbe_update_tx_dca(adapter, tx_ring);
 969 #endif
 970                 tx_ring->total_bytes = 0;
 971                 tx_ring->total_packets = 0;
 972                 ixgbe_clean_tx_irq(adapter, tx_ring);
 973                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 974                                       r_idx + 1);
 975         }
 976
 977         return IRQ_HANDLED;
 978 }
 979
 980 /**
 981  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
 982  * @irq: unused
 983  * @data: pointer to our q_vector struct for this interrupt vector
 984  **/
 985 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
 986 {
 987         struct ixgbe_q_vector *q_vector = data;
 988         struct ixgbe_adapter  *adapter = q_vector->adapter;
 989         struct ixgbe_ring  *rx_ring;
 990         int r_idx;
 991         int i;
 992
 993         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 994         for (i = 0;  i < q_vector->rxr_count; i++) {
 995                 rx_ring = &(adapter->rx_ring[r_idx]);
 996                 rx_ring->total_bytes = 0;
 997                 rx_ring->total_packets = 0;
 998                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 999                                       r_idx + 1);
1000         }
1001
1002         if (!q_vector->rxr_count)
1003                 return IRQ_HANDLED;
1004
1005         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1006         rx_ring = &(adapter->rx_ring[r_idx]);
1007         /* disable interrupts on this vector only */
1008         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1009         netif_rx_schedule(adapter->netdev, &q_vector->napi);
1010
1011         return IRQ_HANDLED;
1012 }
1013
1014 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1015 {
1016         ixgbe_msix_clean_rx(irq, data);
1017         ixgbe_msix_clean_tx(irq, data);
1018
1019         return IRQ_HANDLED;
1020 }
1021
1022 /**
1023  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1024  * @napi: napi struct with our devices info in it
1025  * @budget: amount of work driver is allowed to do this pass, in packets
1026  *
1027  * This function is optimized for cleaning one queue only on a single
1028  * q_vector!!!
1029  **/
1030 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1031 {
1032         struct ixgbe_q_vector *q_vector =
1033                                container_of(napi, struct ixgbe_q_vector, napi);
1034         struct ixgbe_adapter *adapter = q_vector->adapter;
1035         struct ixgbe_ring *rx_ring = NULL;
1036         int work_done = 0;
1037         long r_idx;
1038
1039         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1040         rx_ring = &(adapter->rx_ring[r_idx]);
1041 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
1042         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1043                 ixgbe_update_rx_dca(adapter, rx_ring);
1044 #endif
1045
1046         ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1047
1048         /* If all Rx work done, exit the polling mode */
1049         if (work_done < budget) {
1050                 netif_rx_complete(adapter->netdev, napi);
1051                 if (adapter->itr_setting & 3)
1052                         ixgbe_set_itr_msix(q_vector);
1053                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1054                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1055         }
1056
1057         return work_done;
1058 }
1059
1060 /**
1061  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1062  * @napi: napi struct with our devices info in it
1063  * @budget: amount of work driver is allowed to do this pass, in packets
1064  *
1065  * This function will clean more than one rx queue associated with a
1066  * q_vector.
1067  **/
1068 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1069 {
1070         struct ixgbe_q_vector *q_vector =
1071                                container_of(napi, struct ixgbe_q_vector, napi);
1072         struct ixgbe_adapter *adapter = q_vector->adapter;
1073         struct net_device *netdev = adapter->netdev;
1074         struct ixgbe_ring *rx_ring = NULL;
1075         int work_done = 0, i;
1076         long r_idx;
1077         u16 enable_mask = 0;
1078
1079         /* attempt to distribute budget to each queue fairly, but don't allow
1080          * the budget to go below 1 because we'll exit polling */
1081         budget /= (q_vector->rxr_count ?: 1);
1082         budget = max(budget, 1);
1083         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1084         for (i = 0; i < q_vector->rxr_count; i++) {
1085                 rx_ring = &(adapter->rx_ring[r_idx]);
1086 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
1087                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1088                         ixgbe_update_rx_dca(adapter, rx_ring);
1089 #endif
1090                 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1091                 enable_mask |= rx_ring->v_idx;
1092                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1093                                       r_idx + 1);
1094         }
1095
1096         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1097         rx_ring = &(adapter->rx_ring[r_idx]);
1098         /* If all Rx work done, exit the polling mode */
1099         if ((work_done == 0) || !netif_running(netdev)) {
1100                 netif_rx_complete(netdev, napi);
1101                 if (adapter->itr_setting & 3)
1102                         ixgbe_set_itr_msix(q_vector);
1103                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1104                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1105                 return 0;
1106         }
1107
1108         return work_done;
1109 }
1110 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1111                                      int r_idx)
1112 {
1113         a->q_vector[v_idx].adapter = a;
1114         set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1115         a->q_vector[v_idx].rxr_count++;
1116         a->rx_ring[r_idx].v_idx = 1 << v_idx;
1117 }
1118
1119 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1120                                      int r_idx)
1121 {
1122         a->q_vector[v_idx].adapter = a;
1123         set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1124         a->q_vector[v_idx].txr_count++;
1125         a->tx_ring[r_idx].v_idx = 1 << v_idx;
1126 }
1127
1128 /**
1129  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1130  * @adapter: board private structure to initialize
1131  * @vectors: allotted vector count for descriptor rings
1132  *
1133  * This function maps descriptor rings to the queue-specific vectors
1134  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1135  * one vector per ring/queue, but on a constrained vector budget, we
1136  * group the rings as "efficiently" as possible.  You would add new
1137  * mapping configurations in here.
1138  **/
1139 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1140                                       int vectors)
1141 {
1142         int v_start = 0;
1143         int rxr_idx = 0, txr_idx = 0;
1144         int rxr_remaining = adapter->num_rx_queues;
1145         int txr_remaining = adapter->num_tx_queues;
1146         int i, j;
1147         int rqpv, tqpv;
1148         int err = 0;
1149
1150         /* No mapping required if MSI-X is disabled. */
1151         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1152                 goto out;
1153
1154         /*
1155          * The ideal configuration...
1156          * We have enough vectors to map one per queue.
1157          */
1158         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1159                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1160                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1161
1162                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1163                         map_vector_to_txq(adapter, v_start, txr_idx);
1164
1165                 goto out;
1166         }
1167
1168         /*
1169          * If we don't have enough vectors for a 1-to-1
1170          * mapping, we'll have to group them so there are
1171          * multiple queues per vector.
1172          */
1173         /* Re-adjusting *qpv takes care of the remainder. */
1174         for (i = v_start; i < vectors; i++) {
1175                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1176                 for (j = 0; j < rqpv; j++) {
1177                         map_vector_to_rxq(adapter, i, rxr_idx);
1178                         rxr_idx++;
1179                         rxr_remaining--;
1180                 }
1181         }
1182         for (i = v_start; i < vectors; i++) {
1183                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1184                 for (j = 0; j < tqpv; j++) {
1185                         map_vector_to_txq(adapter, i, txr_idx);
1186                         txr_idx++;
1187                         txr_remaining--;
1188                 }
1189         }
1190
1191 out:
1192         return err;
1193 }
1194
1195 /**
1196  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1197  * @adapter: board private structure
1198  *
1199  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1200  * interrupts from the kernel.
1201  **/
1202 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1203 {
1204         struct net_device *netdev = adapter->netdev;
1205         irqreturn_t (*handler)(int, void *);
1206         int i, vector, q_vectors, err;
1207
1208         /* Decrement for Other and TCP Timer vectors */
1209         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1210
1211         /* Map the Tx/Rx rings to the vectors we were allotted. */
1212         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1213         if (err)
1214                 goto out;
1215
1216 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1217                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1218                          &ixgbe_msix_clean_many)
1219         for (vector = 0; vector < q_vectors; vector++) {
1220                 handler = SET_HANDLER(&adapter->q_vector[vector]);
1221                 sprintf(adapter->name[vector], "%s:v%d-%s",
1222                         netdev->name, vector,
1223                         (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1224                          ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1225                 err = request_irq(adapter->msix_entries[vector].vector,
1226                                   handler, 0, adapter->name[vector],
1227                                   &(adapter->q_vector[vector]));
1228                 if (err) {
1229                         DPRINTK(PROBE, ERR,
1230                                 "request_irq failed for MSIX interrupt "
1231                                 "Error: %d\n", err);
1232                         goto free_queue_irqs;
1233                 }
1234         }
1235
1236         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1237         err = request_irq(adapter->msix_entries[vector].vector,
1238                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1239         if (err) {
1240                 DPRINTK(PROBE, ERR,
1241                         "request_irq for msix_lsc failed: %d\n", err);
1242                 goto free_queue_irqs;
1243         }
1244
1245         return 0;
1246
1247 free_queue_irqs:
1248         for (i = vector - 1; i >= 0; i--)
1249                 free_irq(adapter->msix_entries[--vector].vector,
1250                          &(adapter->q_vector[i]));
1251         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1252         pci_disable_msix(adapter->pdev);
1253         kfree(adapter->msix_entries);
1254         adapter->msix_entries = NULL;
1255 out:
1256         return err;
1257 }
1258
1259 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1260 {
1261         struct ixgbe_hw *hw = &adapter->hw;
1262         struct ixgbe_q_vector *q_vector = adapter->q_vector;
1263         u8 current_itr;
1264         u32 new_itr = q_vector->eitr;
1265         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1266         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1267
1268         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1269                                             q_vector->tx_itr,
1270                                             tx_ring->total_packets,
1271                                             tx_ring->total_bytes);
1272         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1273                                             q_vector->rx_itr,
1274                                             rx_ring->total_packets,
1275                                             rx_ring->total_bytes);
1276
1277         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1278
1279         switch (current_itr) {
1280         /* counts and packets in update_itr are dependent on these numbers */
1281         case lowest_latency:
1282                 new_itr = 100000;
1283                 break;
1284         case low_latency:
1285                 new_itr = 20000; /* aka hwitr = ~200 */
1286                 break;
1287         case bulk_latency:
1288                 new_itr = 8000;
1289                 break;
1290         default:
1291                 break;
1292         }
1293
1294         if (new_itr != q_vector->eitr) {
1295                 u32 itr_reg;
1296                 /* do an exponential smoothing */
1297                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1298                 q_vector->eitr = new_itr;
1299                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1300                 /* must write high and low 16 bits to reset counter */
1301                 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1302         }
1303
1304         return;
1305 }
1306
1307 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1308
1309 /**
1310  * ixgbe_intr - legacy mode Interrupt Handler
1311  * @irq: interrupt number
1312  * @data: pointer to a network interface device structure
1313  * @pt_regs: CPU registers structure
1314  **/
1315 static irqreturn_t ixgbe_intr(int irq, void *data)
1316 {
1317         struct net_device *netdev = data;
1318         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1319         struct ixgbe_hw *hw = &adapter->hw;
1320         u32 eicr;
1321
1322
1323         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1324          * therefore no explict interrupt disable is necessary */
1325         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1326         if (!eicr) {
1327                 /* shared interrupt alert!
1328                  * make sure interrupts are enabled because the read will
1329                  * have disabled interrupts due to EIAM */
1330                 ixgbe_irq_enable(adapter);
1331                 return IRQ_NONE;        /* Not our interrupt */
1332         }
1333
1334         if (eicr & IXGBE_EICR_LSC)
1335                 ixgbe_check_lsc(adapter);
1336
1337         if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
1338                 adapter->tx_ring[0].total_packets = 0;
1339                 adapter->tx_ring[0].total_bytes = 0;
1340                 adapter->rx_ring[0].total_packets = 0;
1341                 adapter->rx_ring[0].total_bytes = 0;
1342                 /* would disable interrupts here but EIAM disabled it */
1343                 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
1344         }
1345
1346         return IRQ_HANDLED;
1347 }
1348
1349 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1350 {
1351         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1352
1353         for (i = 0; i < q_vectors; i++) {
1354                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1355                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1356                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1357                 q_vector->rxr_count = 0;
1358                 q_vector->txr_count = 0;
1359         }
1360 }
1361
1362 /**
1363  * ixgbe_request_irq - initialize interrupts
1364  * @adapter: board private structure
1365  *
1366  * Attempts to configure interrupts using the best available
1367  * capabilities of the hardware and kernel.
1368  **/
1369 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1370 {
1371         struct net_device *netdev = adapter->netdev;
1372         int err;
1373
1374         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1375                 err = ixgbe_request_msix_irqs(adapter);
1376         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1377                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1378                                   netdev->name, netdev);
1379         } else {
1380                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1381                                   netdev->name, netdev);
1382         }
1383
1384         if (err)
1385                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1386
1387         return err;
1388 }
1389
1390 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1391 {
1392         struct net_device *netdev = adapter->netdev;
1393
1394         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1395                 int i, q_vectors;
1396
1397                 q_vectors = adapter->num_msix_vectors;
1398
1399                 i = q_vectors - 1;
1400                 free_irq(adapter->msix_entries[i].vector, netdev);
1401
1402                 i--;
1403                 for (; i >= 0; i--) {
1404                         free_irq(adapter->msix_entries[i].vector,
1405                                  &(adapter->q_vector[i]));
1406                 }
1407
1408                 ixgbe_reset_q_vectors(adapter);
1409         } else {
1410                 free_irq(adapter->pdev->irq, netdev);
1411         }
1412 }
1413
1414 /**
1415  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1416  * @adapter: board private structure
1417  **/
1418 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1419 {
1420         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1421         IXGBE_WRITE_FLUSH(&adapter->hw);
1422         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1423                 int i;
1424                 for (i = 0; i < adapter->num_msix_vectors; i++)
1425                         synchronize_irq(adapter->msix_entries[i].vector);
1426         } else {
1427                 synchronize_irq(adapter->pdev->irq);
1428         }
1429 }
1430
1431 /**
1432  * ixgbe_irq_enable - Enable default interrupt generation settings
1433  * @adapter: board private structure
1434  **/
1435 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1436 {
1437         u32 mask;
1438         mask = IXGBE_EIMS_ENABLE_MASK;
1439         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1440         IXGBE_WRITE_FLUSH(&adapter->hw);
1441 }
1442
1443 /**
1444  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1445  *
1446  **/
1447 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1448 {
1449         struct ixgbe_hw *hw = &adapter->hw;
1450
1451         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1452                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1453
1454         ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
1455         ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1456
1457         map_vector_to_rxq(adapter, 0, 0);
1458         map_vector_to_txq(adapter, 0, 0);
1459
1460         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1461 }
1462
1463 /**
1464  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1465  * @adapter: board private structure
1466  *
1467  * Configure the Tx unit of the MAC after a reset.
1468  **/
1469 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1470 {
1471         u64 tdba, tdwba;
1472         struct ixgbe_hw *hw = &adapter->hw;
1473         u32 i, j, tdlen, txctrl;
1474
1475         /* Setup the HW Tx Head and Tail descriptor pointers */
1476         for (i = 0; i < adapter->num_tx_queues; i++) {
1477                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1478                 j = ring->reg_idx;
1479                 tdba = ring->dma;
1480                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1481                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1482                                 (tdba & DMA_32BIT_MASK));
1483                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1484                 tdwba = ring->dma +
1485                         (ring->count * sizeof(union ixgbe_adv_tx_desc));
1486                 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1487                 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1488                 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
1489                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1490                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1491                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1492                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1493                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1494                 /* Disable Tx Head Writeback RO bit, since this hoses
1495                  * bookkeeping if things aren't delivered in order.
1496                  */
1497                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1498                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1499                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1500         }
1501 }
1502
1503 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1504
1505 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1506 {
1507         struct ixgbe_ring *rx_ring;
1508         u32 srrctl;
1509         int queue0;
1510         unsigned long mask;
1511
1512         /* program one srrctl register per VMDq index */
1513         if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1514                 long shift, len;
1515                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1516                 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1517                 shift = find_first_bit(&mask, len);
1518                 queue0 = index & mask;
1519                 index = (index & mask) >> shift;
1520         /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
1521         } else {
1522                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1523                 queue0 = index & mask;
1524                 index = index & mask;
1525         }
1526
1527         rx_ring = &adapter->rx_ring[queue0];
1528
1529         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1530
1531         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1532         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1533
1534         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1535                 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1536                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1537                 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1538                             IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1539                            IXGBE_SRRCTL_BSIZEHDR_MASK);
1540         } else {
1541                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1542
1543                 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1544                         srrctl |= IXGBE_RXBUFFER_2048 >>
1545                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1546                 else
1547                         srrctl |= rx_ring->rx_buf_len >>
1548                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1549         }
1550         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1551 }
1552
1553 /**
1554  * ixgbe_get_skb_hdr - helper function for LRO header processing
1555  * @skb: pointer to sk_buff to be added to LRO packet
1556  * @iphdr: pointer to tcp header structure
1557  * @tcph: pointer to tcp header structure
1558  * @hdr_flags: pointer to header flags
1559  * @priv: private data
1560  **/
1561 static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1562                              u64 *hdr_flags, void *priv)
1563 {
1564         union ixgbe_adv_rx_desc *rx_desc = priv;
1565
1566         /* Verify that this is a valid IPv4 TCP packet */
1567         if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1568              (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
1569                 return -1;
1570
1571         /* Set network headers */
1572         skb_reset_network_header(skb);
1573         skb_set_transport_header(skb, ip_hdrlen(skb));
1574         *iphdr = ip_hdr(skb);
1575         *tcph = tcp_hdr(skb);
1576         *hdr_flags = LRO_IPV4 | LRO_TCP;
1577         return 0;
1578 }
1579
1580 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1581                         (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1582
1583 /**
1584  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1585  * @adapter: board private structure
1586  *
1587  * Configure the Rx unit of the MAC after a reset.
1588  **/
1589 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1590 {
1591         u64 rdba;
1592         struct ixgbe_hw *hw = &adapter->hw;
1593         struct net_device *netdev = adapter->netdev;
1594         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1595         int i, j;
1596         u32 rdlen, rxctrl, rxcsum;
1597         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1598                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1599                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1600         u32 fctrl, hlreg0;
1601         u32 pages;
1602         u32 reta = 0, mrqc;
1603         u32 rdrxctl;
1604         int rx_buf_len;
1605
1606         /* Decide whether to use packet split mode or not */
1607         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1608
1609         /* Set the RX buffer length according to the mode */
1610         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1611                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1612         } else {
1613                 if (netdev->mtu <= ETH_DATA_LEN)
1614                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1615                 else
1616                         rx_buf_len = ALIGN(max_frame, 1024);
1617         }
1618
1619         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1620         fctrl |= IXGBE_FCTRL_BAM;
1621         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1622         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1623
1624         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1625         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1626                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1627         else
1628                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1629         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1630
1631         pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1632
1633         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1634         /* disable receives while setting up the descriptors */
1635         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1636         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1637
1638         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1639          * the Base and Length of the Rx Descriptor Ring */
1640         for (i = 0; i < adapter->num_rx_queues; i++) {
1641                 rdba = adapter->rx_ring[i].dma;
1642                 j = adapter->rx_ring[i].reg_idx;
1643                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1644                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1645                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1646                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1647                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1648                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1649                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1650                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1651                 /* Intitial LRO Settings */
1652                 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1653                 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1654                 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1655                 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1656                 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1657                         adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1658                 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1659                 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1660                 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1661
1662                 ixgbe_configure_srrctl(adapter, j);
1663         }
1664
1665         /*
1666          * For VMDq support of different descriptor types or
1667          * buffer sizes through the use of multiple SRRCTL
1668          * registers, RDRXCTL.MVMEN must be set to 1
1669          *
1670          * also, the manual doesn't mention it clearly but DCA hints
1671          * will only use queue 0's tags unless this bit is set.  Side
1672          * effects of setting this bit are only that SRRCTL must be
1673          * fully programmed [0..15]
1674          */
1675         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1676         rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1677         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1678
1679
1680         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1681                 /* Fill out redirection table */
1682                 for (i = 0, j = 0; i < 128; i++, j++) {
1683                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1684                                 j = 0;
1685                         /* reta = 4-byte sliding window of
1686                          * 0x00..(indices-1)(indices-1)00..etc. */
1687                         reta = (reta << 8) | (j * 0x11);
1688                         if ((i & 3) == 3)
1689                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1690                 }
1691
1692                 /* Fill out hash function seeds */
1693                 for (i = 0; i < 10; i++)
1694                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1695
1696                 mrqc = IXGBE_MRQC_RSSEN
1697                     /* Perform hash on these packet types */
1698                        | IXGBE_MRQC_RSS_FIELD_IPV4
1699                        | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1700                        | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1701                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1702                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1703                        | IXGBE_MRQC_RSS_FIELD_IPV6
1704                        | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1705                        | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1706                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1707                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1708         }
1709
1710         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1711
1712         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1713             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1714                 /* Disable indicating checksum in descriptor, enables
1715                  * RSS hash */
1716                 rxcsum |= IXGBE_RXCSUM_PCSD;
1717         }
1718         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1719                 /* Enable IPv4 payload checksum for UDP fragments
1720                  * if PCSD is not set */
1721                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1722         }
1723
1724         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1725 }
1726
1727 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1728                                    struct vlan_group *grp)
1729 {
1730         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1731         u32 ctrl;
1732
1733         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1734                 ixgbe_irq_disable(adapter);
1735         adapter->vlgrp = grp;
1736
1737         if (grp) {
1738                 /* enable VLAN tag insert/strip */
1739                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1740                 ctrl |= IXGBE_VLNCTRL_VME;
1741                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1742                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1743         }
1744
1745         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1746                 ixgbe_irq_enable(adapter);
1747 }
1748
1749 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1750 {
1751         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1752         struct ixgbe_hw *hw = &adapter->hw;
1753
1754         /* add VID to filter table */
1755         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1756 }
1757
1758 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1759 {
1760         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1761         struct ixgbe_hw *hw = &adapter->hw;
1762
1763         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1764                 ixgbe_irq_disable(adapter);
1765
1766         vlan_group_set_device(adapter->vlgrp, vid, NULL);
1767
1768         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1769                 ixgbe_irq_enable(adapter);
1770
1771         /* remove VID from filter table */
1772         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1773 }
1774
1775 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1776 {
1777         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1778
1779         if (adapter->vlgrp) {
1780                 u16 vid;
1781                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1782                         if (!vlan_group_get_device(adapter->vlgrp, vid))
1783                                 continue;
1784                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1785                 }
1786         }
1787 }
1788
1789 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1790 {
1791         struct dev_mc_list *mc_ptr;
1792         u8 *addr = *mc_addr_ptr;
1793         *vmdq = 0;
1794
1795         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1796         if (mc_ptr->next)
1797                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1798         else
1799                 *mc_addr_ptr = NULL;
1800
1801         return addr;
1802 }
1803
1804 /**
1805  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1806  * @netdev: network interface device structure
1807  *
1808  * The set_rx_method entry point is called whenever the unicast/multicast
1809  * address list or the network interface flags are updated.  This routine is
1810  * responsible for configuring the hardware for proper unicast, multicast and
1811  * promiscuous mode.
1812  **/
1813 static void ixgbe_set_rx_mode(struct net_device *netdev)
1814 {
1815         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1816         struct ixgbe_hw *hw = &adapter->hw;
1817         u32 fctrl, vlnctrl;
1818         u8 *addr_list = NULL;
1819         int addr_count = 0;
1820
1821         /* Check for Promiscuous and All Multicast modes */
1822
1823         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1824         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1825
1826         if (netdev->flags & IFF_PROMISC) {
1827                 hw->addr_ctrl.user_set_promisc = 1;
1828                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1829                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1830         } else {
1831                 if (netdev->flags & IFF_ALLMULTI) {
1832                         fctrl |= IXGBE_FCTRL_MPE;
1833                         fctrl &= ~IXGBE_FCTRL_UPE;
1834                 } else {
1835                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1836                 }
1837                 vlnctrl |= IXGBE_VLNCTRL_VFE;
1838                 hw->addr_ctrl.user_set_promisc = 0;
1839         }
1840
1841         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1842         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1843
1844         /* reprogram secondary unicast list */
1845         addr_count = netdev->uc_count;
1846         if (addr_count)
1847                 addr_list = netdev->uc_list->dmi_addr;
1848         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1849                                           ixgbe_addr_list_itr);
1850
1851         /* reprogram multicast list */
1852         addr_count = netdev->mc_count;
1853         if (addr_count)
1854                 addr_list = netdev->mc_list->dmi_addr;
1855         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1856                                         ixgbe_addr_list_itr);
1857 }
1858
1859 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1860 {
1861         int q_idx;
1862         struct ixgbe_q_vector *q_vector;
1863         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1864
1865         /* legacy and MSI only use one vector */
1866         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1867                 q_vectors = 1;
1868
1869         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1870                 struct napi_struct *napi;
1871                 q_vector = &adapter->q_vector[q_idx];
1872                 if (!q_vector->rxr_count)
1873                         continue;
1874                 napi = &q_vector->napi;
1875                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1876                     (q_vector->rxr_count > 1))
1877                         napi->poll = &ixgbe_clean_rxonly_many;
1878
1879                 napi_enable(napi);
1880         }
1881 }
1882
1883 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1884 {
1885         int q_idx;
1886         struct ixgbe_q_vector *q_vector;
1887         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1888
1889         /* legacy and MSI only use one vector */
1890         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1891                 q_vectors = 1;
1892
1893         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1894                 q_vector = &adapter->q_vector[q_idx];
1895                 if (!q_vector->rxr_count)
1896                         continue;
1897                 napi_disable(&q_vector->napi);
1898         }
1899 }
1900
1901 static void ixgbe_configure(struct ixgbe_adapter *adapter)
1902 {
1903         struct net_device *netdev = adapter->netdev;
1904         int i;
1905
1906         ixgbe_set_rx_mode(netdev);
1907
1908         ixgbe_restore_vlan(adapter);
1909
1910         ixgbe_configure_tx(adapter);
1911         ixgbe_configure_rx(adapter);
1912         for (i = 0; i < adapter->num_rx_queues; i++)
1913                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1914                                            (adapter->rx_ring[i].count - 1));
1915 }
1916
1917 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1918 {
1919         struct net_device *netdev = adapter->netdev;
1920         struct ixgbe_hw *hw = &adapter->hw;
1921         int i, j = 0;
1922         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1923         u32 txdctl, rxdctl, mhadd;
1924         u32 gpie;
1925
1926         ixgbe_get_hw_control(adapter);
1927
1928         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1929             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
1930                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1931                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1932                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1933                 } else {
1934                         /* MSI only */
1935                         gpie = 0;
1936                 }
1937                 /* XXX: to interrupt immediately for EICS writes, enable this */
1938                 /* gpie |= IXGBE_GPIE_EIMEN; */
1939                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1940         }
1941
1942         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1943                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1944                  * specifically only auto mask tx and rx interrupts */
1945                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1946         }
1947
1948         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
1949         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1950                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1951                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1952
1953                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1954         }
1955
1956         for (i = 0; i < adapter->num_tx_queues; i++) {
1957                 j = adapter->tx_ring[i].reg_idx;
1958                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1959                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1960                 txdctl |= (8 << 16);
1961                 txdctl |= IXGBE_TXDCTL_ENABLE;
1962                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1963         }
1964
1965         for (i = 0; i < adapter->num_rx_queues; i++) {
1966                 j = adapter->rx_ring[i].reg_idx;
1967                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1968                 /* enable PTHRESH=32 descriptors (half the internal cache)
1969                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
1970                  * this also removes a pesky rx_no_buffer_count increment */
1971                 rxdctl |= 0x0020;
1972                 rxdctl |= IXGBE_RXDCTL_ENABLE;
1973                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
1974         }
1975         /* enable all receives */
1976         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1977         rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1978         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1979
1980         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1981                 ixgbe_configure_msix(adapter);
1982         else
1983                 ixgbe_configure_msi_and_legacy(adapter);
1984
1985         clear_bit(__IXGBE_DOWN, &adapter->state);
1986         ixgbe_napi_enable_all(adapter);
1987
1988         /* clear any pending interrupts, may auto mask */
1989         IXGBE_READ_REG(hw, IXGBE_EICR);
1990
1991         ixgbe_irq_enable(adapter);
1992
1993         /* bring the link up in the watchdog, this could race with our first
1994          * link up interrupt but shouldn't be a problem */
1995         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1996         adapter->link_check_timeout = jiffies;
1997         mod_timer(&adapter->watchdog_timer, jiffies);
1998         return 0;
1999 }
2000
2001 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2002 {
2003         WARN_ON(in_interrupt());
2004         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2005                 msleep(1);
2006         ixgbe_down(adapter);
2007         ixgbe_up(adapter);
2008         clear_bit(__IXGBE_RESETTING, &adapter->state);
2009 }
2010
2011 int ixgbe_up(struct ixgbe_adapter *adapter)
2012 {
2013         /* hardware has been reset, we need to reload some things */
2014         ixgbe_configure(adapter);
2015
2016         return ixgbe_up_complete(adapter);
2017 }
2018
2019 void ixgbe_reset(struct ixgbe_adapter *adapter)
2020 {
2021         struct ixgbe_hw *hw = &adapter->hw;
2022         if (hw->mac.ops.init_hw(hw))
2023                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2024
2025         /* reprogram the RAR[0] in case user changed it. */
2026         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2027
2028 }
2029
2030 #ifdef CONFIG_PM
2031 static int ixgbe_resume(struct pci_dev *pdev)
2032 {
2033         struct net_device *netdev = pci_get_drvdata(pdev);
2034         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2035         u32 err;
2036
2037         pci_set_power_state(pdev, PCI_D0);
2038         pci_restore_state(pdev);
2039         err = pci_enable_device(pdev);
2040         if (err) {
2041                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
2042                                 "suspend\n");
2043                 return err;
2044         }
2045         pci_set_master(pdev);
2046
2047         pci_enable_wake(pdev, PCI_D3hot, 0);
2048         pci_enable_wake(pdev, PCI_D3cold, 0);
2049
2050         if (netif_running(netdev)) {
2051                 err = ixgbe_request_irq(adapter);
2052                 if (err)
2053                         return err;
2054         }
2055
2056         ixgbe_reset(adapter);
2057
2058         if (netif_running(netdev))
2059                 ixgbe_up(adapter);
2060
2061         netif_device_attach(netdev);
2062
2063         return 0;
2064 }
2065 #endif
2066
2067 /**
2068  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2069  * @adapter: board private structure
2070  * @rx_ring: ring to free buffers from
2071  **/
2072 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2073                                 struct ixgbe_ring *rx_ring)
2074 {
2075         struct pci_dev *pdev = adapter->pdev;
2076         unsigned long size;
2077         unsigned int i;
2078
2079         /* Free all the Rx ring sk_buffs */
2080
2081         for (i = 0; i < rx_ring->count; i++) {
2082                 struct ixgbe_rx_buffer *rx_buffer_info;
2083
2084                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2085                 if (rx_buffer_info->dma) {
2086                         pci_unmap_single(pdev, rx_buffer_info->dma,
2087                                          rx_ring->rx_buf_len,
2088                                          PCI_DMA_FROMDEVICE);
2089                         rx_buffer_info->dma = 0;
2090                 }
2091                 if (rx_buffer_info->skb) {
2092                         dev_kfree_skb(rx_buffer_info->skb);
2093                         rx_buffer_info->skb = NULL;
2094                 }
2095                 if (!rx_buffer_info->page)
2096                         continue;
2097                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2098                                PCI_DMA_FROMDEVICE);
2099                 rx_buffer_info->page_dma = 0;
2100                 put_page(rx_buffer_info->page);
2101                 rx_buffer_info->page = NULL;
2102                 rx_buffer_info->page_offset = 0;
2103         }
2104
2105         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2106         memset(rx_ring->rx_buffer_info, 0, size);
2107
2108         /* Zero out the descriptor ring */
2109         memset(rx_ring->desc, 0, rx_ring->size);
2110
2111         rx_ring->next_to_clean = 0;
2112         rx_ring->next_to_use = 0;
2113
2114         writel(0, adapter->hw.hw_addr + rx_ring->head);
2115         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2116 }
2117
2118 /**
2119  * ixgbe_clean_tx_ring - Free Tx Buffers
2120  * @adapter: board private structure
2121  * @tx_ring: ring to be cleaned
2122  **/
2123 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2124                                 struct ixgbe_ring *tx_ring)
2125 {
2126         struct ixgbe_tx_buffer *tx_buffer_info;
2127         unsigned long size;
2128         unsigned int i;
2129
2130         /* Free all the Tx ring sk_buffs */
2131
2132         for (i = 0; i < tx_ring->count; i++) {
2133                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2134                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2135         }
2136
2137         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2138         memset(tx_ring->tx_buffer_info, 0, size);
2139
2140         /* Zero out the descriptor ring */
2141         memset(tx_ring->desc, 0, tx_ring->size);
2142
2143         tx_ring->next_to_use = 0;
2144         tx_ring->next_to_clean = 0;
2145
2146         writel(0, adapter->hw.hw_addr + tx_ring->head);
2147         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2148 }
2149
2150 /**
2151  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2152  * @adapter: board private structure
2153  **/
2154 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2155 {
2156         int i;
2157
2158         for (i = 0; i < adapter->num_rx_queues; i++)
2159                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2160 }
2161
2162 /**
2163  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2164  * @adapter: board private structure
2165  **/
2166 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2167 {
2168         int i;
2169
2170         for (i = 0; i < adapter->num_tx_queues; i++)
2171                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2172 }
2173
2174 void ixgbe_down(struct ixgbe_adapter *adapter)
2175 {
2176         struct net_device *netdev = adapter->netdev;
2177         u32 rxctrl;
2178
2179         /* signal that we are down to the interrupt handler */
2180         set_bit(__IXGBE_DOWN, &adapter->state);
2181
2182         /* disable receives */
2183         rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
2184         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
2185                         rxctrl & ~IXGBE_RXCTRL_RXEN);
2186
2187         netif_tx_disable(netdev);
2188
2189         /* disable transmits in the hardware */
2190
2191         /* flush both disables */
2192         IXGBE_WRITE_FLUSH(&adapter->hw);
2193         msleep(10);
2194
2195         ixgbe_irq_disable(adapter);
2196
2197         ixgbe_napi_disable_all(adapter);
2198         del_timer_sync(&adapter->watchdog_timer);
2199         cancel_work_sync(&adapter->watchdog_task);
2200
2201         netif_carrier_off(netdev);
2202         netif_tx_stop_all_queues(netdev);
2203
2204 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2205         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2206                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2207                 dca_remove_requester(&adapter->pdev->dev);
2208         }
2209
2210 #endif
2211         if (!pci_channel_offline(adapter->pdev))
2212                 ixgbe_reset(adapter);
2213         ixgbe_clean_all_tx_rings(adapter);
2214         ixgbe_clean_all_rx_rings(adapter);
2215
2216 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2217         /* since we reset the hardware DCA settings were cleared */
2218         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2219                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2220                 /* always use CB2 mode, difference is masked
2221                  * in the CB driver */
2222                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
2223                 ixgbe_setup_dca(adapter);
2224         }
2225 #endif
2226 }
2227
2228 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2229 {
2230         struct net_device *netdev = pci_get_drvdata(pdev);
2231         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2232 #ifdef CONFIG_PM
2233         int retval = 0;
2234 #endif
2235
2236         netif_device_detach(netdev);
2237
2238         if (netif_running(netdev)) {
2239                 ixgbe_down(adapter);
2240                 ixgbe_free_irq(adapter);
2241         }
2242
2243 #ifdef CONFIG_PM
2244         retval = pci_save_state(pdev);
2245         if (retval)
2246                 return retval;
2247 #endif
2248
2249         pci_enable_wake(pdev, PCI_D3hot, 0);
2250         pci_enable_wake(pdev, PCI_D3cold, 0);
2251
2252         ixgbe_release_hw_control(adapter);
2253
2254         pci_disable_device(pdev);
2255
2256         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2257
2258         return 0;
2259 }
2260
2261 static void ixgbe_shutdown(struct pci_dev *pdev)
2262 {
2263         ixgbe_suspend(pdev, PMSG_SUSPEND);
2264 }
2265
2266 /**
2267  * ixgbe_poll - NAPI Rx polling callback
2268  * @napi: structure for representing this polling device
2269  * @budget: how many packets driver is allowed to clean
2270  *
2271  * This function is used for legacy and MSI, NAPI mode
2272  **/
2273 static int ixgbe_poll(struct napi_struct *napi, int budget)
2274 {
2275         struct ixgbe_q_vector *q_vector = container_of(napi,
2276                                           struct ixgbe_q_vector, napi);
2277         struct ixgbe_adapter *adapter = q_vector->adapter;
2278         int tx_cleaned = 0, work_done = 0;
2279
2280 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2281         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2282                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2283                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2284         }
2285 #endif
2286
2287         tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2288         ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
2289
2290         if (tx_cleaned)
2291                 work_done = budget;
2292
2293         /* If budget not fully consumed, exit the polling mode */
2294         if (work_done < budget) {
2295                 netif_rx_complete(adapter->netdev, napi);
2296                 if (adapter->itr_setting & 3)
2297                         ixgbe_set_itr(adapter);
2298                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2299                         ixgbe_irq_enable(adapter);
2300         }
2301
2302         return work_done;
2303 }
2304
2305 /**
2306  * ixgbe_tx_timeout - Respond to a Tx Hang
2307  * @netdev: network interface device structure
2308  **/
2309 static void ixgbe_tx_timeout(struct net_device *netdev)
2310 {
2311         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2312
2313         /* Do the reset outside of interrupt context */
2314         schedule_work(&adapter->reset_task);
2315 }
2316
2317 static void ixgbe_reset_task(struct work_struct *work)
2318 {
2319         struct ixgbe_adapter *adapter;
2320         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2321
2322         adapter->tx_timeout_count++;
2323
2324         ixgbe_reinit_locked(adapter);
2325 }
2326
2327 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2328                                        int vectors)
2329 {
2330         int err, vector_threshold;
2331
2332         /* We'll want at least 3 (vector_threshold):
2333          * 1) TxQ[0] Cleanup
2334          * 2) RxQ[0] Cleanup
2335          * 3) Other (Link Status Change, etc.)
2336          * 4) TCP Timer (optional)
2337          */
2338         vector_threshold = MIN_MSIX_COUNT;
2339
2340         /* The more we get, the more we will assign to Tx/Rx Cleanup
2341          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2342          * Right now, we simply care about how many we'll get; we'll
2343          * set them up later while requesting irq's.
2344          */
2345         while (vectors >= vector_threshold) {
2346                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2347                                       vectors);
2348                 if (!err) /* Success in acquiring all requested vectors. */
2349                         break;
2350                 else if (err < 0)
2351                         vectors = 0; /* Nasty failure, quit now */
2352                 else /* err == number of vectors we should try again with */
2353                         vectors = err;
2354         }
2355
2356         if (vectors < vector_threshold) {
2357                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2358                  * This just means we'll go with either a single MSI
2359                  * vector or fall back to legacy interrupts.
2360                  */
2361                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2362                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2363                 kfree(adapter->msix_entries);
2364                 adapter->msix_entries = NULL;
2365                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2366                 adapter->num_tx_queues = 1;
2367                 adapter->num_rx_queues = 1;
2368         } else {
2369                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2370                 adapter->num_msix_vectors = vectors;
2371         }
2372 }
2373
2374 static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2375 {
2376         int nrq, ntq;
2377         int feature_mask = 0, rss_i, rss_m;
2378
2379         /* Number of supported queues */
2380         switch (adapter->hw.mac.type) {
2381         case ixgbe_mac_82598EB:
2382                 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2383                 rss_m = 0;
2384                 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2385
2386                 switch (adapter->flags & feature_mask) {
2387                 case (IXGBE_FLAG_RSS_ENABLED):
2388                         rss_m = 0xF;
2389                         nrq = rss_i;
2390                         ntq = rss_i;
2391                         break;
2392                 case 0:
2393                 default:
2394                         rss_i = 0;
2395                         rss_m = 0;
2396                         nrq = 1;
2397                         ntq = 1;
2398                         break;
2399                 }
2400
2401                 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2402                 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2403                 break;
2404         default:
2405                 nrq = 1;
2406                 ntq = 1;
2407                 break;
2408         }
2409
2410         adapter->num_rx_queues = nrq;
2411         adapter->num_tx_queues = ntq;
2412 }
2413
2414 /**
2415  * ixgbe_cache_ring_register - Descriptor ring to register mapping
2416  * @adapter: board private structure to initialize
2417  *
2418  * Once we know the feature-set enabled for the device, we'll cache
2419  * the register offset the descriptor ring is assigned to.
2420  **/
2421 static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2422 {
2423         /* TODO: Remove all uses of the indices in the cases where multiple
2424          *       features are OR'd together, if the feature set makes sense.
2425          */
2426         int feature_mask = 0, rss_i;
2427         int i, txr_idx, rxr_idx;
2428
2429         /* Number of supported queues */
2430         switch (adapter->hw.mac.type) {
2431         case ixgbe_mac_82598EB:
2432                 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2433                 txr_idx = 0;
2434                 rxr_idx = 0;
2435                 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2436                 switch (adapter->flags & feature_mask) {
2437                 case (IXGBE_FLAG_RSS_ENABLED):
2438                         for (i = 0; i < adapter->num_rx_queues; i++)
2439                                 adapter->rx_ring[i].reg_idx = i;
2440                         for (i = 0; i < adapter->num_tx_queues; i++)
2441                                 adapter->tx_ring[i].reg_idx = i;
2442                         break;
2443                 case 0:
2444                 default:
2445                         break;
2446                 }
2447                 break;
2448         default:
2449                 break;
2450         }
2451 }
2452
2453 /**
2454  * ixgbe_alloc_queues - Allocate memory for all rings
2455  * @adapter: board private structure to initialize
2456  *
2457  * We allocate one ring per queue at run-time since we don't know the
2458  * number of queues at compile-time.  The polling_netdev array is
2459  * intended for Multiqueue, but should work fine with a single queue.
2460  **/
2461 static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2462 {
2463         int i;
2464
2465         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2466                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2467         if (!adapter->tx_ring)
2468                 goto err_tx_ring_allocation;
2469
2470         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2471                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2472         if (!adapter->rx_ring)
2473                 goto err_rx_ring_allocation;
2474
2475         for (i = 0; i < adapter->num_tx_queues; i++) {
2476                 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2477                 adapter->tx_ring[i].queue_index = i;
2478         }
2479         for (i = 0; i < adapter->num_rx_queues; i++) {
2480                 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
2481                 adapter->rx_ring[i].queue_index = i;
2482         }
2483
2484         ixgbe_cache_ring_register(adapter);
2485
2486         return 0;
2487
2488 err_rx_ring_allocation:
2489         kfree(adapter->tx_ring);
2490 err_tx_ring_allocation:
2491         return -ENOMEM;
2492 }
2493
2494 /**
2495  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2496  * @adapter: board private structure to initialize
2497  *
2498  * Attempt to configure the interrupts using the best available
2499  * capabilities of the hardware and the kernel.
2500  **/
2501 static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2502                                                     *adapter)
2503 {
2504         int err = 0;
2505         int vector, v_budget;
2506
2507         /*
2508          * It's easy to be greedy for MSI-X vectors, but it really
2509          * doesn't do us much good if we have a lot more vectors
2510          * than CPU's.  So let's be conservative and only ask for
2511          * (roughly) twice the number of vectors as there are CPU's.
2512          */
2513         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2514                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2515
2516         /*
2517          * At the same time, hardware can only support a maximum of
2518          * MAX_MSIX_COUNT vectors.  With features such as RSS and VMDq,
2519          * we can easily reach upwards of 64 Rx descriptor queues and
2520          * 32 Tx queues.  Thus, we cap it off in those rare cases where
2521          * the cpu count also exceeds our vector limit.
2522          */
2523         v_budget = min(v_budget, MAX_MSIX_COUNT);
2524
2525         /* A failure in MSI-X entry allocation isn't fatal, but it does
2526          * mean we disable MSI-X capabilities of the adapter. */
2527         adapter->msix_entries = kcalloc(v_budget,
2528                                         sizeof(struct msix_entry), GFP_KERNEL);
2529         if (!adapter->msix_entries) {
2530                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2531                 ixgbe_set_num_queues(adapter);
2532                 kfree(adapter->tx_ring);
2533                 kfree(adapter->rx_ring);
2534                 err = ixgbe_alloc_queues(adapter);
2535                 if (err) {
2536                         DPRINTK(PROBE, ERR, "Unable to allocate memory "
2537                                             "for queues\n");
2538                         goto out;
2539                 }
2540
2541                 goto try_msi;
2542         }
2543
2544         for (vector = 0; vector < v_budget; vector++)
2545                 adapter->msix_entries[vector].entry = vector;
2546
2547         ixgbe_acquire_msix_vectors(adapter, v_budget);
2548
2549         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2550                 goto out;
2551
2552 try_msi:
2553         err = pci_enable_msi(adapter->pdev);
2554         if (!err) {
2555                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2556         } else {
2557                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2558                                    "falling back to legacy.  Error: %d\n", err);
2559                 /* reset err */
2560                 err = 0;
2561         }
2562
2563 out:
2564         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2565         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2566
2567         return err;
2568 }
2569
2570 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2571 {
2572         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2573                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2574                 pci_disable_msix(adapter->pdev);
2575                 kfree(adapter->msix_entries);
2576                 adapter->msix_entries = NULL;
2577         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2578                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2579                 pci_disable_msi(adapter->pdev);
2580         }
2581         return;
2582 }
2583
2584 /**
2585  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2586  * @adapter: board private structure to initialize
2587  *
2588  * We determine which interrupt scheme to use based on...
2589  * - Kernel support (MSI, MSI-X)
2590  *   - which can be user-defined (via MODULE_PARAM)
2591  * - Hardware queue count (num_*_queues)
2592  *   - defined by miscellaneous hardware support/features (RSS, etc.)
2593  **/
2594 static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2595 {
2596         int err;
2597
2598         /* Number of supported queues */
2599         ixgbe_set_num_queues(adapter);
2600
2601         err = ixgbe_alloc_queues(adapter);
2602         if (err) {
2603                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2604                 goto err_alloc_queues;
2605         }
2606
2607         err = ixgbe_set_interrupt_capability(adapter);
2608         if (err) {
2609                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2610                 goto err_set_interrupt;
2611         }
2612
2613         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2614                            "Tx Queue count = %u\n",
2615                 (adapter->num_rx_queues > 1) ? "Enabled" :
2616                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2617
2618         set_bit(__IXGBE_DOWN, &adapter->state);
2619
2620         return 0;
2621
2622 err_set_interrupt:
2623         kfree(adapter->tx_ring);
2624         kfree(adapter->rx_ring);
2625 err_alloc_queues:
2626         return err;
2627 }
2628
2629 /**
2630  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2631  * @adapter: board private structure to initialize
2632  *
2633  * ixgbe_sw_init initializes the Adapter private data structure.
2634  * Fields are initialized based on PCI device information and
2635  * OS network device settings (MTU size).
2636  **/
2637 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2638 {
2639         struct ixgbe_hw *hw = &adapter->hw;
2640         struct pci_dev *pdev = adapter->pdev;
2641         unsigned int rss;
2642
2643         /* PCI config space info */
2644
2645         hw->vendor_id = pdev->vendor;
2646         hw->device_id = pdev->device;
2647         hw->revision_id = pdev->revision;
2648         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2649         hw->subsystem_device_id = pdev->subsystem_device;
2650
2651         /* Set capability flags */
2652         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2653         adapter->ring_feature[RING_F_RSS].indices = rss;
2654         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2655
2656         /* default flow control settings */
2657         hw->fc.original_type = ixgbe_fc_none;
2658         hw->fc.type = ixgbe_fc_none;
2659         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2660         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2661         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2662         hw->fc.send_xon = true;
2663
2664         /* select 10G link by default */
2665         hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2666
2667         /* enable itr by default in dynamic mode */
2668         adapter->itr_setting = 1;
2669         adapter->eitr_param = 20000;
2670
2671         /* set defaults for eitr in MegaBytes */
2672         adapter->eitr_low = 10;
2673         adapter->eitr_high = 20;
2674
2675         /* set default ring sizes */
2676         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2677         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2678
2679         /* initialize eeprom parameters */
2680         if (ixgbe_init_eeprom_params_generic(hw)) {
2681                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2682                 return -EIO;
2683         }
2684
2685         /* enable rx csum by default */
2686         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2687
2688         set_bit(__IXGBE_DOWN, &adapter->state);
2689
2690         return 0;
2691 }
2692
2693 /**
2694  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2695  * @adapter: board private structure
2696  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
2697  *
2698  * Return 0 on success, negative on failure
2699  **/
2700 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2701                              struct ixgbe_ring *tx_ring)
2702 {
2703         struct pci_dev *pdev = adapter->pdev;
2704         int size;
2705
2706         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2707         tx_ring->tx_buffer_info = vmalloc(size);
2708         if (!tx_ring->tx_buffer_info)
2709                 goto err;
2710         memset(tx_ring->tx_buffer_info, 0, size);
2711
2712         /* round up to nearest 4K */
2713         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2714                         sizeof(u32);
2715         tx_ring->size = ALIGN(tx_ring->size, 4096);
2716
2717         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2718                                              &tx_ring->dma);
2719         if (!tx_ring->desc)
2720                 goto err;
2721
2722         tx_ring->next_to_use = 0;
2723         tx_ring->next_to_clean = 0;
2724         tx_ring->work_limit = tx_ring->count;
2725         return 0;
2726
2727 err:
2728         vfree(tx_ring->tx_buffer_info);
2729         tx_ring->tx_buffer_info = NULL;
2730         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2731                             "descriptor ring\n");
2732         return -ENOMEM;
2733 }
2734
2735 /**
2736  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2737  * @adapter: board private structure
2738  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
2739  *
2740  * Returns 0 on success, negative on failure
2741  **/
2742 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2743                              struct ixgbe_ring *rx_ring)
2744 {
2745         struct pci_dev *pdev = adapter->pdev;
2746         int size;
2747
2748         size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
2749         rx_ring->lro_mgr.lro_arr = vmalloc(size);
2750         if (!rx_ring->lro_mgr.lro_arr)
2751                 return -ENOMEM;
2752         memset(rx_ring->lro_mgr.lro_arr, 0, size);
2753
2754         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2755         rx_ring->rx_buffer_info = vmalloc(size);
2756         if (!rx_ring->rx_buffer_info) {
2757                 DPRINTK(PROBE, ERR,
2758                         "vmalloc allocation failed for the rx desc ring\n");
2759                 goto alloc_failed;
2760         }
2761         memset(rx_ring->rx_buffer_info, 0, size);
2762
2763         /* Round up to nearest 4K */
2764         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2765         rx_ring->size = ALIGN(rx_ring->size, 4096);
2766
2767         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
2768
2769         if (!rx_ring->desc) {
2770                 DPRINTK(PROBE, ERR,
2771                         "Memory allocation failed for the rx desc ring\n");
2772                 vfree(rx_ring->rx_buffer_info);
2773                 goto alloc_failed;
2774         }
2775
2776         rx_ring->next_to_clean = 0;
2777         rx_ring->next_to_use = 0;
2778
2779         return 0;
2780
2781 alloc_failed:
2782         vfree(rx_ring->lro_mgr.lro_arr);
2783         rx_ring->lro_mgr.lro_arr = NULL;
2784         return -ENOMEM;
2785 }
2786
2787 /**
2788  * ixgbe_free_tx_resources - Free Tx Resources per Queue
2789  * @adapter: board private structure
2790  * @tx_ring: Tx descriptor ring for a specific queue
2791  *
2792  * Free all transmit software resources
2793  **/
2794 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2795                              struct ixgbe_ring *tx_ring)
2796 {
2797         struct pci_dev *pdev = adapter->pdev;
2798
2799         ixgbe_clean_tx_ring(adapter, tx_ring);
2800
2801         vfree(tx_ring->tx_buffer_info);
2802         tx_ring->tx_buffer_info = NULL;
2803
2804         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2805
2806         tx_ring->desc = NULL;
2807 }
2808
2809 /**
2810  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2811  * @adapter: board private structure
2812  *
2813  * Free all transmit software resources
2814  **/
2815 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2816 {
2817         int i;
2818
2819         for (i = 0; i < adapter->num_tx_queues; i++)
2820                 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2821 }
2822
2823 /**
2824  * ixgbe_ree_rx_resources - Free Rx Resources
2825  * @adapter: board private structure
2826  * @rx_ring: ring to clean the resources from
2827  *
2828  * Free all receive software resources
2829  **/
2830 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2831                              struct ixgbe_ring *rx_ring)
2832 {
2833         struct pci_dev *pdev = adapter->pdev;
2834
2835         vfree(rx_ring->lro_mgr.lro_arr);
2836         rx_ring->lro_mgr.lro_arr = NULL;
2837
2838         ixgbe_clean_rx_ring(adapter, rx_ring);
2839
2840         vfree(rx_ring->rx_buffer_info);
2841         rx_ring->rx_buffer_info = NULL;
2842
2843         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2844
2845         rx_ring->desc = NULL;
2846 }
2847
2848 /**
2849  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2850  * @adapter: board private structure
2851  *
2852  * Free all receive software resources
2853  **/
2854 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2855 {
2856         int i;
2857
2858         for (i = 0; i < adapter->num_rx_queues; i++)
2859                 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2860 }
2861
2862 /**
2863  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2864  * @adapter: board private structure
2865  *
2866  * If this function returns with an error, then it's possible one or
2867  * more of the rings is populated (while the rest are not).  It is the
2868  * callers duty to clean those orphaned rings.
2869  *
2870  * Return 0 on success, negative on failure
2871  **/
2872 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2873 {
2874         int i, err = 0;
2875
2876         for (i = 0; i < adapter->num_tx_queues; i++) {
2877                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2878                 if (err) {
2879                         DPRINTK(PROBE, ERR,
2880                                 "Allocation for Tx Queue %u failed\n", i);
2881                         break;
2882                 }
2883         }
2884
2885         return err;
2886 }
2887
2888 /**
2889  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2890  * @adapter: board private structure
2891  *
2892  * If this function returns with an error, then it's possible one or
2893  * more of the rings is populated (while the rest are not).  It is the
2894  * callers duty to clean those orphaned rings.
2895  *
2896  * Return 0 on success, negative on failure
2897  **/
2898
2899 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2900 {
2901         int i, err = 0;
2902
2903         for (i = 0; i < adapter->num_rx_queues; i++) {
2904                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2905                 if (err) {
2906                         DPRINTK(PROBE, ERR,
2907                                 "Allocation for Rx Queue %u failed\n", i);
2908                         break;
2909                 }
2910         }
2911
2912         return err;
2913 }
2914
2915 /**
2916  * ixgbe_change_mtu - Change the Maximum Transfer Unit
2917  * @netdev: network interface device structure
2918  * @new_mtu: new value for maximum frame size
2919  *
2920  * Returns 0 on success, negative on failure
2921  **/
2922 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2923 {
2924         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2925         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2926
2927         /* MTU < 68 is an error and causes problems on some kernels */
2928         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2929                 return -EINVAL;
2930
2931         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2932                 netdev->mtu, new_mtu);
2933         /* must set new MTU before calling down or up */
2934         netdev->mtu = new_mtu;
2935
2936         if (netif_running(netdev))
2937                 ixgbe_reinit_locked(adapter);
2938
2939         return 0;
2940 }
2941
2942 /**
2943  * ixgbe_open - Called when a network interface is made active
2944  * @netdev: network interface device structure
2945  *
2946  * Returns 0 on success, negative value on failure
2947  *
2948  * The open entry point is called when a network interface is made
2949  * active by the system (IFF_UP).  At this point all resources needed
2950  * for transmit and receive operations are allocated, the interrupt
2951  * handler is registered with the OS, the watchdog timer is started,
2952  * and the stack is notified that the interface is ready.
2953  **/
2954 static int ixgbe_open(struct net_device *netdev)
2955 {
2956         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2957         int err;
2958
2959         /* disallow open during test */
2960         if (test_bit(__IXGBE_TESTING, &adapter->state))
2961                 return -EBUSY;
2962
2963         /* allocate transmit descriptors */
2964         err = ixgbe_setup_all_tx_resources(adapter);
2965         if (err)
2966                 goto err_setup_tx;
2967
2968         /* allocate receive descriptors */
2969         err = ixgbe_setup_all_rx_resources(adapter);
2970         if (err)
2971                 goto err_setup_rx;
2972
2973         ixgbe_configure(adapter);
2974
2975         err = ixgbe_request_irq(adapter);
2976         if (err)
2977                 goto err_req_irq;
2978
2979         err = ixgbe_up_complete(adapter);
2980         if (err)
2981                 goto err_up;
2982
2983         netif_tx_start_all_queues(netdev);
2984
2985         return 0;
2986
2987 err_up:
2988         ixgbe_release_hw_control(adapter);
2989         ixgbe_free_irq(adapter);
2990 err_req_irq:
2991         ixgbe_free_all_rx_resources(adapter);
2992 err_setup_rx:
2993         ixgbe_free_all_tx_resources(adapter);
2994 err_setup_tx:
2995         ixgbe_reset(adapter);
2996
2997         return err;
2998 }
2999
3000 /**
3001  * ixgbe_close - Disables a network interface
3002  * @netdev: network interface device structure
3003  *
3004  * Returns 0, this is not allowed to fail
3005  *
3006  * The close entry point is called when an interface is de-activated
3007  * by the OS.  The hardware is still under the drivers control, but
3008  * needs to be disabled.  A global MAC reset is issued to stop the
3009  * hardware, and all transmit and receive resources are freed.
3010  **/
3011 static int ixgbe_close(struct net_device *netdev)
3012 {
3013         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3014
3015         ixgbe_down(adapter);
3016         ixgbe_free_irq(adapter);
3017
3018         ixgbe_free_all_tx_resources(adapter);
3019         ixgbe_free_all_rx_resources(adapter);
3020
3021         ixgbe_release_hw_control(adapter);
3022
3023         return 0;
3024 }
3025
3026 /**
3027  * ixgbe_update_stats - Update the board statistics counters.
3028  * @adapter: board private structure
3029  **/
3030 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3031 {
3032         struct ixgbe_hw *hw = &adapter->hw;
3033         u64 total_mpc = 0;
3034         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3035
3036         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3037         for (i = 0; i < 8; i++) {
3038                 /* for packet buffers not used, the register should read 0 */
3039                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3040                 missed_rx += mpc;
3041                 adapter->stats.mpc[i] += mpc;
3042                 total_mpc += adapter->stats.mpc[i];
3043                 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3044         }
3045         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3046         /* work around hardware counting issue */
3047         adapter->stats.gprc -= missed_rx;
3048
3049         /* 82598 hardware only has a 32 bit counter in the high register */
3050         adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3051         adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3052         adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3053         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3054         adapter->stats.bprc += bprc;
3055         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3056         adapter->stats.mprc -= bprc;
3057         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3058         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3059         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3060         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3061         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3062         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3063         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3064         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3065         adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3066         adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3067         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3068         adapter->stats.lxontxc += lxon;
3069         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3070         adapter->stats.lxofftxc += lxoff;
3071         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3072         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3073         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3074         /*
3075          * 82598 errata - tx of flow control packets is included in tx counters
3076          */
3077         xon_off_tot = lxon + lxoff;
3078         adapter->stats.gptc -= xon_off_tot;
3079         adapter->stats.mptc -= xon_off_tot;
3080         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3081         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3082         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3083         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3084         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3085         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3086         adapter->stats.ptc64 -= xon_off_tot;
3087         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3088         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3089         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3090         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3091         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3092         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3093
3094         /* Fill out the OS statistics structure */
3095         adapter->net_stats.multicast = adapter->stats.mprc;
3096
3097         /* Rx Errors */
3098         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3099                                                 adapter->stats.rlec;
3100         adapter->net_stats.rx_dropped = 0;
3101         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3102         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3103         adapter->net_stats.rx_missed_errors = total_mpc;
3104 }
3105
3106 /**
3107  * ixgbe_watchdog - Timer Call-back
3108  * @data: pointer to adapter cast into an unsigned long
3109  **/
3110 static void ixgbe_watchdog(unsigned long data)
3111 {
3112         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3113         struct ixgbe_hw *hw = &adapter->hw;
3114
3115         /* Do the watchdog outside of interrupt context due to the lovely
3116          * delays that some of the newer hardware requires */
3117         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3118                 /* Cause software interrupt to ensure rx rings are cleaned */
3119                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3120                         u32 eics =
3121                          (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3122                         IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3123                 } else {
3124                         /* For legacy and MSI interrupts don't set any bits that
3125                          * are enabled for EIAM, because this operation would
3126                          * set *both* EIMS and EICS for any bit in EIAM */
3127                         IXGBE_WRITE_REG(hw, IXGBE_EICS,
3128                                     (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3129                 }
3130                 /* Reset the timer */
3131                 mod_timer(&adapter->watchdog_timer,
3132                           round_jiffies(jiffies + 2 * HZ));
3133         }
3134
3135         schedule_work(&adapter->watchdog_task);
3136 }
3137
3138 /**
3139  *  ixgbe_watchdog_task - worker thread to bring link up
3140  *  @work: pointer to work_struct containing our data
3141  **/
3142 static void ixgbe_watchdog_task(struct work_struct *work)
3143 {
3144         struct ixgbe_adapter *adapter = container_of(work,
3145                                                      struct ixgbe_adapter,
3146                                                      watchdog_task);
3147         struct net_device *netdev = adapter->netdev;
3148         struct ixgbe_hw *hw = &adapter->hw;
3149         u32 link_speed = adapter->link_speed;
3150         bool link_up = adapter->link_up;
3151
3152         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3153
3154         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3155                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3156                 if (link_up ||
3157                     time_after(jiffies, (adapter->link_check_timeout +
3158                                          IXGBE_TRY_LINK_TIMEOUT))) {
3159                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3160                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3161                 }
3162                 adapter->link_up = link_up;
3163                 adapter->link_speed = link_speed;
3164         }
3165
3166         if (link_up) {
3167                 if (!netif_carrier_ok(netdev)) {
3168                         u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3169                         u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3170 #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3171 #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3172                         DPRINTK(LINK, INFO, "NIC Link is Up %s, "
3173                                 "Flow Control: %s\n",
3174                                 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3175                                  "10 Gbps" :
3176                                  (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3177                                   "1 Gbps" : "unknown speed")),
3178                                 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3179                                  (FLOW_RX ? "RX" :
3180                                  (FLOW_TX ? "TX" : "None"))));
3181
3182                         netif_carrier_on(netdev);
3183                         netif_tx_wake_all_queues(netdev);
3184                 } else {
3185                         /* Force detection of hung controller */
3186                         adapter->detect_tx_hung = true;
3187                 }
3188         } else {
3189                 adapter->link_up = false;
3190                 adapter->link_speed = 0;
3191                 if (netif_carrier_ok(netdev)) {
3192                         DPRINTK(LINK, INFO, "NIC Link is Down\n");
3193                         netif_carrier_off(netdev);
3194                         netif_tx_stop_all_queues(netdev);
3195                 }
3196         }
3197
3198         ixgbe_update_stats(adapter);
3199         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3200 }
3201
3202 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3203                          struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3204                          u32 tx_flags, u8 *hdr_len)
3205 {
3206         struct ixgbe_adv_tx_context_desc *context_desc;
3207         unsigned int i;
3208         int err;
3209         struct ixgbe_tx_buffer *tx_buffer_info;
3210         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3211         u32 mss_l4len_idx = 0, l4len;
3212
3213         if (skb_is_gso(skb)) {
3214                 if (skb_header_cloned(skb)) {
3215                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3216                         if (err)
3217                                 return err;
3218                 }
3219                 l4len = tcp_hdrlen(skb);
3220                 *hdr_len += l4len;
3221
3222                 if (skb->protocol == htons(ETH_P_IP)) {
3223                         struct iphdr *iph = ip_hdr(skb);
3224                         iph->tot_len = 0;
3225                         iph->check = 0;
3226                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3227                                                                  iph->daddr, 0,
3228                                                                  IPPROTO_TCP,
3229                                                                  0);
3230                         adapter->hw_tso_ctxt++;
3231                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3232                         ipv6_hdr(skb)->payload_len = 0;
3233                         tcp_hdr(skb)->check =
3234                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3235                                              &ipv6_hdr(skb)->daddr,
3236                                              0, IPPROTO_TCP, 0);
3237                         adapter->hw_tso6_ctxt++;
3238                 }
3239
3240                 i = tx_ring->next_to_use;
3241
3242                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3243                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3244
3245                 /* VLAN MACLEN IPLEN */
3246                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3247                         vlan_macip_lens |=
3248                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3249                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3250                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3251                 *hdr_len += skb_network_offset(skb);
3252                 vlan_macip_lens |=
3253                     (skb_transport_header(skb) - skb_network_header(skb));
3254                 *hdr_len +=
3255                     (skb_transport_header(skb) - skb_network_header(skb));
3256                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3257                 context_desc->seqnum_seed = 0;
3258
3259                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3260                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3261                                     IXGBE_ADVTXD_DTYP_CTXT);
3262
3263                 if (skb->protocol == htons(ETH_P_IP))
3264                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3265                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3266                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3267
3268                 /* MSS L4LEN IDX */
3269                 mss_l4len_idx |=
3270                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3271                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3272                 /* use index 1 for TSO */
3273                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3274                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3275
3276                 tx_buffer_info->time_stamp = jiffies;
3277                 tx_buffer_info->next_to_watch = i;
3278
3279                 i++;
3280                 if (i == tx_ring->count)
3281                         i = 0;
3282                 tx_ring->next_to_use = i;
3283
3284                 return true;
3285         }
3286         return false;
3287 }
3288
3289 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3290                                    struct ixgbe_ring *tx_ring,
3291                                    struct sk_buff *skb, u32 tx_flags)
3292 {
3293         struct ixgbe_adv_tx_context_desc *context_desc;
3294         unsigned int i;
3295         struct ixgbe_tx_buffer *tx_buffer_info;
3296         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3297
3298         if (skb->ip_summed == CHECKSUM_PARTIAL ||
3299             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3300                 i = tx_ring->next_to_use;
3301                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3302                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3303
3304                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3305                         vlan_macip_lens |=
3306                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3307                 vlan_macip_lens |= (skb_network_offset(skb) <<
3308                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3309                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3310                         vlan_macip_lens |= (skb_transport_header(skb) -
3311                                             skb_network_header(skb));
3312
3313                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3314                 context_desc->seqnum_seed = 0;
3315
3316                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3317                                     IXGBE_ADVTXD_DTYP_CTXT);
3318
3319                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3320                         switch (skb->protocol) {
3321                         case __constant_htons(ETH_P_IP):
3322                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3323                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3324                                         type_tucmd_mlhl |=
3325                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3326                                 break;
3327
3328                         case __constant_htons(ETH_P_IPV6):
3329                                 /* XXX what about other V6 headers?? */
3330                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3331                                         type_tucmd_mlhl |=
3332                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3333                                 break;
3334
3335                         default:
3336                                 if (unlikely(net_ratelimit())) {
3337                                         DPRINTK(PROBE, WARNING,
3338                                          "partial checksum but proto=%x!\n",
3339                                          skb->protocol);
3340                                 }
3341                                 break;
3342                         }
3343                 }
3344
3345                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3346                 /* use index zero for tx checksum offload */
3347                 context_desc->mss_l4len_idx = 0;
3348
3349                 tx_buffer_info->time_stamp = jiffies;
3350                 tx_buffer_info->next_to_watch = i;
3351                 adapter->hw_csum_tx_good++;
3352                 i++;
3353                 if (i == tx_ring->count)
3354                         i = 0;
3355                 tx_ring->next_to_use = i;
3356
3357                 return true;
3358         }
3359         return false;
3360 }
3361
3362 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3363                         struct ixgbe_ring *tx_ring,
3364                         struct sk_buff *skb, unsigned int first)
3365 {
3366         struct ixgbe_tx_buffer *tx_buffer_info;
3367         unsigned int len = skb->len;
3368         unsigned int offset = 0, size, count = 0, i;
3369         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3370         unsigned int f;
3371
3372         len -= skb->data_len;
3373
3374         i = tx_ring->next_to_use;
3375
3376         while (len) {
3377                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3378                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3379
3380                 tx_buffer_info->length = size;
3381                 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3382                                                   skb->data + offset,
3383                                                   size, PCI_DMA_TODEVICE);
3384                 tx_buffer_info->time_stamp = jiffies;
3385                 tx_buffer_info->next_to_watch = i;
3386
3387                 len -= size;
3388                 offset += size;
3389                 count++;
3390                 i++;
3391                 if (i == tx_ring->count)
3392                         i = 0;
3393         }
3394
3395         for (f = 0; f < nr_frags; f++) {
3396                 struct skb_frag_struct *frag;
3397
3398                 frag = &skb_shinfo(skb)->frags[f];
3399                 len = frag->size;
3400                 offset = frag->page_offset;
3401
3402                 while (len) {
3403                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
3404                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3405
3406                         tx_buffer_info->length = size;
3407                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
3408                                                         frag->page,
3409                                                         offset,
3410                                                         size, PCI_DMA_TODEVICE);
3411                         tx_buffer_info->time_stamp = jiffies;
3412                         tx_buffer_info->next_to_watch = i;
3413
3414                         len -= size;
3415                         offset += size;
3416                         count++;
3417                         i++;
3418                         if (i == tx_ring->count)
3419                                 i = 0;
3420                 }
3421         }
3422         if (i == 0)
3423                 i = tx_ring->count - 1;
3424         else
3425                 i = i - 1;
3426         tx_ring->tx_buffer_info[i].skb = skb;
3427         tx_ring->tx_buffer_info[first].next_to_watch = i;
3428
3429         return count;
3430 }
3431
3432 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3433                                struct ixgbe_ring *tx_ring,
3434                                int tx_flags, int count, u32 paylen, u8 hdr_len)
3435 {
3436         union ixgbe_adv_tx_desc *tx_desc = NULL;
3437         struct ixgbe_tx_buffer *tx_buffer_info;
3438         u32 olinfo_status = 0, cmd_type_len = 0;
3439         unsigned int i;
3440         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3441
3442         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3443
3444         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3445
3446         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3447                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3448
3449         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3450                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3451
3452                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3453                                                 IXGBE_ADVTXD_POPTS_SHIFT;
3454
3455                 /* use index 1 context for tso */
3456                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3457                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3458                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3459                                                 IXGBE_ADVTXD_POPTS_SHIFT;
3460
3461         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3462                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3463                                                 IXGBE_ADVTXD_POPTS_SHIFT;
3464
3465         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3466
3467         i = tx_ring->next_to_use;
3468         while (count--) {
3469                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3470                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3471                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3472                 tx_desc->read.cmd_type_len =
3473                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3474                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3475
3476                 i++;
3477                 if (i == tx_ring->count)
3478                         i = 0;
3479         }
3480
3481         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3482
3483         /*
3484          * Force memory writes to complete before letting h/w
3485          * know there are new descriptors to fetch.  (Only
3486          * applicable for weak-ordered memory model archs,
3487          * such as IA-64).
3488          */
3489         wmb();
3490
3491         tx_ring->next_to_use = i;
3492         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3493 }
3494
3495 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3496                                  struct ixgbe_ring *tx_ring, int size)
3497 {
3498         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3499
3500         netif_stop_subqueue(netdev, tx_ring->queue_index);
3501         /* Herbert's original patch had:
3502          *  smp_mb__after_netif_stop_queue();
3503          * but since that doesn't exist yet, just open code it. */
3504         smp_mb();
3505
3506         /* We need to check again in a case another CPU has just
3507          * made room available. */
3508         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3509                 return -EBUSY;
3510
3511         /* A reprieve! - use start_queue because it doesn't call schedule */
3512         netif_start_subqueue(netdev, tx_ring->queue_index);
3513         ++adapter->restart_queue;
3514         return 0;
3515 }
3516
3517 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3518                                struct ixgbe_ring *tx_ring, int size)
3519 {
3520         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3521                 return 0;
3522         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3523 }
3524
3525
3526 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3527 {
3528         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3529         struct ixgbe_ring *tx_ring;
3530         unsigned int len = skb->len;
3531         unsigned int first;
3532         unsigned int tx_flags = 0;
3533         u8 hdr_len = 0;
3534         int r_idx = 0, tso;
3535         unsigned int mss = 0;
3536         int count = 0;
3537         unsigned int f;
3538         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3539         len -= skb->data_len;
3540         r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3541         tx_ring = &adapter->tx_ring[r_idx];
3542
3543
3544         if (skb->len <= 0) {
3545                 dev_kfree_skb(skb);
3546                 return NETDEV_TX_OK;
3547         }
3548         mss = skb_shinfo(skb)->gso_size;
3549
3550         if (mss)
3551                 count++;
3552         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3553                 count++;
3554
3555         count += TXD_USE_COUNT(len);
3556         for (f = 0; f < nr_frags; f++)
3557                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3558
3559         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
3560                 adapter->tx_busy++;
3561                 return NETDEV_TX_BUSY;
3562         }
3563         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3564                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3565                 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3566         }
3567
3568         if (skb->protocol == htons(ETH_P_IP))
3569                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3570         first = tx_ring->next_to_use;
3571         tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3572         if (tso < 0) {
3573                 dev_kfree_skb_any(skb);
3574                 return NETDEV_TX_OK;
3575         }
3576
3577         if (tso)
3578                 tx_flags |= IXGBE_TX_FLAGS_TSO;
3579         else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3580                  (skb->ip_summed == CHECKSUM_PARTIAL))
3581                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3582
3583         ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3584                            ixgbe_tx_map(adapter, tx_ring, skb, first),
3585                            skb->len, hdr_len);
3586
3587         netdev->trans_start = jiffies;
3588
3589         ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3590
3591         return NETDEV_TX_OK;
3592 }
3593
3594 /**
3595  * ixgbe_get_stats - Get System Network Statistics
3596  * @netdev: network interface device structure
3597  *
3598  * Returns the address of the device statistics structure.
3599  * The statistics are actually updated from the timer callback.
3600  **/
3601 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3602 {
3603         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3604
3605         /* only return the current stats */
3606         return &adapter->net_stats;
3607 }
3608
3609 /**
3610  * ixgbe_set_mac - Change the Ethernet Address of the NIC
3611  * @netdev: network interface device structure
3612  * @p: pointer to an address structure
3613  *
3614  * Returns 0 on success, negative on failure
3615  **/
3616 static int ixgbe_set_mac(struct net_device *netdev, void *p)
3617 {
3618         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3619         struct sockaddr *addr = p;
3620
3621         if (!is_valid_ether_addr(addr->sa_data))
3622                 return -EADDRNOTAVAIL;
3623
3624         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3625         memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3626
3627         adapter->hw.mac.ops.set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3628
3629         return 0;
3630 }
3631
3632 #ifdef CONFIG_NET_POLL_CONTROLLER
3633 /*
3634  * Polling 'interrupt' - used by things like netconsole to send skbs
3635  * without having to re-enable interrupts. It's not called while
3636  * the interrupt routine is executing.
3637  */
3638 static void ixgbe_netpoll(struct net_device *netdev)
3639 {
3640         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3641
3642         disable_irq(adapter->pdev->irq);
3643         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3644         ixgbe_intr(adapter->pdev->irq, netdev);
3645         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3646         enable_irq(adapter->pdev->irq);
3647 }
3648 #endif
3649
3650 /**
3651  * ixgbe_link_config - set up initial link with default speed and duplex
3652  * @hw: pointer to private hardware struct
3653  *
3654  * Returns 0 on success, negative on failure
3655  **/
3656 static int ixgbe_link_config(struct ixgbe_hw *hw)
3657 {
3658         u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL;
3659
3660         /* must always autoneg for both 1G and 10G link */
3661         hw->mac.autoneg = true;
3662
3663         return hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3664 }
3665
3666 /**
3667  * ixgbe_napi_add_all - prep napi structs for use
3668  * @adapter: private struct
3669  * helper function to napi_add each possible q_vector->napi
3670  */
3671 static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3672 {
3673         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3674         int (*poll)(struct napi_struct *, int);
3675
3676         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3677                 poll = &ixgbe_clean_rxonly;
3678         } else {
3679                 poll = &ixgbe_poll;
3680                 /* only one q_vector for legacy modes */
3681                 q_vectors = 1;
3682         }
3683
3684         for (i = 0; i < q_vectors; i++) {
3685                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3686                 netif_napi_add(adapter->netdev, &q_vector->napi,
3687                                (*poll), 64);
3688         }
3689 }
3690
3691 /**
3692  * ixgbe_probe - Device Initialization Routine
3693  * @pdev: PCI device information struct
3694  * @ent: entry in ixgbe_pci_tbl
3695  *
3696  * Returns 0 on success, negative on failure
3697  *
3698  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3699  * The OS initialization, configuring of the adapter private structure,
3700  * and a hardware reset occur.
3701  **/
3702 static int __devinit ixgbe_probe(struct pci_dev *pdev,
3703                                  const struct pci_device_id *ent)
3704 {
3705         struct net_device *netdev;
3706         struct ixgbe_adapter *adapter = NULL;
3707         struct ixgbe_hw *hw;
3708         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3709         static int cards_found;
3710         int i, err, pci_using_dac;
3711         u16 link_status, link_speed, link_width;
3712         u32 part_num, eec;
3713
3714         err = pci_enable_device(pdev);
3715         if (err)
3716                 return err;
3717
3718         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3719             !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3720                 pci_using_dac = 1;
3721         } else {
3722                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3723                 if (err) {
3724                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3725                         if (err) {
3726                                 dev_err(&pdev->dev, "No usable DMA configuration, "
3727                                           "aborting\n");
3728                                 goto err_dma;
3729                         }
3730                 }
3731                 pci_using_dac = 0;
3732         }
3733
3734         err = pci_request_regions(pdev, ixgbe_driver_name);
3735         if (err) {
3736                 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3737                 goto err_pci_reg;
3738         }
3739
3740         pci_set_master(pdev);
3741         pci_save_state(pdev);
3742
3743         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
3744         if (!netdev) {
3745                 err = -ENOMEM;
3746                 goto err_alloc_etherdev;
3747         }
3748
3749         SET_NETDEV_DEV(netdev, &pdev->dev);
3750
3751         pci_set_drvdata(pdev, netdev);
3752         adapter = netdev_priv(netdev);
3753
3754         adapter->netdev = netdev;
3755         adapter->pdev = pdev;
3756         hw = &adapter->hw;
3757         hw->back = adapter;
3758         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3759
3760         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3761                               pci_resource_len(pdev, 0));
3762         if (!hw->hw_addr) {
3763                 err = -EIO;
3764                 goto err_ioremap;
3765         }
3766
3767         for (i = 1; i <= 5; i++) {
3768                 if (pci_resource_len(pdev, i) == 0)
3769                         continue;
3770         }
3771
3772         netdev->open = &ixgbe_open;
3773         netdev->stop = &ixgbe_close;
3774         netdev->hard_start_xmit = &ixgbe_xmit_frame;
3775         netdev->get_stats = &ixgbe_get_stats;
3776         netdev->set_rx_mode = &ixgbe_set_rx_mode;
3777         netdev->set_multicast_list = &ixgbe_set_rx_mode;
3778         netdev->set_mac_address = &ixgbe_set_mac;
3779         netdev->change_mtu = &ixgbe_change_mtu;
3780         ixgbe_set_ethtool_ops(netdev);
3781         netdev->tx_timeout = &ixgbe_tx_timeout;
3782         netdev->watchdog_timeo = 5 * HZ;
3783         netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3784         netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3785         netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3786 #ifdef CONFIG_NET_POLL_CONTROLLER
3787         netdev->poll_controller = ixgbe_netpoll;
3788 #endif
3789         strcpy(netdev->name, pci_name(pdev));
3790
3791         adapter->bd_number = cards_found;
3792
3793         /* Setup hw api */
3794         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3795         hw->mac.type  = ii->mac;
3796
3797         /* EEPROM */
3798         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
3799         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
3800         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
3801         if (!(eec & (1 << 8)))
3802                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
3803
3804         /* PHY */
3805         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
3806         /* phy->sfp_type = ixgbe_sfp_type_unknown; */
3807
3808         err = ii->get_invariants(hw);
3809         if (err)
3810                 goto err_hw_init;
3811
3812         /* setup the private structure */
3813         err = ixgbe_sw_init(adapter);
3814         if (err)
3815                 goto err_sw_init;
3816
3817         /* reset_hw fills in the perm_addr as well */
3818         err = hw->mac.ops.reset_hw(hw);
3819         if (err) {
3820                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
3821                 goto err_sw_init;
3822         }
3823
3824         netdev->features = NETIF_F_SG |
3825                            NETIF_F_IP_CSUM |
3826                            NETIF_F_HW_VLAN_TX |
3827                            NETIF_F_HW_VLAN_RX |
3828                            NETIF_F_HW_VLAN_FILTER;
3829
3830         netdev->features |= NETIF_F_IPV6_CSUM;
3831         netdev->features |= NETIF_F_TSO;
3832         netdev->features |= NETIF_F_TSO6;
3833         netdev->features |= NETIF_F_LRO;
3834
3835         netdev->vlan_features |= NETIF_F_TSO;
3836         netdev->vlan_features |= NETIF_F_TSO6;
3837         netdev->vlan_features |= NETIF_F_IP_CSUM;
3838         netdev->vlan_features |= NETIF_F_SG;
3839
3840         if (pci_using_dac)
3841                 netdev->features |= NETIF_F_HIGHDMA;
3842
3843         /* make sure the EEPROM is good */
3844         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
3845                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3846                 err = -EIO;
3847                 goto err_eeprom;
3848         }
3849
3850         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3851         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3852
3853         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
3854                 dev_err(&pdev->dev, "invalid MAC address\n");
3855                 err = -EIO;
3856                 goto err_eeprom;
3857         }
3858
3859         init_timer(&adapter->watchdog_timer);
3860         adapter->watchdog_timer.function = &ixgbe_watchdog;
3861         adapter->watchdog_timer.data = (unsigned long)adapter;
3862
3863         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3864         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
3865
3866         err = ixgbe_init_interrupt_scheme(adapter);
3867         if (err)
3868                 goto err_sw_init;
3869
3870         /* print bus type/speed/width info */
3871         pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3872         link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3873         link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3874         dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3875                  "%02x:%02x:%02x:%02x:%02x:%02x\n",
3876                 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3877                  (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3878                  "Unknown"),
3879                 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3880                  (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3881                  (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3882                  (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3883                  "Unknown"),
3884                 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3885                 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3886         ixgbe_read_pba_num_generic(hw, &part_num);
3887         dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3888                  hw->mac.type, hw->phy.type,
3889                  (part_num >> 8), (part_num & 0xff));
3890
3891         if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3892                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3893                          "this card is not sufficient for optimal "
3894                          "performance.\n");
3895                 dev_warn(&pdev->dev, "For optimal performance a x8 "
3896                          "PCI-Express slot is required.\n");
3897         }
3898
3899         /* reset the hardware with the new settings */
3900         hw->mac.ops.start_hw(hw);
3901
3902         /* link_config depends on start_hw being called at least once */
3903         err = ixgbe_link_config(hw);
3904         if (err) {
3905                 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
3906                 goto err_register;
3907         }
3908
3909         netif_carrier_off(netdev);
3910         netif_tx_stop_all_queues(netdev);
3911
3912         ixgbe_napi_add_all(adapter);
3913
3914         strcpy(netdev->name, "eth%d");
3915         err = register_netdev(netdev);
3916         if (err)
3917                 goto err_register;
3918
3919 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3920         if (dca_add_requester(&pdev->dev) == 0) {
3921                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3922                 /* always use CB2 mode, difference is masked
3923                  * in the CB driver */
3924                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3925                 ixgbe_setup_dca(adapter);
3926         }
3927 #endif
3928
3929         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3930         cards_found++;
3931         return 0;
3932
3933 err_register:
3934         ixgbe_release_hw_control(adapter);
3935 err_hw_init:
3936 err_sw_init:
3937         ixgbe_reset_interrupt_capability(adapter);
3938 err_eeprom:
3939         iounmap(hw->hw_addr);
3940 err_ioremap:
3941         free_netdev(netdev);
3942 err_alloc_etherdev:
3943         pci_release_regions(pdev);
3944 err_pci_reg:
3945 err_dma:
3946         pci_disable_device(pdev);
3947         return err;
3948 }
3949
3950 /**
3951  * ixgbe_remove - Device Removal Routine
3952  * @pdev: PCI device information struct
3953  *
3954  * ixgbe_remove is called by the PCI subsystem to alert the driver
3955  * that it should release a PCI device.  The could be caused by a
3956  * Hot-Plug event, or because the driver is going to be removed from
3957  * memory.
3958  **/
3959 static void __devexit ixgbe_remove(struct pci_dev *pdev)
3960 {
3961         struct net_device *netdev = pci_get_drvdata(pdev);
3962         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3963
3964         set_bit(__IXGBE_DOWN, &adapter->state);
3965         del_timer_sync(&adapter->watchdog_timer);
3966
3967         flush_scheduled_work();
3968
3969 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3970         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3971                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3972                 dca_remove_requester(&pdev->dev);
3973                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3974         }
3975
3976 #endif
3977         unregister_netdev(netdev);
3978
3979         ixgbe_reset_interrupt_capability(adapter);
3980
3981         ixgbe_release_hw_control(adapter);
3982
3983         iounmap(adapter->hw.hw_addr);
3984         pci_release_regions(pdev);
3985
3986         DPRINTK(PROBE, INFO, "complete\n");
3987         kfree(adapter->tx_ring);
3988         kfree(adapter->rx_ring);
3989
3990         free_netdev(netdev);
3991
3992         pci_disable_device(pdev);
3993 }
3994
3995 /**
3996  * ixgbe_io_error_detected - called when PCI error is detected
3997  * @pdev: Pointer to PCI device
3998  * @state: The current pci connection state
3999  *
4000  * This function is called after a PCI bus error affecting
4001  * this device has been detected.
4002  */
4003 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4004                                                 pci_channel_state_t state)
4005 {
4006         struct net_device *netdev = pci_get_drvdata(pdev);
4007         struct ixgbe_adapter *adapter = netdev->priv;
4008
4009         netif_device_detach(netdev);
4010
4011         if (netif_running(netdev))
4012                 ixgbe_down(adapter);
4013         pci_disable_device(pdev);
4014
4015         /* Request a slot slot reset. */
4016         return PCI_ERS_RESULT_NEED_RESET;
4017 }
4018
4019 /**
4020  * ixgbe_io_slot_reset - called after the pci bus has been reset.
4021  * @pdev: Pointer to PCI device
4022  *
4023  * Restart the card from scratch, as if from a cold-boot.
4024  */
4025 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4026 {
4027         struct net_device *netdev = pci_get_drvdata(pdev);
4028         struct ixgbe_adapter *adapter = netdev->priv;
4029
4030         if (pci_enable_device(pdev)) {
4031                 DPRINTK(PROBE, ERR,
4032                         "Cannot re-enable PCI device after reset.\n");
4033                 return PCI_ERS_RESULT_DISCONNECT;
4034         }
4035         pci_set_master(pdev);
4036         pci_restore_state(pdev);
4037
4038         pci_enable_wake(pdev, PCI_D3hot, 0);
4039         pci_enable_wake(pdev, PCI_D3cold, 0);
4040
4041         ixgbe_reset(adapter);
4042
4043         return PCI_ERS_RESULT_RECOVERED;
4044 }
4045
4046 /**
4047  * ixgbe_io_resume - called when traffic can start flowing again.
4048  * @pdev: Pointer to PCI device
4049  *
4050  * This callback is called when the error recovery driver tells us that
4051  * its OK to resume normal operation.
4052  */
4053 static void ixgbe_io_resume(struct pci_dev *pdev)
4054 {
4055         struct net_device *netdev = pci_get_drvdata(pdev);
4056         struct ixgbe_adapter *adapter = netdev->priv;
4057
4058         if (netif_running(netdev)) {
4059                 if (ixgbe_up(adapter)) {
4060                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4061                         return;
4062                 }
4063         }
4064
4065         netif_device_attach(netdev);
4066
4067 }
4068
4069 static struct pci_error_handlers ixgbe_err_handler = {
4070         .error_detected = ixgbe_io_error_detected,
4071         .slot_reset = ixgbe_io_slot_reset,
4072         .resume = ixgbe_io_resume,
4073 };
4074
4075 static struct pci_driver ixgbe_driver = {
4076         .name     = ixgbe_driver_name,
4077         .id_table = ixgbe_pci_tbl,
4078         .probe    = ixgbe_probe,
4079         .remove   = __devexit_p(ixgbe_remove),
4080 #ifdef CONFIG_PM
4081         .suspend  = ixgbe_suspend,
4082         .resume   = ixgbe_resume,
4083 #endif
4084         .shutdown = ixgbe_shutdown,
4085         .err_handler = &ixgbe_err_handler
4086 };
4087
4088 /**
4089  * ixgbe_init_module - Driver Registration Routine
4090  *
4091  * ixgbe_init_module is the first routine called when the driver is
4092  * loaded. All it does is register with the PCI subsystem.
4093  **/
4094 static int __init ixgbe_init_module(void)
4095 {
4096         int ret;
4097         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4098                ixgbe_driver_string, ixgbe_driver_version);
4099
4100         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4101
4102 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
4103         dca_register_notify(&dca_notifier);
4104
4105 #endif
4106         ret = pci_register_driver(&ixgbe_driver);
4107         return ret;
4108 }
4109 module_init(ixgbe_init_module);
4110
4111 /**
4112  * ixgbe_exit_module - Driver Exit Cleanup Routine
4113  *
4114  * ixgbe_exit_module is called just before the driver is removed
4115  * from memory.
4116  **/
4117 static void __exit ixgbe_exit_module(void)
4118 {
4119 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
4120         dca_unregister_notify(&dca_notifier);
4121 #endif
4122         pci_unregister_driver(&ixgbe_driver);
4123 }
4124
4125 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
4126 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4127                             void *p)
4128 {
4129         int ret_val;
4130
4131         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4132                                          __ixgbe_notify_dca);
4133
4134         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4135 }
4136 #endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
4137
4138 module_exit(ixgbe_exit_module);
4139
4140 /* ixgbe_main.c */