1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
44 #include "ixgbe_common.h"
46 char ixgbe_driver_name[] = "ixgbe";
47 static const char ixgbe_driver_string[] =
48 "Intel(R) 10 Gigabit PCI Express Network Driver";
50 #define DRV_VERSION "1.3.56-k2"
51 const char ixgbe_driver_version[] = DRV_VERSION;
52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
55 [board_82598] = &ixgbe_82598_info,
58 /* ixgbe_pci_tbl - PCI Device ID Table
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
66 static struct pci_device_id ixgbe_pci_tbl[] = {
67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 /* required last entry */
93 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
95 #ifdef CONFIG_IXGBE_DCA
96 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
98 static struct notifier_block dca_notifier = {
99 .notifier_call = ixgbe_notify_dca,
105 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
106 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
107 MODULE_LICENSE("GPL");
108 MODULE_VERSION(DRV_VERSION);
110 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
112 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
116 /* Let firmware take over control of h/w */
117 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
118 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
119 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
122 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
126 /* Let firmware know the driver has taken over */
127 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
128 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
129 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
132 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
137 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
138 index = (int_alloc_entry >> 2) & 0x1F;
139 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
140 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
141 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
142 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
145 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
146 struct ixgbe_tx_buffer
149 if (tx_buffer_info->dma) {
150 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
151 tx_buffer_info->length, PCI_DMA_TODEVICE);
152 tx_buffer_info->dma = 0;
154 if (tx_buffer_info->skb) {
155 dev_kfree_skb_any(tx_buffer_info->skb);
156 tx_buffer_info->skb = NULL;
158 /* tx_buffer_info must be completely set up in the transmit path */
161 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
162 struct ixgbe_ring *tx_ring,
165 struct ixgbe_hw *hw = &adapter->hw;
168 /* Detect a transmit hang in hardware, this serializes the
169 * check with the clearing of time_stamp and movement of eop */
170 head = IXGBE_READ_REG(hw, tx_ring->head);
171 tail = IXGBE_READ_REG(hw, tx_ring->tail);
172 adapter->detect_tx_hung = false;
173 if ((head != tail) &&
174 tx_ring->tx_buffer_info[eop].time_stamp &&
175 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
176 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
177 /* detected Tx unit hang */
178 union ixgbe_adv_tx_desc *tx_desc;
179 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
180 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
182 " TDH, TDT <%x>, <%x>\n"
183 " next_to_use <%x>\n"
184 " next_to_clean <%x>\n"
185 "tx_buffer_info[next_to_clean]\n"
186 " time_stamp <%lx>\n"
188 tx_ring->queue_index,
190 tx_ring->next_to_use, eop,
191 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
198 #define IXGBE_MAX_TXD_PWR 14
199 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
201 /* Tx Descriptors needed, worst case */
202 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
203 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
204 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
205 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
207 #define GET_TX_HEAD_FROM_RING(ring) (\
209 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
210 static void ixgbe_tx_timeout(struct net_device *netdev);
213 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
214 * @adapter: board private structure
215 * @tx_ring: tx ring to clean
217 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
218 struct ixgbe_ring *tx_ring)
220 union ixgbe_adv_tx_desc *tx_desc;
221 struct ixgbe_tx_buffer *tx_buffer_info;
222 struct net_device *netdev = adapter->netdev;
226 unsigned int count = 0;
227 unsigned int total_bytes = 0, total_packets = 0;
230 head = GET_TX_HEAD_FROM_RING(tx_ring);
231 head = le32_to_cpu(head);
232 i = tx_ring->next_to_clean;
235 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
236 tx_buffer_info = &tx_ring->tx_buffer_info[i];
237 skb = tx_buffer_info->skb;
240 unsigned int segs, bytecount;
242 /* gso_segs is currently only valid for tcp */
243 segs = skb_shinfo(skb)->gso_segs ?: 1;
244 /* multiply data chunks by size of headers */
245 bytecount = ((segs - 1) * skb_headlen(skb)) +
247 total_packets += segs;
248 total_bytes += bytecount;
251 ixgbe_unmap_and_free_tx_resource(adapter,
255 if (i == tx_ring->count)
259 if (count == tx_ring->count)
264 head = GET_TX_HEAD_FROM_RING(tx_ring);
265 head = le32_to_cpu(head);
271 tx_ring->next_to_clean = i;
273 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
274 if (unlikely(count && netif_carrier_ok(netdev) &&
275 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
276 /* Make sure that anybody stopping the queue after this
277 * sees the new next_to_clean.
280 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
281 !test_bit(__IXGBE_DOWN, &adapter->state)) {
282 netif_wake_subqueue(netdev, tx_ring->queue_index);
283 ++adapter->restart_queue;
287 if (adapter->detect_tx_hung) {
288 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
289 /* schedule immediate reset if we believe we hung */
291 "tx hang %d detected, resetting adapter\n",
292 adapter->tx_timeout_count + 1);
293 ixgbe_tx_timeout(adapter->netdev);
297 /* re-arm the interrupt */
298 if ((total_packets >= tx_ring->work_limit) ||
299 (count == tx_ring->count))
300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
302 tx_ring->total_bytes += total_bytes;
303 tx_ring->total_packets += total_packets;
304 tx_ring->stats.bytes += total_bytes;
305 tx_ring->stats.packets += total_packets;
306 adapter->net_stats.tx_bytes += total_bytes;
307 adapter->net_stats.tx_packets += total_packets;
308 return (total_packets ? true : false);
311 #ifdef CONFIG_IXGBE_DCA
312 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
313 struct ixgbe_ring *rx_ring)
317 int q = rx_ring - adapter->rx_ring;
319 if (rx_ring->cpu != cpu) {
320 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
321 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
322 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
323 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
324 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
325 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
326 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
327 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
328 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
334 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
335 struct ixgbe_ring *tx_ring)
339 int q = tx_ring - adapter->tx_ring;
341 if (tx_ring->cpu != cpu) {
342 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
343 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
344 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
345 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
346 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
352 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
356 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
359 for (i = 0; i < adapter->num_tx_queues; i++) {
360 adapter->tx_ring[i].cpu = -1;
361 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
363 for (i = 0; i < adapter->num_rx_queues; i++) {
364 adapter->rx_ring[i].cpu = -1;
365 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
369 static int __ixgbe_notify_dca(struct device *dev, void *data)
371 struct net_device *netdev = dev_get_drvdata(dev);
372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
373 unsigned long event = *(unsigned long *)data;
376 case DCA_PROVIDER_ADD:
377 /* if we're already enabled, don't do it again */
378 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
380 /* Always use CB2 mode, difference is masked
381 * in the CB driver. */
382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
383 if (dca_add_requester(dev) == 0) {
384 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
385 ixgbe_setup_dca(adapter);
388 /* Fall Through since DCA is disabled. */
389 case DCA_PROVIDER_REMOVE:
390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
391 dca_remove_requester(dev);
392 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
401 #endif /* CONFIG_IXGBE_DCA */
403 * ixgbe_receive_skb - Send a completed packet up the stack
404 * @adapter: board private structure
405 * @skb: packet to send up
406 * @status: hardware indication of status of receive
407 * @rx_ring: rx descriptor ring (for a specific queue) to setup
408 * @rx_desc: rx descriptor
410 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
411 struct sk_buff *skb, u8 status,
412 union ixgbe_adv_rx_desc *rx_desc)
414 struct ixgbe_adapter *adapter = q_vector->adapter;
415 struct napi_struct *napi = &q_vector->napi;
416 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
417 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
419 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
420 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
421 if (adapter->vlgrp && is_vlan && (tag != 0))
422 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
424 napi_gro_receive(napi, skb);
426 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
427 if (adapter->vlgrp && is_vlan && (tag != 0))
428 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
430 netif_receive_skb(skb);
432 if (adapter->vlgrp && is_vlan && (tag != 0))
433 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
441 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
442 * @adapter: address of board private structure
443 * @status_err: hardware indication of status of receive
444 * @skb: skb currently being received and modified
446 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
447 u32 status_err, struct sk_buff *skb)
449 skb->ip_summed = CHECKSUM_NONE;
451 /* Rx csum disabled */
452 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
455 /* if IP and error */
456 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
457 (status_err & IXGBE_RXDADV_ERR_IPE)) {
458 adapter->hw_csum_rx_error++;
462 if (!(status_err & IXGBE_RXD_STAT_L4CS))
465 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
466 adapter->hw_csum_rx_error++;
470 /* It must be a TCP or UDP packet with a valid checksum */
471 skb->ip_summed = CHECKSUM_UNNECESSARY;
472 adapter->hw_csum_rx_good++;
476 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
477 * @adapter: address of board private structure
479 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
480 struct ixgbe_ring *rx_ring,
483 struct pci_dev *pdev = adapter->pdev;
484 union ixgbe_adv_rx_desc *rx_desc;
485 struct ixgbe_rx_buffer *bi;
488 i = rx_ring->next_to_use;
489 bi = &rx_ring->rx_buffer_info[i];
491 while (cleaned_count--) {
492 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
495 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
497 bi->page = alloc_page(GFP_ATOMIC);
499 adapter->alloc_rx_page_failed++;
504 /* use a half page if we're re-using */
505 bi->page_offset ^= (PAGE_SIZE / 2);
508 bi->page_dma = pci_map_page(pdev, bi->page,
516 skb = netdev_alloc_skb(adapter->netdev,
517 (rx_ring->rx_buf_len +
521 adapter->alloc_rx_buff_failed++;
526 * Make buffer alignment 2 beyond a 16 byte boundary
527 * this will result in a 16 byte aligned IP header after
528 * the 14 byte MAC header is removed
530 skb_reserve(skb, NET_IP_ALIGN);
533 bi->dma = pci_map_single(pdev, skb->data,
537 /* Refresh the desc even if buffer_addrs didn't change because
538 * each write-back erases this info. */
539 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
540 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
541 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
543 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
547 if (i == rx_ring->count)
549 bi = &rx_ring->rx_buffer_info[i];
553 if (rx_ring->next_to_use != i) {
554 rx_ring->next_to_use = i;
556 i = (rx_ring->count - 1);
559 * Force memory writes to complete before letting h/w
560 * know there are new descriptors to fetch. (Only
561 * applicable for weak-ordered memory model archs,
565 writel(i, adapter->hw.hw_addr + rx_ring->tail);
569 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
571 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
574 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
576 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
579 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
580 struct ixgbe_ring *rx_ring,
581 int *work_done, int work_to_do)
583 struct ixgbe_adapter *adapter = q_vector->adapter;
584 struct pci_dev *pdev = adapter->pdev;
585 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
586 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
591 bool cleaned = false;
592 int cleaned_count = 0;
593 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
595 i = rx_ring->next_to_clean;
596 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
597 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
598 rx_buffer_info = &rx_ring->rx_buffer_info[i];
600 while (staterr & IXGBE_RXD_STAT_DD) {
602 if (*work_done >= work_to_do)
606 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
607 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
608 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
609 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
610 if (hdr_info & IXGBE_RXDADV_SPH)
611 adapter->rx_hdr_split++;
612 if (len > IXGBE_RX_HDR_SIZE)
613 len = IXGBE_RX_HDR_SIZE;
614 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
616 len = le16_to_cpu(rx_desc->wb.upper.length);
620 skb = rx_buffer_info->skb;
621 prefetch(skb->data - NET_IP_ALIGN);
622 rx_buffer_info->skb = NULL;
624 if (len && !skb_shinfo(skb)->nr_frags) {
625 pci_unmap_single(pdev, rx_buffer_info->dma,
632 pci_unmap_page(pdev, rx_buffer_info->page_dma,
633 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
634 rx_buffer_info->page_dma = 0;
635 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
636 rx_buffer_info->page,
637 rx_buffer_info->page_offset,
640 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
641 (page_count(rx_buffer_info->page) != 1))
642 rx_buffer_info->page = NULL;
644 get_page(rx_buffer_info->page);
646 skb->len += upper_len;
647 skb->data_len += upper_len;
648 skb->truesize += upper_len;
652 if (i == rx_ring->count)
654 next_buffer = &rx_ring->rx_buffer_info[i];
656 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
660 if (staterr & IXGBE_RXD_STAT_EOP) {
661 rx_ring->stats.packets++;
662 rx_ring->stats.bytes += skb->len;
664 rx_buffer_info->skb = next_buffer->skb;
665 rx_buffer_info->dma = next_buffer->dma;
666 next_buffer->skb = skb;
667 next_buffer->dma = 0;
668 adapter->non_eop_descs++;
672 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
673 dev_kfree_skb_irq(skb);
677 ixgbe_rx_checksum(adapter, staterr, skb);
679 /* probably a little skewed due to removing CRC */
680 total_rx_bytes += skb->len;
683 skb->protocol = eth_type_trans(skb, adapter->netdev);
684 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
687 rx_desc->wb.upper.status_error = 0;
689 /* return some buffers to hardware, one at a time is too slow */
690 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
691 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
695 /* use prefetched values */
697 rx_buffer_info = next_buffer;
699 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
702 rx_ring->next_to_clean = i;
703 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
706 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
708 rx_ring->total_packets += total_rx_packets;
709 rx_ring->total_bytes += total_rx_bytes;
710 adapter->net_stats.rx_bytes += total_rx_bytes;
711 adapter->net_stats.rx_packets += total_rx_packets;
716 static int ixgbe_clean_rxonly(struct napi_struct *, int);
718 * ixgbe_configure_msix - Configure MSI-X hardware
719 * @adapter: board private structure
721 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
724 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
726 struct ixgbe_q_vector *q_vector;
727 int i, j, q_vectors, v_idx, r_idx;
730 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
732 /* Populate the IVAR table and set the ITR values to the
733 * corresponding register.
735 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
736 q_vector = &adapter->q_vector[v_idx];
737 /* XXX for_each_bit(...) */
738 r_idx = find_first_bit(q_vector->rxr_idx,
739 adapter->num_rx_queues);
741 for (i = 0; i < q_vector->rxr_count; i++) {
742 j = adapter->rx_ring[r_idx].reg_idx;
743 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
744 r_idx = find_next_bit(q_vector->rxr_idx,
745 adapter->num_rx_queues,
748 r_idx = find_first_bit(q_vector->txr_idx,
749 adapter->num_tx_queues);
751 for (i = 0; i < q_vector->txr_count; i++) {
752 j = adapter->tx_ring[r_idx].reg_idx;
753 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
754 r_idx = find_next_bit(q_vector->txr_idx,
755 adapter->num_tx_queues,
759 /* if this is a tx only vector halve the interrupt rate */
760 if (q_vector->txr_count && !q_vector->rxr_count)
761 q_vector->eitr = (adapter->eitr_param >> 1);
764 q_vector->eitr = adapter->eitr_param;
766 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
767 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
770 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
771 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
773 /* set up to autoclear timer, and the vectors */
774 mask = IXGBE_EIMS_ENABLE_MASK;
775 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
776 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
783 latency_invalid = 255
787 * ixgbe_update_itr - update the dynamic ITR value based on statistics
788 * @adapter: pointer to adapter
789 * @eitr: eitr setting (ints per sec) to give last timeslice
790 * @itr_setting: current throttle rate in ints/second
791 * @packets: the number of packets during this measurement interval
792 * @bytes: the number of bytes during this measurement interval
794 * Stores a new ITR value based on packets and byte
795 * counts during the last interrupt. The advantage of per interrupt
796 * computation is faster updates and more accurate ITR for the current
797 * traffic pattern. Constants in this function were computed
798 * based on theoretical maximum wire speed and thresholds were set based
799 * on testing data as well as attempting to minimize response time
800 * while increasing bulk throughput.
801 * this functionality is controlled by the InterruptThrottleRate module
802 * parameter (see ixgbe_param.c)
804 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
805 u32 eitr, u8 itr_setting,
806 int packets, int bytes)
808 unsigned int retval = itr_setting;
813 goto update_itr_done;
816 /* simple throttlerate management
817 * 0-20MB/s lowest (100000 ints/s)
818 * 20-100MB/s low (20000 ints/s)
819 * 100-1249MB/s bulk (8000 ints/s)
821 /* what was last interrupt timeslice? */
822 timepassed_us = 1000000/eitr;
823 bytes_perint = bytes / timepassed_us; /* bytes/usec */
825 switch (itr_setting) {
827 if (bytes_perint > adapter->eitr_low)
828 retval = low_latency;
831 if (bytes_perint > adapter->eitr_high)
832 retval = bulk_latency;
833 else if (bytes_perint <= adapter->eitr_low)
834 retval = lowest_latency;
837 if (bytes_perint <= adapter->eitr_high)
838 retval = low_latency;
846 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
848 struct ixgbe_adapter *adapter = q_vector->adapter;
849 struct ixgbe_hw *hw = &adapter->hw;
851 u8 current_itr, ret_itr;
852 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
853 sizeof(struct ixgbe_q_vector);
854 struct ixgbe_ring *rx_ring, *tx_ring;
856 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
857 for (i = 0; i < q_vector->txr_count; i++) {
858 tx_ring = &(adapter->tx_ring[r_idx]);
859 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
861 tx_ring->total_packets,
862 tx_ring->total_bytes);
863 /* if the result for this queue would decrease interrupt
864 * rate for this vector then use that result */
865 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
866 q_vector->tx_itr - 1 : ret_itr);
867 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
871 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
872 for (i = 0; i < q_vector->rxr_count; i++) {
873 rx_ring = &(adapter->rx_ring[r_idx]);
874 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
876 rx_ring->total_packets,
877 rx_ring->total_bytes);
878 /* if the result for this queue would decrease interrupt
879 * rate for this vector then use that result */
880 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
881 q_vector->rx_itr - 1 : ret_itr);
882 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
886 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
888 switch (current_itr) {
889 /* counts and packets in update_itr are dependent on these numbers */
894 new_itr = 20000; /* aka hwitr = ~200 */
902 if (new_itr != q_vector->eitr) {
904 /* do an exponential smoothing */
905 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
906 q_vector->eitr = new_itr;
907 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
908 /* must write high and low 16 bits to reset counter */
909 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
911 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
917 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
919 struct ixgbe_hw *hw = &adapter->hw;
921 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
922 (eicr & IXGBE_EICR_GPI_SDP1)) {
923 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
924 /* write to clear the interrupt */
925 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
929 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
931 struct ixgbe_hw *hw = &adapter->hw;
934 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
935 adapter->link_check_timeout = jiffies;
936 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
937 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
938 schedule_work(&adapter->watchdog_task);
942 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
944 struct net_device *netdev = data;
945 struct ixgbe_adapter *adapter = netdev_priv(netdev);
946 struct ixgbe_hw *hw = &adapter->hw;
947 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
949 if (eicr & IXGBE_EICR_LSC)
950 ixgbe_check_lsc(adapter);
952 ixgbe_check_fan_failure(adapter, eicr);
954 if (!test_bit(__IXGBE_DOWN, &adapter->state))
955 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
960 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
962 struct ixgbe_q_vector *q_vector = data;
963 struct ixgbe_adapter *adapter = q_vector->adapter;
964 struct ixgbe_ring *tx_ring;
967 if (!q_vector->txr_count)
970 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
971 for (i = 0; i < q_vector->txr_count; i++) {
972 tx_ring = &(adapter->tx_ring[r_idx]);
973 #ifdef CONFIG_IXGBE_DCA
974 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
975 ixgbe_update_tx_dca(adapter, tx_ring);
977 tx_ring->total_bytes = 0;
978 tx_ring->total_packets = 0;
979 ixgbe_clean_tx_irq(adapter, tx_ring);
980 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
988 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
990 * @data: pointer to our q_vector struct for this interrupt vector
992 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
994 struct ixgbe_q_vector *q_vector = data;
995 struct ixgbe_adapter *adapter = q_vector->adapter;
996 struct ixgbe_ring *rx_ring;
1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1001 for (i = 0; i < q_vector->rxr_count; i++) {
1002 rx_ring = &(adapter->rx_ring[r_idx]);
1003 rx_ring->total_bytes = 0;
1004 rx_ring->total_packets = 0;
1005 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1009 if (!q_vector->rxr_count)
1012 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1013 rx_ring = &(adapter->rx_ring[r_idx]);
1014 /* disable interrupts on this vector only */
1015 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1016 napi_schedule(&q_vector->napi);
1021 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1023 ixgbe_msix_clean_rx(irq, data);
1024 ixgbe_msix_clean_tx(irq, data);
1030 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1031 * @napi: napi struct with our devices info in it
1032 * @budget: amount of work driver is allowed to do this pass, in packets
1034 * This function is optimized for cleaning one queue only on a single
1037 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1039 struct ixgbe_q_vector *q_vector =
1040 container_of(napi, struct ixgbe_q_vector, napi);
1041 struct ixgbe_adapter *adapter = q_vector->adapter;
1042 struct ixgbe_ring *rx_ring = NULL;
1046 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1047 rx_ring = &(adapter->rx_ring[r_idx]);
1048 #ifdef CONFIG_IXGBE_DCA
1049 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1050 ixgbe_update_rx_dca(adapter, rx_ring);
1053 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1055 /* If all Rx work done, exit the polling mode */
1056 if (work_done < budget) {
1057 napi_complete(napi);
1058 if (adapter->itr_setting & 3)
1059 ixgbe_set_itr_msix(q_vector);
1060 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1061 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1068 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1069 * @napi: napi struct with our devices info in it
1070 * @budget: amount of work driver is allowed to do this pass, in packets
1072 * This function will clean more than one rx queue associated with a
1075 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1077 struct ixgbe_q_vector *q_vector =
1078 container_of(napi, struct ixgbe_q_vector, napi);
1079 struct ixgbe_adapter *adapter = q_vector->adapter;
1080 struct ixgbe_ring *rx_ring = NULL;
1081 int work_done = 0, i;
1083 u16 enable_mask = 0;
1085 /* attempt to distribute budget to each queue fairly, but don't allow
1086 * the budget to go below 1 because we'll exit polling */
1087 budget /= (q_vector->rxr_count ?: 1);
1088 budget = max(budget, 1);
1089 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1090 for (i = 0; i < q_vector->rxr_count; i++) {
1091 rx_ring = &(adapter->rx_ring[r_idx]);
1092 #ifdef CONFIG_IXGBE_DCA
1093 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1094 ixgbe_update_rx_dca(adapter, rx_ring);
1096 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1097 enable_mask |= rx_ring->v_idx;
1098 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1102 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1103 rx_ring = &(adapter->rx_ring[r_idx]);
1104 /* If all Rx work done, exit the polling mode */
1105 if (work_done < budget) {
1106 napi_complete(napi);
1107 if (adapter->itr_setting & 3)
1108 ixgbe_set_itr_msix(q_vector);
1109 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1110 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1116 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1119 a->q_vector[v_idx].adapter = a;
1120 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1121 a->q_vector[v_idx].rxr_count++;
1122 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1125 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1128 a->q_vector[v_idx].adapter = a;
1129 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1130 a->q_vector[v_idx].txr_count++;
1131 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1135 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1136 * @adapter: board private structure to initialize
1137 * @vectors: allotted vector count for descriptor rings
1139 * This function maps descriptor rings to the queue-specific vectors
1140 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1141 * one vector per ring/queue, but on a constrained vector budget, we
1142 * group the rings as "efficiently" as possible. You would add new
1143 * mapping configurations in here.
1145 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1149 int rxr_idx = 0, txr_idx = 0;
1150 int rxr_remaining = adapter->num_rx_queues;
1151 int txr_remaining = adapter->num_tx_queues;
1156 /* No mapping required if MSI-X is disabled. */
1157 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1161 * The ideal configuration...
1162 * We have enough vectors to map one per queue.
1164 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1165 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1166 map_vector_to_rxq(adapter, v_start, rxr_idx);
1168 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1169 map_vector_to_txq(adapter, v_start, txr_idx);
1175 * If we don't have enough vectors for a 1-to-1
1176 * mapping, we'll have to group them so there are
1177 * multiple queues per vector.
1179 /* Re-adjusting *qpv takes care of the remainder. */
1180 for (i = v_start; i < vectors; i++) {
1181 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1182 for (j = 0; j < rqpv; j++) {
1183 map_vector_to_rxq(adapter, i, rxr_idx);
1188 for (i = v_start; i < vectors; i++) {
1189 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1190 for (j = 0; j < tqpv; j++) {
1191 map_vector_to_txq(adapter, i, txr_idx);
1202 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1203 * @adapter: board private structure
1205 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1206 * interrupts from the kernel.
1208 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1210 struct net_device *netdev = adapter->netdev;
1211 irqreturn_t (*handler)(int, void *);
1212 int i, vector, q_vectors, err;
1215 /* Decrement for Other and TCP Timer vectors */
1216 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1218 /* Map the Tx/Rx rings to the vectors we were allotted. */
1219 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1223 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1224 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1225 &ixgbe_msix_clean_many)
1226 for (vector = 0; vector < q_vectors; vector++) {
1227 handler = SET_HANDLER(&adapter->q_vector[vector]);
1229 if(handler == &ixgbe_msix_clean_rx) {
1230 sprintf(adapter->name[vector], "%s-%s-%d",
1231 netdev->name, "rx", ri++);
1233 else if(handler == &ixgbe_msix_clean_tx) {
1234 sprintf(adapter->name[vector], "%s-%s-%d",
1235 netdev->name, "tx", ti++);
1238 sprintf(adapter->name[vector], "%s-%s-%d",
1239 netdev->name, "TxRx", vector);
1241 err = request_irq(adapter->msix_entries[vector].vector,
1242 handler, 0, adapter->name[vector],
1243 &(adapter->q_vector[vector]));
1246 "request_irq failed for MSIX interrupt "
1247 "Error: %d\n", err);
1248 goto free_queue_irqs;
1252 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1253 err = request_irq(adapter->msix_entries[vector].vector,
1254 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1257 "request_irq for msix_lsc failed: %d\n", err);
1258 goto free_queue_irqs;
1264 for (i = vector - 1; i >= 0; i--)
1265 free_irq(adapter->msix_entries[--vector].vector,
1266 &(adapter->q_vector[i]));
1267 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1268 pci_disable_msix(adapter->pdev);
1269 kfree(adapter->msix_entries);
1270 adapter->msix_entries = NULL;
1275 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1277 struct ixgbe_hw *hw = &adapter->hw;
1278 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1280 u32 new_itr = q_vector->eitr;
1281 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1282 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1284 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1286 tx_ring->total_packets,
1287 tx_ring->total_bytes);
1288 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1290 rx_ring->total_packets,
1291 rx_ring->total_bytes);
1293 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1295 switch (current_itr) {
1296 /* counts and packets in update_itr are dependent on these numbers */
1297 case lowest_latency:
1301 new_itr = 20000; /* aka hwitr = ~200 */
1310 if (new_itr != q_vector->eitr) {
1312 /* do an exponential smoothing */
1313 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1314 q_vector->eitr = new_itr;
1315 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1316 /* must write high and low 16 bits to reset counter */
1317 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1324 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1325 * @adapter: board private structure
1327 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1329 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1330 IXGBE_WRITE_FLUSH(&adapter->hw);
1331 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1333 for (i = 0; i < adapter->num_msix_vectors; i++)
1334 synchronize_irq(adapter->msix_entries[i].vector);
1336 synchronize_irq(adapter->pdev->irq);
1341 * ixgbe_irq_enable - Enable default interrupt generation settings
1342 * @adapter: board private structure
1344 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1347 mask = IXGBE_EIMS_ENABLE_MASK;
1348 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1349 mask |= IXGBE_EIMS_GPI_SDP1;
1350 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1351 IXGBE_WRITE_FLUSH(&adapter->hw);
1355 * ixgbe_intr - legacy mode Interrupt Handler
1356 * @irq: interrupt number
1357 * @data: pointer to a network interface device structure
1359 static irqreturn_t ixgbe_intr(int irq, void *data)
1361 struct net_device *netdev = data;
1362 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1363 struct ixgbe_hw *hw = &adapter->hw;
1366 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1367 * therefore no explict interrupt disable is necessary */
1368 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1370 /* shared interrupt alert!
1371 * make sure interrupts are enabled because the read will
1372 * have disabled interrupts due to EIAM */
1373 ixgbe_irq_enable(adapter);
1374 return IRQ_NONE; /* Not our interrupt */
1377 if (eicr & IXGBE_EICR_LSC)
1378 ixgbe_check_lsc(adapter);
1380 ixgbe_check_fan_failure(adapter, eicr);
1382 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1383 adapter->tx_ring[0].total_packets = 0;
1384 adapter->tx_ring[0].total_bytes = 0;
1385 adapter->rx_ring[0].total_packets = 0;
1386 adapter->rx_ring[0].total_bytes = 0;
1387 /* would disable interrupts here but EIAM disabled it */
1388 __napi_schedule(&adapter->q_vector[0].napi);
1394 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1396 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1398 for (i = 0; i < q_vectors; i++) {
1399 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1400 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1401 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1402 q_vector->rxr_count = 0;
1403 q_vector->txr_count = 0;
1408 * ixgbe_request_irq - initialize interrupts
1409 * @adapter: board private structure
1411 * Attempts to configure interrupts using the best available
1412 * capabilities of the hardware and kernel.
1414 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1416 struct net_device *netdev = adapter->netdev;
1419 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1420 err = ixgbe_request_msix_irqs(adapter);
1421 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1422 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1423 netdev->name, netdev);
1425 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1426 netdev->name, netdev);
1430 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1435 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1437 struct net_device *netdev = adapter->netdev;
1439 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1442 q_vectors = adapter->num_msix_vectors;
1445 free_irq(adapter->msix_entries[i].vector, netdev);
1448 for (; i >= 0; i--) {
1449 free_irq(adapter->msix_entries[i].vector,
1450 &(adapter->q_vector[i]));
1453 ixgbe_reset_q_vectors(adapter);
1455 free_irq(adapter->pdev->irq, netdev);
1460 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1463 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1465 struct ixgbe_hw *hw = &adapter->hw;
1467 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1468 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1470 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
1471 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1473 map_vector_to_rxq(adapter, 0, 0);
1474 map_vector_to_txq(adapter, 0, 0);
1476 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1480 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1481 * @adapter: board private structure
1483 * Configure the Tx unit of the MAC after a reset.
1485 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1488 struct ixgbe_hw *hw = &adapter->hw;
1489 u32 i, j, tdlen, txctrl;
1491 /* Setup the HW Tx Head and Tail descriptor pointers */
1492 for (i = 0; i < adapter->num_tx_queues; i++) {
1493 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1496 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1497 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1498 (tdba & DMA_32BIT_MASK));
1499 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1501 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1502 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1503 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1504 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
1505 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1506 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1507 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1508 adapter->tx_ring[i].head = IXGBE_TDH(j);
1509 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1510 /* Disable Tx Head Writeback RO bit, since this hoses
1511 * bookkeeping if things aren't delivered in order.
1513 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1514 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1515 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1519 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1521 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1523 struct ixgbe_ring *rx_ring;
1528 /* program one srrctl register per VMDq index */
1529 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1531 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1532 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1533 shift = find_first_bit(&mask, len);
1534 queue0 = index & mask;
1535 index = (index & mask) >> shift;
1536 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
1538 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1539 queue0 = index & mask;
1540 index = index & mask;
1543 rx_ring = &adapter->rx_ring[queue0];
1545 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1547 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1548 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1550 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1551 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1552 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1553 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1554 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1555 IXGBE_SRRCTL_BSIZEHDR_MASK);
1557 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1559 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1560 srrctl |= IXGBE_RXBUFFER_2048 >>
1561 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1563 srrctl |= rx_ring->rx_buf_len >>
1564 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1566 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1569 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1570 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1573 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1574 * @adapter: board private structure
1576 * Configure the Rx unit of the MAC after a reset.
1578 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1581 struct ixgbe_hw *hw = &adapter->hw;
1582 struct net_device *netdev = adapter->netdev;
1583 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1585 u32 rdlen, rxctrl, rxcsum;
1586 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1587 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1588 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1595 /* Decide whether to use packet split mode or not */
1596 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1598 /* Set the RX buffer length according to the mode */
1599 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1600 rx_buf_len = IXGBE_RX_HDR_SIZE;
1602 if (netdev->mtu <= ETH_DATA_LEN)
1603 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1605 rx_buf_len = ALIGN(max_frame, 1024);
1608 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1609 fctrl |= IXGBE_FCTRL_BAM;
1610 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1613 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1614 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1615 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1617 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1618 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1620 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1622 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1623 /* disable receives while setting up the descriptors */
1624 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1625 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1627 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1628 * the Base and Length of the Rx Descriptor Ring */
1629 for (i = 0; i < adapter->num_rx_queues; i++) {
1630 rdba = adapter->rx_ring[i].dma;
1631 j = adapter->rx_ring[i].reg_idx;
1632 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1633 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1634 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1635 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1636 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1637 adapter->rx_ring[i].head = IXGBE_RDH(j);
1638 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1639 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1641 ixgbe_configure_srrctl(adapter, j);
1645 * For VMDq support of different descriptor types or
1646 * buffer sizes through the use of multiple SRRCTL
1647 * registers, RDRXCTL.MVMEN must be set to 1
1649 * also, the manual doesn't mention it clearly but DCA hints
1650 * will only use queue 0's tags unless this bit is set. Side
1651 * effects of setting this bit are only that SRRCTL must be
1652 * fully programmed [0..15]
1654 if (adapter->flags &
1655 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1656 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1657 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1658 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1661 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1662 /* Fill out redirection table */
1663 for (i = 0, j = 0; i < 128; i++, j++) {
1664 if (j == adapter->ring_feature[RING_F_RSS].indices)
1666 /* reta = 4-byte sliding window of
1667 * 0x00..(indices-1)(indices-1)00..etc. */
1668 reta = (reta << 8) | (j * 0x11);
1670 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1673 /* Fill out hash function seeds */
1674 for (i = 0; i < 10; i++)
1675 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1677 mrqc = IXGBE_MRQC_RSSEN
1678 /* Perform hash on these packet types */
1679 | IXGBE_MRQC_RSS_FIELD_IPV4
1680 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1681 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1682 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1683 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1684 | IXGBE_MRQC_RSS_FIELD_IPV6
1685 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1686 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1687 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1688 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1691 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1693 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1694 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1695 /* Disable indicating checksum in descriptor, enables
1697 rxcsum |= IXGBE_RXCSUM_PCSD;
1699 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1700 /* Enable IPv4 payload checksum for UDP fragments
1701 * if PCSD is not set */
1702 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1705 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1708 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1710 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1711 struct ixgbe_hw *hw = &adapter->hw;
1713 /* add VID to filter table */
1714 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1717 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1719 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1720 struct ixgbe_hw *hw = &adapter->hw;
1722 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1723 ixgbe_irq_disable(adapter);
1725 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1727 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1728 ixgbe_irq_enable(adapter);
1730 /* remove VID from filter table */
1731 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1734 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1735 struct vlan_group *grp)
1737 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1740 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1741 ixgbe_irq_disable(adapter);
1742 adapter->vlgrp = grp;
1745 * For a DCB driver, always enable VLAN tag stripping so we can
1746 * still receive traffic from a DCB-enabled host even if we're
1749 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1750 ctrl |= IXGBE_VLNCTRL_VME;
1751 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1752 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1753 ixgbe_vlan_rx_add_vid(netdev, 0);
1756 /* enable VLAN tag insert/strip */
1757 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1758 ctrl |= IXGBE_VLNCTRL_VME;
1759 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1760 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1763 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1764 ixgbe_irq_enable(adapter);
1767 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1769 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1771 if (adapter->vlgrp) {
1773 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1774 if (!vlan_group_get_device(adapter->vlgrp, vid))
1776 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1781 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1783 struct dev_mc_list *mc_ptr;
1784 u8 *addr = *mc_addr_ptr;
1787 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1789 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1791 *mc_addr_ptr = NULL;
1797 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1798 * @netdev: network interface device structure
1800 * The set_rx_method entry point is called whenever the unicast/multicast
1801 * address list or the network interface flags are updated. This routine is
1802 * responsible for configuring the hardware for proper unicast, multicast and
1805 static void ixgbe_set_rx_mode(struct net_device *netdev)
1807 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1808 struct ixgbe_hw *hw = &adapter->hw;
1810 u8 *addr_list = NULL;
1813 /* Check for Promiscuous and All Multicast modes */
1815 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1816 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1818 if (netdev->flags & IFF_PROMISC) {
1819 hw->addr_ctrl.user_set_promisc = 1;
1820 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1821 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1823 if (netdev->flags & IFF_ALLMULTI) {
1824 fctrl |= IXGBE_FCTRL_MPE;
1825 fctrl &= ~IXGBE_FCTRL_UPE;
1827 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1829 vlnctrl |= IXGBE_VLNCTRL_VFE;
1830 hw->addr_ctrl.user_set_promisc = 0;
1833 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1834 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1836 /* reprogram secondary unicast list */
1837 addr_count = netdev->uc_count;
1839 addr_list = netdev->uc_list->dmi_addr;
1840 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1841 ixgbe_addr_list_itr);
1843 /* reprogram multicast list */
1844 addr_count = netdev->mc_count;
1846 addr_list = netdev->mc_list->dmi_addr;
1847 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1848 ixgbe_addr_list_itr);
1851 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1854 struct ixgbe_q_vector *q_vector;
1855 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1857 /* legacy and MSI only use one vector */
1858 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1861 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1862 struct napi_struct *napi;
1863 q_vector = &adapter->q_vector[q_idx];
1864 if (!q_vector->rxr_count)
1866 napi = &q_vector->napi;
1867 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1868 (q_vector->rxr_count > 1))
1869 napi->poll = &ixgbe_clean_rxonly_many;
1875 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1878 struct ixgbe_q_vector *q_vector;
1879 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1881 /* legacy and MSI only use one vector */
1882 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1885 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1886 q_vector = &adapter->q_vector[q_idx];
1887 if (!q_vector->rxr_count)
1889 napi_disable(&q_vector->napi);
1893 #ifdef CONFIG_IXGBE_DCB
1895 * ixgbe_configure_dcb - Configure DCB hardware
1896 * @adapter: ixgbe adapter struct
1898 * This is called by the driver on open to configure the DCB hardware.
1899 * This is also called by the gennetlink interface when reconfiguring
1902 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
1904 struct ixgbe_hw *hw = &adapter->hw;
1905 u32 txdctl, vlnctrl;
1908 ixgbe_dcb_check_config(&adapter->dcb_cfg);
1909 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
1910 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
1912 /* reconfigure the hardware */
1913 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
1915 for (i = 0; i < adapter->num_tx_queues; i++) {
1916 j = adapter->tx_ring[i].reg_idx;
1917 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1918 /* PThresh workaround for Tx hang with DFP enabled. */
1920 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1922 /* Enable VLAN tag insert/strip */
1923 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1924 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1925 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1926 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1927 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
1931 static void ixgbe_configure(struct ixgbe_adapter *adapter)
1933 struct net_device *netdev = adapter->netdev;
1936 ixgbe_set_rx_mode(netdev);
1938 ixgbe_restore_vlan(adapter);
1939 #ifdef CONFIG_IXGBE_DCB
1940 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1941 netif_set_gso_max_size(netdev, 32768);
1942 ixgbe_configure_dcb(adapter);
1944 netif_set_gso_max_size(netdev, 65536);
1947 netif_set_gso_max_size(netdev, 65536);
1950 ixgbe_configure_tx(adapter);
1951 ixgbe_configure_rx(adapter);
1952 for (i = 0; i < adapter->num_rx_queues; i++)
1953 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1954 (adapter->rx_ring[i].count - 1));
1957 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1959 struct net_device *netdev = adapter->netdev;
1960 struct ixgbe_hw *hw = &adapter->hw;
1962 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1963 u32 txdctl, rxdctl, mhadd;
1966 ixgbe_get_hw_control(adapter);
1968 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1969 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
1970 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1971 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1972 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1977 /* XXX: to interrupt immediately for EICS writes, enable this */
1978 /* gpie |= IXGBE_GPIE_EIMEN; */
1979 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1982 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1983 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1984 * specifically only auto mask tx and rx interrupts */
1985 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1988 /* Enable fan failure interrupt if media type is copper */
1989 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
1990 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
1991 gpie |= IXGBE_SDP1_GPIEN;
1992 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1995 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
1996 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1997 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1998 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2000 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2003 for (i = 0; i < adapter->num_tx_queues; i++) {
2004 j = adapter->tx_ring[i].reg_idx;
2005 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2006 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2007 txdctl |= (8 << 16);
2008 txdctl |= IXGBE_TXDCTL_ENABLE;
2009 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2012 for (i = 0; i < adapter->num_rx_queues; i++) {
2013 j = adapter->rx_ring[i].reg_idx;
2014 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2015 /* enable PTHRESH=32 descriptors (half the internal cache)
2016 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2017 * this also removes a pesky rx_no_buffer_count increment */
2019 rxdctl |= IXGBE_RXDCTL_ENABLE;
2020 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2022 /* enable all receives */
2023 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2024 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2025 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
2027 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2028 ixgbe_configure_msix(adapter);
2030 ixgbe_configure_msi_and_legacy(adapter);
2032 ixgbe_napi_add_all(adapter);
2034 clear_bit(__IXGBE_DOWN, &adapter->state);
2035 ixgbe_napi_enable_all(adapter);
2037 /* clear any pending interrupts, may auto mask */
2038 IXGBE_READ_REG(hw, IXGBE_EICR);
2040 ixgbe_irq_enable(adapter);
2042 /* enable transmits */
2043 netif_tx_start_all_queues(netdev);
2045 /* bring the link up in the watchdog, this could race with our first
2046 * link up interrupt but shouldn't be a problem */
2047 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2048 adapter->link_check_timeout = jiffies;
2049 mod_timer(&adapter->watchdog_timer, jiffies);
2053 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2055 WARN_ON(in_interrupt());
2056 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2058 ixgbe_down(adapter);
2060 clear_bit(__IXGBE_RESETTING, &adapter->state);
2063 int ixgbe_up(struct ixgbe_adapter *adapter)
2065 /* hardware has been reset, we need to reload some things */
2066 ixgbe_configure(adapter);
2068 return ixgbe_up_complete(adapter);
2071 void ixgbe_reset(struct ixgbe_adapter *adapter)
2073 struct ixgbe_hw *hw = &adapter->hw;
2074 if (hw->mac.ops.init_hw(hw))
2075 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2077 /* reprogram the RAR[0] in case user changed it. */
2078 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2083 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2084 * @adapter: board private structure
2085 * @rx_ring: ring to free buffers from
2087 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2088 struct ixgbe_ring *rx_ring)
2090 struct pci_dev *pdev = adapter->pdev;
2094 /* Free all the Rx ring sk_buffs */
2096 for (i = 0; i < rx_ring->count; i++) {
2097 struct ixgbe_rx_buffer *rx_buffer_info;
2099 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2100 if (rx_buffer_info->dma) {
2101 pci_unmap_single(pdev, rx_buffer_info->dma,
2102 rx_ring->rx_buf_len,
2103 PCI_DMA_FROMDEVICE);
2104 rx_buffer_info->dma = 0;
2106 if (rx_buffer_info->skb) {
2107 dev_kfree_skb(rx_buffer_info->skb);
2108 rx_buffer_info->skb = NULL;
2110 if (!rx_buffer_info->page)
2112 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2113 PCI_DMA_FROMDEVICE);
2114 rx_buffer_info->page_dma = 0;
2115 put_page(rx_buffer_info->page);
2116 rx_buffer_info->page = NULL;
2117 rx_buffer_info->page_offset = 0;
2120 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2121 memset(rx_ring->rx_buffer_info, 0, size);
2123 /* Zero out the descriptor ring */
2124 memset(rx_ring->desc, 0, rx_ring->size);
2126 rx_ring->next_to_clean = 0;
2127 rx_ring->next_to_use = 0;
2129 writel(0, adapter->hw.hw_addr + rx_ring->head);
2130 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2134 * ixgbe_clean_tx_ring - Free Tx Buffers
2135 * @adapter: board private structure
2136 * @tx_ring: ring to be cleaned
2138 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2139 struct ixgbe_ring *tx_ring)
2141 struct ixgbe_tx_buffer *tx_buffer_info;
2145 /* Free all the Tx ring sk_buffs */
2147 for (i = 0; i < tx_ring->count; i++) {
2148 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2149 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2152 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2153 memset(tx_ring->tx_buffer_info, 0, size);
2155 /* Zero out the descriptor ring */
2156 memset(tx_ring->desc, 0, tx_ring->size);
2158 tx_ring->next_to_use = 0;
2159 tx_ring->next_to_clean = 0;
2161 writel(0, adapter->hw.hw_addr + tx_ring->head);
2162 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2166 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2167 * @adapter: board private structure
2169 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2173 for (i = 0; i < adapter->num_rx_queues; i++)
2174 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2178 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2179 * @adapter: board private structure
2181 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2185 for (i = 0; i < adapter->num_tx_queues; i++)
2186 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2189 void ixgbe_down(struct ixgbe_adapter *adapter)
2191 struct net_device *netdev = adapter->netdev;
2192 struct ixgbe_hw *hw = &adapter->hw;
2197 /* signal that we are down to the interrupt handler */
2198 set_bit(__IXGBE_DOWN, &adapter->state);
2200 /* disable receives */
2201 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2202 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2204 netif_tx_disable(netdev);
2206 IXGBE_WRITE_FLUSH(hw);
2209 netif_tx_stop_all_queues(netdev);
2211 ixgbe_irq_disable(adapter);
2213 ixgbe_napi_disable_all(adapter);
2215 del_timer_sync(&adapter->watchdog_timer);
2216 cancel_work_sync(&adapter->watchdog_task);
2218 /* disable transmits in the hardware now that interrupts are off */
2219 for (i = 0; i < adapter->num_tx_queues; i++) {
2220 j = adapter->tx_ring[i].reg_idx;
2221 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2222 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2223 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2226 netif_carrier_off(netdev);
2228 #ifdef CONFIG_IXGBE_DCA
2229 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2230 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2231 dca_remove_requester(&adapter->pdev->dev);
2235 if (!pci_channel_offline(adapter->pdev))
2236 ixgbe_reset(adapter);
2237 ixgbe_clean_all_tx_rings(adapter);
2238 ixgbe_clean_all_rx_rings(adapter);
2240 #ifdef CONFIG_IXGBE_DCA
2241 /* since we reset the hardware DCA settings were cleared */
2242 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2243 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2244 /* always use CB2 mode, difference is masked
2245 * in the CB driver */
2246 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2247 ixgbe_setup_dca(adapter);
2253 * ixgbe_poll - NAPI Rx polling callback
2254 * @napi: structure for representing this polling device
2255 * @budget: how many packets driver is allowed to clean
2257 * This function is used for legacy and MSI, NAPI mode
2259 static int ixgbe_poll(struct napi_struct *napi, int budget)
2261 struct ixgbe_q_vector *q_vector = container_of(napi,
2262 struct ixgbe_q_vector, napi);
2263 struct ixgbe_adapter *adapter = q_vector->adapter;
2264 int tx_cleaned, work_done = 0;
2266 #ifdef CONFIG_IXGBE_DCA
2267 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2268 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2269 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2273 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2274 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2279 /* If budget not fully consumed, exit the polling mode */
2280 if (work_done < budget) {
2281 napi_complete(napi);
2282 if (adapter->itr_setting & 3)
2283 ixgbe_set_itr(adapter);
2284 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2285 ixgbe_irq_enable(adapter);
2291 * ixgbe_tx_timeout - Respond to a Tx Hang
2292 * @netdev: network interface device structure
2294 static void ixgbe_tx_timeout(struct net_device *netdev)
2296 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2298 /* Do the reset outside of interrupt context */
2299 schedule_work(&adapter->reset_task);
2302 static void ixgbe_reset_task(struct work_struct *work)
2304 struct ixgbe_adapter *adapter;
2305 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2307 /* If we're already down or resetting, just bail */
2308 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2309 test_bit(__IXGBE_RESETTING, &adapter->state))
2312 adapter->tx_timeout_count++;
2314 ixgbe_reinit_locked(adapter);
2317 #ifdef CONFIG_IXGBE_DCB
2318 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2322 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2323 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2324 adapter->num_rx_queues =
2325 adapter->ring_feature[RING_F_DCB].indices;
2326 adapter->num_tx_queues =
2327 adapter->ring_feature[RING_F_DCB].indices;
2330 adapter->ring_feature[RING_F_DCB].mask = 0;
2331 adapter->ring_feature[RING_F_DCB].indices = 0;
2339 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2343 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2344 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2345 adapter->num_rx_queues =
2346 adapter->ring_feature[RING_F_RSS].indices;
2347 adapter->num_tx_queues =
2348 adapter->ring_feature[RING_F_RSS].indices;
2351 adapter->ring_feature[RING_F_RSS].mask = 0;
2352 adapter->ring_feature[RING_F_RSS].indices = 0;
2359 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2361 /* Start with base case */
2362 adapter->num_rx_queues = 1;
2363 adapter->num_tx_queues = 1;
2365 #ifdef CONFIG_IXGBE_DCB
2366 if (ixgbe_set_dcb_queues(adapter))
2370 if (ixgbe_set_rss_queues(adapter))
2374 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2377 int err, vector_threshold;
2379 /* We'll want at least 3 (vector_threshold):
2382 * 3) Other (Link Status Change, etc.)
2383 * 4) TCP Timer (optional)
2385 vector_threshold = MIN_MSIX_COUNT;
2387 /* The more we get, the more we will assign to Tx/Rx Cleanup
2388 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2389 * Right now, we simply care about how many we'll get; we'll
2390 * set them up later while requesting irq's.
2392 while (vectors >= vector_threshold) {
2393 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2395 if (!err) /* Success in acquiring all requested vectors. */
2398 vectors = 0; /* Nasty failure, quit now */
2399 else /* err == number of vectors we should try again with */
2403 if (vectors < vector_threshold) {
2404 /* Can't allocate enough MSI-X interrupts? Oh well.
2405 * This just means we'll go with either a single MSI
2406 * vector or fall back to legacy interrupts.
2408 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2409 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2410 kfree(adapter->msix_entries);
2411 adapter->msix_entries = NULL;
2412 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2413 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2414 ixgbe_set_num_queues(adapter);
2416 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2418 * Adjust for only the vectors we'll use, which is minimum
2419 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2420 * vectors we were allocated.
2422 adapter->num_msix_vectors = min(vectors,
2423 adapter->max_msix_q_vectors + NON_Q_VECTORS);
2428 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2429 * @adapter: board private structure to initialize
2431 * Cache the descriptor ring offsets for RSS to the assigned rings.
2434 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2439 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2440 for (i = 0; i < adapter->num_rx_queues; i++)
2441 adapter->rx_ring[i].reg_idx = i;
2442 for (i = 0; i < adapter->num_tx_queues; i++)
2443 adapter->tx_ring[i].reg_idx = i;
2452 #ifdef CONFIG_IXGBE_DCB
2454 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2455 * @adapter: board private structure to initialize
2457 * Cache the descriptor ring offsets for DCB to the assigned rings.
2460 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2464 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2466 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2467 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2468 /* the number of queues is assumed to be symmetric */
2469 for (i = 0; i < dcb_i; i++) {
2470 adapter->rx_ring[i].reg_idx = i << 3;
2471 adapter->tx_ring[i].reg_idx = i << 2;
2486 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2487 * @adapter: board private structure to initialize
2489 * Once we know the feature-set enabled for the device, we'll cache
2490 * the register offset the descriptor ring is assigned to.
2492 * Note, the order the various feature calls is important. It must start with
2493 * the "most" features enabled at the same time, then trickle down to the
2494 * least amount of features turned on at once.
2496 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2498 /* start with default case */
2499 adapter->rx_ring[0].reg_idx = 0;
2500 adapter->tx_ring[0].reg_idx = 0;
2502 #ifdef CONFIG_IXGBE_DCB
2503 if (ixgbe_cache_ring_dcb(adapter))
2507 if (ixgbe_cache_ring_rss(adapter))
2512 * ixgbe_alloc_queues - Allocate memory for all rings
2513 * @adapter: board private structure to initialize
2515 * We allocate one ring per queue at run-time since we don't know the
2516 * number of queues at compile-time.
2518 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2522 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2523 sizeof(struct ixgbe_ring), GFP_KERNEL);
2524 if (!adapter->tx_ring)
2525 goto err_tx_ring_allocation;
2527 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2528 sizeof(struct ixgbe_ring), GFP_KERNEL);
2529 if (!adapter->rx_ring)
2530 goto err_rx_ring_allocation;
2532 for (i = 0; i < adapter->num_tx_queues; i++) {
2533 adapter->tx_ring[i].count = adapter->tx_ring_count;
2534 adapter->tx_ring[i].queue_index = i;
2537 for (i = 0; i < adapter->num_rx_queues; i++) {
2538 adapter->rx_ring[i].count = adapter->rx_ring_count;
2539 adapter->rx_ring[i].queue_index = i;
2542 ixgbe_cache_ring_register(adapter);
2546 err_rx_ring_allocation:
2547 kfree(adapter->tx_ring);
2548 err_tx_ring_allocation:
2553 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2554 * @adapter: board private structure to initialize
2556 * Attempt to configure the interrupts using the best available
2557 * capabilities of the hardware and the kernel.
2559 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2562 int vector, v_budget;
2565 * It's easy to be greedy for MSI-X vectors, but it really
2566 * doesn't do us much good if we have a lot more vectors
2567 * than CPU's. So let's be conservative and only ask for
2568 * (roughly) twice the number of vectors as there are CPU's.
2570 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2571 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2574 * At the same time, hardware can only support a maximum of
2575 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2576 * we can easily reach upwards of 64 Rx descriptor queues and
2577 * 32 Tx queues. Thus, we cap it off in those rare cases where
2578 * the cpu count also exceeds our vector limit.
2580 v_budget = min(v_budget, MAX_MSIX_COUNT);
2582 /* A failure in MSI-X entry allocation isn't fatal, but it does
2583 * mean we disable MSI-X capabilities of the adapter. */
2584 adapter->msix_entries = kcalloc(v_budget,
2585 sizeof(struct msix_entry), GFP_KERNEL);
2586 if (!adapter->msix_entries) {
2587 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2588 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2589 ixgbe_set_num_queues(adapter);
2590 kfree(adapter->tx_ring);
2591 kfree(adapter->rx_ring);
2592 err = ixgbe_alloc_queues(adapter);
2594 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2602 for (vector = 0; vector < v_budget; vector++)
2603 adapter->msix_entries[vector].entry = vector;
2605 ixgbe_acquire_msix_vectors(adapter, v_budget);
2607 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2611 err = pci_enable_msi(adapter->pdev);
2613 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2615 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2616 "falling back to legacy. Error: %d\n", err);
2622 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2623 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2628 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2630 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2631 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2632 pci_disable_msix(adapter->pdev);
2633 kfree(adapter->msix_entries);
2634 adapter->msix_entries = NULL;
2635 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2636 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2637 pci_disable_msi(adapter->pdev);
2643 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2644 * @adapter: board private structure to initialize
2646 * We determine which interrupt scheme to use based on...
2647 * - Kernel support (MSI, MSI-X)
2648 * - which can be user-defined (via MODULE_PARAM)
2649 * - Hardware queue count (num_*_queues)
2650 * - defined by miscellaneous hardware support/features (RSS, etc.)
2652 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2656 /* Number of supported queues */
2657 ixgbe_set_num_queues(adapter);
2659 err = ixgbe_alloc_queues(adapter);
2661 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2662 goto err_alloc_queues;
2665 err = ixgbe_set_interrupt_capability(adapter);
2667 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2668 goto err_set_interrupt;
2671 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2672 "Tx Queue count = %u\n",
2673 (adapter->num_rx_queues > 1) ? "Enabled" :
2674 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2676 set_bit(__IXGBE_DOWN, &adapter->state);
2681 kfree(adapter->tx_ring);
2682 kfree(adapter->rx_ring);
2688 * ixgbe_sfp_timer - worker thread to find a missing module
2689 * @data: pointer to our adapter struct
2691 static void ixgbe_sfp_timer(unsigned long data)
2693 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2695 /* Do the sfp_timer outside of interrupt context due to the
2696 * delays that sfp+ detection requires
2698 schedule_work(&adapter->sfp_task);
2702 * ixgbe_sfp_task - worker thread to find a missing module
2703 * @work: pointer to work_struct containing our data
2705 static void ixgbe_sfp_task(struct work_struct *work)
2707 struct ixgbe_adapter *adapter = container_of(work,
2708 struct ixgbe_adapter,
2710 struct ixgbe_hw *hw = &adapter->hw;
2712 if ((hw->phy.type == ixgbe_phy_nl) &&
2713 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
2714 s32 ret = hw->phy.ops.identify_sfp(hw);
2717 ret = hw->phy.ops.reset(hw);
2718 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2719 DPRINTK(PROBE, ERR, "failed to initialize because an "
2720 "unsupported SFP+ module type was detected.\n"
2721 "Reload the driver after installing a "
2722 "supported module.\n");
2723 unregister_netdev(adapter->netdev);
2725 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
2728 /* don't need this routine any more */
2729 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2733 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
2734 mod_timer(&adapter->sfp_timer,
2735 round_jiffies(jiffies + (2 * HZ)));
2739 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2740 * @adapter: board private structure to initialize
2742 * ixgbe_sw_init initializes the Adapter private data structure.
2743 * Fields are initialized based on PCI device information and
2744 * OS network device settings (MTU size).
2746 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2748 struct ixgbe_hw *hw = &adapter->hw;
2749 struct pci_dev *pdev = adapter->pdev;
2751 #ifdef CONFIG_IXGBE_DCB
2753 struct tc_configuration *tc;
2756 /* PCI config space info */
2758 hw->vendor_id = pdev->vendor;
2759 hw->device_id = pdev->device;
2760 hw->revision_id = pdev->revision;
2761 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2762 hw->subsystem_device_id = pdev->subsystem_device;
2764 /* Set capability flags */
2765 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2766 adapter->ring_feature[RING_F_RSS].indices = rss;
2767 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2768 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
2769 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
2771 #ifdef CONFIG_IXGBE_DCB
2772 /* Configure DCB traffic classes */
2773 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
2774 tc = &adapter->dcb_cfg.tc_config[j];
2775 tc->path[DCB_TX_CONFIG].bwg_id = 0;
2776 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
2777 tc->path[DCB_RX_CONFIG].bwg_id = 0;
2778 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
2779 tc->dcb_pfc = pfc_disabled;
2781 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
2782 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
2783 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
2784 adapter->dcb_cfg.round_robin_enable = false;
2785 adapter->dcb_set_bitmap = 0x00;
2786 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
2787 adapter->ring_feature[RING_F_DCB].indices);
2790 if (hw->mac.ops.get_media_type &&
2791 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2792 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
2794 /* default flow control settings */
2795 hw->fc.original_type = ixgbe_fc_none;
2796 hw->fc.type = ixgbe_fc_none;
2797 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2798 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2799 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2800 hw->fc.send_xon = true;
2802 /* select 10G link by default */
2803 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2805 /* enable itr by default in dynamic mode */
2806 adapter->itr_setting = 1;
2807 adapter->eitr_param = 20000;
2809 /* set defaults for eitr in MegaBytes */
2810 adapter->eitr_low = 10;
2811 adapter->eitr_high = 20;
2813 /* set default ring sizes */
2814 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2815 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2817 /* initialize eeprom parameters */
2818 if (ixgbe_init_eeprom_params_generic(hw)) {
2819 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2823 /* enable rx csum by default */
2824 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2826 set_bit(__IXGBE_DOWN, &adapter->state);
2832 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2833 * @adapter: board private structure
2834 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2836 * Return 0 on success, negative on failure
2838 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2839 struct ixgbe_ring *tx_ring)
2841 struct pci_dev *pdev = adapter->pdev;
2844 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2845 tx_ring->tx_buffer_info = vmalloc(size);
2846 if (!tx_ring->tx_buffer_info)
2848 memset(tx_ring->tx_buffer_info, 0, size);
2850 /* round up to nearest 4K */
2851 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2853 tx_ring->size = ALIGN(tx_ring->size, 4096);
2855 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2860 tx_ring->next_to_use = 0;
2861 tx_ring->next_to_clean = 0;
2862 tx_ring->work_limit = tx_ring->count;
2866 vfree(tx_ring->tx_buffer_info);
2867 tx_ring->tx_buffer_info = NULL;
2868 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2869 "descriptor ring\n");
2874 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2875 * @adapter: board private structure
2877 * If this function returns with an error, then it's possible one or
2878 * more of the rings is populated (while the rest are not). It is the
2879 * callers duty to clean those orphaned rings.
2881 * Return 0 on success, negative on failure
2883 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2887 for (i = 0; i < adapter->num_tx_queues; i++) {
2888 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2891 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2899 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2900 * @adapter: board private structure
2901 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2903 * Returns 0 on success, negative on failure
2905 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2906 struct ixgbe_ring *rx_ring)
2908 struct pci_dev *pdev = adapter->pdev;
2911 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2912 rx_ring->rx_buffer_info = vmalloc(size);
2913 if (!rx_ring->rx_buffer_info) {
2915 "vmalloc allocation failed for the rx desc ring\n");
2918 memset(rx_ring->rx_buffer_info, 0, size);
2920 /* Round up to nearest 4K */
2921 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2922 rx_ring->size = ALIGN(rx_ring->size, 4096);
2924 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
2926 if (!rx_ring->desc) {
2928 "Memory allocation failed for the rx desc ring\n");
2929 vfree(rx_ring->rx_buffer_info);
2933 rx_ring->next_to_clean = 0;
2934 rx_ring->next_to_use = 0;
2943 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2944 * @adapter: board private structure
2946 * If this function returns with an error, then it's possible one or
2947 * more of the rings is populated (while the rest are not). It is the
2948 * callers duty to clean those orphaned rings.
2950 * Return 0 on success, negative on failure
2953 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2957 for (i = 0; i < adapter->num_rx_queues; i++) {
2958 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2961 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2969 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2970 * @adapter: board private structure
2971 * @tx_ring: Tx descriptor ring for a specific queue
2973 * Free all transmit software resources
2975 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2976 struct ixgbe_ring *tx_ring)
2978 struct pci_dev *pdev = adapter->pdev;
2980 ixgbe_clean_tx_ring(adapter, tx_ring);
2982 vfree(tx_ring->tx_buffer_info);
2983 tx_ring->tx_buffer_info = NULL;
2985 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2987 tx_ring->desc = NULL;
2991 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2992 * @adapter: board private structure
2994 * Free all transmit software resources
2996 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3000 for (i = 0; i < adapter->num_tx_queues; i++)
3001 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3005 * ixgbe_free_rx_resources - Free Rx Resources
3006 * @adapter: board private structure
3007 * @rx_ring: ring to clean the resources from
3009 * Free all receive software resources
3011 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3012 struct ixgbe_ring *rx_ring)
3014 struct pci_dev *pdev = adapter->pdev;
3016 ixgbe_clean_rx_ring(adapter, rx_ring);
3018 vfree(rx_ring->rx_buffer_info);
3019 rx_ring->rx_buffer_info = NULL;
3021 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3023 rx_ring->desc = NULL;
3027 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3028 * @adapter: board private structure
3030 * Free all receive software resources
3032 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3036 for (i = 0; i < adapter->num_rx_queues; i++)
3037 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3041 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3042 * @netdev: network interface device structure
3043 * @new_mtu: new value for maximum frame size
3045 * Returns 0 on success, negative on failure
3047 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3050 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3052 /* MTU < 68 is an error and causes problems on some kernels */
3053 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3056 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3057 netdev->mtu, new_mtu);
3058 /* must set new MTU before calling down or up */
3059 netdev->mtu = new_mtu;
3061 if (netif_running(netdev))
3062 ixgbe_reinit_locked(adapter);
3068 * ixgbe_open - Called when a network interface is made active
3069 * @netdev: network interface device structure
3071 * Returns 0 on success, negative value on failure
3073 * The open entry point is called when a network interface is made
3074 * active by the system (IFF_UP). At this point all resources needed
3075 * for transmit and receive operations are allocated, the interrupt
3076 * handler is registered with the OS, the watchdog timer is started,
3077 * and the stack is notified that the interface is ready.
3079 static int ixgbe_open(struct net_device *netdev)
3081 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3084 /* disallow open during test */
3085 if (test_bit(__IXGBE_TESTING, &adapter->state))
3088 /* allocate transmit descriptors */
3089 err = ixgbe_setup_all_tx_resources(adapter);
3093 /* allocate receive descriptors */
3094 err = ixgbe_setup_all_rx_resources(adapter);
3098 ixgbe_configure(adapter);
3100 err = ixgbe_request_irq(adapter);
3104 err = ixgbe_up_complete(adapter);
3108 netif_tx_start_all_queues(netdev);
3113 ixgbe_release_hw_control(adapter);
3114 ixgbe_free_irq(adapter);
3116 ixgbe_free_all_rx_resources(adapter);
3118 ixgbe_free_all_tx_resources(adapter);
3120 ixgbe_reset(adapter);
3126 * ixgbe_close - Disables a network interface
3127 * @netdev: network interface device structure
3129 * Returns 0, this is not allowed to fail
3131 * The close entry point is called when an interface is de-activated
3132 * by the OS. The hardware is still under the drivers control, but
3133 * needs to be disabled. A global MAC reset is issued to stop the
3134 * hardware, and all transmit and receive resources are freed.
3136 static int ixgbe_close(struct net_device *netdev)
3138 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3140 ixgbe_down(adapter);
3141 ixgbe_free_irq(adapter);
3143 ixgbe_free_all_tx_resources(adapter);
3144 ixgbe_free_all_rx_resources(adapter);
3146 ixgbe_release_hw_control(adapter);
3152 * ixgbe_napi_add_all - prep napi structs for use
3153 * @adapter: private struct
3154 * helper function to napi_add each possible q_vector->napi
3156 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3158 int q_idx, q_vectors;
3159 struct net_device *netdev = adapter->netdev;
3160 int (*poll)(struct napi_struct *, int);
3162 /* check if we already have our netdev->napi_list populated */
3163 if (&netdev->napi_list != netdev->napi_list.next)
3166 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3167 poll = &ixgbe_clean_rxonly;
3168 /* Only enable as many vectors as we have rx queues. */
3169 q_vectors = adapter->num_rx_queues;
3172 /* only one q_vector for legacy modes */
3176 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3177 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3178 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3182 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3185 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3187 /* legacy and MSI only use one vector */
3188 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3191 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3192 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3193 if (!q_vector->rxr_count)
3195 netif_napi_del(&q_vector->napi);
3200 static int ixgbe_resume(struct pci_dev *pdev)
3202 struct net_device *netdev = pci_get_drvdata(pdev);
3203 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3206 pci_set_power_state(pdev, PCI_D0);
3207 pci_restore_state(pdev);
3208 err = pci_enable_device(pdev);
3210 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3214 pci_set_master(pdev);
3216 pci_enable_wake(pdev, PCI_D3hot, 0);
3217 pci_enable_wake(pdev, PCI_D3cold, 0);
3219 err = ixgbe_init_interrupt_scheme(adapter);
3221 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3226 ixgbe_napi_add_all(adapter);
3227 ixgbe_reset(adapter);
3229 if (netif_running(netdev)) {
3230 err = ixgbe_open(adapter->netdev);
3235 netif_device_attach(netdev);
3240 #endif /* CONFIG_PM */
3241 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3243 struct net_device *netdev = pci_get_drvdata(pdev);
3244 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3249 netif_device_detach(netdev);
3251 if (netif_running(netdev)) {
3252 ixgbe_down(adapter);
3253 ixgbe_free_irq(adapter);
3254 ixgbe_free_all_tx_resources(adapter);
3255 ixgbe_free_all_rx_resources(adapter);
3257 ixgbe_reset_interrupt_capability(adapter);
3258 ixgbe_napi_del_all(adapter);
3259 INIT_LIST_HEAD(&netdev->napi_list);
3260 kfree(adapter->tx_ring);
3261 kfree(adapter->rx_ring);
3264 retval = pci_save_state(pdev);
3269 pci_enable_wake(pdev, PCI_D3hot, 0);
3270 pci_enable_wake(pdev, PCI_D3cold, 0);
3272 ixgbe_release_hw_control(adapter);
3274 pci_disable_device(pdev);
3276 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3281 static void ixgbe_shutdown(struct pci_dev *pdev)
3283 ixgbe_suspend(pdev, PMSG_SUSPEND);
3287 * ixgbe_update_stats - Update the board statistics counters.
3288 * @adapter: board private structure
3290 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3292 struct ixgbe_hw *hw = &adapter->hw;
3294 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3296 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3297 for (i = 0; i < 8; i++) {
3298 /* for packet buffers not used, the register should read 0 */
3299 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3301 adapter->stats.mpc[i] += mpc;
3302 total_mpc += adapter->stats.mpc[i];
3303 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3304 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3305 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3306 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3307 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3308 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3310 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3312 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3314 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3317 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3318 /* work around hardware counting issue */
3319 adapter->stats.gprc -= missed_rx;
3321 /* 82598 hardware only has a 32 bit counter in the high register */
3322 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3323 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3324 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3325 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3326 adapter->stats.bprc += bprc;
3327 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3328 adapter->stats.mprc -= bprc;
3329 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3330 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3331 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3332 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3333 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3334 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3335 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3336 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3337 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3338 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3339 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3340 adapter->stats.lxontxc += lxon;
3341 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3342 adapter->stats.lxofftxc += lxoff;
3343 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3344 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3345 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3347 * 82598 errata - tx of flow control packets is included in tx counters
3349 xon_off_tot = lxon + lxoff;
3350 adapter->stats.gptc -= xon_off_tot;
3351 adapter->stats.mptc -= xon_off_tot;
3352 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3353 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3354 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3355 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3356 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3357 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3358 adapter->stats.ptc64 -= xon_off_tot;
3359 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3360 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3361 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3362 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3363 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3364 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3366 /* Fill out the OS statistics structure */
3367 adapter->net_stats.multicast = adapter->stats.mprc;
3370 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3371 adapter->stats.rlec;
3372 adapter->net_stats.rx_dropped = 0;
3373 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3374 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3375 adapter->net_stats.rx_missed_errors = total_mpc;
3379 * ixgbe_watchdog - Timer Call-back
3380 * @data: pointer to adapter cast into an unsigned long
3382 static void ixgbe_watchdog(unsigned long data)
3384 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3385 struct ixgbe_hw *hw = &adapter->hw;
3387 /* Do the watchdog outside of interrupt context due to the lovely
3388 * delays that some of the newer hardware requires */
3389 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3390 /* Cause software interrupt to ensure rx rings are cleaned */
3391 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3393 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3394 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3396 /* For legacy and MSI interrupts don't set any bits that
3397 * are enabled for EIAM, because this operation would
3398 * set *both* EIMS and EICS for any bit in EIAM */
3399 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3400 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3402 /* Reset the timer */
3403 mod_timer(&adapter->watchdog_timer,
3404 round_jiffies(jiffies + 2 * HZ));
3407 schedule_work(&adapter->watchdog_task);
3411 * ixgbe_watchdog_task - worker thread to bring link up
3412 * @work: pointer to work_struct containing our data
3414 static void ixgbe_watchdog_task(struct work_struct *work)
3416 struct ixgbe_adapter *adapter = container_of(work,
3417 struct ixgbe_adapter,
3419 struct net_device *netdev = adapter->netdev;
3420 struct ixgbe_hw *hw = &adapter->hw;
3421 u32 link_speed = adapter->link_speed;
3422 bool link_up = adapter->link_up;
3424 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3426 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3427 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3429 time_after(jiffies, (adapter->link_check_timeout +
3430 IXGBE_TRY_LINK_TIMEOUT))) {
3431 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3432 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3434 adapter->link_up = link_up;
3435 adapter->link_speed = link_speed;
3439 if (!netif_carrier_ok(netdev)) {
3440 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3441 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3442 #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3443 #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3444 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3445 "Flow Control: %s\n",
3447 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3449 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3450 "1 Gbps" : "unknown speed")),
3451 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3453 (FLOW_TX ? "TX" : "None"))));
3455 netif_carrier_on(netdev);
3457 /* Force detection of hung controller */
3458 adapter->detect_tx_hung = true;
3461 adapter->link_up = false;
3462 adapter->link_speed = 0;
3463 if (netif_carrier_ok(netdev)) {
3464 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3466 netif_carrier_off(netdev);
3470 ixgbe_update_stats(adapter);
3471 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3474 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3475 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3476 u32 tx_flags, u8 *hdr_len)
3478 struct ixgbe_adv_tx_context_desc *context_desc;
3481 struct ixgbe_tx_buffer *tx_buffer_info;
3482 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3483 u32 mss_l4len_idx, l4len;
3485 if (skb_is_gso(skb)) {
3486 if (skb_header_cloned(skb)) {
3487 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3491 l4len = tcp_hdrlen(skb);
3494 if (skb->protocol == htons(ETH_P_IP)) {
3495 struct iphdr *iph = ip_hdr(skb);
3498 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3502 adapter->hw_tso_ctxt++;
3503 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3504 ipv6_hdr(skb)->payload_len = 0;
3505 tcp_hdr(skb)->check =
3506 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3507 &ipv6_hdr(skb)->daddr,
3509 adapter->hw_tso6_ctxt++;
3512 i = tx_ring->next_to_use;
3514 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3515 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3517 /* VLAN MACLEN IPLEN */
3518 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3520 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3521 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3522 IXGBE_ADVTXD_MACLEN_SHIFT);
3523 *hdr_len += skb_network_offset(skb);
3525 (skb_transport_header(skb) - skb_network_header(skb));
3527 (skb_transport_header(skb) - skb_network_header(skb));
3528 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3529 context_desc->seqnum_seed = 0;
3531 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3532 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
3533 IXGBE_ADVTXD_DTYP_CTXT);
3535 if (skb->protocol == htons(ETH_P_IP))
3536 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3537 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3538 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3542 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3543 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3544 /* use index 1 for TSO */
3545 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3546 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3548 tx_buffer_info->time_stamp = jiffies;
3549 tx_buffer_info->next_to_watch = i;
3552 if (i == tx_ring->count)
3554 tx_ring->next_to_use = i;
3561 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3562 struct ixgbe_ring *tx_ring,
3563 struct sk_buff *skb, u32 tx_flags)
3565 struct ixgbe_adv_tx_context_desc *context_desc;
3567 struct ixgbe_tx_buffer *tx_buffer_info;
3568 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3570 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3571 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3572 i = tx_ring->next_to_use;
3573 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3574 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3576 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3578 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3579 vlan_macip_lens |= (skb_network_offset(skb) <<
3580 IXGBE_ADVTXD_MACLEN_SHIFT);
3581 if (skb->ip_summed == CHECKSUM_PARTIAL)
3582 vlan_macip_lens |= (skb_transport_header(skb) -
3583 skb_network_header(skb));
3585 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3586 context_desc->seqnum_seed = 0;
3588 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3589 IXGBE_ADVTXD_DTYP_CTXT);
3591 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3592 switch (skb->protocol) {
3593 case cpu_to_be16(ETH_P_IP):
3594 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3595 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3597 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3599 case cpu_to_be16(ETH_P_IPV6):
3600 /* XXX what about other V6 headers?? */
3601 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3603 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3606 if (unlikely(net_ratelimit())) {
3607 DPRINTK(PROBE, WARNING,
3608 "partial checksum but proto=%x!\n",
3615 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3616 /* use index zero for tx checksum offload */
3617 context_desc->mss_l4len_idx = 0;
3619 tx_buffer_info->time_stamp = jiffies;
3620 tx_buffer_info->next_to_watch = i;
3622 adapter->hw_csum_tx_good++;
3624 if (i == tx_ring->count)
3626 tx_ring->next_to_use = i;
3634 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3635 struct ixgbe_ring *tx_ring,
3636 struct sk_buff *skb, unsigned int first)
3638 struct ixgbe_tx_buffer *tx_buffer_info;
3639 unsigned int len = skb->len;
3640 unsigned int offset = 0, size, count = 0, i;
3641 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3644 len -= skb->data_len;
3646 i = tx_ring->next_to_use;
3649 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3650 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3652 tx_buffer_info->length = size;
3653 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3655 size, PCI_DMA_TODEVICE);
3656 tx_buffer_info->time_stamp = jiffies;
3657 tx_buffer_info->next_to_watch = i;
3663 if (i == tx_ring->count)
3667 for (f = 0; f < nr_frags; f++) {
3668 struct skb_frag_struct *frag;
3670 frag = &skb_shinfo(skb)->frags[f];
3672 offset = frag->page_offset;
3675 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3676 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3678 tx_buffer_info->length = size;
3679 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3684 tx_buffer_info->time_stamp = jiffies;
3685 tx_buffer_info->next_to_watch = i;
3691 if (i == tx_ring->count)
3696 i = tx_ring->count - 1;
3699 tx_ring->tx_buffer_info[i].skb = skb;
3700 tx_ring->tx_buffer_info[first].next_to_watch = i;
3705 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3706 struct ixgbe_ring *tx_ring,
3707 int tx_flags, int count, u32 paylen, u8 hdr_len)
3709 union ixgbe_adv_tx_desc *tx_desc = NULL;
3710 struct ixgbe_tx_buffer *tx_buffer_info;
3711 u32 olinfo_status = 0, cmd_type_len = 0;
3713 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3715 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3717 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3719 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3720 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3722 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3723 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3725 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3726 IXGBE_ADVTXD_POPTS_SHIFT;
3728 /* use index 1 context for tso */
3729 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3730 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3731 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3732 IXGBE_ADVTXD_POPTS_SHIFT;
3734 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3735 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3736 IXGBE_ADVTXD_POPTS_SHIFT;
3738 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3740 i = tx_ring->next_to_use;
3742 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3743 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3744 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3745 tx_desc->read.cmd_type_len =
3746 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3747 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3749 if (i == tx_ring->count)
3753 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3756 * Force memory writes to complete before letting h/w
3757 * know there are new descriptors to fetch. (Only
3758 * applicable for weak-ordered memory model archs,
3763 tx_ring->next_to_use = i;
3764 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3767 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3768 struct ixgbe_ring *tx_ring, int size)
3770 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3772 netif_stop_subqueue(netdev, tx_ring->queue_index);
3773 /* Herbert's original patch had:
3774 * smp_mb__after_netif_stop_queue();
3775 * but since that doesn't exist yet, just open code it. */
3778 /* We need to check again in a case another CPU has just
3779 * made room available. */
3780 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3783 /* A reprieve! - use start_queue because it doesn't call schedule */
3784 netif_start_subqueue(netdev, tx_ring->queue_index);
3785 ++adapter->restart_queue;
3789 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3790 struct ixgbe_ring *tx_ring, int size)
3792 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3794 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3797 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3799 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3800 struct ixgbe_ring *tx_ring;
3802 unsigned int tx_flags = 0;
3808 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3809 tx_ring = &adapter->tx_ring[r_idx];
3811 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3812 tx_flags |= vlan_tx_tag_get(skb);
3813 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3814 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
3815 tx_flags |= (skb->queue_mapping << 13);
3817 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3818 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3819 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3820 tx_flags |= (skb->queue_mapping << 13);
3821 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3822 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3824 /* three things can cause us to need a context descriptor */
3825 if (skb_is_gso(skb) ||
3826 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3827 (tx_flags & IXGBE_TX_FLAGS_VLAN))
3830 count += TXD_USE_COUNT(skb_headlen(skb));
3831 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3832 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3834 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
3836 return NETDEV_TX_BUSY;
3839 if (skb->protocol == htons(ETH_P_IP))
3840 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3841 first = tx_ring->next_to_use;
3842 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3844 dev_kfree_skb_any(skb);
3845 return NETDEV_TX_OK;
3849 tx_flags |= IXGBE_TX_FLAGS_TSO;
3850 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3851 (skb->ip_summed == CHECKSUM_PARTIAL))
3852 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3854 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3855 ixgbe_tx_map(adapter, tx_ring, skb, first),
3858 netdev->trans_start = jiffies;
3860 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3862 return NETDEV_TX_OK;
3866 * ixgbe_get_stats - Get System Network Statistics
3867 * @netdev: network interface device structure
3869 * Returns the address of the device statistics structure.
3870 * The statistics are actually updated from the timer callback.
3872 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3874 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3876 /* only return the current stats */
3877 return &adapter->net_stats;
3881 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3882 * @netdev: network interface device structure
3883 * @p: pointer to an address structure
3885 * Returns 0 on success, negative on failure
3887 static int ixgbe_set_mac(struct net_device *netdev, void *p)
3889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3890 struct ixgbe_hw *hw = &adapter->hw;
3891 struct sockaddr *addr = p;
3893 if (!is_valid_ether_addr(addr->sa_data))
3894 return -EADDRNOTAVAIL;
3896 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3897 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3899 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3904 #ifdef CONFIG_NET_POLL_CONTROLLER
3906 * Polling 'interrupt' - used by things like netconsole to send skbs
3907 * without having to re-enable interrupts. It's not called while
3908 * the interrupt routine is executing.
3910 static void ixgbe_netpoll(struct net_device *netdev)
3912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3914 disable_irq(adapter->pdev->irq);
3915 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3916 ixgbe_intr(adapter->pdev->irq, netdev);
3917 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3918 enable_irq(adapter->pdev->irq);
3923 * ixgbe_link_config - set up initial link with default speed and duplex
3924 * @hw: pointer to private hardware struct
3926 * Returns 0 on success, negative on failure
3928 static int ixgbe_link_config(struct ixgbe_hw *hw)
3931 bool link_up = false;
3932 u32 ret = IXGBE_ERR_LINK_SETUP;
3934 if (hw->mac.ops.check_link)
3935 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3937 if (ret || !link_up)
3940 if (hw->mac.ops.get_link_capabilities)
3941 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3946 if (hw->mac.ops.setup_link_speed)
3947 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3953 static const struct net_device_ops ixgbe_netdev_ops = {
3954 .ndo_open = ixgbe_open,
3955 .ndo_stop = ixgbe_close,
3956 .ndo_start_xmit = ixgbe_xmit_frame,
3957 .ndo_get_stats = ixgbe_get_stats,
3958 .ndo_set_multicast_list = ixgbe_set_rx_mode,
3959 .ndo_validate_addr = eth_validate_addr,
3960 .ndo_set_mac_address = ixgbe_set_mac,
3961 .ndo_change_mtu = ixgbe_change_mtu,
3962 .ndo_tx_timeout = ixgbe_tx_timeout,
3963 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
3964 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
3965 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
3966 #ifdef CONFIG_NET_POLL_CONTROLLER
3967 .ndo_poll_controller = ixgbe_netpoll,
3972 * ixgbe_probe - Device Initialization Routine
3973 * @pdev: PCI device information struct
3974 * @ent: entry in ixgbe_pci_tbl
3976 * Returns 0 on success, negative on failure
3978 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3979 * The OS initialization, configuring of the adapter private structure,
3980 * and a hardware reset occur.
3982 static int __devinit ixgbe_probe(struct pci_dev *pdev,
3983 const struct pci_device_id *ent)
3985 struct net_device *netdev;
3986 struct ixgbe_adapter *adapter = NULL;
3987 struct ixgbe_hw *hw;
3988 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3989 static int cards_found;
3990 int i, err, pci_using_dac;
3991 u16 link_status, link_speed, link_width;
3994 err = pci_enable_device(pdev);
3998 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3999 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
4002 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4004 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4006 dev_err(&pdev->dev, "No usable DMA "
4007 "configuration, aborting\n");
4014 err = pci_request_regions(pdev, ixgbe_driver_name);
4016 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4020 err = pci_enable_pcie_error_reporting(pdev);
4022 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4024 /* non-fatal, continue */
4027 pci_set_master(pdev);
4028 pci_save_state(pdev);
4030 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4033 goto err_alloc_etherdev;
4036 SET_NETDEV_DEV(netdev, &pdev->dev);
4038 pci_set_drvdata(pdev, netdev);
4039 adapter = netdev_priv(netdev);
4041 adapter->netdev = netdev;
4042 adapter->pdev = pdev;
4045 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4047 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4048 pci_resource_len(pdev, 0));
4054 for (i = 1; i <= 5; i++) {
4055 if (pci_resource_len(pdev, i) == 0)
4059 netdev->netdev_ops = &ixgbe_netdev_ops;
4060 ixgbe_set_ethtool_ops(netdev);
4061 netdev->watchdog_timeo = 5 * HZ;
4062 strcpy(netdev->name, pci_name(pdev));
4064 adapter->bd_number = cards_found;
4067 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4068 hw->mac.type = ii->mac;
4071 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4072 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4073 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4074 if (!(eec & (1 << 8)))
4075 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4078 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4079 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4081 /* set up this timer and work struct before calling get_invariants
4082 * which might start the timer
4084 init_timer(&adapter->sfp_timer);
4085 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4086 adapter->sfp_timer.data = (unsigned long) adapter;
4088 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4090 err = ii->get_invariants(hw);
4091 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4092 /* start a kernel thread to watch for a module to arrive */
4093 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4094 mod_timer(&adapter->sfp_timer,
4095 round_jiffies(jiffies + (2 * HZ)));
4097 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4098 DPRINTK(PROBE, ERR, "failed to load because an "
4099 "unsupported SFP+ module type was detected.\n");
4105 /* setup the private structure */
4106 err = ixgbe_sw_init(adapter);
4110 /* reset_hw fills in the perm_addr as well */
4111 err = hw->mac.ops.reset_hw(hw);
4113 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4117 netdev->features = NETIF_F_SG |
4119 NETIF_F_HW_VLAN_TX |
4120 NETIF_F_HW_VLAN_RX |
4121 NETIF_F_HW_VLAN_FILTER;
4123 netdev->features |= NETIF_F_IPV6_CSUM;
4124 netdev->features |= NETIF_F_TSO;
4125 netdev->features |= NETIF_F_TSO6;
4126 netdev->features |= NETIF_F_GRO;
4128 netdev->vlan_features |= NETIF_F_TSO;
4129 netdev->vlan_features |= NETIF_F_TSO6;
4130 netdev->vlan_features |= NETIF_F_IP_CSUM;
4131 netdev->vlan_features |= NETIF_F_SG;
4133 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4134 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4136 #ifdef CONFIG_IXGBE_DCB
4137 netdev->dcbnl_ops = &dcbnl_ops;
4141 netdev->features |= NETIF_F_HIGHDMA;
4143 /* make sure the EEPROM is good */
4144 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4145 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4150 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4151 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4153 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4154 dev_err(&pdev->dev, "invalid MAC address\n");
4159 init_timer(&adapter->watchdog_timer);
4160 adapter->watchdog_timer.function = &ixgbe_watchdog;
4161 adapter->watchdog_timer.data = (unsigned long)adapter;
4163 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4164 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4166 err = ixgbe_init_interrupt_scheme(adapter);
4170 /* print bus type/speed/width info */
4171 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
4172 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
4173 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
4174 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4175 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
4176 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
4178 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
4179 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
4180 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
4181 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
4184 ixgbe_read_pba_num_generic(hw, &part_num);
4185 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4186 hw->mac.type, hw->phy.type,
4187 (part_num >> 8), (part_num & 0xff));
4189 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
4190 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4191 "this card is not sufficient for optimal "
4193 dev_warn(&pdev->dev, "For optimal performance a x8 "
4194 "PCI-Express slot is required.\n");
4197 /* reset the hardware with the new settings */
4198 hw->mac.ops.start_hw(hw);
4200 /* link_config depends on start_hw being called at least once */
4201 err = ixgbe_link_config(hw);
4203 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
4207 netif_carrier_off(netdev);
4209 strcpy(netdev->name, "eth%d");
4210 err = register_netdev(netdev);
4214 #ifdef CONFIG_IXGBE_DCA
4215 if (dca_add_requester(&pdev->dev) == 0) {
4216 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4217 /* always use CB2 mode, difference is masked
4218 * in the CB driver */
4219 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4220 ixgbe_setup_dca(adapter);
4224 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4229 ixgbe_release_hw_control(adapter);
4232 ixgbe_reset_interrupt_capability(adapter);
4234 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4235 del_timer_sync(&adapter->sfp_timer);
4236 cancel_work_sync(&adapter->sfp_task);
4237 iounmap(hw->hw_addr);
4239 free_netdev(netdev);
4241 pci_release_regions(pdev);
4244 pci_disable_device(pdev);
4249 * ixgbe_remove - Device Removal Routine
4250 * @pdev: PCI device information struct
4252 * ixgbe_remove is called by the PCI subsystem to alert the driver
4253 * that it should release a PCI device. The could be caused by a
4254 * Hot-Plug event, or because the driver is going to be removed from
4257 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4259 struct net_device *netdev = pci_get_drvdata(pdev);
4260 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4263 set_bit(__IXGBE_DOWN, &adapter->state);
4264 /* clear the module not found bit to make sure the worker won't
4267 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4268 del_timer_sync(&adapter->watchdog_timer);
4270 del_timer_sync(&adapter->sfp_timer);
4271 cancel_work_sync(&adapter->watchdog_task);
4272 cancel_work_sync(&adapter->sfp_task);
4273 flush_scheduled_work();
4275 #ifdef CONFIG_IXGBE_DCA
4276 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4277 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4278 dca_remove_requester(&pdev->dev);
4279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4283 if (netdev->reg_state == NETREG_REGISTERED)
4284 unregister_netdev(netdev);
4286 ixgbe_reset_interrupt_capability(adapter);
4288 ixgbe_release_hw_control(adapter);
4290 iounmap(adapter->hw.hw_addr);
4291 pci_release_regions(pdev);
4293 DPRINTK(PROBE, INFO, "complete\n");
4294 kfree(adapter->tx_ring);
4295 kfree(adapter->rx_ring);
4297 free_netdev(netdev);
4299 err = pci_disable_pcie_error_reporting(pdev);
4302 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4304 pci_disable_device(pdev);
4308 * ixgbe_io_error_detected - called when PCI error is detected
4309 * @pdev: Pointer to PCI device
4310 * @state: The current pci connection state
4312 * This function is called after a PCI bus error affecting
4313 * this device has been detected.
4315 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4316 pci_channel_state_t state)
4318 struct net_device *netdev = pci_get_drvdata(pdev);
4319 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4321 netif_device_detach(netdev);
4323 if (netif_running(netdev))
4324 ixgbe_down(adapter);
4325 pci_disable_device(pdev);
4327 /* Request a slot reset. */
4328 return PCI_ERS_RESULT_NEED_RESET;
4332 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4333 * @pdev: Pointer to PCI device
4335 * Restart the card from scratch, as if from a cold-boot.
4337 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4339 struct net_device *netdev = pci_get_drvdata(pdev);
4340 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4341 pci_ers_result_t result;
4344 if (pci_enable_device(pdev)) {
4346 "Cannot re-enable PCI device after reset.\n");
4347 result = PCI_ERS_RESULT_DISCONNECT;
4349 pci_set_master(pdev);
4350 pci_restore_state(pdev);
4352 pci_enable_wake(pdev, PCI_D3hot, 0);
4353 pci_enable_wake(pdev, PCI_D3cold, 0);
4355 ixgbe_reset(adapter);
4357 result = PCI_ERS_RESULT_RECOVERED;
4360 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4363 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4364 /* non-fatal, continue */
4371 * ixgbe_io_resume - called when traffic can start flowing again.
4372 * @pdev: Pointer to PCI device
4374 * This callback is called when the error recovery driver tells us that
4375 * its OK to resume normal operation.
4377 static void ixgbe_io_resume(struct pci_dev *pdev)
4379 struct net_device *netdev = pci_get_drvdata(pdev);
4380 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4382 if (netif_running(netdev)) {
4383 if (ixgbe_up(adapter)) {
4384 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4389 netif_device_attach(netdev);
4392 static struct pci_error_handlers ixgbe_err_handler = {
4393 .error_detected = ixgbe_io_error_detected,
4394 .slot_reset = ixgbe_io_slot_reset,
4395 .resume = ixgbe_io_resume,
4398 static struct pci_driver ixgbe_driver = {
4399 .name = ixgbe_driver_name,
4400 .id_table = ixgbe_pci_tbl,
4401 .probe = ixgbe_probe,
4402 .remove = __devexit_p(ixgbe_remove),
4404 .suspend = ixgbe_suspend,
4405 .resume = ixgbe_resume,
4407 .shutdown = ixgbe_shutdown,
4408 .err_handler = &ixgbe_err_handler
4412 * ixgbe_init_module - Driver Registration Routine
4414 * ixgbe_init_module is the first routine called when the driver is
4415 * loaded. All it does is register with the PCI subsystem.
4417 static int __init ixgbe_init_module(void)
4420 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4421 ixgbe_driver_string, ixgbe_driver_version);
4423 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4425 #ifdef CONFIG_IXGBE_DCA
4426 dca_register_notify(&dca_notifier);
4429 ret = pci_register_driver(&ixgbe_driver);
4433 module_init(ixgbe_init_module);
4436 * ixgbe_exit_module - Driver Exit Cleanup Routine
4438 * ixgbe_exit_module is called just before the driver is removed
4441 static void __exit ixgbe_exit_module(void)
4443 #ifdef CONFIG_IXGBE_DCA
4444 dca_unregister_notify(&dca_notifier);
4446 pci_unregister_driver(&ixgbe_driver);
4449 #ifdef CONFIG_IXGBE_DCA
4450 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4455 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4456 __ixgbe_notify_dca);
4458 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4460 #endif /* CONFIG_IXGBE_DCA */
4462 module_exit(ixgbe_exit_module);