1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
44 #include "ixgbe_common.h"
46 char ixgbe_driver_name[] = "ixgbe";
47 static const char ixgbe_driver_string[] =
48 "Intel(R) 10 Gigabit PCI Express Network Driver";
50 #define DRV_VERSION "1.3.56-k2"
51 const char ixgbe_driver_version[] = DRV_VERSION;
52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
55 [board_82598] = &ixgbe_82598_info,
58 /* ixgbe_pci_tbl - PCI Device ID Table
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
66 static struct pci_device_id ixgbe_pci_tbl[] = {
67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 /* required last entry */
93 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
95 #ifdef CONFIG_IXGBE_DCA
96 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
98 static struct notifier_block dca_notifier = {
99 .notifier_call = ixgbe_notify_dca,
105 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
106 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
107 MODULE_LICENSE("GPL");
108 MODULE_VERSION(DRV_VERSION);
110 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
112 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
116 /* Let firmware take over control of h/w */
117 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
118 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
119 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
122 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
126 /* Let firmware know the driver has taken over */
127 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
128 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
129 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
132 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
137 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
138 index = (int_alloc_entry >> 2) & 0x1F;
139 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
140 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
141 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
142 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
145 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
146 struct ixgbe_tx_buffer
149 if (tx_buffer_info->dma) {
150 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
151 tx_buffer_info->length, PCI_DMA_TODEVICE);
152 tx_buffer_info->dma = 0;
154 if (tx_buffer_info->skb) {
155 dev_kfree_skb_any(tx_buffer_info->skb);
156 tx_buffer_info->skb = NULL;
158 /* tx_buffer_info must be completely set up in the transmit path */
161 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
162 struct ixgbe_ring *tx_ring,
165 struct ixgbe_hw *hw = &adapter->hw;
168 /* Detect a transmit hang in hardware, this serializes the
169 * check with the clearing of time_stamp and movement of eop */
170 head = IXGBE_READ_REG(hw, tx_ring->head);
171 tail = IXGBE_READ_REG(hw, tx_ring->tail);
172 adapter->detect_tx_hung = false;
173 if ((head != tail) &&
174 tx_ring->tx_buffer_info[eop].time_stamp &&
175 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
176 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
177 /* detected Tx unit hang */
178 union ixgbe_adv_tx_desc *tx_desc;
179 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
180 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
182 " TDH, TDT <%x>, <%x>\n"
183 " next_to_use <%x>\n"
184 " next_to_clean <%x>\n"
185 "tx_buffer_info[next_to_clean]\n"
186 " time_stamp <%lx>\n"
188 tx_ring->queue_index,
190 tx_ring->next_to_use, eop,
191 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
198 #define IXGBE_MAX_TXD_PWR 14
199 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
201 /* Tx Descriptors needed, worst case */
202 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
203 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
204 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
205 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
207 static void ixgbe_tx_timeout(struct net_device *netdev);
210 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
211 * @adapter: board private structure
212 * @tx_ring: tx ring to clean
214 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
215 struct ixgbe_ring *tx_ring)
217 struct net_device *netdev = adapter->netdev;
218 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
219 struct ixgbe_tx_buffer *tx_buffer_info;
220 unsigned int i, eop, count = 0;
221 unsigned int total_bytes = 0, total_packets = 0;
223 i = tx_ring->next_to_clean;
224 eop = tx_ring->tx_buffer_info[i].next_to_watch;
225 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
227 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
228 (count < tx_ring->count)) {
229 bool cleaned = false;
230 for ( ; !cleaned; count++) {
232 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
233 tx_buffer_info = &tx_ring->tx_buffer_info[i];
234 cleaned = (i == eop);
235 skb = tx_buffer_info->skb;
237 if (cleaned && skb) {
238 unsigned int segs, bytecount;
240 /* gso_segs is currently only valid for tcp */
241 segs = skb_shinfo(skb)->gso_segs ?: 1;
242 /* multiply data chunks by size of headers */
243 bytecount = ((segs - 1) * skb_headlen(skb)) +
245 total_packets += segs;
246 total_bytes += bytecount;
249 ixgbe_unmap_and_free_tx_resource(adapter,
252 tx_desc->wb.status = 0;
255 if (i == tx_ring->count)
259 eop = tx_ring->tx_buffer_info[i].next_to_watch;
260 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
263 tx_ring->next_to_clean = i;
265 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
266 if (unlikely(count && netif_carrier_ok(netdev) &&
267 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
268 /* Make sure that anybody stopping the queue after this
269 * sees the new next_to_clean.
272 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
273 !test_bit(__IXGBE_DOWN, &adapter->state)) {
274 netif_wake_subqueue(netdev, tx_ring->queue_index);
275 ++adapter->restart_queue;
279 if (adapter->detect_tx_hung) {
280 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
281 /* schedule immediate reset if we believe we hung */
283 "tx hang %d detected, resetting adapter\n",
284 adapter->tx_timeout_count + 1);
285 ixgbe_tx_timeout(adapter->netdev);
289 /* re-arm the interrupt */
290 if ((total_packets >= tx_ring->work_limit) ||
291 (count == tx_ring->count))
292 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
294 tx_ring->total_bytes += total_bytes;
295 tx_ring->total_packets += total_packets;
296 tx_ring->stats.packets += total_packets;
297 tx_ring->stats.bytes += total_bytes;
298 adapter->net_stats.tx_bytes += total_bytes;
299 adapter->net_stats.tx_packets += total_packets;
300 return (total_packets ? true : false);
303 #ifdef CONFIG_IXGBE_DCA
304 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
305 struct ixgbe_ring *rx_ring)
309 int q = rx_ring - adapter->rx_ring;
311 if (rx_ring->cpu != cpu) {
312 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
313 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
314 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
315 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
316 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
317 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
318 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
319 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
326 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
327 struct ixgbe_ring *tx_ring)
331 int q = tx_ring - adapter->tx_ring;
333 if (tx_ring->cpu != cpu) {
334 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
335 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
336 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
337 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
344 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
348 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
351 for (i = 0; i < adapter->num_tx_queues; i++) {
352 adapter->tx_ring[i].cpu = -1;
353 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
355 for (i = 0; i < adapter->num_rx_queues; i++) {
356 adapter->rx_ring[i].cpu = -1;
357 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
361 static int __ixgbe_notify_dca(struct device *dev, void *data)
363 struct net_device *netdev = dev_get_drvdata(dev);
364 struct ixgbe_adapter *adapter = netdev_priv(netdev);
365 unsigned long event = *(unsigned long *)data;
368 case DCA_PROVIDER_ADD:
369 /* if we're already enabled, don't do it again */
370 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
372 /* Always use CB2 mode, difference is masked
373 * in the CB driver. */
374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
375 if (dca_add_requester(dev) == 0) {
376 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
377 ixgbe_setup_dca(adapter);
380 /* Fall Through since DCA is disabled. */
381 case DCA_PROVIDER_REMOVE:
382 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
383 dca_remove_requester(dev);
384 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
385 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
393 #endif /* CONFIG_IXGBE_DCA */
395 * ixgbe_receive_skb - Send a completed packet up the stack
396 * @adapter: board private structure
397 * @skb: packet to send up
398 * @status: hardware indication of status of receive
399 * @rx_ring: rx descriptor ring (for a specific queue) to setup
400 * @rx_desc: rx descriptor
402 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
403 struct sk_buff *skb, u8 status,
404 union ixgbe_adv_rx_desc *rx_desc)
406 struct ixgbe_adapter *adapter = q_vector->adapter;
407 struct napi_struct *napi = &q_vector->napi;
408 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
409 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
411 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
412 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
413 if (adapter->vlgrp && is_vlan && (tag != 0))
414 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
416 napi_gro_receive(napi, skb);
418 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
419 if (adapter->vlgrp && is_vlan && (tag != 0))
420 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
422 netif_receive_skb(skb);
424 if (adapter->vlgrp && is_vlan && (tag != 0))
425 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
433 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
434 * @adapter: address of board private structure
435 * @status_err: hardware indication of status of receive
436 * @skb: skb currently being received and modified
438 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
439 u32 status_err, struct sk_buff *skb)
441 skb->ip_summed = CHECKSUM_NONE;
443 /* Rx csum disabled */
444 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
447 /* if IP and error */
448 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
449 (status_err & IXGBE_RXDADV_ERR_IPE)) {
450 adapter->hw_csum_rx_error++;
454 if (!(status_err & IXGBE_RXD_STAT_L4CS))
457 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
458 adapter->hw_csum_rx_error++;
462 /* It must be a TCP or UDP packet with a valid checksum */
463 skb->ip_summed = CHECKSUM_UNNECESSARY;
464 adapter->hw_csum_rx_good++;
468 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
469 * @adapter: address of board private structure
471 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
472 struct ixgbe_ring *rx_ring,
475 struct pci_dev *pdev = adapter->pdev;
476 union ixgbe_adv_rx_desc *rx_desc;
477 struct ixgbe_rx_buffer *bi;
480 i = rx_ring->next_to_use;
481 bi = &rx_ring->rx_buffer_info[i];
483 while (cleaned_count--) {
484 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
487 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
489 bi->page = alloc_page(GFP_ATOMIC);
491 adapter->alloc_rx_page_failed++;
496 /* use a half page if we're re-using */
497 bi->page_offset ^= (PAGE_SIZE / 2);
500 bi->page_dma = pci_map_page(pdev, bi->page,
508 skb = netdev_alloc_skb(adapter->netdev,
509 (rx_ring->rx_buf_len +
513 adapter->alloc_rx_buff_failed++;
518 * Make buffer alignment 2 beyond a 16 byte boundary
519 * this will result in a 16 byte aligned IP header after
520 * the 14 byte MAC header is removed
522 skb_reserve(skb, NET_IP_ALIGN);
525 bi->dma = pci_map_single(pdev, skb->data,
529 /* Refresh the desc even if buffer_addrs didn't change because
530 * each write-back erases this info. */
531 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
532 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
533 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
535 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
539 if (i == rx_ring->count)
541 bi = &rx_ring->rx_buffer_info[i];
545 if (rx_ring->next_to_use != i) {
546 rx_ring->next_to_use = i;
548 i = (rx_ring->count - 1);
551 * Force memory writes to complete before letting h/w
552 * know there are new descriptors to fetch. (Only
553 * applicable for weak-ordered memory model archs,
557 writel(i, adapter->hw.hw_addr + rx_ring->tail);
561 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
563 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
566 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
568 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
571 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
572 struct ixgbe_ring *rx_ring,
573 int *work_done, int work_to_do)
575 struct ixgbe_adapter *adapter = q_vector->adapter;
576 struct pci_dev *pdev = adapter->pdev;
577 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
578 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
583 bool cleaned = false;
584 int cleaned_count = 0;
585 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
587 i = rx_ring->next_to_clean;
588 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
589 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
590 rx_buffer_info = &rx_ring->rx_buffer_info[i];
592 while (staterr & IXGBE_RXD_STAT_DD) {
594 if (*work_done >= work_to_do)
598 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
599 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
600 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
601 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
602 if (hdr_info & IXGBE_RXDADV_SPH)
603 adapter->rx_hdr_split++;
604 if (len > IXGBE_RX_HDR_SIZE)
605 len = IXGBE_RX_HDR_SIZE;
606 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
608 len = le16_to_cpu(rx_desc->wb.upper.length);
612 skb = rx_buffer_info->skb;
613 prefetch(skb->data - NET_IP_ALIGN);
614 rx_buffer_info->skb = NULL;
616 if (len && !skb_shinfo(skb)->nr_frags) {
617 pci_unmap_single(pdev, rx_buffer_info->dma,
624 pci_unmap_page(pdev, rx_buffer_info->page_dma,
625 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
626 rx_buffer_info->page_dma = 0;
627 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
628 rx_buffer_info->page,
629 rx_buffer_info->page_offset,
632 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
633 (page_count(rx_buffer_info->page) != 1))
634 rx_buffer_info->page = NULL;
636 get_page(rx_buffer_info->page);
638 skb->len += upper_len;
639 skb->data_len += upper_len;
640 skb->truesize += upper_len;
644 if (i == rx_ring->count)
646 next_buffer = &rx_ring->rx_buffer_info[i];
648 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
652 if (staterr & IXGBE_RXD_STAT_EOP) {
653 rx_ring->stats.packets++;
654 rx_ring->stats.bytes += skb->len;
656 rx_buffer_info->skb = next_buffer->skb;
657 rx_buffer_info->dma = next_buffer->dma;
658 next_buffer->skb = skb;
659 next_buffer->dma = 0;
660 adapter->non_eop_descs++;
664 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
665 dev_kfree_skb_irq(skb);
669 ixgbe_rx_checksum(adapter, staterr, skb);
671 /* probably a little skewed due to removing CRC */
672 total_rx_bytes += skb->len;
675 skb->protocol = eth_type_trans(skb, adapter->netdev);
676 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
679 rx_desc->wb.upper.status_error = 0;
681 /* return some buffers to hardware, one at a time is too slow */
682 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
683 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
687 /* use prefetched values */
689 rx_buffer_info = next_buffer;
691 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
694 rx_ring->next_to_clean = i;
695 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
698 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
700 rx_ring->total_packets += total_rx_packets;
701 rx_ring->total_bytes += total_rx_bytes;
702 adapter->net_stats.rx_bytes += total_rx_bytes;
703 adapter->net_stats.rx_packets += total_rx_packets;
708 static int ixgbe_clean_rxonly(struct napi_struct *, int);
710 * ixgbe_configure_msix - Configure MSI-X hardware
711 * @adapter: board private structure
713 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
716 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
718 struct ixgbe_q_vector *q_vector;
719 int i, j, q_vectors, v_idx, r_idx;
722 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
724 /* Populate the IVAR table and set the ITR values to the
725 * corresponding register.
727 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
728 q_vector = &adapter->q_vector[v_idx];
729 /* XXX for_each_bit(...) */
730 r_idx = find_first_bit(q_vector->rxr_idx,
731 adapter->num_rx_queues);
733 for (i = 0; i < q_vector->rxr_count; i++) {
734 j = adapter->rx_ring[r_idx].reg_idx;
735 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
736 r_idx = find_next_bit(q_vector->rxr_idx,
737 adapter->num_rx_queues,
740 r_idx = find_first_bit(q_vector->txr_idx,
741 adapter->num_tx_queues);
743 for (i = 0; i < q_vector->txr_count; i++) {
744 j = adapter->tx_ring[r_idx].reg_idx;
745 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
746 r_idx = find_next_bit(q_vector->txr_idx,
747 adapter->num_tx_queues,
751 /* if this is a tx only vector halve the interrupt rate */
752 if (q_vector->txr_count && !q_vector->rxr_count)
753 q_vector->eitr = (adapter->eitr_param >> 1);
756 q_vector->eitr = adapter->eitr_param;
758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
759 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
762 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
765 /* set up to autoclear timer, and the vectors */
766 mask = IXGBE_EIMS_ENABLE_MASK;
767 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
768 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
775 latency_invalid = 255
779 * ixgbe_update_itr - update the dynamic ITR value based on statistics
780 * @adapter: pointer to adapter
781 * @eitr: eitr setting (ints per sec) to give last timeslice
782 * @itr_setting: current throttle rate in ints/second
783 * @packets: the number of packets during this measurement interval
784 * @bytes: the number of bytes during this measurement interval
786 * Stores a new ITR value based on packets and byte
787 * counts during the last interrupt. The advantage of per interrupt
788 * computation is faster updates and more accurate ITR for the current
789 * traffic pattern. Constants in this function were computed
790 * based on theoretical maximum wire speed and thresholds were set based
791 * on testing data as well as attempting to minimize response time
792 * while increasing bulk throughput.
793 * this functionality is controlled by the InterruptThrottleRate module
794 * parameter (see ixgbe_param.c)
796 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
797 u32 eitr, u8 itr_setting,
798 int packets, int bytes)
800 unsigned int retval = itr_setting;
805 goto update_itr_done;
808 /* simple throttlerate management
809 * 0-20MB/s lowest (100000 ints/s)
810 * 20-100MB/s low (20000 ints/s)
811 * 100-1249MB/s bulk (8000 ints/s)
813 /* what was last interrupt timeslice? */
814 timepassed_us = 1000000/eitr;
815 bytes_perint = bytes / timepassed_us; /* bytes/usec */
817 switch (itr_setting) {
819 if (bytes_perint > adapter->eitr_low)
820 retval = low_latency;
823 if (bytes_perint > adapter->eitr_high)
824 retval = bulk_latency;
825 else if (bytes_perint <= adapter->eitr_low)
826 retval = lowest_latency;
829 if (bytes_perint <= adapter->eitr_high)
830 retval = low_latency;
838 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
840 struct ixgbe_adapter *adapter = q_vector->adapter;
841 struct ixgbe_hw *hw = &adapter->hw;
843 u8 current_itr, ret_itr;
844 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
845 sizeof(struct ixgbe_q_vector);
846 struct ixgbe_ring *rx_ring, *tx_ring;
848 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
849 for (i = 0; i < q_vector->txr_count; i++) {
850 tx_ring = &(adapter->tx_ring[r_idx]);
851 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
853 tx_ring->total_packets,
854 tx_ring->total_bytes);
855 /* if the result for this queue would decrease interrupt
856 * rate for this vector then use that result */
857 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
858 q_vector->tx_itr - 1 : ret_itr);
859 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
863 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
864 for (i = 0; i < q_vector->rxr_count; i++) {
865 rx_ring = &(adapter->rx_ring[r_idx]);
866 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
868 rx_ring->total_packets,
869 rx_ring->total_bytes);
870 /* if the result for this queue would decrease interrupt
871 * rate for this vector then use that result */
872 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
873 q_vector->rx_itr - 1 : ret_itr);
874 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
878 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
880 switch (current_itr) {
881 /* counts and packets in update_itr are dependent on these numbers */
886 new_itr = 20000; /* aka hwitr = ~200 */
894 if (new_itr != q_vector->eitr) {
896 /* do an exponential smoothing */
897 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
898 q_vector->eitr = new_itr;
899 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
900 /* must write high and low 16 bits to reset counter */
901 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
903 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
909 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
911 struct ixgbe_hw *hw = &adapter->hw;
913 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
914 (eicr & IXGBE_EICR_GPI_SDP1)) {
915 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
916 /* write to clear the interrupt */
917 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
921 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
923 struct ixgbe_hw *hw = &adapter->hw;
926 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
927 adapter->link_check_timeout = jiffies;
928 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
930 schedule_work(&adapter->watchdog_task);
934 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
936 struct net_device *netdev = data;
937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
938 struct ixgbe_hw *hw = &adapter->hw;
942 * Workaround for Silicon errata. Use clear-by-write instead
943 * of clear-by-read. Reading with EICS will return the
944 * interrupt causes without clearing, which later be done
945 * with the write to EICR.
947 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
948 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
950 if (eicr & IXGBE_EICR_LSC)
951 ixgbe_check_lsc(adapter);
953 ixgbe_check_fan_failure(adapter, eicr);
955 if (!test_bit(__IXGBE_DOWN, &adapter->state))
956 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
961 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
963 struct ixgbe_q_vector *q_vector = data;
964 struct ixgbe_adapter *adapter = q_vector->adapter;
965 struct ixgbe_ring *tx_ring;
968 if (!q_vector->txr_count)
971 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
972 for (i = 0; i < q_vector->txr_count; i++) {
973 tx_ring = &(adapter->tx_ring[r_idx]);
974 #ifdef CONFIG_IXGBE_DCA
975 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
976 ixgbe_update_tx_dca(adapter, tx_ring);
978 tx_ring->total_bytes = 0;
979 tx_ring->total_packets = 0;
980 ixgbe_clean_tx_irq(adapter, tx_ring);
981 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
989 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
991 * @data: pointer to our q_vector struct for this interrupt vector
993 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
995 struct ixgbe_q_vector *q_vector = data;
996 struct ixgbe_adapter *adapter = q_vector->adapter;
997 struct ixgbe_ring *rx_ring;
1001 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1002 for (i = 0; i < q_vector->rxr_count; i++) {
1003 rx_ring = &(adapter->rx_ring[r_idx]);
1004 rx_ring->total_bytes = 0;
1005 rx_ring->total_packets = 0;
1006 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1010 if (!q_vector->rxr_count)
1013 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1014 rx_ring = &(adapter->rx_ring[r_idx]);
1015 /* disable interrupts on this vector only */
1016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1017 napi_schedule(&q_vector->napi);
1022 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1024 ixgbe_msix_clean_rx(irq, data);
1025 ixgbe_msix_clean_tx(irq, data);
1031 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1032 * @napi: napi struct with our devices info in it
1033 * @budget: amount of work driver is allowed to do this pass, in packets
1035 * This function is optimized for cleaning one queue only on a single
1038 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1040 struct ixgbe_q_vector *q_vector =
1041 container_of(napi, struct ixgbe_q_vector, napi);
1042 struct ixgbe_adapter *adapter = q_vector->adapter;
1043 struct ixgbe_ring *rx_ring = NULL;
1047 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1048 rx_ring = &(adapter->rx_ring[r_idx]);
1049 #ifdef CONFIG_IXGBE_DCA
1050 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1051 ixgbe_update_rx_dca(adapter, rx_ring);
1054 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1056 /* If all Rx work done, exit the polling mode */
1057 if (work_done < budget) {
1058 napi_complete(napi);
1059 if (adapter->itr_setting & 3)
1060 ixgbe_set_itr_msix(q_vector);
1061 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1062 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1069 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1070 * @napi: napi struct with our devices info in it
1071 * @budget: amount of work driver is allowed to do this pass, in packets
1073 * This function will clean more than one rx queue associated with a
1076 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1078 struct ixgbe_q_vector *q_vector =
1079 container_of(napi, struct ixgbe_q_vector, napi);
1080 struct ixgbe_adapter *adapter = q_vector->adapter;
1081 struct ixgbe_ring *rx_ring = NULL;
1082 int work_done = 0, i;
1084 u16 enable_mask = 0;
1086 /* attempt to distribute budget to each queue fairly, but don't allow
1087 * the budget to go below 1 because we'll exit polling */
1088 budget /= (q_vector->rxr_count ?: 1);
1089 budget = max(budget, 1);
1090 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1091 for (i = 0; i < q_vector->rxr_count; i++) {
1092 rx_ring = &(adapter->rx_ring[r_idx]);
1093 #ifdef CONFIG_IXGBE_DCA
1094 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1095 ixgbe_update_rx_dca(adapter, rx_ring);
1097 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1098 enable_mask |= rx_ring->v_idx;
1099 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1103 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1104 rx_ring = &(adapter->rx_ring[r_idx]);
1105 /* If all Rx work done, exit the polling mode */
1106 if (work_done < budget) {
1107 napi_complete(napi);
1108 if (adapter->itr_setting & 3)
1109 ixgbe_set_itr_msix(q_vector);
1110 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1111 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1117 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1120 a->q_vector[v_idx].adapter = a;
1121 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1122 a->q_vector[v_idx].rxr_count++;
1123 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1126 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1129 a->q_vector[v_idx].adapter = a;
1130 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1131 a->q_vector[v_idx].txr_count++;
1132 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1136 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1137 * @adapter: board private structure to initialize
1138 * @vectors: allotted vector count for descriptor rings
1140 * This function maps descriptor rings to the queue-specific vectors
1141 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1142 * one vector per ring/queue, but on a constrained vector budget, we
1143 * group the rings as "efficiently" as possible. You would add new
1144 * mapping configurations in here.
1146 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1150 int rxr_idx = 0, txr_idx = 0;
1151 int rxr_remaining = adapter->num_rx_queues;
1152 int txr_remaining = adapter->num_tx_queues;
1157 /* No mapping required if MSI-X is disabled. */
1158 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1162 * The ideal configuration...
1163 * We have enough vectors to map one per queue.
1165 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1166 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1167 map_vector_to_rxq(adapter, v_start, rxr_idx);
1169 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1170 map_vector_to_txq(adapter, v_start, txr_idx);
1176 * If we don't have enough vectors for a 1-to-1
1177 * mapping, we'll have to group them so there are
1178 * multiple queues per vector.
1180 /* Re-adjusting *qpv takes care of the remainder. */
1181 for (i = v_start; i < vectors; i++) {
1182 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1183 for (j = 0; j < rqpv; j++) {
1184 map_vector_to_rxq(adapter, i, rxr_idx);
1189 for (i = v_start; i < vectors; i++) {
1190 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1191 for (j = 0; j < tqpv; j++) {
1192 map_vector_to_txq(adapter, i, txr_idx);
1203 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1204 * @adapter: board private structure
1206 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1207 * interrupts from the kernel.
1209 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1211 struct net_device *netdev = adapter->netdev;
1212 irqreturn_t (*handler)(int, void *);
1213 int i, vector, q_vectors, err;
1216 /* Decrement for Other and TCP Timer vectors */
1217 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1219 /* Map the Tx/Rx rings to the vectors we were allotted. */
1220 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1224 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1225 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1226 &ixgbe_msix_clean_many)
1227 for (vector = 0; vector < q_vectors; vector++) {
1228 handler = SET_HANDLER(&adapter->q_vector[vector]);
1230 if(handler == &ixgbe_msix_clean_rx) {
1231 sprintf(adapter->name[vector], "%s-%s-%d",
1232 netdev->name, "rx", ri++);
1234 else if(handler == &ixgbe_msix_clean_tx) {
1235 sprintf(adapter->name[vector], "%s-%s-%d",
1236 netdev->name, "tx", ti++);
1239 sprintf(adapter->name[vector], "%s-%s-%d",
1240 netdev->name, "TxRx", vector);
1242 err = request_irq(adapter->msix_entries[vector].vector,
1243 handler, 0, adapter->name[vector],
1244 &(adapter->q_vector[vector]));
1247 "request_irq failed for MSIX interrupt "
1248 "Error: %d\n", err);
1249 goto free_queue_irqs;
1253 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1254 err = request_irq(adapter->msix_entries[vector].vector,
1255 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1258 "request_irq for msix_lsc failed: %d\n", err);
1259 goto free_queue_irqs;
1265 for (i = vector - 1; i >= 0; i--)
1266 free_irq(adapter->msix_entries[--vector].vector,
1267 &(adapter->q_vector[i]));
1268 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1269 pci_disable_msix(adapter->pdev);
1270 kfree(adapter->msix_entries);
1271 adapter->msix_entries = NULL;
1276 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1278 struct ixgbe_hw *hw = &adapter->hw;
1279 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1281 u32 new_itr = q_vector->eitr;
1282 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1283 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1285 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1287 tx_ring->total_packets,
1288 tx_ring->total_bytes);
1289 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1291 rx_ring->total_packets,
1292 rx_ring->total_bytes);
1294 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1296 switch (current_itr) {
1297 /* counts and packets in update_itr are dependent on these numbers */
1298 case lowest_latency:
1302 new_itr = 20000; /* aka hwitr = ~200 */
1311 if (new_itr != q_vector->eitr) {
1313 /* do an exponential smoothing */
1314 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1315 q_vector->eitr = new_itr;
1316 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1317 /* must write high and low 16 bits to reset counter */
1318 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1325 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1326 * @adapter: board private structure
1328 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1331 IXGBE_WRITE_FLUSH(&adapter->hw);
1332 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1334 for (i = 0; i < adapter->num_msix_vectors; i++)
1335 synchronize_irq(adapter->msix_entries[i].vector);
1337 synchronize_irq(adapter->pdev->irq);
1342 * ixgbe_irq_enable - Enable default interrupt generation settings
1343 * @adapter: board private structure
1345 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1348 mask = IXGBE_EIMS_ENABLE_MASK;
1349 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1350 mask |= IXGBE_EIMS_GPI_SDP1;
1351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1352 IXGBE_WRITE_FLUSH(&adapter->hw);
1356 * ixgbe_intr - legacy mode Interrupt Handler
1357 * @irq: interrupt number
1358 * @data: pointer to a network interface device structure
1360 static irqreturn_t ixgbe_intr(int irq, void *data)
1362 struct net_device *netdev = data;
1363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1364 struct ixgbe_hw *hw = &adapter->hw;
1368 * Workaround for silicon errata. Mask the interrupts
1369 * before the read of EICR.
1371 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1373 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1374 * therefore no explict interrupt disable is necessary */
1375 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1377 /* shared interrupt alert!
1378 * make sure interrupts are enabled because the read will
1379 * have disabled interrupts due to EIAM */
1380 ixgbe_irq_enable(adapter);
1381 return IRQ_NONE; /* Not our interrupt */
1384 if (eicr & IXGBE_EICR_LSC)
1385 ixgbe_check_lsc(adapter);
1387 ixgbe_check_fan_failure(adapter, eicr);
1389 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1390 adapter->tx_ring[0].total_packets = 0;
1391 adapter->tx_ring[0].total_bytes = 0;
1392 adapter->rx_ring[0].total_packets = 0;
1393 adapter->rx_ring[0].total_bytes = 0;
1394 /* would disable interrupts here but EIAM disabled it */
1395 __napi_schedule(&adapter->q_vector[0].napi);
1401 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1403 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1405 for (i = 0; i < q_vectors; i++) {
1406 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1407 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1408 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1409 q_vector->rxr_count = 0;
1410 q_vector->txr_count = 0;
1415 * ixgbe_request_irq - initialize interrupts
1416 * @adapter: board private structure
1418 * Attempts to configure interrupts using the best available
1419 * capabilities of the hardware and kernel.
1421 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1423 struct net_device *netdev = adapter->netdev;
1426 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1427 err = ixgbe_request_msix_irqs(adapter);
1428 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1429 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1430 netdev->name, netdev);
1432 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1433 netdev->name, netdev);
1437 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1442 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1444 struct net_device *netdev = adapter->netdev;
1446 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1449 q_vectors = adapter->num_msix_vectors;
1452 free_irq(adapter->msix_entries[i].vector, netdev);
1455 for (; i >= 0; i--) {
1456 free_irq(adapter->msix_entries[i].vector,
1457 &(adapter->q_vector[i]));
1460 ixgbe_reset_q_vectors(adapter);
1462 free_irq(adapter->pdev->irq, netdev);
1467 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1470 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1472 struct ixgbe_hw *hw = &adapter->hw;
1474 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1475 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1477 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
1478 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1480 map_vector_to_rxq(adapter, 0, 0);
1481 map_vector_to_txq(adapter, 0, 0);
1483 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1487 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1488 * @adapter: board private structure
1490 * Configure the Tx unit of the MAC after a reset.
1492 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1495 struct ixgbe_hw *hw = &adapter->hw;
1496 u32 i, j, tdlen, txctrl;
1498 /* Setup the HW Tx Head and Tail descriptor pointers */
1499 for (i = 0; i < adapter->num_tx_queues; i++) {
1500 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1503 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1504 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1505 (tdba & DMA_32BIT_MASK));
1506 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1507 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1508 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1509 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1510 adapter->tx_ring[i].head = IXGBE_TDH(j);
1511 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1512 /* Disable Tx Head Writeback RO bit, since this hoses
1513 * bookkeeping if things aren't delivered in order.
1515 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1516 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1517 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1521 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1523 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1525 struct ixgbe_ring *rx_ring;
1530 /* program one srrctl register per VMDq index */
1531 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1533 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1534 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1535 shift = find_first_bit(&mask, len);
1536 queue0 = index & mask;
1537 index = (index & mask) >> shift;
1538 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
1540 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1541 queue0 = index & mask;
1542 index = index & mask;
1545 rx_ring = &adapter->rx_ring[queue0];
1547 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1549 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1550 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1552 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1553 u16 bufsz = IXGBE_RXBUFFER_2048;
1554 /* grow the amount we can receive on large page machines */
1555 if (bufsz < (PAGE_SIZE / 2))
1556 bufsz = (PAGE_SIZE / 2);
1557 /* cap the bufsz at our largest descriptor size */
1558 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1560 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1561 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1562 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1563 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1564 IXGBE_SRRCTL_BSIZEHDR_MASK);
1566 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1568 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1569 srrctl |= IXGBE_RXBUFFER_2048 >>
1570 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1572 srrctl |= rx_ring->rx_buf_len >>
1573 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1579 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1580 * @adapter: board private structure
1582 * Configure the Rx unit of the MAC after a reset.
1584 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1587 struct ixgbe_hw *hw = &adapter->hw;
1588 struct net_device *netdev = adapter->netdev;
1589 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1591 u32 rdlen, rxctrl, rxcsum;
1592 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1593 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1594 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1600 /* Decide whether to use packet split mode or not */
1601 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1603 /* Set the RX buffer length according to the mode */
1604 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1605 rx_buf_len = IXGBE_RX_HDR_SIZE;
1607 if (netdev->mtu <= ETH_DATA_LEN)
1608 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1610 rx_buf_len = ALIGN(max_frame, 1024);
1613 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1614 fctrl |= IXGBE_FCTRL_BAM;
1615 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1618 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1619 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1620 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1622 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1623 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1625 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1626 /* disable receives while setting up the descriptors */
1627 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1628 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1630 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1631 * the Base and Length of the Rx Descriptor Ring */
1632 for (i = 0; i < adapter->num_rx_queues; i++) {
1633 rdba = adapter->rx_ring[i].dma;
1634 j = adapter->rx_ring[i].reg_idx;
1635 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1636 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1637 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1638 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1639 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1640 adapter->rx_ring[i].head = IXGBE_RDH(j);
1641 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1642 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1644 ixgbe_configure_srrctl(adapter, j);
1648 * For VMDq support of different descriptor types or
1649 * buffer sizes through the use of multiple SRRCTL
1650 * registers, RDRXCTL.MVMEN must be set to 1
1652 * also, the manual doesn't mention it clearly but DCA hints
1653 * will only use queue 0's tags unless this bit is set. Side
1654 * effects of setting this bit are only that SRRCTL must be
1655 * fully programmed [0..15]
1657 if (adapter->flags &
1658 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1659 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1660 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1661 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1664 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1665 /* Fill out redirection table */
1666 for (i = 0, j = 0; i < 128; i++, j++) {
1667 if (j == adapter->ring_feature[RING_F_RSS].indices)
1669 /* reta = 4-byte sliding window of
1670 * 0x00..(indices-1)(indices-1)00..etc. */
1671 reta = (reta << 8) | (j * 0x11);
1673 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1676 /* Fill out hash function seeds */
1677 for (i = 0; i < 10; i++)
1678 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1680 mrqc = IXGBE_MRQC_RSSEN
1681 /* Perform hash on these packet types */
1682 | IXGBE_MRQC_RSS_FIELD_IPV4
1683 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1684 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1685 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1686 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1687 | IXGBE_MRQC_RSS_FIELD_IPV6
1688 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1689 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1690 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1691 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1694 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1696 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1697 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1698 /* Disable indicating checksum in descriptor, enables
1700 rxcsum |= IXGBE_RXCSUM_PCSD;
1702 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1703 /* Enable IPv4 payload checksum for UDP fragments
1704 * if PCSD is not set */
1705 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1708 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1711 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1713 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1714 struct ixgbe_hw *hw = &adapter->hw;
1716 /* add VID to filter table */
1717 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1720 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1722 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1723 struct ixgbe_hw *hw = &adapter->hw;
1725 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1726 ixgbe_irq_disable(adapter);
1728 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1730 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1731 ixgbe_irq_enable(adapter);
1733 /* remove VID from filter table */
1734 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1737 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1738 struct vlan_group *grp)
1740 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1743 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1744 ixgbe_irq_disable(adapter);
1745 adapter->vlgrp = grp;
1748 * For a DCB driver, always enable VLAN tag stripping so we can
1749 * still receive traffic from a DCB-enabled host even if we're
1752 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1753 ctrl |= IXGBE_VLNCTRL_VME;
1754 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1755 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1756 ixgbe_vlan_rx_add_vid(netdev, 0);
1759 /* enable VLAN tag insert/strip */
1760 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1761 ctrl |= IXGBE_VLNCTRL_VME;
1762 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1766 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1767 ixgbe_irq_enable(adapter);
1770 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1772 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1774 if (adapter->vlgrp) {
1776 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1777 if (!vlan_group_get_device(adapter->vlgrp, vid))
1779 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1784 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1786 struct dev_mc_list *mc_ptr;
1787 u8 *addr = *mc_addr_ptr;
1790 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1792 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1794 *mc_addr_ptr = NULL;
1800 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1801 * @netdev: network interface device structure
1803 * The set_rx_method entry point is called whenever the unicast/multicast
1804 * address list or the network interface flags are updated. This routine is
1805 * responsible for configuring the hardware for proper unicast, multicast and
1808 static void ixgbe_set_rx_mode(struct net_device *netdev)
1810 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1811 struct ixgbe_hw *hw = &adapter->hw;
1813 u8 *addr_list = NULL;
1816 /* Check for Promiscuous and All Multicast modes */
1818 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1819 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1821 if (netdev->flags & IFF_PROMISC) {
1822 hw->addr_ctrl.user_set_promisc = 1;
1823 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1824 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1826 if (netdev->flags & IFF_ALLMULTI) {
1827 fctrl |= IXGBE_FCTRL_MPE;
1828 fctrl &= ~IXGBE_FCTRL_UPE;
1830 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1832 vlnctrl |= IXGBE_VLNCTRL_VFE;
1833 hw->addr_ctrl.user_set_promisc = 0;
1836 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1837 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1839 /* reprogram secondary unicast list */
1840 addr_count = netdev->uc_count;
1842 addr_list = netdev->uc_list->dmi_addr;
1843 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1844 ixgbe_addr_list_itr);
1846 /* reprogram multicast list */
1847 addr_count = netdev->mc_count;
1849 addr_list = netdev->mc_list->dmi_addr;
1850 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1851 ixgbe_addr_list_itr);
1854 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1857 struct ixgbe_q_vector *q_vector;
1858 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1860 /* legacy and MSI only use one vector */
1861 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1864 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1865 struct napi_struct *napi;
1866 q_vector = &adapter->q_vector[q_idx];
1867 if (!q_vector->rxr_count)
1869 napi = &q_vector->napi;
1870 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1871 (q_vector->rxr_count > 1))
1872 napi->poll = &ixgbe_clean_rxonly_many;
1878 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1881 struct ixgbe_q_vector *q_vector;
1882 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1884 /* legacy and MSI only use one vector */
1885 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1888 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1889 q_vector = &adapter->q_vector[q_idx];
1890 if (!q_vector->rxr_count)
1892 napi_disable(&q_vector->napi);
1896 #ifdef CONFIG_IXGBE_DCB
1898 * ixgbe_configure_dcb - Configure DCB hardware
1899 * @adapter: ixgbe adapter struct
1901 * This is called by the driver on open to configure the DCB hardware.
1902 * This is also called by the gennetlink interface when reconfiguring
1905 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
1907 struct ixgbe_hw *hw = &adapter->hw;
1908 u32 txdctl, vlnctrl;
1911 ixgbe_dcb_check_config(&adapter->dcb_cfg);
1912 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
1913 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
1915 /* reconfigure the hardware */
1916 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
1918 for (i = 0; i < adapter->num_tx_queues; i++) {
1919 j = adapter->tx_ring[i].reg_idx;
1920 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1921 /* PThresh workaround for Tx hang with DFP enabled. */
1923 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1925 /* Enable VLAN tag insert/strip */
1926 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1927 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1928 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1929 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1930 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
1934 static void ixgbe_configure(struct ixgbe_adapter *adapter)
1936 struct net_device *netdev = adapter->netdev;
1939 ixgbe_set_rx_mode(netdev);
1941 ixgbe_restore_vlan(adapter);
1942 #ifdef CONFIG_IXGBE_DCB
1943 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1944 netif_set_gso_max_size(netdev, 32768);
1945 ixgbe_configure_dcb(adapter);
1947 netif_set_gso_max_size(netdev, 65536);
1950 netif_set_gso_max_size(netdev, 65536);
1953 ixgbe_configure_tx(adapter);
1954 ixgbe_configure_rx(adapter);
1955 for (i = 0; i < adapter->num_rx_queues; i++)
1956 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1957 (adapter->rx_ring[i].count - 1));
1961 * ixgbe_link_config - set up initial link with default speed and duplex
1962 * @hw: pointer to private hardware struct
1964 * Returns 0 on success, negative on failure
1966 static int ixgbe_link_config(struct ixgbe_hw *hw)
1969 bool link_up = false;
1970 u32 ret = IXGBE_ERR_LINK_SETUP;
1972 if (hw->mac.ops.check_link)
1973 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1978 if (hw->mac.ops.get_link_capabilities)
1979 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
1984 if (hw->mac.ops.setup_link_speed)
1985 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
1991 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1993 struct net_device *netdev = adapter->netdev;
1994 struct ixgbe_hw *hw = &adapter->hw;
1997 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1998 u32 txdctl, rxdctl, mhadd;
2001 ixgbe_get_hw_control(adapter);
2003 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2004 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2006 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2007 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2012 /* XXX: to interrupt immediately for EICS writes, enable this */
2013 /* gpie |= IXGBE_GPIE_EIMEN; */
2014 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2017 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2018 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2019 * specifically only auto mask tx and rx interrupts */
2020 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2023 /* Enable fan failure interrupt if media type is copper */
2024 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2025 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2026 gpie |= IXGBE_SDP1_GPIEN;
2027 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2030 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2031 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2032 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2033 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2035 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2038 for (i = 0; i < adapter->num_tx_queues; i++) {
2039 j = adapter->tx_ring[i].reg_idx;
2040 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2041 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2042 txdctl |= (8 << 16);
2043 txdctl |= IXGBE_TXDCTL_ENABLE;
2044 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2047 for (i = 0; i < adapter->num_rx_queues; i++) {
2048 j = adapter->rx_ring[i].reg_idx;
2049 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2050 /* enable PTHRESH=32 descriptors (half the internal cache)
2051 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2052 * this also removes a pesky rx_no_buffer_count increment */
2054 rxdctl |= IXGBE_RXDCTL_ENABLE;
2055 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2057 /* enable all receives */
2058 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2059 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2060 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
2062 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2063 ixgbe_configure_msix(adapter);
2065 ixgbe_configure_msi_and_legacy(adapter);
2067 ixgbe_napi_add_all(adapter);
2069 clear_bit(__IXGBE_DOWN, &adapter->state);
2070 ixgbe_napi_enable_all(adapter);
2072 /* clear any pending interrupts, may auto mask */
2073 IXGBE_READ_REG(hw, IXGBE_EICR);
2075 ixgbe_irq_enable(adapter);
2077 err = ixgbe_link_config(hw);
2079 dev_err(&adapter->pdev->dev, "link_config FAILED %d\n", err);
2081 /* enable transmits */
2082 netif_tx_start_all_queues(netdev);
2084 /* bring the link up in the watchdog, this could race with our first
2085 * link up interrupt but shouldn't be a problem */
2086 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2087 adapter->link_check_timeout = jiffies;
2088 mod_timer(&adapter->watchdog_timer, jiffies);
2092 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2094 WARN_ON(in_interrupt());
2095 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2097 ixgbe_down(adapter);
2099 clear_bit(__IXGBE_RESETTING, &adapter->state);
2102 int ixgbe_up(struct ixgbe_adapter *adapter)
2104 /* hardware has been reset, we need to reload some things */
2105 ixgbe_configure(adapter);
2107 return ixgbe_up_complete(adapter);
2110 void ixgbe_reset(struct ixgbe_adapter *adapter)
2112 struct ixgbe_hw *hw = &adapter->hw;
2113 if (hw->mac.ops.init_hw(hw))
2114 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2116 /* reprogram the RAR[0] in case user changed it. */
2117 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2122 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2123 * @adapter: board private structure
2124 * @rx_ring: ring to free buffers from
2126 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2127 struct ixgbe_ring *rx_ring)
2129 struct pci_dev *pdev = adapter->pdev;
2133 /* Free all the Rx ring sk_buffs */
2135 for (i = 0; i < rx_ring->count; i++) {
2136 struct ixgbe_rx_buffer *rx_buffer_info;
2138 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2139 if (rx_buffer_info->dma) {
2140 pci_unmap_single(pdev, rx_buffer_info->dma,
2141 rx_ring->rx_buf_len,
2142 PCI_DMA_FROMDEVICE);
2143 rx_buffer_info->dma = 0;
2145 if (rx_buffer_info->skb) {
2146 dev_kfree_skb(rx_buffer_info->skb);
2147 rx_buffer_info->skb = NULL;
2149 if (!rx_buffer_info->page)
2151 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2152 PCI_DMA_FROMDEVICE);
2153 rx_buffer_info->page_dma = 0;
2154 put_page(rx_buffer_info->page);
2155 rx_buffer_info->page = NULL;
2156 rx_buffer_info->page_offset = 0;
2159 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2160 memset(rx_ring->rx_buffer_info, 0, size);
2162 /* Zero out the descriptor ring */
2163 memset(rx_ring->desc, 0, rx_ring->size);
2165 rx_ring->next_to_clean = 0;
2166 rx_ring->next_to_use = 0;
2168 writel(0, adapter->hw.hw_addr + rx_ring->head);
2169 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2173 * ixgbe_clean_tx_ring - Free Tx Buffers
2174 * @adapter: board private structure
2175 * @tx_ring: ring to be cleaned
2177 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2178 struct ixgbe_ring *tx_ring)
2180 struct ixgbe_tx_buffer *tx_buffer_info;
2184 /* Free all the Tx ring sk_buffs */
2186 for (i = 0; i < tx_ring->count; i++) {
2187 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2188 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2191 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2192 memset(tx_ring->tx_buffer_info, 0, size);
2194 /* Zero out the descriptor ring */
2195 memset(tx_ring->desc, 0, tx_ring->size);
2197 tx_ring->next_to_use = 0;
2198 tx_ring->next_to_clean = 0;
2200 writel(0, adapter->hw.hw_addr + tx_ring->head);
2201 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2205 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2206 * @adapter: board private structure
2208 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2212 for (i = 0; i < adapter->num_rx_queues; i++)
2213 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2217 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2218 * @adapter: board private structure
2220 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2224 for (i = 0; i < adapter->num_tx_queues; i++)
2225 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2228 void ixgbe_down(struct ixgbe_adapter *adapter)
2230 struct net_device *netdev = adapter->netdev;
2231 struct ixgbe_hw *hw = &adapter->hw;
2236 /* signal that we are down to the interrupt handler */
2237 set_bit(__IXGBE_DOWN, &adapter->state);
2239 /* disable receives */
2240 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2241 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2243 netif_tx_disable(netdev);
2245 IXGBE_WRITE_FLUSH(hw);
2248 netif_tx_stop_all_queues(netdev);
2250 ixgbe_irq_disable(adapter);
2252 ixgbe_napi_disable_all(adapter);
2254 del_timer_sync(&adapter->watchdog_timer);
2255 cancel_work_sync(&adapter->watchdog_task);
2257 /* disable transmits in the hardware now that interrupts are off */
2258 for (i = 0; i < adapter->num_tx_queues; i++) {
2259 j = adapter->tx_ring[i].reg_idx;
2260 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2261 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2262 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2265 netif_carrier_off(netdev);
2267 #ifdef CONFIG_IXGBE_DCA
2268 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2269 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2270 dca_remove_requester(&adapter->pdev->dev);
2274 if (!pci_channel_offline(adapter->pdev))
2275 ixgbe_reset(adapter);
2276 ixgbe_clean_all_tx_rings(adapter);
2277 ixgbe_clean_all_rx_rings(adapter);
2279 #ifdef CONFIG_IXGBE_DCA
2280 /* since we reset the hardware DCA settings were cleared */
2281 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2282 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2283 /* always use CB2 mode, difference is masked
2284 * in the CB driver */
2285 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2286 ixgbe_setup_dca(adapter);
2292 * ixgbe_poll - NAPI Rx polling callback
2293 * @napi: structure for representing this polling device
2294 * @budget: how many packets driver is allowed to clean
2296 * This function is used for legacy and MSI, NAPI mode
2298 static int ixgbe_poll(struct napi_struct *napi, int budget)
2300 struct ixgbe_q_vector *q_vector = container_of(napi,
2301 struct ixgbe_q_vector, napi);
2302 struct ixgbe_adapter *adapter = q_vector->adapter;
2303 int tx_cleaned, work_done = 0;
2305 #ifdef CONFIG_IXGBE_DCA
2306 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2307 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2308 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2312 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2313 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2318 /* If budget not fully consumed, exit the polling mode */
2319 if (work_done < budget) {
2320 napi_complete(napi);
2321 if (adapter->itr_setting & 3)
2322 ixgbe_set_itr(adapter);
2323 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2324 ixgbe_irq_enable(adapter);
2330 * ixgbe_tx_timeout - Respond to a Tx Hang
2331 * @netdev: network interface device structure
2333 static void ixgbe_tx_timeout(struct net_device *netdev)
2335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2337 /* Do the reset outside of interrupt context */
2338 schedule_work(&adapter->reset_task);
2341 static void ixgbe_reset_task(struct work_struct *work)
2343 struct ixgbe_adapter *adapter;
2344 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2346 /* If we're already down or resetting, just bail */
2347 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2348 test_bit(__IXGBE_RESETTING, &adapter->state))
2351 adapter->tx_timeout_count++;
2353 ixgbe_reinit_locked(adapter);
2356 #ifdef CONFIG_IXGBE_DCB
2357 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2361 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2362 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2363 adapter->num_rx_queues =
2364 adapter->ring_feature[RING_F_DCB].indices;
2365 adapter->num_tx_queues =
2366 adapter->ring_feature[RING_F_DCB].indices;
2376 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2380 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2381 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2382 adapter->num_rx_queues =
2383 adapter->ring_feature[RING_F_RSS].indices;
2384 adapter->num_tx_queues =
2385 adapter->ring_feature[RING_F_RSS].indices;
2394 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2396 /* Start with base case */
2397 adapter->num_rx_queues = 1;
2398 adapter->num_tx_queues = 1;
2400 #ifdef CONFIG_IXGBE_DCB
2401 if (ixgbe_set_dcb_queues(adapter))
2405 if (ixgbe_set_rss_queues(adapter))
2409 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2412 int err, vector_threshold;
2414 /* We'll want at least 3 (vector_threshold):
2417 * 3) Other (Link Status Change, etc.)
2418 * 4) TCP Timer (optional)
2420 vector_threshold = MIN_MSIX_COUNT;
2422 /* The more we get, the more we will assign to Tx/Rx Cleanup
2423 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2424 * Right now, we simply care about how many we'll get; we'll
2425 * set them up later while requesting irq's.
2427 while (vectors >= vector_threshold) {
2428 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2430 if (!err) /* Success in acquiring all requested vectors. */
2433 vectors = 0; /* Nasty failure, quit now */
2434 else /* err == number of vectors we should try again with */
2438 if (vectors < vector_threshold) {
2439 /* Can't allocate enough MSI-X interrupts? Oh well.
2440 * This just means we'll go with either a single MSI
2441 * vector or fall back to legacy interrupts.
2443 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2444 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2445 kfree(adapter->msix_entries);
2446 adapter->msix_entries = NULL;
2447 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2448 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2449 ixgbe_set_num_queues(adapter);
2451 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2453 * Adjust for only the vectors we'll use, which is minimum
2454 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2455 * vectors we were allocated.
2457 adapter->num_msix_vectors = min(vectors,
2458 adapter->max_msix_q_vectors + NON_Q_VECTORS);
2463 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2464 * @adapter: board private structure to initialize
2466 * Cache the descriptor ring offsets for RSS to the assigned rings.
2469 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2474 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2475 for (i = 0; i < adapter->num_rx_queues; i++)
2476 adapter->rx_ring[i].reg_idx = i;
2477 for (i = 0; i < adapter->num_tx_queues; i++)
2478 adapter->tx_ring[i].reg_idx = i;
2487 #ifdef CONFIG_IXGBE_DCB
2489 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2490 * @adapter: board private structure to initialize
2492 * Cache the descriptor ring offsets for DCB to the assigned rings.
2495 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2499 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2501 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2502 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2503 /* the number of queues is assumed to be symmetric */
2504 for (i = 0; i < dcb_i; i++) {
2505 adapter->rx_ring[i].reg_idx = i << 3;
2506 adapter->tx_ring[i].reg_idx = i << 2;
2521 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2522 * @adapter: board private structure to initialize
2524 * Once we know the feature-set enabled for the device, we'll cache
2525 * the register offset the descriptor ring is assigned to.
2527 * Note, the order the various feature calls is important. It must start with
2528 * the "most" features enabled at the same time, then trickle down to the
2529 * least amount of features turned on at once.
2531 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2533 /* start with default case */
2534 adapter->rx_ring[0].reg_idx = 0;
2535 adapter->tx_ring[0].reg_idx = 0;
2537 #ifdef CONFIG_IXGBE_DCB
2538 if (ixgbe_cache_ring_dcb(adapter))
2542 if (ixgbe_cache_ring_rss(adapter))
2547 * ixgbe_alloc_queues - Allocate memory for all rings
2548 * @adapter: board private structure to initialize
2550 * We allocate one ring per queue at run-time since we don't know the
2551 * number of queues at compile-time.
2553 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2557 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2558 sizeof(struct ixgbe_ring), GFP_KERNEL);
2559 if (!adapter->tx_ring)
2560 goto err_tx_ring_allocation;
2562 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2563 sizeof(struct ixgbe_ring), GFP_KERNEL);
2564 if (!adapter->rx_ring)
2565 goto err_rx_ring_allocation;
2567 for (i = 0; i < adapter->num_tx_queues; i++) {
2568 adapter->tx_ring[i].count = adapter->tx_ring_count;
2569 adapter->tx_ring[i].queue_index = i;
2572 for (i = 0; i < adapter->num_rx_queues; i++) {
2573 adapter->rx_ring[i].count = adapter->rx_ring_count;
2574 adapter->rx_ring[i].queue_index = i;
2577 ixgbe_cache_ring_register(adapter);
2581 err_rx_ring_allocation:
2582 kfree(adapter->tx_ring);
2583 err_tx_ring_allocation:
2588 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2589 * @adapter: board private structure to initialize
2591 * Attempt to configure the interrupts using the best available
2592 * capabilities of the hardware and the kernel.
2594 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2597 int vector, v_budget;
2600 * It's easy to be greedy for MSI-X vectors, but it really
2601 * doesn't do us much good if we have a lot more vectors
2602 * than CPU's. So let's be conservative and only ask for
2603 * (roughly) twice the number of vectors as there are CPU's.
2605 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2606 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2609 * At the same time, hardware can only support a maximum of
2610 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2611 * we can easily reach upwards of 64 Rx descriptor queues and
2612 * 32 Tx queues. Thus, we cap it off in those rare cases where
2613 * the cpu count also exceeds our vector limit.
2615 v_budget = min(v_budget, MAX_MSIX_COUNT);
2617 /* A failure in MSI-X entry allocation isn't fatal, but it does
2618 * mean we disable MSI-X capabilities of the adapter. */
2619 adapter->msix_entries = kcalloc(v_budget,
2620 sizeof(struct msix_entry), GFP_KERNEL);
2621 if (!adapter->msix_entries) {
2622 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2623 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2624 ixgbe_set_num_queues(adapter);
2625 kfree(adapter->tx_ring);
2626 kfree(adapter->rx_ring);
2627 err = ixgbe_alloc_queues(adapter);
2629 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2637 for (vector = 0; vector < v_budget; vector++)
2638 adapter->msix_entries[vector].entry = vector;
2640 ixgbe_acquire_msix_vectors(adapter, v_budget);
2642 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2646 err = pci_enable_msi(adapter->pdev);
2648 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2650 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2651 "falling back to legacy. Error: %d\n", err);
2657 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2658 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2663 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2666 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2667 pci_disable_msix(adapter->pdev);
2668 kfree(adapter->msix_entries);
2669 adapter->msix_entries = NULL;
2670 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2671 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2672 pci_disable_msi(adapter->pdev);
2678 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2679 * @adapter: board private structure to initialize
2681 * We determine which interrupt scheme to use based on...
2682 * - Kernel support (MSI, MSI-X)
2683 * - which can be user-defined (via MODULE_PARAM)
2684 * - Hardware queue count (num_*_queues)
2685 * - defined by miscellaneous hardware support/features (RSS, etc.)
2687 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2691 /* Number of supported queues */
2692 ixgbe_set_num_queues(adapter);
2694 err = ixgbe_alloc_queues(adapter);
2696 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2697 goto err_alloc_queues;
2700 err = ixgbe_set_interrupt_capability(adapter);
2702 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2703 goto err_set_interrupt;
2706 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2707 "Tx Queue count = %u\n",
2708 (adapter->num_rx_queues > 1) ? "Enabled" :
2709 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2711 set_bit(__IXGBE_DOWN, &adapter->state);
2716 kfree(adapter->tx_ring);
2717 kfree(adapter->rx_ring);
2723 * ixgbe_sfp_timer - worker thread to find a missing module
2724 * @data: pointer to our adapter struct
2726 static void ixgbe_sfp_timer(unsigned long data)
2728 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2730 /* Do the sfp_timer outside of interrupt context due to the
2731 * delays that sfp+ detection requires
2733 schedule_work(&adapter->sfp_task);
2737 * ixgbe_sfp_task - worker thread to find a missing module
2738 * @work: pointer to work_struct containing our data
2740 static void ixgbe_sfp_task(struct work_struct *work)
2742 struct ixgbe_adapter *adapter = container_of(work,
2743 struct ixgbe_adapter,
2745 struct ixgbe_hw *hw = &adapter->hw;
2747 if ((hw->phy.type == ixgbe_phy_nl) &&
2748 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
2749 s32 ret = hw->phy.ops.identify_sfp(hw);
2752 ret = hw->phy.ops.reset(hw);
2753 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2754 DPRINTK(PROBE, ERR, "failed to initialize because an "
2755 "unsupported SFP+ module type was detected.\n"
2756 "Reload the driver after installing a "
2757 "supported module.\n");
2758 unregister_netdev(adapter->netdev);
2760 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
2763 /* don't need this routine any more */
2764 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2768 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
2769 mod_timer(&adapter->sfp_timer,
2770 round_jiffies(jiffies + (2 * HZ)));
2774 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2775 * @adapter: board private structure to initialize
2777 * ixgbe_sw_init initializes the Adapter private data structure.
2778 * Fields are initialized based on PCI device information and
2779 * OS network device settings (MTU size).
2781 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2783 struct ixgbe_hw *hw = &adapter->hw;
2784 struct pci_dev *pdev = adapter->pdev;
2786 #ifdef CONFIG_IXGBE_DCB
2788 struct tc_configuration *tc;
2791 /* PCI config space info */
2793 hw->vendor_id = pdev->vendor;
2794 hw->device_id = pdev->device;
2795 hw->revision_id = pdev->revision;
2796 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2797 hw->subsystem_device_id = pdev->subsystem_device;
2799 /* Set capability flags */
2800 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2801 adapter->ring_feature[RING_F_RSS].indices = rss;
2802 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2803 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
2804 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
2806 #ifdef CONFIG_IXGBE_DCB
2807 /* Configure DCB traffic classes */
2808 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
2809 tc = &adapter->dcb_cfg.tc_config[j];
2810 tc->path[DCB_TX_CONFIG].bwg_id = 0;
2811 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
2812 tc->path[DCB_RX_CONFIG].bwg_id = 0;
2813 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
2814 tc->dcb_pfc = pfc_disabled;
2816 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
2817 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
2818 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
2819 adapter->dcb_cfg.round_robin_enable = false;
2820 adapter->dcb_set_bitmap = 0x00;
2821 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
2822 adapter->ring_feature[RING_F_DCB].indices);
2825 if (hw->mac.ops.get_media_type &&
2826 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2827 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
2829 /* default flow control settings */
2830 hw->fc.requested_mode = ixgbe_fc_none;
2831 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2832 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2833 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2834 hw->fc.send_xon = true;
2836 /* enable itr by default in dynamic mode */
2837 adapter->itr_setting = 1;
2838 adapter->eitr_param = 20000;
2840 /* set defaults for eitr in MegaBytes */
2841 adapter->eitr_low = 10;
2842 adapter->eitr_high = 20;
2844 /* set default ring sizes */
2845 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2846 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2848 /* initialize eeprom parameters */
2849 if (ixgbe_init_eeprom_params_generic(hw)) {
2850 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2854 /* enable rx csum by default */
2855 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2857 set_bit(__IXGBE_DOWN, &adapter->state);
2863 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2864 * @adapter: board private structure
2865 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2867 * Return 0 on success, negative on failure
2869 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2870 struct ixgbe_ring *tx_ring)
2872 struct pci_dev *pdev = adapter->pdev;
2875 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2876 tx_ring->tx_buffer_info = vmalloc(size);
2877 if (!tx_ring->tx_buffer_info)
2879 memset(tx_ring->tx_buffer_info, 0, size);
2881 /* round up to nearest 4K */
2882 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2883 tx_ring->size = ALIGN(tx_ring->size, 4096);
2885 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2890 tx_ring->next_to_use = 0;
2891 tx_ring->next_to_clean = 0;
2892 tx_ring->work_limit = tx_ring->count;
2896 vfree(tx_ring->tx_buffer_info);
2897 tx_ring->tx_buffer_info = NULL;
2898 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2899 "descriptor ring\n");
2904 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2905 * @adapter: board private structure
2907 * If this function returns with an error, then it's possible one or
2908 * more of the rings is populated (while the rest are not). It is the
2909 * callers duty to clean those orphaned rings.
2911 * Return 0 on success, negative on failure
2913 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2917 for (i = 0; i < adapter->num_tx_queues; i++) {
2918 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2921 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2929 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2930 * @adapter: board private structure
2931 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2933 * Returns 0 on success, negative on failure
2935 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2936 struct ixgbe_ring *rx_ring)
2938 struct pci_dev *pdev = adapter->pdev;
2941 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2942 rx_ring->rx_buffer_info = vmalloc(size);
2943 if (!rx_ring->rx_buffer_info) {
2945 "vmalloc allocation failed for the rx desc ring\n");
2948 memset(rx_ring->rx_buffer_info, 0, size);
2950 /* Round up to nearest 4K */
2951 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2952 rx_ring->size = ALIGN(rx_ring->size, 4096);
2954 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
2956 if (!rx_ring->desc) {
2958 "Memory allocation failed for the rx desc ring\n");
2959 vfree(rx_ring->rx_buffer_info);
2963 rx_ring->next_to_clean = 0;
2964 rx_ring->next_to_use = 0;
2973 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2974 * @adapter: board private structure
2976 * If this function returns with an error, then it's possible one or
2977 * more of the rings is populated (while the rest are not). It is the
2978 * callers duty to clean those orphaned rings.
2980 * Return 0 on success, negative on failure
2983 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2987 for (i = 0; i < adapter->num_rx_queues; i++) {
2988 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2991 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2999 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3000 * @adapter: board private structure
3001 * @tx_ring: Tx descriptor ring for a specific queue
3003 * Free all transmit software resources
3005 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3006 struct ixgbe_ring *tx_ring)
3008 struct pci_dev *pdev = adapter->pdev;
3010 ixgbe_clean_tx_ring(adapter, tx_ring);
3012 vfree(tx_ring->tx_buffer_info);
3013 tx_ring->tx_buffer_info = NULL;
3015 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3017 tx_ring->desc = NULL;
3021 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3022 * @adapter: board private structure
3024 * Free all transmit software resources
3026 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3030 for (i = 0; i < adapter->num_tx_queues; i++)
3031 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3035 * ixgbe_free_rx_resources - Free Rx Resources
3036 * @adapter: board private structure
3037 * @rx_ring: ring to clean the resources from
3039 * Free all receive software resources
3041 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3042 struct ixgbe_ring *rx_ring)
3044 struct pci_dev *pdev = adapter->pdev;
3046 ixgbe_clean_rx_ring(adapter, rx_ring);
3048 vfree(rx_ring->rx_buffer_info);
3049 rx_ring->rx_buffer_info = NULL;
3051 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3053 rx_ring->desc = NULL;
3057 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3058 * @adapter: board private structure
3060 * Free all receive software resources
3062 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3066 for (i = 0; i < adapter->num_rx_queues; i++)
3067 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3071 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3072 * @netdev: network interface device structure
3073 * @new_mtu: new value for maximum frame size
3075 * Returns 0 on success, negative on failure
3077 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3079 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3080 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3082 /* MTU < 68 is an error and causes problems on some kernels */
3083 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3086 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3087 netdev->mtu, new_mtu);
3088 /* must set new MTU before calling down or up */
3089 netdev->mtu = new_mtu;
3091 if (netif_running(netdev))
3092 ixgbe_reinit_locked(adapter);
3098 * ixgbe_open - Called when a network interface is made active
3099 * @netdev: network interface device structure
3101 * Returns 0 on success, negative value on failure
3103 * The open entry point is called when a network interface is made
3104 * active by the system (IFF_UP). At this point all resources needed
3105 * for transmit and receive operations are allocated, the interrupt
3106 * handler is registered with the OS, the watchdog timer is started,
3107 * and the stack is notified that the interface is ready.
3109 static int ixgbe_open(struct net_device *netdev)
3111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3114 /* disallow open during test */
3115 if (test_bit(__IXGBE_TESTING, &adapter->state))
3118 /* allocate transmit descriptors */
3119 err = ixgbe_setup_all_tx_resources(adapter);
3123 /* allocate receive descriptors */
3124 err = ixgbe_setup_all_rx_resources(adapter);
3128 ixgbe_configure(adapter);
3130 err = ixgbe_request_irq(adapter);
3134 err = ixgbe_up_complete(adapter);
3138 netif_tx_start_all_queues(netdev);
3143 ixgbe_release_hw_control(adapter);
3144 ixgbe_free_irq(adapter);
3146 ixgbe_free_all_rx_resources(adapter);
3148 ixgbe_free_all_tx_resources(adapter);
3150 ixgbe_reset(adapter);
3156 * ixgbe_close - Disables a network interface
3157 * @netdev: network interface device structure
3159 * Returns 0, this is not allowed to fail
3161 * The close entry point is called when an interface is de-activated
3162 * by the OS. The hardware is still under the drivers control, but
3163 * needs to be disabled. A global MAC reset is issued to stop the
3164 * hardware, and all transmit and receive resources are freed.
3166 static int ixgbe_close(struct net_device *netdev)
3168 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3170 ixgbe_down(adapter);
3171 ixgbe_free_irq(adapter);
3173 ixgbe_free_all_tx_resources(adapter);
3174 ixgbe_free_all_rx_resources(adapter);
3176 ixgbe_release_hw_control(adapter);
3182 * ixgbe_napi_add_all - prep napi structs for use
3183 * @adapter: private struct
3184 * helper function to napi_add each possible q_vector->napi
3186 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3188 int q_idx, q_vectors;
3189 struct net_device *netdev = adapter->netdev;
3190 int (*poll)(struct napi_struct *, int);
3192 /* check if we already have our netdev->napi_list populated */
3193 if (&netdev->napi_list != netdev->napi_list.next)
3196 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3197 poll = &ixgbe_clean_rxonly;
3198 /* Only enable as many vectors as we have rx queues. */
3199 q_vectors = adapter->num_rx_queues;
3202 /* only one q_vector for legacy modes */
3206 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3207 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3208 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3212 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3215 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3217 /* legacy and MSI only use one vector */
3218 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3221 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3222 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3223 if (!q_vector->rxr_count)
3225 netif_napi_del(&q_vector->napi);
3230 static int ixgbe_resume(struct pci_dev *pdev)
3232 struct net_device *netdev = pci_get_drvdata(pdev);
3233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3236 pci_set_power_state(pdev, PCI_D0);
3237 pci_restore_state(pdev);
3238 err = pci_enable_device(pdev);
3240 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3244 pci_set_master(pdev);
3246 pci_enable_wake(pdev, PCI_D3hot, 0);
3247 pci_enable_wake(pdev, PCI_D3cold, 0);
3249 err = ixgbe_init_interrupt_scheme(adapter);
3251 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3256 ixgbe_napi_add_all(adapter);
3257 ixgbe_reset(adapter);
3259 if (netif_running(netdev)) {
3260 err = ixgbe_open(adapter->netdev);
3265 netif_device_attach(netdev);
3270 #endif /* CONFIG_PM */
3271 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3273 struct net_device *netdev = pci_get_drvdata(pdev);
3274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3279 netif_device_detach(netdev);
3281 if (netif_running(netdev)) {
3282 ixgbe_down(adapter);
3283 ixgbe_free_irq(adapter);
3284 ixgbe_free_all_tx_resources(adapter);
3285 ixgbe_free_all_rx_resources(adapter);
3287 ixgbe_reset_interrupt_capability(adapter);
3288 ixgbe_napi_del_all(adapter);
3289 INIT_LIST_HEAD(&netdev->napi_list);
3290 kfree(adapter->tx_ring);
3291 kfree(adapter->rx_ring);
3294 retval = pci_save_state(pdev);
3299 pci_enable_wake(pdev, PCI_D3hot, 0);
3300 pci_enable_wake(pdev, PCI_D3cold, 0);
3302 ixgbe_release_hw_control(adapter);
3304 pci_disable_device(pdev);
3306 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3311 static void ixgbe_shutdown(struct pci_dev *pdev)
3313 ixgbe_suspend(pdev, PMSG_SUSPEND);
3317 * ixgbe_update_stats - Update the board statistics counters.
3318 * @adapter: board private structure
3320 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3322 struct ixgbe_hw *hw = &adapter->hw;
3324 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3326 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3327 for (i = 0; i < 8; i++) {
3328 /* for packet buffers not used, the register should read 0 */
3329 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3331 adapter->stats.mpc[i] += mpc;
3332 total_mpc += adapter->stats.mpc[i];
3333 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3334 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3335 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3336 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3337 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3338 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3340 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3342 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3344 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3347 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3348 /* work around hardware counting issue */
3349 adapter->stats.gprc -= missed_rx;
3351 /* 82598 hardware only has a 32 bit counter in the high register */
3352 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3353 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3354 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3355 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3356 adapter->stats.bprc += bprc;
3357 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3358 adapter->stats.mprc -= bprc;
3359 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3360 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3361 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3362 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3363 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3364 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3365 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3366 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3367 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3368 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3369 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3370 adapter->stats.lxontxc += lxon;
3371 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3372 adapter->stats.lxofftxc += lxoff;
3373 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3374 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3375 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3377 * 82598 errata - tx of flow control packets is included in tx counters
3379 xon_off_tot = lxon + lxoff;
3380 adapter->stats.gptc -= xon_off_tot;
3381 adapter->stats.mptc -= xon_off_tot;
3382 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3383 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3384 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3385 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3386 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3387 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3388 adapter->stats.ptc64 -= xon_off_tot;
3389 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3390 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3391 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3392 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3393 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3394 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3396 /* Fill out the OS statistics structure */
3397 adapter->net_stats.multicast = adapter->stats.mprc;
3400 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3401 adapter->stats.rlec;
3402 adapter->net_stats.rx_dropped = 0;
3403 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3404 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3405 adapter->net_stats.rx_missed_errors = total_mpc;
3409 * ixgbe_watchdog - Timer Call-back
3410 * @data: pointer to adapter cast into an unsigned long
3412 static void ixgbe_watchdog(unsigned long data)
3414 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3415 struct ixgbe_hw *hw = &adapter->hw;
3417 /* Do the watchdog outside of interrupt context due to the lovely
3418 * delays that some of the newer hardware requires */
3419 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3420 /* Cause software interrupt to ensure rx rings are cleaned */
3421 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3423 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3424 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3426 /* For legacy and MSI interrupts don't set any bits that
3427 * are enabled for EIAM, because this operation would
3428 * set *both* EIMS and EICS for any bit in EIAM */
3429 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3430 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3432 /* Reset the timer */
3433 mod_timer(&adapter->watchdog_timer,
3434 round_jiffies(jiffies + 2 * HZ));
3437 schedule_work(&adapter->watchdog_task);
3441 * ixgbe_watchdog_task - worker thread to bring link up
3442 * @work: pointer to work_struct containing our data
3444 static void ixgbe_watchdog_task(struct work_struct *work)
3446 struct ixgbe_adapter *adapter = container_of(work,
3447 struct ixgbe_adapter,
3449 struct net_device *netdev = adapter->netdev;
3450 struct ixgbe_hw *hw = &adapter->hw;
3451 u32 link_speed = adapter->link_speed;
3452 bool link_up = adapter->link_up;
3454 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3456 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3457 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3459 time_after(jiffies, (adapter->link_check_timeout +
3460 IXGBE_TRY_LINK_TIMEOUT))) {
3461 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3462 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3464 adapter->link_up = link_up;
3465 adapter->link_speed = link_speed;
3469 if (!netif_carrier_ok(netdev)) {
3470 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3471 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3472 #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3473 #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3474 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3475 "Flow Control: %s\n",
3477 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3479 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3480 "1 Gbps" : "unknown speed")),
3481 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3483 (FLOW_TX ? "TX" : "None"))));
3485 netif_carrier_on(netdev);
3487 /* Force detection of hung controller */
3488 adapter->detect_tx_hung = true;
3491 adapter->link_up = false;
3492 adapter->link_speed = 0;
3493 if (netif_carrier_ok(netdev)) {
3494 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3496 netif_carrier_off(netdev);
3500 ixgbe_update_stats(adapter);
3501 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3504 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3505 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3506 u32 tx_flags, u8 *hdr_len)
3508 struct ixgbe_adv_tx_context_desc *context_desc;
3511 struct ixgbe_tx_buffer *tx_buffer_info;
3512 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3513 u32 mss_l4len_idx, l4len;
3515 if (skb_is_gso(skb)) {
3516 if (skb_header_cloned(skb)) {
3517 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3521 l4len = tcp_hdrlen(skb);
3524 if (skb->protocol == htons(ETH_P_IP)) {
3525 struct iphdr *iph = ip_hdr(skb);
3528 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3532 adapter->hw_tso_ctxt++;
3533 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3534 ipv6_hdr(skb)->payload_len = 0;
3535 tcp_hdr(skb)->check =
3536 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3537 &ipv6_hdr(skb)->daddr,
3539 adapter->hw_tso6_ctxt++;
3542 i = tx_ring->next_to_use;
3544 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3545 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3547 /* VLAN MACLEN IPLEN */
3548 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3550 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3551 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3552 IXGBE_ADVTXD_MACLEN_SHIFT);
3553 *hdr_len += skb_network_offset(skb);
3555 (skb_transport_header(skb) - skb_network_header(skb));
3557 (skb_transport_header(skb) - skb_network_header(skb));
3558 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3559 context_desc->seqnum_seed = 0;
3561 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3562 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
3563 IXGBE_ADVTXD_DTYP_CTXT);
3565 if (skb->protocol == htons(ETH_P_IP))
3566 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3567 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3568 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3572 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3573 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3574 /* use index 1 for TSO */
3575 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3576 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3578 tx_buffer_info->time_stamp = jiffies;
3579 tx_buffer_info->next_to_watch = i;
3582 if (i == tx_ring->count)
3584 tx_ring->next_to_use = i;
3591 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3592 struct ixgbe_ring *tx_ring,
3593 struct sk_buff *skb, u32 tx_flags)
3595 struct ixgbe_adv_tx_context_desc *context_desc;
3597 struct ixgbe_tx_buffer *tx_buffer_info;
3598 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3600 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3601 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3602 i = tx_ring->next_to_use;
3603 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3604 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3606 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3608 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3609 vlan_macip_lens |= (skb_network_offset(skb) <<
3610 IXGBE_ADVTXD_MACLEN_SHIFT);
3611 if (skb->ip_summed == CHECKSUM_PARTIAL)
3612 vlan_macip_lens |= (skb_transport_header(skb) -
3613 skb_network_header(skb));
3615 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3616 context_desc->seqnum_seed = 0;
3618 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3619 IXGBE_ADVTXD_DTYP_CTXT);
3621 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3622 switch (skb->protocol) {
3623 case cpu_to_be16(ETH_P_IP):
3624 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3625 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3627 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3629 case cpu_to_be16(ETH_P_IPV6):
3630 /* XXX what about other V6 headers?? */
3631 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3633 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3636 if (unlikely(net_ratelimit())) {
3637 DPRINTK(PROBE, WARNING,
3638 "partial checksum but proto=%x!\n",
3645 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3646 /* use index zero for tx checksum offload */
3647 context_desc->mss_l4len_idx = 0;
3649 tx_buffer_info->time_stamp = jiffies;
3650 tx_buffer_info->next_to_watch = i;
3652 adapter->hw_csum_tx_good++;
3654 if (i == tx_ring->count)
3656 tx_ring->next_to_use = i;
3664 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3665 struct ixgbe_ring *tx_ring,
3666 struct sk_buff *skb, unsigned int first)
3668 struct ixgbe_tx_buffer *tx_buffer_info;
3669 unsigned int len = skb->len;
3670 unsigned int offset = 0, size, count = 0, i;
3671 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3674 len -= skb->data_len;
3676 i = tx_ring->next_to_use;
3679 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3680 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3682 tx_buffer_info->length = size;
3683 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3685 size, PCI_DMA_TODEVICE);
3686 tx_buffer_info->time_stamp = jiffies;
3687 tx_buffer_info->next_to_watch = i;
3693 if (i == tx_ring->count)
3697 for (f = 0; f < nr_frags; f++) {
3698 struct skb_frag_struct *frag;
3700 frag = &skb_shinfo(skb)->frags[f];
3702 offset = frag->page_offset;
3705 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3706 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3708 tx_buffer_info->length = size;
3709 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3714 tx_buffer_info->time_stamp = jiffies;
3715 tx_buffer_info->next_to_watch = i;
3721 if (i == tx_ring->count)
3726 i = tx_ring->count - 1;
3729 tx_ring->tx_buffer_info[i].skb = skb;
3730 tx_ring->tx_buffer_info[first].next_to_watch = i;
3735 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3736 struct ixgbe_ring *tx_ring,
3737 int tx_flags, int count, u32 paylen, u8 hdr_len)
3739 union ixgbe_adv_tx_desc *tx_desc = NULL;
3740 struct ixgbe_tx_buffer *tx_buffer_info;
3741 u32 olinfo_status = 0, cmd_type_len = 0;
3743 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3745 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3747 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3749 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3750 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3752 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3753 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3755 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3756 IXGBE_ADVTXD_POPTS_SHIFT;
3758 /* use index 1 context for tso */
3759 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3760 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3761 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3762 IXGBE_ADVTXD_POPTS_SHIFT;
3764 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3765 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3766 IXGBE_ADVTXD_POPTS_SHIFT;
3768 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3770 i = tx_ring->next_to_use;
3772 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3773 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3774 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3775 tx_desc->read.cmd_type_len =
3776 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3777 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3779 if (i == tx_ring->count)
3783 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3786 * Force memory writes to complete before letting h/w
3787 * know there are new descriptors to fetch. (Only
3788 * applicable for weak-ordered memory model archs,
3793 tx_ring->next_to_use = i;
3794 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3797 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3798 struct ixgbe_ring *tx_ring, int size)
3800 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3802 netif_stop_subqueue(netdev, tx_ring->queue_index);
3803 /* Herbert's original patch had:
3804 * smp_mb__after_netif_stop_queue();
3805 * but since that doesn't exist yet, just open code it. */
3808 /* We need to check again in a case another CPU has just
3809 * made room available. */
3810 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3813 /* A reprieve! - use start_queue because it doesn't call schedule */
3814 netif_start_subqueue(netdev, tx_ring->queue_index);
3815 ++adapter->restart_queue;
3819 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3820 struct ixgbe_ring *tx_ring, int size)
3822 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3824 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3827 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3829 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3830 struct ixgbe_ring *tx_ring;
3832 unsigned int tx_flags = 0;
3838 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3839 tx_ring = &adapter->tx_ring[r_idx];
3841 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3842 tx_flags |= vlan_tx_tag_get(skb);
3843 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3844 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
3845 tx_flags |= (skb->queue_mapping << 13);
3847 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3848 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3849 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3850 tx_flags |= (skb->queue_mapping << 13);
3851 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3852 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3854 /* three things can cause us to need a context descriptor */
3855 if (skb_is_gso(skb) ||
3856 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3857 (tx_flags & IXGBE_TX_FLAGS_VLAN))
3860 count += TXD_USE_COUNT(skb_headlen(skb));
3861 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3862 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3864 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
3866 return NETDEV_TX_BUSY;
3869 if (skb->protocol == htons(ETH_P_IP))
3870 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3871 first = tx_ring->next_to_use;
3872 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3874 dev_kfree_skb_any(skb);
3875 return NETDEV_TX_OK;
3879 tx_flags |= IXGBE_TX_FLAGS_TSO;
3880 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3881 (skb->ip_summed == CHECKSUM_PARTIAL))
3882 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3884 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3885 ixgbe_tx_map(adapter, tx_ring, skb, first),
3888 netdev->trans_start = jiffies;
3890 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3892 return NETDEV_TX_OK;
3896 * ixgbe_get_stats - Get System Network Statistics
3897 * @netdev: network interface device structure
3899 * Returns the address of the device statistics structure.
3900 * The statistics are actually updated from the timer callback.
3902 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3904 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3906 /* only return the current stats */
3907 return &adapter->net_stats;
3911 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3912 * @netdev: network interface device structure
3913 * @p: pointer to an address structure
3915 * Returns 0 on success, negative on failure
3917 static int ixgbe_set_mac(struct net_device *netdev, void *p)
3919 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3920 struct ixgbe_hw *hw = &adapter->hw;
3921 struct sockaddr *addr = p;
3923 if (!is_valid_ether_addr(addr->sa_data))
3924 return -EADDRNOTAVAIL;
3926 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3927 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3929 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3934 #ifdef CONFIG_NET_POLL_CONTROLLER
3936 * Polling 'interrupt' - used by things like netconsole to send skbs
3937 * without having to re-enable interrupts. It's not called while
3938 * the interrupt routine is executing.
3940 static void ixgbe_netpoll(struct net_device *netdev)
3942 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3944 disable_irq(adapter->pdev->irq);
3945 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3946 ixgbe_intr(adapter->pdev->irq, netdev);
3947 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3948 enable_irq(adapter->pdev->irq);
3952 static const struct net_device_ops ixgbe_netdev_ops = {
3953 .ndo_open = ixgbe_open,
3954 .ndo_stop = ixgbe_close,
3955 .ndo_start_xmit = ixgbe_xmit_frame,
3956 .ndo_get_stats = ixgbe_get_stats,
3957 .ndo_set_multicast_list = ixgbe_set_rx_mode,
3958 .ndo_validate_addr = eth_validate_addr,
3959 .ndo_set_mac_address = ixgbe_set_mac,
3960 .ndo_change_mtu = ixgbe_change_mtu,
3961 .ndo_tx_timeout = ixgbe_tx_timeout,
3962 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
3963 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
3964 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
3965 #ifdef CONFIG_NET_POLL_CONTROLLER
3966 .ndo_poll_controller = ixgbe_netpoll,
3971 * ixgbe_probe - Device Initialization Routine
3972 * @pdev: PCI device information struct
3973 * @ent: entry in ixgbe_pci_tbl
3975 * Returns 0 on success, negative on failure
3977 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3978 * The OS initialization, configuring of the adapter private structure,
3979 * and a hardware reset occur.
3981 static int __devinit ixgbe_probe(struct pci_dev *pdev,
3982 const struct pci_device_id *ent)
3984 struct net_device *netdev;
3985 struct ixgbe_adapter *adapter = NULL;
3986 struct ixgbe_hw *hw;
3987 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3988 static int cards_found;
3989 int i, err, pci_using_dac;
3990 u16 link_status, link_speed, link_width;
3993 err = pci_enable_device(pdev);
3997 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3998 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
4001 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4003 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4005 dev_err(&pdev->dev, "No usable DMA "
4006 "configuration, aborting\n");
4013 err = pci_request_regions(pdev, ixgbe_driver_name);
4015 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4019 err = pci_enable_pcie_error_reporting(pdev);
4021 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4023 /* non-fatal, continue */
4026 pci_set_master(pdev);
4027 pci_save_state(pdev);
4029 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4032 goto err_alloc_etherdev;
4035 SET_NETDEV_DEV(netdev, &pdev->dev);
4037 pci_set_drvdata(pdev, netdev);
4038 adapter = netdev_priv(netdev);
4040 adapter->netdev = netdev;
4041 adapter->pdev = pdev;
4044 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4046 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4047 pci_resource_len(pdev, 0));
4053 for (i = 1; i <= 5; i++) {
4054 if (pci_resource_len(pdev, i) == 0)
4058 netdev->netdev_ops = &ixgbe_netdev_ops;
4059 ixgbe_set_ethtool_ops(netdev);
4060 netdev->watchdog_timeo = 5 * HZ;
4061 strcpy(netdev->name, pci_name(pdev));
4063 adapter->bd_number = cards_found;
4066 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4067 hw->mac.type = ii->mac;
4070 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4071 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4072 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4073 if (!(eec & (1 << 8)))
4074 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4077 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4078 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4080 /* set up this timer and work struct before calling get_invariants
4081 * which might start the timer
4083 init_timer(&adapter->sfp_timer);
4084 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4085 adapter->sfp_timer.data = (unsigned long) adapter;
4087 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4089 err = ii->get_invariants(hw);
4090 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4091 /* start a kernel thread to watch for a module to arrive */
4092 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4093 mod_timer(&adapter->sfp_timer,
4094 round_jiffies(jiffies + (2 * HZ)));
4096 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4097 DPRINTK(PROBE, ERR, "failed to load because an "
4098 "unsupported SFP+ module type was detected.\n");
4104 /* setup the private structure */
4105 err = ixgbe_sw_init(adapter);
4109 /* reset_hw fills in the perm_addr as well */
4110 err = hw->mac.ops.reset_hw(hw);
4112 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4116 netdev->features = NETIF_F_SG |
4118 NETIF_F_HW_VLAN_TX |
4119 NETIF_F_HW_VLAN_RX |
4120 NETIF_F_HW_VLAN_FILTER;
4122 netdev->features |= NETIF_F_IPV6_CSUM;
4123 netdev->features |= NETIF_F_TSO;
4124 netdev->features |= NETIF_F_TSO6;
4125 netdev->features |= NETIF_F_GRO;
4127 netdev->vlan_features |= NETIF_F_TSO;
4128 netdev->vlan_features |= NETIF_F_TSO6;
4129 netdev->vlan_features |= NETIF_F_IP_CSUM;
4130 netdev->vlan_features |= NETIF_F_SG;
4132 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4133 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4135 #ifdef CONFIG_IXGBE_DCB
4136 netdev->dcbnl_ops = &dcbnl_ops;
4140 netdev->features |= NETIF_F_HIGHDMA;
4142 /* make sure the EEPROM is good */
4143 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4144 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4149 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4150 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4152 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4153 dev_err(&pdev->dev, "invalid MAC address\n");
4158 init_timer(&adapter->watchdog_timer);
4159 adapter->watchdog_timer.function = &ixgbe_watchdog;
4160 adapter->watchdog_timer.data = (unsigned long)adapter;
4162 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4163 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4165 err = ixgbe_init_interrupt_scheme(adapter);
4169 /* print bus type/speed/width info */
4170 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
4171 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
4172 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
4173 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4174 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
4175 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
4177 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
4178 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
4179 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
4180 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
4183 ixgbe_read_pba_num_generic(hw, &part_num);
4184 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4185 hw->mac.type, hw->phy.type,
4186 (part_num >> 8), (part_num & 0xff));
4188 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
4189 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4190 "this card is not sufficient for optimal "
4192 dev_warn(&pdev->dev, "For optimal performance a x8 "
4193 "PCI-Express slot is required.\n");
4196 /* save off EEPROM version number */
4197 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4199 /* reset the hardware with the new settings */
4200 hw->mac.ops.start_hw(hw);
4202 netif_carrier_off(netdev);
4204 strcpy(netdev->name, "eth%d");
4205 err = register_netdev(netdev);
4209 #ifdef CONFIG_IXGBE_DCA
4210 if (dca_add_requester(&pdev->dev) == 0) {
4211 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4212 /* always use CB2 mode, difference is masked
4213 * in the CB driver */
4214 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4215 ixgbe_setup_dca(adapter);
4219 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4224 ixgbe_release_hw_control(adapter);
4227 ixgbe_reset_interrupt_capability(adapter);
4229 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4230 del_timer_sync(&adapter->sfp_timer);
4231 cancel_work_sync(&adapter->sfp_task);
4232 iounmap(hw->hw_addr);
4234 free_netdev(netdev);
4236 pci_release_regions(pdev);
4239 pci_disable_device(pdev);
4244 * ixgbe_remove - Device Removal Routine
4245 * @pdev: PCI device information struct
4247 * ixgbe_remove is called by the PCI subsystem to alert the driver
4248 * that it should release a PCI device. The could be caused by a
4249 * Hot-Plug event, or because the driver is going to be removed from
4252 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4254 struct net_device *netdev = pci_get_drvdata(pdev);
4255 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4258 set_bit(__IXGBE_DOWN, &adapter->state);
4259 /* clear the module not found bit to make sure the worker won't
4262 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4263 del_timer_sync(&adapter->watchdog_timer);
4265 del_timer_sync(&adapter->sfp_timer);
4266 cancel_work_sync(&adapter->watchdog_task);
4267 cancel_work_sync(&adapter->sfp_task);
4268 flush_scheduled_work();
4270 #ifdef CONFIG_IXGBE_DCA
4271 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4272 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4273 dca_remove_requester(&pdev->dev);
4274 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4278 if (netdev->reg_state == NETREG_REGISTERED)
4279 unregister_netdev(netdev);
4281 ixgbe_reset_interrupt_capability(adapter);
4283 ixgbe_release_hw_control(adapter);
4285 iounmap(adapter->hw.hw_addr);
4286 pci_release_regions(pdev);
4288 DPRINTK(PROBE, INFO, "complete\n");
4289 kfree(adapter->tx_ring);
4290 kfree(adapter->rx_ring);
4292 free_netdev(netdev);
4294 err = pci_disable_pcie_error_reporting(pdev);
4297 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4299 pci_disable_device(pdev);
4303 * ixgbe_io_error_detected - called when PCI error is detected
4304 * @pdev: Pointer to PCI device
4305 * @state: The current pci connection state
4307 * This function is called after a PCI bus error affecting
4308 * this device has been detected.
4310 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4311 pci_channel_state_t state)
4313 struct net_device *netdev = pci_get_drvdata(pdev);
4314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4316 netif_device_detach(netdev);
4318 if (netif_running(netdev))
4319 ixgbe_down(adapter);
4320 pci_disable_device(pdev);
4322 /* Request a slot reset. */
4323 return PCI_ERS_RESULT_NEED_RESET;
4327 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4328 * @pdev: Pointer to PCI device
4330 * Restart the card from scratch, as if from a cold-boot.
4332 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4334 struct net_device *netdev = pci_get_drvdata(pdev);
4335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4336 pci_ers_result_t result;
4339 if (pci_enable_device(pdev)) {
4341 "Cannot re-enable PCI device after reset.\n");
4342 result = PCI_ERS_RESULT_DISCONNECT;
4344 pci_set_master(pdev);
4345 pci_restore_state(pdev);
4347 pci_enable_wake(pdev, PCI_D3hot, 0);
4348 pci_enable_wake(pdev, PCI_D3cold, 0);
4350 ixgbe_reset(adapter);
4352 result = PCI_ERS_RESULT_RECOVERED;
4355 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4358 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4359 /* non-fatal, continue */
4366 * ixgbe_io_resume - called when traffic can start flowing again.
4367 * @pdev: Pointer to PCI device
4369 * This callback is called when the error recovery driver tells us that
4370 * its OK to resume normal operation.
4372 static void ixgbe_io_resume(struct pci_dev *pdev)
4374 struct net_device *netdev = pci_get_drvdata(pdev);
4375 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4377 if (netif_running(netdev)) {
4378 if (ixgbe_up(adapter)) {
4379 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4384 netif_device_attach(netdev);
4387 static struct pci_error_handlers ixgbe_err_handler = {
4388 .error_detected = ixgbe_io_error_detected,
4389 .slot_reset = ixgbe_io_slot_reset,
4390 .resume = ixgbe_io_resume,
4393 static struct pci_driver ixgbe_driver = {
4394 .name = ixgbe_driver_name,
4395 .id_table = ixgbe_pci_tbl,
4396 .probe = ixgbe_probe,
4397 .remove = __devexit_p(ixgbe_remove),
4399 .suspend = ixgbe_suspend,
4400 .resume = ixgbe_resume,
4402 .shutdown = ixgbe_shutdown,
4403 .err_handler = &ixgbe_err_handler
4407 * ixgbe_init_module - Driver Registration Routine
4409 * ixgbe_init_module is the first routine called when the driver is
4410 * loaded. All it does is register with the PCI subsystem.
4412 static int __init ixgbe_init_module(void)
4415 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4416 ixgbe_driver_string, ixgbe_driver_version);
4418 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4420 #ifdef CONFIG_IXGBE_DCA
4421 dca_register_notify(&dca_notifier);
4424 ret = pci_register_driver(&ixgbe_driver);
4428 module_init(ixgbe_init_module);
4431 * ixgbe_exit_module - Driver Exit Cleanup Routine
4433 * ixgbe_exit_module is called just before the driver is removed
4436 static void __exit ixgbe_exit_module(void)
4438 #ifdef CONFIG_IXGBE_DCA
4439 dca_unregister_notify(&dca_notifier);
4441 pci_unregister_driver(&ixgbe_driver);
4444 #ifdef CONFIG_IXGBE_DCA
4445 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4450 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4451 __ixgbe_notify_dca);
4453 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4455 #endif /* CONFIG_IXGBE_DCA */
4457 module_exit(ixgbe_exit_module);