1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
48 #include "ixgbe_sriov.h"
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
54 #define DRV_VERSION "2.0.62-k2"
55 const char ixgbe_driver_version[] = DRV_VERSION;
56 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58 static const struct ixgbe_info *ixgbe_info_tbl[] = {
59 [board_82598] = &ixgbe_82598_info,
60 [board_82599] = &ixgbe_82599_info,
63 /* ixgbe_pci_tbl - PCI Device ID Table
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
71 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
113 /* required last entry */
116 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118 #ifdef CONFIG_IXGBE_DCA
119 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
121 static struct notifier_block dca_notifier = {
122 .notifier_call = ixgbe_notify_dca,
128 #ifdef CONFIG_PCI_IOV
129 static unsigned int max_vfs;
130 module_param(max_vfs, uint, 0);
131 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132 "per physical function");
133 #endif /* CONFIG_PCI_IOV */
135 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137 MODULE_LICENSE("GPL");
138 MODULE_VERSION(DRV_VERSION);
140 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
142 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144 struct ixgbe_hw *hw = &adapter->hw;
149 #ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter->pdev);
154 /* turn off device IOV mode */
155 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162 /* set default pool back to 0 */
163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167 /* take a breather then clean up driver data */
170 kfree(adapter->vfinfo);
171 adapter->vfinfo = NULL;
173 adapter->num_vfs = 0;
174 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
177 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
181 /* Let firmware take over control of h/w */
182 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
184 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
187 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
191 /* Let firmware know the driver has taken over */
192 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
194 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
205 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206 u8 queue, u8 msix_vector)
209 struct ixgbe_hw *hw = &adapter->hw;
210 switch (hw->mac.type) {
211 case ixgbe_mac_82598EB:
212 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
215 index = (((direction * 64) + queue) >> 2) & 0x1F;
216 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218 ivar |= (msix_vector << (8 * (queue & 0x3)));
219 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
221 case ixgbe_mac_82599EB:
222 if (direction == -1) {
224 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225 index = ((queue & 1) * 8);
226 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227 ivar &= ~(0xFF << index);
228 ivar |= (msix_vector << index);
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
232 /* tx or rx causes */
233 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234 index = ((16 * (queue & 1)) + (8 * direction));
235 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236 ivar &= ~(0xFF << index);
237 ivar |= (msix_vector << index);
238 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
246 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
251 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
255 mask = (qmask & 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257 mask = (qmask >> 32);
258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
262 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
263 struct ixgbe_tx_buffer
266 if (tx_buffer_info->dma) {
267 if (tx_buffer_info->mapped_as_page)
268 pci_unmap_page(adapter->pdev,
270 tx_buffer_info->length,
273 pci_unmap_single(adapter->pdev,
275 tx_buffer_info->length,
277 tx_buffer_info->dma = 0;
279 if (tx_buffer_info->skb) {
280 dev_kfree_skb_any(tx_buffer_info->skb);
281 tx_buffer_info->skb = NULL;
283 tx_buffer_info->time_stamp = 0;
284 /* tx_buffer_info must be completely set up in the transmit path */
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
295 * Returns : true if paused
297 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298 struct ixgbe_ring *tx_ring)
300 u32 txoff = IXGBE_TFCS_TXOFF;
302 #ifdef CONFIG_IXGBE_DCB
303 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
305 int reg_idx = tx_ring->reg_idx;
306 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
308 switch (adapter->hw.mac.type) {
309 case ixgbe_mac_82598EB:
311 txoff = IXGBE_TFCS_TXOFF0;
313 case ixgbe_mac_82599EB:
315 txoff = IXGBE_TFCS_TXOFF;
319 if (tc == 2) /* TC2, TC3 */
320 tc += (reg_idx - 64) >> 4;
321 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322 tc += 1 + ((reg_idx - 96) >> 3);
323 } else if (dcb_i == 4) {
327 tc += (reg_idx - 64) >> 5;
328 if (tc == 2) /* TC2, TC3 */
329 tc += (reg_idx - 96) >> 4;
339 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
342 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
343 struct ixgbe_ring *tx_ring,
346 struct ixgbe_hw *hw = &adapter->hw;
348 /* Detect a transmit hang in hardware, this serializes the
349 * check with the clearing of time_stamp and movement of eop */
350 adapter->detect_tx_hung = false;
351 if (tx_ring->tx_buffer_info[eop].time_stamp &&
352 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
353 !ixgbe_tx_is_paused(adapter, tx_ring)) {
354 /* detected Tx unit hang */
355 union ixgbe_adv_tx_desc *tx_desc;
356 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
357 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
359 " TDH, TDT <%x>, <%x>\n"
360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
365 tx_ring->queue_index,
366 IXGBE_READ_REG(hw, tx_ring->head),
367 IXGBE_READ_REG(hw, tx_ring->tail),
368 tx_ring->next_to_use, eop,
369 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
376 #define IXGBE_MAX_TXD_PWR 14
377 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
379 /* Tx Descriptors needed, worst case */
380 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
385 static void ixgbe_tx_timeout(struct net_device *netdev);
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
389 * @q_vector: structure containing interrupt and ring information
390 * @tx_ring: tx ring to clean
392 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
393 struct ixgbe_ring *tx_ring)
395 struct ixgbe_adapter *adapter = q_vector->adapter;
396 struct net_device *netdev = adapter->netdev;
397 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398 struct ixgbe_tx_buffer *tx_buffer_info;
399 unsigned int i, eop, count = 0;
400 unsigned int total_bytes = 0, total_packets = 0;
402 i = tx_ring->next_to_clean;
403 eop = tx_ring->tx_buffer_info[i].next_to_watch;
404 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
406 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
407 (count < tx_ring->work_limit)) {
408 bool cleaned = false;
409 for ( ; !cleaned; count++) {
411 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412 tx_buffer_info = &tx_ring->tx_buffer_info[i];
413 cleaned = (i == eop);
414 skb = tx_buffer_info->skb;
416 if (cleaned && skb) {
417 unsigned int segs, bytecount;
418 unsigned int hlen = skb_headlen(skb);
420 /* gso_segs is currently only valid for tcp */
421 segs = skb_shinfo(skb)->gso_segs ?: 1;
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425 && (skb->protocol == htons(ETH_P_FCOE)) &&
427 hlen = skb_transport_offset(skb) +
428 sizeof(struct fc_frame_header) +
429 sizeof(struct fcoe_crc_eof);
430 segs = DIV_ROUND_UP(skb->len - hlen,
431 skb_shinfo(skb)->gso_size);
433 #endif /* IXGBE_FCOE */
434 /* multiply data chunks by size of headers */
435 bytecount = ((segs - 1) * hlen) + skb->len;
436 total_packets += segs;
437 total_bytes += bytecount;
440 ixgbe_unmap_and_free_tx_resource(adapter,
443 tx_desc->wb.status = 0;
446 if (i == tx_ring->count)
450 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
454 tx_ring->next_to_clean = i;
456 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
457 if (unlikely(count && netif_carrier_ok(netdev) &&
458 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
463 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464 !test_bit(__IXGBE_DOWN, &adapter->state)) {
465 netif_wake_subqueue(netdev, tx_ring->queue_index);
466 ++tx_ring->restart_queue;
470 if (adapter->detect_tx_hung) {
471 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472 /* schedule immediate reset if we believe we hung */
474 "tx hang %d detected, resetting adapter\n",
475 adapter->tx_timeout_count + 1);
476 ixgbe_tx_timeout(adapter->netdev);
480 /* re-arm the interrupt */
481 if (count >= tx_ring->work_limit)
482 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
484 tx_ring->total_bytes += total_bytes;
485 tx_ring->total_packets += total_packets;
486 tx_ring->stats.packets += total_packets;
487 tx_ring->stats.bytes += total_bytes;
488 return (count < tx_ring->work_limit);
491 #ifdef CONFIG_IXGBE_DCA
492 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
493 struct ixgbe_ring *rx_ring)
497 int q = rx_ring->reg_idx;
499 if (rx_ring->cpu != cpu) {
500 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
501 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
509 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
511 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
520 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
521 struct ixgbe_ring *tx_ring)
525 int q = tx_ring->reg_idx;
526 struct ixgbe_hw *hw = &adapter->hw;
528 if (tx_ring->cpu != cpu) {
529 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
530 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
531 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
533 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
535 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
536 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
537 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
548 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
552 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
558 for (i = 0; i < adapter->num_tx_queues; i++) {
559 adapter->tx_ring[i]->cpu = -1;
560 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
562 for (i = 0; i < adapter->num_rx_queues; i++) {
563 adapter->rx_ring[i]->cpu = -1;
564 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
568 static int __ixgbe_notify_dca(struct device *dev, void *data)
570 struct net_device *netdev = dev_get_drvdata(dev);
571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
572 unsigned long event = *(unsigned long *)data;
575 case DCA_PROVIDER_ADD:
576 /* if we're already enabled, don't do it again */
577 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
579 if (dca_add_requester(dev) == 0) {
580 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
581 ixgbe_setup_dca(adapter);
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE:
586 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587 dca_remove_requester(dev);
588 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
597 #endif /* CONFIG_IXGBE_DCA */
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
606 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
607 struct sk_buff *skb, u8 status,
608 struct ixgbe_ring *ring,
609 union ixgbe_adv_rx_desc *rx_desc)
611 struct ixgbe_adapter *adapter = q_vector->adapter;
612 struct napi_struct *napi = &q_vector->napi;
613 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
616 skb_record_rx_queue(skb, ring->queue_index);
617 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
618 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
619 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
621 napi_gro_receive(napi, skb);
623 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
624 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
636 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
637 union ixgbe_adv_rx_desc *rx_desc,
640 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
642 skb->ip_summed = CHECKSUM_NONE;
644 /* Rx csum disabled */
645 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
648 /* if IP and error */
649 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650 (status_err & IXGBE_RXDADV_ERR_IPE)) {
651 adapter->hw_csum_rx_error++;
655 if (!(status_err & IXGBE_RXD_STAT_L4CS))
658 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
659 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
665 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666 (adapter->hw.mac.type == ixgbe_mac_82599EB))
669 adapter->hw_csum_rx_error++;
673 /* It must be a TCP or UDP packet with a valid checksum */
674 skb->ip_summed = CHECKSUM_UNNECESSARY;
677 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678 struct ixgbe_ring *rx_ring, u32 val)
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
687 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
694 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
695 struct ixgbe_ring *rx_ring,
698 struct pci_dev *pdev = adapter->pdev;
699 union ixgbe_adv_rx_desc *rx_desc;
700 struct ixgbe_rx_buffer *bi;
703 i = rx_ring->next_to_use;
704 bi = &rx_ring->rx_buffer_info[i];
706 while (cleaned_count--) {
707 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
710 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
712 bi->page = alloc_page(GFP_ATOMIC);
714 adapter->alloc_rx_page_failed++;
719 /* use a half page if we're re-using */
720 bi->page_offset ^= (PAGE_SIZE / 2);
723 bi->page_dma = pci_map_page(pdev, bi->page,
731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733 skb = netdev_alloc_skb(adapter->netdev, bufsz);
736 adapter->alloc_rx_buff_failed++;
740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
745 bi->dma = pci_map_single(pdev, skb->data,
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
751 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
752 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
755 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
759 if (i == rx_ring->count)
761 bi = &rx_ring->rx_buffer_info[i];
765 if (rx_ring->next_to_use != i) {
766 rx_ring->next_to_use = i;
768 i = (rx_ring->count - 1);
770 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
774 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
776 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
779 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
781 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
784 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
786 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787 IXGBE_RXDADV_RSCCNT_MASK) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT;
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
794 * @count: pointer to number of packets coalesced in this context
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
800 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
803 unsigned int frag_list_size = 0;
806 struct sk_buff *prev = skb->prev;
807 frag_list_size += skb->len;
813 skb_shinfo(skb)->frag_list = skb->next;
815 skb->len += frag_list_size;
816 skb->data_len += frag_list_size;
817 skb->truesize += frag_list_size;
821 struct ixgbe_rsc_cb {
825 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
827 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
828 struct ixgbe_ring *rx_ring,
829 int *work_done, int work_to_do)
831 struct ixgbe_adapter *adapter = q_vector->adapter;
832 struct net_device *netdev = adapter->netdev;
833 struct pci_dev *pdev = adapter->pdev;
834 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
835 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
837 unsigned int i, rsc_count = 0;
840 bool cleaned = false;
841 int cleaned_count = 0;
842 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
845 #endif /* IXGBE_FCOE */
847 i = rx_ring->next_to_clean;
848 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
849 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
850 rx_buffer_info = &rx_ring->rx_buffer_info[i];
852 while (staterr & IXGBE_RXD_STAT_DD) {
854 if (*work_done >= work_to_do)
858 rmb(); /* read descriptor and rx_buffer_info after status DD */
859 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
860 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
861 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
862 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
863 if (len > IXGBE_RX_HDR_SIZE)
864 len = IXGBE_RX_HDR_SIZE;
865 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
867 len = le16_to_cpu(rx_desc->wb.upper.length);
871 skb = rx_buffer_info->skb;
873 rx_buffer_info->skb = NULL;
875 if (rx_buffer_info->dma) {
876 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
877 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
880 * When HWRSC is enabled, delay unmapping
881 * of the first packet. It carries the
882 * header information, HW may still
883 * access the header after the writeback.
884 * Only unmap it when EOP is reached
886 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
888 pci_unmap_single(pdev, rx_buffer_info->dma,
891 rx_buffer_info->dma = 0;
896 pci_unmap_page(pdev, rx_buffer_info->page_dma,
897 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
898 rx_buffer_info->page_dma = 0;
899 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
900 rx_buffer_info->page,
901 rx_buffer_info->page_offset,
904 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
905 (page_count(rx_buffer_info->page) != 1))
906 rx_buffer_info->page = NULL;
908 get_page(rx_buffer_info->page);
910 skb->len += upper_len;
911 skb->data_len += upper_len;
912 skb->truesize += upper_len;
916 if (i == rx_ring->count)
919 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
923 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
924 rsc_count = ixgbe_get_rsc_count(rx_desc);
927 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
928 IXGBE_RXDADV_NEXTP_SHIFT;
929 next_buffer = &rx_ring->rx_buffer_info[nextp];
931 next_buffer = &rx_ring->rx_buffer_info[i];
934 if (staterr & IXGBE_RXD_STAT_EOP) {
936 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
937 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
938 if (IXGBE_RSC_CB(skb)->dma) {
939 pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
942 IXGBE_RSC_CB(skb)->dma = 0;
944 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
945 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
947 rx_ring->rsc_count++;
948 rx_ring->rsc_flush++;
950 rx_ring->stats.packets++;
951 rx_ring->stats.bytes += skb->len;
953 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
954 rx_buffer_info->skb = next_buffer->skb;
955 rx_buffer_info->dma = next_buffer->dma;
956 next_buffer->skb = skb;
957 next_buffer->dma = 0;
959 skb->next = next_buffer->skb;
960 skb->next->prev = skb;
962 rx_ring->non_eop_descs++;
966 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
967 dev_kfree_skb_irq(skb);
971 ixgbe_rx_checksum(adapter, rx_desc, skb);
973 /* probably a little skewed due to removing CRC */
974 total_rx_bytes += skb->len;
977 skb->protocol = eth_type_trans(skb, adapter->netdev);
979 /* if ddp, not passing to ULD unless for FCP_RSP or error */
980 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
981 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
985 #endif /* IXGBE_FCOE */
986 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
989 rx_desc->wb.upper.status_error = 0;
991 /* return some buffers to hardware, one at a time is too slow */
992 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
993 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
997 /* use prefetched values */
999 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1001 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1004 rx_ring->next_to_clean = i;
1005 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1008 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1011 /* include DDPed FCoE data */
1012 if (ddp_bytes > 0) {
1015 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1016 sizeof(struct fc_frame_header) -
1017 sizeof(struct fcoe_crc_eof);
1020 total_rx_bytes += ddp_bytes;
1021 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1023 #endif /* IXGBE_FCOE */
1025 rx_ring->total_packets += total_rx_packets;
1026 rx_ring->total_bytes += total_rx_bytes;
1027 netdev->stats.rx_bytes += total_rx_bytes;
1028 netdev->stats.rx_packets += total_rx_packets;
1033 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1035 * ixgbe_configure_msix - Configure MSI-X hardware
1036 * @adapter: board private structure
1038 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1041 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1043 struct ixgbe_q_vector *q_vector;
1044 int i, j, q_vectors, v_idx, r_idx;
1047 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1050 * Populate the IVAR table and set the ITR values to the
1051 * corresponding register.
1053 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1054 q_vector = adapter->q_vector[v_idx];
1055 /* XXX for_each_set_bit(...) */
1056 r_idx = find_first_bit(q_vector->rxr_idx,
1057 adapter->num_rx_queues);
1059 for (i = 0; i < q_vector->rxr_count; i++) {
1060 j = adapter->rx_ring[r_idx]->reg_idx;
1061 ixgbe_set_ivar(adapter, 0, j, v_idx);
1062 r_idx = find_next_bit(q_vector->rxr_idx,
1063 adapter->num_rx_queues,
1066 r_idx = find_first_bit(q_vector->txr_idx,
1067 adapter->num_tx_queues);
1069 for (i = 0; i < q_vector->txr_count; i++) {
1070 j = adapter->tx_ring[r_idx]->reg_idx;
1071 ixgbe_set_ivar(adapter, 1, j, v_idx);
1072 r_idx = find_next_bit(q_vector->txr_idx,
1073 adapter->num_tx_queues,
1077 if (q_vector->txr_count && !q_vector->rxr_count)
1079 q_vector->eitr = adapter->tx_eitr_param;
1080 else if (q_vector->rxr_count)
1082 q_vector->eitr = adapter->rx_eitr_param;
1084 ixgbe_write_eitr(q_vector);
1087 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1088 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1090 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1091 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1092 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1094 /* set up to autoclear timer, and the vectors */
1095 mask = IXGBE_EIMS_ENABLE_MASK;
1096 if (adapter->num_vfs)
1097 mask &= ~(IXGBE_EIMS_OTHER |
1098 IXGBE_EIMS_MAILBOX |
1101 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1102 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1105 enum latency_range {
1109 latency_invalid = 255
1113 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1114 * @adapter: pointer to adapter
1115 * @eitr: eitr setting (ints per sec) to give last timeslice
1116 * @itr_setting: current throttle rate in ints/second
1117 * @packets: the number of packets during this measurement interval
1118 * @bytes: the number of bytes during this measurement interval
1120 * Stores a new ITR value based on packets and byte
1121 * counts during the last interrupt. The advantage of per interrupt
1122 * computation is faster updates and more accurate ITR for the current
1123 * traffic pattern. Constants in this function were computed
1124 * based on theoretical maximum wire speed and thresholds were set based
1125 * on testing data as well as attempting to minimize response time
1126 * while increasing bulk throughput.
1127 * this functionality is controlled by the InterruptThrottleRate module
1128 * parameter (see ixgbe_param.c)
1130 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1131 u32 eitr, u8 itr_setting,
1132 int packets, int bytes)
1134 unsigned int retval = itr_setting;
1139 goto update_itr_done;
1142 /* simple throttlerate management
1143 * 0-20MB/s lowest (100000 ints/s)
1144 * 20-100MB/s low (20000 ints/s)
1145 * 100-1249MB/s bulk (8000 ints/s)
1147 /* what was last interrupt timeslice? */
1148 timepassed_us = 1000000/eitr;
1149 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1151 switch (itr_setting) {
1152 case lowest_latency:
1153 if (bytes_perint > adapter->eitr_low)
1154 retval = low_latency;
1157 if (bytes_perint > adapter->eitr_high)
1158 retval = bulk_latency;
1159 else if (bytes_perint <= adapter->eitr_low)
1160 retval = lowest_latency;
1163 if (bytes_perint <= adapter->eitr_high)
1164 retval = low_latency;
1173 * ixgbe_write_eitr - write EITR register in hardware specific way
1174 * @q_vector: structure containing interrupt and ring information
1176 * This function is made to be called by ethtool and by the driver
1177 * when it needs to update EITR registers at runtime. Hardware
1178 * specific quirks/differences are taken care of here.
1180 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1182 struct ixgbe_adapter *adapter = q_vector->adapter;
1183 struct ixgbe_hw *hw = &adapter->hw;
1184 int v_idx = q_vector->v_idx;
1185 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1187 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1188 /* must write high and low 16 bits to reset counter */
1189 itr_reg |= (itr_reg << 16);
1190 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1192 * set the WDIS bit to not clear the timer bits and cause an
1193 * immediate assertion of the interrupt
1195 itr_reg |= IXGBE_EITR_CNT_WDIS;
1197 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1200 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1202 struct ixgbe_adapter *adapter = q_vector->adapter;
1204 u8 current_itr, ret_itr;
1206 struct ixgbe_ring *rx_ring, *tx_ring;
1208 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1209 for (i = 0; i < q_vector->txr_count; i++) {
1210 tx_ring = adapter->tx_ring[r_idx];
1211 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1213 tx_ring->total_packets,
1214 tx_ring->total_bytes);
1215 /* if the result for this queue would decrease interrupt
1216 * rate for this vector then use that result */
1217 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1218 q_vector->tx_itr - 1 : ret_itr);
1219 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1223 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1224 for (i = 0; i < q_vector->rxr_count; i++) {
1225 rx_ring = adapter->rx_ring[r_idx];
1226 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1228 rx_ring->total_packets,
1229 rx_ring->total_bytes);
1230 /* if the result for this queue would decrease interrupt
1231 * rate for this vector then use that result */
1232 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1233 q_vector->rx_itr - 1 : ret_itr);
1234 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1238 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1240 switch (current_itr) {
1241 /* counts and packets in update_itr are dependent on these numbers */
1242 case lowest_latency:
1246 new_itr = 20000; /* aka hwitr = ~200 */
1254 if (new_itr != q_vector->eitr) {
1255 /* do an exponential smoothing */
1256 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1258 /* save the algorithm value here, not the smoothed one */
1259 q_vector->eitr = new_itr;
1261 ixgbe_write_eitr(q_vector);
1267 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1269 struct ixgbe_hw *hw = &adapter->hw;
1271 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1272 (eicr & IXGBE_EICR_GPI_SDP1)) {
1273 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1274 /* write to clear the interrupt */
1275 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1279 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1281 struct ixgbe_hw *hw = &adapter->hw;
1283 if (eicr & IXGBE_EICR_GPI_SDP1) {
1284 /* Clear the interrupt */
1285 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1286 schedule_work(&adapter->multispeed_fiber_task);
1287 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1288 /* Clear the interrupt */
1289 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1290 schedule_work(&adapter->sfp_config_module_task);
1292 /* Interrupt isn't for us... */
1297 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1299 struct ixgbe_hw *hw = &adapter->hw;
1302 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1303 adapter->link_check_timeout = jiffies;
1304 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1305 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1306 IXGBE_WRITE_FLUSH(hw);
1307 schedule_work(&adapter->watchdog_task);
1311 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1313 struct net_device *netdev = data;
1314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1315 struct ixgbe_hw *hw = &adapter->hw;
1319 * Workaround for Silicon errata. Use clear-by-write instead
1320 * of clear-by-read. Reading with EICS will return the
1321 * interrupt causes without clearing, which later be done
1322 * with the write to EICR.
1324 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1325 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1327 if (eicr & IXGBE_EICR_LSC)
1328 ixgbe_check_lsc(adapter);
1330 if (eicr & IXGBE_EICR_MAILBOX)
1331 ixgbe_msg_task(adapter);
1333 if (hw->mac.type == ixgbe_mac_82598EB)
1334 ixgbe_check_fan_failure(adapter, eicr);
1336 if (hw->mac.type == ixgbe_mac_82599EB) {
1337 ixgbe_check_sfp_event(adapter, eicr);
1339 /* Handle Flow Director Full threshold interrupt */
1340 if (eicr & IXGBE_EICR_FLOW_DIR) {
1342 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1343 /* Disable transmits before FDIR Re-initialization */
1344 netif_tx_stop_all_queues(netdev);
1345 for (i = 0; i < adapter->num_tx_queues; i++) {
1346 struct ixgbe_ring *tx_ring =
1347 adapter->tx_ring[i];
1348 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1349 &tx_ring->reinit_state))
1350 schedule_work(&adapter->fdir_reinit_task);
1354 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1355 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1360 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1365 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1366 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1369 mask = (qmask & 0xFFFFFFFF);
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1371 mask = (qmask >> 32);
1372 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1374 /* skip the flush */
1377 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1382 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1383 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1386 mask = (qmask & 0xFFFFFFFF);
1387 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1388 mask = (qmask >> 32);
1389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1391 /* skip the flush */
1394 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1396 struct ixgbe_q_vector *q_vector = data;
1397 struct ixgbe_adapter *adapter = q_vector->adapter;
1398 struct ixgbe_ring *tx_ring;
1401 if (!q_vector->txr_count)
1404 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1405 for (i = 0; i < q_vector->txr_count; i++) {
1406 tx_ring = adapter->tx_ring[r_idx];
1407 tx_ring->total_bytes = 0;
1408 tx_ring->total_packets = 0;
1409 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1413 /* EIAM disabled interrupts (on this vector) for us */
1414 napi_schedule(&q_vector->napi);
1420 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1422 * @data: pointer to our q_vector struct for this interrupt vector
1424 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1426 struct ixgbe_q_vector *q_vector = data;
1427 struct ixgbe_adapter *adapter = q_vector->adapter;
1428 struct ixgbe_ring *rx_ring;
1432 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1433 for (i = 0; i < q_vector->rxr_count; i++) {
1434 rx_ring = adapter->rx_ring[r_idx];
1435 rx_ring->total_bytes = 0;
1436 rx_ring->total_packets = 0;
1437 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1441 if (!q_vector->rxr_count)
1444 /* disable interrupts on this vector only */
1445 /* EIAM disabled interrupts (on this vector) for us */
1446 napi_schedule(&q_vector->napi);
1451 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1453 struct ixgbe_q_vector *q_vector = data;
1454 struct ixgbe_adapter *adapter = q_vector->adapter;
1455 struct ixgbe_ring *ring;
1459 if (!q_vector->txr_count && !q_vector->rxr_count)
1462 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1463 for (i = 0; i < q_vector->txr_count; i++) {
1464 ring = adapter->tx_ring[r_idx];
1465 ring->total_bytes = 0;
1466 ring->total_packets = 0;
1467 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1471 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1472 for (i = 0; i < q_vector->rxr_count; i++) {
1473 ring = adapter->rx_ring[r_idx];
1474 ring->total_bytes = 0;
1475 ring->total_packets = 0;
1476 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1480 /* EIAM disabled interrupts (on this vector) for us */
1481 napi_schedule(&q_vector->napi);
1487 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1488 * @napi: napi struct with our devices info in it
1489 * @budget: amount of work driver is allowed to do this pass, in packets
1491 * This function is optimized for cleaning one queue only on a single
1494 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1496 struct ixgbe_q_vector *q_vector =
1497 container_of(napi, struct ixgbe_q_vector, napi);
1498 struct ixgbe_adapter *adapter = q_vector->adapter;
1499 struct ixgbe_ring *rx_ring = NULL;
1503 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1504 rx_ring = adapter->rx_ring[r_idx];
1505 #ifdef CONFIG_IXGBE_DCA
1506 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1507 ixgbe_update_rx_dca(adapter, rx_ring);
1510 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1512 /* If all Rx work done, exit the polling mode */
1513 if (work_done < budget) {
1514 napi_complete(napi);
1515 if (adapter->rx_itr_setting & 1)
1516 ixgbe_set_itr_msix(q_vector);
1517 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1518 ixgbe_irq_enable_queues(adapter,
1519 ((u64)1 << q_vector->v_idx));
1526 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1527 * @napi: napi struct with our devices info in it
1528 * @budget: amount of work driver is allowed to do this pass, in packets
1530 * This function will clean more than one rx queue associated with a
1533 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1535 struct ixgbe_q_vector *q_vector =
1536 container_of(napi, struct ixgbe_q_vector, napi);
1537 struct ixgbe_adapter *adapter = q_vector->adapter;
1538 struct ixgbe_ring *ring = NULL;
1539 int work_done = 0, i;
1541 bool tx_clean_complete = true;
1543 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1544 for (i = 0; i < q_vector->txr_count; i++) {
1545 ring = adapter->tx_ring[r_idx];
1546 #ifdef CONFIG_IXGBE_DCA
1547 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1548 ixgbe_update_tx_dca(adapter, ring);
1550 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1551 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1555 /* attempt to distribute budget to each queue fairly, but don't allow
1556 * the budget to go below 1 because we'll exit polling */
1557 budget /= (q_vector->rxr_count ?: 1);
1558 budget = max(budget, 1);
1559 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1560 for (i = 0; i < q_vector->rxr_count; i++) {
1561 ring = adapter->rx_ring[r_idx];
1562 #ifdef CONFIG_IXGBE_DCA
1563 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1564 ixgbe_update_rx_dca(adapter, ring);
1566 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1567 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1571 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1572 ring = adapter->rx_ring[r_idx];
1573 /* If all Rx work done, exit the polling mode */
1574 if (work_done < budget) {
1575 napi_complete(napi);
1576 if (adapter->rx_itr_setting & 1)
1577 ixgbe_set_itr_msix(q_vector);
1578 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1579 ixgbe_irq_enable_queues(adapter,
1580 ((u64)1 << q_vector->v_idx));
1588 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1589 * @napi: napi struct with our devices info in it
1590 * @budget: amount of work driver is allowed to do this pass, in packets
1592 * This function is optimized for cleaning one queue only on a single
1595 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1597 struct ixgbe_q_vector *q_vector =
1598 container_of(napi, struct ixgbe_q_vector, napi);
1599 struct ixgbe_adapter *adapter = q_vector->adapter;
1600 struct ixgbe_ring *tx_ring = NULL;
1604 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1605 tx_ring = adapter->tx_ring[r_idx];
1606 #ifdef CONFIG_IXGBE_DCA
1607 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1608 ixgbe_update_tx_dca(adapter, tx_ring);
1611 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1614 /* If all Tx work done, exit the polling mode */
1615 if (work_done < budget) {
1616 napi_complete(napi);
1617 if (adapter->tx_itr_setting & 1)
1618 ixgbe_set_itr_msix(q_vector);
1619 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1620 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1626 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1629 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1631 set_bit(r_idx, q_vector->rxr_idx);
1632 q_vector->rxr_count++;
1635 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1638 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1640 set_bit(t_idx, q_vector->txr_idx);
1641 q_vector->txr_count++;
1645 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1646 * @adapter: board private structure to initialize
1647 * @vectors: allotted vector count for descriptor rings
1649 * This function maps descriptor rings to the queue-specific vectors
1650 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1651 * one vector per ring/queue, but on a constrained vector budget, we
1652 * group the rings as "efficiently" as possible. You would add new
1653 * mapping configurations in here.
1655 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1659 int rxr_idx = 0, txr_idx = 0;
1660 int rxr_remaining = adapter->num_rx_queues;
1661 int txr_remaining = adapter->num_tx_queues;
1666 /* No mapping required if MSI-X is disabled. */
1667 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1671 * The ideal configuration...
1672 * We have enough vectors to map one per queue.
1674 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1675 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1676 map_vector_to_rxq(adapter, v_start, rxr_idx);
1678 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1679 map_vector_to_txq(adapter, v_start, txr_idx);
1685 * If we don't have enough vectors for a 1-to-1
1686 * mapping, we'll have to group them so there are
1687 * multiple queues per vector.
1689 /* Re-adjusting *qpv takes care of the remainder. */
1690 for (i = v_start; i < vectors; i++) {
1691 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1692 for (j = 0; j < rqpv; j++) {
1693 map_vector_to_rxq(adapter, i, rxr_idx);
1698 for (i = v_start; i < vectors; i++) {
1699 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1700 for (j = 0; j < tqpv; j++) {
1701 map_vector_to_txq(adapter, i, txr_idx);
1712 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1713 * @adapter: board private structure
1715 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1716 * interrupts from the kernel.
1718 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1720 struct net_device *netdev = adapter->netdev;
1721 irqreturn_t (*handler)(int, void *);
1722 int i, vector, q_vectors, err;
1725 /* Decrement for Other and TCP Timer vectors */
1726 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1728 /* Map the Tx/Rx rings to the vectors we were allotted. */
1729 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1733 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1734 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1735 &ixgbe_msix_clean_many)
1736 for (vector = 0; vector < q_vectors; vector++) {
1737 handler = SET_HANDLER(adapter->q_vector[vector]);
1739 if(handler == &ixgbe_msix_clean_rx) {
1740 sprintf(adapter->name[vector], "%s-%s-%d",
1741 netdev->name, "rx", ri++);
1743 else if(handler == &ixgbe_msix_clean_tx) {
1744 sprintf(adapter->name[vector], "%s-%s-%d",
1745 netdev->name, "tx", ti++);
1748 sprintf(adapter->name[vector], "%s-%s-%d",
1749 netdev->name, "TxRx", vector);
1751 err = request_irq(adapter->msix_entries[vector].vector,
1752 handler, 0, adapter->name[vector],
1753 adapter->q_vector[vector]);
1756 "request_irq failed for MSIX interrupt "
1757 "Error: %d\n", err);
1758 goto free_queue_irqs;
1762 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1763 err = request_irq(adapter->msix_entries[vector].vector,
1764 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1767 "request_irq for msix_lsc failed: %d\n", err);
1768 goto free_queue_irqs;
1774 for (i = vector - 1; i >= 0; i--)
1775 free_irq(adapter->msix_entries[--vector].vector,
1776 adapter->q_vector[i]);
1777 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1778 pci_disable_msix(adapter->pdev);
1779 kfree(adapter->msix_entries);
1780 adapter->msix_entries = NULL;
1785 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1787 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1789 u32 new_itr = q_vector->eitr;
1790 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1791 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1793 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1795 tx_ring->total_packets,
1796 tx_ring->total_bytes);
1797 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1799 rx_ring->total_packets,
1800 rx_ring->total_bytes);
1802 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1804 switch (current_itr) {
1805 /* counts and packets in update_itr are dependent on these numbers */
1806 case lowest_latency:
1810 new_itr = 20000; /* aka hwitr = ~200 */
1819 if (new_itr != q_vector->eitr) {
1820 /* do an exponential smoothing */
1821 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1823 /* save the algorithm value here, not the smoothed one */
1824 q_vector->eitr = new_itr;
1826 ixgbe_write_eitr(q_vector);
1833 * ixgbe_irq_enable - Enable default interrupt generation settings
1834 * @adapter: board private structure
1836 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1840 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1841 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1842 mask |= IXGBE_EIMS_GPI_SDP1;
1843 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1844 mask |= IXGBE_EIMS_ECC;
1845 mask |= IXGBE_EIMS_GPI_SDP1;
1846 mask |= IXGBE_EIMS_GPI_SDP2;
1847 if (adapter->num_vfs)
1848 mask |= IXGBE_EIMS_MAILBOX;
1850 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1851 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1852 mask |= IXGBE_EIMS_FLOW_DIR;
1854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1855 ixgbe_irq_enable_queues(adapter, ~0);
1856 IXGBE_WRITE_FLUSH(&adapter->hw);
1858 if (adapter->num_vfs > 32) {
1859 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1865 * ixgbe_intr - legacy mode Interrupt Handler
1866 * @irq: interrupt number
1867 * @data: pointer to a network interface device structure
1869 static irqreturn_t ixgbe_intr(int irq, void *data)
1871 struct net_device *netdev = data;
1872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1873 struct ixgbe_hw *hw = &adapter->hw;
1874 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1878 * Workaround for silicon errata. Mask the interrupts
1879 * before the read of EICR.
1881 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1883 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1884 * therefore no explict interrupt disable is necessary */
1885 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1887 /* shared interrupt alert!
1888 * make sure interrupts are enabled because the read will
1889 * have disabled interrupts due to EIAM */
1890 ixgbe_irq_enable(adapter);
1891 return IRQ_NONE; /* Not our interrupt */
1894 if (eicr & IXGBE_EICR_LSC)
1895 ixgbe_check_lsc(adapter);
1897 if (hw->mac.type == ixgbe_mac_82599EB)
1898 ixgbe_check_sfp_event(adapter, eicr);
1900 ixgbe_check_fan_failure(adapter, eicr);
1902 if (napi_schedule_prep(&(q_vector->napi))) {
1903 adapter->tx_ring[0]->total_packets = 0;
1904 adapter->tx_ring[0]->total_bytes = 0;
1905 adapter->rx_ring[0]->total_packets = 0;
1906 adapter->rx_ring[0]->total_bytes = 0;
1907 /* would disable interrupts here but EIAM disabled it */
1908 __napi_schedule(&(q_vector->napi));
1914 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1916 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1918 for (i = 0; i < q_vectors; i++) {
1919 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1920 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1921 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1922 q_vector->rxr_count = 0;
1923 q_vector->txr_count = 0;
1928 * ixgbe_request_irq - initialize interrupts
1929 * @adapter: board private structure
1931 * Attempts to configure interrupts using the best available
1932 * capabilities of the hardware and kernel.
1934 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1936 struct net_device *netdev = adapter->netdev;
1939 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1940 err = ixgbe_request_msix_irqs(adapter);
1941 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1942 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1943 netdev->name, netdev);
1945 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1946 netdev->name, netdev);
1950 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1955 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1957 struct net_device *netdev = adapter->netdev;
1959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1962 q_vectors = adapter->num_msix_vectors;
1965 free_irq(adapter->msix_entries[i].vector, netdev);
1968 for (; i >= 0; i--) {
1969 free_irq(adapter->msix_entries[i].vector,
1970 adapter->q_vector[i]);
1973 ixgbe_reset_q_vectors(adapter);
1975 free_irq(adapter->pdev->irq, netdev);
1980 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1981 * @adapter: board private structure
1983 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1985 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1986 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1988 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1989 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1991 if (adapter->num_vfs > 32)
1992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
1994 IXGBE_WRITE_FLUSH(&adapter->hw);
1995 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1997 for (i = 0; i < adapter->num_msix_vectors; i++)
1998 synchronize_irq(adapter->msix_entries[i].vector);
2000 synchronize_irq(adapter->pdev->irq);
2005 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2008 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2010 struct ixgbe_hw *hw = &adapter->hw;
2012 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2013 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2015 ixgbe_set_ivar(adapter, 0, 0, 0);
2016 ixgbe_set_ivar(adapter, 1, 0, 0);
2018 map_vector_to_rxq(adapter, 0, 0);
2019 map_vector_to_txq(adapter, 0, 0);
2021 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2025 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2026 * @adapter: board private structure
2028 * Configure the Tx unit of the MAC after a reset.
2030 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2033 struct ixgbe_hw *hw = &adapter->hw;
2034 u32 i, j, tdlen, txctrl;
2036 /* Setup the HW Tx Head and Tail descriptor pointers */
2037 for (i = 0; i < adapter->num_tx_queues; i++) {
2038 struct ixgbe_ring *ring = adapter->tx_ring[i];
2041 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2042 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2043 (tdba & DMA_BIT_MASK(32)));
2044 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2045 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2046 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2047 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2048 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2049 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2051 * Disable Tx Head Writeback RO bit, since this hoses
2052 * bookkeeping if things aren't delivered in order.
2054 switch (hw->mac.type) {
2055 case ixgbe_mac_82598EB:
2056 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2058 case ixgbe_mac_82599EB:
2060 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2063 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2064 switch (hw->mac.type) {
2065 case ixgbe_mac_82598EB:
2066 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2068 case ixgbe_mac_82599EB:
2070 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2075 if (hw->mac.type == ixgbe_mac_82599EB) {
2079 /* disable the arbiter while setting MTQC */
2080 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2081 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2082 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2084 /* set transmit pool layout */
2085 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2086 switch (adapter->flags & mask) {
2088 case (IXGBE_FLAG_SRIOV_ENABLED):
2089 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2090 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2093 case (IXGBE_FLAG_DCB_ENABLED):
2094 /* We enable 8 traffic classes, DCB only */
2095 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2096 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2100 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2104 /* re-eable the arbiter */
2105 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2106 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2110 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2112 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2113 struct ixgbe_ring *rx_ring)
2117 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2119 index = rx_ring->reg_idx;
2120 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2122 mask = (unsigned long) feature[RING_F_RSS].mask;
2123 index = index & mask;
2125 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2127 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2128 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2130 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2131 IXGBE_SRRCTL_BSIZEHDR_MASK;
2133 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2134 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2135 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2137 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2139 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2141 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2142 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2143 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2146 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2149 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2154 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2157 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2158 #ifdef CONFIG_IXGBE_DCB
2159 | IXGBE_FLAG_DCB_ENABLED
2161 | IXGBE_FLAG_SRIOV_ENABLED
2165 case (IXGBE_FLAG_RSS_ENABLED):
2166 mrqc = IXGBE_MRQC_RSSEN;
2168 case (IXGBE_FLAG_SRIOV_ENABLED):
2169 mrqc = IXGBE_MRQC_VMDQEN;
2171 #ifdef CONFIG_IXGBE_DCB
2172 case (IXGBE_FLAG_DCB_ENABLED):
2173 mrqc = IXGBE_MRQC_RT8TCEN;
2175 #endif /* CONFIG_IXGBE_DCB */
2184 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2185 * @adapter: address of board private structure
2186 * @index: index of ring to set
2188 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2190 struct ixgbe_ring *rx_ring;
2191 struct ixgbe_hw *hw = &adapter->hw;
2196 rx_ring = adapter->rx_ring[index];
2197 j = rx_ring->reg_idx;
2198 rx_buf_len = rx_ring->rx_buf_len;
2199 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2200 rscctrl |= IXGBE_RSCCTL_RSCEN;
2202 * we must limit the number of descriptors so that the
2203 * total size of max desc * buf_len is not greater
2206 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2207 #if (MAX_SKB_FRAGS > 16)
2208 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2209 #elif (MAX_SKB_FRAGS > 8)
2210 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2211 #elif (MAX_SKB_FRAGS > 4)
2212 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2214 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2217 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2218 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2219 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2220 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2222 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2224 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2228 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2229 * @adapter: board private structure
2231 * Configure the Rx unit of the MAC after a reset.
2233 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2236 struct ixgbe_hw *hw = &adapter->hw;
2237 struct ixgbe_ring *rx_ring;
2238 struct net_device *netdev = adapter->netdev;
2239 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2241 u32 rdlen, rxctrl, rxcsum;
2242 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2243 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2244 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2246 u32 reta = 0, mrqc = 0;
2250 /* Decide whether to use packet split mode or not */
2251 /* Do not use packet split if we're in SR-IOV Mode */
2252 if (!adapter->num_vfs)
2253 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2255 /* Set the RX buffer length according to the mode */
2256 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2257 rx_buf_len = IXGBE_RX_HDR_SIZE;
2258 if (hw->mac.type == ixgbe_mac_82599EB) {
2259 /* PSRTYPE must be initialized in 82599 */
2260 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2261 IXGBE_PSRTYPE_UDPHDR |
2262 IXGBE_PSRTYPE_IPV4HDR |
2263 IXGBE_PSRTYPE_IPV6HDR |
2264 IXGBE_PSRTYPE_L2HDR;
2266 IXGBE_PSRTYPE(adapter->num_vfs),
2270 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2271 (netdev->mtu <= ETH_DATA_LEN))
2272 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2274 rx_buf_len = ALIGN(max_frame, 1024);
2277 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2278 fctrl |= IXGBE_FCTRL_BAM;
2279 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2280 fctrl |= IXGBE_FCTRL_PMCF;
2281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2283 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2284 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2285 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2287 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2289 if (netdev->features & NETIF_F_FCOE_MTU)
2290 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2292 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2294 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2295 /* disable receives while setting up the descriptors */
2296 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2297 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2300 * Setup the HW Rx Head and Tail Descriptor Pointers and
2301 * the Base and Length of the Rx Descriptor Ring
2303 for (i = 0; i < adapter->num_rx_queues; i++) {
2304 rx_ring = adapter->rx_ring[i];
2305 rdba = rx_ring->dma;
2306 j = rx_ring->reg_idx;
2307 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2308 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2309 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2310 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2311 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2312 rx_ring->head = IXGBE_RDH(j);
2313 rx_ring->tail = IXGBE_RDT(j);
2314 rx_ring->rx_buf_len = rx_buf_len;
2316 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2317 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2319 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2322 if (netdev->features & NETIF_F_FCOE_MTU) {
2323 struct ixgbe_ring_feature *f;
2324 f = &adapter->ring_feature[RING_F_FCOE];
2325 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2326 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2327 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2328 rx_ring->rx_buf_len =
2329 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2333 #endif /* IXGBE_FCOE */
2334 ixgbe_configure_srrctl(adapter, rx_ring);
2337 if (hw->mac.type == ixgbe_mac_82598EB) {
2339 * For VMDq support of different descriptor types or
2340 * buffer sizes through the use of multiple SRRCTL
2341 * registers, RDRXCTL.MVMEN must be set to 1
2343 * also, the manual doesn't mention it clearly but DCA hints
2344 * will only use queue 0's tags unless this bit is set. Side
2345 * effects of setting this bit are only that SRRCTL must be
2346 * fully programmed [0..15]
2348 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2349 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2350 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2353 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2355 u32 reg_offset, vf_shift;
2356 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2357 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2358 | IXGBE_VT_CTL_REPLEN;
2359 vt_reg_bits |= (adapter->num_vfs <<
2360 IXGBE_VT_CTL_POOL_SHIFT);
2361 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2362 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2364 vf_shift = adapter->num_vfs % 32;
2365 reg_offset = adapter->num_vfs / 32;
2366 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2367 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2368 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2369 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2370 /* Enable only the PF's pool for Tx/Rx */
2371 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2372 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2373 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2374 ixgbe_set_vmolr(hw, adapter->num_vfs);
2377 /* Program MRQC for the distribution of queues */
2378 mrqc = ixgbe_setup_mrqc(adapter);
2380 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2381 /* Fill out redirection table */
2382 for (i = 0, j = 0; i < 128; i++, j++) {
2383 if (j == adapter->ring_feature[RING_F_RSS].indices)
2385 /* reta = 4-byte sliding window of
2386 * 0x00..(indices-1)(indices-1)00..etc. */
2387 reta = (reta << 8) | (j * 0x11);
2389 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2392 /* Fill out hash function seeds */
2393 for (i = 0; i < 10; i++)
2394 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2396 if (hw->mac.type == ixgbe_mac_82598EB)
2397 mrqc |= IXGBE_MRQC_RSSEN;
2398 /* Perform hash on these packet types */
2399 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2400 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2401 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2402 | IXGBE_MRQC_RSS_FIELD_IPV6
2403 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2404 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2406 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2408 if (adapter->num_vfs) {
2411 /* Map PF MAC address in RAR Entry 0 to first pool
2413 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2415 /* Set up VF register offsets for selected VT Mode, i.e.
2416 * 64 VFs for SR-IOV */
2417 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2418 reg |= IXGBE_GCR_EXT_SRIOV;
2419 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2422 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2424 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2425 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2426 /* Disable indicating checksum in descriptor, enables
2428 rxcsum |= IXGBE_RXCSUM_PCSD;
2430 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2431 /* Enable IPv4 payload checksum for UDP fragments
2432 * if PCSD is not set */
2433 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2436 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2438 if (hw->mac.type == ixgbe_mac_82599EB) {
2439 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2440 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2441 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2442 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2445 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2446 /* Enable 82599 HW-RSC */
2447 for (i = 0; i < adapter->num_rx_queues; i++)
2448 ixgbe_configure_rscctl(adapter, i);
2450 /* Disable RSC for ACK packets */
2451 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2452 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2456 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2459 struct ixgbe_hw *hw = &adapter->hw;
2460 int pool_ndx = adapter->num_vfs;
2462 /* add VID to filter table */
2463 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2466 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2469 struct ixgbe_hw *hw = &adapter->hw;
2470 int pool_ndx = adapter->num_vfs;
2472 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2473 ixgbe_irq_disable(adapter);
2475 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2477 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2478 ixgbe_irq_enable(adapter);
2480 /* remove VID from filter table */
2481 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2484 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2485 struct vlan_group *grp)
2487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2491 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2492 ixgbe_irq_disable(adapter);
2493 adapter->vlgrp = grp;
2496 * For a DCB driver, always enable VLAN tag stripping so we can
2497 * still receive traffic from a DCB-enabled host even if we're
2500 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2502 /* Disable CFI check */
2503 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2505 /* enable VLAN tag stripping */
2506 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2507 ctrl |= IXGBE_VLNCTRL_VME;
2508 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2509 for (i = 0; i < adapter->num_rx_queues; i++) {
2511 j = adapter->rx_ring[i]->reg_idx;
2512 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2513 ctrl |= IXGBE_RXDCTL_VME;
2514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2518 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2520 ixgbe_vlan_rx_add_vid(netdev, 0);
2522 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2523 ixgbe_irq_enable(adapter);
2526 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2528 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2530 if (adapter->vlgrp) {
2532 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2533 if (!vlan_group_get_device(adapter->vlgrp, vid))
2535 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2540 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2542 struct dev_mc_list *mc_ptr;
2543 u8 *addr = *mc_addr_ptr;
2546 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2548 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2550 *mc_addr_ptr = NULL;
2556 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2557 * @netdev: network interface device structure
2559 * The set_rx_method entry point is called whenever the unicast/multicast
2560 * address list or the network interface flags are updated. This routine is
2561 * responsible for configuring the hardware for proper unicast, multicast and
2564 void ixgbe_set_rx_mode(struct net_device *netdev)
2566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2567 struct ixgbe_hw *hw = &adapter->hw;
2569 u8 *addr_list = NULL;
2572 /* Check for Promiscuous and All Multicast modes */
2574 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2575 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2577 if (netdev->flags & IFF_PROMISC) {
2578 hw->addr_ctrl.user_set_promisc = 1;
2579 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2580 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2582 if (netdev->flags & IFF_ALLMULTI) {
2583 fctrl |= IXGBE_FCTRL_MPE;
2584 fctrl &= ~IXGBE_FCTRL_UPE;
2586 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2588 vlnctrl |= IXGBE_VLNCTRL_VFE;
2589 hw->addr_ctrl.user_set_promisc = 0;
2592 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2593 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2595 /* reprogram secondary unicast list */
2596 hw->mac.ops.update_uc_addr_list(hw, netdev);
2598 /* reprogram multicast list */
2599 addr_count = netdev_mc_count(netdev);
2601 addr_list = netdev->mc_list->dmi_addr;
2602 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2603 ixgbe_addr_list_itr);
2604 if (adapter->num_vfs)
2605 ixgbe_restore_vf_multicasts(adapter);
2608 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2611 struct ixgbe_q_vector *q_vector;
2612 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2614 /* legacy and MSI only use one vector */
2615 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2618 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2619 struct napi_struct *napi;
2620 q_vector = adapter->q_vector[q_idx];
2621 napi = &q_vector->napi;
2622 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2623 if (!q_vector->rxr_count || !q_vector->txr_count) {
2624 if (q_vector->txr_count == 1)
2625 napi->poll = &ixgbe_clean_txonly;
2626 else if (q_vector->rxr_count == 1)
2627 napi->poll = &ixgbe_clean_rxonly;
2635 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2638 struct ixgbe_q_vector *q_vector;
2639 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2641 /* legacy and MSI only use one vector */
2642 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2645 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2646 q_vector = adapter->q_vector[q_idx];
2647 napi_disable(&q_vector->napi);
2651 #ifdef CONFIG_IXGBE_DCB
2653 * ixgbe_configure_dcb - Configure DCB hardware
2654 * @adapter: ixgbe adapter struct
2656 * This is called by the driver on open to configure the DCB hardware.
2657 * This is also called by the gennetlink interface when reconfiguring
2660 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2662 struct ixgbe_hw *hw = &adapter->hw;
2663 u32 txdctl, vlnctrl;
2666 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2667 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2668 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2670 /* reconfigure the hardware */
2671 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2673 for (i = 0; i < adapter->num_tx_queues; i++) {
2674 j = adapter->tx_ring[i]->reg_idx;
2675 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2676 /* PThresh workaround for Tx hang with DFP enabled. */
2678 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2680 /* Enable VLAN tag insert/strip */
2681 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2682 if (hw->mac.type == ixgbe_mac_82598EB) {
2683 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2684 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2685 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2686 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2687 vlnctrl |= IXGBE_VLNCTRL_VFE;
2688 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2689 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2690 for (i = 0; i < adapter->num_rx_queues; i++) {
2691 j = adapter->rx_ring[i]->reg_idx;
2692 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2693 vlnctrl |= IXGBE_RXDCTL_VME;
2694 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2697 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2701 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2703 struct net_device *netdev = adapter->netdev;
2704 struct ixgbe_hw *hw = &adapter->hw;
2707 ixgbe_set_rx_mode(netdev);
2709 ixgbe_restore_vlan(adapter);
2710 #ifdef CONFIG_IXGBE_DCB
2711 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2712 if (hw->mac.type == ixgbe_mac_82598EB)
2713 netif_set_gso_max_size(netdev, 32768);
2715 netif_set_gso_max_size(netdev, 65536);
2716 ixgbe_configure_dcb(adapter);
2718 netif_set_gso_max_size(netdev, 65536);
2721 netif_set_gso_max_size(netdev, 65536);
2725 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2726 ixgbe_configure_fcoe(adapter);
2728 #endif /* IXGBE_FCOE */
2729 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2730 for (i = 0; i < adapter->num_tx_queues; i++)
2731 adapter->tx_ring[i]->atr_sample_rate =
2732 adapter->atr_sample_rate;
2733 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2734 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2735 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2738 ixgbe_configure_tx(adapter);
2739 ixgbe_configure_rx(adapter);
2740 for (i = 0; i < adapter->num_rx_queues; i++)
2741 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2742 (adapter->rx_ring[i]->count - 1));
2745 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2747 switch (hw->phy.type) {
2748 case ixgbe_phy_sfp_avago:
2749 case ixgbe_phy_sfp_ftl:
2750 case ixgbe_phy_sfp_intel:
2751 case ixgbe_phy_sfp_unknown:
2752 case ixgbe_phy_tw_tyco:
2753 case ixgbe_phy_tw_unknown:
2761 * ixgbe_sfp_link_config - set up SFP+ link
2762 * @adapter: pointer to private adapter struct
2764 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2766 struct ixgbe_hw *hw = &adapter->hw;
2768 if (hw->phy.multispeed_fiber) {
2770 * In multispeed fiber setups, the device may not have
2771 * had a physical connection when the driver loaded.
2772 * If that's the case, the initial link configuration
2773 * couldn't get the MAC into 10G or 1G mode, so we'll
2774 * never have a link status change interrupt fire.
2775 * We need to try and force an autonegotiation
2776 * session, then bring up link.
2778 hw->mac.ops.setup_sfp(hw);
2779 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2780 schedule_work(&adapter->multispeed_fiber_task);
2783 * Direct Attach Cu and non-multispeed fiber modules
2784 * still need to be configured properly prior to
2787 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2788 schedule_work(&adapter->sfp_config_module_task);
2793 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2794 * @hw: pointer to private hardware struct
2796 * Returns 0 on success, negative on failure
2798 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2801 bool negotiation, link_up = false;
2802 u32 ret = IXGBE_ERR_LINK_SETUP;
2804 if (hw->mac.ops.check_link)
2805 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2810 if (hw->mac.ops.get_link_capabilities)
2811 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2815 if (hw->mac.ops.setup_link)
2816 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2821 #define IXGBE_MAX_RX_DESC_POLL 10
2822 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2825 int j = adapter->rx_ring[rxr]->reg_idx;
2828 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2829 if (IXGBE_READ_REG(&adapter->hw,
2830 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2835 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2836 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2837 "not set within the polling period\n", rxr);
2839 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2840 (adapter->rx_ring[rxr]->count - 1));
2843 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2845 struct net_device *netdev = adapter->netdev;
2846 struct ixgbe_hw *hw = &adapter->hw;
2848 int num_rx_rings = adapter->num_rx_queues;
2850 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2851 u32 txdctl, rxdctl, mhadd;
2856 ixgbe_get_hw_control(adapter);
2858 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2859 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2860 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2861 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2862 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2867 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2868 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2869 gpie |= IXGBE_GPIE_VTMODE_64;
2871 /* XXX: to interrupt immediately for EICS writes, enable this */
2872 /* gpie |= IXGBE_GPIE_EIMEN; */
2873 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2876 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2878 * use EIAM to auto-mask when MSI-X interrupt is asserted
2879 * this saves a register write for every interrupt
2881 switch (hw->mac.type) {
2882 case ixgbe_mac_82598EB:
2883 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2886 case ixgbe_mac_82599EB:
2887 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2888 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2892 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2893 * specifically only auto mask tx and rx interrupts */
2894 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2897 /* Enable fan failure interrupt if media type is copper */
2898 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2899 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2900 gpie |= IXGBE_SDP1_GPIEN;
2901 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2904 if (hw->mac.type == ixgbe_mac_82599EB) {
2905 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2906 gpie |= IXGBE_SDP1_GPIEN;
2907 gpie |= IXGBE_SDP2_GPIEN;
2908 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2912 /* adjust max frame to be able to do baby jumbo for FCoE */
2913 if ((netdev->features & NETIF_F_FCOE_MTU) &&
2914 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2915 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2917 #endif /* IXGBE_FCOE */
2918 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2919 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2920 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2921 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2923 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2926 for (i = 0; i < adapter->num_tx_queues; i++) {
2927 j = adapter->tx_ring[i]->reg_idx;
2928 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2929 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2930 txdctl |= (8 << 16);
2931 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2934 if (hw->mac.type == ixgbe_mac_82599EB) {
2935 /* DMATXCTL.EN must be set after all Tx queue config is done */
2936 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2937 dmatxctl |= IXGBE_DMATXCTL_TE;
2938 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2940 for (i = 0; i < adapter->num_tx_queues; i++) {
2941 j = adapter->tx_ring[i]->reg_idx;
2942 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2943 txdctl |= IXGBE_TXDCTL_ENABLE;
2944 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2945 if (hw->mac.type == ixgbe_mac_82599EB) {
2947 /* poll for Tx Enable ready */
2950 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2951 } while (--wait_loop &&
2952 !(txdctl & IXGBE_TXDCTL_ENABLE));
2954 DPRINTK(DRV, ERR, "Could not enable "
2955 "Tx Queue %d\n", j);
2959 for (i = 0; i < num_rx_rings; i++) {
2960 j = adapter->rx_ring[i]->reg_idx;
2961 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2962 /* enable PTHRESH=32 descriptors (half the internal cache)
2963 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2964 * this also removes a pesky rx_no_buffer_count increment */
2966 rxdctl |= IXGBE_RXDCTL_ENABLE;
2967 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2968 if (hw->mac.type == ixgbe_mac_82599EB)
2969 ixgbe_rx_desc_queue_enable(adapter, i);
2971 /* enable all receives */
2972 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2973 if (hw->mac.type == ixgbe_mac_82598EB)
2974 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2976 rxdctl |= IXGBE_RXCTRL_RXEN;
2977 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2979 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2980 ixgbe_configure_msix(adapter);
2982 ixgbe_configure_msi_and_legacy(adapter);
2984 clear_bit(__IXGBE_DOWN, &adapter->state);
2985 ixgbe_napi_enable_all(adapter);
2987 /* clear any pending interrupts, may auto mask */
2988 IXGBE_READ_REG(hw, IXGBE_EICR);
2990 ixgbe_irq_enable(adapter);
2993 * If this adapter has a fan, check to see if we had a failure
2994 * before we enabled the interrupt.
2996 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2997 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2998 if (esdp & IXGBE_ESDP_SDP1)
3000 "Fan has stopped, replace the adapter\n");
3004 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3005 * arrived before interrupts were enabled but after probe. Such
3006 * devices wouldn't have their type identified yet. We need to
3007 * kick off the SFP+ module setup first, then try to bring up link.
3008 * If we're not hot-pluggable SFP+, we just need to configure link
3011 if (hw->phy.type == ixgbe_phy_unknown) {
3012 err = hw->phy.ops.identify(hw);
3013 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3015 * Take the device down and schedule the sfp tasklet
3016 * which will unregister_netdev and log it.
3018 ixgbe_down(adapter);
3019 schedule_work(&adapter->sfp_config_module_task);
3024 if (ixgbe_is_sfp(hw)) {
3025 ixgbe_sfp_link_config(adapter);
3027 err = ixgbe_non_sfp_link_config(hw);
3029 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3032 for (i = 0; i < adapter->num_tx_queues; i++)
3033 set_bit(__IXGBE_FDIR_INIT_DONE,
3034 &(adapter->tx_ring[i]->reinit_state));
3036 /* enable transmits */
3037 netif_tx_start_all_queues(netdev);
3039 /* bring the link up in the watchdog, this could race with our first
3040 * link up interrupt but shouldn't be a problem */
3041 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3042 adapter->link_check_timeout = jiffies;
3043 mod_timer(&adapter->watchdog_timer, jiffies);
3045 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3046 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3047 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3048 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3053 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3055 WARN_ON(in_interrupt());
3056 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3058 ixgbe_down(adapter);
3060 clear_bit(__IXGBE_RESETTING, &adapter->state);
3063 int ixgbe_up(struct ixgbe_adapter *adapter)
3065 /* hardware has been reset, we need to reload some things */
3066 ixgbe_configure(adapter);
3068 return ixgbe_up_complete(adapter);
3071 void ixgbe_reset(struct ixgbe_adapter *adapter)
3073 struct ixgbe_hw *hw = &adapter->hw;
3076 err = hw->mac.ops.init_hw(hw);
3079 case IXGBE_ERR_SFP_NOT_PRESENT:
3081 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3082 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3084 case IXGBE_ERR_EEPROM_VERSION:
3085 /* We are running on a pre-production device, log a warning */
3086 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3087 "adapter/LOM. Please be aware there may be issues "
3088 "associated with your hardware. If you are "
3089 "experiencing problems please contact your Intel or "
3090 "hardware representative who provided you with this "
3094 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3097 /* reprogram the RAR[0] in case user changed it. */
3098 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3103 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3104 * @adapter: board private structure
3105 * @rx_ring: ring to free buffers from
3107 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3108 struct ixgbe_ring *rx_ring)
3110 struct pci_dev *pdev = adapter->pdev;
3114 /* Free all the Rx ring sk_buffs */
3116 for (i = 0; i < rx_ring->count; i++) {
3117 struct ixgbe_rx_buffer *rx_buffer_info;
3119 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3120 if (rx_buffer_info->dma) {
3121 pci_unmap_single(pdev, rx_buffer_info->dma,
3122 rx_ring->rx_buf_len,
3123 PCI_DMA_FROMDEVICE);
3124 rx_buffer_info->dma = 0;
3126 if (rx_buffer_info->skb) {
3127 struct sk_buff *skb = rx_buffer_info->skb;
3128 rx_buffer_info->skb = NULL;
3130 struct sk_buff *this = skb;
3131 if (IXGBE_RSC_CB(this)->dma) {
3132 pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3133 rx_ring->rx_buf_len,
3134 PCI_DMA_FROMDEVICE);
3135 IXGBE_RSC_CB(this)->dma = 0;
3138 dev_kfree_skb(this);
3141 if (!rx_buffer_info->page)
3143 if (rx_buffer_info->page_dma) {
3144 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3145 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3146 rx_buffer_info->page_dma = 0;
3148 put_page(rx_buffer_info->page);
3149 rx_buffer_info->page = NULL;
3150 rx_buffer_info->page_offset = 0;
3153 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3154 memset(rx_ring->rx_buffer_info, 0, size);
3156 /* Zero out the descriptor ring */
3157 memset(rx_ring->desc, 0, rx_ring->size);
3159 rx_ring->next_to_clean = 0;
3160 rx_ring->next_to_use = 0;
3163 writel(0, adapter->hw.hw_addr + rx_ring->head);
3165 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3169 * ixgbe_clean_tx_ring - Free Tx Buffers
3170 * @adapter: board private structure
3171 * @tx_ring: ring to be cleaned
3173 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3174 struct ixgbe_ring *tx_ring)
3176 struct ixgbe_tx_buffer *tx_buffer_info;
3180 /* Free all the Tx ring sk_buffs */
3182 for (i = 0; i < tx_ring->count; i++) {
3183 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3184 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3187 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3188 memset(tx_ring->tx_buffer_info, 0, size);
3190 /* Zero out the descriptor ring */
3191 memset(tx_ring->desc, 0, tx_ring->size);
3193 tx_ring->next_to_use = 0;
3194 tx_ring->next_to_clean = 0;
3197 writel(0, adapter->hw.hw_addr + tx_ring->head);
3199 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3203 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3204 * @adapter: board private structure
3206 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3210 for (i = 0; i < adapter->num_rx_queues; i++)
3211 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3215 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3216 * @adapter: board private structure
3218 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3222 for (i = 0; i < adapter->num_tx_queues; i++)
3223 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3226 void ixgbe_down(struct ixgbe_adapter *adapter)
3228 struct net_device *netdev = adapter->netdev;
3229 struct ixgbe_hw *hw = &adapter->hw;
3234 /* signal that we are down to the interrupt handler */
3235 set_bit(__IXGBE_DOWN, &adapter->state);
3237 /* disable receive for all VFs and wait one second */
3238 if (adapter->num_vfs) {
3239 for (i = 0 ; i < adapter->num_vfs; i++)
3240 adapter->vfinfo[i].clear_to_send = 0;
3242 /* ping all the active vfs to let them know we are going down */
3243 ixgbe_ping_all_vfs(adapter);
3244 /* Disable all VFTE/VFRE TX/RX */
3245 ixgbe_disable_tx_rx(adapter);
3248 /* disable receives */
3249 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3250 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3252 netif_tx_disable(netdev);
3254 IXGBE_WRITE_FLUSH(hw);
3257 netif_tx_stop_all_queues(netdev);
3259 ixgbe_irq_disable(adapter);
3261 ixgbe_napi_disable_all(adapter);
3263 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3264 del_timer_sync(&adapter->sfp_timer);
3265 del_timer_sync(&adapter->watchdog_timer);
3266 cancel_work_sync(&adapter->watchdog_task);
3268 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3269 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3270 cancel_work_sync(&adapter->fdir_reinit_task);
3272 /* disable transmits in the hardware now that interrupts are off */
3273 for (i = 0; i < adapter->num_tx_queues; i++) {
3274 j = adapter->tx_ring[i]->reg_idx;
3275 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3276 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3277 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3279 /* Disable the Tx DMA engine on 82599 */
3280 if (hw->mac.type == ixgbe_mac_82599EB)
3281 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3282 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3283 ~IXGBE_DMATXCTL_TE));
3285 netif_carrier_off(netdev);
3287 /* clear n-tuple filters that are cached */
3288 ethtool_ntuple_flush(netdev);
3290 if (!pci_channel_offline(adapter->pdev))
3291 ixgbe_reset(adapter);
3292 ixgbe_clean_all_tx_rings(adapter);
3293 ixgbe_clean_all_rx_rings(adapter);
3295 #ifdef CONFIG_IXGBE_DCA
3296 /* since we reset the hardware DCA settings were cleared */
3297 ixgbe_setup_dca(adapter);
3302 * ixgbe_poll - NAPI Rx polling callback
3303 * @napi: structure for representing this polling device
3304 * @budget: how many packets driver is allowed to clean
3306 * This function is used for legacy and MSI, NAPI mode
3308 static int ixgbe_poll(struct napi_struct *napi, int budget)
3310 struct ixgbe_q_vector *q_vector =
3311 container_of(napi, struct ixgbe_q_vector, napi);
3312 struct ixgbe_adapter *adapter = q_vector->adapter;
3313 int tx_clean_complete, work_done = 0;
3315 #ifdef CONFIG_IXGBE_DCA
3316 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3317 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3318 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3322 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3323 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3325 if (!tx_clean_complete)
3328 /* If budget not fully consumed, exit the polling mode */
3329 if (work_done < budget) {
3330 napi_complete(napi);
3331 if (adapter->rx_itr_setting & 1)
3332 ixgbe_set_itr(adapter);
3333 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3334 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3340 * ixgbe_tx_timeout - Respond to a Tx Hang
3341 * @netdev: network interface device structure
3343 static void ixgbe_tx_timeout(struct net_device *netdev)
3345 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3347 /* Do the reset outside of interrupt context */
3348 schedule_work(&adapter->reset_task);
3351 static void ixgbe_reset_task(struct work_struct *work)
3353 struct ixgbe_adapter *adapter;
3354 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3356 /* If we're already down or resetting, just bail */
3357 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3358 test_bit(__IXGBE_RESETTING, &adapter->state))
3361 adapter->tx_timeout_count++;
3363 ixgbe_reinit_locked(adapter);
3366 #ifdef CONFIG_IXGBE_DCB
3367 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3370 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3372 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3376 adapter->num_rx_queues = f->indices;
3377 adapter->num_tx_queues = f->indices;
3385 * ixgbe_set_rss_queues: Allocate queues for RSS
3386 * @adapter: board private structure to initialize
3388 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3389 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3392 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3395 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3397 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3399 adapter->num_rx_queues = f->indices;
3400 adapter->num_tx_queues = f->indices;
3410 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3411 * @adapter: board private structure to initialize
3413 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3414 * to the original CPU that initiated the Tx session. This runs in addition
3415 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3416 * Rx load across CPUs using RSS.
3419 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3422 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3424 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3427 /* Flow Director must have RSS enabled */
3428 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3429 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3430 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3431 adapter->num_tx_queues = f_fdir->indices;
3432 adapter->num_rx_queues = f_fdir->indices;
3435 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3436 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3443 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3444 * @adapter: board private structure to initialize
3446 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3447 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3448 * rx queues out of the max number of rx queues, instead, it is used as the
3449 * index of the first rx queue used by FCoE.
3452 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3455 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3457 f->indices = min((int)num_online_cpus(), f->indices);
3458 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3459 adapter->num_rx_queues = 1;
3460 adapter->num_tx_queues = 1;
3461 #ifdef CONFIG_IXGBE_DCB
3462 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3463 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3464 ixgbe_set_dcb_queues(adapter);
3467 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3468 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3469 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3470 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3471 ixgbe_set_fdir_queues(adapter);
3473 ixgbe_set_rss_queues(adapter);
3475 /* adding FCoE rx rings to the end */
3476 f->mask = adapter->num_rx_queues;
3477 adapter->num_rx_queues += f->indices;
3478 adapter->num_tx_queues += f->indices;
3486 #endif /* IXGBE_FCOE */
3488 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3489 * @adapter: board private structure to initialize
3491 * IOV doesn't actually use anything, so just NAK the
3492 * request for now and let the other queue routines
3493 * figure out what to do.
3495 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3501 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3502 * @adapter: board private structure to initialize
3504 * This is the top level queue allocation routine. The order here is very
3505 * important, starting with the "most" number of features turned on at once,
3506 * and ending with the smallest set of features. This way large combinations
3507 * can be allocated if they're turned on, and smaller combinations are the
3508 * fallthrough conditions.
3511 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3513 /* Start with base case */
3514 adapter->num_rx_queues = 1;
3515 adapter->num_tx_queues = 1;
3516 adapter->num_rx_pools = adapter->num_rx_queues;
3517 adapter->num_rx_queues_per_pool = 1;
3519 if (ixgbe_set_sriov_queues(adapter))
3523 if (ixgbe_set_fcoe_queues(adapter))
3526 #endif /* IXGBE_FCOE */
3527 #ifdef CONFIG_IXGBE_DCB
3528 if (ixgbe_set_dcb_queues(adapter))
3532 if (ixgbe_set_fdir_queues(adapter))
3535 if (ixgbe_set_rss_queues(adapter))
3538 /* fallback to base case */
3539 adapter->num_rx_queues = 1;
3540 adapter->num_tx_queues = 1;
3543 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3544 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3547 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3550 int err, vector_threshold;
3552 /* We'll want at least 3 (vector_threshold):
3555 * 3) Other (Link Status Change, etc.)
3556 * 4) TCP Timer (optional)
3558 vector_threshold = MIN_MSIX_COUNT;
3560 /* The more we get, the more we will assign to Tx/Rx Cleanup
3561 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3562 * Right now, we simply care about how many we'll get; we'll
3563 * set them up later while requesting irq's.
3565 while (vectors >= vector_threshold) {
3566 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3568 if (!err) /* Success in acquiring all requested vectors. */
3571 vectors = 0; /* Nasty failure, quit now */
3572 else /* err == number of vectors we should try again with */
3576 if (vectors < vector_threshold) {
3577 /* Can't allocate enough MSI-X interrupts? Oh well.
3578 * This just means we'll go with either a single MSI
3579 * vector or fall back to legacy interrupts.
3581 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3582 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3583 kfree(adapter->msix_entries);
3584 adapter->msix_entries = NULL;
3586 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3588 * Adjust for only the vectors we'll use, which is minimum
3589 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3590 * vectors we were allocated.
3592 adapter->num_msix_vectors = min(vectors,
3593 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3598 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3599 * @adapter: board private structure to initialize
3601 * Cache the descriptor ring offsets for RSS to the assigned rings.
3604 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3609 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3610 for (i = 0; i < adapter->num_rx_queues; i++)
3611 adapter->rx_ring[i]->reg_idx = i;
3612 for (i = 0; i < adapter->num_tx_queues; i++)
3613 adapter->tx_ring[i]->reg_idx = i;
3622 #ifdef CONFIG_IXGBE_DCB
3624 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3625 * @adapter: board private structure to initialize
3627 * Cache the descriptor ring offsets for DCB to the assigned rings.
3630 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3634 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3636 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3637 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3638 /* the number of queues is assumed to be symmetric */
3639 for (i = 0; i < dcb_i; i++) {
3640 adapter->rx_ring[i]->reg_idx = i << 3;
3641 adapter->tx_ring[i]->reg_idx = i << 2;
3644 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3647 * Tx TC0 starts at: descriptor queue 0
3648 * Tx TC1 starts at: descriptor queue 32
3649 * Tx TC2 starts at: descriptor queue 64
3650 * Tx TC3 starts at: descriptor queue 80
3651 * Tx TC4 starts at: descriptor queue 96
3652 * Tx TC5 starts at: descriptor queue 104
3653 * Tx TC6 starts at: descriptor queue 112
3654 * Tx TC7 starts at: descriptor queue 120
3656 * Rx TC0-TC7 are offset by 16 queues each
3658 for (i = 0; i < 3; i++) {
3659 adapter->tx_ring[i]->reg_idx = i << 5;
3660 adapter->rx_ring[i]->reg_idx = i << 4;
3662 for ( ; i < 5; i++) {
3663 adapter->tx_ring[i]->reg_idx =
3665 adapter->rx_ring[i]->reg_idx = i << 4;
3667 for ( ; i < dcb_i; i++) {
3668 adapter->tx_ring[i]->reg_idx =
3670 adapter->rx_ring[i]->reg_idx = i << 4;
3674 } else if (dcb_i == 4) {
3676 * Tx TC0 starts at: descriptor queue 0
3677 * Tx TC1 starts at: descriptor queue 64
3678 * Tx TC2 starts at: descriptor queue 96
3679 * Tx TC3 starts at: descriptor queue 112
3681 * Rx TC0-TC3 are offset by 32 queues each
3683 adapter->tx_ring[0]->reg_idx = 0;
3684 adapter->tx_ring[1]->reg_idx = 64;
3685 adapter->tx_ring[2]->reg_idx = 96;
3686 adapter->tx_ring[3]->reg_idx = 112;
3687 for (i = 0 ; i < dcb_i; i++)
3688 adapter->rx_ring[i]->reg_idx = i << 5;
3706 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3707 * @adapter: board private structure to initialize
3709 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3712 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3717 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3718 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3719 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3720 for (i = 0; i < adapter->num_rx_queues; i++)
3721 adapter->rx_ring[i]->reg_idx = i;
3722 for (i = 0; i < adapter->num_tx_queues; i++)
3723 adapter->tx_ring[i]->reg_idx = i;
3732 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3733 * @adapter: board private structure to initialize
3735 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3738 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3740 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3742 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3744 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3745 #ifdef CONFIG_IXGBE_DCB
3746 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3747 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3749 ixgbe_cache_ring_dcb(adapter);
3750 /* find out queues in TC for FCoE */
3751 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3752 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
3754 * In 82599, the number of Tx queues for each traffic
3755 * class for both 8-TC and 4-TC modes are:
3756 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3757 * 8 TCs: 32 32 16 16 8 8 8 8
3758 * 4 TCs: 64 64 32 32
3759 * We have max 8 queues for FCoE, where 8 the is
3760 * FCoE redirection table size. If TC for FCoE is
3761 * less than or equal to TC3, we have enough queues
3762 * to add max of 8 queues for FCoE, so we start FCoE
3763 * tx descriptor from the next one, i.e., reg_idx + 1.
3764 * If TC for FCoE is above TC3, implying 8 TC mode,
3765 * and we need 8 for FCoE, we have to take all queues
3766 * in that traffic class for FCoE.
3768 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3771 #endif /* CONFIG_IXGBE_DCB */
3772 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3773 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3774 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3775 ixgbe_cache_ring_fdir(adapter);
3777 ixgbe_cache_ring_rss(adapter);
3779 fcoe_rx_i = f->mask;
3780 fcoe_tx_i = f->mask;
3782 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3783 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3784 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
3791 #endif /* IXGBE_FCOE */
3793 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3794 * @adapter: board private structure to initialize
3796 * SR-IOV doesn't use any descriptor rings but changes the default if
3797 * no other mapping is used.
3800 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3802 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3803 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
3804 if (adapter->num_vfs)
3811 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3812 * @adapter: board private structure to initialize
3814 * Once we know the feature-set enabled for the device, we'll cache
3815 * the register offset the descriptor ring is assigned to.
3817 * Note, the order the various feature calls is important. It must start with
3818 * the "most" features enabled at the same time, then trickle down to the
3819 * least amount of features turned on at once.
3821 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3823 /* start with default case */
3824 adapter->rx_ring[0]->reg_idx = 0;
3825 adapter->tx_ring[0]->reg_idx = 0;
3827 if (ixgbe_cache_ring_sriov(adapter))
3831 if (ixgbe_cache_ring_fcoe(adapter))
3834 #endif /* IXGBE_FCOE */
3835 #ifdef CONFIG_IXGBE_DCB
3836 if (ixgbe_cache_ring_dcb(adapter))
3840 if (ixgbe_cache_ring_fdir(adapter))
3843 if (ixgbe_cache_ring_rss(adapter))
3848 * ixgbe_alloc_queues - Allocate memory for all rings
3849 * @adapter: board private structure to initialize
3851 * We allocate one ring per queue at run-time since we don't know the
3852 * number of queues at compile-time. The polling_netdev array is
3853 * intended for Multiqueue, but should work fine with a single queue.
3855 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3858 int orig_node = adapter->node;
3860 for (i = 0; i < adapter->num_tx_queues; i++) {
3861 struct ixgbe_ring *ring = adapter->tx_ring[i];
3862 if (orig_node == -1) {
3863 int cur_node = next_online_node(adapter->node);
3864 if (cur_node == MAX_NUMNODES)
3865 cur_node = first_online_node;
3866 adapter->node = cur_node;
3868 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3871 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3873 goto err_tx_ring_allocation;
3874 ring->count = adapter->tx_ring_count;
3875 ring->queue_index = i;
3876 ring->numa_node = adapter->node;
3878 adapter->tx_ring[i] = ring;
3881 /* Restore the adapter's original node */
3882 adapter->node = orig_node;
3884 for (i = 0; i < adapter->num_rx_queues; i++) {
3885 struct ixgbe_ring *ring = adapter->rx_ring[i];
3886 if (orig_node == -1) {
3887 int cur_node = next_online_node(adapter->node);
3888 if (cur_node == MAX_NUMNODES)
3889 cur_node = first_online_node;
3890 adapter->node = cur_node;
3892 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3895 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3897 goto err_rx_ring_allocation;
3898 ring->count = adapter->rx_ring_count;
3899 ring->queue_index = i;
3900 ring->numa_node = adapter->node;
3902 adapter->rx_ring[i] = ring;
3905 /* Restore the adapter's original node */
3906 adapter->node = orig_node;
3908 ixgbe_cache_ring_register(adapter);
3912 err_rx_ring_allocation:
3913 for (i = 0; i < adapter->num_tx_queues; i++)
3914 kfree(adapter->tx_ring[i]);
3915 err_tx_ring_allocation:
3920 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3921 * @adapter: board private structure to initialize
3923 * Attempt to configure the interrupts using the best available
3924 * capabilities of the hardware and the kernel.
3926 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3928 struct ixgbe_hw *hw = &adapter->hw;
3930 int vector, v_budget;
3933 * It's easy to be greedy for MSI-X vectors, but it really
3934 * doesn't do us much good if we have a lot more vectors
3935 * than CPU's. So let's be conservative and only ask for
3936 * (roughly) the same number of vectors as there are CPU's.
3938 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3939 (int)num_online_cpus()) + NON_Q_VECTORS;
3942 * At the same time, hardware can only support a maximum of
3943 * hw.mac->max_msix_vectors vectors. With features
3944 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3945 * descriptor queues supported by our device. Thus, we cap it off in
3946 * those rare cases where the cpu count also exceeds our vector limit.
3948 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3950 /* A failure in MSI-X entry allocation isn't fatal, but it does
3951 * mean we disable MSI-X capabilities of the adapter. */
3952 adapter->msix_entries = kcalloc(v_budget,
3953 sizeof(struct msix_entry), GFP_KERNEL);
3954 if (adapter->msix_entries) {
3955 for (vector = 0; vector < v_budget; vector++)
3956 adapter->msix_entries[vector].entry = vector;
3958 ixgbe_acquire_msix_vectors(adapter, v_budget);
3960 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3964 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3965 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3966 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3967 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3968 adapter->atr_sample_rate = 0;
3969 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3970 ixgbe_disable_sriov(adapter);
3972 ixgbe_set_num_queues(adapter);
3974 err = pci_enable_msi(adapter->pdev);
3976 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3978 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3979 "falling back to legacy. Error: %d\n", err);
3989 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3990 * @adapter: board private structure to initialize
3992 * We allocate one q_vector per queue interrupt. If allocation fails we
3995 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3997 int q_idx, num_q_vectors;
3998 struct ixgbe_q_vector *q_vector;
4000 int (*poll)(struct napi_struct *, int);
4002 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4003 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4004 napi_vectors = adapter->num_rx_queues;
4005 poll = &ixgbe_clean_rxtx_many;
4012 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4013 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4014 GFP_KERNEL, adapter->node);
4016 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4020 q_vector->adapter = adapter;
4021 if (q_vector->txr_count && !q_vector->rxr_count)
4022 q_vector->eitr = adapter->tx_eitr_param;
4024 q_vector->eitr = adapter->rx_eitr_param;
4025 q_vector->v_idx = q_idx;
4026 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4027 adapter->q_vector[q_idx] = q_vector;
4035 q_vector = adapter->q_vector[q_idx];
4036 netif_napi_del(&q_vector->napi);
4038 adapter->q_vector[q_idx] = NULL;
4044 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4045 * @adapter: board private structure to initialize
4047 * This function frees the memory allocated to the q_vectors. In addition if
4048 * NAPI is enabled it will delete any references to the NAPI struct prior
4049 * to freeing the q_vector.
4051 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4053 int q_idx, num_q_vectors;
4055 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4056 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4060 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4061 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4062 adapter->q_vector[q_idx] = NULL;
4063 netif_napi_del(&q_vector->napi);
4068 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4070 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4071 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4072 pci_disable_msix(adapter->pdev);
4073 kfree(adapter->msix_entries);
4074 adapter->msix_entries = NULL;
4075 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4076 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4077 pci_disable_msi(adapter->pdev);
4083 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4084 * @adapter: board private structure to initialize
4086 * We determine which interrupt scheme to use based on...
4087 * - Kernel support (MSI, MSI-X)
4088 * - which can be user-defined (via MODULE_PARAM)
4089 * - Hardware queue count (num_*_queues)
4090 * - defined by miscellaneous hardware support/features (RSS, etc.)
4092 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4096 /* Number of supported queues */
4097 ixgbe_set_num_queues(adapter);
4099 err = ixgbe_set_interrupt_capability(adapter);
4101 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4102 goto err_set_interrupt;
4105 err = ixgbe_alloc_q_vectors(adapter);
4107 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4109 goto err_alloc_q_vectors;
4112 err = ixgbe_alloc_queues(adapter);
4114 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4115 goto err_alloc_queues;
4118 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4119 "Tx Queue count = %u\n",
4120 (adapter->num_rx_queues > 1) ? "Enabled" :
4121 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4123 set_bit(__IXGBE_DOWN, &adapter->state);
4128 ixgbe_free_q_vectors(adapter);
4129 err_alloc_q_vectors:
4130 ixgbe_reset_interrupt_capability(adapter);
4136 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4137 * @adapter: board private structure to clear interrupt scheme on
4139 * We go through and clear interrupt specific resources and reset the structure
4140 * to pre-load conditions
4142 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4146 for (i = 0; i < adapter->num_tx_queues; i++) {
4147 kfree(adapter->tx_ring[i]);
4148 adapter->tx_ring[i] = NULL;
4150 for (i = 0; i < adapter->num_rx_queues; i++) {
4151 kfree(adapter->rx_ring[i]);
4152 adapter->rx_ring[i] = NULL;
4155 ixgbe_free_q_vectors(adapter);
4156 ixgbe_reset_interrupt_capability(adapter);
4160 * ixgbe_sfp_timer - worker thread to find a missing module
4161 * @data: pointer to our adapter struct
4163 static void ixgbe_sfp_timer(unsigned long data)
4165 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4168 * Do the sfp_timer outside of interrupt context due to the
4169 * delays that sfp+ detection requires
4171 schedule_work(&adapter->sfp_task);
4175 * ixgbe_sfp_task - worker thread to find a missing module
4176 * @work: pointer to work_struct containing our data
4178 static void ixgbe_sfp_task(struct work_struct *work)
4180 struct ixgbe_adapter *adapter = container_of(work,
4181 struct ixgbe_adapter,
4183 struct ixgbe_hw *hw = &adapter->hw;
4185 if ((hw->phy.type == ixgbe_phy_nl) &&
4186 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4187 s32 ret = hw->phy.ops.identify_sfp(hw);
4188 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4190 ret = hw->phy.ops.reset(hw);
4191 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4192 dev_err(&adapter->pdev->dev, "failed to initialize "
4193 "because an unsupported SFP+ module type "
4195 "Reload the driver after installing a "
4196 "supported module.\n");
4197 unregister_netdev(adapter->netdev);
4199 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4202 /* don't need this routine any more */
4203 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4207 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4208 mod_timer(&adapter->sfp_timer,
4209 round_jiffies(jiffies + (2 * HZ)));
4213 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4214 * @adapter: board private structure to initialize
4216 * ixgbe_sw_init initializes the Adapter private data structure.
4217 * Fields are initialized based on PCI device information and
4218 * OS network device settings (MTU size).
4220 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4222 struct ixgbe_hw *hw = &adapter->hw;
4223 struct pci_dev *pdev = adapter->pdev;
4224 struct net_device *dev = adapter->netdev;
4226 #ifdef CONFIG_IXGBE_DCB
4228 struct tc_configuration *tc;
4231 /* PCI config space info */
4233 hw->vendor_id = pdev->vendor;
4234 hw->device_id = pdev->device;
4235 hw->revision_id = pdev->revision;
4236 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4237 hw->subsystem_device_id = pdev->subsystem_device;
4239 /* Set capability flags */
4240 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4241 adapter->ring_feature[RING_F_RSS].indices = rss;
4242 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4243 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4244 if (hw->mac.type == ixgbe_mac_82598EB) {
4245 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4246 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4247 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4248 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4249 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4250 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4251 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4252 if (dev->features & NETIF_F_NTUPLE) {
4253 /* Flow Director perfect filter enabled */
4254 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4255 adapter->atr_sample_rate = 0;
4256 spin_lock_init(&adapter->fdir_perfect_lock);
4258 /* Flow Director hash filters enabled */
4259 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4260 adapter->atr_sample_rate = 20;
4262 adapter->ring_feature[RING_F_FDIR].indices =
4263 IXGBE_MAX_FDIR_INDICES;
4264 adapter->fdir_pballoc = 0;
4266 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4267 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4268 adapter->ring_feature[RING_F_FCOE].indices = 0;
4269 #ifdef CONFIG_IXGBE_DCB
4270 /* Default traffic class to use for FCoE */
4271 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4273 #endif /* IXGBE_FCOE */
4276 #ifdef CONFIG_IXGBE_DCB
4277 /* Configure DCB traffic classes */
4278 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4279 tc = &adapter->dcb_cfg.tc_config[j];
4280 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4281 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4282 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4283 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4284 tc->dcb_pfc = pfc_disabled;
4286 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4287 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4288 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4289 adapter->dcb_cfg.pfc_mode_enable = false;
4290 adapter->dcb_cfg.round_robin_enable = false;
4291 adapter->dcb_set_bitmap = 0x00;
4292 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4293 adapter->ring_feature[RING_F_DCB].indices);
4297 /* default flow control settings */
4298 hw->fc.requested_mode = ixgbe_fc_full;
4299 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4301 adapter->last_lfc_mode = hw->fc.current_mode;
4303 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4304 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4305 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4306 hw->fc.send_xon = true;
4307 hw->fc.disable_fc_autoneg = false;
4309 /* enable itr by default in dynamic mode */
4310 adapter->rx_itr_setting = 1;
4311 adapter->rx_eitr_param = 20000;
4312 adapter->tx_itr_setting = 1;
4313 adapter->tx_eitr_param = 10000;
4315 /* set defaults for eitr in MegaBytes */
4316 adapter->eitr_low = 10;
4317 adapter->eitr_high = 20;
4319 /* set default ring sizes */
4320 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4321 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4323 /* initialize eeprom parameters */
4324 if (ixgbe_init_eeprom_params_generic(hw)) {
4325 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4329 /* enable rx csum by default */
4330 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4332 /* get assigned NUMA node */
4333 adapter->node = dev_to_node(&pdev->dev);
4335 set_bit(__IXGBE_DOWN, &adapter->state);
4341 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4342 * @adapter: board private structure
4343 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4345 * Return 0 on success, negative on failure
4347 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4348 struct ixgbe_ring *tx_ring)
4350 struct pci_dev *pdev = adapter->pdev;
4353 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4354 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4355 if (!tx_ring->tx_buffer_info)
4356 tx_ring->tx_buffer_info = vmalloc(size);
4357 if (!tx_ring->tx_buffer_info)
4359 memset(tx_ring->tx_buffer_info, 0, size);
4361 /* round up to nearest 4K */
4362 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4363 tx_ring->size = ALIGN(tx_ring->size, 4096);
4365 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4370 tx_ring->next_to_use = 0;
4371 tx_ring->next_to_clean = 0;
4372 tx_ring->work_limit = tx_ring->count;
4376 vfree(tx_ring->tx_buffer_info);
4377 tx_ring->tx_buffer_info = NULL;
4378 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4379 "descriptor ring\n");
4384 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4385 * @adapter: board private structure
4387 * If this function returns with an error, then it's possible one or
4388 * more of the rings is populated (while the rest are not). It is the
4389 * callers duty to clean those orphaned rings.
4391 * Return 0 on success, negative on failure
4393 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4397 for (i = 0; i < adapter->num_tx_queues; i++) {
4398 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4401 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4409 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4410 * @adapter: board private structure
4411 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4413 * Returns 0 on success, negative on failure
4415 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4416 struct ixgbe_ring *rx_ring)
4418 struct pci_dev *pdev = adapter->pdev;
4421 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4422 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4423 if (!rx_ring->rx_buffer_info)
4424 rx_ring->rx_buffer_info = vmalloc(size);
4425 if (!rx_ring->rx_buffer_info) {
4427 "vmalloc allocation failed for the rx desc ring\n");
4430 memset(rx_ring->rx_buffer_info, 0, size);
4432 /* Round up to nearest 4K */
4433 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4434 rx_ring->size = ALIGN(rx_ring->size, 4096);
4436 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4438 if (!rx_ring->desc) {
4440 "Memory allocation failed for the rx desc ring\n");
4441 vfree(rx_ring->rx_buffer_info);
4445 rx_ring->next_to_clean = 0;
4446 rx_ring->next_to_use = 0;
4455 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4456 * @adapter: board private structure
4458 * If this function returns with an error, then it's possible one or
4459 * more of the rings is populated (while the rest are not). It is the
4460 * callers duty to clean those orphaned rings.
4462 * Return 0 on success, negative on failure
4465 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4469 for (i = 0; i < adapter->num_rx_queues; i++) {
4470 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4473 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4481 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4482 * @adapter: board private structure
4483 * @tx_ring: Tx descriptor ring for a specific queue
4485 * Free all transmit software resources
4487 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4488 struct ixgbe_ring *tx_ring)
4490 struct pci_dev *pdev = adapter->pdev;
4492 ixgbe_clean_tx_ring(adapter, tx_ring);
4494 vfree(tx_ring->tx_buffer_info);
4495 tx_ring->tx_buffer_info = NULL;
4497 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4499 tx_ring->desc = NULL;
4503 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4504 * @adapter: board private structure
4506 * Free all transmit software resources
4508 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4512 for (i = 0; i < adapter->num_tx_queues; i++)
4513 if (adapter->tx_ring[i]->desc)
4514 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4518 * ixgbe_free_rx_resources - Free Rx Resources
4519 * @adapter: board private structure
4520 * @rx_ring: ring to clean the resources from
4522 * Free all receive software resources
4524 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4525 struct ixgbe_ring *rx_ring)
4527 struct pci_dev *pdev = adapter->pdev;
4529 ixgbe_clean_rx_ring(adapter, rx_ring);
4531 vfree(rx_ring->rx_buffer_info);
4532 rx_ring->rx_buffer_info = NULL;
4534 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4536 rx_ring->desc = NULL;
4540 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4541 * @adapter: board private structure
4543 * Free all receive software resources
4545 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4549 for (i = 0; i < adapter->num_rx_queues; i++)
4550 if (adapter->rx_ring[i]->desc)
4551 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
4555 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4556 * @netdev: network interface device structure
4557 * @new_mtu: new value for maximum frame size
4559 * Returns 0 on success, negative on failure
4561 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4563 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4564 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4566 /* MTU < 68 is an error and causes problems on some kernels */
4567 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4570 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4571 netdev->mtu, new_mtu);
4572 /* must set new MTU before calling down or up */
4573 netdev->mtu = new_mtu;
4575 if (netif_running(netdev))
4576 ixgbe_reinit_locked(adapter);
4582 * ixgbe_open - Called when a network interface is made active
4583 * @netdev: network interface device structure
4585 * Returns 0 on success, negative value on failure
4587 * The open entry point is called when a network interface is made
4588 * active by the system (IFF_UP). At this point all resources needed
4589 * for transmit and receive operations are allocated, the interrupt
4590 * handler is registered with the OS, the watchdog timer is started,
4591 * and the stack is notified that the interface is ready.
4593 static int ixgbe_open(struct net_device *netdev)
4595 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4598 /* disallow open during test */
4599 if (test_bit(__IXGBE_TESTING, &adapter->state))
4602 netif_carrier_off(netdev);
4604 /* allocate transmit descriptors */
4605 err = ixgbe_setup_all_tx_resources(adapter);
4609 /* allocate receive descriptors */
4610 err = ixgbe_setup_all_rx_resources(adapter);
4614 ixgbe_configure(adapter);
4616 err = ixgbe_request_irq(adapter);
4620 err = ixgbe_up_complete(adapter);
4624 netif_tx_start_all_queues(netdev);
4629 ixgbe_release_hw_control(adapter);
4630 ixgbe_free_irq(adapter);
4633 ixgbe_free_all_rx_resources(adapter);
4635 ixgbe_free_all_tx_resources(adapter);
4636 ixgbe_reset(adapter);
4642 * ixgbe_close - Disables a network interface
4643 * @netdev: network interface device structure
4645 * Returns 0, this is not allowed to fail
4647 * The close entry point is called when an interface is de-activated
4648 * by the OS. The hardware is still under the drivers control, but
4649 * needs to be disabled. A global MAC reset is issued to stop the
4650 * hardware, and all transmit and receive resources are freed.
4652 static int ixgbe_close(struct net_device *netdev)
4654 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4656 ixgbe_down(adapter);
4657 ixgbe_free_irq(adapter);
4659 ixgbe_free_all_tx_resources(adapter);
4660 ixgbe_free_all_rx_resources(adapter);
4662 ixgbe_release_hw_control(adapter);
4668 static int ixgbe_resume(struct pci_dev *pdev)
4670 struct net_device *netdev = pci_get_drvdata(pdev);
4671 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4674 pci_set_power_state(pdev, PCI_D0);
4675 pci_restore_state(pdev);
4677 * pci_restore_state clears dev->state_saved so call
4678 * pci_save_state to restore it.
4680 pci_save_state(pdev);
4682 err = pci_enable_device_mem(pdev);
4684 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4688 pci_set_master(pdev);
4690 pci_wake_from_d3(pdev, false);
4692 err = ixgbe_init_interrupt_scheme(adapter);
4694 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4699 ixgbe_reset(adapter);
4701 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4703 if (netif_running(netdev)) {
4704 err = ixgbe_open(adapter->netdev);
4709 netif_device_attach(netdev);
4713 #endif /* CONFIG_PM */
4715 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4717 struct net_device *netdev = pci_get_drvdata(pdev);
4718 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4719 struct ixgbe_hw *hw = &adapter->hw;
4721 u32 wufc = adapter->wol;
4726 netif_device_detach(netdev);
4728 if (netif_running(netdev)) {
4729 ixgbe_down(adapter);
4730 ixgbe_free_irq(adapter);
4731 ixgbe_free_all_tx_resources(adapter);
4732 ixgbe_free_all_rx_resources(adapter);
4734 ixgbe_clear_interrupt_scheme(adapter);
4737 retval = pci_save_state(pdev);
4743 ixgbe_set_rx_mode(netdev);
4745 /* turn on all-multi mode if wake on multicast is enabled */
4746 if (wufc & IXGBE_WUFC_MC) {
4747 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4748 fctrl |= IXGBE_FCTRL_MPE;
4749 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4752 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4753 ctrl |= IXGBE_CTRL_GIO_DIS;
4754 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4756 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4758 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4759 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4762 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4763 pci_wake_from_d3(pdev, true);
4765 pci_wake_from_d3(pdev, false);
4767 *enable_wake = !!wufc;
4769 ixgbe_release_hw_control(adapter);
4771 pci_disable_device(pdev);
4777 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4782 retval = __ixgbe_shutdown(pdev, &wake);
4787 pci_prepare_to_sleep(pdev);
4789 pci_wake_from_d3(pdev, false);
4790 pci_set_power_state(pdev, PCI_D3hot);
4795 #endif /* CONFIG_PM */
4797 static void ixgbe_shutdown(struct pci_dev *pdev)
4801 __ixgbe_shutdown(pdev, &wake);
4803 if (system_state == SYSTEM_POWER_OFF) {
4804 pci_wake_from_d3(pdev, wake);
4805 pci_set_power_state(pdev, PCI_D3hot);
4810 * ixgbe_update_stats - Update the board statistics counters.
4811 * @adapter: board private structure
4813 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4815 struct net_device *netdev = adapter->netdev;
4816 struct ixgbe_hw *hw = &adapter->hw;
4818 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4819 u64 non_eop_descs = 0, restart_queue = 0;
4821 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4824 for (i = 0; i < 16; i++)
4825 adapter->hw_rx_no_dma_resources +=
4826 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4827 for (i = 0; i < adapter->num_rx_queues; i++) {
4828 rsc_count += adapter->rx_ring[i]->rsc_count;
4829 rsc_flush += adapter->rx_ring[i]->rsc_flush;
4831 adapter->rsc_total_count = rsc_count;
4832 adapter->rsc_total_flush = rsc_flush;
4835 /* gather some stats to the adapter struct that are per queue */
4836 for (i = 0; i < adapter->num_tx_queues; i++)
4837 restart_queue += adapter->tx_ring[i]->restart_queue;
4838 adapter->restart_queue = restart_queue;
4840 for (i = 0; i < adapter->num_rx_queues; i++)
4841 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
4842 adapter->non_eop_descs = non_eop_descs;
4844 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4845 for (i = 0; i < 8; i++) {
4846 /* for packet buffers not used, the register should read 0 */
4847 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4849 adapter->stats.mpc[i] += mpc;
4850 total_mpc += adapter->stats.mpc[i];
4851 if (hw->mac.type == ixgbe_mac_82598EB)
4852 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4853 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4854 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4855 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4856 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4857 if (hw->mac.type == ixgbe_mac_82599EB) {
4858 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4859 IXGBE_PXONRXCNT(i));
4860 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4861 IXGBE_PXOFFRXCNT(i));
4862 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4864 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4866 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4869 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4871 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4874 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4875 /* work around hardware counting issue */
4876 adapter->stats.gprc -= missed_rx;
4878 /* 82598 hardware only has a 32 bit counter in the high register */
4879 if (hw->mac.type == ixgbe_mac_82599EB) {
4881 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4882 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4883 adapter->stats.gorc += (tmp << 32);
4884 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4885 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4886 adapter->stats.gotc += (tmp << 32);
4887 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4888 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4889 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4890 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4891 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4892 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4894 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4895 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4896 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4897 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4898 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4899 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4900 #endif /* IXGBE_FCOE */
4902 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4903 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4904 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4905 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4906 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4908 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4909 adapter->stats.bprc += bprc;
4910 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4911 if (hw->mac.type == ixgbe_mac_82598EB)
4912 adapter->stats.mprc -= bprc;
4913 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4914 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4915 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4916 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4917 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4918 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4919 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4920 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4921 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4922 adapter->stats.lxontxc += lxon;
4923 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4924 adapter->stats.lxofftxc += lxoff;
4925 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4926 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4927 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4929 * 82598 errata - tx of flow control packets is included in tx counters
4931 xon_off_tot = lxon + lxoff;
4932 adapter->stats.gptc -= xon_off_tot;
4933 adapter->stats.mptc -= xon_off_tot;
4934 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4935 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4936 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4937 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4938 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4939 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4940 adapter->stats.ptc64 -= xon_off_tot;
4941 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4942 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4943 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4944 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4945 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4946 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4948 /* Fill out the OS statistics structure */
4949 netdev->stats.multicast = adapter->stats.mprc;
4952 netdev->stats.rx_errors = adapter->stats.crcerrs +
4953 adapter->stats.rlec;
4954 netdev->stats.rx_dropped = 0;
4955 netdev->stats.rx_length_errors = adapter->stats.rlec;
4956 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4957 netdev->stats.rx_missed_errors = total_mpc;
4961 * ixgbe_watchdog - Timer Call-back
4962 * @data: pointer to adapter cast into an unsigned long
4964 static void ixgbe_watchdog(unsigned long data)
4966 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4967 struct ixgbe_hw *hw = &adapter->hw;
4972 * Do the watchdog outside of interrupt context due to the lovely
4973 * delays that some of the newer hardware requires
4976 if (test_bit(__IXGBE_DOWN, &adapter->state))
4977 goto watchdog_short_circuit;
4979 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4981 * for legacy and MSI interrupts don't set any bits
4982 * that are enabled for EIAM, because this operation
4983 * would set *both* EIMS and EICS for any bit in EIAM
4985 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4986 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4987 goto watchdog_reschedule;
4990 /* get one bit for every active tx/rx interrupt vector */
4991 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4992 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4993 if (qv->rxr_count || qv->txr_count)
4994 eics |= ((u64)1 << i);
4997 /* Cause software interrupt to ensure rx rings are cleaned */
4998 ixgbe_irq_rearm_queues(adapter, eics);
5000 watchdog_reschedule:
5001 /* Reset the timer */
5002 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5004 watchdog_short_circuit:
5005 schedule_work(&adapter->watchdog_task);
5009 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5010 * @work: pointer to work_struct containing our data
5012 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5014 struct ixgbe_adapter *adapter = container_of(work,
5015 struct ixgbe_adapter,
5016 multispeed_fiber_task);
5017 struct ixgbe_hw *hw = &adapter->hw;
5021 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5022 autoneg = hw->phy.autoneg_advertised;
5023 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5024 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5025 hw->mac.autotry_restart = false;
5026 if (hw->mac.ops.setup_link)
5027 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5028 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5029 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5033 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5034 * @work: pointer to work_struct containing our data
5036 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5038 struct ixgbe_adapter *adapter = container_of(work,
5039 struct ixgbe_adapter,
5040 sfp_config_module_task);
5041 struct ixgbe_hw *hw = &adapter->hw;
5044 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5046 /* Time for electrical oscillations to settle down */
5048 err = hw->phy.ops.identify_sfp(hw);
5050 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5051 dev_err(&adapter->pdev->dev, "failed to initialize because "
5052 "an unsupported SFP+ module type was detected.\n"
5053 "Reload the driver after installing a supported "
5055 unregister_netdev(adapter->netdev);
5058 hw->mac.ops.setup_sfp(hw);
5060 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5061 /* This will also work for DA Twinax connections */
5062 schedule_work(&adapter->multispeed_fiber_task);
5063 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5067 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5068 * @work: pointer to work_struct containing our data
5070 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5072 struct ixgbe_adapter *adapter = container_of(work,
5073 struct ixgbe_adapter,
5075 struct ixgbe_hw *hw = &adapter->hw;
5078 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5079 for (i = 0; i < adapter->num_tx_queues; i++)
5080 set_bit(__IXGBE_FDIR_INIT_DONE,
5081 &(adapter->tx_ring[i]->reinit_state));
5083 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5084 "ignored adding FDIR ATR filters \n");
5086 /* Done FDIR Re-initialization, enable transmits */
5087 netif_tx_start_all_queues(adapter->netdev);
5090 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5093 * ixgbe_watchdog_task - worker thread to bring link up
5094 * @work: pointer to work_struct containing our data
5096 static void ixgbe_watchdog_task(struct work_struct *work)
5098 struct ixgbe_adapter *adapter = container_of(work,
5099 struct ixgbe_adapter,
5101 struct net_device *netdev = adapter->netdev;
5102 struct ixgbe_hw *hw = &adapter->hw;
5106 struct ixgbe_ring *tx_ring;
5107 int some_tx_pending = 0;
5109 mutex_lock(&ixgbe_watchdog_lock);
5111 link_up = adapter->link_up;
5112 link_speed = adapter->link_speed;
5114 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5115 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5118 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5119 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5120 hw->mac.ops.fc_enable(hw, i);
5122 hw->mac.ops.fc_enable(hw, 0);
5125 hw->mac.ops.fc_enable(hw, 0);
5130 time_after(jiffies, (adapter->link_check_timeout +
5131 IXGBE_TRY_LINK_TIMEOUT))) {
5132 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5133 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5135 adapter->link_up = link_up;
5136 adapter->link_speed = link_speed;
5140 if (!netif_carrier_ok(netdev)) {
5141 bool flow_rx, flow_tx;
5143 if (hw->mac.type == ixgbe_mac_82599EB) {
5144 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5145 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5146 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5147 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5149 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5150 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5151 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5152 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5155 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5156 "Flow Control: %s\n",
5158 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5160 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5161 "1 Gbps" : "unknown speed")),
5162 ((flow_rx && flow_tx) ? "RX/TX" :
5164 (flow_tx ? "TX" : "None"))));
5166 netif_carrier_on(netdev);
5168 /* Force detection of hung controller */
5169 adapter->detect_tx_hung = true;
5172 adapter->link_up = false;
5173 adapter->link_speed = 0;
5174 if (netif_carrier_ok(netdev)) {
5175 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5177 netif_carrier_off(netdev);
5181 if (!netif_carrier_ok(netdev)) {
5182 for (i = 0; i < adapter->num_tx_queues; i++) {
5183 tx_ring = adapter->tx_ring[i];
5184 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5185 some_tx_pending = 1;
5190 if (some_tx_pending) {
5191 /* We've lost link, so the controller stops DMA,
5192 * but we've got queued Tx work that's never going
5193 * to get done, so reset controller to flush Tx.
5194 * (Do the reset outside of interrupt context).
5196 schedule_work(&adapter->reset_task);
5200 ixgbe_update_stats(adapter);
5201 mutex_unlock(&ixgbe_watchdog_lock);
5204 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5205 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5206 u32 tx_flags, u8 *hdr_len)
5208 struct ixgbe_adv_tx_context_desc *context_desc;
5211 struct ixgbe_tx_buffer *tx_buffer_info;
5212 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5213 u32 mss_l4len_idx, l4len;
5215 if (skb_is_gso(skb)) {
5216 if (skb_header_cloned(skb)) {
5217 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5221 l4len = tcp_hdrlen(skb);
5224 if (skb->protocol == htons(ETH_P_IP)) {
5225 struct iphdr *iph = ip_hdr(skb);
5228 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5232 } else if (skb_is_gso_v6(skb)) {
5233 ipv6_hdr(skb)->payload_len = 0;
5234 tcp_hdr(skb)->check =
5235 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5236 &ipv6_hdr(skb)->daddr,
5240 i = tx_ring->next_to_use;
5242 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5243 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5245 /* VLAN MACLEN IPLEN */
5246 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5248 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5249 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5250 IXGBE_ADVTXD_MACLEN_SHIFT);
5251 *hdr_len += skb_network_offset(skb);
5253 (skb_transport_header(skb) - skb_network_header(skb));
5255 (skb_transport_header(skb) - skb_network_header(skb));
5256 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5257 context_desc->seqnum_seed = 0;
5259 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5260 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5261 IXGBE_ADVTXD_DTYP_CTXT);
5263 if (skb->protocol == htons(ETH_P_IP))
5264 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5265 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5266 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5270 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5271 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5272 /* use index 1 for TSO */
5273 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5274 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5276 tx_buffer_info->time_stamp = jiffies;
5277 tx_buffer_info->next_to_watch = i;
5280 if (i == tx_ring->count)
5282 tx_ring->next_to_use = i;
5289 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5290 struct ixgbe_ring *tx_ring,
5291 struct sk_buff *skb, u32 tx_flags)
5293 struct ixgbe_adv_tx_context_desc *context_desc;
5295 struct ixgbe_tx_buffer *tx_buffer_info;
5296 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5298 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5299 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5300 i = tx_ring->next_to_use;
5301 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5302 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5304 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5306 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5307 vlan_macip_lens |= (skb_network_offset(skb) <<
5308 IXGBE_ADVTXD_MACLEN_SHIFT);
5309 if (skb->ip_summed == CHECKSUM_PARTIAL)
5310 vlan_macip_lens |= (skb_transport_header(skb) -
5311 skb_network_header(skb));
5313 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5314 context_desc->seqnum_seed = 0;
5316 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5317 IXGBE_ADVTXD_DTYP_CTXT);
5319 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5322 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5323 const struct vlan_ethhdr *vhdr =
5324 (const struct vlan_ethhdr *)skb->data;
5326 protocol = vhdr->h_vlan_encapsulated_proto;
5328 protocol = skb->protocol;
5332 case cpu_to_be16(ETH_P_IP):
5333 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5334 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5336 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5337 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5339 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5341 case cpu_to_be16(ETH_P_IPV6):
5342 /* XXX what about other V6 headers?? */
5343 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5345 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5346 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5348 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5351 if (unlikely(net_ratelimit())) {
5352 DPRINTK(PROBE, WARNING,
5353 "partial checksum but proto=%x!\n",
5360 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5361 /* use index zero for tx checksum offload */
5362 context_desc->mss_l4len_idx = 0;
5364 tx_buffer_info->time_stamp = jiffies;
5365 tx_buffer_info->next_to_watch = i;
5368 if (i == tx_ring->count)
5370 tx_ring->next_to_use = i;
5378 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5379 struct ixgbe_ring *tx_ring,
5380 struct sk_buff *skb, u32 tx_flags,
5383 struct pci_dev *pdev = adapter->pdev;
5384 struct ixgbe_tx_buffer *tx_buffer_info;
5386 unsigned int total = skb->len;
5387 unsigned int offset = 0, size, count = 0, i;
5388 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5391 i = tx_ring->next_to_use;
5393 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5394 /* excluding fcoe_crc_eof for FCoE */
5395 total -= sizeof(struct fcoe_crc_eof);
5397 len = min(skb_headlen(skb), total);
5399 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5400 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5402 tx_buffer_info->length = size;
5403 tx_buffer_info->mapped_as_page = false;
5404 tx_buffer_info->dma = pci_map_single(pdev,
5406 size, PCI_DMA_TODEVICE);
5407 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5409 tx_buffer_info->time_stamp = jiffies;
5410 tx_buffer_info->next_to_watch = i;
5419 if (i == tx_ring->count)
5424 for (f = 0; f < nr_frags; f++) {
5425 struct skb_frag_struct *frag;
5427 frag = &skb_shinfo(skb)->frags[f];
5428 len = min((unsigned int)frag->size, total);
5429 offset = frag->page_offset;
5433 if (i == tx_ring->count)
5436 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5437 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5439 tx_buffer_info->length = size;
5440 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5444 tx_buffer_info->mapped_as_page = true;
5445 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5447 tx_buffer_info->time_stamp = jiffies;
5448 tx_buffer_info->next_to_watch = i;
5459 tx_ring->tx_buffer_info[i].skb = skb;
5460 tx_ring->tx_buffer_info[first].next_to_watch = i;
5465 dev_err(&pdev->dev, "TX DMA map failed\n");
5467 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5468 tx_buffer_info->dma = 0;
5469 tx_buffer_info->time_stamp = 0;
5470 tx_buffer_info->next_to_watch = 0;
5474 /* clear timestamp and dma mappings for remaining portion of packet */
5477 i += tx_ring->count;
5479 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5480 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5486 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5487 struct ixgbe_ring *tx_ring,
5488 int tx_flags, int count, u32 paylen, u8 hdr_len)
5490 union ixgbe_adv_tx_desc *tx_desc = NULL;
5491 struct ixgbe_tx_buffer *tx_buffer_info;
5492 u32 olinfo_status = 0, cmd_type_len = 0;
5494 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5496 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5498 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5500 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5501 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5503 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5504 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5506 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5507 IXGBE_ADVTXD_POPTS_SHIFT;
5509 /* use index 1 context for tso */
5510 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5511 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5512 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5513 IXGBE_ADVTXD_POPTS_SHIFT;
5515 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5516 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5517 IXGBE_ADVTXD_POPTS_SHIFT;
5519 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5520 olinfo_status |= IXGBE_ADVTXD_CC;
5521 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5522 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5523 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5526 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5528 i = tx_ring->next_to_use;
5530 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5531 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5532 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5533 tx_desc->read.cmd_type_len =
5534 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5535 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5537 if (i == tx_ring->count)
5541 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5544 * Force memory writes to complete before letting h/w
5545 * know there are new descriptors to fetch. (Only
5546 * applicable for weak-ordered memory model archs,
5551 tx_ring->next_to_use = i;
5552 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5555 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5556 int queue, u32 tx_flags)
5558 /* Right now, we support IPv4 only */
5559 struct ixgbe_atr_input atr_input;
5561 struct iphdr *iph = ip_hdr(skb);
5562 struct ethhdr *eth = (struct ethhdr *)skb->data;
5563 u16 vlan_id, src_port, dst_port, flex_bytes;
5564 u32 src_ipv4_addr, dst_ipv4_addr;
5567 /* check if we're UDP or TCP */
5568 if (iph->protocol == IPPROTO_TCP) {
5570 src_port = th->source;
5571 dst_port = th->dest;
5572 l4type |= IXGBE_ATR_L4TYPE_TCP;
5573 /* l4type IPv4 type is 0, no need to assign */
5575 /* Unsupported L4 header, just bail here */
5579 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5581 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5582 IXGBE_TX_FLAGS_VLAN_SHIFT;
5583 src_ipv4_addr = iph->saddr;
5584 dst_ipv4_addr = iph->daddr;
5585 flex_bytes = eth->h_proto;
5587 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5588 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5589 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5590 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5591 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5592 /* src and dst are inverted, think how the receiver sees them */
5593 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5594 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5596 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5597 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5600 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5601 struct ixgbe_ring *tx_ring, int size)
5603 netif_stop_subqueue(netdev, tx_ring->queue_index);
5604 /* Herbert's original patch had:
5605 * smp_mb__after_netif_stop_queue();
5606 * but since that doesn't exist yet, just open code it. */
5609 /* We need to check again in a case another CPU has just
5610 * made room available. */
5611 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5614 /* A reprieve! - use start_queue because it doesn't call schedule */
5615 netif_start_subqueue(netdev, tx_ring->queue_index);
5616 ++tx_ring->restart_queue;
5620 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5621 struct ixgbe_ring *tx_ring, int size)
5623 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5625 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5628 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5630 struct ixgbe_adapter *adapter = netdev_priv(dev);
5631 int txq = smp_processor_id();
5633 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5634 while (unlikely(txq >= dev->real_num_tx_queues))
5635 txq -= dev->real_num_tx_queues;
5640 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5641 (skb->protocol == htons(ETH_P_FCOE))) {
5642 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5643 txq += adapter->ring_feature[RING_F_FCOE].mask;
5647 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5648 if (skb->priority == TC_PRIO_CONTROL)
5649 txq = adapter->ring_feature[RING_F_DCB].indices-1;
5651 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5656 return skb_tx_hash(dev, skb);
5659 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5660 struct net_device *netdev)
5662 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5663 struct ixgbe_ring *tx_ring;
5664 struct netdev_queue *txq;
5666 unsigned int tx_flags = 0;
5672 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5673 tx_flags |= vlan_tx_tag_get(skb);
5674 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5675 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5676 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5678 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5679 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5680 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5681 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5682 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5683 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5686 tx_ring = adapter->tx_ring[skb->queue_mapping];
5688 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5689 (skb->protocol == htons(ETH_P_FCOE))) {
5690 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5692 #ifdef CONFIG_IXGBE_DCB
5693 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5694 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5695 tx_flags |= ((adapter->fcoe.up << 13)
5696 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5700 /* four things can cause us to need a context descriptor */
5701 if (skb_is_gso(skb) ||
5702 (skb->ip_summed == CHECKSUM_PARTIAL) ||
5703 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5704 (tx_flags & IXGBE_TX_FLAGS_FCOE))
5707 count += TXD_USE_COUNT(skb_headlen(skb));
5708 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5709 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5711 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5713 return NETDEV_TX_BUSY;
5716 first = tx_ring->next_to_use;
5717 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5719 /* setup tx offload for FCoE */
5720 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5722 dev_kfree_skb_any(skb);
5723 return NETDEV_TX_OK;
5726 tx_flags |= IXGBE_TX_FLAGS_FSO;
5727 #endif /* IXGBE_FCOE */
5729 if (skb->protocol == htons(ETH_P_IP))
5730 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5731 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5733 dev_kfree_skb_any(skb);
5734 return NETDEV_TX_OK;
5738 tx_flags |= IXGBE_TX_FLAGS_TSO;
5739 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5740 (skb->ip_summed == CHECKSUM_PARTIAL))
5741 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5744 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5746 /* add the ATR filter if ATR is on */
5747 if (tx_ring->atr_sample_rate) {
5748 ++tx_ring->atr_count;
5749 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5750 test_bit(__IXGBE_FDIR_INIT_DONE,
5751 &tx_ring->reinit_state)) {
5752 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5754 tx_ring->atr_count = 0;
5757 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5758 txq->tx_bytes += skb->len;
5760 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5762 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5765 dev_kfree_skb_any(skb);
5766 tx_ring->tx_buffer_info[first].time_stamp = 0;
5767 tx_ring->next_to_use = first;
5770 return NETDEV_TX_OK;
5774 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5775 * @netdev: network interface device structure
5776 * @p: pointer to an address structure
5778 * Returns 0 on success, negative on failure
5780 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5782 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5783 struct ixgbe_hw *hw = &adapter->hw;
5784 struct sockaddr *addr = p;
5786 if (!is_valid_ether_addr(addr->sa_data))
5787 return -EADDRNOTAVAIL;
5789 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5790 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5792 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5799 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5801 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5802 struct ixgbe_hw *hw = &adapter->hw;
5806 if (prtad != hw->phy.mdio.prtad)
5808 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5814 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5815 u16 addr, u16 value)
5817 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5818 struct ixgbe_hw *hw = &adapter->hw;
5820 if (prtad != hw->phy.mdio.prtad)
5822 return hw->phy.ops.write_reg(hw, addr, devad, value);
5825 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5827 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5829 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5833 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5835 * @netdev: network interface device structure
5837 * Returns non-zero on failure
5839 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5842 struct ixgbe_adapter *adapter = netdev_priv(dev);
5843 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5845 if (is_valid_ether_addr(mac->san_addr)) {
5847 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5854 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5856 * @netdev: network interface device structure
5858 * Returns non-zero on failure
5860 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5863 struct ixgbe_adapter *adapter = netdev_priv(dev);
5864 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5866 if (is_valid_ether_addr(mac->san_addr)) {
5868 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5874 #ifdef CONFIG_NET_POLL_CONTROLLER
5876 * Polling 'interrupt' - used by things like netconsole to send skbs
5877 * without having to re-enable interrupts. It's not called while
5878 * the interrupt routine is executing.
5880 static void ixgbe_netpoll(struct net_device *netdev)
5882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5885 /* if interface is down do nothing */
5886 if (test_bit(__IXGBE_DOWN, &adapter->state))
5889 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5890 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5891 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5892 for (i = 0; i < num_q_vectors; i++) {
5893 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5894 ixgbe_msix_clean_many(0, q_vector);
5897 ixgbe_intr(adapter->pdev->irq, netdev);
5899 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5903 static const struct net_device_ops ixgbe_netdev_ops = {
5904 .ndo_open = ixgbe_open,
5905 .ndo_stop = ixgbe_close,
5906 .ndo_start_xmit = ixgbe_xmit_frame,
5907 .ndo_select_queue = ixgbe_select_queue,
5908 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5909 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5910 .ndo_validate_addr = eth_validate_addr,
5911 .ndo_set_mac_address = ixgbe_set_mac,
5912 .ndo_change_mtu = ixgbe_change_mtu,
5913 .ndo_tx_timeout = ixgbe_tx_timeout,
5914 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5915 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5916 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5917 .ndo_do_ioctl = ixgbe_ioctl,
5918 #ifdef CONFIG_NET_POLL_CONTROLLER
5919 .ndo_poll_controller = ixgbe_netpoll,
5922 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5923 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5924 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5925 .ndo_fcoe_disable = ixgbe_fcoe_disable,
5926 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5927 #endif /* IXGBE_FCOE */
5930 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5931 const struct ixgbe_info *ii)
5933 #ifdef CONFIG_PCI_IOV
5934 struct ixgbe_hw *hw = &adapter->hw;
5937 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5940 /* The 82599 supports up to 64 VFs per physical function
5941 * but this implementation limits allocation to 63 so that
5942 * basic networking resources are still available to the
5945 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5946 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5947 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5950 "Failed to enable PCI sriov: %d\n", err);
5953 /* If call to enable VFs succeeded then allocate memory
5954 * for per VF control structures.
5957 kcalloc(adapter->num_vfs,
5958 sizeof(struct vf_data_storage), GFP_KERNEL);
5959 if (adapter->vfinfo) {
5960 /* Now that we're sure SR-IOV is enabled
5961 * and memory allocated set up the mailbox parameters
5963 ixgbe_init_mbx_params_pf(hw);
5964 memcpy(&hw->mbx.ops, ii->mbx_ops,
5965 sizeof(hw->mbx.ops));
5967 /* Disable RSC when in SR-IOV mode */
5968 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
5969 IXGBE_FLAG2_RSC_ENABLED);
5975 "Unable to allocate memory for VF "
5976 "Data Storage - SRIOV disabled\n");
5977 pci_disable_sriov(adapter->pdev);
5980 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
5981 adapter->num_vfs = 0;
5982 #endif /* CONFIG_PCI_IOV */
5986 * ixgbe_probe - Device Initialization Routine
5987 * @pdev: PCI device information struct
5988 * @ent: entry in ixgbe_pci_tbl
5990 * Returns 0 on success, negative on failure
5992 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5993 * The OS initialization, configuring of the adapter private structure,
5994 * and a hardware reset occur.
5996 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5997 const struct pci_device_id *ent)
5999 struct net_device *netdev;
6000 struct ixgbe_adapter *adapter = NULL;
6001 struct ixgbe_hw *hw;
6002 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6003 static int cards_found;
6004 int i, err, pci_using_dac;
6005 unsigned int indices = num_possible_cpus();
6011 err = pci_enable_device_mem(pdev);
6015 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
6016 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
6019 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6021 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6023 dev_err(&pdev->dev, "No usable DMA "
6024 "configuration, aborting\n");
6031 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6032 IORESOURCE_MEM), ixgbe_driver_name);
6035 "pci_request_selected_regions failed 0x%x\n", err);
6039 pci_enable_pcie_error_reporting(pdev);
6041 pci_set_master(pdev);
6042 pci_save_state(pdev);
6044 if (ii->mac == ixgbe_mac_82598EB)
6045 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6047 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6049 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6051 indices += min_t(unsigned int, num_possible_cpus(),
6052 IXGBE_MAX_FCOE_INDICES);
6054 indices = min_t(unsigned int, indices, MAX_TX_QUEUES);
6055 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6058 goto err_alloc_etherdev;
6061 SET_NETDEV_DEV(netdev, &pdev->dev);
6063 pci_set_drvdata(pdev, netdev);
6064 adapter = netdev_priv(netdev);
6066 adapter->netdev = netdev;
6067 adapter->pdev = pdev;
6070 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6072 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6073 pci_resource_len(pdev, 0));
6079 for (i = 1; i <= 5; i++) {
6080 if (pci_resource_len(pdev, i) == 0)
6084 netdev->netdev_ops = &ixgbe_netdev_ops;
6085 ixgbe_set_ethtool_ops(netdev);
6086 netdev->watchdog_timeo = 5 * HZ;
6087 strcpy(netdev->name, pci_name(pdev));
6089 adapter->bd_number = cards_found;
6092 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6093 hw->mac.type = ii->mac;
6096 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6097 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6098 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6099 if (!(eec & (1 << 8)))
6100 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6103 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6104 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6105 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6106 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6107 hw->phy.mdio.mmds = 0;
6108 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6109 hw->phy.mdio.dev = netdev;
6110 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6111 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6113 /* set up this timer and work struct before calling get_invariants
6114 * which might start the timer
6116 init_timer(&adapter->sfp_timer);
6117 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6118 adapter->sfp_timer.data = (unsigned long) adapter;
6120 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6122 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6123 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6125 /* a new SFP+ module arrival, called from GPI SDP2 context */
6126 INIT_WORK(&adapter->sfp_config_module_task,
6127 ixgbe_sfp_config_module_task);
6129 ii->get_invariants(hw);
6131 /* setup the private structure */
6132 err = ixgbe_sw_init(adapter);
6136 /* Make it possible the adapter to be woken up via WOL */
6137 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6138 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6141 * If there is a fan on this device and it has failed log the
6144 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6145 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6146 if (esdp & IXGBE_ESDP_SDP1)
6147 DPRINTK(PROBE, CRIT,
6148 "Fan has stopped, replace the adapter\n");
6151 /* reset_hw fills in the perm_addr as well */
6152 err = hw->mac.ops.reset_hw(hw);
6153 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6154 hw->mac.type == ixgbe_mac_82598EB) {
6156 * Start a kernel thread to watch for a module to arrive.
6157 * Only do this for 82598, since 82599 will generate
6158 * interrupts on module arrival.
6160 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6161 mod_timer(&adapter->sfp_timer,
6162 round_jiffies(jiffies + (2 * HZ)));
6164 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6165 dev_err(&adapter->pdev->dev, "failed to initialize because "
6166 "an unsupported SFP+ module type was detected.\n"
6167 "Reload the driver after installing a supported "
6171 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6175 ixgbe_probe_vf(adapter, ii);
6177 netdev->features = NETIF_F_SG |
6179 NETIF_F_HW_VLAN_TX |
6180 NETIF_F_HW_VLAN_RX |
6181 NETIF_F_HW_VLAN_FILTER;
6183 netdev->features |= NETIF_F_IPV6_CSUM;
6184 netdev->features |= NETIF_F_TSO;
6185 netdev->features |= NETIF_F_TSO6;
6186 netdev->features |= NETIF_F_GRO;
6188 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6189 netdev->features |= NETIF_F_SCTP_CSUM;
6191 netdev->vlan_features |= NETIF_F_TSO;
6192 netdev->vlan_features |= NETIF_F_TSO6;
6193 netdev->vlan_features |= NETIF_F_IP_CSUM;
6194 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6195 netdev->vlan_features |= NETIF_F_SG;
6197 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6198 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6199 IXGBE_FLAG_DCB_ENABLED);
6200 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6201 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6203 #ifdef CONFIG_IXGBE_DCB
6204 netdev->dcbnl_ops = &dcbnl_ops;
6208 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6209 if (hw->mac.ops.get_device_caps) {
6210 hw->mac.ops.get_device_caps(hw, &device_caps);
6211 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6212 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6215 #endif /* IXGBE_FCOE */
6217 netdev->features |= NETIF_F_HIGHDMA;
6219 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6220 netdev->features |= NETIF_F_LRO;
6222 /* make sure the EEPROM is good */
6223 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6224 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6229 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6230 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6232 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6233 dev_err(&pdev->dev, "invalid MAC address\n");
6238 init_timer(&adapter->watchdog_timer);
6239 adapter->watchdog_timer.function = &ixgbe_watchdog;
6240 adapter->watchdog_timer.data = (unsigned long)adapter;
6242 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6243 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6245 err = ixgbe_init_interrupt_scheme(adapter);
6249 switch (pdev->device) {
6250 case IXGBE_DEV_ID_82599_KX4:
6251 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6252 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6258 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6260 /* pick up the PCI bus settings for reporting later */
6261 hw->mac.ops.get_bus_info(hw);
6263 /* print bus type/speed/width info */
6264 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
6265 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6266 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6267 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6268 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6269 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6272 ixgbe_read_pba_num_generic(hw, &part_num);
6273 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6274 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6275 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6276 (part_num >> 8), (part_num & 0xff));
6278 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6279 hw->mac.type, hw->phy.type,
6280 (part_num >> 8), (part_num & 0xff));
6282 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6283 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
6284 "this card is not sufficient for optimal "
6286 dev_warn(&pdev->dev, "For optimal performance a x8 "
6287 "PCI-Express slot is required.\n");
6290 /* save off EEPROM version number */
6291 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6293 /* reset the hardware with the new settings */
6294 err = hw->mac.ops.start_hw(hw);
6296 if (err == IXGBE_ERR_EEPROM_VERSION) {
6297 /* We are running on a pre-production device, log a warning */
6298 dev_warn(&pdev->dev, "This device is a pre-production "
6299 "adapter/LOM. Please be aware there may be issues "
6300 "associated with your hardware. If you are "
6301 "experiencing problems please contact your Intel or "
6302 "hardware representative who provided you with this "
6305 strcpy(netdev->name, "eth%d");
6306 err = register_netdev(netdev);
6310 /* carrier off reporting is important to ethtool even BEFORE open */
6311 netif_carrier_off(netdev);
6313 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6314 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6315 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6317 #ifdef CONFIG_IXGBE_DCA
6318 if (dca_add_requester(&pdev->dev) == 0) {
6319 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6320 ixgbe_setup_dca(adapter);
6323 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6324 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6326 for (i = 0; i < adapter->num_vfs; i++)
6327 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6330 /* add san mac addr to netdev */
6331 ixgbe_add_sanmac_netdev(netdev);
6333 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6338 ixgbe_release_hw_control(adapter);
6339 ixgbe_clear_interrupt_scheme(adapter);
6342 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6343 ixgbe_disable_sriov(adapter);
6344 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6345 del_timer_sync(&adapter->sfp_timer);
6346 cancel_work_sync(&adapter->sfp_task);
6347 cancel_work_sync(&adapter->multispeed_fiber_task);
6348 cancel_work_sync(&adapter->sfp_config_module_task);
6349 iounmap(hw->hw_addr);
6351 free_netdev(netdev);
6353 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6357 pci_disable_device(pdev);
6362 * ixgbe_remove - Device Removal Routine
6363 * @pdev: PCI device information struct
6365 * ixgbe_remove is called by the PCI subsystem to alert the driver
6366 * that it should release a PCI device. The could be caused by a
6367 * Hot-Plug event, or because the driver is going to be removed from
6370 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6372 struct net_device *netdev = pci_get_drvdata(pdev);
6373 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6375 set_bit(__IXGBE_DOWN, &adapter->state);
6376 /* clear the module not found bit to make sure the worker won't
6379 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6380 del_timer_sync(&adapter->watchdog_timer);
6382 del_timer_sync(&adapter->sfp_timer);
6383 cancel_work_sync(&adapter->watchdog_task);
6384 cancel_work_sync(&adapter->sfp_task);
6385 if (adapter->hw.phy.multispeed_fiber) {
6386 struct ixgbe_hw *hw = &adapter->hw;
6388 * Restart clause 37 autoneg, disable and re-enable
6389 * the tx laser, to clear & alert the link partner
6390 * that it needs to restart autotry
6392 hw->mac.autotry_restart = true;
6393 hw->mac.ops.flap_tx_laser(hw);
6395 cancel_work_sync(&adapter->multispeed_fiber_task);
6396 cancel_work_sync(&adapter->sfp_config_module_task);
6397 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6398 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6399 cancel_work_sync(&adapter->fdir_reinit_task);
6400 flush_scheduled_work();
6402 #ifdef CONFIG_IXGBE_DCA
6403 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6404 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6405 dca_remove_requester(&pdev->dev);
6406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6411 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6412 ixgbe_cleanup_fcoe(adapter);
6414 #endif /* IXGBE_FCOE */
6416 /* remove the added san mac */
6417 ixgbe_del_sanmac_netdev(netdev);
6419 if (netdev->reg_state == NETREG_REGISTERED)
6420 unregister_netdev(netdev);
6422 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6423 ixgbe_disable_sriov(adapter);
6425 ixgbe_clear_interrupt_scheme(adapter);
6427 ixgbe_release_hw_control(adapter);
6429 iounmap(adapter->hw.hw_addr);
6430 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6433 DPRINTK(PROBE, INFO, "complete\n");
6435 free_netdev(netdev);
6437 pci_disable_pcie_error_reporting(pdev);
6439 pci_disable_device(pdev);
6443 * ixgbe_io_error_detected - called when PCI error is detected
6444 * @pdev: Pointer to PCI device
6445 * @state: The current pci connection state
6447 * This function is called after a PCI bus error affecting
6448 * this device has been detected.
6450 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6451 pci_channel_state_t state)
6453 struct net_device *netdev = pci_get_drvdata(pdev);
6454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6456 netif_device_detach(netdev);
6458 if (state == pci_channel_io_perm_failure)
6459 return PCI_ERS_RESULT_DISCONNECT;
6461 if (netif_running(netdev))
6462 ixgbe_down(adapter);
6463 pci_disable_device(pdev);
6465 /* Request a slot reset. */
6466 return PCI_ERS_RESULT_NEED_RESET;
6470 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6471 * @pdev: Pointer to PCI device
6473 * Restart the card from scratch, as if from a cold-boot.
6475 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6477 struct net_device *netdev = pci_get_drvdata(pdev);
6478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6479 pci_ers_result_t result;
6482 if (pci_enable_device_mem(pdev)) {
6484 "Cannot re-enable PCI device after reset.\n");
6485 result = PCI_ERS_RESULT_DISCONNECT;
6487 pci_set_master(pdev);
6488 pci_restore_state(pdev);
6489 pci_save_state(pdev);
6491 pci_wake_from_d3(pdev, false);
6493 ixgbe_reset(adapter);
6494 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6495 result = PCI_ERS_RESULT_RECOVERED;
6498 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6501 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6502 /* non-fatal, continue */
6509 * ixgbe_io_resume - called when traffic can start flowing again.
6510 * @pdev: Pointer to PCI device
6512 * This callback is called when the error recovery driver tells us that
6513 * its OK to resume normal operation.
6515 static void ixgbe_io_resume(struct pci_dev *pdev)
6517 struct net_device *netdev = pci_get_drvdata(pdev);
6518 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6520 if (netif_running(netdev)) {
6521 if (ixgbe_up(adapter)) {
6522 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6527 netif_device_attach(netdev);
6530 static struct pci_error_handlers ixgbe_err_handler = {
6531 .error_detected = ixgbe_io_error_detected,
6532 .slot_reset = ixgbe_io_slot_reset,
6533 .resume = ixgbe_io_resume,
6536 static struct pci_driver ixgbe_driver = {
6537 .name = ixgbe_driver_name,
6538 .id_table = ixgbe_pci_tbl,
6539 .probe = ixgbe_probe,
6540 .remove = __devexit_p(ixgbe_remove),
6542 .suspend = ixgbe_suspend,
6543 .resume = ixgbe_resume,
6545 .shutdown = ixgbe_shutdown,
6546 .err_handler = &ixgbe_err_handler
6550 * ixgbe_init_module - Driver Registration Routine
6552 * ixgbe_init_module is the first routine called when the driver is
6553 * loaded. All it does is register with the PCI subsystem.
6555 static int __init ixgbe_init_module(void)
6558 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6559 ixgbe_driver_string, ixgbe_driver_version);
6561 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6563 #ifdef CONFIG_IXGBE_DCA
6564 dca_register_notify(&dca_notifier);
6567 ret = pci_register_driver(&ixgbe_driver);
6571 module_init(ixgbe_init_module);
6574 * ixgbe_exit_module - Driver Exit Cleanup Routine
6576 * ixgbe_exit_module is called just before the driver is removed
6579 static void __exit ixgbe_exit_module(void)
6581 #ifdef CONFIG_IXGBE_DCA
6582 dca_unregister_notify(&dca_notifier);
6584 pci_unregister_driver(&ixgbe_driver);
6587 #ifdef CONFIG_IXGBE_DCA
6588 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6593 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6594 __ixgbe_notify_dca);
6596 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6599 #endif /* CONFIG_IXGBE_DCA */
6602 * ixgbe_get_hw_dev_name - return device name string
6603 * used by hardware layer to print debugging information
6605 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6607 struct ixgbe_adapter *adapter = hw->back;
6608 return adapter->netdev->name;
6612 module_exit(ixgbe_exit_module);