1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
46 #include "ixgbe_common.h"
48 char ixgbe_driver_name[] = "ixgbe";
49 static const char ixgbe_driver_string[] =
50 "Intel(R) 10 Gigabit PCI Express Network Driver";
52 #define DRV_VERSION "2.0.34-k2"
53 const char ixgbe_driver_version[] = DRV_VERSION;
54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
57 [board_82598] = &ixgbe_82598_info,
58 [board_82599] = &ixgbe_82599_info,
61 /* ixgbe_pci_tbl - PCI Device ID Table
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
69 static struct pci_device_id ixgbe_pci_tbl[] = {
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 /* required last entry */
102 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
104 #ifdef CONFIG_IXGBE_DCA
105 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
107 static struct notifier_block dca_notifier = {
108 .notifier_call = ixgbe_notify_dca,
114 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
115 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
116 MODULE_LICENSE("GPL");
117 MODULE_VERSION(DRV_VERSION);
119 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
121 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
125 /* Let firmware take over control of h/w */
126 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
128 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
131 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
135 /* Let firmware know the driver has taken over */
136 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
137 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
138 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
142 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
143 * @adapter: pointer to adapter struct
144 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
145 * @queue: queue to map the corresponding interrupt to
146 * @msix_vector: the vector to map to the corresponding queue
149 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
150 u8 queue, u8 msix_vector)
153 struct ixgbe_hw *hw = &adapter->hw;
154 switch (hw->mac.type) {
155 case ixgbe_mac_82598EB:
156 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
159 index = (((direction * 64) + queue) >> 2) & 0x1F;
160 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
161 ivar &= ~(0xFF << (8 * (queue & 0x3)));
162 ivar |= (msix_vector << (8 * (queue & 0x3)));
163 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
165 case ixgbe_mac_82599EB:
166 if (direction == -1) {
168 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
169 index = ((queue & 1) * 8);
170 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
171 ivar &= ~(0xFF << index);
172 ivar |= (msix_vector << index);
173 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
176 /* tx or rx causes */
177 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
178 index = ((16 * (queue & 1)) + (8 * direction));
179 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
180 ivar &= ~(0xFF << index);
181 ivar |= (msix_vector << index);
182 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
190 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
195 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
196 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
197 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
199 mask = (qmask & 0xFFFFFFFF);
200 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
201 mask = (qmask >> 32);
202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
206 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
207 struct ixgbe_tx_buffer
210 tx_buffer_info->dma = 0;
211 if (tx_buffer_info->skb) {
212 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
214 dev_kfree_skb_any(tx_buffer_info->skb);
215 tx_buffer_info->skb = NULL;
217 tx_buffer_info->time_stamp = 0;
218 /* tx_buffer_info must be completely set up in the transmit path */
221 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
222 struct ixgbe_ring *tx_ring,
225 struct ixgbe_hw *hw = &adapter->hw;
227 /* Detect a transmit hang in hardware, this serializes the
228 * check with the clearing of time_stamp and movement of eop */
229 adapter->detect_tx_hung = false;
230 if (tx_ring->tx_buffer_info[eop].time_stamp &&
231 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
232 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
233 /* detected Tx unit hang */
234 union ixgbe_adv_tx_desc *tx_desc;
235 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
236 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
238 " TDH, TDT <%x>, <%x>\n"
239 " next_to_use <%x>\n"
240 " next_to_clean <%x>\n"
241 "tx_buffer_info[next_to_clean]\n"
242 " time_stamp <%lx>\n"
244 tx_ring->queue_index,
245 IXGBE_READ_REG(hw, tx_ring->head),
246 IXGBE_READ_REG(hw, tx_ring->tail),
247 tx_ring->next_to_use, eop,
248 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
255 #define IXGBE_MAX_TXD_PWR 14
256 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
258 /* Tx Descriptors needed, worst case */
259 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
260 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
261 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
262 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
264 static void ixgbe_tx_timeout(struct net_device *netdev);
267 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
268 * @q_vector: structure containing interrupt and ring information
269 * @tx_ring: tx ring to clean
271 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
272 struct ixgbe_ring *tx_ring)
274 struct ixgbe_adapter *adapter = q_vector->adapter;
275 struct net_device *netdev = adapter->netdev;
276 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
277 struct ixgbe_tx_buffer *tx_buffer_info;
278 unsigned int i, eop, count = 0;
279 unsigned int total_bytes = 0, total_packets = 0;
281 i = tx_ring->next_to_clean;
282 eop = tx_ring->tx_buffer_info[i].next_to_watch;
283 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
285 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
286 (count < tx_ring->work_limit)) {
287 bool cleaned = false;
288 for ( ; !cleaned; count++) {
290 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
291 tx_buffer_info = &tx_ring->tx_buffer_info[i];
292 cleaned = (i == eop);
293 skb = tx_buffer_info->skb;
295 if (cleaned && skb) {
296 unsigned int segs, bytecount;
297 unsigned int hlen = skb_headlen(skb);
299 /* gso_segs is currently only valid for tcp */
300 segs = skb_shinfo(skb)->gso_segs ?: 1;
302 /* adjust for FCoE Sequence Offload */
303 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
304 && (skb->protocol == htons(ETH_P_FCOE)) &&
306 hlen = skb_transport_offset(skb) +
307 sizeof(struct fc_frame_header) +
308 sizeof(struct fcoe_crc_eof);
309 segs = DIV_ROUND_UP(skb->len - hlen,
310 skb_shinfo(skb)->gso_size);
312 #endif /* IXGBE_FCOE */
313 /* multiply data chunks by size of headers */
314 bytecount = ((segs - 1) * hlen) + skb->len;
315 total_packets += segs;
316 total_bytes += bytecount;
319 ixgbe_unmap_and_free_tx_resource(adapter,
322 tx_desc->wb.status = 0;
325 if (i == tx_ring->count)
329 eop = tx_ring->tx_buffer_info[i].next_to_watch;
330 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
333 tx_ring->next_to_clean = i;
335 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
336 if (unlikely(count && netif_carrier_ok(netdev) &&
337 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
338 /* Make sure that anybody stopping the queue after this
339 * sees the new next_to_clean.
342 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
343 !test_bit(__IXGBE_DOWN, &adapter->state)) {
344 netif_wake_subqueue(netdev, tx_ring->queue_index);
345 ++adapter->restart_queue;
349 if (adapter->detect_tx_hung) {
350 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
351 /* schedule immediate reset if we believe we hung */
353 "tx hang %d detected, resetting adapter\n",
354 adapter->tx_timeout_count + 1);
355 ixgbe_tx_timeout(adapter->netdev);
359 /* re-arm the interrupt */
360 if (count >= tx_ring->work_limit)
361 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
363 tx_ring->total_bytes += total_bytes;
364 tx_ring->total_packets += total_packets;
365 tx_ring->stats.packets += total_packets;
366 tx_ring->stats.bytes += total_bytes;
367 adapter->net_stats.tx_bytes += total_bytes;
368 adapter->net_stats.tx_packets += total_packets;
369 return (count < tx_ring->work_limit);
372 #ifdef CONFIG_IXGBE_DCA
373 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
374 struct ixgbe_ring *rx_ring)
378 int q = rx_ring - adapter->rx_ring;
380 if (rx_ring->cpu != cpu) {
381 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
382 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
383 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
384 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
385 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
386 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
387 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
388 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
390 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
391 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
392 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
393 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
394 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
401 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
402 struct ixgbe_ring *tx_ring)
406 int q = tx_ring - adapter->tx_ring;
408 if (tx_ring->cpu != cpu) {
409 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
410 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
411 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
412 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
413 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
414 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
415 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
416 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
418 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
419 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
425 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
429 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
432 /* always use CB2 mode, difference is masked in the CB driver */
433 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
435 for (i = 0; i < adapter->num_tx_queues; i++) {
436 adapter->tx_ring[i].cpu = -1;
437 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
439 for (i = 0; i < adapter->num_rx_queues; i++) {
440 adapter->rx_ring[i].cpu = -1;
441 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
445 static int __ixgbe_notify_dca(struct device *dev, void *data)
447 struct net_device *netdev = dev_get_drvdata(dev);
448 struct ixgbe_adapter *adapter = netdev_priv(netdev);
449 unsigned long event = *(unsigned long *)data;
452 case DCA_PROVIDER_ADD:
453 /* if we're already enabled, don't do it again */
454 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
456 if (dca_add_requester(dev) == 0) {
457 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
458 ixgbe_setup_dca(adapter);
461 /* Fall Through since DCA is disabled. */
462 case DCA_PROVIDER_REMOVE:
463 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
464 dca_remove_requester(dev);
465 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
474 #endif /* CONFIG_IXGBE_DCA */
476 * ixgbe_receive_skb - Send a completed packet up the stack
477 * @adapter: board private structure
478 * @skb: packet to send up
479 * @status: hardware indication of status of receive
480 * @rx_ring: rx descriptor ring (for a specific queue) to setup
481 * @rx_desc: rx descriptor
483 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
484 struct sk_buff *skb, u8 status,
485 struct ixgbe_ring *ring,
486 union ixgbe_adv_rx_desc *rx_desc)
488 struct ixgbe_adapter *adapter = q_vector->adapter;
489 struct napi_struct *napi = &q_vector->napi;
490 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
491 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
493 skb_record_rx_queue(skb, ring->queue_index);
494 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
495 if (adapter->vlgrp && is_vlan && (tag != 0))
496 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
498 napi_gro_receive(napi, skb);
500 if (adapter->vlgrp && is_vlan && (tag != 0))
501 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
508 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
509 * @adapter: address of board private structure
510 * @status_err: hardware indication of status of receive
511 * @skb: skb currently being received and modified
513 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
514 u32 status_err, struct sk_buff *skb)
516 skb->ip_summed = CHECKSUM_NONE;
518 /* Rx csum disabled */
519 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
522 /* if IP and error */
523 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
524 (status_err & IXGBE_RXDADV_ERR_IPE)) {
525 adapter->hw_csum_rx_error++;
529 if (!(status_err & IXGBE_RXD_STAT_L4CS))
532 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
533 adapter->hw_csum_rx_error++;
537 /* It must be a TCP or UDP packet with a valid checksum */
538 skb->ip_summed = CHECKSUM_UNNECESSARY;
539 adapter->hw_csum_rx_good++;
542 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
543 struct ixgbe_ring *rx_ring, u32 val)
546 * Force memory writes to complete before letting h/w
547 * know there are new descriptors to fetch. (Only
548 * applicable for weak-ordered memory model archs,
552 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
556 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
557 * @adapter: address of board private structure
559 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
560 struct ixgbe_ring *rx_ring,
563 struct pci_dev *pdev = adapter->pdev;
564 union ixgbe_adv_rx_desc *rx_desc;
565 struct ixgbe_rx_buffer *bi;
568 i = rx_ring->next_to_use;
569 bi = &rx_ring->rx_buffer_info[i];
571 while (cleaned_count--) {
572 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
575 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
577 bi->page = alloc_page(GFP_ATOMIC);
579 adapter->alloc_rx_page_failed++;
584 /* use a half page if we're re-using */
585 bi->page_offset ^= (PAGE_SIZE / 2);
588 bi->page_dma = pci_map_page(pdev, bi->page,
596 skb = netdev_alloc_skb(adapter->netdev,
597 (rx_ring->rx_buf_len +
601 adapter->alloc_rx_buff_failed++;
606 * Make buffer alignment 2 beyond a 16 byte boundary
607 * this will result in a 16 byte aligned IP header after
608 * the 14 byte MAC header is removed
610 skb_reserve(skb, NET_IP_ALIGN);
613 bi->dma = pci_map_single(pdev, skb->data,
617 /* Refresh the desc even if buffer_addrs didn't change because
618 * each write-back erases this info. */
619 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
620 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
621 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
623 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
627 if (i == rx_ring->count)
629 bi = &rx_ring->rx_buffer_info[i];
633 if (rx_ring->next_to_use != i) {
634 rx_ring->next_to_use = i;
636 i = (rx_ring->count - 1);
638 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
642 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
644 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
647 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
649 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
652 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
654 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
655 IXGBE_RXDADV_RSCCNT_MASK) >>
656 IXGBE_RXDADV_RSCCNT_SHIFT;
660 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
661 * @skb: pointer to the last skb in the rsc queue
663 * This function changes a queue full of hw rsc buffers into a completed
664 * packet. It uses the ->prev pointers to find the first packet and then
665 * turns it into the frag list owner.
667 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
669 unsigned int frag_list_size = 0;
672 struct sk_buff *prev = skb->prev;
673 frag_list_size += skb->len;
678 skb_shinfo(skb)->frag_list = skb->next;
680 skb->len += frag_list_size;
681 skb->data_len += frag_list_size;
682 skb->truesize += frag_list_size;
686 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
687 struct ixgbe_ring *rx_ring,
688 int *work_done, int work_to_do)
690 struct ixgbe_adapter *adapter = q_vector->adapter;
691 struct pci_dev *pdev = adapter->pdev;
692 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
693 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
695 unsigned int i, rsc_count = 0;
698 bool cleaned = false;
699 int cleaned_count = 0;
700 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
703 #endif /* IXGBE_FCOE */
705 i = rx_ring->next_to_clean;
706 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
707 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
708 rx_buffer_info = &rx_ring->rx_buffer_info[i];
710 while (staterr & IXGBE_RXD_STAT_DD) {
712 if (*work_done >= work_to_do)
716 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
717 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
718 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
719 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
720 if (hdr_info & IXGBE_RXDADV_SPH)
721 adapter->rx_hdr_split++;
722 if (len > IXGBE_RX_HDR_SIZE)
723 len = IXGBE_RX_HDR_SIZE;
724 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
726 len = le16_to_cpu(rx_desc->wb.upper.length);
730 skb = rx_buffer_info->skb;
731 prefetch(skb->data - NET_IP_ALIGN);
732 rx_buffer_info->skb = NULL;
734 if (rx_buffer_info->dma) {
735 pci_unmap_single(pdev, rx_buffer_info->dma,
738 rx_buffer_info->dma = 0;
743 pci_unmap_page(pdev, rx_buffer_info->page_dma,
744 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
745 rx_buffer_info->page_dma = 0;
746 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
747 rx_buffer_info->page,
748 rx_buffer_info->page_offset,
751 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
752 (page_count(rx_buffer_info->page) != 1))
753 rx_buffer_info->page = NULL;
755 get_page(rx_buffer_info->page);
757 skb->len += upper_len;
758 skb->data_len += upper_len;
759 skb->truesize += upper_len;
763 if (i == rx_ring->count)
766 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
770 if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)
771 rsc_count = ixgbe_get_rsc_count(rx_desc);
774 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
775 IXGBE_RXDADV_NEXTP_SHIFT;
776 next_buffer = &rx_ring->rx_buffer_info[nextp];
777 rx_ring->rsc_count += (rsc_count - 1);
779 next_buffer = &rx_ring->rx_buffer_info[i];
782 if (staterr & IXGBE_RXD_STAT_EOP) {
784 skb = ixgbe_transform_rsc_queue(skb);
785 rx_ring->stats.packets++;
786 rx_ring->stats.bytes += skb->len;
788 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
789 rx_buffer_info->skb = next_buffer->skb;
790 rx_buffer_info->dma = next_buffer->dma;
791 next_buffer->skb = skb;
792 next_buffer->dma = 0;
794 skb->next = next_buffer->skb;
795 skb->next->prev = skb;
797 adapter->non_eop_descs++;
801 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
802 dev_kfree_skb_irq(skb);
806 ixgbe_rx_checksum(adapter, staterr, skb);
808 /* probably a little skewed due to removing CRC */
809 total_rx_bytes += skb->len;
812 skb->protocol = eth_type_trans(skb, adapter->netdev);
814 /* if ddp, not passing to ULD unless for FCP_RSP or error */
815 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
816 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
820 #endif /* IXGBE_FCOE */
821 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
824 rx_desc->wb.upper.status_error = 0;
826 /* return some buffers to hardware, one at a time is too slow */
827 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
828 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
832 /* use prefetched values */
834 rx_buffer_info = &rx_ring->rx_buffer_info[i];
836 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
839 rx_ring->next_to_clean = i;
840 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
843 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
846 /* include DDPed FCoE data */
850 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
851 sizeof(struct fc_frame_header) -
852 sizeof(struct fcoe_crc_eof);
855 total_rx_bytes += ddp_bytes;
856 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
858 #endif /* IXGBE_FCOE */
860 rx_ring->total_packets += total_rx_packets;
861 rx_ring->total_bytes += total_rx_bytes;
862 adapter->net_stats.rx_bytes += total_rx_bytes;
863 adapter->net_stats.rx_packets += total_rx_packets;
868 static int ixgbe_clean_rxonly(struct napi_struct *, int);
870 * ixgbe_configure_msix - Configure MSI-X hardware
871 * @adapter: board private structure
873 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
876 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
878 struct ixgbe_q_vector *q_vector;
879 int i, j, q_vectors, v_idx, r_idx;
882 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
885 * Populate the IVAR table and set the ITR values to the
886 * corresponding register.
888 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
889 q_vector = adapter->q_vector[v_idx];
890 /* XXX for_each_bit(...) */
891 r_idx = find_first_bit(q_vector->rxr_idx,
892 adapter->num_rx_queues);
894 for (i = 0; i < q_vector->rxr_count; i++) {
895 j = adapter->rx_ring[r_idx].reg_idx;
896 ixgbe_set_ivar(adapter, 0, j, v_idx);
897 r_idx = find_next_bit(q_vector->rxr_idx,
898 adapter->num_rx_queues,
901 r_idx = find_first_bit(q_vector->txr_idx,
902 adapter->num_tx_queues);
904 for (i = 0; i < q_vector->txr_count; i++) {
905 j = adapter->tx_ring[r_idx].reg_idx;
906 ixgbe_set_ivar(adapter, 1, j, v_idx);
907 r_idx = find_next_bit(q_vector->txr_idx,
908 adapter->num_tx_queues,
912 /* if this is a tx only vector halve the interrupt rate */
913 if (q_vector->txr_count && !q_vector->rxr_count)
914 q_vector->eitr = (adapter->eitr_param >> 1);
915 else if (q_vector->rxr_count)
917 q_vector->eitr = adapter->eitr_param;
919 ixgbe_write_eitr(q_vector);
922 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
923 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
925 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
926 ixgbe_set_ivar(adapter, -1, 1, v_idx);
927 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
929 /* set up to autoclear timer, and the vectors */
930 mask = IXGBE_EIMS_ENABLE_MASK;
931 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
939 latency_invalid = 255
943 * ixgbe_update_itr - update the dynamic ITR value based on statistics
944 * @adapter: pointer to adapter
945 * @eitr: eitr setting (ints per sec) to give last timeslice
946 * @itr_setting: current throttle rate in ints/second
947 * @packets: the number of packets during this measurement interval
948 * @bytes: the number of bytes during this measurement interval
950 * Stores a new ITR value based on packets and byte
951 * counts during the last interrupt. The advantage of per interrupt
952 * computation is faster updates and more accurate ITR for the current
953 * traffic pattern. Constants in this function were computed
954 * based on theoretical maximum wire speed and thresholds were set based
955 * on testing data as well as attempting to minimize response time
956 * while increasing bulk throughput.
957 * this functionality is controlled by the InterruptThrottleRate module
958 * parameter (see ixgbe_param.c)
960 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
961 u32 eitr, u8 itr_setting,
962 int packets, int bytes)
964 unsigned int retval = itr_setting;
969 goto update_itr_done;
972 /* simple throttlerate management
973 * 0-20MB/s lowest (100000 ints/s)
974 * 20-100MB/s low (20000 ints/s)
975 * 100-1249MB/s bulk (8000 ints/s)
977 /* what was last interrupt timeslice? */
978 timepassed_us = 1000000/eitr;
979 bytes_perint = bytes / timepassed_us; /* bytes/usec */
981 switch (itr_setting) {
983 if (bytes_perint > adapter->eitr_low)
984 retval = low_latency;
987 if (bytes_perint > adapter->eitr_high)
988 retval = bulk_latency;
989 else if (bytes_perint <= adapter->eitr_low)
990 retval = lowest_latency;
993 if (bytes_perint <= adapter->eitr_high)
994 retval = low_latency;
1003 * ixgbe_write_eitr - write EITR register in hardware specific way
1004 * @q_vector: structure containing interrupt and ring information
1006 * This function is made to be called by ethtool and by the driver
1007 * when it needs to update EITR registers at runtime. Hardware
1008 * specific quirks/differences are taken care of here.
1010 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1012 struct ixgbe_adapter *adapter = q_vector->adapter;
1013 struct ixgbe_hw *hw = &adapter->hw;
1014 int v_idx = q_vector->v_idx;
1015 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1017 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1018 /* must write high and low 16 bits to reset counter */
1019 itr_reg |= (itr_reg << 16);
1020 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1022 * set the WDIS bit to not clear the timer bits and cause an
1023 * immediate assertion of the interrupt
1025 itr_reg |= IXGBE_EITR_CNT_WDIS;
1027 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1030 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1032 struct ixgbe_adapter *adapter = q_vector->adapter;
1034 u8 current_itr, ret_itr;
1036 struct ixgbe_ring *rx_ring, *tx_ring;
1038 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1039 for (i = 0; i < q_vector->txr_count; i++) {
1040 tx_ring = &(adapter->tx_ring[r_idx]);
1041 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1043 tx_ring->total_packets,
1044 tx_ring->total_bytes);
1045 /* if the result for this queue would decrease interrupt
1046 * rate for this vector then use that result */
1047 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1048 q_vector->tx_itr - 1 : ret_itr);
1049 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1053 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1054 for (i = 0; i < q_vector->rxr_count; i++) {
1055 rx_ring = &(adapter->rx_ring[r_idx]);
1056 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1058 rx_ring->total_packets,
1059 rx_ring->total_bytes);
1060 /* if the result for this queue would decrease interrupt
1061 * rate for this vector then use that result */
1062 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1063 q_vector->rx_itr - 1 : ret_itr);
1064 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1068 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1070 switch (current_itr) {
1071 /* counts and packets in update_itr are dependent on these numbers */
1072 case lowest_latency:
1076 new_itr = 20000; /* aka hwitr = ~200 */
1084 if (new_itr != q_vector->eitr) {
1085 /* do an exponential smoothing */
1086 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1088 /* save the algorithm value here, not the smoothed one */
1089 q_vector->eitr = new_itr;
1091 ixgbe_write_eitr(q_vector);
1097 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1099 struct ixgbe_hw *hw = &adapter->hw;
1101 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1102 (eicr & IXGBE_EICR_GPI_SDP1)) {
1103 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1104 /* write to clear the interrupt */
1105 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1109 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1111 struct ixgbe_hw *hw = &adapter->hw;
1113 if (eicr & IXGBE_EICR_GPI_SDP1) {
1114 /* Clear the interrupt */
1115 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1116 schedule_work(&adapter->multispeed_fiber_task);
1117 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1118 /* Clear the interrupt */
1119 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1120 schedule_work(&adapter->sfp_config_module_task);
1122 /* Interrupt isn't for us... */
1127 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1129 struct ixgbe_hw *hw = &adapter->hw;
1132 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1133 adapter->link_check_timeout = jiffies;
1134 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1135 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1136 schedule_work(&adapter->watchdog_task);
1140 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1142 struct net_device *netdev = data;
1143 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1144 struct ixgbe_hw *hw = &adapter->hw;
1148 * Workaround for Silicon errata. Use clear-by-write instead
1149 * of clear-by-read. Reading with EICS will return the
1150 * interrupt causes without clearing, which later be done
1151 * with the write to EICR.
1153 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1154 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1156 if (eicr & IXGBE_EICR_LSC)
1157 ixgbe_check_lsc(adapter);
1159 if (hw->mac.type == ixgbe_mac_82598EB)
1160 ixgbe_check_fan_failure(adapter, eicr);
1162 if (hw->mac.type == ixgbe_mac_82599EB) {
1163 ixgbe_check_sfp_event(adapter, eicr);
1165 /* Handle Flow Director Full threshold interrupt */
1166 if (eicr & IXGBE_EICR_FLOW_DIR) {
1168 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1169 /* Disable transmits before FDIR Re-initialization */
1170 netif_tx_stop_all_queues(netdev);
1171 for (i = 0; i < adapter->num_tx_queues; i++) {
1172 struct ixgbe_ring *tx_ring =
1173 &adapter->tx_ring[i];
1174 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1175 &tx_ring->reinit_state))
1176 schedule_work(&adapter->fdir_reinit_task);
1180 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1181 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1186 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1191 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1192 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1195 mask = (qmask & 0xFFFFFFFF);
1196 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1197 mask = (qmask >> 32);
1198 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1200 /* skip the flush */
1203 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1208 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1209 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1210 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1212 mask = (qmask & 0xFFFFFFFF);
1213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1214 mask = (qmask >> 32);
1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1217 /* skip the flush */
1220 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1222 struct ixgbe_q_vector *q_vector = data;
1223 struct ixgbe_adapter *adapter = q_vector->adapter;
1224 struct ixgbe_ring *tx_ring;
1227 if (!q_vector->txr_count)
1230 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1231 for (i = 0; i < q_vector->txr_count; i++) {
1232 tx_ring = &(adapter->tx_ring[r_idx]);
1233 tx_ring->total_bytes = 0;
1234 tx_ring->total_packets = 0;
1235 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1239 /* disable interrupts on this vector only */
1240 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1241 napi_schedule(&q_vector->napi);
1247 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1249 * @data: pointer to our q_vector struct for this interrupt vector
1251 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1253 struct ixgbe_q_vector *q_vector = data;
1254 struct ixgbe_adapter *adapter = q_vector->adapter;
1255 struct ixgbe_ring *rx_ring;
1259 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1260 for (i = 0; i < q_vector->rxr_count; i++) {
1261 rx_ring = &(adapter->rx_ring[r_idx]);
1262 rx_ring->total_bytes = 0;
1263 rx_ring->total_packets = 0;
1264 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1268 if (!q_vector->rxr_count)
1271 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1272 rx_ring = &(adapter->rx_ring[r_idx]);
1273 /* disable interrupts on this vector only */
1274 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1275 napi_schedule(&q_vector->napi);
1280 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1282 struct ixgbe_q_vector *q_vector = data;
1283 struct ixgbe_adapter *adapter = q_vector->adapter;
1284 struct ixgbe_ring *ring;
1288 if (!q_vector->txr_count && !q_vector->rxr_count)
1291 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1292 for (i = 0; i < q_vector->txr_count; i++) {
1293 ring = &(adapter->tx_ring[r_idx]);
1294 ring->total_bytes = 0;
1295 ring->total_packets = 0;
1296 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1300 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1301 for (i = 0; i < q_vector->rxr_count; i++) {
1302 ring = &(adapter->rx_ring[r_idx]);
1303 ring->total_bytes = 0;
1304 ring->total_packets = 0;
1305 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1309 /* disable interrupts on this vector only */
1310 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1311 napi_schedule(&q_vector->napi);
1317 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1318 * @napi: napi struct with our devices info in it
1319 * @budget: amount of work driver is allowed to do this pass, in packets
1321 * This function is optimized for cleaning one queue only on a single
1324 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1326 struct ixgbe_q_vector *q_vector =
1327 container_of(napi, struct ixgbe_q_vector, napi);
1328 struct ixgbe_adapter *adapter = q_vector->adapter;
1329 struct ixgbe_ring *rx_ring = NULL;
1333 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1334 rx_ring = &(adapter->rx_ring[r_idx]);
1335 #ifdef CONFIG_IXGBE_DCA
1336 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1337 ixgbe_update_rx_dca(adapter, rx_ring);
1340 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1342 /* If all Rx work done, exit the polling mode */
1343 if (work_done < budget) {
1344 napi_complete(napi);
1345 if (adapter->itr_setting & 1)
1346 ixgbe_set_itr_msix(q_vector);
1347 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1348 ixgbe_irq_enable_queues(adapter,
1349 ((u64)1 << q_vector->v_idx));
1356 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1357 * @napi: napi struct with our devices info in it
1358 * @budget: amount of work driver is allowed to do this pass, in packets
1360 * This function will clean more than one rx queue associated with a
1363 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1365 struct ixgbe_q_vector *q_vector =
1366 container_of(napi, struct ixgbe_q_vector, napi);
1367 struct ixgbe_adapter *adapter = q_vector->adapter;
1368 struct ixgbe_ring *ring = NULL;
1369 int work_done = 0, i;
1371 bool tx_clean_complete = true;
1373 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1374 for (i = 0; i < q_vector->txr_count; i++) {
1375 ring = &(adapter->tx_ring[r_idx]);
1376 #ifdef CONFIG_IXGBE_DCA
1377 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1378 ixgbe_update_tx_dca(adapter, ring);
1380 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1381 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1385 /* attempt to distribute budget to each queue fairly, but don't allow
1386 * the budget to go below 1 because we'll exit polling */
1387 budget /= (q_vector->rxr_count ?: 1);
1388 budget = max(budget, 1);
1389 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1390 for (i = 0; i < q_vector->rxr_count; i++) {
1391 ring = &(adapter->rx_ring[r_idx]);
1392 #ifdef CONFIG_IXGBE_DCA
1393 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1394 ixgbe_update_rx_dca(adapter, ring);
1396 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1397 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1401 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1402 ring = &(adapter->rx_ring[r_idx]);
1403 /* If all Rx work done, exit the polling mode */
1404 if (work_done < budget) {
1405 napi_complete(napi);
1406 if (adapter->itr_setting & 1)
1407 ixgbe_set_itr_msix(q_vector);
1408 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1409 ixgbe_irq_enable_queues(adapter,
1410 ((u64)1 << q_vector->v_idx));
1418 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1419 * @napi: napi struct with our devices info in it
1420 * @budget: amount of work driver is allowed to do this pass, in packets
1422 * This function is optimized for cleaning one queue only on a single
1425 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1427 struct ixgbe_q_vector *q_vector =
1428 container_of(napi, struct ixgbe_q_vector, napi);
1429 struct ixgbe_adapter *adapter = q_vector->adapter;
1430 struct ixgbe_ring *tx_ring = NULL;
1434 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1435 tx_ring = &(adapter->tx_ring[r_idx]);
1436 #ifdef CONFIG_IXGBE_DCA
1437 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1438 ixgbe_update_tx_dca(adapter, tx_ring);
1441 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1444 /* If all Rx work done, exit the polling mode */
1445 if (work_done < budget) {
1446 napi_complete(napi);
1447 if (adapter->itr_setting & 1)
1448 ixgbe_set_itr_msix(q_vector);
1449 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1450 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1456 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1459 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1461 set_bit(r_idx, q_vector->rxr_idx);
1462 q_vector->rxr_count++;
1465 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1468 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1470 set_bit(t_idx, q_vector->txr_idx);
1471 q_vector->txr_count++;
1475 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1476 * @adapter: board private structure to initialize
1477 * @vectors: allotted vector count for descriptor rings
1479 * This function maps descriptor rings to the queue-specific vectors
1480 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1481 * one vector per ring/queue, but on a constrained vector budget, we
1482 * group the rings as "efficiently" as possible. You would add new
1483 * mapping configurations in here.
1485 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1489 int rxr_idx = 0, txr_idx = 0;
1490 int rxr_remaining = adapter->num_rx_queues;
1491 int txr_remaining = adapter->num_tx_queues;
1496 /* No mapping required if MSI-X is disabled. */
1497 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1501 * The ideal configuration...
1502 * We have enough vectors to map one per queue.
1504 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1505 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1506 map_vector_to_rxq(adapter, v_start, rxr_idx);
1508 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1509 map_vector_to_txq(adapter, v_start, txr_idx);
1515 * If we don't have enough vectors for a 1-to-1
1516 * mapping, we'll have to group them so there are
1517 * multiple queues per vector.
1519 /* Re-adjusting *qpv takes care of the remainder. */
1520 for (i = v_start; i < vectors; i++) {
1521 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1522 for (j = 0; j < rqpv; j++) {
1523 map_vector_to_rxq(adapter, i, rxr_idx);
1528 for (i = v_start; i < vectors; i++) {
1529 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1530 for (j = 0; j < tqpv; j++) {
1531 map_vector_to_txq(adapter, i, txr_idx);
1542 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1543 * @adapter: board private structure
1545 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1546 * interrupts from the kernel.
1548 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1550 struct net_device *netdev = adapter->netdev;
1551 irqreturn_t (*handler)(int, void *);
1552 int i, vector, q_vectors, err;
1555 /* Decrement for Other and TCP Timer vectors */
1556 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1558 /* Map the Tx/Rx rings to the vectors we were allotted. */
1559 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1563 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1564 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1565 &ixgbe_msix_clean_many)
1566 for (vector = 0; vector < q_vectors; vector++) {
1567 handler = SET_HANDLER(adapter->q_vector[vector]);
1569 if(handler == &ixgbe_msix_clean_rx) {
1570 sprintf(adapter->name[vector], "%s-%s-%d",
1571 netdev->name, "rx", ri++);
1573 else if(handler == &ixgbe_msix_clean_tx) {
1574 sprintf(adapter->name[vector], "%s-%s-%d",
1575 netdev->name, "tx", ti++);
1578 sprintf(adapter->name[vector], "%s-%s-%d",
1579 netdev->name, "TxRx", vector);
1581 err = request_irq(adapter->msix_entries[vector].vector,
1582 handler, 0, adapter->name[vector],
1583 adapter->q_vector[vector]);
1586 "request_irq failed for MSIX interrupt "
1587 "Error: %d\n", err);
1588 goto free_queue_irqs;
1592 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1593 err = request_irq(adapter->msix_entries[vector].vector,
1594 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1597 "request_irq for msix_lsc failed: %d\n", err);
1598 goto free_queue_irqs;
1604 for (i = vector - 1; i >= 0; i--)
1605 free_irq(adapter->msix_entries[--vector].vector,
1606 adapter->q_vector[i]);
1607 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1608 pci_disable_msix(adapter->pdev);
1609 kfree(adapter->msix_entries);
1610 adapter->msix_entries = NULL;
1615 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1617 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1619 u32 new_itr = q_vector->eitr;
1620 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1621 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1623 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1625 tx_ring->total_packets,
1626 tx_ring->total_bytes);
1627 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1629 rx_ring->total_packets,
1630 rx_ring->total_bytes);
1632 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1634 switch (current_itr) {
1635 /* counts and packets in update_itr are dependent on these numbers */
1636 case lowest_latency:
1640 new_itr = 20000; /* aka hwitr = ~200 */
1649 if (new_itr != q_vector->eitr) {
1650 /* do an exponential smoothing */
1651 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1653 /* save the algorithm value here, not the smoothed one */
1654 q_vector->eitr = new_itr;
1656 ixgbe_write_eitr(q_vector);
1663 * ixgbe_irq_enable - Enable default interrupt generation settings
1664 * @adapter: board private structure
1666 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1670 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1671 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1672 mask |= IXGBE_EIMS_GPI_SDP1;
1673 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1674 mask |= IXGBE_EIMS_ECC;
1675 mask |= IXGBE_EIMS_GPI_SDP1;
1676 mask |= IXGBE_EIMS_GPI_SDP2;
1678 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1679 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1680 mask |= IXGBE_EIMS_FLOW_DIR;
1682 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1683 ixgbe_irq_enable_queues(adapter, ~0);
1684 IXGBE_WRITE_FLUSH(&adapter->hw);
1688 * ixgbe_intr - legacy mode Interrupt Handler
1689 * @irq: interrupt number
1690 * @data: pointer to a network interface device structure
1692 static irqreturn_t ixgbe_intr(int irq, void *data)
1694 struct net_device *netdev = data;
1695 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1696 struct ixgbe_hw *hw = &adapter->hw;
1697 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1701 * Workaround for silicon errata. Mask the interrupts
1702 * before the read of EICR.
1704 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1706 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1707 * therefore no explict interrupt disable is necessary */
1708 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1710 /* shared interrupt alert!
1711 * make sure interrupts are enabled because the read will
1712 * have disabled interrupts due to EIAM */
1713 ixgbe_irq_enable(adapter);
1714 return IRQ_NONE; /* Not our interrupt */
1717 if (eicr & IXGBE_EICR_LSC)
1718 ixgbe_check_lsc(adapter);
1720 if (hw->mac.type == ixgbe_mac_82599EB)
1721 ixgbe_check_sfp_event(adapter, eicr);
1723 ixgbe_check_fan_failure(adapter, eicr);
1725 if (napi_schedule_prep(&(q_vector->napi))) {
1726 adapter->tx_ring[0].total_packets = 0;
1727 adapter->tx_ring[0].total_bytes = 0;
1728 adapter->rx_ring[0].total_packets = 0;
1729 adapter->rx_ring[0].total_bytes = 0;
1730 /* would disable interrupts here but EIAM disabled it */
1731 __napi_schedule(&(q_vector->napi));
1737 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1739 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1741 for (i = 0; i < q_vectors; i++) {
1742 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1743 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1744 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1745 q_vector->rxr_count = 0;
1746 q_vector->txr_count = 0;
1751 * ixgbe_request_irq - initialize interrupts
1752 * @adapter: board private structure
1754 * Attempts to configure interrupts using the best available
1755 * capabilities of the hardware and kernel.
1757 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1759 struct net_device *netdev = adapter->netdev;
1762 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1763 err = ixgbe_request_msix_irqs(adapter);
1764 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1765 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1766 netdev->name, netdev);
1768 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1769 netdev->name, netdev);
1773 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1778 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1780 struct net_device *netdev = adapter->netdev;
1782 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1785 q_vectors = adapter->num_msix_vectors;
1788 free_irq(adapter->msix_entries[i].vector, netdev);
1791 for (; i >= 0; i--) {
1792 free_irq(adapter->msix_entries[i].vector,
1793 adapter->q_vector[i]);
1796 ixgbe_reset_q_vectors(adapter);
1798 free_irq(adapter->pdev->irq, netdev);
1803 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1804 * @adapter: board private structure
1806 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1808 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1809 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1811 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1812 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1813 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1815 IXGBE_WRITE_FLUSH(&adapter->hw);
1816 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1818 for (i = 0; i < adapter->num_msix_vectors; i++)
1819 synchronize_irq(adapter->msix_entries[i].vector);
1821 synchronize_irq(adapter->pdev->irq);
1826 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1829 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1831 struct ixgbe_hw *hw = &adapter->hw;
1833 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1834 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1836 ixgbe_set_ivar(adapter, 0, 0, 0);
1837 ixgbe_set_ivar(adapter, 1, 0, 0);
1839 map_vector_to_rxq(adapter, 0, 0);
1840 map_vector_to_txq(adapter, 0, 0);
1842 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1846 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1847 * @adapter: board private structure
1849 * Configure the Tx unit of the MAC after a reset.
1851 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1854 struct ixgbe_hw *hw = &adapter->hw;
1855 u32 i, j, tdlen, txctrl;
1857 /* Setup the HW Tx Head and Tail descriptor pointers */
1858 for (i = 0; i < adapter->num_tx_queues; i++) {
1859 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1862 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1863 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1864 (tdba & DMA_BIT_MASK(32)));
1865 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1866 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1867 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1868 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1869 adapter->tx_ring[i].head = IXGBE_TDH(j);
1870 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1871 /* Disable Tx Head Writeback RO bit, since this hoses
1872 * bookkeeping if things aren't delivered in order.
1874 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1875 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1878 if (hw->mac.type == ixgbe_mac_82599EB) {
1879 /* We enable 8 traffic classes, DCB only */
1880 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1881 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1882 IXGBE_MTQC_8TC_8TQ));
1886 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1888 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1890 struct ixgbe_ring *rx_ring;
1894 struct ixgbe_ring_feature *feature = adapter->ring_feature;
1896 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1897 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1898 int dcb_i = feature[RING_F_DCB].indices;
1900 queue0 = index >> 4;
1901 else if (dcb_i == 4)
1902 queue0 = index >> 5;
1904 dev_err(&adapter->pdev->dev, "Invalid DCB "
1907 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1908 struct ixgbe_ring_feature *f;
1910 rx_ring = &adapter->rx_ring[queue0];
1911 f = &adapter->ring_feature[RING_F_FCOE];
1912 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1913 queue0 = f->mask + index -
1914 rx_ring->reg_idx - 1;
1916 #endif /* IXGBE_FCOE */
1921 mask = (unsigned long) feature[RING_F_RSS].mask;
1922 queue0 = index & mask;
1923 index = index & mask;
1926 rx_ring = &adapter->rx_ring[queue0];
1928 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1930 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1931 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1933 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1934 IXGBE_SRRCTL_BSIZEHDR_MASK;
1936 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1937 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1938 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1940 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1942 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1944 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1945 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1946 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1952 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1957 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1960 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1961 #ifdef CONFIG_IXGBE_DCB
1962 | IXGBE_FLAG_DCB_ENABLED
1967 case (IXGBE_FLAG_RSS_ENABLED):
1968 mrqc = IXGBE_MRQC_RSSEN;
1970 #ifdef CONFIG_IXGBE_DCB
1971 case (IXGBE_FLAG_DCB_ENABLED):
1972 mrqc = IXGBE_MRQC_RT8TCEN;
1974 #endif /* CONFIG_IXGBE_DCB */
1983 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1984 * @adapter: board private structure
1986 * Configure the Rx unit of the MAC after a reset.
1988 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1991 struct ixgbe_hw *hw = &adapter->hw;
1992 struct net_device *netdev = adapter->netdev;
1993 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1995 u32 rdlen, rxctrl, rxcsum;
1996 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1997 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1998 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2000 u32 reta = 0, mrqc = 0;
2005 /* Decide whether to use packet split mode or not */
2006 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2009 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2010 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2011 #endif /* IXGBE_FCOE */
2013 /* Set the RX buffer length according to the mode */
2014 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2015 rx_buf_len = IXGBE_RX_HDR_SIZE;
2016 if (hw->mac.type == ixgbe_mac_82599EB) {
2017 /* PSRTYPE must be initialized in 82599 */
2018 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2019 IXGBE_PSRTYPE_UDPHDR |
2020 IXGBE_PSRTYPE_IPV4HDR |
2021 IXGBE_PSRTYPE_IPV6HDR |
2022 IXGBE_PSRTYPE_L2HDR;
2023 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2026 if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) &&
2027 (netdev->mtu <= ETH_DATA_LEN))
2028 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2030 rx_buf_len = ALIGN(max_frame, 1024);
2033 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2034 fctrl |= IXGBE_FCTRL_BAM;
2035 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2036 fctrl |= IXGBE_FCTRL_PMCF;
2037 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2039 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2040 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2041 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2043 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2045 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2046 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2048 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2050 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2051 /* disable receives while setting up the descriptors */
2052 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2053 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2056 * Setup the HW Rx Head and Tail Descriptor Pointers and
2057 * the Base and Length of the Rx Descriptor Ring
2059 for (i = 0; i < adapter->num_rx_queues; i++) {
2060 rdba = adapter->rx_ring[i].dma;
2061 j = adapter->rx_ring[i].reg_idx;
2062 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2063 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2064 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2065 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2066 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2067 adapter->rx_ring[i].head = IXGBE_RDH(j);
2068 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2069 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
2072 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2073 struct ixgbe_ring_feature *f;
2074 f = &adapter->ring_feature[RING_F_FCOE];
2075 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2076 (i >= f->mask) && (i < f->mask + f->indices))
2077 adapter->rx_ring[i].rx_buf_len =
2078 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2081 #endif /* IXGBE_FCOE */
2082 ixgbe_configure_srrctl(adapter, j);
2085 if (hw->mac.type == ixgbe_mac_82598EB) {
2087 * For VMDq support of different descriptor types or
2088 * buffer sizes through the use of multiple SRRCTL
2089 * registers, RDRXCTL.MVMEN must be set to 1
2091 * also, the manual doesn't mention it clearly but DCA hints
2092 * will only use queue 0's tags unless this bit is set. Side
2093 * effects of setting this bit are only that SRRCTL must be
2094 * fully programmed [0..15]
2096 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2097 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2098 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2101 /* Program MRQC for the distribution of queues */
2102 mrqc = ixgbe_setup_mrqc(adapter);
2104 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2105 /* Fill out redirection table */
2106 for (i = 0, j = 0; i < 128; i++, j++) {
2107 if (j == adapter->ring_feature[RING_F_RSS].indices)
2109 /* reta = 4-byte sliding window of
2110 * 0x00..(indices-1)(indices-1)00..etc. */
2111 reta = (reta << 8) | (j * 0x11);
2113 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2116 /* Fill out hash function seeds */
2117 for (i = 0; i < 10; i++)
2118 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2120 if (hw->mac.type == ixgbe_mac_82598EB)
2121 mrqc |= IXGBE_MRQC_RSSEN;
2122 /* Perform hash on these packet types */
2123 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2124 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2125 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2126 | IXGBE_MRQC_RSS_FIELD_IPV6
2127 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2128 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2130 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2132 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2134 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2135 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2136 /* Disable indicating checksum in descriptor, enables
2138 rxcsum |= IXGBE_RXCSUM_PCSD;
2140 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2141 /* Enable IPv4 payload checksum for UDP fragments
2142 * if PCSD is not set */
2143 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2146 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2148 if (hw->mac.type == ixgbe_mac_82599EB) {
2149 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2150 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2151 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2152 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2155 if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) {
2156 /* Enable 82599 HW-RSC */
2157 for (i = 0; i < adapter->num_rx_queues; i++) {
2158 j = adapter->rx_ring[i].reg_idx;
2159 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2160 rscctrl |= IXGBE_RSCCTL_RSCEN;
2162 * we must limit the number of descriptors so that the
2163 * total size of max desc * buf_len is not greater
2166 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2167 #if (MAX_SKB_FRAGS > 16)
2168 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2169 #elif (MAX_SKB_FRAGS > 8)
2170 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2171 #elif (MAX_SKB_FRAGS > 4)
2172 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2174 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2177 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2178 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2179 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2180 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2182 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2184 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2186 /* Disable RSC for ACK packets */
2187 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2188 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2192 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2195 struct ixgbe_hw *hw = &adapter->hw;
2197 /* add VID to filter table */
2198 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2201 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2203 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2204 struct ixgbe_hw *hw = &adapter->hw;
2206 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2207 ixgbe_irq_disable(adapter);
2209 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2211 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2212 ixgbe_irq_enable(adapter);
2214 /* remove VID from filter table */
2215 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2218 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2219 struct vlan_group *grp)
2221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2225 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2226 ixgbe_irq_disable(adapter);
2227 adapter->vlgrp = grp;
2230 * For a DCB driver, always enable VLAN tag stripping so we can
2231 * still receive traffic from a DCB-enabled host even if we're
2234 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2235 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2236 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2237 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2238 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2239 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2240 ctrl |= IXGBE_VLNCTRL_VFE;
2241 /* enable VLAN tag insert/strip */
2242 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2243 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2244 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2245 for (i = 0; i < adapter->num_rx_queues; i++) {
2246 j = adapter->rx_ring[i].reg_idx;
2247 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2248 ctrl |= IXGBE_RXDCTL_VME;
2249 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2252 ixgbe_vlan_rx_add_vid(netdev, 0);
2254 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2255 ixgbe_irq_enable(adapter);
2258 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2260 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2262 if (adapter->vlgrp) {
2264 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2265 if (!vlan_group_get_device(adapter->vlgrp, vid))
2267 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2272 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2274 struct dev_mc_list *mc_ptr;
2275 u8 *addr = *mc_addr_ptr;
2278 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2280 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2282 *mc_addr_ptr = NULL;
2288 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2289 * @netdev: network interface device structure
2291 * The set_rx_method entry point is called whenever the unicast/multicast
2292 * address list or the network interface flags are updated. This routine is
2293 * responsible for configuring the hardware for proper unicast, multicast and
2296 static void ixgbe_set_rx_mode(struct net_device *netdev)
2298 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2299 struct ixgbe_hw *hw = &adapter->hw;
2301 u8 *addr_list = NULL;
2304 /* Check for Promiscuous and All Multicast modes */
2306 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2307 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2309 if (netdev->flags & IFF_PROMISC) {
2310 hw->addr_ctrl.user_set_promisc = 1;
2311 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2312 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2314 if (netdev->flags & IFF_ALLMULTI) {
2315 fctrl |= IXGBE_FCTRL_MPE;
2316 fctrl &= ~IXGBE_FCTRL_UPE;
2318 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2320 vlnctrl |= IXGBE_VLNCTRL_VFE;
2321 hw->addr_ctrl.user_set_promisc = 0;
2324 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2325 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2327 /* reprogram secondary unicast list */
2328 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2330 /* reprogram multicast list */
2331 addr_count = netdev->mc_count;
2333 addr_list = netdev->mc_list->dmi_addr;
2334 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2335 ixgbe_addr_list_itr);
2338 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2341 struct ixgbe_q_vector *q_vector;
2342 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2344 /* legacy and MSI only use one vector */
2345 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2348 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2349 struct napi_struct *napi;
2350 q_vector = adapter->q_vector[q_idx];
2351 napi = &q_vector->napi;
2352 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2353 if (!q_vector->rxr_count || !q_vector->txr_count) {
2354 if (q_vector->txr_count == 1)
2355 napi->poll = &ixgbe_clean_txonly;
2356 else if (q_vector->rxr_count == 1)
2357 napi->poll = &ixgbe_clean_rxonly;
2365 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2368 struct ixgbe_q_vector *q_vector;
2369 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2371 /* legacy and MSI only use one vector */
2372 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2375 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2376 q_vector = adapter->q_vector[q_idx];
2377 napi_disable(&q_vector->napi);
2381 #ifdef CONFIG_IXGBE_DCB
2383 * ixgbe_configure_dcb - Configure DCB hardware
2384 * @adapter: ixgbe adapter struct
2386 * This is called by the driver on open to configure the DCB hardware.
2387 * This is also called by the gennetlink interface when reconfiguring
2390 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2392 struct ixgbe_hw *hw = &adapter->hw;
2393 u32 txdctl, vlnctrl;
2396 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2397 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2398 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2400 /* reconfigure the hardware */
2401 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2403 for (i = 0; i < adapter->num_tx_queues; i++) {
2404 j = adapter->tx_ring[i].reg_idx;
2405 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2406 /* PThresh workaround for Tx hang with DFP enabled. */
2408 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2410 /* Enable VLAN tag insert/strip */
2411 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2412 if (hw->mac.type == ixgbe_mac_82598EB) {
2413 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2414 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2415 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2416 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2417 vlnctrl |= IXGBE_VLNCTRL_VFE;
2418 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2419 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2420 for (i = 0; i < adapter->num_rx_queues; i++) {
2421 j = adapter->rx_ring[i].reg_idx;
2422 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2423 vlnctrl |= IXGBE_RXDCTL_VME;
2424 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2427 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2431 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2433 struct net_device *netdev = adapter->netdev;
2434 struct ixgbe_hw *hw = &adapter->hw;
2437 ixgbe_set_rx_mode(netdev);
2439 ixgbe_restore_vlan(adapter);
2440 #ifdef CONFIG_IXGBE_DCB
2441 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2442 netif_set_gso_max_size(netdev, 32768);
2443 ixgbe_configure_dcb(adapter);
2445 netif_set_gso_max_size(netdev, 65536);
2448 netif_set_gso_max_size(netdev, 65536);
2452 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2453 ixgbe_configure_fcoe(adapter);
2455 #endif /* IXGBE_FCOE */
2456 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2457 for (i = 0; i < adapter->num_tx_queues; i++)
2458 adapter->tx_ring[i].atr_sample_rate =
2459 adapter->atr_sample_rate;
2460 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2461 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2462 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2465 ixgbe_configure_tx(adapter);
2466 ixgbe_configure_rx(adapter);
2467 for (i = 0; i < adapter->num_rx_queues; i++)
2468 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2469 (adapter->rx_ring[i].count - 1));
2472 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2474 switch (hw->phy.type) {
2475 case ixgbe_phy_sfp_avago:
2476 case ixgbe_phy_sfp_ftl:
2477 case ixgbe_phy_sfp_intel:
2478 case ixgbe_phy_sfp_unknown:
2479 case ixgbe_phy_tw_tyco:
2480 case ixgbe_phy_tw_unknown:
2488 * ixgbe_sfp_link_config - set up SFP+ link
2489 * @adapter: pointer to private adapter struct
2491 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2493 struct ixgbe_hw *hw = &adapter->hw;
2495 if (hw->phy.multispeed_fiber) {
2497 * In multispeed fiber setups, the device may not have
2498 * had a physical connection when the driver loaded.
2499 * If that's the case, the initial link configuration
2500 * couldn't get the MAC into 10G or 1G mode, so we'll
2501 * never have a link status change interrupt fire.
2502 * We need to try and force an autonegotiation
2503 * session, then bring up link.
2505 hw->mac.ops.setup_sfp(hw);
2506 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2507 schedule_work(&adapter->multispeed_fiber_task);
2510 * Direct Attach Cu and non-multispeed fiber modules
2511 * still need to be configured properly prior to
2514 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2515 schedule_work(&adapter->sfp_config_module_task);
2520 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2521 * @hw: pointer to private hardware struct
2523 * Returns 0 on success, negative on failure
2525 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2528 bool link_up = false;
2529 u32 ret = IXGBE_ERR_LINK_SETUP;
2531 if (hw->mac.ops.check_link)
2532 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2537 if (hw->mac.ops.get_link_capabilities)
2538 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2543 if (hw->mac.ops.setup_link_speed)
2544 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2549 #define IXGBE_MAX_RX_DESC_POLL 10
2550 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2553 int j = adapter->rx_ring[rxr].reg_idx;
2556 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2557 if (IXGBE_READ_REG(&adapter->hw,
2558 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2563 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2564 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2565 "not set within the polling period\n", rxr);
2567 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2568 (adapter->rx_ring[rxr].count - 1));
2571 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2573 struct net_device *netdev = adapter->netdev;
2574 struct ixgbe_hw *hw = &adapter->hw;
2576 int num_rx_rings = adapter->num_rx_queues;
2578 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2579 u32 txdctl, rxdctl, mhadd;
2583 ixgbe_get_hw_control(adapter);
2585 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2586 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2587 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2588 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2589 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2594 /* XXX: to interrupt immediately for EICS writes, enable this */
2595 /* gpie |= IXGBE_GPIE_EIMEN; */
2596 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2599 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2600 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2601 * specifically only auto mask tx and rx interrupts */
2602 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2605 /* Enable fan failure interrupt if media type is copper */
2606 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2607 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2608 gpie |= IXGBE_SDP1_GPIEN;
2609 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2612 if (hw->mac.type == ixgbe_mac_82599EB) {
2613 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2614 gpie |= IXGBE_SDP1_GPIEN;
2615 gpie |= IXGBE_SDP2_GPIEN;
2616 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2620 /* adjust max frame to be able to do baby jumbo for FCoE */
2621 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2622 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2623 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2625 #endif /* IXGBE_FCOE */
2626 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2627 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2628 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2629 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2631 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2634 for (i = 0; i < adapter->num_tx_queues; i++) {
2635 j = adapter->tx_ring[i].reg_idx;
2636 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2637 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2638 txdctl |= (8 << 16);
2639 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2642 if (hw->mac.type == ixgbe_mac_82599EB) {
2643 /* DMATXCTL.EN must be set after all Tx queue config is done */
2644 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2645 dmatxctl |= IXGBE_DMATXCTL_TE;
2646 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2648 for (i = 0; i < adapter->num_tx_queues; i++) {
2649 j = adapter->tx_ring[i].reg_idx;
2650 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2651 txdctl |= IXGBE_TXDCTL_ENABLE;
2652 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2655 for (i = 0; i < num_rx_rings; i++) {
2656 j = adapter->rx_ring[i].reg_idx;
2657 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2658 /* enable PTHRESH=32 descriptors (half the internal cache)
2659 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2660 * this also removes a pesky rx_no_buffer_count increment */
2662 rxdctl |= IXGBE_RXDCTL_ENABLE;
2663 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2664 if (hw->mac.type == ixgbe_mac_82599EB)
2665 ixgbe_rx_desc_queue_enable(adapter, i);
2667 /* enable all receives */
2668 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2669 if (hw->mac.type == ixgbe_mac_82598EB)
2670 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2672 rxdctl |= IXGBE_RXCTRL_RXEN;
2673 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2675 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2676 ixgbe_configure_msix(adapter);
2678 ixgbe_configure_msi_and_legacy(adapter);
2680 clear_bit(__IXGBE_DOWN, &adapter->state);
2681 ixgbe_napi_enable_all(adapter);
2683 /* clear any pending interrupts, may auto mask */
2684 IXGBE_READ_REG(hw, IXGBE_EICR);
2686 ixgbe_irq_enable(adapter);
2689 * If this adapter has a fan, check to see if we had a failure
2690 * before we enabled the interrupt.
2692 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2693 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2694 if (esdp & IXGBE_ESDP_SDP1)
2696 "Fan has stopped, replace the adapter\n");
2700 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2701 * arrived before interrupts were enabled but after probe. Such
2702 * devices wouldn't have their type identified yet. We need to
2703 * kick off the SFP+ module setup first, then try to bring up link.
2704 * If we're not hot-pluggable SFP+, we just need to configure link
2707 if (hw->phy.type == ixgbe_phy_unknown) {
2708 err = hw->phy.ops.identify(hw);
2709 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2711 * Take the device down and schedule the sfp tasklet
2712 * which will unregister_netdev and log it.
2714 ixgbe_down(adapter);
2715 schedule_work(&adapter->sfp_config_module_task);
2720 if (ixgbe_is_sfp(hw)) {
2721 ixgbe_sfp_link_config(adapter);
2723 err = ixgbe_non_sfp_link_config(hw);
2725 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2728 for (i = 0; i < adapter->num_tx_queues; i++)
2729 set_bit(__IXGBE_FDIR_INIT_DONE,
2730 &(adapter->tx_ring[i].reinit_state));
2732 /* enable transmits */
2733 netif_tx_start_all_queues(netdev);
2735 /* bring the link up in the watchdog, this could race with our first
2736 * link up interrupt but shouldn't be a problem */
2737 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2738 adapter->link_check_timeout = jiffies;
2739 mod_timer(&adapter->watchdog_timer, jiffies);
2743 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2745 WARN_ON(in_interrupt());
2746 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2748 ixgbe_down(adapter);
2750 clear_bit(__IXGBE_RESETTING, &adapter->state);
2753 int ixgbe_up(struct ixgbe_adapter *adapter)
2755 /* hardware has been reset, we need to reload some things */
2756 ixgbe_configure(adapter);
2758 return ixgbe_up_complete(adapter);
2761 void ixgbe_reset(struct ixgbe_adapter *adapter)
2763 struct ixgbe_hw *hw = &adapter->hw;
2766 err = hw->mac.ops.init_hw(hw);
2769 case IXGBE_ERR_SFP_NOT_PRESENT:
2771 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2772 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2774 case IXGBE_ERR_EEPROM_VERSION:
2775 /* We are running on a pre-production device, log a warning */
2776 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2777 "adapter/LOM. Please be aware there may be issues "
2778 "associated with your hardware. If you are "
2779 "experiencing problems please contact your Intel or "
2780 "hardware representative who provided you with this "
2784 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2787 /* reprogram the RAR[0] in case user changed it. */
2788 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2792 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2793 * @adapter: board private structure
2794 * @rx_ring: ring to free buffers from
2796 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2797 struct ixgbe_ring *rx_ring)
2799 struct pci_dev *pdev = adapter->pdev;
2803 /* Free all the Rx ring sk_buffs */
2805 for (i = 0; i < rx_ring->count; i++) {
2806 struct ixgbe_rx_buffer *rx_buffer_info;
2808 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2809 if (rx_buffer_info->dma) {
2810 pci_unmap_single(pdev, rx_buffer_info->dma,
2811 rx_ring->rx_buf_len,
2812 PCI_DMA_FROMDEVICE);
2813 rx_buffer_info->dma = 0;
2815 if (rx_buffer_info->skb) {
2816 struct sk_buff *skb = rx_buffer_info->skb;
2817 rx_buffer_info->skb = NULL;
2819 struct sk_buff *this = skb;
2821 dev_kfree_skb(this);
2824 if (!rx_buffer_info->page)
2826 if (rx_buffer_info->page_dma) {
2827 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2828 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2829 rx_buffer_info->page_dma = 0;
2831 put_page(rx_buffer_info->page);
2832 rx_buffer_info->page = NULL;
2833 rx_buffer_info->page_offset = 0;
2836 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2837 memset(rx_ring->rx_buffer_info, 0, size);
2839 /* Zero out the descriptor ring */
2840 memset(rx_ring->desc, 0, rx_ring->size);
2842 rx_ring->next_to_clean = 0;
2843 rx_ring->next_to_use = 0;
2846 writel(0, adapter->hw.hw_addr + rx_ring->head);
2848 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2852 * ixgbe_clean_tx_ring - Free Tx Buffers
2853 * @adapter: board private structure
2854 * @tx_ring: ring to be cleaned
2856 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2857 struct ixgbe_ring *tx_ring)
2859 struct ixgbe_tx_buffer *tx_buffer_info;
2863 /* Free all the Tx ring sk_buffs */
2865 for (i = 0; i < tx_ring->count; i++) {
2866 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2867 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2870 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2871 memset(tx_ring->tx_buffer_info, 0, size);
2873 /* Zero out the descriptor ring */
2874 memset(tx_ring->desc, 0, tx_ring->size);
2876 tx_ring->next_to_use = 0;
2877 tx_ring->next_to_clean = 0;
2880 writel(0, adapter->hw.hw_addr + tx_ring->head);
2882 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2886 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2887 * @adapter: board private structure
2889 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2893 for (i = 0; i < adapter->num_rx_queues; i++)
2894 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2898 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2899 * @adapter: board private structure
2901 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2905 for (i = 0; i < adapter->num_tx_queues; i++)
2906 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2909 void ixgbe_down(struct ixgbe_adapter *adapter)
2911 struct net_device *netdev = adapter->netdev;
2912 struct ixgbe_hw *hw = &adapter->hw;
2917 /* signal that we are down to the interrupt handler */
2918 set_bit(__IXGBE_DOWN, &adapter->state);
2920 /* disable receives */
2921 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2922 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2924 netif_tx_disable(netdev);
2926 IXGBE_WRITE_FLUSH(hw);
2929 netif_tx_stop_all_queues(netdev);
2931 ixgbe_irq_disable(adapter);
2933 ixgbe_napi_disable_all(adapter);
2935 del_timer_sync(&adapter->watchdog_timer);
2936 cancel_work_sync(&adapter->watchdog_task);
2938 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2939 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2940 cancel_work_sync(&adapter->fdir_reinit_task);
2942 /* disable transmits in the hardware now that interrupts are off */
2943 for (i = 0; i < adapter->num_tx_queues; i++) {
2944 j = adapter->tx_ring[i].reg_idx;
2945 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2946 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2947 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2949 /* Disable the Tx DMA engine on 82599 */
2950 if (hw->mac.type == ixgbe_mac_82599EB)
2951 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2952 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2953 ~IXGBE_DMATXCTL_TE));
2955 netif_carrier_off(netdev);
2957 if (!pci_channel_offline(adapter->pdev))
2958 ixgbe_reset(adapter);
2959 ixgbe_clean_all_tx_rings(adapter);
2960 ixgbe_clean_all_rx_rings(adapter);
2962 #ifdef CONFIG_IXGBE_DCA
2963 /* since we reset the hardware DCA settings were cleared */
2964 ixgbe_setup_dca(adapter);
2969 * ixgbe_poll - NAPI Rx polling callback
2970 * @napi: structure for representing this polling device
2971 * @budget: how many packets driver is allowed to clean
2973 * This function is used for legacy and MSI, NAPI mode
2975 static int ixgbe_poll(struct napi_struct *napi, int budget)
2977 struct ixgbe_q_vector *q_vector =
2978 container_of(napi, struct ixgbe_q_vector, napi);
2979 struct ixgbe_adapter *adapter = q_vector->adapter;
2980 int tx_clean_complete, work_done = 0;
2982 #ifdef CONFIG_IXGBE_DCA
2983 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2984 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2985 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2989 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2990 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2992 if (!tx_clean_complete)
2995 /* If budget not fully consumed, exit the polling mode */
2996 if (work_done < budget) {
2997 napi_complete(napi);
2998 if (adapter->itr_setting & 1)
2999 ixgbe_set_itr(adapter);
3000 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3001 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3007 * ixgbe_tx_timeout - Respond to a Tx Hang
3008 * @netdev: network interface device structure
3010 static void ixgbe_tx_timeout(struct net_device *netdev)
3012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3014 /* Do the reset outside of interrupt context */
3015 schedule_work(&adapter->reset_task);
3018 static void ixgbe_reset_task(struct work_struct *work)
3020 struct ixgbe_adapter *adapter;
3021 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3023 /* If we're already down or resetting, just bail */
3024 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3025 test_bit(__IXGBE_RESETTING, &adapter->state))
3028 adapter->tx_timeout_count++;
3030 ixgbe_reinit_locked(adapter);
3033 #ifdef CONFIG_IXGBE_DCB
3034 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3037 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3039 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3043 adapter->num_rx_queues = f->indices;
3044 adapter->num_tx_queues = f->indices;
3052 * ixgbe_set_rss_queues: Allocate queues for RSS
3053 * @adapter: board private structure to initialize
3055 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3056 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3059 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3062 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3064 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3066 adapter->num_rx_queues = f->indices;
3067 adapter->num_tx_queues = f->indices;
3077 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3078 * @adapter: board private structure to initialize
3080 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3081 * to the original CPU that initiated the Tx session. This runs in addition
3082 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3083 * Rx load across CPUs using RSS.
3086 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3089 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3091 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3094 /* Flow Director must have RSS enabled */
3095 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3096 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3097 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3098 adapter->num_tx_queues = f_fdir->indices;
3099 adapter->num_rx_queues = f_fdir->indices;
3102 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3103 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3110 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3111 * @adapter: board private structure to initialize
3113 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3114 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3115 * rx queues out of the max number of rx queues, instead, it is used as the
3116 * index of the first rx queue used by FCoE.
3119 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3122 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3124 f->indices = min((int)num_online_cpus(), f->indices);
3125 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3126 #ifdef CONFIG_IXGBE_DCB
3127 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3128 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3129 ixgbe_set_dcb_queues(adapter);
3132 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3133 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3134 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3135 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3136 ixgbe_set_fdir_queues(adapter);
3138 ixgbe_set_rss_queues(adapter);
3140 /* adding FCoE rx rings to the end */
3141 f->mask = adapter->num_rx_queues;
3142 adapter->num_rx_queues += f->indices;
3143 if (adapter->num_tx_queues == 0)
3144 adapter->num_tx_queues = f->indices;
3152 #endif /* IXGBE_FCOE */
3154 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3155 * @adapter: board private structure to initialize
3157 * This is the top level queue allocation routine. The order here is very
3158 * important, starting with the "most" number of features turned on at once,
3159 * and ending with the smallest set of features. This way large combinations
3160 * can be allocated if they're turned on, and smaller combinations are the
3161 * fallthrough conditions.
3164 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3167 if (ixgbe_set_fcoe_queues(adapter))
3170 #endif /* IXGBE_FCOE */
3171 #ifdef CONFIG_IXGBE_DCB
3172 if (ixgbe_set_dcb_queues(adapter))
3176 if (ixgbe_set_fdir_queues(adapter))
3179 if (ixgbe_set_rss_queues(adapter))
3182 /* fallback to base case */
3183 adapter->num_rx_queues = 1;
3184 adapter->num_tx_queues = 1;
3187 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3188 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3191 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3194 int err, vector_threshold;
3196 /* We'll want at least 3 (vector_threshold):
3199 * 3) Other (Link Status Change, etc.)
3200 * 4) TCP Timer (optional)
3202 vector_threshold = MIN_MSIX_COUNT;
3204 /* The more we get, the more we will assign to Tx/Rx Cleanup
3205 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3206 * Right now, we simply care about how many we'll get; we'll
3207 * set them up later while requesting irq's.
3209 while (vectors >= vector_threshold) {
3210 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3212 if (!err) /* Success in acquiring all requested vectors. */
3215 vectors = 0; /* Nasty failure, quit now */
3216 else /* err == number of vectors we should try again with */
3220 if (vectors < vector_threshold) {
3221 /* Can't allocate enough MSI-X interrupts? Oh well.
3222 * This just means we'll go with either a single MSI
3223 * vector or fall back to legacy interrupts.
3225 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3226 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3227 kfree(adapter->msix_entries);
3228 adapter->msix_entries = NULL;
3230 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3232 * Adjust for only the vectors we'll use, which is minimum
3233 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3234 * vectors we were allocated.
3236 adapter->num_msix_vectors = min(vectors,
3237 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3242 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3243 * @adapter: board private structure to initialize
3245 * Cache the descriptor ring offsets for RSS to the assigned rings.
3248 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3253 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3254 for (i = 0; i < adapter->num_rx_queues; i++)
3255 adapter->rx_ring[i].reg_idx = i;
3256 for (i = 0; i < adapter->num_tx_queues; i++)
3257 adapter->tx_ring[i].reg_idx = i;
3266 #ifdef CONFIG_IXGBE_DCB
3268 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3269 * @adapter: board private structure to initialize
3271 * Cache the descriptor ring offsets for DCB to the assigned rings.
3274 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3278 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3280 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3281 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3282 /* the number of queues is assumed to be symmetric */
3283 for (i = 0; i < dcb_i; i++) {
3284 adapter->rx_ring[i].reg_idx = i << 3;
3285 adapter->tx_ring[i].reg_idx = i << 2;
3288 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3291 * Tx TC0 starts at: descriptor queue 0
3292 * Tx TC1 starts at: descriptor queue 32
3293 * Tx TC2 starts at: descriptor queue 64
3294 * Tx TC3 starts at: descriptor queue 80
3295 * Tx TC4 starts at: descriptor queue 96
3296 * Tx TC5 starts at: descriptor queue 104
3297 * Tx TC6 starts at: descriptor queue 112
3298 * Tx TC7 starts at: descriptor queue 120
3300 * Rx TC0-TC7 are offset by 16 queues each
3302 for (i = 0; i < 3; i++) {
3303 adapter->tx_ring[i].reg_idx = i << 5;
3304 adapter->rx_ring[i].reg_idx = i << 4;
3306 for ( ; i < 5; i++) {
3307 adapter->tx_ring[i].reg_idx =
3309 adapter->rx_ring[i].reg_idx = i << 4;
3311 for ( ; i < dcb_i; i++) {
3312 adapter->tx_ring[i].reg_idx =
3314 adapter->rx_ring[i].reg_idx = i << 4;
3318 } else if (dcb_i == 4) {
3320 * Tx TC0 starts at: descriptor queue 0
3321 * Tx TC1 starts at: descriptor queue 64
3322 * Tx TC2 starts at: descriptor queue 96
3323 * Tx TC3 starts at: descriptor queue 112
3325 * Rx TC0-TC3 are offset by 32 queues each
3327 adapter->tx_ring[0].reg_idx = 0;
3328 adapter->tx_ring[1].reg_idx = 64;
3329 adapter->tx_ring[2].reg_idx = 96;
3330 adapter->tx_ring[3].reg_idx = 112;
3331 for (i = 0 ; i < dcb_i; i++)
3332 adapter->rx_ring[i].reg_idx = i << 5;
3350 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3351 * @adapter: board private structure to initialize
3353 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3356 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3361 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3362 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3363 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3364 for (i = 0; i < adapter->num_rx_queues; i++)
3365 adapter->rx_ring[i].reg_idx = i;
3366 for (i = 0; i < adapter->num_tx_queues; i++)
3367 adapter->tx_ring[i].reg_idx = i;
3376 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3377 * @adapter: board private structure to initialize
3379 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3382 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3386 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3388 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3389 #ifdef CONFIG_IXGBE_DCB
3390 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3391 ixgbe_cache_ring_dcb(adapter);
3392 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3394 #endif /* CONFIG_IXGBE_DCB */
3395 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3396 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3397 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3398 ixgbe_cache_ring_fdir(adapter);
3400 ixgbe_cache_ring_rss(adapter);
3404 for (i = 0; i < f->indices; i++, fcoe_i++)
3405 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3411 #endif /* IXGBE_FCOE */
3413 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3414 * @adapter: board private structure to initialize
3416 * Once we know the feature-set enabled for the device, we'll cache
3417 * the register offset the descriptor ring is assigned to.
3419 * Note, the order the various feature calls is important. It must start with
3420 * the "most" features enabled at the same time, then trickle down to the
3421 * least amount of features turned on at once.
3423 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3425 /* start with default case */
3426 adapter->rx_ring[0].reg_idx = 0;
3427 adapter->tx_ring[0].reg_idx = 0;
3430 if (ixgbe_cache_ring_fcoe(adapter))
3433 #endif /* IXGBE_FCOE */
3434 #ifdef CONFIG_IXGBE_DCB
3435 if (ixgbe_cache_ring_dcb(adapter))
3439 if (ixgbe_cache_ring_fdir(adapter))
3442 if (ixgbe_cache_ring_rss(adapter))
3447 * ixgbe_alloc_queues - Allocate memory for all rings
3448 * @adapter: board private structure to initialize
3450 * We allocate one ring per queue at run-time since we don't know the
3451 * number of queues at compile-time. The polling_netdev array is
3452 * intended for Multiqueue, but should work fine with a single queue.
3454 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3458 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3459 sizeof(struct ixgbe_ring), GFP_KERNEL);
3460 if (!adapter->tx_ring)
3461 goto err_tx_ring_allocation;
3463 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3464 sizeof(struct ixgbe_ring), GFP_KERNEL);
3465 if (!adapter->rx_ring)
3466 goto err_rx_ring_allocation;
3468 for (i = 0; i < adapter->num_tx_queues; i++) {
3469 adapter->tx_ring[i].count = adapter->tx_ring_count;
3470 adapter->tx_ring[i].queue_index = i;
3473 for (i = 0; i < adapter->num_rx_queues; i++) {
3474 adapter->rx_ring[i].count = adapter->rx_ring_count;
3475 adapter->rx_ring[i].queue_index = i;
3478 ixgbe_cache_ring_register(adapter);
3482 err_rx_ring_allocation:
3483 kfree(adapter->tx_ring);
3484 err_tx_ring_allocation:
3489 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3490 * @adapter: board private structure to initialize
3492 * Attempt to configure the interrupts using the best available
3493 * capabilities of the hardware and the kernel.
3495 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3497 struct ixgbe_hw *hw = &adapter->hw;
3499 int vector, v_budget;
3502 * It's easy to be greedy for MSI-X vectors, but it really
3503 * doesn't do us much good if we have a lot more vectors
3504 * than CPU's. So let's be conservative and only ask for
3505 * (roughly) twice the number of vectors as there are CPU's.
3507 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3508 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3511 * At the same time, hardware can only support a maximum of
3512 * hw.mac->max_msix_vectors vectors. With features
3513 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3514 * descriptor queues supported by our device. Thus, we cap it off in
3515 * those rare cases where the cpu count also exceeds our vector limit.
3517 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3519 /* A failure in MSI-X entry allocation isn't fatal, but it does
3520 * mean we disable MSI-X capabilities of the adapter. */
3521 adapter->msix_entries = kcalloc(v_budget,
3522 sizeof(struct msix_entry), GFP_KERNEL);
3523 if (adapter->msix_entries) {
3524 for (vector = 0; vector < v_budget; vector++)
3525 adapter->msix_entries[vector].entry = vector;
3527 ixgbe_acquire_msix_vectors(adapter, v_budget);
3529 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3533 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3534 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3535 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3536 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3537 adapter->atr_sample_rate = 0;
3538 ixgbe_set_num_queues(adapter);
3540 err = pci_enable_msi(adapter->pdev);
3542 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3544 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3545 "falling back to legacy. Error: %d\n", err);
3555 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3556 * @adapter: board private structure to initialize
3558 * We allocate one q_vector per queue interrupt. If allocation fails we
3561 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3563 int q_idx, num_q_vectors;
3564 struct ixgbe_q_vector *q_vector;
3566 int (*poll)(struct napi_struct *, int);
3568 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3569 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3570 napi_vectors = adapter->num_rx_queues;
3571 poll = &ixgbe_clean_rxtx_many;
3578 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3579 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3582 q_vector->adapter = adapter;
3583 q_vector->eitr = adapter->eitr_param;
3584 q_vector->v_idx = q_idx;
3585 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3586 adapter->q_vector[q_idx] = q_vector;
3594 q_vector = adapter->q_vector[q_idx];
3595 netif_napi_del(&q_vector->napi);
3597 adapter->q_vector[q_idx] = NULL;
3603 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3604 * @adapter: board private structure to initialize
3606 * This function frees the memory allocated to the q_vectors. In addition if
3607 * NAPI is enabled it will delete any references to the NAPI struct prior
3608 * to freeing the q_vector.
3610 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3612 int q_idx, num_q_vectors;
3614 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3615 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3619 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3620 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3621 adapter->q_vector[q_idx] = NULL;
3622 netif_napi_del(&q_vector->napi);
3627 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3629 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3630 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3631 pci_disable_msix(adapter->pdev);
3632 kfree(adapter->msix_entries);
3633 adapter->msix_entries = NULL;
3634 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3635 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3636 pci_disable_msi(adapter->pdev);
3642 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3643 * @adapter: board private structure to initialize
3645 * We determine which interrupt scheme to use based on...
3646 * - Kernel support (MSI, MSI-X)
3647 * - which can be user-defined (via MODULE_PARAM)
3648 * - Hardware queue count (num_*_queues)
3649 * - defined by miscellaneous hardware support/features (RSS, etc.)
3651 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3655 /* Number of supported queues */
3656 ixgbe_set_num_queues(adapter);
3658 err = ixgbe_set_interrupt_capability(adapter);
3660 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3661 goto err_set_interrupt;
3664 err = ixgbe_alloc_q_vectors(adapter);
3666 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3668 goto err_alloc_q_vectors;
3671 err = ixgbe_alloc_queues(adapter);
3673 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3674 goto err_alloc_queues;
3677 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3678 "Tx Queue count = %u\n",
3679 (adapter->num_rx_queues > 1) ? "Enabled" :
3680 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3682 set_bit(__IXGBE_DOWN, &adapter->state);
3687 ixgbe_free_q_vectors(adapter);
3688 err_alloc_q_vectors:
3689 ixgbe_reset_interrupt_capability(adapter);
3695 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3696 * @adapter: board private structure to clear interrupt scheme on
3698 * We go through and clear interrupt specific resources and reset the structure
3699 * to pre-load conditions
3701 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3703 kfree(adapter->tx_ring);
3704 kfree(adapter->rx_ring);
3705 adapter->tx_ring = NULL;
3706 adapter->rx_ring = NULL;
3708 ixgbe_free_q_vectors(adapter);
3709 ixgbe_reset_interrupt_capability(adapter);
3713 * ixgbe_sfp_timer - worker thread to find a missing module
3714 * @data: pointer to our adapter struct
3716 static void ixgbe_sfp_timer(unsigned long data)
3718 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3721 * Do the sfp_timer outside of interrupt context due to the
3722 * delays that sfp+ detection requires
3724 schedule_work(&adapter->sfp_task);
3728 * ixgbe_sfp_task - worker thread to find a missing module
3729 * @work: pointer to work_struct containing our data
3731 static void ixgbe_sfp_task(struct work_struct *work)
3733 struct ixgbe_adapter *adapter = container_of(work,
3734 struct ixgbe_adapter,
3736 struct ixgbe_hw *hw = &adapter->hw;
3738 if ((hw->phy.type == ixgbe_phy_nl) &&
3739 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3740 s32 ret = hw->phy.ops.identify_sfp(hw);
3741 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3743 ret = hw->phy.ops.reset(hw);
3744 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3745 dev_err(&adapter->pdev->dev, "failed to initialize "
3746 "because an unsupported SFP+ module type "
3748 "Reload the driver after installing a "
3749 "supported module.\n");
3750 unregister_netdev(adapter->netdev);
3752 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3755 /* don't need this routine any more */
3756 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3760 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3761 mod_timer(&adapter->sfp_timer,
3762 round_jiffies(jiffies + (2 * HZ)));
3766 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3767 * @adapter: board private structure to initialize
3769 * ixgbe_sw_init initializes the Adapter private data structure.
3770 * Fields are initialized based on PCI device information and
3771 * OS network device settings (MTU size).
3773 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3775 struct ixgbe_hw *hw = &adapter->hw;
3776 struct pci_dev *pdev = adapter->pdev;
3778 #ifdef CONFIG_IXGBE_DCB
3780 struct tc_configuration *tc;
3783 /* PCI config space info */
3785 hw->vendor_id = pdev->vendor;
3786 hw->device_id = pdev->device;
3787 hw->revision_id = pdev->revision;
3788 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3789 hw->subsystem_device_id = pdev->subsystem_device;
3791 /* Set capability flags */
3792 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3793 adapter->ring_feature[RING_F_RSS].indices = rss;
3794 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3795 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3796 if (hw->mac.type == ixgbe_mac_82598EB) {
3797 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3798 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3799 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3800 } else if (hw->mac.type == ixgbe_mac_82599EB) {
3801 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3802 adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE;
3803 adapter->flags |= IXGBE_FLAG2_RSC_ENABLED;
3804 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3805 adapter->ring_feature[RING_F_FDIR].indices =
3806 IXGBE_MAX_FDIR_INDICES;
3807 adapter->atr_sample_rate = 20;
3808 adapter->fdir_pballoc = 0;
3810 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3811 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3812 adapter->ring_feature[RING_F_FCOE].indices = 0;
3813 #endif /* IXGBE_FCOE */
3816 #ifdef CONFIG_IXGBE_DCB
3817 /* Configure DCB traffic classes */
3818 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3819 tc = &adapter->dcb_cfg.tc_config[j];
3820 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3821 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3822 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3823 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3824 tc->dcb_pfc = pfc_disabled;
3826 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3827 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3828 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3829 adapter->dcb_cfg.pfc_mode_enable = false;
3830 adapter->dcb_cfg.round_robin_enable = false;
3831 adapter->dcb_set_bitmap = 0x00;
3832 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3833 adapter->ring_feature[RING_F_DCB].indices);
3837 /* default flow control settings */
3838 hw->fc.requested_mode = ixgbe_fc_full;
3839 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
3841 adapter->last_lfc_mode = hw->fc.current_mode;
3843 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3844 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3845 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3846 hw->fc.send_xon = true;
3847 hw->fc.disable_fc_autoneg = false;
3849 /* enable itr by default in dynamic mode */
3850 adapter->itr_setting = 1;
3851 adapter->eitr_param = 20000;
3853 /* set defaults for eitr in MegaBytes */
3854 adapter->eitr_low = 10;
3855 adapter->eitr_high = 20;
3857 /* set default ring sizes */
3858 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3859 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3861 /* initialize eeprom parameters */
3862 if (ixgbe_init_eeprom_params_generic(hw)) {
3863 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3867 /* enable rx csum by default */
3868 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3870 set_bit(__IXGBE_DOWN, &adapter->state);
3876 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3877 * @adapter: board private structure
3878 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3880 * Return 0 on success, negative on failure
3882 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3883 struct ixgbe_ring *tx_ring)
3885 struct pci_dev *pdev = adapter->pdev;
3888 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3889 tx_ring->tx_buffer_info = vmalloc(size);
3890 if (!tx_ring->tx_buffer_info)
3892 memset(tx_ring->tx_buffer_info, 0, size);
3894 /* round up to nearest 4K */
3895 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3896 tx_ring->size = ALIGN(tx_ring->size, 4096);
3898 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3903 tx_ring->next_to_use = 0;
3904 tx_ring->next_to_clean = 0;
3905 tx_ring->work_limit = tx_ring->count;
3909 vfree(tx_ring->tx_buffer_info);
3910 tx_ring->tx_buffer_info = NULL;
3911 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3912 "descriptor ring\n");
3917 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3918 * @adapter: board private structure
3920 * If this function returns with an error, then it's possible one or
3921 * more of the rings is populated (while the rest are not). It is the
3922 * callers duty to clean those orphaned rings.
3924 * Return 0 on success, negative on failure
3926 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3930 for (i = 0; i < adapter->num_tx_queues; i++) {
3931 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3934 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3942 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3943 * @adapter: board private structure
3944 * @rx_ring: rx descriptor ring (for a specific queue) to setup
3946 * Returns 0 on success, negative on failure
3948 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3949 struct ixgbe_ring *rx_ring)
3951 struct pci_dev *pdev = adapter->pdev;
3954 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3955 rx_ring->rx_buffer_info = vmalloc(size);
3956 if (!rx_ring->rx_buffer_info) {
3958 "vmalloc allocation failed for the rx desc ring\n");
3961 memset(rx_ring->rx_buffer_info, 0, size);
3963 /* Round up to nearest 4K */
3964 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3965 rx_ring->size = ALIGN(rx_ring->size, 4096);
3967 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3969 if (!rx_ring->desc) {
3971 "Memory allocation failed for the rx desc ring\n");
3972 vfree(rx_ring->rx_buffer_info);
3976 rx_ring->next_to_clean = 0;
3977 rx_ring->next_to_use = 0;
3986 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3987 * @adapter: board private structure
3989 * If this function returns with an error, then it's possible one or
3990 * more of the rings is populated (while the rest are not). It is the
3991 * callers duty to clean those orphaned rings.
3993 * Return 0 on success, negative on failure
3996 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4000 for (i = 0; i < adapter->num_rx_queues; i++) {
4001 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4004 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4012 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4013 * @adapter: board private structure
4014 * @tx_ring: Tx descriptor ring for a specific queue
4016 * Free all transmit software resources
4018 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4019 struct ixgbe_ring *tx_ring)
4021 struct pci_dev *pdev = adapter->pdev;
4023 ixgbe_clean_tx_ring(adapter, tx_ring);
4025 vfree(tx_ring->tx_buffer_info);
4026 tx_ring->tx_buffer_info = NULL;
4028 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4030 tx_ring->desc = NULL;
4034 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4035 * @adapter: board private structure
4037 * Free all transmit software resources
4039 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4043 for (i = 0; i < adapter->num_tx_queues; i++)
4044 if (adapter->tx_ring[i].desc)
4045 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4049 * ixgbe_free_rx_resources - Free Rx Resources
4050 * @adapter: board private structure
4051 * @rx_ring: ring to clean the resources from
4053 * Free all receive software resources
4055 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4056 struct ixgbe_ring *rx_ring)
4058 struct pci_dev *pdev = adapter->pdev;
4060 ixgbe_clean_rx_ring(adapter, rx_ring);
4062 vfree(rx_ring->rx_buffer_info);
4063 rx_ring->rx_buffer_info = NULL;
4065 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4067 rx_ring->desc = NULL;
4071 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4072 * @adapter: board private structure
4074 * Free all receive software resources
4076 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4080 for (i = 0; i < adapter->num_rx_queues; i++)
4081 if (adapter->rx_ring[i].desc)
4082 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4086 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4087 * @netdev: network interface device structure
4088 * @new_mtu: new value for maximum frame size
4090 * Returns 0 on success, negative on failure
4092 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4094 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4095 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4097 /* MTU < 68 is an error and causes problems on some kernels */
4098 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4101 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4102 netdev->mtu, new_mtu);
4103 /* must set new MTU before calling down or up */
4104 netdev->mtu = new_mtu;
4106 if (netif_running(netdev))
4107 ixgbe_reinit_locked(adapter);
4113 * ixgbe_open - Called when a network interface is made active
4114 * @netdev: network interface device structure
4116 * Returns 0 on success, negative value on failure
4118 * The open entry point is called when a network interface is made
4119 * active by the system (IFF_UP). At this point all resources needed
4120 * for transmit and receive operations are allocated, the interrupt
4121 * handler is registered with the OS, the watchdog timer is started,
4122 * and the stack is notified that the interface is ready.
4124 static int ixgbe_open(struct net_device *netdev)
4126 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4129 /* disallow open during test */
4130 if (test_bit(__IXGBE_TESTING, &adapter->state))
4133 netif_carrier_off(netdev);
4135 /* allocate transmit descriptors */
4136 err = ixgbe_setup_all_tx_resources(adapter);
4140 /* allocate receive descriptors */
4141 err = ixgbe_setup_all_rx_resources(adapter);
4145 ixgbe_configure(adapter);
4147 err = ixgbe_request_irq(adapter);
4151 err = ixgbe_up_complete(adapter);
4155 netif_tx_start_all_queues(netdev);
4160 ixgbe_release_hw_control(adapter);
4161 ixgbe_free_irq(adapter);
4164 ixgbe_free_all_rx_resources(adapter);
4166 ixgbe_free_all_tx_resources(adapter);
4167 ixgbe_reset(adapter);
4173 * ixgbe_close - Disables a network interface
4174 * @netdev: network interface device structure
4176 * Returns 0, this is not allowed to fail
4178 * The close entry point is called when an interface is de-activated
4179 * by the OS. The hardware is still under the drivers control, but
4180 * needs to be disabled. A global MAC reset is issued to stop the
4181 * hardware, and all transmit and receive resources are freed.
4183 static int ixgbe_close(struct net_device *netdev)
4185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4187 ixgbe_down(adapter);
4188 ixgbe_free_irq(adapter);
4190 ixgbe_free_all_tx_resources(adapter);
4191 ixgbe_free_all_rx_resources(adapter);
4193 ixgbe_release_hw_control(adapter);
4199 static int ixgbe_resume(struct pci_dev *pdev)
4201 struct net_device *netdev = pci_get_drvdata(pdev);
4202 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4205 pci_set_power_state(pdev, PCI_D0);
4206 pci_restore_state(pdev);
4208 err = pci_enable_device_mem(pdev);
4210 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4214 pci_set_master(pdev);
4216 pci_wake_from_d3(pdev, false);
4218 err = ixgbe_init_interrupt_scheme(adapter);
4220 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4225 ixgbe_reset(adapter);
4227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4229 if (netif_running(netdev)) {
4230 err = ixgbe_open(adapter->netdev);
4235 netif_device_attach(netdev);
4239 #endif /* CONFIG_PM */
4241 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4243 struct net_device *netdev = pci_get_drvdata(pdev);
4244 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4245 struct ixgbe_hw *hw = &adapter->hw;
4247 u32 wufc = adapter->wol;
4252 netif_device_detach(netdev);
4254 if (netif_running(netdev)) {
4255 ixgbe_down(adapter);
4256 ixgbe_free_irq(adapter);
4257 ixgbe_free_all_tx_resources(adapter);
4258 ixgbe_free_all_rx_resources(adapter);
4260 ixgbe_clear_interrupt_scheme(adapter);
4263 retval = pci_save_state(pdev);
4269 ixgbe_set_rx_mode(netdev);
4271 /* turn on all-multi mode if wake on multicast is enabled */
4272 if (wufc & IXGBE_WUFC_MC) {
4273 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4274 fctrl |= IXGBE_FCTRL_MPE;
4275 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4278 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4279 ctrl |= IXGBE_CTRL_GIO_DIS;
4280 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4282 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4284 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4285 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4288 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4289 pci_wake_from_d3(pdev, true);
4291 pci_wake_from_d3(pdev, false);
4293 *enable_wake = !!wufc;
4295 ixgbe_release_hw_control(adapter);
4297 pci_disable_device(pdev);
4303 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4308 retval = __ixgbe_shutdown(pdev, &wake);
4313 pci_prepare_to_sleep(pdev);
4315 pci_wake_from_d3(pdev, false);
4316 pci_set_power_state(pdev, PCI_D3hot);
4321 #endif /* CONFIG_PM */
4323 static void ixgbe_shutdown(struct pci_dev *pdev)
4327 __ixgbe_shutdown(pdev, &wake);
4329 if (system_state == SYSTEM_POWER_OFF) {
4330 pci_wake_from_d3(pdev, wake);
4331 pci_set_power_state(pdev, PCI_D3hot);
4336 * ixgbe_update_stats - Update the board statistics counters.
4337 * @adapter: board private structure
4339 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4341 struct ixgbe_hw *hw = &adapter->hw;
4343 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4345 if (hw->mac.type == ixgbe_mac_82599EB) {
4347 for (i = 0; i < 16; i++)
4348 adapter->hw_rx_no_dma_resources +=
4349 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4350 for (i = 0; i < adapter->num_rx_queues; i++)
4351 rsc_count += adapter->rx_ring[i].rsc_count;
4352 adapter->rsc_count = rsc_count;
4355 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4356 for (i = 0; i < 8; i++) {
4357 /* for packet buffers not used, the register should read 0 */
4358 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4360 adapter->stats.mpc[i] += mpc;
4361 total_mpc += adapter->stats.mpc[i];
4362 if (hw->mac.type == ixgbe_mac_82598EB)
4363 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4364 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4365 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4366 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4367 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4368 if (hw->mac.type == ixgbe_mac_82599EB) {
4369 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4370 IXGBE_PXONRXCNT(i));
4371 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4372 IXGBE_PXOFFRXCNT(i));
4373 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4375 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4377 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4380 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4382 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4385 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4386 /* work around hardware counting issue */
4387 adapter->stats.gprc -= missed_rx;
4389 /* 82598 hardware only has a 32 bit counter in the high register */
4390 if (hw->mac.type == ixgbe_mac_82599EB) {
4391 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4392 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4393 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4394 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4395 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4396 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4397 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4398 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4399 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4400 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4402 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4403 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4404 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4405 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4406 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4407 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4408 #endif /* IXGBE_FCOE */
4410 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4411 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4412 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4413 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4414 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4416 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4417 adapter->stats.bprc += bprc;
4418 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4419 if (hw->mac.type == ixgbe_mac_82598EB)
4420 adapter->stats.mprc -= bprc;
4421 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4422 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4423 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4424 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4425 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4426 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4427 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4428 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4429 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4430 adapter->stats.lxontxc += lxon;
4431 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4432 adapter->stats.lxofftxc += lxoff;
4433 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4434 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4435 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4437 * 82598 errata - tx of flow control packets is included in tx counters
4439 xon_off_tot = lxon + lxoff;
4440 adapter->stats.gptc -= xon_off_tot;
4441 adapter->stats.mptc -= xon_off_tot;
4442 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4443 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4444 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4445 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4446 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4447 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4448 adapter->stats.ptc64 -= xon_off_tot;
4449 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4450 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4451 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4452 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4453 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4454 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4456 /* Fill out the OS statistics structure */
4457 adapter->net_stats.multicast = adapter->stats.mprc;
4460 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4461 adapter->stats.rlec;
4462 adapter->net_stats.rx_dropped = 0;
4463 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4464 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4465 adapter->net_stats.rx_missed_errors = total_mpc;
4469 * ixgbe_watchdog - Timer Call-back
4470 * @data: pointer to adapter cast into an unsigned long
4472 static void ixgbe_watchdog(unsigned long data)
4474 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4475 struct ixgbe_hw *hw = &adapter->hw;
4480 * Do the watchdog outside of interrupt context due to the lovely
4481 * delays that some of the newer hardware requires
4484 if (test_bit(__IXGBE_DOWN, &adapter->state))
4485 goto watchdog_short_circuit;
4487 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4489 * for legacy and MSI interrupts don't set any bits
4490 * that are enabled for EIAM, because this operation
4491 * would set *both* EIMS and EICS for any bit in EIAM
4493 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4494 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4495 goto watchdog_reschedule;
4498 /* get one bit for every active tx/rx interrupt vector */
4499 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4500 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4501 if (qv->rxr_count || qv->txr_count)
4502 eics |= ((u64)1 << i);
4505 /* Cause software interrupt to ensure rx rings are cleaned */
4506 ixgbe_irq_rearm_queues(adapter, eics);
4508 watchdog_reschedule:
4509 /* Reset the timer */
4510 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4512 watchdog_short_circuit:
4513 schedule_work(&adapter->watchdog_task);
4517 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4518 * @work: pointer to work_struct containing our data
4520 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4522 struct ixgbe_adapter *adapter = container_of(work,
4523 struct ixgbe_adapter,
4524 multispeed_fiber_task);
4525 struct ixgbe_hw *hw = &adapter->hw;
4528 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4529 autoneg = hw->phy.autoneg_advertised;
4530 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4531 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4533 if (hw->mac.ops.setup_link_speed)
4534 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4535 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4536 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4540 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4541 * @work: pointer to work_struct containing our data
4543 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4545 struct ixgbe_adapter *adapter = container_of(work,
4546 struct ixgbe_adapter,
4547 sfp_config_module_task);
4548 struct ixgbe_hw *hw = &adapter->hw;
4551 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4553 /* Time for electrical oscillations to settle down */
4555 err = hw->phy.ops.identify_sfp(hw);
4557 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4558 dev_err(&adapter->pdev->dev, "failed to initialize because "
4559 "an unsupported SFP+ module type was detected.\n"
4560 "Reload the driver after installing a supported "
4562 unregister_netdev(adapter->netdev);
4565 hw->mac.ops.setup_sfp(hw);
4567 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4568 /* This will also work for DA Twinax connections */
4569 schedule_work(&adapter->multispeed_fiber_task);
4570 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4574 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4575 * @work: pointer to work_struct containing our data
4577 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4579 struct ixgbe_adapter *adapter = container_of(work,
4580 struct ixgbe_adapter,
4582 struct ixgbe_hw *hw = &adapter->hw;
4585 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4586 for (i = 0; i < adapter->num_tx_queues; i++)
4587 set_bit(__IXGBE_FDIR_INIT_DONE,
4588 &(adapter->tx_ring[i].reinit_state));
4590 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4591 "ignored adding FDIR ATR filters \n");
4593 /* Done FDIR Re-initialization, enable transmits */
4594 netif_tx_start_all_queues(adapter->netdev);
4598 * ixgbe_watchdog_task - worker thread to bring link up
4599 * @work: pointer to work_struct containing our data
4601 static void ixgbe_watchdog_task(struct work_struct *work)
4603 struct ixgbe_adapter *adapter = container_of(work,
4604 struct ixgbe_adapter,
4606 struct net_device *netdev = adapter->netdev;
4607 struct ixgbe_hw *hw = &adapter->hw;
4608 u32 link_speed = adapter->link_speed;
4609 bool link_up = adapter->link_up;
4611 struct ixgbe_ring *tx_ring;
4612 int some_tx_pending = 0;
4614 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4616 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4617 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4620 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4621 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4622 hw->mac.ops.fc_enable(hw, i);
4624 hw->mac.ops.fc_enable(hw, 0);
4627 hw->mac.ops.fc_enable(hw, 0);
4632 time_after(jiffies, (adapter->link_check_timeout +
4633 IXGBE_TRY_LINK_TIMEOUT))) {
4634 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4635 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4637 adapter->link_up = link_up;
4638 adapter->link_speed = link_speed;
4642 if (!netif_carrier_ok(netdev)) {
4643 bool flow_rx, flow_tx;
4645 if (hw->mac.type == ixgbe_mac_82599EB) {
4646 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4647 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4648 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4649 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4651 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4652 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4653 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4654 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4657 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4658 "Flow Control: %s\n",
4660 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4662 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4663 "1 Gbps" : "unknown speed")),
4664 ((flow_rx && flow_tx) ? "RX/TX" :
4666 (flow_tx ? "TX" : "None"))));
4668 netif_carrier_on(netdev);
4670 /* Force detection of hung controller */
4671 adapter->detect_tx_hung = true;
4674 adapter->link_up = false;
4675 adapter->link_speed = 0;
4676 if (netif_carrier_ok(netdev)) {
4677 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4679 netif_carrier_off(netdev);
4683 if (!netif_carrier_ok(netdev)) {
4684 for (i = 0; i < adapter->num_tx_queues; i++) {
4685 tx_ring = &adapter->tx_ring[i];
4686 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4687 some_tx_pending = 1;
4692 if (some_tx_pending) {
4693 /* We've lost link, so the controller stops DMA,
4694 * but we've got queued Tx work that's never going
4695 * to get done, so reset controller to flush Tx.
4696 * (Do the reset outside of interrupt context).
4698 schedule_work(&adapter->reset_task);
4702 ixgbe_update_stats(adapter);
4703 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4706 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4707 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4708 u32 tx_flags, u8 *hdr_len)
4710 struct ixgbe_adv_tx_context_desc *context_desc;
4713 struct ixgbe_tx_buffer *tx_buffer_info;
4714 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4715 u32 mss_l4len_idx, l4len;
4717 if (skb_is_gso(skb)) {
4718 if (skb_header_cloned(skb)) {
4719 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4723 l4len = tcp_hdrlen(skb);
4726 if (skb->protocol == htons(ETH_P_IP)) {
4727 struct iphdr *iph = ip_hdr(skb);
4730 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4734 adapter->hw_tso_ctxt++;
4735 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4736 ipv6_hdr(skb)->payload_len = 0;
4737 tcp_hdr(skb)->check =
4738 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4739 &ipv6_hdr(skb)->daddr,
4741 adapter->hw_tso6_ctxt++;
4744 i = tx_ring->next_to_use;
4746 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4747 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4749 /* VLAN MACLEN IPLEN */
4750 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4752 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4753 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4754 IXGBE_ADVTXD_MACLEN_SHIFT);
4755 *hdr_len += skb_network_offset(skb);
4757 (skb_transport_header(skb) - skb_network_header(skb));
4759 (skb_transport_header(skb) - skb_network_header(skb));
4760 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4761 context_desc->seqnum_seed = 0;
4763 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4764 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4765 IXGBE_ADVTXD_DTYP_CTXT);
4767 if (skb->protocol == htons(ETH_P_IP))
4768 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4769 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4770 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4774 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4775 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4776 /* use index 1 for TSO */
4777 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4778 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4780 tx_buffer_info->time_stamp = jiffies;
4781 tx_buffer_info->next_to_watch = i;
4784 if (i == tx_ring->count)
4786 tx_ring->next_to_use = i;
4793 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4794 struct ixgbe_ring *tx_ring,
4795 struct sk_buff *skb, u32 tx_flags)
4797 struct ixgbe_adv_tx_context_desc *context_desc;
4799 struct ixgbe_tx_buffer *tx_buffer_info;
4800 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4802 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4803 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4804 i = tx_ring->next_to_use;
4805 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4806 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4808 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4810 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4811 vlan_macip_lens |= (skb_network_offset(skb) <<
4812 IXGBE_ADVTXD_MACLEN_SHIFT);
4813 if (skb->ip_summed == CHECKSUM_PARTIAL)
4814 vlan_macip_lens |= (skb_transport_header(skb) -
4815 skb_network_header(skb));
4817 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4818 context_desc->seqnum_seed = 0;
4820 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4821 IXGBE_ADVTXD_DTYP_CTXT);
4823 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4824 switch (skb->protocol) {
4825 case cpu_to_be16(ETH_P_IP):
4826 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4827 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4829 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4830 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4832 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4834 case cpu_to_be16(ETH_P_IPV6):
4835 /* XXX what about other V6 headers?? */
4836 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4838 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4839 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4841 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4844 if (unlikely(net_ratelimit())) {
4845 DPRINTK(PROBE, WARNING,
4846 "partial checksum but proto=%x!\n",
4853 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4854 /* use index zero for tx checksum offload */
4855 context_desc->mss_l4len_idx = 0;
4857 tx_buffer_info->time_stamp = jiffies;
4858 tx_buffer_info->next_to_watch = i;
4860 adapter->hw_csum_tx_good++;
4862 if (i == tx_ring->count)
4864 tx_ring->next_to_use = i;
4872 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4873 struct ixgbe_ring *tx_ring,
4874 struct sk_buff *skb, u32 tx_flags,
4877 struct ixgbe_tx_buffer *tx_buffer_info;
4879 unsigned int total = skb->len;
4880 unsigned int offset = 0, size, count = 0, i;
4881 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4885 i = tx_ring->next_to_use;
4887 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4888 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4892 map = skb_shinfo(skb)->dma_maps;
4894 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4895 /* excluding fcoe_crc_eof for FCoE */
4896 total -= sizeof(struct fcoe_crc_eof);
4898 len = min(skb_headlen(skb), total);
4900 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4901 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4903 tx_buffer_info->length = size;
4904 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4905 tx_buffer_info->time_stamp = jiffies;
4906 tx_buffer_info->next_to_watch = i;
4915 if (i == tx_ring->count)
4920 for (f = 0; f < nr_frags; f++) {
4921 struct skb_frag_struct *frag;
4923 frag = &skb_shinfo(skb)->frags[f];
4924 len = min((unsigned int)frag->size, total);
4929 if (i == tx_ring->count)
4932 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4933 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4935 tx_buffer_info->length = size;
4936 tx_buffer_info->dma = map[f] + offset;
4937 tx_buffer_info->time_stamp = jiffies;
4938 tx_buffer_info->next_to_watch = i;
4949 tx_ring->tx_buffer_info[i].skb = skb;
4950 tx_ring->tx_buffer_info[first].next_to_watch = i;
4955 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4956 struct ixgbe_ring *tx_ring,
4957 int tx_flags, int count, u32 paylen, u8 hdr_len)
4959 union ixgbe_adv_tx_desc *tx_desc = NULL;
4960 struct ixgbe_tx_buffer *tx_buffer_info;
4961 u32 olinfo_status = 0, cmd_type_len = 0;
4963 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4965 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4967 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4969 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4970 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4972 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4973 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4975 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4976 IXGBE_ADVTXD_POPTS_SHIFT;
4978 /* use index 1 context for tso */
4979 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4980 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4981 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4982 IXGBE_ADVTXD_POPTS_SHIFT;
4984 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4985 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4986 IXGBE_ADVTXD_POPTS_SHIFT;
4988 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4989 olinfo_status |= IXGBE_ADVTXD_CC;
4990 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4991 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4992 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4995 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4997 i = tx_ring->next_to_use;
4999 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5000 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5001 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5002 tx_desc->read.cmd_type_len =
5003 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5004 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5006 if (i == tx_ring->count)
5010 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5013 * Force memory writes to complete before letting h/w
5014 * know there are new descriptors to fetch. (Only
5015 * applicable for weak-ordered memory model archs,
5020 tx_ring->next_to_use = i;
5021 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5024 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5025 int queue, u32 tx_flags)
5027 /* Right now, we support IPv4 only */
5028 struct ixgbe_atr_input atr_input;
5031 struct iphdr *iph = ip_hdr(skb);
5032 struct ethhdr *eth = (struct ethhdr *)skb->data;
5033 u16 vlan_id, src_port, dst_port, flex_bytes;
5034 u32 src_ipv4_addr, dst_ipv4_addr;
5037 /* check if we're UDP or TCP */
5038 if (iph->protocol == IPPROTO_TCP) {
5040 src_port = th->source;
5041 dst_port = th->dest;
5042 l4type |= IXGBE_ATR_L4TYPE_TCP;
5043 /* l4type IPv4 type is 0, no need to assign */
5044 } else if(iph->protocol == IPPROTO_UDP) {
5046 src_port = uh->source;
5047 dst_port = uh->dest;
5048 l4type |= IXGBE_ATR_L4TYPE_UDP;
5049 /* l4type IPv4 type is 0, no need to assign */
5051 /* Unsupported L4 header, just bail here */
5055 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5057 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5058 IXGBE_TX_FLAGS_VLAN_SHIFT;
5059 src_ipv4_addr = iph->saddr;
5060 dst_ipv4_addr = iph->daddr;
5061 flex_bytes = eth->h_proto;
5063 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5064 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5065 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5066 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5067 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5068 /* src and dst are inverted, think how the receiver sees them */
5069 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5070 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5072 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5073 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5076 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5077 struct ixgbe_ring *tx_ring, int size)
5079 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5081 netif_stop_subqueue(netdev, tx_ring->queue_index);
5082 /* Herbert's original patch had:
5083 * smp_mb__after_netif_stop_queue();
5084 * but since that doesn't exist yet, just open code it. */
5087 /* We need to check again in a case another CPU has just
5088 * made room available. */
5089 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5092 /* A reprieve! - use start_queue because it doesn't call schedule */
5093 netif_start_subqueue(netdev, tx_ring->queue_index);
5094 ++adapter->restart_queue;
5098 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5099 struct ixgbe_ring *tx_ring, int size)
5101 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5103 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5106 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5108 struct ixgbe_adapter *adapter = netdev_priv(dev);
5110 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5111 return smp_processor_id();
5113 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5114 return 0; /* All traffic should default to class 0 */
5116 return skb_tx_hash(dev, skb);
5119 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5121 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5122 struct ixgbe_ring *tx_ring;
5124 unsigned int tx_flags = 0;
5130 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5131 tx_flags |= vlan_tx_tag_get(skb);
5132 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5133 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5134 tx_flags |= (skb->queue_mapping << 13);
5136 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5137 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5138 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5139 if (skb->priority != TC_PRIO_CONTROL) {
5140 tx_flags |= (skb->queue_mapping << 13);
5141 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5142 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5144 skb->queue_mapping =
5145 adapter->ring_feature[RING_F_DCB].indices-1;
5149 r_idx = skb->queue_mapping;
5150 tx_ring = &adapter->tx_ring[r_idx];
5152 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5153 (skb->protocol == htons(ETH_P_FCOE)))
5154 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5156 /* four things can cause us to need a context descriptor */
5157 if (skb_is_gso(skb) ||
5158 (skb->ip_summed == CHECKSUM_PARTIAL) ||
5159 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5160 (tx_flags & IXGBE_TX_FLAGS_FCOE))
5163 count += TXD_USE_COUNT(skb_headlen(skb));
5164 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5165 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5167 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5169 return NETDEV_TX_BUSY;
5172 first = tx_ring->next_to_use;
5173 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5175 /* setup tx offload for FCoE */
5176 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5178 dev_kfree_skb_any(skb);
5179 return NETDEV_TX_OK;
5182 tx_flags |= IXGBE_TX_FLAGS_FSO;
5183 #endif /* IXGBE_FCOE */
5185 if (skb->protocol == htons(ETH_P_IP))
5186 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5187 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5189 dev_kfree_skb_any(skb);
5190 return NETDEV_TX_OK;
5194 tx_flags |= IXGBE_TX_FLAGS_TSO;
5195 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5196 (skb->ip_summed == CHECKSUM_PARTIAL))
5197 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5200 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5202 /* add the ATR filter if ATR is on */
5203 if (tx_ring->atr_sample_rate) {
5204 ++tx_ring->atr_count;
5205 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5206 test_bit(__IXGBE_FDIR_INIT_DONE,
5207 &tx_ring->reinit_state)) {
5208 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5210 tx_ring->atr_count = 0;
5213 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5215 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5218 dev_kfree_skb_any(skb);
5219 tx_ring->tx_buffer_info[first].time_stamp = 0;
5220 tx_ring->next_to_use = first;
5223 return NETDEV_TX_OK;
5227 * ixgbe_get_stats - Get System Network Statistics
5228 * @netdev: network interface device structure
5230 * Returns the address of the device statistics structure.
5231 * The statistics are actually updated from the timer callback.
5233 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5235 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5237 /* only return the current stats */
5238 return &adapter->net_stats;
5242 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5243 * @netdev: network interface device structure
5244 * @p: pointer to an address structure
5246 * Returns 0 on success, negative on failure
5248 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5251 struct ixgbe_hw *hw = &adapter->hw;
5252 struct sockaddr *addr = p;
5254 if (!is_valid_ether_addr(addr->sa_data))
5255 return -EADDRNOTAVAIL;
5257 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5258 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5260 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5266 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5269 struct ixgbe_hw *hw = &adapter->hw;
5273 if (prtad != hw->phy.mdio.prtad)
5275 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5281 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5282 u16 addr, u16 value)
5284 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5285 struct ixgbe_hw *hw = &adapter->hw;
5287 if (prtad != hw->phy.mdio.prtad)
5289 return hw->phy.ops.write_reg(hw, addr, devad, value);
5292 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5294 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5296 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5300 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5302 * @netdev: network interface device structure
5304 * Returns non-zero on failure
5306 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5309 struct ixgbe_adapter *adapter = netdev_priv(dev);
5310 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5312 if (is_valid_ether_addr(mac->san_addr)) {
5314 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5321 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5323 * @netdev: network interface device structure
5325 * Returns non-zero on failure
5327 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5330 struct ixgbe_adapter *adapter = netdev_priv(dev);
5331 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5333 if (is_valid_ether_addr(mac->san_addr)) {
5335 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5341 #ifdef CONFIG_NET_POLL_CONTROLLER
5343 * Polling 'interrupt' - used by things like netconsole to send skbs
5344 * without having to re-enable interrupts. It's not called while
5345 * the interrupt routine is executing.
5347 static void ixgbe_netpoll(struct net_device *netdev)
5349 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5351 disable_irq(adapter->pdev->irq);
5352 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5353 ixgbe_intr(adapter->pdev->irq, netdev);
5354 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5355 enable_irq(adapter->pdev->irq);
5359 static const struct net_device_ops ixgbe_netdev_ops = {
5360 .ndo_open = ixgbe_open,
5361 .ndo_stop = ixgbe_close,
5362 .ndo_start_xmit = ixgbe_xmit_frame,
5363 .ndo_select_queue = ixgbe_select_queue,
5364 .ndo_get_stats = ixgbe_get_stats,
5365 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5366 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5367 .ndo_validate_addr = eth_validate_addr,
5368 .ndo_set_mac_address = ixgbe_set_mac,
5369 .ndo_change_mtu = ixgbe_change_mtu,
5370 .ndo_tx_timeout = ixgbe_tx_timeout,
5371 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5372 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5373 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5374 .ndo_do_ioctl = ixgbe_ioctl,
5375 #ifdef CONFIG_NET_POLL_CONTROLLER
5376 .ndo_poll_controller = ixgbe_netpoll,
5379 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5380 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5381 #endif /* IXGBE_FCOE */
5385 * ixgbe_probe - Device Initialization Routine
5386 * @pdev: PCI device information struct
5387 * @ent: entry in ixgbe_pci_tbl
5389 * Returns 0 on success, negative on failure
5391 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5392 * The OS initialization, configuring of the adapter private structure,
5393 * and a hardware reset occur.
5395 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5396 const struct pci_device_id *ent)
5398 struct net_device *netdev;
5399 struct ixgbe_adapter *adapter = NULL;
5400 struct ixgbe_hw *hw;
5401 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5402 static int cards_found;
5403 int i, err, pci_using_dac;
5409 err = pci_enable_device_mem(pdev);
5413 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5414 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5417 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5419 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5421 dev_err(&pdev->dev, "No usable DMA "
5422 "configuration, aborting\n");
5429 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5430 IORESOURCE_MEM), ixgbe_driver_name);
5433 "pci_request_selected_regions failed 0x%x\n", err);
5437 err = pci_enable_pcie_error_reporting(pdev);
5439 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5441 /* non-fatal, continue */
5444 pci_set_master(pdev);
5445 pci_save_state(pdev);
5447 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5450 goto err_alloc_etherdev;
5453 SET_NETDEV_DEV(netdev, &pdev->dev);
5455 pci_set_drvdata(pdev, netdev);
5456 adapter = netdev_priv(netdev);
5458 adapter->netdev = netdev;
5459 adapter->pdev = pdev;
5462 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5464 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5465 pci_resource_len(pdev, 0));
5471 for (i = 1; i <= 5; i++) {
5472 if (pci_resource_len(pdev, i) == 0)
5476 netdev->netdev_ops = &ixgbe_netdev_ops;
5477 ixgbe_set_ethtool_ops(netdev);
5478 netdev->watchdog_timeo = 5 * HZ;
5479 strcpy(netdev->name, pci_name(pdev));
5481 adapter->bd_number = cards_found;
5484 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5485 hw->mac.type = ii->mac;
5488 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5489 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5490 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5491 if (!(eec & (1 << 8)))
5492 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5495 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5496 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5497 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5498 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5499 hw->phy.mdio.mmds = 0;
5500 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5501 hw->phy.mdio.dev = netdev;
5502 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5503 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5505 /* set up this timer and work struct before calling get_invariants
5506 * which might start the timer
5508 init_timer(&adapter->sfp_timer);
5509 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5510 adapter->sfp_timer.data = (unsigned long) adapter;
5512 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5514 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5515 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5517 /* a new SFP+ module arrival, called from GPI SDP2 context */
5518 INIT_WORK(&adapter->sfp_config_module_task,
5519 ixgbe_sfp_config_module_task);
5521 ii->get_invariants(hw);
5523 /* setup the private structure */
5524 err = ixgbe_sw_init(adapter);
5529 * If there is a fan on this device and it has failed log the
5532 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5533 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5534 if (esdp & IXGBE_ESDP_SDP1)
5535 DPRINTK(PROBE, CRIT,
5536 "Fan has stopped, replace the adapter\n");
5539 /* reset_hw fills in the perm_addr as well */
5540 err = hw->mac.ops.reset_hw(hw);
5541 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5542 hw->mac.type == ixgbe_mac_82598EB) {
5544 * Start a kernel thread to watch for a module to arrive.
5545 * Only do this for 82598, since 82599 will generate
5546 * interrupts on module arrival.
5548 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5549 mod_timer(&adapter->sfp_timer,
5550 round_jiffies(jiffies + (2 * HZ)));
5552 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5553 dev_err(&adapter->pdev->dev, "failed to initialize because "
5554 "an unsupported SFP+ module type was detected.\n"
5555 "Reload the driver after installing a supported "
5559 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5563 netdev->features = NETIF_F_SG |
5565 NETIF_F_HW_VLAN_TX |
5566 NETIF_F_HW_VLAN_RX |
5567 NETIF_F_HW_VLAN_FILTER;
5569 netdev->features |= NETIF_F_IPV6_CSUM;
5570 netdev->features |= NETIF_F_TSO;
5571 netdev->features |= NETIF_F_TSO6;
5572 netdev->features |= NETIF_F_GRO;
5574 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5575 netdev->features |= NETIF_F_SCTP_CSUM;
5577 netdev->vlan_features |= NETIF_F_TSO;
5578 netdev->vlan_features |= NETIF_F_TSO6;
5579 netdev->vlan_features |= NETIF_F_IP_CSUM;
5580 netdev->vlan_features |= NETIF_F_SG;
5582 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5583 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5585 #ifdef CONFIG_IXGBE_DCB
5586 netdev->dcbnl_ops = &dcbnl_ops;
5590 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5591 if (hw->mac.ops.get_device_caps) {
5592 hw->mac.ops.get_device_caps(hw, &device_caps);
5593 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5594 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5597 #endif /* IXGBE_FCOE */
5599 netdev->features |= NETIF_F_HIGHDMA;
5601 if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED)
5602 netdev->features |= NETIF_F_LRO;
5604 /* make sure the EEPROM is good */
5605 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5606 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5611 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5612 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5614 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5615 dev_err(&pdev->dev, "invalid MAC address\n");
5620 init_timer(&adapter->watchdog_timer);
5621 adapter->watchdog_timer.function = &ixgbe_watchdog;
5622 adapter->watchdog_timer.data = (unsigned long)adapter;
5624 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5625 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5627 err = ixgbe_init_interrupt_scheme(adapter);
5631 switch (pdev->device) {
5632 case IXGBE_DEV_ID_82599_KX4:
5633 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5634 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5635 /* Enable ACPI wakeup in GRC */
5636 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5637 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5643 device_init_wakeup(&adapter->pdev->dev, true);
5644 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5646 /* pick up the PCI bus settings for reporting later */
5647 hw->mac.ops.get_bus_info(hw);
5649 /* print bus type/speed/width info */
5650 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5651 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5652 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5653 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5654 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5655 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5658 ixgbe_read_pba_num_generic(hw, &part_num);
5659 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5660 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5661 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5662 (part_num >> 8), (part_num & 0xff));
5664 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5665 hw->mac.type, hw->phy.type,
5666 (part_num >> 8), (part_num & 0xff));
5668 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5669 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5670 "this card is not sufficient for optimal "
5672 dev_warn(&pdev->dev, "For optimal performance a x8 "
5673 "PCI-Express slot is required.\n");
5676 /* save off EEPROM version number */
5677 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5679 /* reset the hardware with the new settings */
5680 err = hw->mac.ops.start_hw(hw);
5682 if (err == IXGBE_ERR_EEPROM_VERSION) {
5683 /* We are running on a pre-production device, log a warning */
5684 dev_warn(&pdev->dev, "This device is a pre-production "
5685 "adapter/LOM. Please be aware there may be issues "
5686 "associated with your hardware. If you are "
5687 "experiencing problems please contact your Intel or "
5688 "hardware representative who provided you with this "
5691 strcpy(netdev->name, "eth%d");
5692 err = register_netdev(netdev);
5696 /* carrier off reporting is important to ethtool even BEFORE open */
5697 netif_carrier_off(netdev);
5699 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5700 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5701 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5703 #ifdef CONFIG_IXGBE_DCA
5704 if (dca_add_requester(&pdev->dev) == 0) {
5705 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5706 ixgbe_setup_dca(adapter);
5709 /* add san mac addr to netdev */
5710 ixgbe_add_sanmac_netdev(netdev);
5712 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5717 ixgbe_release_hw_control(adapter);
5718 ixgbe_clear_interrupt_scheme(adapter);
5721 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5722 del_timer_sync(&adapter->sfp_timer);
5723 cancel_work_sync(&adapter->sfp_task);
5724 cancel_work_sync(&adapter->multispeed_fiber_task);
5725 cancel_work_sync(&adapter->sfp_config_module_task);
5726 iounmap(hw->hw_addr);
5728 free_netdev(netdev);
5730 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5734 pci_disable_device(pdev);
5739 * ixgbe_remove - Device Removal Routine
5740 * @pdev: PCI device information struct
5742 * ixgbe_remove is called by the PCI subsystem to alert the driver
5743 * that it should release a PCI device. The could be caused by a
5744 * Hot-Plug event, or because the driver is going to be removed from
5747 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5749 struct net_device *netdev = pci_get_drvdata(pdev);
5750 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5753 set_bit(__IXGBE_DOWN, &adapter->state);
5754 /* clear the module not found bit to make sure the worker won't
5757 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5758 del_timer_sync(&adapter->watchdog_timer);
5760 del_timer_sync(&adapter->sfp_timer);
5761 cancel_work_sync(&adapter->watchdog_task);
5762 cancel_work_sync(&adapter->sfp_task);
5763 cancel_work_sync(&adapter->multispeed_fiber_task);
5764 cancel_work_sync(&adapter->sfp_config_module_task);
5765 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5766 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5767 cancel_work_sync(&adapter->fdir_reinit_task);
5768 flush_scheduled_work();
5770 #ifdef CONFIG_IXGBE_DCA
5771 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5772 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5773 dca_remove_requester(&pdev->dev);
5774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5779 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5780 ixgbe_cleanup_fcoe(adapter);
5782 #endif /* IXGBE_FCOE */
5784 /* remove the added san mac */
5785 ixgbe_del_sanmac_netdev(netdev);
5787 if (netdev->reg_state == NETREG_REGISTERED)
5788 unregister_netdev(netdev);
5790 ixgbe_clear_interrupt_scheme(adapter);
5792 ixgbe_release_hw_control(adapter);
5794 iounmap(adapter->hw.hw_addr);
5795 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5798 DPRINTK(PROBE, INFO, "complete\n");
5800 free_netdev(netdev);
5802 err = pci_disable_pcie_error_reporting(pdev);
5805 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5807 pci_disable_device(pdev);
5811 * ixgbe_io_error_detected - called when PCI error is detected
5812 * @pdev: Pointer to PCI device
5813 * @state: The current pci connection state
5815 * This function is called after a PCI bus error affecting
5816 * this device has been detected.
5818 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5819 pci_channel_state_t state)
5821 struct net_device *netdev = pci_get_drvdata(pdev);
5822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5824 netif_device_detach(netdev);
5826 if (state == pci_channel_io_perm_failure)
5827 return PCI_ERS_RESULT_DISCONNECT;
5829 if (netif_running(netdev))
5830 ixgbe_down(adapter);
5831 pci_disable_device(pdev);
5833 /* Request a slot reset. */
5834 return PCI_ERS_RESULT_NEED_RESET;
5838 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5839 * @pdev: Pointer to PCI device
5841 * Restart the card from scratch, as if from a cold-boot.
5843 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5845 struct net_device *netdev = pci_get_drvdata(pdev);
5846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5847 pci_ers_result_t result;
5850 if (pci_enable_device_mem(pdev)) {
5852 "Cannot re-enable PCI device after reset.\n");
5853 result = PCI_ERS_RESULT_DISCONNECT;
5855 pci_set_master(pdev);
5856 pci_restore_state(pdev);
5858 pci_wake_from_d3(pdev, false);
5860 ixgbe_reset(adapter);
5861 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5862 result = PCI_ERS_RESULT_RECOVERED;
5865 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5868 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5869 /* non-fatal, continue */
5876 * ixgbe_io_resume - called when traffic can start flowing again.
5877 * @pdev: Pointer to PCI device
5879 * This callback is called when the error recovery driver tells us that
5880 * its OK to resume normal operation.
5882 static void ixgbe_io_resume(struct pci_dev *pdev)
5884 struct net_device *netdev = pci_get_drvdata(pdev);
5885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5887 if (netif_running(netdev)) {
5888 if (ixgbe_up(adapter)) {
5889 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5894 netif_device_attach(netdev);
5897 static struct pci_error_handlers ixgbe_err_handler = {
5898 .error_detected = ixgbe_io_error_detected,
5899 .slot_reset = ixgbe_io_slot_reset,
5900 .resume = ixgbe_io_resume,
5903 static struct pci_driver ixgbe_driver = {
5904 .name = ixgbe_driver_name,
5905 .id_table = ixgbe_pci_tbl,
5906 .probe = ixgbe_probe,
5907 .remove = __devexit_p(ixgbe_remove),
5909 .suspend = ixgbe_suspend,
5910 .resume = ixgbe_resume,
5912 .shutdown = ixgbe_shutdown,
5913 .err_handler = &ixgbe_err_handler
5917 * ixgbe_init_module - Driver Registration Routine
5919 * ixgbe_init_module is the first routine called when the driver is
5920 * loaded. All it does is register with the PCI subsystem.
5922 static int __init ixgbe_init_module(void)
5925 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5926 ixgbe_driver_string, ixgbe_driver_version);
5928 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5930 #ifdef CONFIG_IXGBE_DCA
5931 dca_register_notify(&dca_notifier);
5934 ret = pci_register_driver(&ixgbe_driver);
5938 module_init(ixgbe_init_module);
5941 * ixgbe_exit_module - Driver Exit Cleanup Routine
5943 * ixgbe_exit_module is called just before the driver is removed
5946 static void __exit ixgbe_exit_module(void)
5948 #ifdef CONFIG_IXGBE_DCA
5949 dca_unregister_notify(&dca_notifier);
5951 pci_unregister_driver(&ixgbe_driver);
5954 #ifdef CONFIG_IXGBE_DCA
5955 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5960 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5961 __ixgbe_notify_dca);
5963 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5966 #endif /* CONFIG_IXGBE_DCA */
5969 * ixgbe_get_hw_dev_name - return device name string
5970 * used by hardware layer to print debugging information
5972 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5974 struct ixgbe_adapter *adapter = hw->back;
5975 return adapter->netdev->name;
5979 module_exit(ixgbe_exit_module);