1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
64 bool autoneg_wait_to_complete);
65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
71 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
81 struct ixgbe_mac_info *mac = &hw->mac;
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
85 &ixgbe_setup_mac_link_multispeed_fiber;
86 mac->ops.setup_link_speed =
87 &ixgbe_setup_mac_link_speed_multispeed_fiber;
90 &ixgbe_setup_mac_link_82599;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_mac_link_speed_82599;
96 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
99 u16 list_offset, data_offset, data_value;
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
104 hw->phy.ops.reset = NULL;
106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 /* PHY config will finish before releasing the semaphore */
113 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
115 ret_val = IXGBE_ERR_SWFW_SYNC;
119 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
120 while (data_value != 0xffff) {
121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
122 IXGBE_WRITE_FLUSH(hw);
123 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 /* Now restart DSP by setting Restart_AN */
126 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
127 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
129 /* Release the semaphore */
130 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
131 /* Delay obtaining semaphore again to allow FW access */
132 msleep(hw->eeprom.semaphore_delay);
140 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
141 * @hw: pointer to hardware structure
143 * Read PCIe configuration space, and get the MSI-X vector count from
144 * the capabilities table.
146 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
148 struct ixgbe_adapter *adapter = hw->back;
150 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
152 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
154 /* MSI-X count is zero-based in HW, so increment to give proper value */
160 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
162 struct ixgbe_mac_info *mac = &hw->mac;
164 ixgbe_init_mac_link_ops_82599(hw);
166 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
167 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
168 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
169 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
170 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
171 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
177 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
178 * @hw: pointer to hardware structure
180 * Initialize any function pointers that were not able to be
181 * set during get_invariants because the PHY/SFP type was
182 * not known. Perform the SFP init if necessary.
185 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
187 struct ixgbe_mac_info *mac = &hw->mac;
188 struct ixgbe_phy_info *phy = &hw->phy;
191 /* Identify the PHY or SFP module */
192 ret_val = phy->ops.identify(hw);
194 /* Setup function pointers based on detected SFP module and speeds */
195 ixgbe_init_mac_link_ops_82599(hw);
197 /* If copper media, overwrite with copper function pointers */
198 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
199 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
200 mac->ops.setup_link_speed =
201 &ixgbe_setup_copper_link_speed_82599;
202 mac->ops.get_link_capabilities =
203 &ixgbe_get_copper_link_capabilities_82599;
206 /* Set necessary function pointers based on phy type */
207 switch (hw->phy.type) {
209 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
210 phy->ops.get_firmware_version =
211 &ixgbe_get_phy_firmware_version_tnx;
221 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
222 * @hw: pointer to hardware structure
223 * @speed: pointer to link speed
224 * @negotiation: true when autoneg or autotry is enabled
226 * Determines the link capabilities by reading the AUTOC register.
228 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
229 ixgbe_link_speed *speed,
236 * Determine link capabilities based on the stored value of AUTOC,
237 * which represents EEPROM defaults. If AUTOC value has not been
238 * stored, use the current register value.
240 if (hw->mac.orig_link_settings_stored)
241 autoc = hw->mac.orig_autoc;
243 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
245 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
246 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = false;
251 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
252 *speed = IXGBE_LINK_SPEED_10GB_FULL;
253 *negotiation = false;
256 case IXGBE_AUTOC_LMS_1G_AN:
257 *speed = IXGBE_LINK_SPEED_1GB_FULL;
261 case IXGBE_AUTOC_LMS_10G_SERIAL:
262 *speed = IXGBE_LINK_SPEED_10GB_FULL;
263 *negotiation = false;
266 case IXGBE_AUTOC_LMS_KX4_KX_KR:
267 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
268 *speed = IXGBE_LINK_SPEED_UNKNOWN;
269 if (autoc & IXGBE_AUTOC_KR_SUPP)
270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
271 if (autoc & IXGBE_AUTOC_KX4_SUPP)
272 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
273 if (autoc & IXGBE_AUTOC_KX_SUPP)
274 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
278 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
279 *speed = IXGBE_LINK_SPEED_100_FULL;
280 if (autoc & IXGBE_AUTOC_KR_SUPP)
281 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
282 if (autoc & IXGBE_AUTOC_KX4_SUPP)
283 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
284 if (autoc & IXGBE_AUTOC_KX_SUPP)
285 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
289 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
290 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
291 *negotiation = false;
295 status = IXGBE_ERR_LINK_SETUP;
300 if (hw->phy.multispeed_fiber) {
301 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
302 IXGBE_LINK_SPEED_1GB_FULL;
311 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
312 * @hw: pointer to hardware structure
313 * @speed: pointer to link speed
314 * @autoneg: boolean auto-negotiation value
316 * Determines the link capabilities by reading the AUTOC register.
318 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
319 ixgbe_link_speed *speed,
322 s32 status = IXGBE_ERR_LINK_SETUP;
328 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
332 if (speed_ability & MDIO_SPEED_10G)
333 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
334 if (speed_ability & MDIO_PMA_SPEED_1000)
335 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
342 * ixgbe_get_media_type_82599 - Get media type
343 * @hw: pointer to hardware structure
345 * Returns the media type (fiber, copper, backplane)
347 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
349 enum ixgbe_media_type media_type;
351 /* Detect if there is a copper PHY attached. */
352 if (hw->phy.type == ixgbe_phy_cu_unknown ||
353 hw->phy.type == ixgbe_phy_tn) {
354 media_type = ixgbe_media_type_copper;
358 switch (hw->device_id) {
359 case IXGBE_DEV_ID_82599_KX4:
360 case IXGBE_DEV_ID_82599_XAUI_LOM:
361 /* Default device ID is mezzanine card KX/KX4 */
362 media_type = ixgbe_media_type_backplane;
364 case IXGBE_DEV_ID_82599_SFP:
365 media_type = ixgbe_media_type_fiber;
368 media_type = ixgbe_media_type_unknown;
376 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
377 * @hw: pointer to hardware structure
379 * Configures link settings based on values in the ixgbe_hw struct.
380 * Restarts the link. Performs autonegotiation if needed.
382 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
390 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
391 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
392 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
394 /* Only poll for autoneg to complete if specified to do so */
395 if (hw->phy.autoneg_wait_to_complete) {
396 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
397 IXGBE_AUTOC_LMS_KX4_KX_KR ||
398 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
399 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
400 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
401 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
402 links_reg = 0; /* Just in case Autoneg time = 0 */
403 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
404 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
405 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
409 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
410 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
411 hw_dbg(hw, "Autoneg did not complete.\n");
416 /* Add delay to filter out noises during initial link setup */
423 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
424 * @hw: pointer to hardware structure
426 * Configures link settings based on values in the ixgbe_hw struct.
427 * Restarts the link for multi-speed fiber at 1G speed, if link
429 * Performs autonegotiation if needed.
431 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
434 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
435 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
441 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
442 * @hw: pointer to hardware structure
443 * @speed: new link speed
444 * @autoneg: true if autonegotiation enabled
445 * @autoneg_wait_to_complete: true when waiting for completion is needed
447 * Set the link speed in the AUTOC register and restarts link.
449 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
450 ixgbe_link_speed speed,
452 bool autoneg_wait_to_complete)
455 ixgbe_link_speed phy_link_speed;
456 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
458 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
459 bool link_up = false;
463 /* Mask off requested but non-supported speeds */
464 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
465 speed &= phy_link_speed;
468 * When the driver changes the link speeds that it can support,
469 * it sets autotry_restart to true to indicate that we need to
470 * initiate a new autotry session with the link partner. To do
471 * so, we set the speed then disable and re-enable the tx laser, to
472 * alert the link partner that it also needs to restart autotry on its
473 * end. This is consistent with true clause 37 autoneg, which also
474 * involves a loss of signal.
478 * Try each speed one by one, highest priority first. We do this in
479 * software because 10gb fiber doesn't support speed autonegotiation.
481 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
483 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
485 /* If we already have link at this speed, just jump out */
486 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
488 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
491 /* Set the module link speed */
492 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
493 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
495 /* Allow module to change analog characteristics (1G->10G) */
498 status = ixgbe_setup_mac_link_speed_82599(hw,
499 IXGBE_LINK_SPEED_10GB_FULL,
501 autoneg_wait_to_complete);
505 /* Flap the tx laser if it has not already been done */
506 if (hw->mac.autotry_restart) {
507 /* Disable tx laser; allow 100us to go dark per spec */
508 esdp_reg |= IXGBE_ESDP_SDP3;
509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
512 /* Enable tx laser; allow 2ms to light up per spec */
513 esdp_reg &= ~IXGBE_ESDP_SDP3;
514 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
517 hw->mac.autotry_restart = false;
520 /* The controller may take up to 500ms at 10g to acquire link */
521 for (i = 0; i < 5; i++) {
522 /* Wait for the link partner to also set speed */
525 /* If we have link, just jump out */
526 hw->mac.ops.check_link(hw, &phy_link_speed,
533 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
535 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
536 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
538 /* If we already have link at this speed, just jump out */
539 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
541 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
544 /* Set the module link speed */
545 esdp_reg &= ~IXGBE_ESDP_SDP5;
546 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
547 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
549 /* Allow module to change analog characteristics (10G->1G) */
552 status = ixgbe_setup_mac_link_speed_82599(hw,
553 IXGBE_LINK_SPEED_1GB_FULL,
555 autoneg_wait_to_complete);
559 /* Flap the tx laser if it has not already been done */
560 if (hw->mac.autotry_restart) {
561 /* Disable tx laser; allow 100us to go dark per spec */
562 esdp_reg |= IXGBE_ESDP_SDP3;
563 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
566 /* Enable tx laser; allow 2ms to light up per spec */
567 esdp_reg &= ~IXGBE_ESDP_SDP3;
568 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
571 hw->mac.autotry_restart = false;
574 /* Wait for the link partner to also set speed */
577 /* If we have link, just jump out */
578 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
584 * We didn't get link. Configure back to the highest speed we tried,
585 * (if there was more than one). We call ourselves back with just the
586 * single highest speed that the user requested.
589 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
592 autoneg_wait_to_complete);
599 * ixgbe_check_mac_link_82599 - Determine link and speed status
600 * @hw: pointer to hardware structure
601 * @speed: pointer to link speed
602 * @link_up: true when link is up
603 * @link_up_wait_to_complete: bool used to wait for link up or not
605 * Reads the links register to determine if link is up and the current speed
607 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
608 bool *link_up, bool link_up_wait_to_complete)
613 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
614 if (link_up_wait_to_complete) {
615 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
616 if (links_reg & IXGBE_LINKS_UP) {
623 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
626 if (links_reg & IXGBE_LINKS_UP)
632 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
633 IXGBE_LINKS_SPEED_10G_82599)
634 *speed = IXGBE_LINK_SPEED_10GB_FULL;
635 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
636 IXGBE_LINKS_SPEED_1G_82599)
637 *speed = IXGBE_LINK_SPEED_1GB_FULL;
639 *speed = IXGBE_LINK_SPEED_100_FULL;
641 /* if link is down, zero out the current_mode */
642 if (*link_up == false) {
643 hw->fc.current_mode = ixgbe_fc_none;
644 hw->fc.fc_was_autonegged = false;
651 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
652 * @hw: pointer to hardware structure
653 * @speed: new link speed
654 * @autoneg: true if autonegotiation enabled
655 * @autoneg_wait_to_complete: true when waiting for completion is needed
657 * Set the link speed in the AUTOC register and restarts link.
659 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
660 ixgbe_link_speed speed, bool autoneg,
661 bool autoneg_wait_to_complete)
664 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
665 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
666 u32 start_autoc = autoc;
668 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
669 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
670 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
673 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
675 /* Check to see if speed passed in is supported. */
676 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
677 speed &= link_capabilities;
679 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
680 status = IXGBE_ERR_LINK_SETUP;
684 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
685 if (hw->mac.orig_link_settings_stored)
686 orig_autoc = hw->mac.orig_autoc;
691 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
692 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
693 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
694 /* Set KX4/KX/KR support according to speed requested */
695 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
696 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
697 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
698 autoc |= IXGBE_AUTOC_KX4_SUPP;
699 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
700 autoc |= IXGBE_AUTOC_KR_SUPP;
701 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
702 autoc |= IXGBE_AUTOC_KX_SUPP;
703 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
704 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
705 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
706 /* Switch from 1G SFI to 10G SFI if requested */
707 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
708 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
709 autoc &= ~IXGBE_AUTOC_LMS_MASK;
710 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
712 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
713 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
714 /* Switch from 10G SFI to 1G SFI if requested */
715 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
716 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
717 autoc &= ~IXGBE_AUTOC_LMS_MASK;
719 autoc |= IXGBE_AUTOC_LMS_1G_AN;
721 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
725 if (autoc != start_autoc) {
727 autoc |= IXGBE_AUTOC_AN_RESTART;
728 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
730 /* Only poll for autoneg to complete if specified to do so */
731 if (autoneg_wait_to_complete) {
732 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
733 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
734 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
735 links_reg = 0; /*Just in case Autoneg time=0*/
736 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
738 IXGBE_READ_REG(hw, IXGBE_LINKS);
739 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
743 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
745 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
746 hw_dbg(hw, "Autoneg did not "
752 /* Add delay to filter out noises during initial link setup */
761 * ixgbe_setup_copper_link_82599 - Setup copper link settings
762 * @hw: pointer to hardware structure
764 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
766 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
770 /* Restart autonegotiation on PHY */
771 status = hw->phy.ops.setup_link(hw);
774 ixgbe_setup_mac_link_82599(hw);
780 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
781 * @hw: pointer to hardware structure
782 * @speed: new link speed
783 * @autoneg: true if autonegotiation enabled
784 * @autoneg_wait_to_complete: true if waiting is needed to complete
786 * Restarts link on PHY and MAC based on settings passed in.
788 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
789 ixgbe_link_speed speed,
791 bool autoneg_wait_to_complete)
795 /* Setup the PHY according to input speed */
796 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
797 autoneg_wait_to_complete);
799 ixgbe_setup_mac_link_82599(hw);
805 * ixgbe_reset_hw_82599 - Perform hardware reset
806 * @hw: pointer to hardware structure
808 * Resets the hardware by resetting the transmit and receive units, masks
809 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
812 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
820 /* Call adapter stop to disable tx/rx and clear interrupts */
821 hw->mac.ops.stop_adapter(hw);
823 /* PHY ops must be identified and initialized prior to reset */
825 /* Init PHY and function pointers, perform SFP setup */
826 status = hw->phy.ops.init(hw);
828 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
831 /* Setup SFP module if there is one present. */
832 if (hw->phy.sfp_setup_needed) {
833 status = hw->mac.ops.setup_sfp(hw);
834 hw->phy.sfp_setup_needed = false;
838 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
839 hw->phy.ops.reset(hw);
842 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
843 * access and verify no pending requests before reset
845 status = ixgbe_disable_pcie_master(hw);
847 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
848 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
852 * Issue global reset to the MAC. This needs to be a SW reset.
853 * If link reset is used, it might reset the MAC when mng is using it
855 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
856 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
857 IXGBE_WRITE_FLUSH(hw);
859 /* Poll for reset bit to self-clear indicating reset is complete */
860 for (i = 0; i < 10; i++) {
862 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
863 if (!(ctrl & IXGBE_CTRL_RST))
866 if (ctrl & IXGBE_CTRL_RST) {
867 status = IXGBE_ERR_RESET_FAILED;
868 hw_dbg(hw, "Reset polling failed to complete.\n");
870 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
871 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
872 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
873 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
880 * Store the original AUTOC/AUTOC2 values if they have not been
881 * stored off yet. Otherwise restore the stored original
882 * values since the reset operation sets back to defaults.
884 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
885 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
886 if (hw->mac.orig_link_settings_stored == false) {
887 hw->mac.orig_autoc = autoc;
888 hw->mac.orig_autoc2 = autoc2;
889 hw->mac.orig_link_settings_stored = true;
891 if (autoc != hw->mac.orig_autoc)
892 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
893 IXGBE_AUTOC_AN_RESTART));
895 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
896 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
897 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
898 autoc2 |= (hw->mac.orig_autoc2 &
899 IXGBE_AUTOC2_UPPER_MASK);
900 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
905 * Store MAC address from RAR0, clear receive address registers, and
906 * clear the multicast table. Also reset num_rar_entries to 128,
907 * since we modify this value when programming the SAN MAC address.
909 hw->mac.num_rar_entries = 128;
910 hw->mac.ops.init_rx_addrs(hw);
912 /* Store the permanent mac address */
913 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
915 /* Store the permanent SAN mac address */
916 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
918 /* Add the SAN MAC address to the RAR only if it's a valid address */
919 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
920 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
921 hw->mac.san_addr, 0, IXGBE_RAH_AV);
923 /* Reserve the last RAR for the SAN MAC address */
924 hw->mac.num_rar_entries--;
932 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
933 * @hw: pointer to hardware struct
934 * @rar: receive address register index to disassociate
935 * @vmdq: VMDq pool index to remove from the rar
937 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
939 u32 mpsar_lo, mpsar_hi;
940 u32 rar_entries = hw->mac.num_rar_entries;
942 if (rar < rar_entries) {
943 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
944 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
946 if (!mpsar_lo && !mpsar_hi)
949 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
951 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
955 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
958 } else if (vmdq < 32) {
959 mpsar_lo &= ~(1 << vmdq);
960 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
962 mpsar_hi &= ~(1 << (vmdq - 32));
963 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
966 /* was that the last pool using this rar? */
967 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
968 hw->mac.ops.clear_rar(hw, rar);
970 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
978 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
979 * @hw: pointer to hardware struct
980 * @rar: receive address register index to associate with a VMDq index
981 * @vmdq: VMDq pool index
983 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
986 u32 rar_entries = hw->mac.num_rar_entries;
988 if (rar < rar_entries) {
990 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
992 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
994 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
995 mpsar |= 1 << (vmdq - 32);
996 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
999 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1005 * ixgbe_set_vfta_82599 - Set VLAN filter table
1006 * @hw: pointer to hardware structure
1007 * @vlan: VLAN id to write to VLAN filter
1008 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1009 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1011 * Turn on/off specified VLAN in the VLAN filter table.
1013 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1019 u32 first_empty_slot;
1022 return IXGBE_ERR_PARAM;
1025 * this is a 2 part operation - first the VFTA, then the
1026 * VLVF and VLVFB if vind is set
1030 * The VFTA is a bitstring made up of 128 32-bit registers
1031 * that enable the particular VLAN id, much like the MTA:
1032 * bits[11-5]: which register
1033 * bits[4-0]: which bit in the register
1035 regindex = (vlan >> 5) & 0x7F;
1036 bitindex = vlan & 0x1F;
1037 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1039 bits |= (1 << bitindex);
1041 bits &= ~(1 << bitindex);
1042 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1046 * If the vind is set
1048 * make sure the vlan is in VLVF
1049 * set the vind bit in the matching VLVFB
1051 * clear the pool bit and possibly the vind
1054 /* find the vlanid or the first empty slot */
1055 first_empty_slot = 0;
1057 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1058 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1059 if (!bits && !first_empty_slot)
1060 first_empty_slot = regindex;
1061 else if ((bits & 0x0FFF) == vlan)
1065 if (regindex >= IXGBE_VLVF_ENTRIES) {
1066 if (first_empty_slot)
1067 regindex = first_empty_slot;
1069 hw_dbg(hw, "No space in VLVF.\n");
1075 /* set the pool bit */
1077 bits = IXGBE_READ_REG(hw,
1078 IXGBE_VLVFB(regindex * 2));
1079 bits |= (1 << vind);
1081 IXGBE_VLVFB(regindex * 2), bits);
1083 bits = IXGBE_READ_REG(hw,
1084 IXGBE_VLVFB((regindex * 2) + 1));
1085 bits |= (1 << vind);
1087 IXGBE_VLVFB((regindex * 2) + 1), bits);
1090 /* clear the pool bit */
1092 bits = IXGBE_READ_REG(hw,
1093 IXGBE_VLVFB(regindex * 2));
1094 bits &= ~(1 << vind);
1096 IXGBE_VLVFB(regindex * 2), bits);
1097 bits |= IXGBE_READ_REG(hw,
1098 IXGBE_VLVFB((regindex * 2) + 1));
1100 bits = IXGBE_READ_REG(hw,
1101 IXGBE_VLVFB((regindex * 2) + 1));
1102 bits &= ~(1 << vind);
1104 IXGBE_VLVFB((regindex * 2) + 1), bits);
1105 bits |= IXGBE_READ_REG(hw,
1106 IXGBE_VLVFB(regindex * 2));
1111 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1112 (IXGBE_VLVF_VIEN | vlan));
1114 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1122 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1123 * @hw: pointer to hardware structure
1125 * Clears the VLAN filer table, and the VMDq index associated with the filter
1127 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1131 for (offset = 0; offset < hw->mac.vft_size; offset++)
1132 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1134 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1135 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1136 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1137 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1144 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1145 * @hw: pointer to hardware structure
1147 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1150 hw_dbg(hw, " Clearing UTA\n");
1152 for (i = 0; i < 128; i++)
1153 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1159 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1160 * @hw: pointer to hardware structure
1161 * @reg: analog register to read
1164 * Performs read operation to Omer analog register specified.
1166 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1170 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1172 IXGBE_WRITE_FLUSH(hw);
1174 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1175 *val = (u8)core_ctl;
1181 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1182 * @hw: pointer to hardware structure
1183 * @reg: atlas register to write
1184 * @val: value to write
1186 * Performs write operation to Omer analog register specified.
1188 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1192 core_ctl = (reg << 8) | val;
1193 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1194 IXGBE_WRITE_FLUSH(hw);
1201 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1202 * @hw: pointer to hardware structure
1204 * Starts the hardware using the generic start_hw function.
1205 * Then performs device-specific:
1206 * Clears the rate limiter registers.
1208 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1212 ixgbe_start_hw_generic(hw);
1214 /* Clear the rate limiters */
1215 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1216 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1217 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1219 IXGBE_WRITE_FLUSH(hw);
1221 /* We need to run link autotry after the driver loads */
1222 hw->mac.autotry_restart = true;
1228 * ixgbe_identify_phy_82599 - Get physical layer module
1229 * @hw: pointer to hardware structure
1231 * Determines the physical layer module found on the current adapter.
1233 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1235 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1236 status = ixgbe_identify_phy_generic(hw);
1238 status = ixgbe_identify_sfp_module_generic(hw);
1243 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1244 * @hw: pointer to hardware structure
1246 * Determines physical layer capabilities of the current configuration.
1248 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1250 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1251 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1252 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1253 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1254 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1255 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1256 u16 ext_ability = 0;
1257 u8 comp_codes_10g = 0;
1259 hw->phy.ops.identify(hw);
1261 if (hw->phy.type == ixgbe_phy_tn ||
1262 hw->phy.type == ixgbe_phy_cu_unknown) {
1263 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1265 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1266 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1267 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1268 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1269 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1270 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1274 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1275 case IXGBE_AUTOC_LMS_1G_AN:
1276 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1277 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1278 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1279 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1282 /* SFI mode so read SFP module */
1285 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1286 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1287 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1288 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1289 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1290 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1291 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1294 case IXGBE_AUTOC_LMS_10G_SERIAL:
1295 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1296 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1298 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1301 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1302 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1303 if (autoc & IXGBE_AUTOC_KX_SUPP)
1304 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1305 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1306 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1307 if (autoc & IXGBE_AUTOC_KR_SUPP)
1308 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1317 /* SFP check must be done last since DA modules are sometimes used to
1318 * test KR mode - we need to id KR mode correctly before SFP module.
1319 * Call identify_sfp because the pluggable module may have changed */
1320 hw->phy.ops.identify_sfp(hw);
1321 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1324 switch (hw->phy.type) {
1325 case ixgbe_phy_tw_tyco:
1326 case ixgbe_phy_tw_unknown:
1327 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1329 case ixgbe_phy_sfp_avago:
1330 case ixgbe_phy_sfp_ftl:
1331 case ixgbe_phy_sfp_intel:
1332 case ixgbe_phy_sfp_unknown:
1333 hw->phy.ops.read_i2c_eeprom(hw,
1334 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1335 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1336 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1337 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1338 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1345 return physical_layer;
1349 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1350 * @hw: pointer to hardware structure
1351 * @regval: register value to write to RXCTRL
1353 * Enables the Rx DMA unit for 82599
1355 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1357 #define IXGBE_MAX_SECRX_POLL 30
1362 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1363 * If traffic is incoming before we enable the Rx unit, it could hang
1364 * the Rx DMA unit. Therefore, make sure the security engine is
1365 * completely disabled prior to enabling the Rx unit.
1367 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1368 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1369 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1370 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1371 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1372 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1378 /* For informational purposes only */
1379 if (i >= IXGBE_MAX_SECRX_POLL)
1380 hw_dbg(hw, "Rx unit being enabled before security "
1381 "path fully disabled. Continuing with init.\n");
1383 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1384 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1385 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1386 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1387 IXGBE_WRITE_FLUSH(hw);
1393 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1394 * @hw: pointer to hardware structure
1395 * @device_caps: the EEPROM word with the extra device capabilities
1397 * This function will read the EEPROM location for the device capabilities,
1398 * and return the word through device_caps.
1400 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1402 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1408 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
1409 * @hw: pointer to hardware structure
1410 * @san_mac_offset: SAN MAC address offset
1412 * This function will read the EEPROM location for the SAN MAC address
1413 * pointer, and returns the value at that location. This is used in both
1414 * get and set mac_addr routines.
1416 s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
1417 u16 *san_mac_offset)
1420 * First read the EEPROM pointer to see if the MAC addresses are
1423 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
1429 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
1430 * @hw: pointer to hardware structure
1431 * @san_mac_addr: SAN MAC address
1433 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1434 * per-port, so set_lan_id() must be called before reading the addresses.
1435 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1436 * upon for non-SFP connections, so we must call it here.
1438 s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
1440 u16 san_mac_data, san_mac_offset;
1444 * First read the EEPROM pointer to see if the MAC addresses are
1445 * available. If they're not, no point in calling set_lan_id() here.
1447 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
1449 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
1451 * No addresses available in this EEPROM. It's not an
1452 * error though, so just wipe the local address and return.
1454 for (i = 0; i < 6; i++)
1455 san_mac_addr[i] = 0xFF;
1457 goto san_mac_addr_out;
1460 /* make sure we know which port we need to program */
1461 hw->mac.ops.set_lan_id(hw);
1462 /* apply the port offset to the address offset */
1463 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1464 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1465 for (i = 0; i < 3; i++) {
1466 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
1467 san_mac_addr[i * 2] = (u8)(san_mac_data);
1468 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1476 static struct ixgbe_mac_operations mac_ops_82599 = {
1477 .init_hw = &ixgbe_init_hw_generic,
1478 .reset_hw = &ixgbe_reset_hw_82599,
1479 .start_hw = &ixgbe_start_hw_82599,
1480 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1481 .get_media_type = &ixgbe_get_media_type_82599,
1482 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1483 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1484 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1485 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
1486 .get_device_caps = &ixgbe_get_device_caps_82599,
1487 .stop_adapter = &ixgbe_stop_adapter_generic,
1488 .get_bus_info = &ixgbe_get_bus_info_generic,
1489 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1490 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1491 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1492 .setup_link = &ixgbe_setup_mac_link_82599,
1493 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1494 .check_link = &ixgbe_check_mac_link_82599,
1495 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1496 .led_on = &ixgbe_led_on_generic,
1497 .led_off = &ixgbe_led_off_generic,
1498 .blink_led_start = &ixgbe_blink_led_start_generic,
1499 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1500 .set_rar = &ixgbe_set_rar_generic,
1501 .clear_rar = &ixgbe_clear_rar_generic,
1502 .set_vmdq = &ixgbe_set_vmdq_82599,
1503 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1504 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1505 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1506 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1507 .enable_mc = &ixgbe_enable_mc_generic,
1508 .disable_mc = &ixgbe_disable_mc_generic,
1509 .clear_vfta = &ixgbe_clear_vfta_82599,
1510 .set_vfta = &ixgbe_set_vfta_82599,
1511 .fc_enable = &ixgbe_fc_enable_generic,
1512 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1513 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1516 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1517 .init_params = &ixgbe_init_eeprom_params_generic,
1518 .read = &ixgbe_read_eeprom_generic,
1519 .write = &ixgbe_write_eeprom_generic,
1520 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1521 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1524 static struct ixgbe_phy_operations phy_ops_82599 = {
1525 .identify = &ixgbe_identify_phy_82599,
1526 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1527 .init = &ixgbe_init_phy_ops_82599,
1528 .reset = &ixgbe_reset_phy_generic,
1529 .read_reg = &ixgbe_read_phy_reg_generic,
1530 .write_reg = &ixgbe_write_phy_reg_generic,
1531 .setup_link = &ixgbe_setup_phy_link_generic,
1532 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1533 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1534 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1535 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1536 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1539 struct ixgbe_info ixgbe_82599_info = {
1540 .mac = ixgbe_mac_82599EB,
1541 .get_invariants = &ixgbe_get_invariants_82599,
1542 .mac_ops = &mac_ops_82599,
1543 .eeprom_ops = &eeprom_ops_82599,
1544 .phy_ops = &phy_ops_82599,