1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
64 bool autoneg_wait_to_complete);
65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
71 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
81 struct ixgbe_mac_info *mac = &hw->mac;
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
85 &ixgbe_setup_mac_link_multispeed_fiber;
86 mac->ops.setup_link_speed =
87 &ixgbe_setup_mac_link_speed_multispeed_fiber;
90 &ixgbe_setup_mac_link_82599;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_mac_link_speed_82599;
96 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
99 u16 list_offset, data_offset, data_value;
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
104 hw->phy.ops.reset = NULL;
106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
113 while (data_value != 0xffff) {
114 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
115 IXGBE_WRITE_FLUSH(hw);
116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
118 /* Now restart DSP */
119 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
120 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
121 IXGBE_WRITE_FLUSH(hw);
129 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
130 * @hw: pointer to hardware structure
132 * Read PCIe configuration space, and get the MSI-X vector count from
133 * the capabilities table.
135 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
137 struct ixgbe_adapter *adapter = hw->back;
139 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
141 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
143 /* MSI-X count is zero-based in HW, so increment to give proper value */
149 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
151 struct ixgbe_mac_info *mac = &hw->mac;
153 ixgbe_init_mac_link_ops_82599(hw);
155 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
156 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
157 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
158 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
159 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
160 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
166 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
167 * @hw: pointer to hardware structure
169 * Initialize any function pointers that were not able to be
170 * set during get_invariants because the PHY/SFP type was
171 * not known. Perform the SFP init if necessary.
174 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
176 struct ixgbe_mac_info *mac = &hw->mac;
177 struct ixgbe_phy_info *phy = &hw->phy;
180 /* Identify the PHY or SFP module */
181 ret_val = phy->ops.identify(hw);
183 /* Setup function pointers based on detected SFP module and speeds */
184 ixgbe_init_mac_link_ops_82599(hw);
186 /* If copper media, overwrite with copper function pointers */
187 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
188 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
189 mac->ops.setup_link_speed =
190 &ixgbe_setup_copper_link_speed_82599;
191 mac->ops.get_link_capabilities =
192 &ixgbe_get_copper_link_capabilities_82599;
195 /* Set necessary function pointers based on phy type */
196 switch (hw->phy.type) {
198 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
199 phy->ops.get_firmware_version =
200 &ixgbe_get_phy_firmware_version_tnx;
210 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
211 * @hw: pointer to hardware structure
212 * @speed: pointer to link speed
213 * @negotiation: true when autoneg or autotry is enabled
215 * Determines the link capabilities by reading the AUTOC register.
217 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
218 ixgbe_link_speed *speed,
225 * Determine link capabilities based on the stored value of AUTOC,
226 * which represents EEPROM defaults. If AUTOC value has not been
227 * stored, use the current register value.
229 if (hw->mac.orig_link_settings_stored)
230 autoc = hw->mac.orig_autoc;
232 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
234 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
235 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
236 *speed = IXGBE_LINK_SPEED_1GB_FULL;
237 *negotiation = false;
240 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
241 *speed = IXGBE_LINK_SPEED_10GB_FULL;
242 *negotiation = false;
245 case IXGBE_AUTOC_LMS_1G_AN:
246 *speed = IXGBE_LINK_SPEED_1GB_FULL;
250 case IXGBE_AUTOC_LMS_10G_SERIAL:
251 *speed = IXGBE_LINK_SPEED_10GB_FULL;
252 *negotiation = false;
255 case IXGBE_AUTOC_LMS_KX4_KX_KR:
256 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
257 *speed = IXGBE_LINK_SPEED_UNKNOWN;
258 if (autoc & IXGBE_AUTOC_KR_SUPP)
259 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
260 if (autoc & IXGBE_AUTOC_KX4_SUPP)
261 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
262 if (autoc & IXGBE_AUTOC_KX_SUPP)
263 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
267 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
268 *speed = IXGBE_LINK_SPEED_100_FULL;
269 if (autoc & IXGBE_AUTOC_KR_SUPP)
270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
271 if (autoc & IXGBE_AUTOC_KX4_SUPP)
272 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
273 if (autoc & IXGBE_AUTOC_KX_SUPP)
274 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
278 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
279 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
280 *negotiation = false;
284 status = IXGBE_ERR_LINK_SETUP;
289 if (hw->phy.multispeed_fiber) {
290 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
291 IXGBE_LINK_SPEED_1GB_FULL;
300 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
301 * @hw: pointer to hardware structure
302 * @speed: pointer to link speed
303 * @autoneg: boolean auto-negotiation value
305 * Determines the link capabilities by reading the AUTOC register.
307 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
308 ixgbe_link_speed *speed,
311 s32 status = IXGBE_ERR_LINK_SETUP;
317 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
321 if (speed_ability & MDIO_SPEED_10G)
322 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
323 if (speed_ability & MDIO_PMA_SPEED_1000)
324 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
331 * ixgbe_get_media_type_82599 - Get media type
332 * @hw: pointer to hardware structure
334 * Returns the media type (fiber, copper, backplane)
336 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
338 enum ixgbe_media_type media_type;
340 /* Detect if there is a copper PHY attached. */
341 if (hw->phy.type == ixgbe_phy_cu_unknown ||
342 hw->phy.type == ixgbe_phy_tn) {
343 media_type = ixgbe_media_type_copper;
347 switch (hw->device_id) {
348 case IXGBE_DEV_ID_82599:
349 case IXGBE_DEV_ID_82599_KX4:
350 case IXGBE_DEV_ID_82599_XAUI_LOM:
351 /* Default device ID is mezzanine card KX/KX4 */
352 media_type = ixgbe_media_type_backplane;
354 case IXGBE_DEV_ID_82599_SFP:
355 media_type = ixgbe_media_type_fiber;
358 media_type = ixgbe_media_type_unknown;
366 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
367 * @hw: pointer to hardware structure
369 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed.
372 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
380 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
381 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
382 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
384 /* Only poll for autoneg to complete if specified to do so */
385 if (hw->phy.autoneg_wait_to_complete) {
386 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
387 IXGBE_AUTOC_LMS_KX4_KX_KR ||
388 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
389 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
390 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
391 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
392 links_reg = 0; /* Just in case Autoneg time = 0 */
393 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
394 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
395 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
399 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
400 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
401 hw_dbg(hw, "Autoneg did not complete.\n");
406 /* Set up flow control */
407 status = ixgbe_setup_fc_generic(hw, 0);
409 /* Add delay to filter out noises during initial link setup */
416 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
417 * @hw: pointer to hardware structure
419 * Configures link settings based on values in the ixgbe_hw struct.
420 * Restarts the link for multi-speed fiber at 1G speed, if link
422 * Performs autonegotiation if needed.
424 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
427 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
428 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
434 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
435 * @hw: pointer to hardware structure
436 * @speed: new link speed
437 * @autoneg: true if autonegotiation enabled
438 * @autoneg_wait_to_complete: true when waiting for completion is needed
440 * Set the link speed in the AUTOC register and restarts link.
442 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
443 ixgbe_link_speed speed,
445 bool autoneg_wait_to_complete)
448 ixgbe_link_speed phy_link_speed;
449 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
451 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
452 bool link_up = false;
455 /* Mask off requested but non-supported speeds */
456 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
457 speed &= phy_link_speed;
460 * Try each speed one by one, highest priority first. We do this in
461 * software because 10gb fiber doesn't support speed autonegotiation.
463 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
465 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
467 /* Set hardware SDP's */
468 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
469 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
471 ixgbe_setup_mac_link_speed_82599(hw,
472 IXGBE_LINK_SPEED_10GB_FULL,
474 autoneg_wait_to_complete);
478 /* If we have link, just jump out */
479 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
484 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
486 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
487 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
489 /* Set hardware SDP's */
490 esdp_reg &= ~IXGBE_ESDP_SDP5;
491 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
492 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
494 ixgbe_setup_mac_link_speed_82599(
495 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
496 autoneg_wait_to_complete);
500 /* If we have link, just jump out */
501 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
507 * We didn't get link. Configure back to the highest speed we tried,
508 * (if there was more than one). We call ourselves back with just the
509 * single highest speed that the user requested.
512 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
515 autoneg_wait_to_complete);
522 * ixgbe_check_mac_link_82599 - Determine link and speed status
523 * @hw: pointer to hardware structure
524 * @speed: pointer to link speed
525 * @link_up: true when link is up
526 * @link_up_wait_to_complete: bool used to wait for link up or not
528 * Reads the links register to determine if link is up and the current speed
530 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
531 bool *link_up, bool link_up_wait_to_complete)
536 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
537 if (link_up_wait_to_complete) {
538 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
539 if (links_reg & IXGBE_LINKS_UP) {
546 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
549 if (links_reg & IXGBE_LINKS_UP)
555 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
556 IXGBE_LINKS_SPEED_10G_82599)
557 *speed = IXGBE_LINK_SPEED_10GB_FULL;
558 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
559 IXGBE_LINKS_SPEED_1G_82599)
560 *speed = IXGBE_LINK_SPEED_1GB_FULL;
562 *speed = IXGBE_LINK_SPEED_100_FULL;
569 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
570 * @hw: pointer to hardware structure
571 * @speed: new link speed
572 * @autoneg: true if autonegotiation enabled
573 * @autoneg_wait_to_complete: true when waiting for completion is needed
575 * Set the link speed in the AUTOC register and restarts link.
577 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
578 ixgbe_link_speed speed, bool autoneg,
579 bool autoneg_wait_to_complete)
582 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
583 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
585 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
586 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
587 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
590 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
592 /* Check to see if speed passed in is supported. */
593 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
594 speed &= link_capabilities;
596 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
597 if (hw->mac.orig_link_settings_stored)
598 orig_autoc = hw->mac.orig_autoc;
603 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
604 status = IXGBE_ERR_LINK_SETUP;
605 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
606 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
607 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
608 /* Set KX4/KX/KR support according to speed requested */
609 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
610 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
611 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
612 autoc |= IXGBE_AUTOC_KX4_SUPP;
613 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
614 autoc |= IXGBE_AUTOC_KR_SUPP;
615 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
616 autoc |= IXGBE_AUTOC_KX_SUPP;
617 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
618 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
619 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
620 /* Switch from 1G SFI to 10G SFI if requested */
621 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
622 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
623 autoc &= ~IXGBE_AUTOC_LMS_MASK;
624 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
626 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
627 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
628 /* Switch from 10G SFI to 1G SFI if requested */
629 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
630 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
631 autoc &= ~IXGBE_AUTOC_LMS_MASK;
633 autoc |= IXGBE_AUTOC_LMS_1G_AN;
635 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
641 autoc |= IXGBE_AUTOC_AN_RESTART;
642 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
644 /* Only poll for autoneg to complete if specified to do so */
645 if (autoneg_wait_to_complete) {
646 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
647 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
648 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
649 links_reg = 0; /*Just in case Autoneg time=0*/
650 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
652 IXGBE_READ_REG(hw, IXGBE_LINKS);
653 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
657 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
659 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
660 hw_dbg(hw, "Autoneg did not "
666 /* Set up flow control */
667 status = ixgbe_setup_fc_generic(hw, 0);
669 /* Add delay to filter out noises during initial link setup */
677 * ixgbe_setup_copper_link_82599 - Setup copper link settings
678 * @hw: pointer to hardware structure
680 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
682 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
686 /* Restart autonegotiation on PHY */
687 status = hw->phy.ops.setup_link(hw);
690 ixgbe_setup_mac_link_82599(hw);
696 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
697 * @hw: pointer to hardware structure
698 * @speed: new link speed
699 * @autoneg: true if autonegotiation enabled
700 * @autoneg_wait_to_complete: true if waiting is needed to complete
702 * Restarts link on PHY and MAC based on settings passed in.
704 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
705 ixgbe_link_speed speed,
707 bool autoneg_wait_to_complete)
711 /* Setup the PHY according to input speed */
712 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
713 autoneg_wait_to_complete);
715 ixgbe_setup_mac_link_82599(hw);
721 * ixgbe_reset_hw_82599 - Perform hardware reset
722 * @hw: pointer to hardware structure
724 * Resets the hardware by resetting the transmit and receive units, masks
725 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
728 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
736 /* Call adapter stop to disable tx/rx and clear interrupts */
737 hw->mac.ops.stop_adapter(hw);
739 /* PHY ops must be identified and initialized prior to reset */
741 /* Init PHY and function pointers, perform SFP setup */
742 status = hw->phy.ops.init(hw);
744 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
747 /* Setup SFP module if there is one present. */
748 if (hw->phy.sfp_setup_needed) {
749 status = hw->mac.ops.setup_sfp(hw);
750 hw->phy.sfp_setup_needed = false;
754 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
755 hw->phy.ops.reset(hw);
758 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
759 * access and verify no pending requests before reset
761 status = ixgbe_disable_pcie_master(hw);
763 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
764 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
768 * Issue global reset to the MAC. This needs to be a SW reset.
769 * If link reset is used, it might reset the MAC when mng is using it
771 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
772 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
773 IXGBE_WRITE_FLUSH(hw);
775 /* Poll for reset bit to self-clear indicating reset is complete */
776 for (i = 0; i < 10; i++) {
778 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
779 if (!(ctrl & IXGBE_CTRL_RST))
782 if (ctrl & IXGBE_CTRL_RST) {
783 status = IXGBE_ERR_RESET_FAILED;
784 hw_dbg(hw, "Reset polling failed to complete.\n");
786 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
787 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
788 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
789 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
796 * Store the original AUTOC/AUTOC2 values if they have not been
797 * stored off yet. Otherwise restore the stored original
798 * values since the reset operation sets back to defaults.
800 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
801 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
802 if (hw->mac.orig_link_settings_stored == false) {
803 hw->mac.orig_autoc = autoc;
804 hw->mac.orig_autoc2 = autoc2;
805 hw->mac.orig_link_settings_stored = true;
807 if (autoc != hw->mac.orig_autoc)
808 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
809 IXGBE_AUTOC_AN_RESTART));
811 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
812 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
813 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
814 autoc2 |= (hw->mac.orig_autoc2 &
815 IXGBE_AUTOC2_UPPER_MASK);
816 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
821 * Store MAC address from RAR0, clear receive address registers, and
822 * clear the multicast table. Also reset num_rar_entries to 128,
823 * since we modify this value when programming the SAN MAC address.
825 hw->mac.num_rar_entries = 128;
826 hw->mac.ops.init_rx_addrs(hw);
828 /* Store the permanent mac address */
829 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
831 /* Store the permanent SAN mac address */
832 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
834 /* Add the SAN MAC address to the RAR only if it's a valid address */
835 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
836 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
837 hw->mac.san_addr, 0, IXGBE_RAH_AV);
839 /* Reserve the last RAR for the SAN MAC address */
840 hw->mac.num_rar_entries--;
848 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
849 * @hw: pointer to hardware struct
850 * @rar: receive address register index to disassociate
851 * @vmdq: VMDq pool index to remove from the rar
853 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
855 u32 mpsar_lo, mpsar_hi;
856 u32 rar_entries = hw->mac.num_rar_entries;
858 if (rar < rar_entries) {
859 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
860 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
862 if (!mpsar_lo && !mpsar_hi)
865 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
867 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
871 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
874 } else if (vmdq < 32) {
875 mpsar_lo &= ~(1 << vmdq);
876 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
878 mpsar_hi &= ~(1 << (vmdq - 32));
879 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
882 /* was that the last pool using this rar? */
883 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
884 hw->mac.ops.clear_rar(hw, rar);
886 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
894 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
895 * @hw: pointer to hardware struct
896 * @rar: receive address register index to associate with a VMDq index
897 * @vmdq: VMDq pool index
899 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
902 u32 rar_entries = hw->mac.num_rar_entries;
904 if (rar < rar_entries) {
906 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
908 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
910 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
911 mpsar |= 1 << (vmdq - 32);
912 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
915 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
921 * ixgbe_set_vfta_82599 - Set VLAN filter table
922 * @hw: pointer to hardware structure
923 * @vlan: VLAN id to write to VLAN filter
924 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
925 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
927 * Turn on/off specified VLAN in the VLAN filter table.
929 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
935 u32 first_empty_slot;
938 return IXGBE_ERR_PARAM;
941 * this is a 2 part operation - first the VFTA, then the
942 * VLVF and VLVFB if vind is set
946 * The VFTA is a bitstring made up of 128 32-bit registers
947 * that enable the particular VLAN id, much like the MTA:
948 * bits[11-5]: which register
949 * bits[4-0]: which bit in the register
951 regindex = (vlan >> 5) & 0x7F;
952 bitindex = vlan & 0x1F;
953 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
955 bits |= (1 << bitindex);
957 bits &= ~(1 << bitindex);
958 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
964 * make sure the vlan is in VLVF
965 * set the vind bit in the matching VLVFB
967 * clear the pool bit and possibly the vind
970 /* find the vlanid or the first empty slot */
971 first_empty_slot = 0;
973 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
974 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
975 if (!bits && !first_empty_slot)
976 first_empty_slot = regindex;
977 else if ((bits & 0x0FFF) == vlan)
981 if (regindex >= IXGBE_VLVF_ENTRIES) {
982 if (first_empty_slot)
983 regindex = first_empty_slot;
985 hw_dbg(hw, "No space in VLVF.\n");
991 /* set the pool bit */
993 bits = IXGBE_READ_REG(hw,
994 IXGBE_VLVFB(regindex * 2));
997 IXGBE_VLVFB(regindex * 2), bits);
999 bits = IXGBE_READ_REG(hw,
1000 IXGBE_VLVFB((regindex * 2) + 1));
1001 bits |= (1 << vind);
1003 IXGBE_VLVFB((regindex * 2) + 1), bits);
1006 /* clear the pool bit */
1008 bits = IXGBE_READ_REG(hw,
1009 IXGBE_VLVFB(regindex * 2));
1010 bits &= ~(1 << vind);
1012 IXGBE_VLVFB(regindex * 2), bits);
1013 bits |= IXGBE_READ_REG(hw,
1014 IXGBE_VLVFB((regindex * 2) + 1));
1016 bits = IXGBE_READ_REG(hw,
1017 IXGBE_VLVFB((regindex * 2) + 1));
1018 bits &= ~(1 << vind);
1020 IXGBE_VLVFB((regindex * 2) + 1), bits);
1021 bits |= IXGBE_READ_REG(hw,
1022 IXGBE_VLVFB(regindex * 2));
1027 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1028 (IXGBE_VLVF_VIEN | vlan));
1030 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1038 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1039 * @hw: pointer to hardware structure
1041 * Clears the VLAN filer table, and the VMDq index associated with the filter
1043 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1047 for (offset = 0; offset < hw->mac.vft_size; offset++)
1048 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1050 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1051 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1052 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1053 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1060 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1061 * @hw: pointer to hardware structure
1063 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1066 hw_dbg(hw, " Clearing UTA\n");
1068 for (i = 0; i < 128; i++)
1069 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1075 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1076 * @hw: pointer to hardware structure
1077 * @reg: analog register to read
1080 * Performs read operation to Omer analog register specified.
1082 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1086 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1088 IXGBE_WRITE_FLUSH(hw);
1090 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1091 *val = (u8)core_ctl;
1097 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1098 * @hw: pointer to hardware structure
1099 * @reg: atlas register to write
1100 * @val: value to write
1102 * Performs write operation to Omer analog register specified.
1104 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1108 core_ctl = (reg << 8) | val;
1109 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1110 IXGBE_WRITE_FLUSH(hw);
1117 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1118 * @hw: pointer to hardware structure
1120 * Starts the hardware using the generic start_hw function.
1121 * Then performs device-specific:
1122 * Clears the rate limiter registers.
1124 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1128 ixgbe_start_hw_generic(hw);
1130 /* Clear the rate limiters */
1131 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1132 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1133 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1135 IXGBE_WRITE_FLUSH(hw);
1141 * ixgbe_identify_phy_82599 - Get physical layer module
1142 * @hw: pointer to hardware structure
1144 * Determines the physical layer module found on the current adapter.
1146 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1148 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1149 status = ixgbe_identify_phy_generic(hw);
1151 status = ixgbe_identify_sfp_module_generic(hw);
1156 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1157 * @hw: pointer to hardware structure
1159 * Determines physical layer capabilities of the current configuration.
1161 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1163 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1164 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1165 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1166 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1167 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1168 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1169 u16 ext_ability = 0;
1170 u8 comp_codes_10g = 0;
1172 hw->phy.ops.identify(hw);
1174 if (hw->phy.type == ixgbe_phy_tn ||
1175 hw->phy.type == ixgbe_phy_cu_unknown) {
1176 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1178 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1179 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1180 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1181 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1182 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1183 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1187 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1188 case IXGBE_AUTOC_LMS_1G_AN:
1189 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1190 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1191 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1192 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1195 /* SFI mode so read SFP module */
1198 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1199 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1200 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1201 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1202 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1203 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1204 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1207 case IXGBE_AUTOC_LMS_10G_SERIAL:
1208 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1209 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1211 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1214 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1215 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1216 if (autoc & IXGBE_AUTOC_KX_SUPP)
1217 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1218 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1219 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1220 if (autoc & IXGBE_AUTOC_KR_SUPP)
1221 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1230 /* SFP check must be done last since DA modules are sometimes used to
1231 * test KR mode - we need to id KR mode correctly before SFP module.
1232 * Call identify_sfp because the pluggable module may have changed */
1233 hw->phy.ops.identify_sfp(hw);
1234 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1237 switch (hw->phy.type) {
1238 case ixgbe_phy_tw_tyco:
1239 case ixgbe_phy_tw_unknown:
1240 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1242 case ixgbe_phy_sfp_avago:
1243 case ixgbe_phy_sfp_ftl:
1244 case ixgbe_phy_sfp_intel:
1245 case ixgbe_phy_sfp_unknown:
1246 hw->phy.ops.read_i2c_eeprom(hw,
1247 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1248 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1249 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1250 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1251 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1258 return physical_layer;
1262 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1263 * @hw: pointer to hardware structure
1264 * @regval: register value to write to RXCTRL
1266 * Enables the Rx DMA unit for 82599
1268 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1270 #define IXGBE_MAX_SECRX_POLL 30
1275 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1276 * If traffic is incoming before we enable the Rx unit, it could hang
1277 * the Rx DMA unit. Therefore, make sure the security engine is
1278 * completely disabled prior to enabling the Rx unit.
1280 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1281 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1282 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1283 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1284 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1285 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1291 /* For informational purposes only */
1292 if (i >= IXGBE_MAX_SECRX_POLL)
1293 hw_dbg(hw, "Rx unit being enabled before security "
1294 "path fully disabled. Continuing with init.\n");
1296 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1297 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1298 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1299 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1300 IXGBE_WRITE_FLUSH(hw);
1306 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1307 * @hw: pointer to hardware structure
1308 * @device_caps: the EEPROM word with the extra device capabilities
1310 * This function will read the EEPROM location for the device capabilities,
1311 * and return the word through device_caps.
1313 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1315 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1321 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
1322 * @hw: pointer to hardware structure
1323 * @san_mac_offset: SAN MAC address offset
1325 * This function will read the EEPROM location for the SAN MAC address
1326 * pointer, and returns the value at that location. This is used in both
1327 * get and set mac_addr routines.
1329 s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
1330 u16 *san_mac_offset)
1333 * First read the EEPROM pointer to see if the MAC addresses are
1336 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
1342 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
1343 * @hw: pointer to hardware structure
1344 * @san_mac_addr: SAN MAC address
1346 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1347 * per-port, so set_lan_id() must be called before reading the addresses.
1348 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1349 * upon for non-SFP connections, so we must call it here.
1351 s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
1353 u16 san_mac_data, san_mac_offset;
1357 * First read the EEPROM pointer to see if the MAC addresses are
1358 * available. If they're not, no point in calling set_lan_id() here.
1360 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
1362 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
1364 * No addresses available in this EEPROM. It's not an
1365 * error though, so just wipe the local address and return.
1367 for (i = 0; i < 6; i++)
1368 san_mac_addr[i] = 0xFF;
1370 goto san_mac_addr_out;
1373 /* make sure we know which port we need to program */
1374 hw->mac.ops.set_lan_id(hw);
1375 /* apply the port offset to the address offset */
1376 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1377 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1378 for (i = 0; i < 3; i++) {
1379 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
1380 san_mac_addr[i * 2] = (u8)(san_mac_data);
1381 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1389 static struct ixgbe_mac_operations mac_ops_82599 = {
1390 .init_hw = &ixgbe_init_hw_generic,
1391 .reset_hw = &ixgbe_reset_hw_82599,
1392 .start_hw = &ixgbe_start_hw_82599,
1393 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1394 .get_media_type = &ixgbe_get_media_type_82599,
1395 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1396 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1397 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1398 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
1399 .get_device_caps = &ixgbe_get_device_caps_82599,
1400 .stop_adapter = &ixgbe_stop_adapter_generic,
1401 .get_bus_info = &ixgbe_get_bus_info_generic,
1402 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1403 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1404 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1405 .setup_link = &ixgbe_setup_mac_link_82599,
1406 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1407 .check_link = &ixgbe_check_mac_link_82599,
1408 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1409 .led_on = &ixgbe_led_on_generic,
1410 .led_off = &ixgbe_led_off_generic,
1411 .blink_led_start = &ixgbe_blink_led_start_generic,
1412 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1413 .set_rar = &ixgbe_set_rar_generic,
1414 .clear_rar = &ixgbe_clear_rar_generic,
1415 .set_vmdq = &ixgbe_set_vmdq_82599,
1416 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1417 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1418 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1419 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1420 .enable_mc = &ixgbe_enable_mc_generic,
1421 .disable_mc = &ixgbe_disable_mc_generic,
1422 .clear_vfta = &ixgbe_clear_vfta_82599,
1423 .set_vfta = &ixgbe_set_vfta_82599,
1424 .setup_fc = &ixgbe_setup_fc_generic,
1425 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1426 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1429 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1430 .init_params = &ixgbe_init_eeprom_params_generic,
1431 .read = &ixgbe_read_eeprom_generic,
1432 .write = &ixgbe_write_eeprom_generic,
1433 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1434 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1437 static struct ixgbe_phy_operations phy_ops_82599 = {
1438 .identify = &ixgbe_identify_phy_82599,
1439 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1440 .init = &ixgbe_init_phy_ops_82599,
1441 .reset = &ixgbe_reset_phy_generic,
1442 .read_reg = &ixgbe_read_phy_reg_generic,
1443 .write_reg = &ixgbe_write_phy_reg_generic,
1444 .setup_link = &ixgbe_setup_phy_link_generic,
1445 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1446 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1447 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1448 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1449 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1452 struct ixgbe_info ixgbe_82599_info = {
1453 .mac = ixgbe_mac_82599EB,
1454 .get_invariants = &ixgbe_get_invariants_82599,
1455 .mac_ops = &mac_ops_82599,
1456 .eeprom_ops = &eeprom_ops_82599,
1457 .phy_ops = &phy_ops_82599,