SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78         struct ixgbe_phy_info *phy = &hw->phy;
  79         s32 ret_val = 0;
  80         u16 list_offset, data_offset;
  81
  82         /* Set the bus information prior to PHY identification */
  83         mac->ops.get_bus_info(hw);
  84
  85         /* Call PHY identify routine to get the phy type */
  86         ixgbe_identify_phy_generic(hw);
  87
  88         /* PHY Init */
  89         switch (phy->type) {
  90         case ixgbe_phy_tn:
  91                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
  92                 phy->ops.get_firmware_version =
  93                              &ixgbe_get_phy_firmware_version_tnx;
  94                 break;
  95         case ixgbe_phy_nl:
  96                 phy->ops.reset = &ixgbe_reset_phy_nl;
  97
  98                 /* Call SFP+ identify routine to get the SFP+ module type */
  99                 ret_val = phy->ops.identify_sfp(hw);
 100                 if (ret_val != 0)
 101                         goto out;
 102                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 103                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 104                         goto out;
 105                 }
 106
 107                 /* Check to see if SFP+ module is supported */
 108                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 109                                                               &list_offset,
 110                                                               &data_offset);
 111                 if (ret_val != 0) {
 112                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 113                         goto out;
 114                 }
 115                 break;
 116         default:
 117                 break;
 118         }
 119
 120         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 121                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 122                 mac->ops.setup_link_speed =
 123                                      &ixgbe_setup_copper_link_speed_82598;
 124                 mac->ops.get_link_capabilities =
 125                                      &ixgbe_get_copper_link_capabilities_82598;
 126         }
 127
 128         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
 129         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
 130         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
 131         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
 132         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
 133         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
 134
 135 out:
 136         return ret_val;
 137 }
 138
 139 /**
 140  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 141  *  @hw: pointer to hardware structure
 142  *  @speed: pointer to link speed
 143  *  @autoneg: boolean auto-negotiation value
 144  *
 145  *  Determines the link capabilities by reading the AUTOC register.
 146  **/
 147 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 148                                              ixgbe_link_speed *speed,
 149                                              bool *autoneg)
 150 {
 151         s32 status = 0;
 152
 153         /*
 154          * Determine link capabilities based on the stored value of AUTOC,
 155          * which represents EEPROM defaults.
 156          */
 157         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
 158         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 159                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 160                 *autoneg = false;
 161                 break;
 162
 163         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 164                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 165                 *autoneg = false;
 166                 break;
 167
 168         case IXGBE_AUTOC_LMS_1G_AN:
 169                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 170                 *autoneg = true;
 171                 break;
 172
 173         case IXGBE_AUTOC_LMS_KX4_AN:
 174         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 175                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 176                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 177                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 178                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 179                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 180                 *autoneg = true;
 181                 break;
 182
 183         default:
 184                 status = IXGBE_ERR_LINK_SETUP;
 185                 break;
 186         }
 187
 188         return status;
 189 }
 190
 191 /**
 192  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 193  *  @hw: pointer to hardware structure
 194  *  @speed: pointer to link speed
 195  *  @autoneg: boolean auto-negotiation value
 196  *
 197  *  Determines the link capabilities by reading the AUTOC register.
 198  **/
 199 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 200                                                     ixgbe_link_speed *speed,
 201                                                     bool *autoneg)
 202 {
 203         s32 status = IXGBE_ERR_LINK_SETUP;
 204         u16 speed_ability;
 205
 206         *speed = 0;
 207         *autoneg = true;
 208
 209         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 210                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 211                                       &speed_ability);
 212
 213         if (status == 0) {
 214                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 215                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 216                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 217                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 218         }
 219
 220         return status;
 221 }
 222
 223 /**
 224  *  ixgbe_get_media_type_82598 - Determines media type
 225  *  @hw: pointer to hardware structure
 226  *
 227  *  Returns the media type (fiber, copper, backplane)
 228  **/
 229 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 230 {
 231         enum ixgbe_media_type media_type;
 232
 233         /* Media type for I82598 is based on device ID */
 234         switch (hw->device_id) {
 235         case IXGBE_DEV_ID_82598:
 236         case IXGBE_DEV_ID_82598_BX:
 237                 media_type = ixgbe_media_type_backplane;
 238                 break;
 239         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 240         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 241         case IXGBE_DEV_ID_82598EB_CX4:
 242         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 243         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 244         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 245         case IXGBE_DEV_ID_82598EB_XF_LR:
 246         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 247                 media_type = ixgbe_media_type_fiber;
 248                 break;
 249         case IXGBE_DEV_ID_82598AT:
 250                 media_type = ixgbe_media_type_copper;
 251                 break;
 252         default:
 253                 media_type = ixgbe_media_type_unknown;
 254                 break;
 255         }
 256
 257         return media_type;
 258 }
 259
 260 /**
 261  *  ixgbe_fc_enable_82598 - Enable flow control
 262  *  @hw: pointer to hardware structure
 263  *  @packetbuf_num: packet buffer number (0-7)
 264  *
 265  *  Enable flow control according to the current settings.
 266  **/
 267 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 268 {
 269         s32 ret_val = 0;
 270         u32 fctrl_reg;
 271         u32 rmcs_reg;
 272         u32 reg;
 273
 274         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 275         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 276
 277         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 278         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 279
 280         /*
 281          * The possible values of fc.current_mode are:
 282          * 0: Flow control is completely disabled
 283          * 1: Rx flow control is enabled (we can receive pause frames,
 284          *    but not send pause frames).
 285          * 2:  Tx flow control is enabled (we can send pause frames but
 286          *     we do not support receiving pause frames).
 287          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 288          * other: Invalid.
 289          */
 290         switch (hw->fc.current_mode) {
 291         case ixgbe_fc_none:
 292                 /* Flow control completely disabled by software override. */
 293                 break;
 294         case ixgbe_fc_rx_pause:
 295                 /*
 296                  * Rx Flow control is enabled and Tx Flow control is
 297                  * disabled by software override. Since there really
 298                  * isn't a way to advertise that we are capable of RX
 299                  * Pause ONLY, we will advertise that we support both
 300                  * symmetric and asymmetric Rx PAUSE.  Later, we will
 301                  * disable the adapter's ability to send PAUSE frames.
 302                  */
 303                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 304                 break;
 305         case ixgbe_fc_tx_pause:
 306                 /*
 307                  * Tx Flow control is enabled, and Rx Flow control is
 308                  * disabled by software override.
 309                  */
 310                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 311                 break;
 312         case ixgbe_fc_full:
 313                 /* Flow control (both Rx and Tx) is enabled by SW override. */
 314                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 315                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 316                 break;
 317         default:
 318                 hw_dbg(hw, "Flow control param set incorrectly\n");
 319                 ret_val = -IXGBE_ERR_CONFIG;
 320                 goto out;
 321                 break;
 322         }
 323
 324         /* Enable 802.3x based flow control settings. */
 325         fctrl_reg |= IXGBE_FCTRL_DPF;
 326         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 327         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 328
 329         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 330         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
 331                 if (hw->fc.send_xon) {
 332                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 333                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 334                 } else {
 335                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 336                                         hw->fc.low_water);
 337                 }
 338
 339                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 340                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 341         }
 342
 343         /* Configure pause time (2 TCs per register) */
 344         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
 345         if ((packetbuf_num & 1) == 0)
 346                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 347         else
 348                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
 349         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
 350
 351         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 352
 353 out:
 354         return ret_val;
 355 }
 356
 357 /**
 358  *  ixgbe_setup_fc_82598 - Configure flow control settings
 359  *  @hw: pointer to hardware structure
 360  *  @packetbuf_num: packet buffer number (0-7)
 361  *
 362  *  Configures the flow control settings based on SW configuration.  This
 363  *  function is used for 802.3x flow control configuration only.
 364  **/
 365 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 366 {
 367         s32 ret_val = 0;
 368         ixgbe_link_speed speed;
 369         bool link_up;
 370
 371         /* Validate the packetbuf configuration */
 372         if (packetbuf_num < 0 || packetbuf_num > 7) {
 373                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
 374                           " 0-7\n", packetbuf_num);
 375                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 376                 goto out;
 377         }
 378
 379         /*
 380          * Validate the water mark configuration.  Zero water marks are invalid
 381          * because it causes the controller to just blast out fc packets.
 382          */
 383         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
 384                 if (hw->fc.requested_mode != ixgbe_fc_none) {
 385                         hw_dbg(hw, "Invalid water mark configuration\n");
 386                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 387                         goto out;
 388                 }
 389         }
 390
 391         /*
 392          * Validate the requested mode.  Strict IEEE mode does not allow
 393          * ixgbe_fc_rx_pause because it will cause testing anomalies.
 394          */
 395         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 396                 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 397                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 398                 goto out;
 399         }
 400
 401         /*
 402          * 10gig parts do not have a word in the EEPROM to determine the
 403          * default flow control setting, so we explicitly set it to full.
 404          */
 405         if (hw->fc.requested_mode == ixgbe_fc_default)
 406                 hw->fc.requested_mode = ixgbe_fc_full;
 407
 408         /*
 409          * Save off the requested flow control mode for use later.  Depending
 410          * on the link partner's capabilities, we may or may not use this mode.
 411          */
 412
 413         hw->fc.current_mode = hw->fc.requested_mode;
 414
 415         /* Decide whether to use autoneg or not. */
 416         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 417         if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
 418             (speed == IXGBE_LINK_SPEED_1GB_FULL))
 419                 ret_val = ixgbe_fc_autoneg(hw);
 420
 421         if (ret_val)
 422                 goto out;
 423
 424         ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
 425
 426 out:
 427         return ret_val;
 428 }
 429
 430 /**
 431  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 432  *  @hw: pointer to hardware structure
 433  *
 434  *  Configures link settings based on values in the ixgbe_hw struct.
 435  *  Restarts the link.  Performs autonegotiation if needed.
 436  **/
 437 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 438 {
 439         u32 autoc_reg;
 440         u32 links_reg;
 441         u32 i;
 442         s32 status = 0;
 443
 444         /* Restart link */
 445         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 446         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 447         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 448
 449         /* Only poll for autoneg to complete if specified to do so */
 450         if (hw->phy.autoneg_wait_to_complete) {
 451                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 452                      IXGBE_AUTOC_LMS_KX4_AN ||
 453                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 454                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 455                         links_reg = 0; /* Just in case Autoneg time = 0 */
 456                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 457                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 458                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 459                                         break;
 460                                 msleep(100);
 461                         }
 462                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 463                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 464                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 465                         }
 466                 }
 467         }
 468
 469         /*
 470          * We want to save off the original Flow Control configuration just in
 471          * case we get disconnected and then reconnected into a different hub
 472          * or switch with different Flow Control capabilities.
 473          */
 474         ixgbe_setup_fc_82598(hw, 0);
 475
 476         /* Add delay to filter out noises during initial link setup */
 477         msleep(50);
 478
 479         return status;
 480 }
 481
 482 /**
 483  *  ixgbe_check_mac_link_82598 - Get link/speed status
 484  *  @hw: pointer to hardware structure
 485  *  @speed: pointer to link speed
 486  *  @link_up: true is link is up, false otherwise
 487  *  @link_up_wait_to_complete: bool used to wait for link up or not
 488  *
 489  *  Reads the links register to determine if link is up and the current speed
 490  **/
 491 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 492                                       ixgbe_link_speed *speed, bool *link_up,
 493                                       bool link_up_wait_to_complete)
 494 {
 495         u32 links_reg;
 496         u32 i;
 497         u16 link_reg, adapt_comp_reg;
 498
 499         /*
 500          * SERDES PHY requires us to read link status from register 0xC79F.
 501          * Bit 0 set indicates link is up/ready; clear indicates link down.
 502          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 503          * clear indicates active; set indicates inactive.
 504          */
 505         if (hw->phy.type == ixgbe_phy_nl) {
 506                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 507                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 508                 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
 509                                      &adapt_comp_reg);
 510                 if (link_up_wait_to_complete) {
 511                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 512                                 if ((link_reg & 1) &&
 513                                     ((adapt_comp_reg & 1) == 0)) {
 514                                         *link_up = true;
 515                                         break;
 516                                 } else {
 517                                         *link_up = false;
 518                                 }
 519                                 msleep(100);
 520                                 hw->phy.ops.read_reg(hw, 0xC79F,
 521                                                      IXGBE_TWINAX_DEV,
 522                                                      &link_reg);
 523                                 hw->phy.ops.read_reg(hw, 0xC00C,
 524                                                      IXGBE_TWINAX_DEV,
 525                                                      &adapt_comp_reg);
 526                         }
 527                 } else {
 528                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 529                                 *link_up = true;
 530                         else
 531                                 *link_up = false;
 532                 }
 533
 534                 if (*link_up == false)
 535                         goto out;
 536         }
 537
 538         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 539         if (link_up_wait_to_complete) {
 540                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 541                         if (links_reg & IXGBE_LINKS_UP) {
 542                                 *link_up = true;
 543                                 break;
 544                         } else {
 545                                 *link_up = false;
 546                         }
 547                         msleep(100);
 548                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 549                 }
 550         } else {
 551                 if (links_reg & IXGBE_LINKS_UP)
 552                         *link_up = true;
 553                 else
 554                         *link_up = false;
 555         }
 556
 557         if (links_reg & IXGBE_LINKS_SPEED)
 558                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 559         else
 560                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 561
 562 out:
 563         return 0;
 564 }
 565
 566
 567 /**
 568  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 569  *  @hw: pointer to hardware structure
 570  *  @speed: new link speed
 571  *  @autoneg: true if auto-negotiation enabled
 572  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 573  *
 574  *  Set the link speed in the AUTOC register and restarts link.
 575  **/
 576 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 577                                            ixgbe_link_speed speed, bool autoneg,
 578                                            bool autoneg_wait_to_complete)
 579 {
 580         s32              status            = 0;
 581         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 582         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 583         u32              autoc             = curr_autoc;
 584         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 585
 586         /* Check to see if speed passed in is supported. */
 587         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 588         speed &= link_capabilities;
 589
 590         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 591                 status = IXGBE_ERR_LINK_SETUP;
 592
 593         /* Set KX4/KX support according to speed requested */
 594         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 595                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 596                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 597                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 598                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 599                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 600                         autoc |= IXGBE_AUTOC_KX_SUPP;
 601                 if (autoc != curr_autoc)
 602                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 603         }
 604
 605         if (status == 0) {
 606                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 607
 608                 /*
 609                  * Setup and restart the link based on the new values in
 610                  * ixgbe_hw This will write the AUTOC register based on the new
 611                  * stored values
 612                  */
 613                 status = ixgbe_setup_mac_link_82598(hw);
 614         }
 615
 616         return status;
 617 }
 618
 619
 620 /**
 621  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 622  *  @hw: pointer to hardware structure
 623  *
 624  *  Configures link settings based on values in the ixgbe_hw struct.
 625  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 626  *  phy and wait for autonegotiate to finish.  Then synchronize the
 627  *  MAC and PHY.
 628  **/
 629 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 630 {
 631         s32 status;
 632
 633         /* Restart autonegotiation on PHY */
 634         status = hw->phy.ops.setup_link(hw);
 635
 636         /* Set up MAC */
 637         ixgbe_setup_mac_link_82598(hw);
 638
 639         return status;
 640 }
 641
 642 /**
 643  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 644  *  @hw: pointer to hardware structure
 645  *  @speed: new link speed
 646  *  @autoneg: true if autonegotiation enabled
 647  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 648  *
 649  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 650  **/
 651 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 652                                                ixgbe_link_speed speed,
 653                                                bool autoneg,
 654                                                bool autoneg_wait_to_complete)
 655 {
 656         s32 status;
 657
 658         /* Setup the PHY according to input speed */
 659         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 660                                               autoneg_wait_to_complete);
 661
 662         /* Set up MAC */
 663         ixgbe_setup_mac_link_82598(hw);
 664
 665         return status;
 666 }
 667
 668 /**
 669  *  ixgbe_reset_hw_82598 - Performs hardware reset
 670  *  @hw: pointer to hardware structure
 671  *
 672  *  Resets the hardware by resetting the transmit and receive units, masks and
 673  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 674  *  reset.
 675  **/
 676 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 677 {
 678         s32 status = 0;
 679         u32 ctrl;
 680         u32 gheccr;
 681         u32 i;
 682         u32 autoc;
 683         u8  analog_val;
 684
 685         /* Call adapter stop to disable tx/rx and clear interrupts */
 686         hw->mac.ops.stop_adapter(hw);
 687
 688         /*
 689          * Power up the Atlas Tx lanes if they are currently powered down.
 690          * Atlas Tx lanes are powered down for MAC loopback tests, but
 691          * they are not automatically restored on reset.
 692          */
 693         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 694         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 695                 /* Enable Tx Atlas so packets can be transmitted again */
 696                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 697                                              &analog_val);
 698                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 699                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 700                                               analog_val);
 701
 702                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 703                                              &analog_val);
 704                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 705                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 706                                               analog_val);
 707
 708                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 709                                              &analog_val);
 710                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 711                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 712                                               analog_val);
 713
 714                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 715                                              &analog_val);
 716                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 717                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 718                                               analog_val);
 719         }
 720
 721         /* Reset PHY */
 722         if (hw->phy.reset_disable == false)
 723                 hw->phy.ops.reset(hw);
 724
 725         /*
 726          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 727          * access and verify no pending requests before reset
 728          */
 729         if (ixgbe_disable_pcie_master(hw) != 0) {
 730                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 731                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 732         }
 733
 734         /*
 735          * Issue global reset to the MAC.  This needs to be a SW reset.
 736          * If link reset is used, it might reset the MAC when mng is using it
 737          */
 738         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 739         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 740         IXGBE_WRITE_FLUSH(hw);
 741
 742         /* Poll for reset bit to self-clear indicating reset is complete */
 743         for (i = 0; i < 10; i++) {
 744                 udelay(1);
 745                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 746                 if (!(ctrl & IXGBE_CTRL_RST))
 747                         break;
 748         }
 749         if (ctrl & IXGBE_CTRL_RST) {
 750                 status = IXGBE_ERR_RESET_FAILED;
 751                 hw_dbg(hw, "Reset polling failed to complete.\n");
 752         }
 753
 754         msleep(50);
 755
 756         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 757         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 758         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 759
 760         /*
 761          * Store the original AUTOC value if it has not been
 762          * stored off yet.  Otherwise restore the stored original
 763          * AUTOC value since the reset operation sets back to deaults.
 764          */
 765         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 766         if (hw->mac.orig_link_settings_stored == false) {
 767                 hw->mac.orig_autoc = autoc;
 768                 hw->mac.orig_link_settings_stored = true;
 769         } else if (autoc != hw->mac.orig_autoc) {
 770                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 771         }
 772
 773         /* Store the permanent mac address */
 774         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 775
 776         return status;
 777 }
 778
 779 /**
 780  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 781  *  @hw: pointer to hardware struct
 782  *  @rar: receive address register index to associate with a VMDq index
 783  *  @vmdq: VMDq set index
 784  **/
 785 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 786 {
 787         u32 rar_high;
 788
 789         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 790         rar_high &= ~IXGBE_RAH_VIND_MASK;
 791         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 792         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 793         return 0;
 794 }
 795
 796 /**
 797  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 798  *  @hw: pointer to hardware struct
 799  *  @rar: receive address register index to associate with a VMDq index
 800  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 801  **/
 802 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 803 {
 804         u32 rar_high;
 805         u32 rar_entries = hw->mac.num_rar_entries;
 806
 807         if (rar < rar_entries) {
 808                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 809                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 810                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 811                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 812                 }
 813         } else {
 814                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 815         }
 816
 817         return 0;
 818 }
 819
 820 /**
 821  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 822  *  @hw: pointer to hardware structure
 823  *  @vlan: VLAN id to write to VLAN filter
 824  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 825  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 826  *
 827  *  Turn on/off specified VLAN in the VLAN filter table.
 828  **/
 829 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 830                                 bool vlan_on)
 831 {
 832         u32 regindex;
 833         u32 bitindex;
 834         u32 bits;
 835         u32 vftabyte;
 836
 837         if (vlan > 4095)
 838                 return IXGBE_ERR_PARAM;
 839
 840         /* Determine 32-bit word position in array */
 841         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 842
 843         /* Determine the location of the (VMD) queue index */
 844         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 845         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 846
 847         /* Set the nibble for VMD queue index */
 848         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 849         bits &= (~(0x0F << bitindex));
 850         bits |= (vind << bitindex);
 851         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 852
 853         /* Determine the location of the bit for this VLAN id */
 854         bitindex = vlan & 0x1F;   /* lower five bits */
 855
 856         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 857         if (vlan_on)
 858                 /* Turn on this VLAN id */
 859                 bits |= (1 << bitindex);
 860         else
 861                 /* Turn off this VLAN id */
 862                 bits &= ~(1 << bitindex);
 863         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 864
 865         return 0;
 866 }
 867
 868 /**
 869  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 870  *  @hw: pointer to hardware structure
 871  *
 872  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 873  **/
 874 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 875 {
 876         u32 offset;
 877         u32 vlanbyte;
 878
 879         for (offset = 0; offset < hw->mac.vft_size; offset++)
 880                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 881
 882         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 883                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 884                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 885                                         0);
 886
 887         return 0;
 888 }
 889
 890 /**
 891  *  ixgbe_blink_led_start_82598 - Blink LED based on index.
 892  *  @hw: pointer to hardware structure
 893  *  @index: led number to blink
 894  **/
 895 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
 896 {
 897         ixgbe_link_speed speed = 0;
 898         bool link_up = 0;
 899         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 900         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 901
 902         /*
 903          * Link must be up to auto-blink the LEDs on the 82598EB MAC;
 904          * force it if link is down.
 905          */
 906         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 907
 908         if (!link_up) {
 909                 autoc_reg |= IXGBE_AUTOC_FLU;
 910                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 911                 msleep(10);
 912         }
 913
 914         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 915         led_reg |= IXGBE_LED_BLINK(index);
 916         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 917         IXGBE_WRITE_FLUSH(hw);
 918
 919         return 0;
 920 }
 921
 922 /**
 923  *  ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
 924  *  @hw: pointer to hardware structure
 925  *  @index: led number to stop blinking
 926  **/
 927 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
 928 {
 929         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 930         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 931
 932         autoc_reg &= ~IXGBE_AUTOC_FLU;
 933         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 934         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 935
 936         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 937         led_reg &= ~IXGBE_LED_BLINK(index);
 938         led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 939         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 940         IXGBE_WRITE_FLUSH(hw);
 941
 942         return 0;
 943 }
 944
 945 /**
 946  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 947  *  @hw: pointer to hardware structure
 948  *  @reg: analog register to read
 949  *  @val: read value
 950  *
 951  *  Performs read operation to Atlas analog register specified.
 952  **/
 953 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 954 {
 955         u32  atlas_ctl;
 956
 957         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 958                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 959         IXGBE_WRITE_FLUSH(hw);
 960         udelay(10);
 961         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 962         *val = (u8)atlas_ctl;
 963
 964         return 0;
 965 }
 966
 967 /**
 968  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
 969  *  @hw: pointer to hardware structure
 970  *  @reg: atlas register to write
 971  *  @val: value to write
 972  *
 973  *  Performs write operation to Atlas analog register specified.
 974  **/
 975 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 976 {
 977         u32  atlas_ctl;
 978
 979         atlas_ctl = (reg << 8) | val;
 980         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
 981         IXGBE_WRITE_FLUSH(hw);
 982         udelay(10);
 983
 984         return 0;
 985 }
 986
 987 /**
 988  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
 989  *  over I2C interface through an intermediate phy.
 990  *  @hw: pointer to hardware structure
 991  *  @byte_offset: EEPROM byte offset to read
 992  *  @eeprom_data: value read
 993  *
 994  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 995  **/
 996 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
 997                                        u8 *eeprom_data)
 998 {
 999         s32 status = 0;
1000         u16 sfp_addr = 0;
1001         u16 sfp_data = 0;
1002         u16 sfp_stat = 0;
1003         u32 i;
1004
1005         if (hw->phy.type == ixgbe_phy_nl) {
1006                 /*
1007                  * phy SDA/SCL registers are at addresses 0xC30A to
1008                  * 0xC30D.  These registers are used to talk to the SFP+
1009                  * module's EEPROM through the SDA/SCL (I2C) interface.
1010                  */
1011                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1012                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1013                 hw->phy.ops.write_reg(hw,
1014                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1015                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1016                                       sfp_addr);
1017
1018                 /* Poll status */
1019                 for (i = 0; i < 100; i++) {
1020                         hw->phy.ops.read_reg(hw,
1021                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1022                                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1023                                              &sfp_stat);
1024                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1025                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1026                                 break;
1027                         msleep(10);
1028                 }
1029
1030                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1031                         hw_dbg(hw, "EEPROM read did not pass.\n");
1032                         status = IXGBE_ERR_SFP_NOT_PRESENT;
1033                         goto out;
1034                 }
1035
1036                 /* Read data */
1037                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1038                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1039
1040                 *eeprom_data = (u8)(sfp_data >> 8);
1041         } else {
1042                 status = IXGBE_ERR_PHY;
1043                 goto out;
1044         }
1045
1046 out:
1047         return status;
1048 }
1049
1050 /**
1051  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1052  *  @hw: pointer to hardware structure
1053  *
1054  *  Determines physical layer capabilities of the current configuration.
1055  **/
1056 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1057 {
1058         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1059
1060         switch (hw->device_id) {
1061         case IXGBE_DEV_ID_82598:
1062                 /* Default device ID is mezzanine card KX/KX4 */
1063                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1064                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1065                 break;
1066         case IXGBE_DEV_ID_82598_BX:
1067                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1068         case IXGBE_DEV_ID_82598EB_CX4:
1069         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1070                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1071                 break;
1072         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1073                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1074                 break;
1075         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1076         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1077         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1078                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1079                 break;
1080         case IXGBE_DEV_ID_82598EB_XF_LR:
1081                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1082                 break;
1083         case IXGBE_DEV_ID_82598AT:
1084                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1085                                   IXGBE_PHYSICAL_LAYER_1000BASE_T);
1086                 break;
1087         case IXGBE_DEV_ID_82598EB_SFP_LOM:
1088                 hw->phy.ops.identify_sfp(hw);
1089
1090                 switch (hw->phy.sfp_type) {
1091                 case ixgbe_sfp_type_da_cu:
1092                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1093                         break;
1094                 case ixgbe_sfp_type_sr:
1095                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1096                         break;
1097                 case ixgbe_sfp_type_lr:
1098                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1099                         break;
1100                 default:
1101                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1102                         break;
1103                 }
1104                 break;
1105
1106         default:
1107                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1108                 break;
1109         }
1110
1111         return physical_layer;
1112 }
1113
1114 static struct ixgbe_mac_operations mac_ops_82598 = {
1115         .init_hw                = &ixgbe_init_hw_generic,
1116         .reset_hw               = &ixgbe_reset_hw_82598,
1117         .start_hw               = &ixgbe_start_hw_generic,
1118         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1119         .get_media_type         = &ixgbe_get_media_type_82598,
1120         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1121         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1122         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1123         .stop_adapter           = &ixgbe_stop_adapter_generic,
1124         .get_bus_info           = &ixgbe_get_bus_info_generic,
1125         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1126         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1127         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1128         .setup_link             = &ixgbe_setup_mac_link_82598,
1129         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1130         .check_link             = &ixgbe_check_mac_link_82598,
1131         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1132         .led_on                 = &ixgbe_led_on_generic,
1133         .led_off                = &ixgbe_led_off_generic,
1134         .blink_led_start        = &ixgbe_blink_led_start_82598,
1135         .blink_led_stop         = &ixgbe_blink_led_stop_82598,
1136         .set_rar                = &ixgbe_set_rar_generic,
1137         .clear_rar              = &ixgbe_clear_rar_generic,
1138         .set_vmdq               = &ixgbe_set_vmdq_82598,
1139         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1140         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1141         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1142         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1143         .enable_mc              = &ixgbe_enable_mc_generic,
1144         .disable_mc             = &ixgbe_disable_mc_generic,
1145         .clear_vfta             = &ixgbe_clear_vfta_82598,
1146         .set_vfta               = &ixgbe_set_vfta_82598,
1147         .setup_fc               = &ixgbe_setup_fc_82598,
1148 };
1149
1150 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1151         .init_params            = &ixgbe_init_eeprom_params_generic,
1152         .read                   = &ixgbe_read_eeprom_generic,
1153         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1154         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1155 };
1156
1157 static struct ixgbe_phy_operations phy_ops_82598 = {
1158         .identify               = &ixgbe_identify_phy_generic,
1159         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1160         .reset                  = &ixgbe_reset_phy_generic,
1161         .read_reg               = &ixgbe_read_phy_reg_generic,
1162         .write_reg              = &ixgbe_write_phy_reg_generic,
1163         .setup_link             = &ixgbe_setup_phy_link_generic,
1164         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1165         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1166 };
1167
1168 struct ixgbe_info ixgbe_82598_info = {
1169         .mac                    = ixgbe_mac_82598EB,
1170         .get_invariants         = &ixgbe_get_invariants_82598,
1171         .mac_ops                = &mac_ops_82598,
1172         .eeprom_ops             = &eeprom_ops_82598,
1173         .phy_ops                = &phy_ops_82598,
1174 };
1175