1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/inet_lro.h>
37 #include "ixgbe_type.h"
38 #include "ixgbe_common.h"
40 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
41 #include <linux/dca.h>
45 #define DPRINTK(nlevel, klevel, fmt, args...) \
46 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
47 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
48 __FUNCTION__ , ## args)))
50 /* TX/RX descriptor defines */
51 #define IXGBE_DEFAULT_TXD 1024
52 #define IXGBE_MAX_TXD 4096
53 #define IXGBE_MIN_TXD 64
55 #define IXGBE_DEFAULT_RXD 1024
56 #define IXGBE_MAX_RXD 4096
57 #define IXGBE_MIN_RXD 64
60 #define IXGBE_DEFAULT_FCRTL 0x10000
61 #define IXGBE_MIN_FCRTL 0x40
62 #define IXGBE_MAX_FCRTL 0x7FF80
63 #define IXGBE_DEFAULT_FCRTH 0x20000
64 #define IXGBE_MIN_FCRTH 0x600
65 #define IXGBE_MAX_FCRTH 0x7FFF0
66 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
67 #define IXGBE_MIN_FCPAUSE 0
68 #define IXGBE_MAX_FCPAUSE 0xFFFF
70 /* Supported Rx Buffer Sizes */
71 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
72 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
73 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
74 #define IXGBE_RXBUFFER_2048 2048
76 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
78 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
80 /* How many Rx Buffers do we bundle into one write to the hardware ? */
81 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
83 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
84 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
85 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
86 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
87 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
88 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
90 #define IXGBE_MAX_LRO_DESCRIPTORS 8
91 #define IXGBE_MAX_LRO_AGGREGATE 32
93 /* wrapper around a pointer to a socket buffer,
94 * so a DMA handle can be stored along with the buffer */
95 struct ixgbe_tx_buffer {
98 unsigned long time_stamp;
103 struct ixgbe_rx_buffer {
108 unsigned int page_offset;
111 struct ixgbe_queue_stats {
117 void *desc; /* descriptor ring memory */
118 dma_addr_t dma; /* phys. address of descriptor ring */
119 unsigned int size; /* length in bytes */
120 unsigned int count; /* amount of descriptors */
121 unsigned int next_to_use;
122 unsigned int next_to_clean;
124 int queue_index; /* needed for multiqueue queue management */
126 struct ixgbe_tx_buffer *tx_buffer_info;
127 struct ixgbe_rx_buffer *rx_buffer_info;
133 unsigned int total_bytes;
134 unsigned int total_packets;
136 u16 reg_idx; /* holds the special value that gets the hardware register
137 * offset associated with this ring, which is different
138 * for DCE and RSS modes */
140 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
141 /* cpu for tx queue */
144 struct net_lro_mgr lro_mgr;
146 struct ixgbe_queue_stats stats;
147 u16 v_idx; /* maps directly to the index for this ring in the hardware
148 * vector array, can also be used for finding the bit in EICR
149 * and friends that represents the vector for this ring */
152 u16 work_limit; /* max work per interrupt */
156 #define RING_F_VMDQ 1
158 #define IXGBE_MAX_RSS_INDICES 16
159 #define IXGBE_MAX_VMDQ_INDICES 16
160 struct ixgbe_ring_feature {
165 #define MAX_RX_QUEUES 64
166 #define MAX_TX_QUEUES 32
168 /* MAX_MSIX_Q_VECTORS of these are allocated,
169 * but we only use one per queue-specific vector.
171 struct ixgbe_q_vector {
172 struct ixgbe_adapter *adapter;
173 struct napi_struct napi;
174 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
175 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
176 u8 rxr_count; /* Rx ring count assigned to this vector */
177 u8 txr_count; /* Tx ring count assigned to this vector */
183 /* Helper macros to switch between ints/sec and what the register uses.
184 * And yes, it's the same math going both ways.
186 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
187 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
188 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
190 #define IXGBE_DESC_UNUSED(R) \
191 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
192 (R)->next_to_clean - (R)->next_to_use - 1)
194 #define IXGBE_RX_DESC_ADV(R, i) \
195 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
196 #define IXGBE_TX_DESC_ADV(R, i) \
197 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
198 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
199 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
201 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
203 #define OTHER_VECTOR 1
204 #define NON_Q_VECTORS (OTHER_VECTOR)
206 #define MAX_MSIX_Q_VECTORS 16
207 #define MIN_MSIX_Q_VECTORS 2
208 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
209 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
211 /* board specific private data structure */
212 struct ixgbe_adapter {
213 struct timer_list watchdog_timer;
214 struct vlan_group *vlgrp;
216 struct work_struct reset_task;
217 struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
218 char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
220 /* Interrupt Throttle Rate */
226 struct ixgbe_ring *tx_ring; /* One per active queue */
233 u32 tx_timeout_count;
237 struct ixgbe_ring *rx_ring; /* One per active queue */
239 u64 hw_csum_rx_error;
242 int num_msix_vectors;
243 struct ixgbe_ring_feature ring_feature[3];
244 struct msix_entry *msix_entries;
247 u32 alloc_rx_page_failed;
248 u32 alloc_rx_buff_failed;
250 /* Some features need tri-state capability,
251 * thus the additional *_CAPABLE flags.
254 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
255 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
256 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
257 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
258 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
259 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
260 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
261 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
262 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
263 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
264 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
265 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
266 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
267 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
268 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
269 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
270 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
271 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
272 #define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
274 /* default to trying for four seconds */
275 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
277 /* OS defined structs */
278 struct net_device *netdev;
279 struct pci_dev *pdev;
280 struct net_device_stats net_stats;
282 /* structs defined in ixgbe_hw.h */
285 struct ixgbe_hw_stats stats;
287 /* Interrupt Throttle Rate */
295 unsigned int tx_ring_count;
296 unsigned int rx_ring_count;
300 unsigned long link_check_timeout;
302 struct work_struct watchdog_task;
315 extern struct ixgbe_info ixgbe_82598_info;
317 extern char ixgbe_driver_name[];
318 extern const char ixgbe_driver_version[];
320 extern int ixgbe_up(struct ixgbe_adapter *adapter);
321 extern void ixgbe_down(struct ixgbe_adapter *adapter);
322 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
323 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
324 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
325 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
326 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
327 struct ixgbe_ring *rxdr);
328 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
329 struct ixgbe_ring *txdr);
330 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
331 struct ixgbe_ring *rxdr);
332 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
333 struct ixgbe_ring *txdr);
335 #endif /* _IXGBE_H_ */