1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/inet_lro.h>
37 #include "ixgbe_type.h"
38 #include "ixgbe_common.h"
40 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
41 #include <linux/dca.h>
44 #define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
47 #define DPRINTK(nlevel, klevel, fmt, args...) \
48 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
49 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
50 __FUNCTION__ , ## args)))
52 /* TX/RX descriptor defines */
53 #define IXGBE_DEFAULT_TXD 1024
54 #define IXGBE_MAX_TXD 4096
55 #define IXGBE_MIN_TXD 64
57 #define IXGBE_DEFAULT_RXD 1024
58 #define IXGBE_MAX_RXD 4096
59 #define IXGBE_MIN_RXD 64
61 #define IXGBE_DEFAULT_RXQ 1
62 #define IXGBE_MAX_RXQ 1
63 #define IXGBE_MIN_RXQ 1
66 #define IXGBE_DEFAULT_FCRTL 0x10000
67 #define IXGBE_MIN_FCRTL 0x40
68 #define IXGBE_MAX_FCRTL 0x7FF80
69 #define IXGBE_DEFAULT_FCRTH 0x20000
70 #define IXGBE_MIN_FCRTH 0x600
71 #define IXGBE_MAX_FCRTH 0x7FFF0
72 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
73 #define IXGBE_MIN_FCPAUSE 0
74 #define IXGBE_MAX_FCPAUSE 0xFFFF
76 /* Supported Rx Buffer Sizes */
77 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
78 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
79 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
80 #define IXGBE_RXBUFFER_2048 2048
82 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
84 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
86 /* How many Tx Descriptors do we need to call netif_wake_queue? */
87 #define IXGBE_TX_QUEUE_WAKE 16
89 /* How many Rx Buffers do we bundle into one write to the hardware ? */
90 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
93 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
94 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
95 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
96 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
97 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
99 #define IXGBE_MAX_LRO_DESCRIPTORS 8
100 #define IXGBE_MAX_LRO_AGGREGATE 32
102 /* wrapper around a pointer to a socket buffer,
103 * so a DMA handle can be stored along with the buffer */
104 struct ixgbe_tx_buffer {
107 unsigned long time_stamp;
112 struct ixgbe_rx_buffer {
119 struct ixgbe_queue_stats {
125 void *desc; /* descriptor ring memory */
126 dma_addr_t dma; /* phys. address of descriptor ring */
127 unsigned int size; /* length in bytes */
128 unsigned int count; /* amount of descriptors */
129 unsigned int next_to_use;
130 unsigned int next_to_clean;
132 int queue_index; /* needed for multiqueue queue management */
134 struct ixgbe_tx_buffer *tx_buffer_info;
135 struct ixgbe_rx_buffer *rx_buffer_info;
141 unsigned int total_bytes;
142 unsigned int total_packets;
144 u16 reg_idx; /* holds the special value that gets the hardware register
145 * offset associated with this ring, which is different
146 * for DCE and RSS modes */
148 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
149 /* cpu for tx queue */
152 struct net_lro_mgr lro_mgr;
154 struct ixgbe_queue_stats stats;
155 u16 v_idx; /* maps directly to the index for this ring in the hardware
156 * vector array, can also be used for finding the bit in EICR
157 * and friends that represents the vector for this ring */
160 u16 work_limit; /* max work per interrupt */
164 #define RING_F_VMDQ 1
166 #define IXGBE_MAX_RSS_INDICES 16
167 #define IXGBE_MAX_VMDQ_INDICES 16
168 struct ixgbe_ring_feature {
173 #define MAX_RX_QUEUES 64
174 #define MAX_TX_QUEUES 32
176 /* MAX_MSIX_Q_VECTORS of these are allocated,
177 * but we only use one per queue-specific vector.
179 struct ixgbe_q_vector {
180 struct ixgbe_adapter *adapter;
181 struct napi_struct napi;
182 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
183 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
184 u8 rxr_count; /* Rx ring count assigned to this vector */
185 u8 txr_count; /* Tx ring count assigned to this vector */
191 /* Helper macros to switch between ints/sec and what the register uses.
192 * And yes, it's the same math going both ways.
194 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
195 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
196 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
198 #define IXGBE_DESC_UNUSED(R) \
199 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
200 (R)->next_to_clean - (R)->next_to_use - 1)
202 #define IXGBE_RX_DESC_ADV(R, i) \
203 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
204 #define IXGBE_TX_DESC_ADV(R, i) \
205 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
206 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
207 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
209 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
211 #define OTHER_VECTOR 1
212 #define NON_Q_VECTORS (OTHER_VECTOR)
214 #define MAX_MSIX_Q_VECTORS 16
215 #define MIN_MSIX_Q_VECTORS 2
216 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
217 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
219 /* board specific private data structure */
220 struct ixgbe_adapter {
221 struct timer_list watchdog_timer;
222 struct vlan_group *vlgrp;
224 struct work_struct reset_task;
225 struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
226 char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
228 /* Interrupt Throttle Rate */
234 struct ixgbe_ring *tx_ring; /* One per active queue */
241 u32 tx_timeout_count;
245 struct ixgbe_ring *rx_ring; /* One per active queue */
247 u64 hw_csum_rx_error;
250 int num_msix_vectors;
251 struct ixgbe_ring_feature ring_feature[3];
252 struct msix_entry *msix_entries;
255 u32 alloc_rx_page_failed;
256 u32 alloc_rx_buff_failed;
258 /* Some features need tri-state capability,
259 * thus the additional *_CAPABLE flags.
262 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
263 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
264 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
265 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
266 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
267 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
268 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
269 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
270 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
271 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
272 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
273 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
274 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
275 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
276 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
277 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
278 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
279 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
280 #define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
282 /* default to trying for four seconds */
283 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
285 /* OS defined structs */
286 struct net_device *netdev;
287 struct pci_dev *pdev;
288 struct net_device_stats net_stats;
290 /* structs defined in ixgbe_hw.h */
293 struct ixgbe_hw_stats stats;
295 /* Interrupt Throttle Rate */
303 unsigned int tx_ring_count;
304 unsigned int rx_ring_count;
308 unsigned long link_check_timeout;
310 struct work_struct watchdog_task;
323 extern struct ixgbe_info ixgbe_82598_info;
325 extern char ixgbe_driver_name[];
326 extern const char ixgbe_driver_version[];
328 extern int ixgbe_up(struct ixgbe_adapter *adapter);
329 extern void ixgbe_down(struct ixgbe_adapter *adapter);
330 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
331 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
332 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
333 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
334 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
335 struct ixgbe_ring *rxdr);
336 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
337 struct ixgbe_ring *txdr);
339 #endif /* _IXGBE_H_ */