SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/irda/w83977af_ir.c

   1 /*********************************************************************
   2  *
   3  * Filename:      w83977af_ir.c
   4  * Version:       1.0
   5  * Description:   FIR driver for the Winbond W83977AF Super I/O chip
   6  * Status:        Experimental.
   7  * Author:        Paul VanderSpek
   8  * Created at:    Wed Nov  4 11:46:16 1998
   9  * Modified at:   Fri Jan 28 12:10:59 2000
  10  * Modified by:   Dag Brattli <dagb@cs.uit.no>
  11  *
  12  *     Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
  13  *     Copyright (c) 1998-1999 Rebel.com
  14  *
  15  *     This program is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of
  18  *     the License, or (at your option) any later version.
  19  *
  20  *     Neither Paul VanderSpek nor Rebel.com admit liability nor provide
  21  *     warranty for any of this software. This material is provided "AS-IS"
  22  *     and at no charge.
  23  *
  24  *     If you find bugs in this file, its very likely that the same bug
  25  *     will also be in pc87108.c since the implementations are quite
  26  *     similar.
  27  *
  28  *     Notice that all functions that needs to access the chip in _any_
  29  *     way, must save BSR register on entry, and restore it on exit.
  30  *     It is _very_ important to follow this policy!
  31  *
  32  *         __u8 bank;
  33  *
  34  *         bank = inb( iobase+BSR);
  35  *
  36  *         do_your_stuff_here();
  37  *
  38  *         outb( bank, iobase+BSR);
  39  *
  40  ********************************************************************/
  41
  42 #include <linux/module.h>
  43 #include <linux/kernel.h>
  44 #include <linux/types.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/netdevice.h>
  47 #include <linux/ioport.h>
  48 #include <linux/delay.h>
  49 #include <linux/slab.h>
  50 #include <linux/init.h>
  51 #include <linux/rtnetlink.h>
  52 #include <linux/dma-mapping.h>
  53
  54 #include <asm/io.h>
  55 #include <asm/dma.h>
  56 #include <asm/byteorder.h>
  57
  58 #include <net/irda/irda.h>
  59 #include <net/irda/wrapper.h>
  60 #include <net/irda/irda_device.h>
  61 #include "w83977af.h"
  62 #include "w83977af_ir.h"
  63
  64 #ifdef  CONFIG_ARCH_NETWINDER            /* Adjust to NetWinder differences */
  65 #undef  CONFIG_NETWINDER_TX_DMA_PROBLEMS /* Not needed */
  66 #define CONFIG_NETWINDER_RX_DMA_PROBLEMS /* Must have this one! */
  67 #endif
  68 #undef  CONFIG_USE_INTERNAL_TIMER  /* Just cannot make that timer work */
  69 #define CONFIG_USE_W977_PNP        /* Currently needed */
  70 #define PIO_MAX_SPEED       115200
  71
  72 static char *driver_name = "w83977af_ir";
  73 static int  qos_mtt_bits = 0x07;   /* 1 ms or more */
  74
  75 #define CHIP_IO_EXTENT 8
  76
  77 static unsigned int io[] = { 0x180, ~0, ~0, ~0 };
  78 #ifdef CONFIG_ARCH_NETWINDER             /* Adjust to NetWinder differences */
  79 static unsigned int irq[] = { 6, 0, 0, 0 };
  80 #else
  81 static unsigned int irq[] = { 11, 0, 0, 0 };
  82 #endif
  83 static unsigned int dma[] = { 1, 0, 0, 0 };
  84 static unsigned int efbase[] = { W977_EFIO_BASE, W977_EFIO2_BASE };
  85 static unsigned int efio = W977_EFIO_BASE;
  86
  87 static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL};
  88
  89 /* Some prototypes */
  90 static int  w83977af_open(int i, unsigned int iobase, unsigned int irq,
  91                           unsigned int dma);
  92 static int  w83977af_close(struct w83977af_ir *self);
  93 static int  w83977af_probe(int iobase, int irq, int dma);
  94 static int  w83977af_dma_receive(struct w83977af_ir *self);
  95 static int  w83977af_dma_receive_complete(struct w83977af_ir *self);
  96 static int  w83977af_hard_xmit(struct sk_buff *skb, struct net_device *dev);
  97 static int  w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
  98 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
  99 static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed);
 100 static int  w83977af_is_receiving(struct w83977af_ir *self);
 101
 102 static int  w83977af_net_open(struct net_device *dev);
 103 static int  w83977af_net_close(struct net_device *dev);
 104 static int  w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 105
 106 /*
 107  * Function w83977af_init ()
 108  *
 109  *    Initialize chip. Just try to find out how many chips we are dealing with
 110  *    and where they are
 111  */
 112 static int __init w83977af_init(void)
 113 {
 114         int i;
 115
 116         IRDA_DEBUG(0, "%s()\n", __func__ );
 117
 118         for (i=0; (io[i] < 2000) && (i < ARRAY_SIZE(dev_self)); i++) {
 119                 if (w83977af_open(i, io[i], irq[i], dma[i]) == 0)
 120                         return 0;
 121         }
 122         return -ENODEV;
 123 }
 124
 125 /*
 126  * Function w83977af_cleanup ()
 127  *
 128  *    Close all configured chips
 129  *
 130  */
 131 static void __exit w83977af_cleanup(void)
 132 {
 133         int i;
 134
 135         IRDA_DEBUG(4, "%s()\n", __func__ );
 136
 137         for (i=0; i < ARRAY_SIZE(dev_self); i++) {
 138                 if (dev_self[i])
 139                         w83977af_close(dev_self[i]);
 140         }
 141 }
 142
 143 /*
 144  * Function w83977af_open (iobase, irq)
 145  *
 146  *    Open driver instance
 147  *
 148  */
 149 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
 150                          unsigned int dma)
 151 {
 152         struct net_device *dev;
 153         struct w83977af_ir *self;
 154         int err;
 155
 156         IRDA_DEBUG(0, "%s()\n", __func__ );
 157
 158         /* Lock the port that we need */
 159         if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) {
 160                 IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
 161                       __func__ , iobase);
 162                 return -ENODEV;
 163         }
 164
 165         if (w83977af_probe(iobase, irq, dma) == -1) {
 166                 err = -1;
 167                 goto err_out;
 168         }
 169         /*
 170          *  Allocate new instance of the driver
 171          */
 172         dev = alloc_irdadev(sizeof(struct w83977af_ir));
 173         if (dev == NULL) {
 174                 printk( KERN_ERR "IrDA: Can't allocate memory for "
 175                         "IrDA control block!\n");
 176                 err = -ENOMEM;
 177                 goto err_out;
 178         }
 179
 180         self = netdev_priv(dev);
 181         spin_lock_init(&self->lock);
 182
 183
 184         /* Initialize IO */
 185         self->io.fir_base   = iobase;
 186         self->io.irq       = irq;
 187         self->io.fir_ext   = CHIP_IO_EXTENT;
 188         self->io.dma       = dma;
 189         self->io.fifo_size = 32;
 190
 191         /* Initialize QoS for this device */
 192         irda_init_max_qos_capabilies(&self->qos);
 193
 194         /* The only value we must override it the baudrate */
 195
 196         /* FIXME: The HP HDLS-1100 does not support 1152000! */
 197         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 198                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 199
 200         /* The HP HDLS-1100 needs 1 ms according to the specs */
 201         self->qos.min_turn_time.bits = qos_mtt_bits;
 202         irda_qos_bits_to_value(&self->qos);
 203
 204         /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 205         self->rx_buff.truesize = 14384;
 206         self->tx_buff.truesize = 4000;
 207
 208         /* Allocate memory if needed */
 209         self->rx_buff.head =
 210                 dma_alloc_coherent(NULL, self->rx_buff.truesize,
 211                                    &self->rx_buff_dma, GFP_KERNEL);
 212         if (self->rx_buff.head == NULL) {
 213                 err = -ENOMEM;
 214                 goto err_out1;
 215         }
 216
 217         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 218
 219         self->tx_buff.head =
 220                 dma_alloc_coherent(NULL, self->tx_buff.truesize,
 221                                    &self->tx_buff_dma, GFP_KERNEL);
 222         if (self->tx_buff.head == NULL) {
 223                 err = -ENOMEM;
 224                 goto err_out2;
 225         }
 226         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 227
 228         self->rx_buff.in_frame = FALSE;
 229         self->rx_buff.state = OUTSIDE_FRAME;
 230         self->tx_buff.data = self->tx_buff.head;
 231         self->rx_buff.data = self->rx_buff.head;
 232         self->netdev = dev;
 233
 234         /* Override the network functions we need to use */
 235         dev->hard_start_xmit = w83977af_hard_xmit;
 236         dev->open            = w83977af_net_open;
 237         dev->stop            = w83977af_net_close;
 238         dev->do_ioctl        = w83977af_net_ioctl;
 239
 240         err = register_netdev(dev);
 241         if (err) {
 242                 IRDA_ERROR("%s(), register_netdevice() failed!\n", __func__);
 243                 goto err_out3;
 244         }
 245         IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
 246
 247         /* Need to store self somewhere */
 248         dev_self[i] = self;
 249
 250         return 0;
 251 err_out3:
 252         dma_free_coherent(NULL, self->tx_buff.truesize,
 253                           self->tx_buff.head, self->tx_buff_dma);
 254 err_out2:
 255         dma_free_coherent(NULL, self->rx_buff.truesize,
 256                           self->rx_buff.head, self->rx_buff_dma);
 257 err_out1:
 258         free_netdev(dev);
 259 err_out:
 260         release_region(iobase, CHIP_IO_EXTENT);
 261         return err;
 262 }
 263
 264 /*
 265  * Function w83977af_close (self)
 266  *
 267  *    Close driver instance
 268  *
 269  */
 270 static int w83977af_close(struct w83977af_ir *self)
 271 {
 272         int iobase;
 273
 274         IRDA_DEBUG(0, "%s()\n", __func__ );
 275
 276         iobase = self->io.fir_base;
 277
 278 #ifdef CONFIG_USE_W977_PNP
 279         /* enter PnP configuration mode */
 280         w977_efm_enter(efio);
 281
 282         w977_select_device(W977_DEVICE_IR, efio);
 283
 284         /* Deactivate device */
 285         w977_write_reg(0x30, 0x00, efio);
 286
 287         w977_efm_exit(efio);
 288 #endif /* CONFIG_USE_W977_PNP */
 289
 290         /* Remove netdevice */
 291         unregister_netdev(self->netdev);
 292
 293         /* Release the PORT that this driver is using */
 294         IRDA_DEBUG(0 , "%s(), Releasing Region %03x\n",
 295               __func__ , self->io.fir_base);
 296         release_region(self->io.fir_base, self->io.fir_ext);
 297
 298         if (self->tx_buff.head)
 299                 dma_free_coherent(NULL, self->tx_buff.truesize,
 300                                   self->tx_buff.head, self->tx_buff_dma);
 301
 302         if (self->rx_buff.head)
 303                 dma_free_coherent(NULL, self->rx_buff.truesize,
 304                                   self->rx_buff.head, self->rx_buff_dma);
 305
 306         free_netdev(self->netdev);
 307
 308         return 0;
 309 }
 310
 311 static int w83977af_probe(int iobase, int irq, int dma)
 312 {
 313         int version;
 314         int i;
 315
 316         for (i=0; i < 2; i++) {
 317                 IRDA_DEBUG( 0, "%s()\n", __func__ );
 318 #ifdef CONFIG_USE_W977_PNP
 319                 /* Enter PnP configuration mode */
 320                 w977_efm_enter(efbase[i]);
 321
 322                 w977_select_device(W977_DEVICE_IR, efbase[i]);
 323
 324                 /* Configure PnP port, IRQ, and DMA channel */
 325                 w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
 326                 w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
 327
 328                 w977_write_reg(0x70, irq, efbase[i]);
 329 #ifdef CONFIG_ARCH_NETWINDER
 330                 /* Netwinder uses 1 higher than Linux */
 331                 w977_write_reg(0x74, dma+1, efbase[i]);
 332 #else
 333                 w977_write_reg(0x74, dma, efbase[i]);
 334 #endif /*CONFIG_ARCH_NETWINDER */
 335                 w977_write_reg(0x75, 0x04, efbase[i]);  /* Disable Tx DMA */
 336
 337                 /* Set append hardware CRC, enable IR bank selection */
 338                 w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]);
 339
 340                 /* Activate device */
 341                 w977_write_reg(0x30, 0x01, efbase[i]);
 342
 343                 w977_efm_exit(efbase[i]);
 344 #endif /* CONFIG_USE_W977_PNP */
 345                 /* Disable Advanced mode */
 346                 switch_bank(iobase, SET2);
 347                 outb(iobase+2, 0x00);
 348
 349                 /* Turn on UART (global) interrupts */
 350                 switch_bank(iobase, SET0);
 351                 outb(HCR_EN_IRQ, iobase+HCR);
 352
 353                 /* Switch to advanced mode */
 354                 switch_bank(iobase, SET2);
 355                 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
 356
 357                 /* Set default IR-mode */
 358                 switch_bank(iobase, SET0);
 359                 outb(HCR_SIR, iobase+HCR);
 360
 361                 /* Read the Advanced IR ID */
 362                 switch_bank(iobase, SET3);
 363                 version = inb(iobase+AUID);
 364
 365                 /* Should be 0x1? */
 366                 if (0x10 == (version & 0xf0)) {
 367                         efio = efbase[i];
 368
 369                         /* Set FIFO size to 32 */
 370                         switch_bank(iobase, SET2);
 371                         outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
 372
 373                         /* Set FIFO threshold to TX17, RX16 */
 374                         switch_bank(iobase, SET0);
 375                         outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
 376                              UFR_EN_FIFO,iobase+UFR);
 377
 378                         /* Receiver frame length */
 379                         switch_bank(iobase, SET4);
 380                         outb(2048 & 0xff, iobase+6);
 381                         outb((2048 >> 8) & 0x1f, iobase+7);
 382
 383                         /*
 384                          * Init HP HSDL-1100 transceiver.
 385                          *
 386                          * Set IRX_MSL since we have 2 * receive paths IRRX,
 387                          * and IRRXH. Clear IRSL0D since we want IRSL0 * to
 388                          * be a input pin used for IRRXH
 389                          *
 390                          *   IRRX  pin 37 connected to receiver
 391                          *   IRTX  pin 38 connected to transmitter
 392                          *   FIRRX pin 39 connected to receiver      (IRSL0)
 393                          *   CIRRX pin 40 connected to pin 37
 394                          */
 395                         switch_bank(iobase, SET7);
 396                         outb(0x40, iobase+7);
 397
 398                         IRDA_MESSAGE("W83977AF (IR) driver loaded. "
 399                                      "Version: 0x%02x\n", version);
 400
 401                         return 0;
 402                 } else {
 403                         /* Try next extented function register address */
 404                         IRDA_DEBUG( 0, "%s(), Wrong chip version", __func__ );
 405                 }
 406         }
 407         return -1;
 408 }
 409
 410 static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
 411 {
 412         int ir_mode = HCR_SIR;
 413         int iobase;
 414         __u8 set;
 415
 416         iobase = self->io.fir_base;
 417
 418         /* Update accounting for new speed */
 419         self->io.speed = speed;
 420
 421         /* Save current bank */
 422         set = inb(iobase+SSR);
 423
 424         /* Disable interrupts */
 425         switch_bank(iobase, SET0);
 426         outb(0, iobase+ICR);
 427
 428         /* Select Set 2 */
 429         switch_bank(iobase, SET2);
 430         outb(0x00, iobase+ABHL);
 431
 432         switch (speed) {
 433         case 9600:   outb(0x0c, iobase+ABLL); break;
 434         case 19200:  outb(0x06, iobase+ABLL); break;
 435         case 38400:  outb(0x03, iobase+ABLL); break;
 436         case 57600:  outb(0x02, iobase+ABLL); break;
 437         case 115200: outb(0x01, iobase+ABLL); break;
 438         case 576000:
 439                 ir_mode = HCR_MIR_576;
 440                 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__ );
 441                 break;
 442         case 1152000:
 443                 ir_mode = HCR_MIR_1152;
 444                 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __func__ );
 445                 break;
 446         case 4000000:
 447                 ir_mode = HCR_FIR;
 448                 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __func__ );
 449                 break;
 450         default:
 451                 ir_mode = HCR_FIR;
 452                 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n", __func__ , speed);
 453                 break;
 454         }
 455
 456         /* Set speed mode */
 457         switch_bank(iobase, SET0);
 458         outb(ir_mode, iobase+HCR);
 459
 460         /* set FIFO size to 32 */
 461         switch_bank(iobase, SET2);
 462         outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
 463
 464         /* set FIFO threshold to TX17, RX16 */
 465         switch_bank(iobase, SET0);
 466         outb(0x00, iobase+UFR);        /* Reset */
 467         outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */
 468         outb(0xa7, iobase+UFR);
 469
 470         netif_wake_queue(self->netdev);
 471
 472         /* Enable some interrupts so we can receive frames */
 473         switch_bank(iobase, SET0);
 474         if (speed > PIO_MAX_SPEED) {
 475                 outb(ICR_EFSFI, iobase+ICR);
 476                 w83977af_dma_receive(self);
 477         } else
 478                 outb(ICR_ERBRI, iobase+ICR);
 479
 480         /* Restore SSR */
 481         outb(set, iobase+SSR);
 482 }
 483
 484 /*
 485  * Function w83977af_hard_xmit (skb, dev)
 486  *
 487  *    Sets up a DMA transfer to send the current frame.
 488  *
 489  */
 490 static int w83977af_hard_xmit(struct sk_buff *skb, struct net_device *dev)
 491 {
 492         struct w83977af_ir *self;
 493         __s32 speed;
 494         int iobase;
 495         __u8 set;
 496         int mtt;
 497
 498         self = netdev_priv(dev);
 499
 500         iobase = self->io.fir_base;
 501
 502         IRDA_DEBUG(4, "%s(%ld), skb->len=%d\n", __func__ , jiffies,
 503                    (int) skb->len);
 504
 505         /* Lock transmit buffer */
 506         netif_stop_queue(dev);
 507
 508         /* Check if we need to change the speed */
 509         speed = irda_get_next_speed(skb);
 510         if ((speed != self->io.speed) && (speed != -1)) {
 511                 /* Check for empty frame */
 512                 if (!skb->len) {
 513                         w83977af_change_speed(self, speed);
 514                         dev->trans_start = jiffies;
 515                         dev_kfree_skb(skb);
 516                         return 0;
 517                 } else
 518                         self->new_speed = speed;
 519         }
 520
 521         /* Save current set */
 522         set = inb(iobase+SSR);
 523
 524         /* Decide if we should use PIO or DMA transfer */
 525         if (self->io.speed > PIO_MAX_SPEED) {
 526                 self->tx_buff.data = self->tx_buff.head;
 527                 skb_copy_from_linear_data(skb, self->tx_buff.data, skb->len);
 528                 self->tx_buff.len = skb->len;
 529
 530                 mtt = irda_get_mtt(skb);
 531 #ifdef CONFIG_USE_INTERNAL_TIMER
 532                 if (mtt > 50) {
 533                         /* Adjust for timer resolution */
 534                         mtt /= 1000+1;
 535
 536                         /* Setup timer */
 537                         switch_bank(iobase, SET4);
 538                         outb(mtt & 0xff, iobase+TMRL);
 539                         outb((mtt >> 8) & 0x0f, iobase+TMRH);
 540
 541                         /* Start timer */
 542                         outb(IR_MSL_EN_TMR, iobase+IR_MSL);
 543                         self->io.direction = IO_XMIT;
 544
 545                         /* Enable timer interrupt */
 546                         switch_bank(iobase, SET0);
 547                         outb(ICR_ETMRI, iobase+ICR);
 548                 } else {
 549 #endif
 550                         IRDA_DEBUG(4, "%s(%ld), mtt=%d\n", __func__ , jiffies, mtt);
 551                         if (mtt)
 552                                 udelay(mtt);
 553
 554                         /* Enable DMA interrupt */
 555                         switch_bank(iobase, SET0);
 556                         outb(ICR_EDMAI, iobase+ICR);
 557                         w83977af_dma_write(self, iobase);
 558 #ifdef CONFIG_USE_INTERNAL_TIMER
 559                 }
 560 #endif
 561         } else {
 562                 self->tx_buff.data = self->tx_buff.head;
 563                 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 564                                                    self->tx_buff.truesize);
 565
 566                 /* Add interrupt on tx low level (will fire immediately) */
 567                 switch_bank(iobase, SET0);
 568                 outb(ICR_ETXTHI, iobase+ICR);
 569         }
 570         dev->trans_start = jiffies;
 571         dev_kfree_skb(skb);
 572
 573         /* Restore set register */
 574         outb(set, iobase+SSR);
 575
 576         return 0;
 577 }
 578
 579 /*
 580  * Function w83977af_dma_write (self, iobase)
 581  *
 582  *    Send frame using DMA
 583  *
 584  */
 585 static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
 586 {
 587         __u8 set;
 588 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
 589         unsigned long flags;
 590         __u8 hcr;
 591 #endif
 592         IRDA_DEBUG(4, "%s(), len=%d\n", __func__ , self->tx_buff.len);
 593
 594         /* Save current set */
 595         set = inb(iobase+SSR);
 596
 597         /* Disable DMA */
 598         switch_bank(iobase, SET0);
 599         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 600
 601         /* Choose transmit DMA channel  */
 602         switch_bank(iobase, SET2);
 603         outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
 604 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
 605         spin_lock_irqsave(&self->lock, flags);
 606
 607         disable_dma(self->io.dma);
 608         clear_dma_ff(self->io.dma);
 609         set_dma_mode(self->io.dma, DMA_MODE_READ);
 610         set_dma_addr(self->io.dma, self->tx_buff_dma);
 611         set_dma_count(self->io.dma, self->tx_buff.len);
 612 #else
 613         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
 614                        DMA_MODE_WRITE);
 615 #endif
 616         self->io.direction = IO_XMIT;
 617
 618         /* Enable DMA */
 619         switch_bank(iobase, SET0);
 620 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
 621         hcr = inb(iobase+HCR);
 622         outb(hcr | HCR_EN_DMA, iobase+HCR);
 623         enable_dma(self->io.dma);
 624         spin_unlock_irqrestore(&self->lock, flags);
 625 #else
 626         outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
 627 #endif
 628
 629         /* Restore set register */
 630         outb(set, iobase+SSR);
 631 }
 632
 633 /*
 634  * Function w83977af_pio_write (iobase, buf, len, fifo_size)
 635  *
 636  *
 637  *
 638  */
 639 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
 640 {
 641         int actual = 0;
 642         __u8 set;
 643
 644         IRDA_DEBUG(4, "%s()\n", __func__ );
 645
 646         /* Save current bank */
 647         set = inb(iobase+SSR);
 648
 649         switch_bank(iobase, SET0);
 650         if (!(inb_p(iobase+USR) & USR_TSRE)) {
 651                 IRDA_DEBUG(4,
 652                            "%s(), warning, FIFO not empty yet!\n", __func__  );
 653
 654                 fifo_size -= 17;
 655                 IRDA_DEBUG(4, "%s(), %d bytes left in tx fifo\n",
 656                            __func__ , fifo_size);
 657         }
 658
 659         /* Fill FIFO with current frame */
 660         while ((fifo_size-- > 0) && (actual < len)) {
 661                 /* Transmit next byte */
 662                 outb(buf[actual++], iobase+TBR);
 663         }
 664
 665         IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
 666                    __func__ , fifo_size, actual, len);
 667
 668         /* Restore bank */
 669         outb(set, iobase+SSR);
 670
 671         return actual;
 672 }
 673
 674 /*
 675  * Function w83977af_dma_xmit_complete (self)
 676  *
 677  *    The transfer of a frame in finished. So do the necessary things
 678  *
 679  *
 680  */
 681 static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
 682 {
 683         int iobase;
 684         __u8 set;
 685
 686         IRDA_DEBUG(4, "%s(%ld)\n", __func__ , jiffies);
 687
 688         IRDA_ASSERT(self != NULL, return;);
 689
 690         iobase = self->io.fir_base;
 691
 692         /* Save current set */
 693         set = inb(iobase+SSR);
 694
 695         /* Disable DMA */
 696         switch_bank(iobase, SET0);
 697         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 698
 699         /* Check for underrrun! */
 700         if (inb(iobase+AUDR) & AUDR_UNDR) {
 701                 IRDA_DEBUG(0, "%s(), Transmit underrun!\n", __func__ );
 702
 703                 self->netdev->stats.tx_errors++;
 704                 self->netdev->stats.tx_fifo_errors++;
 705
 706                 /* Clear bit, by writing 1 to it */
 707                 outb(AUDR_UNDR, iobase+AUDR);
 708         } else
 709                 self->netdev->stats.tx_packets++;
 710
 711
 712         if (self->new_speed) {
 713                 w83977af_change_speed(self, self->new_speed);
 714                 self->new_speed = 0;
 715         }
 716
 717         /* Unlock tx_buff and request another frame */
 718         /* Tell the network layer, that we want more frames */
 719         netif_wake_queue(self->netdev);
 720
 721         /* Restore set */
 722         outb(set, iobase+SSR);
 723 }
 724
 725 /*
 726  * Function w83977af_dma_receive (self)
 727  *
 728  *    Get ready for receiving a frame. The device will initiate a DMA
 729  *    if it starts to receive a frame.
 730  *
 731  */
 732 static int w83977af_dma_receive(struct w83977af_ir *self)
 733 {
 734         int iobase;
 735         __u8 set;
 736 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
 737         unsigned long flags;
 738         __u8 hcr;
 739 #endif
 740         IRDA_ASSERT(self != NULL, return -1;);
 741
 742         IRDA_DEBUG(4, "%s\n", __func__ );
 743
 744         iobase= self->io.fir_base;
 745
 746         /* Save current set */
 747         set = inb(iobase+SSR);
 748
 749         /* Disable DMA */
 750         switch_bank(iobase, SET0);
 751         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 752
 753         /* Choose DMA Rx, DMA Fairness, and Advanced mode */
 754         switch_bank(iobase, SET2);
 755         outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL,
 756              iobase+ADCR1);
 757
 758         self->io.direction = IO_RECV;
 759         self->rx_buff.data = self->rx_buff.head;
 760
 761 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
 762         spin_lock_irqsave(&self->lock, flags);
 763
 764         disable_dma(self->io.dma);
 765         clear_dma_ff(self->io.dma);
 766         set_dma_mode(self->io.dma, DMA_MODE_READ);
 767         set_dma_addr(self->io.dma, self->rx_buff_dma);
 768         set_dma_count(self->io.dma, self->rx_buff.truesize);
 769 #else
 770         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
 771                        DMA_MODE_READ);
 772 #endif
 773         /*
 774          * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
 775          * important that we don't reset the Tx FIFO since it might not
 776          * be finished transmitting yet
 777          */
 778         switch_bank(iobase, SET0);
 779         outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
 780         self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0;
 781
 782         /* Enable DMA */
 783         switch_bank(iobase, SET0);
 784 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
 785         hcr = inb(iobase+HCR);
 786         outb(hcr | HCR_EN_DMA, iobase+HCR);
 787         enable_dma(self->io.dma);
 788         spin_unlock_irqrestore(&self->lock, flags);
 789 #else
 790         outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
 791 #endif
 792         /* Restore set */
 793         outb(set, iobase+SSR);
 794
 795         return 0;
 796 }
 797
 798 /*
 799  * Function w83977af_receive_complete (self)
 800  *
 801  *    Finished with receiving a frame
 802  *
 803  */
 804 static int w83977af_dma_receive_complete(struct w83977af_ir *self)
 805 {
 806         struct sk_buff *skb;
 807         struct st_fifo *st_fifo;
 808         int len;
 809         int iobase;
 810         __u8 set;
 811         __u8 status;
 812
 813         IRDA_DEBUG(4, "%s\n", __func__ );
 814
 815         st_fifo = &self->st_fifo;
 816
 817         iobase = self->io.fir_base;
 818
 819         /* Save current set */
 820         set = inb(iobase+SSR);
 821
 822         iobase = self->io.fir_base;
 823
 824         /* Read status FIFO */
 825         switch_bank(iobase, SET5);
 826         while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
 827                 st_fifo->entries[st_fifo->tail].status = status;
 828
 829                 st_fifo->entries[st_fifo->tail].len  = inb(iobase+RFLFL);
 830                 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
 831
 832                 st_fifo->tail++;
 833                 st_fifo->len++;
 834         }
 835
 836         while (st_fifo->len) {
 837                 /* Get first entry */
 838                 status = st_fifo->entries[st_fifo->head].status;
 839                 len    = st_fifo->entries[st_fifo->head].len;
 840                 st_fifo->head++;
 841                 st_fifo->len--;
 842
 843                 /* Check for errors */
 844                 if (status & FS_FO_ERR_MSK) {
 845                         if (status & FS_FO_LST_FR) {
 846                                 /* Add number of lost frames to stats */
 847                                 self->netdev->stats.rx_errors += len;
 848                         } else {
 849                                 /* Skip frame */
 850                                 self->netdev->stats.rx_errors++;
 851
 852                                 self->rx_buff.data += len;
 853
 854                                 if (status & FS_FO_MX_LEX)
 855                                         self->netdev->stats.rx_length_errors++;
 856
 857                                 if (status & FS_FO_PHY_ERR)
 858                                         self->netdev->stats.rx_frame_errors++;
 859
 860                                 if (status & FS_FO_CRC_ERR)
 861                                         self->netdev->stats.rx_crc_errors++;
 862                         }
 863                         /* The errors below can be reported in both cases */
 864                         if (status & FS_FO_RX_OV)
 865                                 self->netdev->stats.rx_fifo_errors++;
 866
 867                         if (status & FS_FO_FSF_OV)
 868                                 self->netdev->stats.rx_fifo_errors++;
 869
 870                 } else {
 871                         /* Check if we have transferred all data to memory */
 872                         switch_bank(iobase, SET0);
 873                         if (inb(iobase+USR) & USR_RDR) {
 874 #ifdef CONFIG_USE_INTERNAL_TIMER
 875                                 /* Put this entry back in fifo */
 876                                 st_fifo->head--;
 877                                 st_fifo->len++;
 878                                 st_fifo->entries[st_fifo->head].status = status;
 879                                 st_fifo->entries[st_fifo->head].len = len;
 880
 881                                 /* Restore set register */
 882                                 outb(set, iobase+SSR);
 883
 884                                 return FALSE;   /* I'll be back! */
 885 #else
 886                                 udelay(80); /* Should be enough!? */
 887 #endif
 888                         }
 889
 890                         skb = dev_alloc_skb(len+1);
 891                         if (skb == NULL)  {
 892                                 printk(KERN_INFO
 893                                        "%s(), memory squeeze, dropping frame.\n", __func__);
 894                                 /* Restore set register */
 895                                 outb(set, iobase+SSR);
 896
 897                                 return FALSE;
 898                         }
 899
 900                         /*  Align to 20 bytes */
 901                         skb_reserve(skb, 1);
 902
 903                         /* Copy frame without CRC */
 904                         if (self->io.speed < 4000000) {
 905                                 skb_put(skb, len-2);
 906                                 skb_copy_to_linear_data(skb,
 907                                                         self->rx_buff.data,
 908                                                         len - 2);
 909                         } else {
 910                                 skb_put(skb, len-4);
 911                                 skb_copy_to_linear_data(skb,
 912                                                         self->rx_buff.data,
 913                                                         len - 4);
 914                         }
 915
 916                         /* Move to next frame */
 917                         self->rx_buff.data += len;
 918                         self->netdev->stats.rx_packets++;
 919
 920                         skb->dev = self->netdev;
 921                         skb_reset_mac_header(skb);
 922                         skb->protocol = htons(ETH_P_IRDA);
 923                         netif_rx(skb);
 924                 }
 925         }
 926         /* Restore set register */
 927         outb(set, iobase+SSR);
 928
 929         return TRUE;
 930 }
 931
 932 /*
 933  * Function pc87108_pio_receive (self)
 934  *
 935  *    Receive all data in receiver FIFO
 936  *
 937  */
 938 static void w83977af_pio_receive(struct w83977af_ir *self)
 939 {
 940         __u8 byte = 0x00;
 941         int iobase;
 942
 943         IRDA_DEBUG(4, "%s()\n", __func__ );
 944
 945         IRDA_ASSERT(self != NULL, return;);
 946
 947         iobase = self->io.fir_base;
 948
 949         /*  Receive all characters in Rx FIFO */
 950         do {
 951                 byte = inb(iobase+RBR);
 952                 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
 953                                   byte);
 954         } while (inb(iobase+USR) & USR_RDR); /* Data available */
 955 }
 956
 957 /*
 958  * Function w83977af_sir_interrupt (self, eir)
 959  *
 960  *    Handle SIR interrupt
 961  *
 962  */
 963 static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
 964 {
 965         int actual;
 966         __u8 new_icr = 0;
 967         __u8 set;
 968         int iobase;
 969
 970         IRDA_DEBUG(4, "%s(), isr=%#x\n", __func__ , isr);
 971
 972         iobase = self->io.fir_base;
 973         /* Transmit FIFO low on data */
 974         if (isr & ISR_TXTH_I) {
 975                 /* Write data left in transmit buffer */
 976                 actual = w83977af_pio_write(self->io.fir_base,
 977                                             self->tx_buff.data,
 978                                             self->tx_buff.len,
 979                                             self->io.fifo_size);
 980
 981                 self->tx_buff.data += actual;
 982                 self->tx_buff.len  -= actual;
 983
 984                 self->io.direction = IO_XMIT;
 985
 986                 /* Check if finished */
 987                 if (self->tx_buff.len > 0) {
 988                         new_icr |= ICR_ETXTHI;
 989                 } else {
 990                         set = inb(iobase+SSR);
 991                         switch_bank(iobase, SET0);
 992                         outb(AUDR_SFEND, iobase+AUDR);
 993                         outb(set, iobase+SSR);
 994
 995                         self->netdev->stats.tx_packets++;
 996
 997                         /* Feed me more packets */
 998                         netif_wake_queue(self->netdev);
 999                         new_icr |= ICR_ETBREI;
1000                 }
1001         }
1002         /* Check if transmission has completed */
1003         if (isr & ISR_TXEMP_I) {
1004                 /* Check if we need to change the speed? */
1005                 if (self->new_speed) {
1006                         IRDA_DEBUG(2,
1007                                    "%s(), Changing speed!\n", __func__ );
1008                         w83977af_change_speed(self, self->new_speed);
1009                         self->new_speed = 0;
1010                 }
1011
1012                 /* Turn around and get ready to receive some data */
1013                 self->io.direction = IO_RECV;
1014                 new_icr |= ICR_ERBRI;
1015         }
1016
1017         /* Rx FIFO threshold or timeout */
1018         if (isr & ISR_RXTH_I) {
1019                 w83977af_pio_receive(self);
1020
1021                 /* Keep receiving */
1022                 new_icr |= ICR_ERBRI;
1023         }
1024         return new_icr;
1025 }
1026
1027 /*
1028  * Function pc87108_fir_interrupt (self, eir)
1029  *
1030  *    Handle MIR/FIR interrupt
1031  *
1032  */
1033 static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
1034 {
1035         __u8 new_icr = 0;
1036         __u8 set;
1037         int iobase;
1038
1039         iobase = self->io.fir_base;
1040         set = inb(iobase+SSR);
1041
1042         /* End of frame detected in FIFO */
1043         if (isr & (ISR_FEND_I|ISR_FSF_I)) {
1044                 if (w83977af_dma_receive_complete(self)) {
1045
1046                         /* Wait for next status FIFO interrupt */
1047                         new_icr |= ICR_EFSFI;
1048                 } else {
1049                         /* DMA not finished yet */
1050
1051                         /* Set timer value, resolution 1 ms */
1052                         switch_bank(iobase, SET4);
1053                         outb(0x01, iobase+TMRL); /* 1 ms */
1054                         outb(0x00, iobase+TMRH);
1055
1056                         /* Start timer */
1057                         outb(IR_MSL_EN_TMR, iobase+IR_MSL);
1058
1059                         new_icr |= ICR_ETMRI;
1060                 }
1061         }
1062         /* Timer finished */
1063         if (isr & ISR_TMR_I) {
1064                 /* Disable timer */
1065                 switch_bank(iobase, SET4);
1066                 outb(0, iobase+IR_MSL);
1067
1068                 /* Clear timer event */
1069                 /* switch_bank(iobase, SET0); */
1070 /*              outb(ASCR_CTE, iobase+ASCR); */
1071
1072                 /* Check if this is a TX timer interrupt */
1073                 if (self->io.direction == IO_XMIT) {
1074                         w83977af_dma_write(self, iobase);
1075
1076                         new_icr |= ICR_EDMAI;
1077                 } else {
1078                         /* Check if DMA has now finished */
1079                         w83977af_dma_receive_complete(self);
1080
1081                         new_icr |= ICR_EFSFI;
1082                 }
1083         }
1084         /* Finished with DMA */
1085         if (isr & ISR_DMA_I) {
1086                 w83977af_dma_xmit_complete(self);
1087
1088                 /* Check if there are more frames to be transmitted */
1089                 /* if (irda_device_txqueue_empty(self)) { */
1090
1091                 /* Prepare for receive
1092                  *
1093                  * ** Netwinder Tx DMA likes that we do this anyway **
1094                  */
1095                 w83977af_dma_receive(self);
1096                 new_icr = ICR_EFSFI;
1097                /* } */
1098         }
1099
1100         /* Restore set */
1101         outb(set, iobase+SSR);
1102
1103         return new_icr;
1104 }
1105
1106 /*
1107  * Function w83977af_interrupt (irq, dev_id, regs)
1108  *
1109  *    An interrupt from the chip has arrived. Time to do some work
1110  *
1111  */
1112 static irqreturn_t w83977af_interrupt(int irq, void *dev_id)
1113 {
1114         struct net_device *dev = dev_id;
1115         struct w83977af_ir *self;
1116         __u8 set, icr, isr;
1117         int iobase;
1118
1119         self = netdev_priv(dev);
1120
1121         iobase = self->io.fir_base;
1122
1123         /* Save current bank */
1124         set = inb(iobase+SSR);
1125         switch_bank(iobase, SET0);
1126
1127         icr = inb(iobase+ICR);
1128         isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
1129
1130         outb(0, iobase+ICR); /* Disable interrupts */
1131
1132         if (isr) {
1133                 /* Dispatch interrupt handler for the current speed */
1134                 if (self->io.speed > PIO_MAX_SPEED )
1135                         icr = w83977af_fir_interrupt(self, isr);
1136                 else
1137                         icr = w83977af_sir_interrupt(self, isr);
1138         }
1139
1140         outb(icr, iobase+ICR);    /* Restore (new) interrupts */
1141         outb(set, iobase+SSR);    /* Restore bank register */
1142         return IRQ_RETVAL(isr);
1143 }
1144
1145 /*
1146  * Function w83977af_is_receiving (self)
1147  *
1148  *    Return TRUE is we are currently receiving a frame
1149  *
1150  */
1151 static int w83977af_is_receiving(struct w83977af_ir *self)
1152 {
1153         int status = FALSE;
1154         int iobase;
1155         __u8 set;
1156
1157         IRDA_ASSERT(self != NULL, return FALSE;);
1158
1159         if (self->io.speed > 115200) {
1160                 iobase = self->io.fir_base;
1161
1162                 /* Check if rx FIFO is not empty */
1163                 set = inb(iobase+SSR);
1164                 switch_bank(iobase, SET2);
1165                 if ((inb(iobase+RXFDTH) & 0x3f) != 0) {
1166                         /* We are receiving something */
1167                         status =  TRUE;
1168                 }
1169                 outb(set, iobase+SSR);
1170         } else
1171                 status = (self->rx_buff.state != OUTSIDE_FRAME);
1172
1173         return status;
1174 }
1175
1176 /*
1177  * Function w83977af_net_open (dev)
1178  *
1179  *    Start the device
1180  *
1181  */
1182 static int w83977af_net_open(struct net_device *dev)
1183 {
1184         struct w83977af_ir *self;
1185         int iobase;
1186         char hwname[32];
1187         __u8 set;
1188
1189         IRDA_DEBUG(0, "%s()\n", __func__ );
1190
1191         IRDA_ASSERT(dev != NULL, return -1;);
1192         self = netdev_priv(dev);
1193
1194         IRDA_ASSERT(self != NULL, return 0;);
1195
1196         iobase = self->io.fir_base;
1197
1198         if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name,
1199                         (void *) dev)) {
1200                 return -EAGAIN;
1201         }
1202         /*
1203          * Always allocate the DMA channel after the IRQ,
1204          * and clean up on failure.
1205          */
1206         if (request_dma(self->io.dma, dev->name)) {
1207                 free_irq(self->io.irq, self);
1208                 return -EAGAIN;
1209         }
1210
1211         /* Save current set */
1212         set = inb(iobase+SSR);
1213
1214         /* Enable some interrupts so we can receive frames again */
1215         switch_bank(iobase, SET0);
1216         if (self->io.speed > 115200) {
1217                 outb(ICR_EFSFI, iobase+ICR);
1218                 w83977af_dma_receive(self);
1219         } else
1220                 outb(ICR_ERBRI, iobase+ICR);
1221
1222         /* Restore bank register */
1223         outb(set, iobase+SSR);
1224
1225         /* Ready to play! */
1226         netif_start_queue(dev);
1227
1228         /* Give self a hardware name */
1229         sprintf(hwname, "w83977af @ 0x%03x", self->io.fir_base);
1230
1231         /*
1232          * Open new IrLAP layer instance, now that everything should be
1233          * initialized properly
1234          */
1235         self->irlap = irlap_open(dev, &self->qos, hwname);
1236
1237         return 0;
1238 }
1239
1240 /*
1241  * Function w83977af_net_close (dev)
1242  *
1243  *    Stop the device
1244  *
1245  */
1246 static int w83977af_net_close(struct net_device *dev)
1247 {
1248         struct w83977af_ir *self;
1249         int iobase;
1250         __u8 set;
1251
1252         IRDA_DEBUG(0, "%s()\n", __func__ );
1253
1254         IRDA_ASSERT(dev != NULL, return -1;);
1255
1256         self = netdev_priv(dev);
1257
1258         IRDA_ASSERT(self != NULL, return 0;);
1259
1260         iobase = self->io.fir_base;
1261
1262         /* Stop device */
1263         netif_stop_queue(dev);
1264
1265         /* Stop and remove instance of IrLAP */
1266         if (self->irlap)
1267                 irlap_close(self->irlap);
1268         self->irlap = NULL;
1269
1270         disable_dma(self->io.dma);
1271
1272         /* Save current set */
1273         set = inb(iobase+SSR);
1274
1275         /* Disable interrupts */
1276         switch_bank(iobase, SET0);
1277         outb(0, iobase+ICR);
1278
1279         free_irq(self->io.irq, dev);
1280         free_dma(self->io.dma);
1281
1282         /* Restore bank register */
1283         outb(set, iobase+SSR);
1284
1285         return 0;
1286 }
1287
1288 /*
1289  * Function w83977af_net_ioctl (dev, rq, cmd)
1290  *
1291  *    Process IOCTL commands for this device
1292  *
1293  */
1294 static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1295 {
1296         struct if_irda_req *irq = (struct if_irda_req *) rq;
1297         struct w83977af_ir *self;
1298         unsigned long flags;
1299         int ret = 0;
1300
1301         IRDA_ASSERT(dev != NULL, return -1;);
1302
1303         self = netdev_priv(dev);
1304
1305         IRDA_ASSERT(self != NULL, return -1;);
1306
1307         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
1308
1309         spin_lock_irqsave(&self->lock, flags);
1310
1311         switch (cmd) {
1312         case SIOCSBANDWIDTH: /* Set bandwidth */
1313                 if (!capable(CAP_NET_ADMIN)) {
1314                         ret = -EPERM;
1315                         goto out;
1316                 }
1317                 w83977af_change_speed(self, irq->ifr_baudrate);
1318                 break;
1319         case SIOCSMEDIABUSY: /* Set media busy */
1320                 if (!capable(CAP_NET_ADMIN)) {
1321                         ret = -EPERM;
1322                         goto out;
1323                 }
1324                 irda_device_set_media_busy(self->netdev, TRUE);
1325                 break;
1326         case SIOCGRECEIVING: /* Check if we are receiving right now */
1327                 irq->ifr_receiving = w83977af_is_receiving(self);
1328                 break;
1329         default:
1330                 ret = -EOPNOTSUPP;
1331         }
1332 out:
1333         spin_unlock_irqrestore(&self->lock, flags);
1334         return ret;
1335 }
1336
1337 MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
1338 MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver");
1339 MODULE_LICENSE("GPL");
1340
1341
1342 module_param(qos_mtt_bits, int, 0);
1343 MODULE_PARM_DESC(qos_mtt_bits, "Mimimum Turn Time");
1344 module_param_array(io, int, NULL, 0);
1345 MODULE_PARM_DESC(io, "Base I/O addresses");
1346 module_param_array(irq, int, NULL, 0);
1347 MODULE_PARM_DESC(irq, "IRQ lines");
1348
1349 /*
1350  * Function init_module (void)
1351  *
1352  *
1353  *
1354  */
1355 module_init(w83977af_init);
1356
1357 /*
1358  * Function cleanup_module (void)
1359  *
1360  *
1361  *
1362  */
1363 module_exit(w83977af_cleanup);