SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/ipg.c

   1 /*
   2  * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
   3  *
   4  * Copyright (C) 2003, 2007  IC Plus Corp
   5  *
   6  * Original Author:
   7  *
   8  *   Craig Rich
   9  *   Sundance Technology, Inc.
  10  *   www.sundanceti.com
  11  *   craig_rich@sundanceti.com
  12  *
  13  * Current Maintainer:
  14  *
  15  *   Sorbica Shieh.
  16  *   http://www.icplus.com.tw
  17  *   sorbica@icplus.com.tw
  18  *
  19  *   Jesse Huang
  20  *   http://www.icplus.com.tw
  21  *   jesse@icplus.com.tw
  22  */
  23 #include <linux/crc32.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mii.h>
  26 #include <linux/mutex.h>
  27
  28 #include <asm/div64.h>
  29
  30 #define IPG_RX_RING_BYTES       (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
  31 #define IPG_TX_RING_BYTES       (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
  32 #define IPG_RESET_MASK \
  33         (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
  34          IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
  35          IPG_AC_AUTO_INIT)
  36
  37 #define ipg_w32(val32,reg)      iowrite32((val32), ioaddr + (reg))
  38 #define ipg_w16(val16,reg)      iowrite16((val16), ioaddr + (reg))
  39 #define ipg_w8(val8,reg)        iowrite8((val8), ioaddr + (reg))
  40
  41 #define ipg_r32(reg)            ioread32(ioaddr + (reg))
  42 #define ipg_r16(reg)            ioread16(ioaddr + (reg))
  43 #define ipg_r8(reg)             ioread8(ioaddr + (reg))
  44
  45 #define JUMBO_FRAME_4k_ONLY
  46 enum {
  47         netdev_io_size = 128
  48 };
  49
  50 #include "ipg.h"
  51 #define DRV_NAME        "ipg"
  52
  53 MODULE_AUTHOR("IC Plus Corp. 2003");
  54 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
  55 MODULE_LICENSE("GPL");
  56
  57 //variable record -- index by leading revision/length
  58 //Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
  59 static unsigned short DefaultPhyParam[] = {
  60         // 11/12/03 IP1000A v1-3 rev=0x40
  61         /*--------------------------------------------------------------------------
  62         (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
  63                                  27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
  64                                  31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7,  9, 0x0700,
  65           --------------------------------------------------------------------------*/
  66         // 12/17/03 IP1000A v1-4 rev=0x40
  67         (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  68             0x0000,
  69         30, 0x005e, 9, 0x0700,
  70         // 01/09/04 IP1000A v1-5 rev=0x41
  71         (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  72             0x0000,
  73         30, 0x005e, 9, 0x0700,
  74         0x0000
  75 };
  76
  77 static const char *ipg_brand_name[] = {
  78         "IC PLUS IP1000 1000/100/10 based NIC",
  79         "Sundance Technology ST2021 based NIC",
  80         "Tamarack Microelectronics TC9020/9021 based NIC",
  81         "Tamarack Microelectronics TC9020/9021 based NIC",
  82         "D-Link NIC",
  83         "D-Link NIC IP1000A"
  84 };
  85
  86 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
  87         { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
  88         { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
  89         { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
  90         { PCI_VDEVICE(DLINK,    0x9021), 3 },
  91         { PCI_VDEVICE(DLINK,    0x4000), 4 },
  92         { PCI_VDEVICE(DLINK,    0x4020), 5 },
  93         { 0, }
  94 };
  95
  96 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
  97
  98 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
  99 {
 100         struct ipg_nic_private *sp = netdev_priv(dev);
 101         return sp->ioaddr;
 102 }
 103
 104 #ifdef IPG_DEBUG
 105 static void ipg_dump_rfdlist(struct net_device *dev)
 106 {
 107         struct ipg_nic_private *sp = netdev_priv(dev);
 108         void __iomem *ioaddr = sp->ioaddr;
 109         unsigned int i;
 110         u32 offset;
 111
 112         IPG_DEBUG_MSG("_dump_rfdlist\n");
 113
 114         printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
 115         printk(KERN_INFO "rx_dirty   = %2.2x\n", sp->rx_dirty);
 116         printk(KERN_INFO "RFDList start address = %16.16lx\n",
 117                (unsigned long) sp->rxd_map);
 118         printk(KERN_INFO "RFDListPtr register   = %8.8x%8.8x\n",
 119                ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
 120
 121         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 122                 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
 123                 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
 124                        offset, (unsigned long) sp->rxd[i].next_desc);
 125                 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
 126                 printk(KERN_INFO "%2.2x %4.4x RFS        = %16.16lx\n", i,
 127                        offset, (unsigned long) sp->rxd[i].rfs);
 128                 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
 129                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 130                        offset, (unsigned long) sp->rxd[i].frag_info);
 131         }
 132 }
 133
 134 static void ipg_dump_tfdlist(struct net_device *dev)
 135 {
 136         struct ipg_nic_private *sp = netdev_priv(dev);
 137         void __iomem *ioaddr = sp->ioaddr;
 138         unsigned int i;
 139         u32 offset;
 140
 141         IPG_DEBUG_MSG("_dump_tfdlist\n");
 142
 143         printk(KERN_INFO "tx_current         = %2.2x\n", sp->tx_current);
 144         printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
 145         printk(KERN_INFO "TFDList start address = %16.16lx\n",
 146                (unsigned long) sp->txd_map);
 147         printk(KERN_INFO "TFDListPtr register   = %8.8x%8.8x\n",
 148                ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
 149
 150         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 151                 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
 152                 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
 153                        offset, (unsigned long) sp->txd[i].next_desc);
 154
 155                 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
 156                 printk(KERN_INFO "%2.2x %4.4x TFC        = %16.16lx\n", i,
 157                        offset, (unsigned long) sp->txd[i].tfc);
 158                 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
 159                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 160                        offset, (unsigned long) sp->txd[i].frag_info);
 161         }
 162 }
 163 #endif
 164
 165 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
 166 {
 167         ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
 168         ndelay(IPG_PC_PHYCTRLWAIT_NS);
 169 }
 170
 171 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
 172 {
 173         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
 174         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
 175 }
 176
 177 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
 178 {
 179         phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
 180
 181         ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
 182 }
 183
 184 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
 185 {
 186         ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
 187                 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
 188 }
 189
 190 static u16 read_phy_bit(void __iomem * ioaddr, u8 phyctrlpolarity)
 191 {
 192         u16 bit_data;
 193
 194         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
 195
 196         bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
 197
 198         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
 199
 200         return bit_data;
 201 }
 202
 203 /*
 204  * Read a register from the Physical Layer device located
 205  * on the IPG NIC, using the IPG PHYCTRL register.
 206  */
 207 static int mdio_read(struct net_device * dev, int phy_id, int phy_reg)
 208 {
 209         void __iomem *ioaddr = ipg_ioaddr(dev);
 210         /*
 211          * The GMII mangement frame structure for a read is as follows:
 212          *
 213          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 214          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 215          *
 216          * <32 1s> = 32 consecutive logic 1 values
 217          * A = bit of Physical Layer device address (MSB first)
 218          * R = bit of register address (MSB first)
 219          * z = High impedance state
 220          * D = bit of read data (MSB first)
 221          *
 222          * Transmission order is 'Preamble' field first, bits transmitted
 223          * left to right (first to last).
 224          */
 225         struct {
 226                 u32 field;
 227                 unsigned int len;
 228         } p[] = {
 229                 { GMII_PREAMBLE,        32 },   /* Preamble */
 230                 { GMII_ST,              2  },   /* ST */
 231                 { GMII_READ,            2  },   /* OP */
 232                 { phy_id,               5  },   /* PHYAD */
 233                 { phy_reg,              5  },   /* REGAD */
 234                 { 0x0000,               2  },   /* TA */
 235                 { 0x0000,               16 },   /* DATA */
 236                 { 0x0000,               1  }    /* IDLE */
 237         };
 238         unsigned int i, j;
 239         u8 polarity, data;
 240
 241         polarity  = ipg_r8(PHY_CTRL);
 242         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 243
 244         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 245         for (j = 0; j < 5; j++) {
 246                 for (i = 0; i < p[j].len; i++) {
 247                         /* For each variable length field, the MSB must be
 248                          * transmitted first. Rotate through the field bits,
 249                          * starting with the MSB, and move each bit into the
 250                          * the 1st (2^1) bit position (this is the bit position
 251                          * corresponding to the MgmtData bit of the PhyCtrl
 252                          * register for the IPG).
 253                          *
 254                          * Example: ST = 01;
 255                          *
 256                          *          First write a '0' to bit 1 of the PhyCtrl
 257                          *          register, then write a '1' to bit 1 of the
 258                          *          PhyCtrl register.
 259                          *
 260                          * To do this, right shift the MSB of ST by the value:
 261                          * [field length - 1 - #ST bits already written]
 262                          * then left shift this result by 1.
 263                          */
 264                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 265                         data &= IPG_PC_MGMTDATA;
 266                         data |= polarity | IPG_PC_MGMTDIR;
 267
 268                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 269                 }
 270         }
 271
 272         send_three_state(ioaddr, polarity);
 273
 274         read_phy_bit(ioaddr, polarity);
 275
 276         /*
 277          * For a read cycle, the bits for the next two fields (TA and
 278          * DATA) are driven by the PHY (the IPG reads these bits).
 279          */
 280         for (i = 0; i < p[6].len; i++) {
 281                 p[6].field |=
 282                     (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
 283         }
 284
 285         send_three_state(ioaddr, polarity);
 286         send_three_state(ioaddr, polarity);
 287         send_three_state(ioaddr, polarity);
 288         send_end(ioaddr, polarity);
 289
 290         /* Return the value of the DATA field. */
 291         return p[6].field;
 292 }
 293
 294 /*
 295  * Write to a register from the Physical Layer device located
 296  * on the IPG NIC, using the IPG PHYCTRL register.
 297  */
 298 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
 299 {
 300         void __iomem *ioaddr = ipg_ioaddr(dev);
 301         /*
 302          * The GMII mangement frame structure for a read is as follows:
 303          *
 304          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 305          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 306          *
 307          * <32 1s> = 32 consecutive logic 1 values
 308          * A = bit of Physical Layer device address (MSB first)
 309          * R = bit of register address (MSB first)
 310          * z = High impedance state
 311          * D = bit of write data (MSB first)
 312          *
 313          * Transmission order is 'Preamble' field first, bits transmitted
 314          * left to right (first to last).
 315          */
 316         struct {
 317                 u32 field;
 318                 unsigned int len;
 319         } p[] = {
 320                 { GMII_PREAMBLE,        32 },   /* Preamble */
 321                 { GMII_ST,              2  },   /* ST */
 322                 { GMII_WRITE,           2  },   /* OP */
 323                 { phy_id,               5  },   /* PHYAD */
 324                 { phy_reg,              5  },   /* REGAD */
 325                 { 0x0002,               2  },   /* TA */
 326                 { val & 0xffff,         16 },   /* DATA */
 327                 { 0x0000,               1  }    /* IDLE */
 328         };
 329         unsigned int i, j;
 330         u8 polarity, data;
 331
 332         polarity  = ipg_r8(PHY_CTRL);
 333         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 334
 335         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 336         for (j = 0; j < 7; j++) {
 337                 for (i = 0; i < p[j].len; i++) {
 338                         /* For each variable length field, the MSB must be
 339                          * transmitted first. Rotate through the field bits,
 340                          * starting with the MSB, and move each bit into the
 341                          * the 1st (2^1) bit position (this is the bit position
 342                          * corresponding to the MgmtData bit of the PhyCtrl
 343                          * register for the IPG).
 344                          *
 345                          * Example: ST = 01;
 346                          *
 347                          *          First write a '0' to bit 1 of the PhyCtrl
 348                          *          register, then write a '1' to bit 1 of the
 349                          *          PhyCtrl register.
 350                          *
 351                          * To do this, right shift the MSB of ST by the value:
 352                          * [field length - 1 - #ST bits already written]
 353                          * then left shift this result by 1.
 354                          */
 355                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 356                         data &= IPG_PC_MGMTDATA;
 357                         data |= polarity | IPG_PC_MGMTDIR;
 358
 359                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 360                 }
 361         }
 362
 363         /* The last cycle is a tri-state, so read from the PHY. */
 364         for (j = 7; j < 8; j++) {
 365                 for (i = 0; i < p[j].len; i++) {
 366                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
 367
 368                         p[j].field |= ((ipg_r8(PHY_CTRL) &
 369                                 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
 370
 371                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
 372                 }
 373         }
 374 }
 375
 376 /* Set LED_Mode JES20040127EEPROM */
 377 static void ipg_set_led_mode(struct net_device *dev)
 378 {
 379         struct ipg_nic_private *sp = netdev_priv(dev);
 380         void __iomem *ioaddr = sp->ioaddr;
 381         u32 mode;
 382
 383         mode = ipg_r32(ASIC_CTRL);
 384         mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
 385
 386         if ((sp->LED_Mode & 0x03) > 1)
 387                 mode |= IPG_AC_LED_MODE_BIT_1;  /* Write Asic Control Bit 29 */
 388
 389         if ((sp->LED_Mode & 0x01) == 1)
 390                 mode |= IPG_AC_LED_MODE;        /* Write Asic Control Bit 14 */
 391
 392         if ((sp->LED_Mode & 0x08) == 8)
 393                 mode |= IPG_AC_LED_SPEED;       /* Write Asic Control Bit 27 */
 394
 395         ipg_w32(mode, ASIC_CTRL);
 396 }
 397
 398 /* Set PHYSet JES20040127EEPROM */
 399 static void ipg_set_phy_set(struct net_device *dev)
 400 {
 401         struct ipg_nic_private *sp = netdev_priv(dev);
 402         void __iomem *ioaddr = sp->ioaddr;
 403         int physet;
 404
 405         physet = ipg_r8(PHY_SET);
 406         physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
 407         physet |= ((sp->LED_Mode & 0x70) >> 4);
 408         ipg_w8(physet, PHY_SET);
 409 }
 410
 411 static int ipg_reset(struct net_device *dev, u32 resetflags)
 412 {
 413         /* Assert functional resets via the IPG AsicCtrl
 414          * register as specified by the 'resetflags' input
 415          * parameter.
 416          */
 417         void __iomem *ioaddr = ipg_ioaddr(dev); //JES20040127EEPROM:
 418         unsigned int timeout_count = 0;
 419
 420         IPG_DEBUG_MSG("_reset\n");
 421
 422         ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
 423
 424         /* Delay added to account for problem with 10Mbps reset. */
 425         mdelay(IPG_AC_RESETWAIT);
 426
 427         while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
 428                 mdelay(IPG_AC_RESETWAIT);
 429                 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
 430                         return -ETIME;
 431         }
 432         /* Set LED Mode in Asic Control JES20040127EEPROM */
 433         ipg_set_led_mode(dev);
 434
 435         /* Set PHYSet Register Value JES20040127EEPROM */
 436         ipg_set_phy_set(dev);
 437         return 0;
 438 }
 439
 440 /* Find the GMII PHY address. */
 441 static int ipg_find_phyaddr(struct net_device *dev)
 442 {
 443         unsigned int phyaddr, i;
 444
 445         for (i = 0; i < 32; i++) {
 446                 u32 status;
 447
 448                 /* Search for the correct PHY address among 32 possible. */
 449                 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
 450
 451                 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
 452                    GMII_PHY_ID1
 453                  */
 454
 455                 status = mdio_read(dev, phyaddr, MII_BMSR);
 456
 457                 if ((status != 0xFFFF) && (status != 0))
 458                         return phyaddr;
 459         }
 460
 461         return 0x1f;
 462 }
 463
 464 /*
 465  * Configure IPG based on result of IEEE 802.3 PHY
 466  * auto-negotiation.
 467  */
 468 static int ipg_config_autoneg(struct net_device *dev)
 469 {
 470         struct ipg_nic_private *sp = netdev_priv(dev);
 471         void __iomem *ioaddr = sp->ioaddr;
 472         unsigned int txflowcontrol;
 473         unsigned int rxflowcontrol;
 474         unsigned int fullduplex;
 475         unsigned int gig;
 476         u32 mac_ctrl_val;
 477         u32 asicctrl;
 478         u8 phyctrl;
 479
 480         IPG_DEBUG_MSG("_config_autoneg\n");
 481
 482         asicctrl = ipg_r32(ASIC_CTRL);
 483         phyctrl = ipg_r8(PHY_CTRL);
 484         mac_ctrl_val = ipg_r32(MAC_CTRL);
 485
 486         /* Set flags for use in resolving auto-negotation, assuming
 487          * non-1000Mbps, half duplex, no flow control.
 488          */
 489         fullduplex = 0;
 490         txflowcontrol = 0;
 491         rxflowcontrol = 0;
 492         gig = 0;
 493
 494         /* To accomodate a problem in 10Mbps operation,
 495          * set a global flag if PHY running in 10Mbps mode.
 496          */
 497         sp->tenmbpsmode = 0;
 498
 499         printk(KERN_INFO "%s: Link speed = ", dev->name);
 500
 501         /* Determine actual speed of operation. */
 502         switch (phyctrl & IPG_PC_LINK_SPEED) {
 503         case IPG_PC_LINK_SPEED_10MBPS:
 504                 printk("10Mbps.\n");
 505                 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
 506                        dev->name);
 507                 sp->tenmbpsmode = 1;
 508                 break;
 509         case IPG_PC_LINK_SPEED_100MBPS:
 510                 printk("100Mbps.\n");
 511                 break;
 512         case IPG_PC_LINK_SPEED_1000MBPS:
 513                 printk("1000Mbps.\n");
 514                 gig = 1;
 515                 break;
 516         default:
 517                 printk("undefined!\n");
 518                 return 0;
 519         }
 520
 521         if (phyctrl & IPG_PC_DUPLEX_STATUS) {
 522                 fullduplex = 1;
 523                 txflowcontrol = 1;
 524                 rxflowcontrol = 1;
 525         }
 526
 527         /* Configure full duplex, and flow control. */
 528         if (fullduplex == 1) {
 529                 /* Configure IPG for full duplex operation. */
 530                 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
 531
 532                 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
 533
 534                 if (txflowcontrol == 1) {
 535                         printk("TX flow control");
 536                         mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
 537                 } else {
 538                         printk("no TX flow control");
 539                         mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
 540                 }
 541
 542                 if (rxflowcontrol == 1) {
 543                         printk(", RX flow control.");
 544                         mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
 545                 } else {
 546                         printk(", no RX flow control.");
 547                         mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 548                 }
 549
 550                 printk("\n");
 551         } else {
 552                 /* Configure IPG for half duplex operation. */
 553                 printk(KERN_INFO "%s: setting half duplex, "
 554                        "no TX flow control, no RX flow control.\n", dev->name);
 555
 556                 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
 557                         ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
 558                         ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 559         }
 560         ipg_w32(mac_ctrl_val, MAC_CTRL);
 561         return 0;
 562 }
 563
 564 /* Determine and configure multicast operation and set
 565  * receive mode for IPG.
 566  */
 567 static void ipg_nic_set_multicast_list(struct net_device *dev)
 568 {
 569         void __iomem *ioaddr = ipg_ioaddr(dev);
 570         struct dev_mc_list *mc_list_ptr;
 571         unsigned int hashindex;
 572         u32 hashtable[2];
 573         u8 receivemode;
 574
 575         IPG_DEBUG_MSG("_nic_set_multicast_list\n");
 576
 577         receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
 578
 579         if (dev->flags & IFF_PROMISC) {
 580                 /* NIC to be configured in promiscuous mode. */
 581                 receivemode = IPG_RM_RECEIVEALLFRAMES;
 582         } else if ((dev->flags & IFF_ALLMULTI) ||
 583                    (dev->flags & IFF_MULTICAST &
 584                     (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
 585                 /* NIC to be configured to receive all multicast
 586                  * frames. */
 587                 receivemode |= IPG_RM_RECEIVEMULTICAST;
 588         } else if (dev->flags & IFF_MULTICAST & (dev->mc_count > 0)) {
 589                 /* NIC to be configured to receive selected
 590                  * multicast addresses. */
 591                 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
 592         }
 593
 594         /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
 595          * The IPG applies a cyclic-redundancy-check (the same CRC
 596          * used to calculate the frame data FCS) to the destination
 597          * address all incoming multicast frames whose destination
 598          * address has the multicast bit set. The least significant
 599          * 6 bits of the CRC result are used as an addressing index
 600          * into the hash table. If the value of the bit addressed by
 601          * this index is a 1, the frame is passed to the host system.
 602          */
 603
 604         /* Clear hashtable. */
 605         hashtable[0] = 0x00000000;
 606         hashtable[1] = 0x00000000;
 607
 608         /* Cycle through all multicast addresses to filter. */
 609         for (mc_list_ptr = dev->mc_list;
 610              mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
 611                 /* Calculate CRC result for each multicast address. */
 612                 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
 613                                      ETH_ALEN);
 614
 615                 /* Use only the least significant 6 bits. */
 616                 hashindex = hashindex & 0x3F;
 617
 618                 /* Within "hashtable", set bit number "hashindex"
 619                  * to a logic 1.
 620                  */
 621                 set_bit(hashindex, (void *)hashtable);
 622         }
 623
 624         /* Write the value of the hashtable, to the 4, 16 bit
 625          * HASHTABLE IPG registers.
 626          */
 627         ipg_w32(hashtable[0], HASHTABLE_0);
 628         ipg_w32(hashtable[1], HASHTABLE_1);
 629
 630         ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
 631
 632         IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
 633 }
 634
 635 static int ipg_io_config(struct net_device *dev)
 636 {
 637         void __iomem *ioaddr = ipg_ioaddr(dev);
 638         u32 origmacctrl;
 639         u32 restoremacctrl;
 640
 641         IPG_DEBUG_MSG("_io_config\n");
 642
 643         origmacctrl = ipg_r32(MAC_CTRL);
 644
 645         restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
 646
 647         /* Based on compilation option, determine if FCS is to be
 648          * stripped on receive frames by IPG.
 649          */
 650         if (!IPG_STRIP_FCS_ON_RX)
 651                 restoremacctrl |= IPG_MC_RCV_FCS;
 652
 653         /* Determine if transmitter and/or receiver are
 654          * enabled so we may restore MACCTRL correctly.
 655          */
 656         if (origmacctrl & IPG_MC_TX_ENABLED)
 657                 restoremacctrl |= IPG_MC_TX_ENABLE;
 658
 659         if (origmacctrl & IPG_MC_RX_ENABLED)
 660                 restoremacctrl |= IPG_MC_RX_ENABLE;
 661
 662         /* Transmitter and receiver must be disabled before setting
 663          * IFSSelect.
 664          */
 665         ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
 666                 IPG_MC_RSVD_MASK, MAC_CTRL);
 667
 668         /* Now that transmitter and receiver are disabled, write
 669          * to IFSSelect.
 670          */
 671         ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
 672
 673         /* Set RECEIVEMODE register. */
 674         ipg_nic_set_multicast_list(dev);
 675
 676         ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
 677
 678         ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE,   RX_DMA_POLL_PERIOD);
 679         ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
 680         ipg_w8(IPG_RXDMABURSTTHRESH_VALUE,  RX_DMA_BURST_THRESH);
 681         ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE,   TX_DMA_POLL_PERIOD);
 682         ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
 683         ipg_w8(IPG_TXDMABURSTTHRESH_VALUE,  TX_DMA_BURST_THRESH);
 684         ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
 685                  IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
 686                  IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
 687                  IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
 688         ipg_w16(IPG_FLOWONTHRESH_VALUE,  FLOW_ON_THRESH);
 689         ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
 690
 691         /* IPG multi-frag frame bug workaround.
 692          * Per silicon revision B3 eratta.
 693          */
 694         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
 695
 696         /* IPG TX poll now bug workaround.
 697          * Per silicon revision B3 eratta.
 698          */
 699         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
 700
 701         /* IPG RX poll now bug workaround.
 702          * Per silicon revision B3 eratta.
 703          */
 704         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
 705
 706         /* Now restore MACCTRL to original setting. */
 707         ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
 708
 709         /* Disable unused RMON statistics. */
 710         ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
 711
 712         /* Disable unused MIB statistics. */
 713         ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
 714                 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
 715                 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
 716                 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
 717                 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
 718                 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
 719
 720         return 0;
 721 }
 722
 723 /*
 724  * Create a receive buffer within system memory and update
 725  * NIC private structure appropriately.
 726  */
 727 static int ipg_get_rxbuff(struct net_device *dev, int entry)
 728 {
 729         struct ipg_nic_private *sp = netdev_priv(dev);
 730         struct ipg_rx *rxfd = sp->rxd + entry;
 731         struct sk_buff *skb;
 732         u64 rxfragsize;
 733
 734         IPG_DEBUG_MSG("_get_rxbuff\n");
 735
 736         skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
 737         if (!skb) {
 738                 sp->RxBuff[entry] = NULL;
 739                 return -ENOMEM;
 740         }
 741
 742         /* Adjust the data start location within the buffer to
 743          * align IP address field to a 16 byte boundary.
 744          */
 745         skb_reserve(skb, NET_IP_ALIGN);
 746
 747         /* Associate the receive buffer with the IPG NIC. */
 748         skb->dev = dev;
 749
 750         /* Save the address of the sk_buff structure. */
 751         sp->RxBuff[entry] = skb;
 752
 753         rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
 754                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
 755
 756         /* Set the RFD fragment length. */
 757         rxfragsize = IPG_RXFRAG_SIZE;
 758         rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
 759
 760         return 0;
 761 }
 762
 763 static int init_rfdlist(struct net_device *dev)
 764 {
 765         struct ipg_nic_private *sp = netdev_priv(dev);
 766         void __iomem *ioaddr = sp->ioaddr;
 767         unsigned int i;
 768
 769         IPG_DEBUG_MSG("_init_rfdlist\n");
 770
 771         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 772                 struct ipg_rx *rxfd = sp->rxd + i;
 773
 774                 if (sp->RxBuff[i]) {
 775                         pci_unmap_single(sp->pdev,
 776                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
 777                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
 778                         dev_kfree_skb_irq(sp->RxBuff[i]);
 779                         sp->RxBuff[i] = NULL;
 780                 }
 781
 782                 /* Clear out the RFS field. */
 783                 rxfd->rfs = 0x0000000000000000;
 784
 785                 if (ipg_get_rxbuff(dev, i) < 0) {
 786                         /*
 787                          * A receive buffer was not ready, break the
 788                          * RFD list here.
 789                          */
 790                         IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
 791
 792                         /* Just in case we cannot allocate a single RFD.
 793                          * Should not occur.
 794                          */
 795                         if (i == 0) {
 796                                 printk(KERN_ERR "%s: No memory available"
 797                                         " for RFD list.\n", dev->name);
 798                                 return -ENOMEM;
 799                         }
 800                 }
 801
 802                 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
 803                         sizeof(struct ipg_rx)*(i + 1));
 804         }
 805         sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
 806
 807         sp->rx_current = 0;
 808         sp->rx_dirty = 0;
 809
 810         /* Write the location of the RFDList to the IPG. */
 811         ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
 812         ipg_w32(0x00000000, RFD_LIST_PTR_1);
 813
 814         return 0;
 815 }
 816
 817 static void init_tfdlist(struct net_device *dev)
 818 {
 819         struct ipg_nic_private *sp = netdev_priv(dev);
 820         void __iomem *ioaddr = sp->ioaddr;
 821         unsigned int i;
 822
 823         IPG_DEBUG_MSG("_init_tfdlist\n");
 824
 825         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 826                 struct ipg_tx *txfd = sp->txd + i;
 827
 828                 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
 829
 830                 if (sp->TxBuff[i]) {
 831                         dev_kfree_skb_irq(sp->TxBuff[i]);
 832                         sp->TxBuff[i] = NULL;
 833                 }
 834
 835                 txfd->next_desc = cpu_to_le64(sp->txd_map +
 836                         sizeof(struct ipg_tx)*(i + 1));
 837         }
 838         sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
 839
 840         sp->tx_current = 0;
 841         sp->tx_dirty = 0;
 842
 843         /* Write the location of the TFDList to the IPG. */
 844         IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
 845                        (u32) sp->txd_map);
 846         ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
 847         ipg_w32(0x00000000, TFD_LIST_PTR_1);
 848
 849         sp->ResetCurrentTFD = 1;
 850 }
 851
 852 /*
 853  * Free all transmit buffers which have already been transfered
 854  * via DMA to the IPG.
 855  */
 856 static void ipg_nic_txfree(struct net_device *dev)
 857 {
 858         struct ipg_nic_private *sp = netdev_priv(dev);
 859         unsigned int released, pending, dirty;
 860
 861         IPG_DEBUG_MSG("_nic_txfree\n");
 862
 863         pending = sp->tx_current - sp->tx_dirty;
 864         dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
 865
 866         for (released = 0; released < pending; released++) {
 867                 struct sk_buff *skb = sp->TxBuff[dirty];
 868                 struct ipg_tx *txfd = sp->txd + dirty;
 869
 870                 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
 871
 872                 /* Look at each TFD's TFC field beginning
 873                  * at the last freed TFD up to the current TFD.
 874                  * If the TFDDone bit is set, free the associated
 875                  * buffer.
 876                  */
 877                 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
 878                         break;
 879
 880                 /* Free the transmit buffer. */
 881                 if (skb) {
 882                         pci_unmap_single(sp->pdev,
 883                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
 884                                 skb->len, PCI_DMA_TODEVICE);
 885
 886                         dev_kfree_skb_irq(skb);
 887
 888                         sp->TxBuff[dirty] = NULL;
 889                 }
 890                 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
 891         }
 892
 893         sp->tx_dirty += released;
 894
 895         if (netif_queue_stopped(dev) &&
 896             (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
 897                 netif_wake_queue(dev);
 898         }
 899 }
 900
 901 static void ipg_tx_timeout(struct net_device *dev)
 902 {
 903         struct ipg_nic_private *sp = netdev_priv(dev);
 904         void __iomem *ioaddr = sp->ioaddr;
 905
 906         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
 907                   IPG_AC_FIFO);
 908
 909         spin_lock_irq(&sp->lock);
 910
 911         /* Re-configure after DMA reset. */
 912         if (ipg_io_config(dev) < 0) {
 913                 printk(KERN_INFO "%s: Error during re-configuration.\n",
 914                        dev->name);
 915         }
 916
 917         init_tfdlist(dev);
 918
 919         spin_unlock_irq(&sp->lock);
 920
 921         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
 922                 MAC_CTRL);
 923 }
 924
 925 /*
 926  * For TxComplete interrupts, free all transmit
 927  * buffers which have already been transfered via DMA
 928  * to the IPG.
 929  */
 930 static void ipg_nic_txcleanup(struct net_device *dev)
 931 {
 932         struct ipg_nic_private *sp = netdev_priv(dev);
 933         void __iomem *ioaddr = sp->ioaddr;
 934         unsigned int i;
 935
 936         IPG_DEBUG_MSG("_nic_txcleanup\n");
 937
 938         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 939                 /* Reading the TXSTATUS register clears the
 940                  * TX_COMPLETE interrupt.
 941                  */
 942                 u32 txstatusdword = ipg_r32(TX_STATUS);
 943
 944                 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
 945
 946                 /* Check for Transmit errors. Error bits only valid if
 947                  * TX_COMPLETE bit in the TXSTATUS register is a 1.
 948                  */
 949                 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
 950                         break;
 951
 952                 /* If in 10Mbps mode, indicate transmit is ready. */
 953                 if (sp->tenmbpsmode) {
 954                         netif_wake_queue(dev);
 955                 }
 956
 957                 /* Transmit error, increment stat counters. */
 958                 if (txstatusdword & IPG_TS_TX_ERROR) {
 959                         IPG_DEBUG_MSG("Transmit error.\n");
 960                         sp->stats.tx_errors++;
 961                 }
 962
 963                 /* Late collision, re-enable transmitter. */
 964                 if (txstatusdword & IPG_TS_LATE_COLLISION) {
 965                         IPG_DEBUG_MSG("Late collision on transmit.\n");
 966                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 967                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 968                 }
 969
 970                 /* Maximum collisions, re-enable transmitter. */
 971                 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
 972                         IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
 973                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 974                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 975                 }
 976
 977                 /* Transmit underrun, reset and re-enable
 978                  * transmitter.
 979                  */
 980                 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
 981                         IPG_DEBUG_MSG("Transmitter underrun.\n");
 982                         sp->stats.tx_fifo_errors++;
 983                         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
 984                                   IPG_AC_NETWORK | IPG_AC_FIFO);
 985
 986                         /* Re-configure after DMA reset. */
 987                         if (ipg_io_config(dev) < 0) {
 988                                 printk(KERN_INFO
 989                                        "%s: Error during re-configuration.\n",
 990                                        dev->name);
 991                         }
 992                         init_tfdlist(dev);
 993
 994                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 995                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 996                 }
 997         }
 998
 999         ipg_nic_txfree(dev);
1000 }
1001
1002 /* Provides statistical information about the IPG NIC. */
1003 static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1004 {
1005         struct ipg_nic_private *sp = netdev_priv(dev);
1006         void __iomem *ioaddr = sp->ioaddr;
1007         u16 temp1;
1008         u16 temp2;
1009
1010         IPG_DEBUG_MSG("_nic_get_stats\n");
1011
1012         /* Check to see if the NIC has been initialized via nic_open,
1013          * before trying to read statistic registers.
1014          */
1015         if (!test_bit(__LINK_STATE_START, &dev->state))
1016                 return &sp->stats;
1017
1018         sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1019         sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1020         sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1021         sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1022         temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1023         sp->stats.rx_errors += temp1;
1024         sp->stats.rx_missed_errors += temp1;
1025         temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1026                 ipg_r32(IPG_LATECOLLISIONS);
1027         temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1028         sp->stats.collisions += temp1;
1029         sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1030         sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1031                 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1032         sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1033
1034         /* detailed tx_errors */
1035         sp->stats.tx_carrier_errors += temp2;
1036
1037         /* detailed rx_errors */
1038         sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1039                 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1040         sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1041
1042         /* Unutilized IPG statistic registers. */
1043         ipg_r32(IPG_MCSTFRAMESRCVDOK);
1044
1045         return &sp->stats;
1046 }
1047
1048 /* Restore used receive buffers. */
1049 static int ipg_nic_rxrestore(struct net_device *dev)
1050 {
1051         struct ipg_nic_private *sp = netdev_priv(dev);
1052         const unsigned int curr = sp->rx_current;
1053         unsigned int dirty = sp->rx_dirty;
1054
1055         IPG_DEBUG_MSG("_nic_rxrestore\n");
1056
1057         for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1058                 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1059
1060                 /* rx_copybreak may poke hole here and there. */
1061                 if (sp->RxBuff[entry])
1062                         continue;
1063
1064                 /* Generate a new receive buffer to replace the
1065                  * current buffer (which will be released by the
1066                  * Linux system).
1067                  */
1068                 if (ipg_get_rxbuff(dev, entry) < 0) {
1069                         IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1070
1071                         break;
1072                 }
1073
1074                 /* Reset the RFS field. */
1075                 sp->rxd[entry].rfs = 0x0000000000000000;
1076         }
1077         sp->rx_dirty = dirty;
1078
1079         return 0;
1080 }
1081
1082 #ifdef JUMBO_FRAME
1083
1084 /* use jumboindex and jumbosize to control jumbo frame status
1085    initial status is jumboindex=-1 and jumbosize=0
1086    1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1087    2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1088    3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1089                 previous receiving and need to continue dumping the current one
1090 */
1091 enum {
1092         NormalPacket,
1093         ErrorPacket
1094 };
1095
1096 enum {
1097         Frame_NoStart_NoEnd     = 0,
1098         Frame_WithStart         = 1,
1099         Frame_WithEnd           = 10,
1100         Frame_WithStart_WithEnd = 11
1101 };
1102
1103 inline void ipg_nic_rx_free_skb(struct net_device *dev)
1104 {
1105         struct ipg_nic_private *sp = netdev_priv(dev);
1106         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1107
1108         if (sp->RxBuff[entry]) {
1109                 struct ipg_rx *rxfd = sp->rxd + entry;
1110
1111                 pci_unmap_single(sp->pdev,
1112                         le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1113                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1114                 dev_kfree_skb_irq(sp->RxBuff[entry]);
1115                 sp->RxBuff[entry] = NULL;
1116         }
1117 }
1118
1119 inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1120 {
1121         struct ipg_nic_private *sp = netdev_priv(dev);
1122         struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1123         int type = Frame_NoStart_NoEnd;
1124
1125         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1126                 type += Frame_WithStart;
1127         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1128                 type += Frame_WithEnd;
1129         return type;
1130 }
1131
1132 inline int ipg_nic_rx_check_error(struct net_device *dev)
1133 {
1134         struct ipg_nic_private *sp = netdev_priv(dev);
1135         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1136         struct ipg_rx *rxfd = sp->rxd + entry;
1137
1138         if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1139              (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1140               IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1141               IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1142                 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1143                               (unsigned long) rxfd->rfs);
1144
1145                 /* Increment general receive error statistic. */
1146                 sp->stats.rx_errors++;
1147
1148                 /* Increment detailed receive error statistics. */
1149                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1150                         IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1151
1152                         sp->stats.rx_fifo_errors++;
1153                 }
1154
1155                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1156                         IPG_DEBUG_MSG("RX runt occured.\n");
1157                         sp->stats.rx_length_errors++;
1158                 }
1159
1160                 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1161                  * error count handled by a IPG statistic register.
1162                  */
1163
1164                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1165                         IPG_DEBUG_MSG("RX alignment error occured.\n");
1166                         sp->stats.rx_frame_errors++;
1167                 }
1168
1169                 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1170                  * handled by a IPG statistic register.
1171                  */
1172
1173                 /* Free the memory associated with the RX
1174                  * buffer since it is erroneous and we will
1175                  * not pass it to higher layer processes.
1176                  */
1177                 if (sp->RxBuff[entry]) {
1178                         pci_unmap_single(sp->pdev,
1179                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1180                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1181
1182                         dev_kfree_skb_irq(sp->RxBuff[entry]);
1183                         sp->RxBuff[entry] = NULL;
1184                 }
1185                 return ErrorPacket;
1186         }
1187         return NormalPacket;
1188 }
1189
1190 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1191                                           struct ipg_nic_private *sp,
1192                                           struct ipg_rx *rxfd, unsigned entry)
1193 {
1194         struct SJumbo *jumbo = &sp->Jumbo;
1195         struct sk_buff *skb;
1196         int framelen;
1197
1198         if (jumbo->FoundStart) {
1199                 dev_kfree_skb_irq(jumbo->skb);
1200                 jumbo->FoundStart = 0;
1201                 jumbo->CurrentSize = 0;
1202                 jumbo->skb = NULL;
1203         }
1204
1205         // 1: found error, 0 no error
1206         if (ipg_nic_rx_check_error(dev) != NormalPacket)
1207                 return;
1208
1209         skb = sp->RxBuff[entry];
1210         if (!skb)
1211                 return;
1212
1213         // accept this frame and send to upper layer
1214         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1215         if (framelen > IPG_RXFRAG_SIZE)
1216                 framelen = IPG_RXFRAG_SIZE;
1217
1218         skb_put(skb, framelen);
1219         skb->protocol = eth_type_trans(skb, dev);
1220         skb->ip_summed = CHECKSUM_NONE;
1221         netif_rx(skb);
1222         dev->last_rx = jiffies;
1223         sp->RxBuff[entry] = NULL;
1224 }
1225
1226 static void ipg_nic_rx_with_start(struct net_device *dev,
1227                                   struct ipg_nic_private *sp,
1228                                   struct ipg_rx *rxfd, unsigned entry)
1229 {
1230         struct SJumbo *jumbo = &sp->Jumbo;
1231         struct pci_dev *pdev = sp->pdev;
1232         struct sk_buff *skb;
1233
1234         // 1: found error, 0 no error
1235         if (ipg_nic_rx_check_error(dev) != NormalPacket)
1236                 return;
1237
1238         // accept this frame and send to upper layer
1239         skb = sp->RxBuff[entry];
1240         if (!skb)
1241                 return;
1242
1243         if (jumbo->FoundStart)
1244                 dev_kfree_skb_irq(jumbo->skb);
1245
1246         pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1247                          sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1248
1249         skb_put(skb, IPG_RXFRAG_SIZE);
1250
1251         jumbo->FoundStart = 1;
1252         jumbo->CurrentSize = IPG_RXFRAG_SIZE;
1253         jumbo->skb = skb;
1254
1255         sp->RxBuff[entry] = NULL;
1256         dev->last_rx = jiffies;
1257 }
1258
1259 static void ipg_nic_rx_with_end(struct net_device *dev,
1260                                 struct ipg_nic_private *sp,
1261                                 struct ipg_rx *rxfd, unsigned entry)
1262 {
1263         struct SJumbo *jumbo = &sp->Jumbo;
1264
1265         //1: found error, 0 no error
1266         if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1267                 struct sk_buff *skb = sp->RxBuff[entry];
1268
1269                 if (!skb)
1270                         return;
1271
1272                 if (jumbo->FoundStart) {
1273                         int framelen, endframelen;
1274
1275                         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1276
1277                         endframeLen = framelen - jumbo->CurrentSize;
1278                         /*
1279                         if (framelen > IPG_RXFRAG_SIZE)
1280                                 framelen=IPG_RXFRAG_SIZE;
1281                          */
1282                         if (framelen > IPG_RXSUPPORT_SIZE)
1283                                 dev_kfree_skb_irq(jumbo->skb);
1284                         else {
1285                                 memcpy(skb_put(jumbo->skb, endframeLen),
1286                                        skb->data, endframeLen);
1287
1288                                 jumbo->skb->protocol =
1289                                     eth_type_trans(jumbo->skb, dev);
1290
1291                                 jumbo->skb->ip_summed = CHECKSUM_NONE;
1292                                 netif_rx(jumbo->skb);
1293                         }
1294                 }
1295
1296                 dev->last_rx = jiffies;
1297                 jumbo->FoundStart = 0;
1298                 jumbo->CurrentSize = 0;
1299                 jumbo->skb = NULL;
1300
1301                 ipg_nic_rx_free_skb(dev);
1302         } else {
1303                 dev_kfree_skb_irq(jumbo->skb);
1304                 jumbo->FoundStart = 0;
1305                 jumbo->CurrentSize = 0;
1306                 jumbo->skb = NULL;
1307         }
1308 }
1309
1310 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1311                                        struct ipg_nic_private *sp,
1312                                        struct ipg_rx *rxfd, unsigned entry)
1313 {
1314         struct SJumbo *jumbo = &sp->Jumbo;
1315
1316         //1: found error, 0 no error
1317         if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1318                 struct sk_buff *skb = sp->RxBuff[entry];
1319
1320                 if (skb) {
1321                         if (jumbo->FoundStart) {
1322                                 jumbo->CurrentSize += IPG_RXFRAG_SIZE;
1323                                 if (jumbo->CurrentSize <= IPG_RXSUPPORT_SIZE) {
1324                                         memcpy(skb_put(jumbo->skb,
1325                                                        IPG_RXFRAG_SIZE),
1326                                                skb->data, IPG_RXFRAG_SIZE);
1327                                 }
1328                         }
1329                         dev->last_rx = jiffies;
1330                         ipg_nic_rx_free_skb(dev);
1331                 }
1332         } else {
1333                 dev_kfree_skb_irq(jumbo->skb);
1334                 jumbo->FoundStart = 0;
1335                 jumbo->CurrentSize = 0;
1336                 jumbo->skb = NULL;
1337         }
1338 }
1339
1340 static int ipg_nic_rx(struct net_device *dev)
1341 {
1342         struct ipg_nic_private *sp = netdev_priv(dev);
1343         unsigned int curr = sp->rx_current;
1344         void __iomem *ioaddr = sp->ioaddr;
1345         unsigned int i;
1346
1347         IPG_DEBUG_MSG("_nic_rx\n");
1348
1349         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1350                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1351                 struct ipg_rx *rxfd = sp->rxd + entry;
1352
1353                 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1354                         break;
1355
1356                 switch (ipg_nic_rx_check_frame_type(dev)) {
1357                 case Frame_WithStart_WithEnd:
1358                         ipg_nic_rx_with_start_and_end(dev, tp, rxfd, entry);
1359                         break;
1360                 case Frame_WithStart:
1361                         ipg_nic_rx_with_start(dev, tp, rxfd, entry);
1362                         break;
1363                 case Frame_WithEnd:
1364                         ipg_nic_rx_with_end(dev, tp, rxfd, entry);
1365                         break;
1366                 case Frame_NoStart_NoEnd:
1367                         ipg_nic_rx_no_start_no_end(dev, tp, rxfd, entry);
1368                         break;
1369                 }
1370         }
1371
1372         sp->rx_current = curr;
1373
1374         if (i == IPG_MAXRFDPROCESS_COUNT) {
1375                 /* There are more RFDs to process, however the
1376                  * allocated amount of RFD processing time has
1377                  * expired. Assert Interrupt Requested to make
1378                  * sure we come back to process the remaining RFDs.
1379                  */
1380                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1381         }
1382
1383         ipg_nic_rxrestore(dev);
1384
1385         return 0;
1386 }
1387
1388 #else
1389 static int ipg_nic_rx(struct net_device *dev)
1390 {
1391         /* Transfer received Ethernet frames to higher network layers. */
1392         struct ipg_nic_private *sp = netdev_priv(dev);
1393         unsigned int curr = sp->rx_current;
1394         void __iomem *ioaddr = sp->ioaddr;
1395         struct ipg_rx *rxfd;
1396         unsigned int i;
1397
1398         IPG_DEBUG_MSG("_nic_rx\n");
1399
1400 #define __RFS_MASK \
1401         cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1402
1403         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1404                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1405                 struct sk_buff *skb = sp->RxBuff[entry];
1406                 unsigned int framelen;
1407
1408                 rxfd = sp->rxd + entry;
1409
1410                 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1411                         break;
1412
1413                 /* Get received frame length. */
1414                 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1415
1416                 /* Check for jumbo frame arrival with too small
1417                  * RXFRAG_SIZE.
1418                  */
1419                 if (framelen > IPG_RXFRAG_SIZE) {
1420                         IPG_DEBUG_MSG
1421                             ("RFS FrameLen > allocated fragment size.\n");
1422
1423                         framelen = IPG_RXFRAG_SIZE;
1424                 }
1425
1426                 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1427                        (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1428                         IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1429                         IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1430
1431                         IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1432                                       (unsigned long int) rxfd->rfs);
1433
1434                         /* Increment general receive error statistic. */
1435                         sp->stats.rx_errors++;
1436
1437                         /* Increment detailed receive error statistics. */
1438                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1439                                 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1440                                 sp->stats.rx_fifo_errors++;
1441                         }
1442
1443                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1444                                 IPG_DEBUG_MSG("RX runt occured.\n");
1445                                 sp->stats.rx_length_errors++;
1446                         }
1447
1448                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1449                         /* Do nothing, error count handled by a IPG
1450                          * statistic register.
1451                          */
1452
1453                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1454                                 IPG_DEBUG_MSG("RX alignment error occured.\n");
1455                                 sp->stats.rx_frame_errors++;
1456                         }
1457
1458                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1459                         /* Do nothing, error count handled by a IPG
1460                          * statistic register.
1461                          */
1462
1463                         /* Free the memory associated with the RX
1464                          * buffer since it is erroneous and we will
1465                          * not pass it to higher layer processes.
1466                          */
1467                         if (skb) {
1468                                 __le64 info = rxfd->frag_info;
1469
1470                                 pci_unmap_single(sp->pdev,
1471                                         le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1472                                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1473
1474                                 dev_kfree_skb_irq(skb);
1475                         }
1476                 } else {
1477
1478                         /* Adjust the new buffer length to accomodate the size
1479                          * of the received frame.
1480                          */
1481                         skb_put(skb, framelen);
1482
1483                         /* Set the buffer's protocol field to Ethernet. */
1484                         skb->protocol = eth_type_trans(skb, dev);
1485
1486                         /* If the frame contains an IP/TCP/UDP frame,
1487                          * determine if upper layer must check IP/TCP/UDP
1488                          * checksums.
1489                          *
1490                          * NOTE: DO NOT RELY ON THE TCP/UDP CHECKSUM
1491                          *       VERIFICATION FOR SILICON REVISIONS B3
1492                          *       AND EARLIER!
1493                          *
1494                          if ((le64_to_cpu(rxfd->rfs &
1495                              (IPG_RFS_TCPDETECTED | IPG_RFS_UDPDETECTED |
1496                               IPG_RFS_IPDETECTED))) &&
1497                             !(le64_to_cpu(rxfd->rfs &
1498                               (IPG_RFS_TCPERROR | IPG_RFS_UDPERROR |
1499                                IPG_RFS_IPERROR)))) {
1500                                  * Indicate IP checksums were performed
1501                                  * by the IPG.
1502                                  *
1503                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1504                          } else
1505                          */
1506                          {
1507                                 /* The IPG encountered an error with (or
1508                                  * there were no) IP/TCP/UDP checksums.
1509                                  * This may or may not indicate an invalid
1510                                  * IP/TCP/UDP frame was received. Let the
1511                                  * upper layer decide.
1512                                  */
1513                                 skb->ip_summed = CHECKSUM_NONE;
1514                         }
1515
1516                         /* Hand off frame for higher layer processing.
1517                          * The function netif_rx() releases the sk_buff
1518                          * when processing completes.
1519                          */
1520                         netif_rx(skb);
1521
1522                         /* Record frame receive time (jiffies = Linux
1523                          * kernel current time stamp).
1524                          */
1525                         dev->last_rx = jiffies;
1526                 }
1527
1528                 /* Assure RX buffer is not reused by IPG. */
1529                 sp->RxBuff[entry] = NULL;
1530         }
1531
1532         /*
1533          * If there are more RFDs to proces and the allocated amount of RFD
1534          * processing time has expired, assert Interrupt Requested to make
1535          * sure we come back to process the remaining RFDs.
1536          */
1537         if (i == IPG_MAXRFDPROCESS_COUNT)
1538                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1539
1540 #ifdef IPG_DEBUG
1541         /* Check if the RFD list contained no receive frame data. */
1542         if (!i)
1543                 sp->EmptyRFDListCount++;
1544 #endif
1545         while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1546                !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1547                  (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1548                 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1549
1550                 rxfd = sp->rxd + entry;
1551
1552                 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1553
1554                 /* An unexpected event, additional code needed to handle
1555                  * properly. So for the time being, just disregard the
1556                  * frame.
1557                  */
1558
1559                 /* Free the memory associated with the RX
1560                  * buffer since it is erroneous and we will
1561                  * not pass it to higher layer processes.
1562                  */
1563                 if (sp->RxBuff[entry]) {
1564                         pci_unmap_single(sp->pdev,
1565                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1566                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1567                         dev_kfree_skb_irq(sp->RxBuff[entry]);
1568                 }
1569
1570                 /* Assure RX buffer is not reused by IPG. */
1571                 sp->RxBuff[entry] = NULL;
1572         }
1573
1574         sp->rx_current = curr;
1575
1576         /* Check to see if there are a minimum number of used
1577          * RFDs before restoring any (should improve performance.)
1578          */
1579         if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1580                 ipg_nic_rxrestore(dev);
1581
1582         return 0;
1583 }
1584 #endif
1585
1586 static void ipg_reset_after_host_error(struct work_struct *work)
1587 {
1588         struct ipg_nic_private *sp =
1589                 container_of(work, struct ipg_nic_private, task.work);
1590         struct net_device *dev = sp->dev;
1591
1592         IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1593
1594         /*
1595          * Acknowledge HostError interrupt by resetting
1596          * IPG DMA and HOST.
1597          */
1598         ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1599
1600         init_rfdlist(dev);
1601         init_tfdlist(dev);
1602
1603         if (ipg_io_config(dev) < 0) {
1604                 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1605                        dev->name);
1606                 schedule_delayed_work(&sp->task, HZ);
1607         }
1608 }
1609
1610 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1611 {
1612         struct net_device *dev = dev_inst;
1613         struct ipg_nic_private *sp = netdev_priv(dev);
1614         void __iomem *ioaddr = sp->ioaddr;
1615         unsigned int handled = 0;
1616         u16 status;
1617
1618         IPG_DEBUG_MSG("_interrupt_handler\n");
1619
1620 #ifdef JUMBO_FRAME
1621         ipg_nic_rxrestore(dev);
1622 #endif
1623         spin_lock(&sp->lock);
1624
1625         /* Get interrupt source information, and acknowledge
1626          * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1627          * IntRequested, MacControlFrame, LinkEvent) interrupts
1628          * if issued. Also, all IPG interrupts are disabled by
1629          * reading IntStatusAck.
1630          */
1631         status = ipg_r16(INT_STATUS_ACK);
1632
1633         IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1634
1635         /* Shared IRQ of remove event. */
1636         if (!(status & IPG_IS_RSVD_MASK))
1637                 goto out_enable;
1638
1639         handled = 1;
1640
1641         if (unlikely(!netif_running(dev)))
1642                 goto out_unlock;
1643
1644         /* If RFDListEnd interrupt, restore all used RFDs. */
1645         if (status & IPG_IS_RFD_LIST_END) {
1646                 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1647
1648                 /* The RFD list end indicates an RFD was encountered
1649                  * with a 0 NextPtr, or with an RFDDone bit set to 1
1650                  * (indicating the RFD is not read for use by the
1651                  * IPG.) Try to restore all RFDs.
1652                  */
1653                 ipg_nic_rxrestore(dev);
1654
1655 #ifdef IPG_DEBUG
1656                 /* Increment the RFDlistendCount counter. */
1657                 sp->RFDlistendCount++;
1658 #endif
1659         }
1660
1661         /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1662          * IntRequested interrupt, process received frames. */
1663         if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1664             (status & IPG_IS_RFD_LIST_END) ||
1665             (status & IPG_IS_RX_DMA_COMPLETE) ||
1666             (status & IPG_IS_INT_REQUESTED)) {
1667 #ifdef IPG_DEBUG
1668                 /* Increment the RFD list checked counter if interrupted
1669                  * only to check the RFD list. */
1670                 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1671                                 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1672                                (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1673                                 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1674                                 IPG_IS_UPDATE_STATS)))
1675                         sp->RFDListCheckedCount++;
1676 #endif
1677
1678                 ipg_nic_rx(dev);
1679         }
1680
1681         /* If TxDMAComplete interrupt, free used TFDs. */
1682         if (status & IPG_IS_TX_DMA_COMPLETE)
1683                 ipg_nic_txfree(dev);
1684
1685         /* TxComplete interrupts indicate one of numerous actions.
1686          * Determine what action to take based on TXSTATUS register.
1687          */
1688         if (status & IPG_IS_TX_COMPLETE)
1689                 ipg_nic_txcleanup(dev);
1690
1691         /* If UpdateStats interrupt, update Linux Ethernet statistics */
1692         if (status & IPG_IS_UPDATE_STATS)
1693                 ipg_nic_get_stats(dev);
1694
1695         /* If HostError interrupt, reset IPG. */
1696         if (status & IPG_IS_HOST_ERROR) {
1697                 IPG_DDEBUG_MSG("HostError Interrupt\n");
1698
1699                 schedule_delayed_work(&sp->task, 0);
1700         }
1701
1702         /* If LinkEvent interrupt, resolve autonegotiation. */
1703         if (status & IPG_IS_LINK_EVENT) {
1704                 if (ipg_config_autoneg(dev) < 0)
1705                         printk(KERN_INFO "%s: Auto-negotiation error.\n",
1706                                dev->name);
1707         }
1708
1709         /* If MACCtrlFrame interrupt, do nothing. */
1710         if (status & IPG_IS_MAC_CTRL_FRAME)
1711                 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1712
1713         /* If RxComplete interrupt, do nothing. */
1714         if (status & IPG_IS_RX_COMPLETE)
1715                 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1716
1717         /* If RxEarly interrupt, do nothing. */
1718         if (status & IPG_IS_RX_EARLY)
1719                 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1720
1721 out_enable:
1722         /* Re-enable IPG interrupts. */
1723         ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1724                 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1725                 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1726 out_unlock:
1727         spin_unlock(&sp->lock);
1728
1729         return IRQ_RETVAL(handled);
1730 }
1731
1732 static void ipg_rx_clear(struct ipg_nic_private *sp)
1733 {
1734         unsigned int i;
1735
1736         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1737                 if (sp->RxBuff[i]) {
1738                         struct ipg_rx *rxfd = sp->rxd + i;
1739
1740                         dev_kfree_skb_irq(sp->RxBuff[i]);
1741                         sp->RxBuff[i] = NULL;
1742                         pci_unmap_single(sp->pdev,
1743                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1744                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1745                 }
1746         }
1747 }
1748
1749 static void ipg_tx_clear(struct ipg_nic_private *sp)
1750 {
1751         unsigned int i;
1752
1753         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1754                 if (sp->TxBuff[i]) {
1755                         struct ipg_tx *txfd = sp->txd + i;
1756
1757                         pci_unmap_single(sp->pdev,
1758                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1759                                 sp->TxBuff[i]->len, PCI_DMA_TODEVICE);
1760
1761                         dev_kfree_skb_irq(sp->TxBuff[i]);
1762
1763                         sp->TxBuff[i] = NULL;
1764                 }
1765         }
1766 }
1767
1768 static int ipg_nic_open(struct net_device *dev)
1769 {
1770         struct ipg_nic_private *sp = netdev_priv(dev);
1771         void __iomem *ioaddr = sp->ioaddr;
1772         struct pci_dev *pdev = sp->pdev;
1773         int rc;
1774
1775         IPG_DEBUG_MSG("_nic_open\n");
1776
1777         sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1778
1779         /* Check for interrupt line conflicts, and request interrupt
1780          * line for IPG.
1781          *
1782          * IMPORTANT: Disable IPG interrupts prior to registering
1783          *            IRQ.
1784          */
1785         ipg_w16(0x0000, INT_ENABLE);
1786
1787         /* Register the interrupt line to be used by the IPG within
1788          * the Linux system.
1789          */
1790         rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1791                          dev->name, dev);
1792         if (rc < 0) {
1793                 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1794                        dev->name);
1795                 goto out;
1796         }
1797
1798         dev->irq = pdev->irq;
1799
1800         rc = -ENOMEM;
1801
1802         sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1803                                      &sp->rxd_map, GFP_KERNEL);
1804         if (!sp->rxd)
1805                 goto err_free_irq_0;
1806
1807         sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1808                                      &sp->txd_map, GFP_KERNEL);
1809         if (!sp->txd)
1810                 goto err_free_rx_1;
1811
1812         rc = init_rfdlist(dev);
1813         if (rc < 0) {
1814                 printk(KERN_INFO "%s: Error during configuration.\n",
1815                        dev->name);
1816                 goto err_free_tx_2;
1817         }
1818
1819         init_tfdlist(dev);
1820
1821         rc = ipg_io_config(dev);
1822         if (rc < 0) {
1823                 printk(KERN_INFO "%s: Error during configuration.\n",
1824                        dev->name);
1825                 goto err_release_tfdlist_3;
1826         }
1827
1828         /* Resolve autonegotiation. */
1829         if (ipg_config_autoneg(dev) < 0)
1830                 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1831
1832 #ifdef JUMBO_FRAME
1833         /* initialize JUMBO Frame control variable */
1834         sp->Jumbo.FoundStart = 0;
1835         sp->Jumbo.CurrentSize = 0;
1836         sp->Jumbo.skb = 0;
1837         dev->mtu = IPG_TXFRAG_SIZE;
1838 #endif
1839
1840         /* Enable transmit and receive operation of the IPG. */
1841         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1842                  IPG_MC_RSVD_MASK, MAC_CTRL);
1843
1844         netif_start_queue(dev);
1845 out:
1846         return rc;
1847
1848 err_release_tfdlist_3:
1849         ipg_tx_clear(sp);
1850         ipg_rx_clear(sp);
1851 err_free_tx_2:
1852         dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1853 err_free_rx_1:
1854         dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1855 err_free_irq_0:
1856         free_irq(pdev->irq, dev);
1857         goto out;
1858 }
1859
1860 static int ipg_nic_stop(struct net_device *dev)
1861 {
1862         struct ipg_nic_private *sp = netdev_priv(dev);
1863         void __iomem *ioaddr = sp->ioaddr;
1864         struct pci_dev *pdev = sp->pdev;
1865
1866         IPG_DEBUG_MSG("_nic_stop\n");
1867
1868         netif_stop_queue(dev);
1869
1870         IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1871         IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1872         IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1873         IPG_DUMPTFDLIST(dev);
1874
1875         do {
1876                 (void) ipg_r16(INT_STATUS_ACK);
1877
1878                 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1879
1880                 synchronize_irq(pdev->irq);
1881         } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1882
1883         ipg_rx_clear(sp);
1884
1885         ipg_tx_clear(sp);
1886
1887         pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1888         pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1889
1890         free_irq(pdev->irq, dev);
1891
1892         return 0;
1893 }
1894
1895 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1896 {
1897         struct ipg_nic_private *sp = netdev_priv(dev);
1898         void __iomem *ioaddr = sp->ioaddr;
1899         unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1900         unsigned long flags;
1901         struct ipg_tx *txfd;
1902
1903         IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1904
1905         /* If in 10Mbps mode, stop the transmit queue so
1906          * no more transmit frames are accepted.
1907          */
1908         if (sp->tenmbpsmode)
1909                 netif_stop_queue(dev);
1910
1911         if (sp->ResetCurrentTFD) {
1912                 sp->ResetCurrentTFD = 0;
1913                 entry = 0;
1914         }
1915
1916         txfd = sp->txd + entry;
1917
1918         sp->TxBuff[entry] = skb;
1919
1920         /* Clear all TFC fields, except TFDDONE. */
1921         txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1922
1923         /* Specify the TFC field within the TFD. */
1924         txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1925                 (IPG_TFC_FRAMEID & cpu_to_le64(sp->tx_current)) |
1926                 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1927
1928         /* Request TxComplete interrupts at an interval defined
1929          * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1930          * Request TxComplete interrupt for every frame
1931          * if in 10Mbps mode to accomodate problem with 10Mbps
1932          * processing.
1933          */
1934         if (sp->tenmbpsmode)
1935                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1936         txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1937         /* Based on compilation option, determine if FCS is to be
1938          * appended to transmit frame by IPG.
1939          */
1940         if (!(IPG_APPEND_FCS_ON_TX))
1941                 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1942
1943         /* Based on compilation option, determine if IP, TCP and/or
1944          * UDP checksums are to be added to transmit frame by IPG.
1945          */
1946         if (IPG_ADD_IPCHECKSUM_ON_TX)
1947                 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1948
1949         if (IPG_ADD_TCPCHECKSUM_ON_TX)
1950                 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1951
1952         if (IPG_ADD_UDPCHECKSUM_ON_TX)
1953                 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1954
1955         /* Based on compilation option, determine if VLAN tag info is to be
1956          * inserted into transmit frame by IPG.
1957          */
1958         if (IPG_INSERT_MANUAL_VLAN_TAG) {
1959                 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1960                         ((u64) IPG_MANUAL_VLAN_VID << 32) |
1961                         ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1962                         ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1963         }
1964
1965         /* The fragment start location within system memory is defined
1966          * by the sk_buff structure's data field. The physical address
1967          * of this location within the system's virtual memory space
1968          * is determined using the IPG_HOST2BUS_MAP function.
1969          */
1970         txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1971                 skb->len, PCI_DMA_TODEVICE));
1972
1973         /* The length of the fragment within system memory is defined by
1974          * the sk_buff structure's len field.
1975          */
1976         txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1977                 ((u64) (skb->len & 0xffff) << 48));
1978
1979         /* Clear the TFDDone bit last to indicate the TFD is ready
1980          * for transfer to the IPG.
1981          */
1982         txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1983
1984         spin_lock_irqsave(&sp->lock, flags);
1985
1986         sp->tx_current++;
1987
1988         mmiowb();
1989
1990         ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1991
1992         if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1993                 netif_stop_queue(dev);
1994
1995         spin_unlock_irqrestore(&sp->lock, flags);
1996
1997         return NETDEV_TX_OK;
1998 }
1999
2000 static void ipg_set_phy_default_param(unsigned char rev,
2001                                       struct net_device *dev, int phy_address)
2002 {
2003         unsigned short length;
2004         unsigned char revision;
2005         unsigned short *phy_param;
2006         unsigned short address, value;
2007
2008         phy_param = &DefaultPhyParam[0];
2009         length = *phy_param & 0x00FF;
2010         revision = (unsigned char)((*phy_param) >> 8);
2011         phy_param++;
2012         while (length != 0) {
2013                 if (rev == revision) {
2014                         while (length > 1) {
2015                                 address = *phy_param;
2016                                 value = *(phy_param + 1);
2017                                 phy_param += 2;
2018                                 mdio_write(dev, phy_address, address, value);
2019                                 length -= 4;
2020                         }
2021                         break;
2022                 } else {
2023                         phy_param += length / 2;
2024                         length = *phy_param & 0x00FF;
2025                         revision = (unsigned char)((*phy_param) >> 8);
2026                         phy_param++;
2027                 }
2028         }
2029 }
2030
2031 /* JES20040127EEPROM */
2032 static int read_eeprom(struct net_device *dev, int eep_addr)
2033 {
2034         void __iomem *ioaddr = ipg_ioaddr(dev);
2035         unsigned int i;
2036         int ret = 0;
2037         u16 value;
2038
2039         value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2040         ipg_w16(value, EEPROM_CTRL);
2041
2042         for (i = 0; i < 1000; i++) {
2043                 u16 data;
2044
2045                 mdelay(10);
2046                 data = ipg_r16(EEPROM_CTRL);
2047                 if (!(data & IPG_EC_EEPROM_BUSY)) {
2048                         ret = ipg_r16(EEPROM_DATA);
2049                         break;
2050                 }
2051         }
2052         return ret;
2053 }
2054
2055 static void ipg_init_mii(struct net_device *dev)
2056 {
2057         struct ipg_nic_private *sp = netdev_priv(dev);
2058         struct mii_if_info *mii_if = &sp->mii_if;
2059         int phyaddr;
2060
2061         mii_if->dev          = dev;
2062         mii_if->mdio_read    = mdio_read;
2063         mii_if->mdio_write   = mdio_write;
2064         mii_if->phy_id_mask  = 0x1f;
2065         mii_if->reg_num_mask = 0x1f;
2066
2067         mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2068
2069         if (phyaddr != 0x1f) {
2070                 u16 mii_phyctrl, mii_1000cr;
2071                 u8 revisionid = 0;
2072
2073                 mii_1000cr  = mdio_read(dev, phyaddr, MII_CTRL1000);
2074                 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2075                         GMII_PHY_1000BASETCONTROL_PreferMaster;
2076                 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2077
2078                 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2079
2080                 /* Set default phyparam */
2081                 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2082                 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2083
2084                 /* Reset PHY */
2085                 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2086                 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2087
2088         }
2089 }
2090
2091 static int ipg_hw_init(struct net_device *dev)
2092 {
2093         struct ipg_nic_private *sp = netdev_priv(dev);
2094         void __iomem *ioaddr = sp->ioaddr;
2095         unsigned int i;
2096         int rc;
2097
2098         /* Read/Write and Reset EEPROM Value Jesse20040128EEPROM_VALUE */
2099         /* Read LED Mode Configuration from EEPROM */
2100         sp->LED_Mode = read_eeprom(dev, 6);
2101
2102         /* Reset all functions within the IPG. Do not assert
2103          * RST_OUT as not compatible with some PHYs.
2104          */
2105         rc = ipg_reset(dev, IPG_RESET_MASK);
2106         if (rc < 0)
2107                 goto out;
2108
2109         ipg_init_mii(dev);
2110
2111         /* Read MAC Address from EEPROM */
2112         for (i = 0; i < 3; i++)
2113                 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2114
2115         for (i = 0; i < 3; i++)
2116                 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2117
2118         /* Set station address in ethernet_device structure. */
2119         dev->dev_addr[0] =  ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2120         dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2121         dev->dev_addr[2] =  ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2122         dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2123         dev->dev_addr[4] =  ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2124         dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2125 out:
2126         return rc;
2127 }
2128
2129 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2130 {
2131         struct ipg_nic_private *sp = netdev_priv(dev);
2132         int rc;
2133
2134         mutex_lock(&sp->mii_mutex);
2135         rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2136         mutex_unlock(&sp->mii_mutex);
2137
2138         return rc;
2139 }
2140
2141 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2142 {
2143         /* Function to accomodate changes to Maximum Transfer Unit
2144          * (or MTU) of IPG NIC. Cannot use default function since
2145          * the default will not allow for MTU > 1500 bytes.
2146          */
2147
2148         IPG_DEBUG_MSG("_nic_change_mtu\n");
2149
2150         /* Check that the new MTU value is between 68 (14 byte header, 46
2151          * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2152          * corresponds to the MAXFRAMESIZE register in the IPG.
2153          */
2154         if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2155                 return -EINVAL;
2156
2157         dev->mtu = new_mtu;
2158
2159         return 0;
2160 }
2161
2162 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2163 {
2164         struct ipg_nic_private *sp = netdev_priv(dev);
2165         int rc;
2166
2167         mutex_lock(&sp->mii_mutex);
2168         rc = mii_ethtool_gset(&sp->mii_if, cmd);
2169         mutex_unlock(&sp->mii_mutex);
2170
2171         return rc;
2172 }
2173
2174 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2175 {
2176         struct ipg_nic_private *sp = netdev_priv(dev);
2177         int rc;
2178
2179         mutex_lock(&sp->mii_mutex);
2180         rc = mii_ethtool_sset(&sp->mii_if, cmd);
2181         mutex_unlock(&sp->mii_mutex);
2182
2183         return rc;
2184 }
2185
2186 static int ipg_nway_reset(struct net_device *dev)
2187 {
2188         struct ipg_nic_private *sp = netdev_priv(dev);
2189         int rc;
2190
2191         mutex_lock(&sp->mii_mutex);
2192         rc = mii_nway_restart(&sp->mii_if);
2193         mutex_unlock(&sp->mii_mutex);
2194
2195         return rc;
2196 }
2197
2198 static struct ethtool_ops ipg_ethtool_ops = {
2199         .get_settings = ipg_get_settings,
2200         .set_settings = ipg_set_settings,
2201         .nway_reset   = ipg_nway_reset,
2202 };
2203
2204 static void ipg_remove(struct pci_dev *pdev)
2205 {
2206         struct net_device *dev = pci_get_drvdata(pdev);
2207         struct ipg_nic_private *sp = netdev_priv(dev);
2208
2209         IPG_DEBUG_MSG("_remove\n");
2210
2211         /* Un-register Ethernet device. */
2212         unregister_netdev(dev);
2213
2214         pci_iounmap(pdev, sp->ioaddr);
2215
2216         pci_release_regions(pdev);
2217
2218         free_netdev(dev);
2219         pci_disable_device(pdev);
2220         pci_set_drvdata(pdev, NULL);
2221 }
2222
2223 static int __devinit ipg_probe(struct pci_dev *pdev,
2224                                const struct pci_device_id *id)
2225 {
2226         unsigned int i = id->driver_data;
2227         struct ipg_nic_private *sp;
2228         struct net_device *dev;
2229         void __iomem *ioaddr;
2230         int rc;
2231
2232         rc = pci_enable_device(pdev);
2233         if (rc < 0)
2234                 goto out;
2235
2236         printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2237
2238         pci_set_master(pdev);
2239
2240         rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2241         if (rc < 0) {
2242                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2243                 if (rc < 0) {
2244                         printk(KERN_ERR "%s: DMA config failed.\n",
2245                                pci_name(pdev));
2246                         goto err_disable_0;
2247                 }
2248         }
2249
2250         /*
2251          * Initialize net device.
2252          */
2253         dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2254         if (!dev) {
2255                 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2256                 rc = -ENOMEM;
2257                 goto err_disable_0;
2258         }
2259
2260         sp = netdev_priv(dev);
2261         spin_lock_init(&sp->lock);
2262         mutex_init(&sp->mii_mutex);
2263
2264         /* Declare IPG NIC functions for Ethernet device methods.
2265          */
2266         dev->open = &ipg_nic_open;
2267         dev->stop = &ipg_nic_stop;
2268         dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2269         dev->get_stats = &ipg_nic_get_stats;
2270         dev->set_multicast_list = &ipg_nic_set_multicast_list;
2271         dev->do_ioctl = ipg_ioctl;
2272         dev->tx_timeout = ipg_tx_timeout;
2273         dev->change_mtu = &ipg_nic_change_mtu;
2274
2275         SET_NETDEV_DEV(dev, &pdev->dev);
2276         SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2277
2278         rc = pci_request_regions(pdev, DRV_NAME);
2279         if (rc)
2280                 goto err_free_dev_1;
2281
2282         ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2283         if (!ioaddr) {
2284                 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2285                 rc = -EIO;
2286                 goto err_release_regions_2;
2287         }
2288
2289         /* Save the pointer to the PCI device information. */
2290         sp->ioaddr = ioaddr;
2291         sp->pdev = pdev;
2292         sp->dev = dev;
2293
2294         INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2295
2296         pci_set_drvdata(pdev, dev);
2297
2298         rc = ipg_hw_init(dev);
2299         if (rc < 0)
2300                 goto err_unmap_3;
2301
2302         rc = register_netdev(dev);
2303         if (rc < 0)
2304                 goto err_unmap_3;
2305
2306         printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2307 out:
2308         return rc;
2309
2310 err_unmap_3:
2311         pci_iounmap(pdev, ioaddr);
2312 err_release_regions_2:
2313         pci_release_regions(pdev);
2314 err_free_dev_1:
2315         free_netdev(dev);
2316 err_disable_0:
2317         pci_disable_device(pdev);
2318         goto out;
2319 }
2320
2321 static struct pci_driver ipg_pci_driver = {
2322         .name           = IPG_DRIVER_NAME,
2323         .id_table       = ipg_pci_tbl,
2324         .probe          = ipg_probe,
2325         .remove         = __devexit_p(ipg_remove),
2326 };
2327
2328 static int __init ipg_init_module(void)
2329 {
2330         return pci_register_driver(&ipg_pci_driver);
2331 }
2332
2333 static void __exit ipg_exit_module(void)
2334 {
2335         pci_unregister_driver(&ipg_pci_driver);
2336 }
2337
2338 module_init(ipg_init_module);
2339 module_exit(ipg_exit_module);