1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
48 #include <linux/dca.h>
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
63 static struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
70 /* required last entry */
74 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
76 void igb_reset(struct igb_adapter *);
77 static int igb_setup_all_tx_resources(struct igb_adapter *);
78 static int igb_setup_all_rx_resources(struct igb_adapter *);
79 static void igb_free_all_tx_resources(struct igb_adapter *);
80 static void igb_free_all_rx_resources(struct igb_adapter *);
81 void igb_update_stats(struct igb_adapter *);
82 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83 static void __devexit igb_remove(struct pci_dev *pdev);
84 static int igb_sw_init(struct igb_adapter *);
85 static int igb_open(struct net_device *);
86 static int igb_close(struct net_device *);
87 static void igb_configure_tx(struct igb_adapter *);
88 static void igb_configure_rx(struct igb_adapter *);
89 static void igb_setup_rctl(struct igb_adapter *);
90 static void igb_clean_all_tx_rings(struct igb_adapter *);
91 static void igb_clean_all_rx_rings(struct igb_adapter *);
92 static void igb_clean_tx_ring(struct igb_ring *);
93 static void igb_clean_rx_ring(struct igb_ring *);
94 static void igb_set_multi(struct net_device *);
95 static void igb_update_phy_info(unsigned long);
96 static void igb_watchdog(unsigned long);
97 static void igb_watchdog_task(struct work_struct *);
98 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
100 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101 static struct net_device_stats *igb_get_stats(struct net_device *);
102 static int igb_change_mtu(struct net_device *, int);
103 static int igb_set_mac(struct net_device *, void *);
104 static irqreturn_t igb_intr(int irq, void *);
105 static irqreturn_t igb_intr_msi(int irq, void *);
106 static irqreturn_t igb_msix_other(int irq, void *);
107 static irqreturn_t igb_msix_rx(int irq, void *);
108 static irqreturn_t igb_msix_tx(int irq, void *);
109 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
110 #ifdef CONFIG_IGB_DCA
111 static void igb_update_rx_dca(struct igb_ring *);
112 static void igb_update_tx_dca(struct igb_ring *);
113 static void igb_setup_dca(struct igb_adapter *);
114 #endif /* CONFIG_IGB_DCA */
115 static bool igb_clean_tx_irq(struct igb_ring *);
116 static int igb_poll(struct napi_struct *, int);
117 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
119 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
120 static void igb_tx_timeout(struct net_device *);
121 static void igb_reset_task(struct work_struct *);
122 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
123 static void igb_vlan_rx_add_vid(struct net_device *, u16);
124 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
125 static void igb_restore_vlan(struct igb_adapter *);
127 static int igb_suspend(struct pci_dev *, pm_message_t);
129 static int igb_resume(struct pci_dev *);
131 static void igb_shutdown(struct pci_dev *);
132 #ifdef CONFIG_IGB_DCA
133 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
134 static struct notifier_block dca_notifier = {
135 .notifier_call = igb_notify_dca,
141 #ifdef CONFIG_NET_POLL_CONTROLLER
142 /* for netdump / net console */
143 static void igb_netpoll(struct net_device *);
146 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
147 pci_channel_state_t);
148 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
149 static void igb_io_resume(struct pci_dev *);
151 static struct pci_error_handlers igb_err_handler = {
152 .error_detected = igb_io_error_detected,
153 .slot_reset = igb_io_slot_reset,
154 .resume = igb_io_resume,
158 static struct pci_driver igb_driver = {
159 .name = igb_driver_name,
160 .id_table = igb_pci_tbl,
162 .remove = __devexit_p(igb_remove),
164 /* Power Managment Hooks */
165 .suspend = igb_suspend,
166 .resume = igb_resume,
168 .shutdown = igb_shutdown,
169 .err_handler = &igb_err_handler
172 static int global_quad_port_a; /* global quad port a indication */
174 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
175 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
176 MODULE_LICENSE("GPL");
177 MODULE_VERSION(DRV_VERSION);
180 * Scale the NIC clock cycle by a large factor so that
181 * relatively small clock corrections can be added or
182 * substracted at each clock tick. The drawbacks of a
183 * large factor are a) that the clock register overflows
184 * more quickly (not such a big deal) and b) that the
185 * increment per tick has to fit into 24 bits.
188 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
190 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
192 * The base scale factor is intentionally a power of two
193 * so that the division in %struct timecounter can be done with
196 #define IGB_TSYNC_SHIFT (19)
197 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
200 * The duration of one clock cycle of the NIC.
202 * @todo This hard-coded value is part of the specification and might change
203 * in future hardware revisions. Add revision check.
205 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
207 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
208 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
212 * igb_read_clock - read raw cycle counter (to be used by time counter)
214 static cycle_t igb_read_clock(const struct cyclecounter *tc)
216 struct igb_adapter *adapter =
217 container_of(tc, struct igb_adapter, cycles);
218 struct e1000_hw *hw = &adapter->hw;
221 stamp = rd32(E1000_SYSTIML);
222 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
229 * igb_get_hw_dev_name - return device name string
230 * used by hardware layer to print debugging information
232 char *igb_get_hw_dev_name(struct e1000_hw *hw)
234 struct igb_adapter *adapter = hw->back;
235 return adapter->netdev->name;
239 * igb_get_time_str - format current NIC and system time as string
241 static char *igb_get_time_str(struct igb_adapter *adapter,
244 cycle_t hw = adapter->cycles.read(&adapter->cycles);
245 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
247 struct timespec delta;
248 getnstimeofday(&sys);
250 delta = timespec_sub(nic, sys);
253 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
255 (long)nic.tv_sec, nic.tv_nsec,
256 (long)sys.tv_sec, sys.tv_nsec,
257 (long)delta.tv_sec, delta.tv_nsec);
264 * igb_init_module - Driver Registration Routine
266 * igb_init_module is the first routine called when the driver is
267 * loaded. All it does is register with the PCI subsystem.
269 static int __init igb_init_module(void)
272 printk(KERN_INFO "%s - version %s\n",
273 igb_driver_string, igb_driver_version);
275 printk(KERN_INFO "%s\n", igb_copyright);
277 global_quad_port_a = 0;
279 #ifdef CONFIG_IGB_DCA
280 dca_register_notify(&dca_notifier);
283 ret = pci_register_driver(&igb_driver);
287 module_init(igb_init_module);
290 * igb_exit_module - Driver Exit Cleanup Routine
292 * igb_exit_module is called just before the driver is removed
295 static void __exit igb_exit_module(void)
297 #ifdef CONFIG_IGB_DCA
298 dca_unregister_notify(&dca_notifier);
300 pci_unregister_driver(&igb_driver);
303 module_exit(igb_exit_module);
305 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
307 * igb_cache_ring_register - Descriptor ring to register mapping
308 * @adapter: board private structure to initialize
310 * Once we know the feature-set enabled for the device, we'll cache
311 * the register offset the descriptor ring is assigned to.
313 static void igb_cache_ring_register(struct igb_adapter *adapter)
317 switch (adapter->hw.mac.type) {
319 /* The queues are allocated for virtualization such that VF 0
320 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
321 * In order to avoid collision we start at the first free queue
322 * and continue consuming queues in the same sequence
324 for (i = 0; i < adapter->num_rx_queues; i++)
325 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
326 for (i = 0; i < adapter->num_tx_queues; i++)
327 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
331 for (i = 0; i < adapter->num_rx_queues; i++)
332 adapter->rx_ring[i].reg_idx = i;
333 for (i = 0; i < adapter->num_tx_queues; i++)
334 adapter->tx_ring[i].reg_idx = i;
340 * igb_alloc_queues - Allocate memory for all rings
341 * @adapter: board private structure to initialize
343 * We allocate one ring per queue at run-time since we don't know the
344 * number of queues at compile-time.
346 static int igb_alloc_queues(struct igb_adapter *adapter)
350 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
351 sizeof(struct igb_ring), GFP_KERNEL);
352 if (!adapter->tx_ring)
355 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
356 sizeof(struct igb_ring), GFP_KERNEL);
357 if (!adapter->rx_ring) {
358 kfree(adapter->tx_ring);
362 adapter->rx_ring->buddy = adapter->tx_ring;
364 for (i = 0; i < adapter->num_tx_queues; i++) {
365 struct igb_ring *ring = &(adapter->tx_ring[i]);
366 ring->count = adapter->tx_ring_count;
367 ring->adapter = adapter;
368 ring->queue_index = i;
370 for (i = 0; i < adapter->num_rx_queues; i++) {
371 struct igb_ring *ring = &(adapter->rx_ring[i]);
372 ring->count = adapter->rx_ring_count;
373 ring->adapter = adapter;
374 ring->queue_index = i;
375 ring->itr_register = E1000_ITR;
377 /* set a default napi handler for each rx_ring */
378 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
381 igb_cache_ring_register(adapter);
385 static void igb_free_queues(struct igb_adapter *adapter)
389 for (i = 0; i < adapter->num_rx_queues; i++)
390 netif_napi_del(&adapter->rx_ring[i].napi);
392 kfree(adapter->tx_ring);
393 kfree(adapter->rx_ring);
396 #define IGB_N0_QUEUE -1
397 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
398 int tx_queue, int msix_vector)
401 struct e1000_hw *hw = &adapter->hw;
404 switch (hw->mac.type) {
406 /* The 82575 assigns vectors using a bitmask, which matches the
407 bitmask for the EICR/EIMS/EIMC registers. To assign one
408 or more queues to a vector, we write the appropriate bits
409 into the MSIXBM register for that vector. */
410 if (rx_queue > IGB_N0_QUEUE) {
411 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
412 adapter->rx_ring[rx_queue].eims_value = msixbm;
414 if (tx_queue > IGB_N0_QUEUE) {
415 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
416 adapter->tx_ring[tx_queue].eims_value =
417 E1000_EICR_TX_QUEUE0 << tx_queue;
419 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
422 /* 82576 uses a table-based method for assigning vectors.
423 Each queue has a single entry in the table to which we write
424 a vector number along with a "valid" bit. Sadly, the layout
425 of the table is somewhat counterintuitive. */
426 if (rx_queue > IGB_N0_QUEUE) {
427 index = (rx_queue >> 1);
428 ivar = array_rd32(E1000_IVAR0, index);
429 if (rx_queue & 0x1) {
430 /* vector goes into third byte of register */
431 ivar = ivar & 0xFF00FFFF;
432 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
434 /* vector goes into low byte of register */
435 ivar = ivar & 0xFFFFFF00;
436 ivar |= msix_vector | E1000_IVAR_VALID;
438 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
439 array_wr32(E1000_IVAR0, index, ivar);
441 if (tx_queue > IGB_N0_QUEUE) {
442 index = (tx_queue >> 1);
443 ivar = array_rd32(E1000_IVAR0, index);
444 if (tx_queue & 0x1) {
445 /* vector goes into high byte of register */
446 ivar = ivar & 0x00FFFFFF;
447 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
449 /* vector goes into second byte of register */
450 ivar = ivar & 0xFFFF00FF;
451 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
453 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
454 array_wr32(E1000_IVAR0, index, ivar);
464 * igb_configure_msix - Configure MSI-X hardware
466 * igb_configure_msix sets up the hardware to properly
467 * generate MSI-X interrupts.
469 static void igb_configure_msix(struct igb_adapter *adapter)
473 struct e1000_hw *hw = &adapter->hw;
475 adapter->eims_enable_mask = 0;
476 if (hw->mac.type == e1000_82576)
477 /* Turn on MSI-X capability first, or our settings
478 * won't stick. And it will take days to debug. */
479 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
480 E1000_GPIE_PBA | E1000_GPIE_EIAME |
483 for (i = 0; i < adapter->num_tx_queues; i++) {
484 struct igb_ring *tx_ring = &adapter->tx_ring[i];
485 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
486 adapter->eims_enable_mask |= tx_ring->eims_value;
487 if (tx_ring->itr_val)
488 writel(tx_ring->itr_val,
489 hw->hw_addr + tx_ring->itr_register);
491 writel(1, hw->hw_addr + tx_ring->itr_register);
494 for (i = 0; i < adapter->num_rx_queues; i++) {
495 struct igb_ring *rx_ring = &adapter->rx_ring[i];
496 rx_ring->buddy = NULL;
497 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
498 adapter->eims_enable_mask |= rx_ring->eims_value;
499 if (rx_ring->itr_val)
500 writel(rx_ring->itr_val,
501 hw->hw_addr + rx_ring->itr_register);
503 writel(1, hw->hw_addr + rx_ring->itr_register);
507 /* set vector for other causes, i.e. link changes */
508 switch (hw->mac.type) {
510 array_wr32(E1000_MSIXBM(0), vector++,
513 tmp = rd32(E1000_CTRL_EXT);
514 /* enable MSI-X PBA support*/
515 tmp |= E1000_CTRL_EXT_PBA_CLR;
517 /* Auto-Mask interrupts upon ICR read. */
518 tmp |= E1000_CTRL_EXT_EIAME;
519 tmp |= E1000_CTRL_EXT_IRCA;
521 wr32(E1000_CTRL_EXT, tmp);
522 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
523 adapter->eims_other = E1000_EIMS_OTHER;
528 tmp = (vector++ | E1000_IVAR_VALID) << 8;
529 wr32(E1000_IVAR_MISC, tmp);
531 adapter->eims_enable_mask = (1 << (vector)) - 1;
532 adapter->eims_other = 1 << (vector - 1);
535 /* do nothing, since nothing else supports MSI-X */
537 } /* switch (hw->mac.type) */
542 * igb_request_msix - Initialize MSI-X interrupts
544 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
547 static int igb_request_msix(struct igb_adapter *adapter)
549 struct net_device *netdev = adapter->netdev;
550 int i, err = 0, vector = 0;
554 for (i = 0; i < adapter->num_tx_queues; i++) {
555 struct igb_ring *ring = &(adapter->tx_ring[i]);
556 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
557 err = request_irq(adapter->msix_entries[vector].vector,
558 &igb_msix_tx, 0, ring->name,
559 &(adapter->tx_ring[i]));
562 ring->itr_register = E1000_EITR(0) + (vector << 2);
563 ring->itr_val = 976; /* ~4000 ints/sec */
566 for (i = 0; i < adapter->num_rx_queues; i++) {
567 struct igb_ring *ring = &(adapter->rx_ring[i]);
568 if (strlen(netdev->name) < (IFNAMSIZ - 5))
569 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
571 memcpy(ring->name, netdev->name, IFNAMSIZ);
572 err = request_irq(adapter->msix_entries[vector].vector,
573 &igb_msix_rx, 0, ring->name,
574 &(adapter->rx_ring[i]));
577 ring->itr_register = E1000_EITR(0) + (vector << 2);
578 ring->itr_val = adapter->itr;
579 /* overwrite the poll routine for MSIX, we've already done
581 ring->napi.poll = &igb_clean_rx_ring_msix;
585 err = request_irq(adapter->msix_entries[vector].vector,
586 &igb_msix_other, 0, netdev->name, netdev);
590 igb_configure_msix(adapter);
596 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
598 if (adapter->msix_entries) {
599 pci_disable_msix(adapter->pdev);
600 kfree(adapter->msix_entries);
601 adapter->msix_entries = NULL;
602 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
603 pci_disable_msi(adapter->pdev);
609 * igb_set_interrupt_capability - set MSI or MSI-X if supported
611 * Attempt to configure interrupts using the best available
612 * capabilities of the hardware and kernel.
614 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
619 /* Number of supported queues. */
620 /* Having more queues than CPUs doesn't make sense. */
621 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
622 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
624 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
625 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
627 if (!adapter->msix_entries)
630 for (i = 0; i < numvecs; i++)
631 adapter->msix_entries[i].entry = i;
633 err = pci_enable_msix(adapter->pdev,
634 adapter->msix_entries,
639 igb_reset_interrupt_capability(adapter);
641 /* If we can't do MSI-X, try MSI */
643 adapter->num_rx_queues = 1;
644 adapter->num_tx_queues = 1;
645 if (!pci_enable_msi(adapter->pdev))
646 adapter->flags |= IGB_FLAG_HAS_MSI;
648 /* Notify the stack of the (possibly) reduced Tx Queue count. */
649 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
654 * igb_request_irq - initialize interrupts
656 * Attempts to configure interrupts using the best available
657 * capabilities of the hardware and kernel.
659 static int igb_request_irq(struct igb_adapter *adapter)
661 struct net_device *netdev = adapter->netdev;
662 struct e1000_hw *hw = &adapter->hw;
665 if (adapter->msix_entries) {
666 err = igb_request_msix(adapter);
669 /* fall back to MSI */
670 igb_reset_interrupt_capability(adapter);
671 if (!pci_enable_msi(adapter->pdev))
672 adapter->flags |= IGB_FLAG_HAS_MSI;
673 igb_free_all_tx_resources(adapter);
674 igb_free_all_rx_resources(adapter);
675 adapter->num_rx_queues = 1;
676 igb_alloc_queues(adapter);
678 switch (hw->mac.type) {
680 wr32(E1000_MSIXBM(0),
681 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
684 wr32(E1000_IVAR0, E1000_IVAR_VALID);
691 if (adapter->flags & IGB_FLAG_HAS_MSI) {
692 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
693 netdev->name, netdev);
696 /* fall back to legacy interrupts */
697 igb_reset_interrupt_capability(adapter);
698 adapter->flags &= ~IGB_FLAG_HAS_MSI;
701 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
702 netdev->name, netdev);
705 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
712 static void igb_free_irq(struct igb_adapter *adapter)
714 struct net_device *netdev = adapter->netdev;
716 if (adapter->msix_entries) {
719 for (i = 0; i < adapter->num_tx_queues; i++)
720 free_irq(adapter->msix_entries[vector++].vector,
721 &(adapter->tx_ring[i]));
722 for (i = 0; i < adapter->num_rx_queues; i++)
723 free_irq(adapter->msix_entries[vector++].vector,
724 &(adapter->rx_ring[i]));
726 free_irq(adapter->msix_entries[vector++].vector, netdev);
730 free_irq(adapter->pdev->irq, netdev);
734 * igb_irq_disable - Mask off interrupt generation on the NIC
735 * @adapter: board private structure
737 static void igb_irq_disable(struct igb_adapter *adapter)
739 struct e1000_hw *hw = &adapter->hw;
741 if (adapter->msix_entries) {
743 wr32(E1000_EIMC, ~0);
750 synchronize_irq(adapter->pdev->irq);
754 * igb_irq_enable - Enable default interrupt generation settings
755 * @adapter: board private structure
757 static void igb_irq_enable(struct igb_adapter *adapter)
759 struct e1000_hw *hw = &adapter->hw;
761 if (adapter->msix_entries) {
762 wr32(E1000_EIAC, adapter->eims_enable_mask);
763 wr32(E1000_EIAM, adapter->eims_enable_mask);
764 wr32(E1000_EIMS, adapter->eims_enable_mask);
765 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
767 wr32(E1000_IMS, IMS_ENABLE_MASK);
768 wr32(E1000_IAM, IMS_ENABLE_MASK);
772 static void igb_update_mng_vlan(struct igb_adapter *adapter)
774 struct net_device *netdev = adapter->netdev;
775 u16 vid = adapter->hw.mng_cookie.vlan_id;
776 u16 old_vid = adapter->mng_vlan_id;
777 if (adapter->vlgrp) {
778 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
779 if (adapter->hw.mng_cookie.status &
780 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
781 igb_vlan_rx_add_vid(netdev, vid);
782 adapter->mng_vlan_id = vid;
784 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
786 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
788 !vlan_group_get_device(adapter->vlgrp, old_vid))
789 igb_vlan_rx_kill_vid(netdev, old_vid);
791 adapter->mng_vlan_id = vid;
796 * igb_release_hw_control - release control of the h/w to f/w
797 * @adapter: address of board private structure
799 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
800 * For ASF and Pass Through versions of f/w this means that the
801 * driver is no longer loaded.
804 static void igb_release_hw_control(struct igb_adapter *adapter)
806 struct e1000_hw *hw = &adapter->hw;
809 /* Let firmware take over control of h/w */
810 ctrl_ext = rd32(E1000_CTRL_EXT);
812 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
817 * igb_get_hw_control - get control of the h/w from f/w
818 * @adapter: address of board private structure
820 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
821 * For ASF and Pass Through versions of f/w this means that
822 * the driver is loaded.
825 static void igb_get_hw_control(struct igb_adapter *adapter)
827 struct e1000_hw *hw = &adapter->hw;
830 /* Let firmware know the driver has taken over */
831 ctrl_ext = rd32(E1000_CTRL_EXT);
833 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
837 * igb_configure - configure the hardware for RX and TX
838 * @adapter: private board structure
840 static void igb_configure(struct igb_adapter *adapter)
842 struct net_device *netdev = adapter->netdev;
845 igb_get_hw_control(adapter);
846 igb_set_multi(netdev);
848 igb_restore_vlan(adapter);
850 igb_configure_tx(adapter);
851 igb_setup_rctl(adapter);
852 igb_configure_rx(adapter);
854 igb_rx_fifo_flush_82575(&adapter->hw);
856 /* call IGB_DESC_UNUSED which always leaves
857 * at least 1 descriptor unused to make sure
858 * next_to_use != next_to_clean */
859 for (i = 0; i < adapter->num_rx_queues; i++) {
860 struct igb_ring *ring = &adapter->rx_ring[i];
861 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
865 adapter->tx_queue_len = netdev->tx_queue_len;
870 * igb_up - Open the interface and prepare it to handle traffic
871 * @adapter: board private structure
874 int igb_up(struct igb_adapter *adapter)
876 struct e1000_hw *hw = &adapter->hw;
879 /* hardware has been reset, we need to reload some things */
880 igb_configure(adapter);
882 clear_bit(__IGB_DOWN, &adapter->state);
884 for (i = 0; i < adapter->num_rx_queues; i++)
885 napi_enable(&adapter->rx_ring[i].napi);
886 if (adapter->msix_entries)
887 igb_configure_msix(adapter);
889 /* Clear any pending interrupts. */
891 igb_irq_enable(adapter);
893 /* Fire a link change interrupt to start the watchdog. */
894 wr32(E1000_ICS, E1000_ICS_LSC);
898 void igb_down(struct igb_adapter *adapter)
900 struct e1000_hw *hw = &adapter->hw;
901 struct net_device *netdev = adapter->netdev;
905 /* signal that we're down so the interrupt handler does not
906 * reschedule our watchdog timer */
907 set_bit(__IGB_DOWN, &adapter->state);
909 /* disable receives in the hardware */
910 rctl = rd32(E1000_RCTL);
911 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
912 /* flush and sleep below */
914 netif_tx_stop_all_queues(netdev);
916 /* disable transmits in the hardware */
917 tctl = rd32(E1000_TCTL);
918 tctl &= ~E1000_TCTL_EN;
919 wr32(E1000_TCTL, tctl);
920 /* flush both disables and wait for them to finish */
924 for (i = 0; i < adapter->num_rx_queues; i++)
925 napi_disable(&adapter->rx_ring[i].napi);
927 igb_irq_disable(adapter);
929 del_timer_sync(&adapter->watchdog_timer);
930 del_timer_sync(&adapter->phy_info_timer);
932 netdev->tx_queue_len = adapter->tx_queue_len;
933 netif_carrier_off(netdev);
935 /* record the stats before reset*/
936 igb_update_stats(adapter);
938 adapter->link_speed = 0;
939 adapter->link_duplex = 0;
941 if (!pci_channel_offline(adapter->pdev))
943 igb_clean_all_tx_rings(adapter);
944 igb_clean_all_rx_rings(adapter);
947 void igb_reinit_locked(struct igb_adapter *adapter)
949 WARN_ON(in_interrupt());
950 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
954 clear_bit(__IGB_RESETTING, &adapter->state);
957 void igb_reset(struct igb_adapter *adapter)
959 struct e1000_hw *hw = &adapter->hw;
960 struct e1000_mac_info *mac = &hw->mac;
961 struct e1000_fc_info *fc = &hw->fc;
962 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
965 /* Repartition Pba for greater than 9k mtu
966 * To take effect CTRL.RST is required.
978 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
979 (mac->type < e1000_82576)) {
980 /* adjust PBA for jumbo frames */
981 wr32(E1000_PBA, pba);
983 /* To maintain wire speed transmits, the Tx FIFO should be
984 * large enough to accommodate two full transmit packets,
985 * rounded up to the next 1KB and expressed in KB. Likewise,
986 * the Rx FIFO should be large enough to accommodate at least
987 * one full receive packet and is similarly rounded up and
988 * expressed in KB. */
989 pba = rd32(E1000_PBA);
990 /* upper 16 bits has Tx packet buffer allocation size in KB */
991 tx_space = pba >> 16;
992 /* lower 16 bits has Rx packet buffer allocation size in KB */
994 /* the tx fifo also stores 16 bytes of information about the tx
995 * but don't include ethernet FCS because hardware appends it */
996 min_tx_space = (adapter->max_frame_size +
997 sizeof(struct e1000_tx_desc) -
999 min_tx_space = ALIGN(min_tx_space, 1024);
1000 min_tx_space >>= 10;
1001 /* software strips receive CRC, so leave room for it */
1002 min_rx_space = adapter->max_frame_size;
1003 min_rx_space = ALIGN(min_rx_space, 1024);
1004 min_rx_space >>= 10;
1006 /* If current Tx allocation is less than the min Tx FIFO size,
1007 * and the min Tx FIFO size is less than the current Rx FIFO
1008 * allocation, take space away from current Rx allocation */
1009 if (tx_space < min_tx_space &&
1010 ((min_tx_space - tx_space) < pba)) {
1011 pba = pba - (min_tx_space - tx_space);
1013 /* if short on rx space, rx wins and must trump tx
1015 if (pba < min_rx_space)
1018 wr32(E1000_PBA, pba);
1021 /* flow control settings */
1022 /* The high water mark must be low enough to fit one full frame
1023 * (or the size used for early receive) above it in the Rx FIFO.
1024 * Set it to the lower of:
1025 * - 90% of the Rx FIFO size, or
1026 * - the full Rx FIFO size minus one full frame */
1027 hwm = min(((pba << 10) * 9 / 10),
1028 ((pba << 10) - 2 * adapter->max_frame_size));
1030 if (mac->type < e1000_82576) {
1031 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1032 fc->low_water = fc->high_water - 8;
1034 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1035 fc->low_water = fc->high_water - 16;
1037 fc->pause_time = 0xFFFF;
1039 fc->type = fc->original_type;
1041 /* Allow time for pending master requests to run */
1042 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1045 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1046 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1048 igb_update_mng_vlan(adapter);
1050 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1051 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1053 igb_reset_adaptive(&adapter->hw);
1054 igb_get_phy_info(&adapter->hw);
1057 static const struct net_device_ops igb_netdev_ops = {
1058 .ndo_open = igb_open,
1059 .ndo_stop = igb_close,
1060 .ndo_start_xmit = igb_xmit_frame_adv,
1061 .ndo_get_stats = igb_get_stats,
1062 .ndo_set_multicast_list = igb_set_multi,
1063 .ndo_set_mac_address = igb_set_mac,
1064 .ndo_change_mtu = igb_change_mtu,
1065 .ndo_do_ioctl = igb_ioctl,
1066 .ndo_tx_timeout = igb_tx_timeout,
1067 .ndo_validate_addr = eth_validate_addr,
1068 .ndo_vlan_rx_register = igb_vlan_rx_register,
1069 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1070 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1071 #ifdef CONFIG_NET_POLL_CONTROLLER
1072 .ndo_poll_controller = igb_netpoll,
1077 * igb_probe - Device Initialization Routine
1078 * @pdev: PCI device information struct
1079 * @ent: entry in igb_pci_tbl
1081 * Returns 0 on success, negative on failure
1083 * igb_probe initializes an adapter identified by a pci_dev structure.
1084 * The OS initialization, configuring of the adapter private structure,
1085 * and a hardware reset occur.
1087 static int __devinit igb_probe(struct pci_dev *pdev,
1088 const struct pci_device_id *ent)
1090 struct net_device *netdev;
1091 struct igb_adapter *adapter;
1092 struct e1000_hw *hw;
1093 struct pci_dev *us_dev;
1094 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1095 unsigned long mmio_start, mmio_len;
1096 int err, pci_using_dac, pos;
1097 u16 eeprom_data = 0, state = 0;
1098 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1101 err = pci_enable_device_mem(pdev);
1106 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1108 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1112 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1114 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1116 dev_err(&pdev->dev, "No usable DMA "
1117 "configuration, aborting\n");
1123 /* 82575 requires that the pci-e link partner disable the L0s state */
1124 switch (pdev->device) {
1125 case E1000_DEV_ID_82575EB_COPPER:
1126 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1127 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1128 us_dev = pdev->bus->self;
1129 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1131 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1133 state &= ~PCIE_LINK_STATE_L0S;
1134 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1136 dev_info(&pdev->dev,
1137 "Disabling ASPM L0s upstream switch port %s\n",
1144 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1150 err = pci_enable_pcie_error_reporting(pdev);
1152 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1154 /* non-fatal, continue */
1157 pci_set_master(pdev);
1158 pci_save_state(pdev);
1161 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1163 goto err_alloc_etherdev;
1165 SET_NETDEV_DEV(netdev, &pdev->dev);
1167 pci_set_drvdata(pdev, netdev);
1168 adapter = netdev_priv(netdev);
1169 adapter->netdev = netdev;
1170 adapter->pdev = pdev;
1173 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1175 mmio_start = pci_resource_start(pdev, 0);
1176 mmio_len = pci_resource_len(pdev, 0);
1179 hw->hw_addr = ioremap(mmio_start, mmio_len);
1183 netdev->netdev_ops = &igb_netdev_ops;
1184 igb_set_ethtool_ops(netdev);
1185 netdev->watchdog_timeo = 5 * HZ;
1187 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1189 netdev->mem_start = mmio_start;
1190 netdev->mem_end = mmio_start + mmio_len;
1192 /* PCI config space info */
1193 hw->vendor_id = pdev->vendor;
1194 hw->device_id = pdev->device;
1195 hw->revision_id = pdev->revision;
1196 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1197 hw->subsystem_device_id = pdev->subsystem_device;
1199 /* setup the private structure */
1201 /* Copy the default MAC, PHY and NVM function pointers */
1202 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1203 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1204 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1205 /* Initialize skew-specific constants */
1206 err = ei->get_invariants(hw);
1210 /* setup the private structure */
1211 err = igb_sw_init(adapter);
1215 igb_get_bus_info_pcie(hw);
1218 switch (hw->mac.type) {
1220 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1227 hw->phy.autoneg_wait_to_complete = false;
1228 hw->mac.adaptive_ifs = true;
1230 /* Copper options */
1231 if (hw->phy.media_type == e1000_media_type_copper) {
1232 hw->phy.mdix = AUTO_ALL_MODES;
1233 hw->phy.disable_polarity_correction = false;
1234 hw->phy.ms_type = e1000_ms_hw_default;
1237 if (igb_check_reset_block(hw))
1238 dev_info(&pdev->dev,
1239 "PHY reset is blocked due to SOL/IDER session.\n");
1241 netdev->features = NETIF_F_SG |
1243 NETIF_F_HW_VLAN_TX |
1244 NETIF_F_HW_VLAN_RX |
1245 NETIF_F_HW_VLAN_FILTER;
1247 netdev->features |= NETIF_F_IPV6_CSUM;
1248 netdev->features |= NETIF_F_TSO;
1249 netdev->features |= NETIF_F_TSO6;
1251 #ifdef CONFIG_IGB_LRO
1252 netdev->features |= NETIF_F_GRO;
1255 netdev->vlan_features |= NETIF_F_TSO;
1256 netdev->vlan_features |= NETIF_F_TSO6;
1257 netdev->vlan_features |= NETIF_F_IP_CSUM;
1258 netdev->vlan_features |= NETIF_F_SG;
1261 netdev->features |= NETIF_F_HIGHDMA;
1263 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1265 /* before reading the NVM, reset the controller to put the device in a
1266 * known good starting state */
1267 hw->mac.ops.reset_hw(hw);
1269 /* make sure the NVM is good */
1270 if (igb_validate_nvm_checksum(hw) < 0) {
1271 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1276 /* copy the MAC address out of the NVM */
1277 if (hw->mac.ops.read_mac_addr(hw))
1278 dev_err(&pdev->dev, "NVM Read Error\n");
1280 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1281 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1283 if (!is_valid_ether_addr(netdev->perm_addr)) {
1284 dev_err(&pdev->dev, "Invalid MAC Address\n");
1289 init_timer(&adapter->watchdog_timer);
1290 adapter->watchdog_timer.function = &igb_watchdog;
1291 adapter->watchdog_timer.data = (unsigned long) adapter;
1293 init_timer(&adapter->phy_info_timer);
1294 adapter->phy_info_timer.function = &igb_update_phy_info;
1295 adapter->phy_info_timer.data = (unsigned long) adapter;
1297 INIT_WORK(&adapter->reset_task, igb_reset_task);
1298 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1300 /* Initialize link properties that are user-changeable */
1301 adapter->fc_autoneg = true;
1302 hw->mac.autoneg = true;
1303 hw->phy.autoneg_advertised = 0x2f;
1305 hw->fc.original_type = e1000_fc_default;
1306 hw->fc.type = e1000_fc_default;
1308 adapter->itr_setting = 3;
1309 adapter->itr = IGB_START_ITR;
1311 igb_validate_mdi_setting(hw);
1313 adapter->rx_csum = 1;
1315 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1316 * enable the ACPI Magic Packet filter
1319 if (hw->bus.func == 0 ||
1320 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1321 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1323 if (eeprom_data & eeprom_apme_mask)
1324 adapter->eeprom_wol |= E1000_WUFC_MAG;
1326 /* now that we have the eeprom settings, apply the special cases where
1327 * the eeprom may be wrong or the board simply won't support wake on
1328 * lan on a particular port */
1329 switch (pdev->device) {
1330 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1331 adapter->eeprom_wol = 0;
1333 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1334 case E1000_DEV_ID_82576_FIBER:
1335 case E1000_DEV_ID_82576_SERDES:
1336 /* Wake events only supported on port A for dual fiber
1337 * regardless of eeprom setting */
1338 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1339 adapter->eeprom_wol = 0;
1343 /* initialize the wol settings based on the eeprom settings */
1344 adapter->wol = adapter->eeprom_wol;
1345 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1347 /* reset the hardware with the new settings */
1350 /* let the f/w know that the h/w is now under the control of the
1352 igb_get_hw_control(adapter);
1354 /* tell the stack to leave us alone until igb_open() is called */
1355 netif_carrier_off(netdev);
1356 netif_tx_stop_all_queues(netdev);
1358 strcpy(netdev->name, "eth%d");
1359 err = register_netdev(netdev);
1363 #ifdef CONFIG_IGB_DCA
1364 if (dca_add_requester(&pdev->dev) == 0) {
1365 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1366 dev_info(&pdev->dev, "DCA enabled\n");
1367 /* Always use CB2 mode, difference is masked
1368 * in the CB driver. */
1369 wr32(E1000_DCA_CTRL, 2);
1370 igb_setup_dca(adapter);
1375 * Initialize hardware timer: we keep it running just in case
1376 * that some program needs it later on.
1378 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1379 adapter->cycles.read = igb_read_clock;
1380 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1381 adapter->cycles.mult = 1;
1382 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1385 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1388 * Avoid rollover while we initialize by resetting the time counter.
1390 wr32(E1000_SYSTIML, 0x00000000);
1391 wr32(E1000_SYSTIMH, 0x00000000);
1394 * Set registers so that rollover occurs soon to test this.
1396 wr32(E1000_SYSTIML, 0x00000000);
1397 wr32(E1000_SYSTIMH, 0xFF800000);
1400 timecounter_init(&adapter->clock,
1402 ktime_to_ns(ktime_get_real()));
1405 * Synchronize our NIC clock against system wall clock. NIC
1406 * time stamp reading requires ~3us per sample, each sample
1407 * was pretty stable even under load => only require 10
1408 * samples for each offset comparison.
1410 memset(&adapter->compare, 0, sizeof(adapter->compare));
1411 adapter->compare.source = &adapter->clock;
1412 adapter->compare.target = ktime_get_real;
1413 adapter->compare.num_samples = 10;
1414 timecompare_update(&adapter->compare, 0);
1420 "igb: %s: hw %p initialized timer\n",
1421 igb_get_time_str(adapter, buffer),
1426 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1427 /* print bus type/speed/width info */
1428 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1430 ((hw->bus.speed == e1000_bus_speed_2500)
1431 ? "2.5Gb/s" : "unknown"),
1432 ((hw->bus.width == e1000_bus_width_pcie_x4)
1433 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1434 ? "Width x1" : "unknown"),
1437 igb_read_part_num(hw, &part_num);
1438 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1439 (part_num >> 8), (part_num & 0xff));
1441 dev_info(&pdev->dev,
1442 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1443 adapter->msix_entries ? "MSI-X" :
1444 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1445 adapter->num_rx_queues, adapter->num_tx_queues);
1450 igb_release_hw_control(adapter);
1452 if (!igb_check_reset_block(hw))
1455 if (hw->flash_address)
1456 iounmap(hw->flash_address);
1458 igb_free_queues(adapter);
1460 iounmap(hw->hw_addr);
1462 free_netdev(netdev);
1464 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1468 pci_disable_device(pdev);
1473 * igb_remove - Device Removal Routine
1474 * @pdev: PCI device information struct
1476 * igb_remove is called by the PCI subsystem to alert the driver
1477 * that it should release a PCI device. The could be caused by a
1478 * Hot-Plug event, or because the driver is going to be removed from
1481 static void __devexit igb_remove(struct pci_dev *pdev)
1483 struct net_device *netdev = pci_get_drvdata(pdev);
1484 struct igb_adapter *adapter = netdev_priv(netdev);
1485 struct e1000_hw *hw = &adapter->hw;
1488 /* flush_scheduled work may reschedule our watchdog task, so
1489 * explicitly disable watchdog tasks from being rescheduled */
1490 set_bit(__IGB_DOWN, &adapter->state);
1491 del_timer_sync(&adapter->watchdog_timer);
1492 del_timer_sync(&adapter->phy_info_timer);
1494 flush_scheduled_work();
1496 #ifdef CONFIG_IGB_DCA
1497 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1498 dev_info(&pdev->dev, "DCA disabled\n");
1499 dca_remove_requester(&pdev->dev);
1500 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1501 wr32(E1000_DCA_CTRL, 1);
1505 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1506 * would have already happened in close and is redundant. */
1507 igb_release_hw_control(adapter);
1509 unregister_netdev(netdev);
1511 if (!igb_check_reset_block(&adapter->hw))
1512 igb_reset_phy(&adapter->hw);
1514 igb_reset_interrupt_capability(adapter);
1516 igb_free_queues(adapter);
1518 iounmap(hw->hw_addr);
1519 if (hw->flash_address)
1520 iounmap(hw->flash_address);
1521 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1524 free_netdev(netdev);
1526 err = pci_disable_pcie_error_reporting(pdev);
1529 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1531 pci_disable_device(pdev);
1535 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1536 * @adapter: board private structure to initialize
1538 * igb_sw_init initializes the Adapter private data structure.
1539 * Fields are initialized based on PCI device information and
1540 * OS network device settings (MTU size).
1542 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1544 struct e1000_hw *hw = &adapter->hw;
1545 struct net_device *netdev = adapter->netdev;
1546 struct pci_dev *pdev = adapter->pdev;
1548 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1550 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1551 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1552 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1553 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1554 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1555 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1557 /* This call may decrease the number of queues depending on
1558 * interrupt mode. */
1559 igb_set_interrupt_capability(adapter);
1561 if (igb_alloc_queues(adapter)) {
1562 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1566 /* Explicitly disable IRQ since the NIC can be in any state. */
1567 igb_irq_disable(adapter);
1569 set_bit(__IGB_DOWN, &adapter->state);
1574 * igb_open - Called when a network interface is made active
1575 * @netdev: network interface device structure
1577 * Returns 0 on success, negative value on failure
1579 * The open entry point is called when a network interface is made
1580 * active by the system (IFF_UP). At this point all resources needed
1581 * for transmit and receive operations are allocated, the interrupt
1582 * handler is registered with the OS, the watchdog timer is started,
1583 * and the stack is notified that the interface is ready.
1585 static int igb_open(struct net_device *netdev)
1587 struct igb_adapter *adapter = netdev_priv(netdev);
1588 struct e1000_hw *hw = &adapter->hw;
1592 /* disallow open during test */
1593 if (test_bit(__IGB_TESTING, &adapter->state))
1596 /* allocate transmit descriptors */
1597 err = igb_setup_all_tx_resources(adapter);
1601 /* allocate receive descriptors */
1602 err = igb_setup_all_rx_resources(adapter);
1606 /* e1000_power_up_phy(adapter); */
1608 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1609 if ((adapter->hw.mng_cookie.status &
1610 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1611 igb_update_mng_vlan(adapter);
1613 /* before we allocate an interrupt, we must be ready to handle it.
1614 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1615 * as soon as we call pci_request_irq, so we have to setup our
1616 * clean_rx handler before we do so. */
1617 igb_configure(adapter);
1619 err = igb_request_irq(adapter);
1623 /* From here on the code is the same as igb_up() */
1624 clear_bit(__IGB_DOWN, &adapter->state);
1626 for (i = 0; i < adapter->num_rx_queues; i++)
1627 napi_enable(&adapter->rx_ring[i].napi);
1629 /* Clear any pending interrupts. */
1632 igb_irq_enable(adapter);
1634 netif_tx_start_all_queues(netdev);
1636 /* Fire a link status change interrupt to start the watchdog. */
1637 wr32(E1000_ICS, E1000_ICS_LSC);
1642 igb_release_hw_control(adapter);
1643 /* e1000_power_down_phy(adapter); */
1644 igb_free_all_rx_resources(adapter);
1646 igb_free_all_tx_resources(adapter);
1654 * igb_close - Disables a network interface
1655 * @netdev: network interface device structure
1657 * Returns 0, this is not allowed to fail
1659 * The close entry point is called when an interface is de-activated
1660 * by the OS. The hardware is still under the driver's control, but
1661 * needs to be disabled. A global MAC reset is issued to stop the
1662 * hardware, and all transmit and receive resources are freed.
1664 static int igb_close(struct net_device *netdev)
1666 struct igb_adapter *adapter = netdev_priv(netdev);
1668 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1671 igb_free_irq(adapter);
1673 igb_free_all_tx_resources(adapter);
1674 igb_free_all_rx_resources(adapter);
1676 /* kill manageability vlan ID if supported, but not if a vlan with
1677 * the same ID is registered on the host OS (let 8021q kill it) */
1678 if ((adapter->hw.mng_cookie.status &
1679 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1681 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1682 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1688 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1689 * @adapter: board private structure
1690 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1692 * Return 0 on success, negative on failure
1694 int igb_setup_tx_resources(struct igb_adapter *adapter,
1695 struct igb_ring *tx_ring)
1697 struct pci_dev *pdev = adapter->pdev;
1700 size = sizeof(struct igb_buffer) * tx_ring->count;
1701 tx_ring->buffer_info = vmalloc(size);
1702 if (!tx_ring->buffer_info)
1704 memset(tx_ring->buffer_info, 0, size);
1706 /* round up to nearest 4K */
1707 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1708 tx_ring->size = ALIGN(tx_ring->size, 4096);
1710 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1716 tx_ring->adapter = adapter;
1717 tx_ring->next_to_use = 0;
1718 tx_ring->next_to_clean = 0;
1722 vfree(tx_ring->buffer_info);
1723 dev_err(&adapter->pdev->dev,
1724 "Unable to allocate memory for the transmit descriptor ring\n");
1729 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1730 * (Descriptors) for all queues
1731 * @adapter: board private structure
1733 * Return 0 on success, negative on failure
1735 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1740 for (i = 0; i < adapter->num_tx_queues; i++) {
1741 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1743 dev_err(&adapter->pdev->dev,
1744 "Allocation for Tx Queue %u failed\n", i);
1745 for (i--; i >= 0; i--)
1746 igb_free_tx_resources(&adapter->tx_ring[i]);
1751 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1752 r_idx = i % adapter->num_tx_queues;
1753 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1759 * igb_configure_tx - Configure transmit Unit after Reset
1760 * @adapter: board private structure
1762 * Configure the Tx unit of the MAC after a reset.
1764 static void igb_configure_tx(struct igb_adapter *adapter)
1767 struct e1000_hw *hw = &adapter->hw;
1772 for (i = 0; i < adapter->num_tx_queues; i++) {
1773 struct igb_ring *ring = &adapter->tx_ring[i];
1775 wr32(E1000_TDLEN(j),
1776 ring->count * sizeof(struct e1000_tx_desc));
1778 wr32(E1000_TDBAL(j),
1779 tdba & 0x00000000ffffffffULL);
1780 wr32(E1000_TDBAH(j), tdba >> 32);
1782 ring->head = E1000_TDH(j);
1783 ring->tail = E1000_TDT(j);
1784 writel(0, hw->hw_addr + ring->tail);
1785 writel(0, hw->hw_addr + ring->head);
1786 txdctl = rd32(E1000_TXDCTL(j));
1787 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1788 wr32(E1000_TXDCTL(j), txdctl);
1790 /* Turn off Relaxed Ordering on head write-backs. The
1791 * writebacks MUST be delivered in order or it will
1792 * completely screw up our bookeeping.
1794 txctrl = rd32(E1000_DCA_TXCTRL(j));
1795 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1796 wr32(E1000_DCA_TXCTRL(j), txctrl);
1799 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1801 /* Program the Transmit Control Register */
1803 tctl = rd32(E1000_TCTL);
1804 tctl &= ~E1000_TCTL_CT;
1805 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1806 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1808 igb_config_collision_dist(hw);
1810 /* Setup Transmit Descriptor Settings for eop descriptor */
1811 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1813 /* Enable transmits */
1814 tctl |= E1000_TCTL_EN;
1816 wr32(E1000_TCTL, tctl);
1820 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1821 * @adapter: board private structure
1822 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1824 * Returns 0 on success, negative on failure
1826 int igb_setup_rx_resources(struct igb_adapter *adapter,
1827 struct igb_ring *rx_ring)
1829 struct pci_dev *pdev = adapter->pdev;
1832 size = sizeof(struct igb_buffer) * rx_ring->count;
1833 rx_ring->buffer_info = vmalloc(size);
1834 if (!rx_ring->buffer_info)
1836 memset(rx_ring->buffer_info, 0, size);
1838 desc_len = sizeof(union e1000_adv_rx_desc);
1840 /* Round up to nearest 4K */
1841 rx_ring->size = rx_ring->count * desc_len;
1842 rx_ring->size = ALIGN(rx_ring->size, 4096);
1844 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1850 rx_ring->next_to_clean = 0;
1851 rx_ring->next_to_use = 0;
1853 rx_ring->adapter = adapter;
1858 vfree(rx_ring->buffer_info);
1859 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1860 "the receive descriptor ring\n");
1865 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1866 * (Descriptors) for all queues
1867 * @adapter: board private structure
1869 * Return 0 on success, negative on failure
1871 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1875 for (i = 0; i < adapter->num_rx_queues; i++) {
1876 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1878 dev_err(&adapter->pdev->dev,
1879 "Allocation for Rx Queue %u failed\n", i);
1880 for (i--; i >= 0; i--)
1881 igb_free_rx_resources(&adapter->rx_ring[i]);
1890 * igb_setup_rctl - configure the receive control registers
1891 * @adapter: Board private structure
1893 static void igb_setup_rctl(struct igb_adapter *adapter)
1895 struct e1000_hw *hw = &adapter->hw;
1900 rctl = rd32(E1000_RCTL);
1902 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1903 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1905 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1906 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1909 * enable stripping of CRC. It's unlikely this will break BMC
1910 * redirection as it did with e1000. Newer features require
1911 * that the HW strips the CRC.
1913 rctl |= E1000_RCTL_SECRC;
1916 * disable store bad packets and clear size bits.
1918 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1920 /* enable LPE when to prevent packets larger than max_frame_size */
1921 rctl |= E1000_RCTL_LPE;
1923 /* Setup buffer sizes */
1924 switch (adapter->rx_buffer_len) {
1925 case IGB_RXBUFFER_256:
1926 rctl |= E1000_RCTL_SZ_256;
1928 case IGB_RXBUFFER_512:
1929 rctl |= E1000_RCTL_SZ_512;
1932 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1933 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1937 /* 82575 and greater support packet-split where the protocol
1938 * header is placed in skb->data and the packet data is
1939 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1940 * In the case of a non-split, skb->data is linearly filled,
1941 * followed by the page buffers. Therefore, skb->data is
1942 * sized to hold the largest protocol header.
1944 /* allocations using alloc_page take too long for regular MTU
1945 * so only enable packet split for jumbo frames */
1946 if (adapter->netdev->mtu > ETH_DATA_LEN) {
1947 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1948 srrctl |= adapter->rx_ps_hdr_size <<
1949 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1950 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1952 adapter->rx_ps_hdr_size = 0;
1953 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1956 for (i = 0; i < adapter->num_rx_queues; i++) {
1957 j = adapter->rx_ring[i].reg_idx;
1958 wr32(E1000_SRRCTL(j), srrctl);
1961 wr32(E1000_RCTL, rctl);
1965 * igb_configure_rx - Configure receive Unit after Reset
1966 * @adapter: board private structure
1968 * Configure the Rx unit of the MAC after a reset.
1970 static void igb_configure_rx(struct igb_adapter *adapter)
1973 struct e1000_hw *hw = &adapter->hw;
1978 /* disable receives while setting up the descriptors */
1979 rctl = rd32(E1000_RCTL);
1980 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1984 if (adapter->itr_setting > 3)
1985 wr32(E1000_ITR, adapter->itr);
1987 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1988 * the Base and Length of the Rx Descriptor Ring */
1989 for (i = 0; i < adapter->num_rx_queues; i++) {
1990 struct igb_ring *ring = &adapter->rx_ring[i];
1993 wr32(E1000_RDBAL(j),
1994 rdba & 0x00000000ffffffffULL);
1995 wr32(E1000_RDBAH(j), rdba >> 32);
1996 wr32(E1000_RDLEN(j),
1997 ring->count * sizeof(union e1000_adv_rx_desc));
1999 ring->head = E1000_RDH(j);
2000 ring->tail = E1000_RDT(j);
2001 writel(0, hw->hw_addr + ring->tail);
2002 writel(0, hw->hw_addr + ring->head);
2004 rxdctl = rd32(E1000_RXDCTL(j));
2005 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2006 rxdctl &= 0xFFF00000;
2007 rxdctl |= IGB_RX_PTHRESH;
2008 rxdctl |= IGB_RX_HTHRESH << 8;
2009 rxdctl |= IGB_RX_WTHRESH << 16;
2010 wr32(E1000_RXDCTL(j), rxdctl);
2013 if (adapter->num_rx_queues > 1) {
2022 get_random_bytes(&random[0], 40);
2024 if (hw->mac.type >= e1000_82576)
2028 for (j = 0; j < (32 * 4); j++) {
2030 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2033 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2035 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2037 /* Fill out hash function seeds */
2038 for (j = 0; j < 10; j++)
2039 array_wr32(E1000_RSSRK(0), j, random[j]);
2041 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2042 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2043 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2044 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2045 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2046 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2047 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2048 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2051 wr32(E1000_MRQC, mrqc);
2053 /* Multiqueue and raw packet checksumming are mutually
2054 * exclusive. Note that this not the same as TCP/IP
2055 * checksumming, which works fine. */
2056 rxcsum = rd32(E1000_RXCSUM);
2057 rxcsum |= E1000_RXCSUM_PCSD;
2058 wr32(E1000_RXCSUM, rxcsum);
2060 /* Enable Receive Checksum Offload for TCP and UDP */
2061 rxcsum = rd32(E1000_RXCSUM);
2062 if (adapter->rx_csum)
2063 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2065 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2067 wr32(E1000_RXCSUM, rxcsum);
2072 adapter->max_frame_size + VLAN_TAG_SIZE);
2074 wr32(E1000_RLPML, adapter->max_frame_size);
2076 /* Enable Receives */
2077 wr32(E1000_RCTL, rctl);
2081 * igb_free_tx_resources - Free Tx Resources per Queue
2082 * @tx_ring: Tx descriptor ring for a specific queue
2084 * Free all transmit software resources
2086 void igb_free_tx_resources(struct igb_ring *tx_ring)
2088 struct pci_dev *pdev = tx_ring->adapter->pdev;
2090 igb_clean_tx_ring(tx_ring);
2092 vfree(tx_ring->buffer_info);
2093 tx_ring->buffer_info = NULL;
2095 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2097 tx_ring->desc = NULL;
2101 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2102 * @adapter: board private structure
2104 * Free all transmit software resources
2106 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2110 for (i = 0; i < adapter->num_tx_queues; i++)
2111 igb_free_tx_resources(&adapter->tx_ring[i]);
2114 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2115 struct igb_buffer *buffer_info)
2117 if (buffer_info->dma) {
2118 pci_unmap_page(adapter->pdev,
2120 buffer_info->length,
2122 buffer_info->dma = 0;
2124 if (buffer_info->skb) {
2125 dev_kfree_skb_any(buffer_info->skb);
2126 buffer_info->skb = NULL;
2128 buffer_info->time_stamp = 0;
2129 buffer_info->next_to_watch = 0;
2130 /* buffer_info must be completely set up in the transmit path */
2134 * igb_clean_tx_ring - Free Tx Buffers
2135 * @tx_ring: ring to be cleaned
2137 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2139 struct igb_adapter *adapter = tx_ring->adapter;
2140 struct igb_buffer *buffer_info;
2144 if (!tx_ring->buffer_info)
2146 /* Free all the Tx ring sk_buffs */
2148 for (i = 0; i < tx_ring->count; i++) {
2149 buffer_info = &tx_ring->buffer_info[i];
2150 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2153 size = sizeof(struct igb_buffer) * tx_ring->count;
2154 memset(tx_ring->buffer_info, 0, size);
2156 /* Zero out the descriptor ring */
2158 memset(tx_ring->desc, 0, tx_ring->size);
2160 tx_ring->next_to_use = 0;
2161 tx_ring->next_to_clean = 0;
2163 writel(0, adapter->hw.hw_addr + tx_ring->head);
2164 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2168 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2169 * @adapter: board private structure
2171 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2175 for (i = 0; i < adapter->num_tx_queues; i++)
2176 igb_clean_tx_ring(&adapter->tx_ring[i]);
2180 * igb_free_rx_resources - Free Rx Resources
2181 * @rx_ring: ring to clean the resources from
2183 * Free all receive software resources
2185 void igb_free_rx_resources(struct igb_ring *rx_ring)
2187 struct pci_dev *pdev = rx_ring->adapter->pdev;
2189 igb_clean_rx_ring(rx_ring);
2191 vfree(rx_ring->buffer_info);
2192 rx_ring->buffer_info = NULL;
2194 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2196 rx_ring->desc = NULL;
2200 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2201 * @adapter: board private structure
2203 * Free all receive software resources
2205 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2209 for (i = 0; i < adapter->num_rx_queues; i++)
2210 igb_free_rx_resources(&adapter->rx_ring[i]);
2214 * igb_clean_rx_ring - Free Rx Buffers per Queue
2215 * @rx_ring: ring to free buffers from
2217 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2219 struct igb_adapter *adapter = rx_ring->adapter;
2220 struct igb_buffer *buffer_info;
2221 struct pci_dev *pdev = adapter->pdev;
2225 if (!rx_ring->buffer_info)
2227 /* Free all the Rx ring sk_buffs */
2228 for (i = 0; i < rx_ring->count; i++) {
2229 buffer_info = &rx_ring->buffer_info[i];
2230 if (buffer_info->dma) {
2231 if (adapter->rx_ps_hdr_size)
2232 pci_unmap_single(pdev, buffer_info->dma,
2233 adapter->rx_ps_hdr_size,
2234 PCI_DMA_FROMDEVICE);
2236 pci_unmap_single(pdev, buffer_info->dma,
2237 adapter->rx_buffer_len,
2238 PCI_DMA_FROMDEVICE);
2239 buffer_info->dma = 0;
2242 if (buffer_info->skb) {
2243 dev_kfree_skb(buffer_info->skb);
2244 buffer_info->skb = NULL;
2246 if (buffer_info->page) {
2247 if (buffer_info->page_dma)
2248 pci_unmap_page(pdev, buffer_info->page_dma,
2250 PCI_DMA_FROMDEVICE);
2251 put_page(buffer_info->page);
2252 buffer_info->page = NULL;
2253 buffer_info->page_dma = 0;
2254 buffer_info->page_offset = 0;
2258 size = sizeof(struct igb_buffer) * rx_ring->count;
2259 memset(rx_ring->buffer_info, 0, size);
2261 /* Zero out the descriptor ring */
2262 memset(rx_ring->desc, 0, rx_ring->size);
2264 rx_ring->next_to_clean = 0;
2265 rx_ring->next_to_use = 0;
2267 writel(0, adapter->hw.hw_addr + rx_ring->head);
2268 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2272 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2273 * @adapter: board private structure
2275 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2279 for (i = 0; i < adapter->num_rx_queues; i++)
2280 igb_clean_rx_ring(&adapter->rx_ring[i]);
2284 * igb_set_mac - Change the Ethernet Address of the NIC
2285 * @netdev: network interface device structure
2286 * @p: pointer to an address structure
2288 * Returns 0 on success, negative on failure
2290 static int igb_set_mac(struct net_device *netdev, void *p)
2292 struct igb_adapter *adapter = netdev_priv(netdev);
2293 struct e1000_hw *hw = &adapter->hw;
2294 struct sockaddr *addr = p;
2296 if (!is_valid_ether_addr(addr->sa_data))
2297 return -EADDRNOTAVAIL;
2299 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2300 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2302 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2308 * igb_set_multi - Multicast and Promiscuous mode set
2309 * @netdev: network interface device structure
2311 * The set_multi entry point is called whenever the multicast address
2312 * list or the network interface flags are updated. This routine is
2313 * responsible for configuring the hardware for proper multicast,
2314 * promiscuous mode, and all-multi behavior.
2316 static void igb_set_multi(struct net_device *netdev)
2318 struct igb_adapter *adapter = netdev_priv(netdev);
2319 struct e1000_hw *hw = &adapter->hw;
2320 struct e1000_mac_info *mac = &hw->mac;
2321 struct dev_mc_list *mc_ptr;
2326 /* Check for Promiscuous and All Multicast modes */
2328 rctl = rd32(E1000_RCTL);
2330 if (netdev->flags & IFF_PROMISC) {
2331 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2332 rctl &= ~E1000_RCTL_VFE;
2334 if (netdev->flags & IFF_ALLMULTI) {
2335 rctl |= E1000_RCTL_MPE;
2336 rctl &= ~E1000_RCTL_UPE;
2338 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2339 rctl |= E1000_RCTL_VFE;
2341 wr32(E1000_RCTL, rctl);
2343 if (!netdev->mc_count) {
2344 /* nothing to program, so clear mc list */
2345 igb_update_mc_addr_list(hw, NULL, 0, 1,
2346 mac->rar_entry_count);
2350 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2354 /* The shared function expects a packed array of only addresses. */
2355 mc_ptr = netdev->mc_list;
2357 for (i = 0; i < netdev->mc_count; i++) {
2360 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2361 mc_ptr = mc_ptr->next;
2363 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2367 /* Need to wait a few seconds after link up to get diagnostic information from
2369 static void igb_update_phy_info(unsigned long data)
2371 struct igb_adapter *adapter = (struct igb_adapter *) data;
2372 igb_get_phy_info(&adapter->hw);
2376 * igb_has_link - check shared code for link and determine up/down
2377 * @adapter: pointer to driver private info
2379 static bool igb_has_link(struct igb_adapter *adapter)
2381 struct e1000_hw *hw = &adapter->hw;
2382 bool link_active = false;
2385 /* get_link_status is set on LSC (link status) interrupt or
2386 * rx sequence error interrupt. get_link_status will stay
2387 * false until the e1000_check_for_link establishes link
2388 * for copper adapters ONLY
2390 switch (hw->phy.media_type) {
2391 case e1000_media_type_copper:
2392 if (hw->mac.get_link_status) {
2393 ret_val = hw->mac.ops.check_for_link(hw);
2394 link_active = !hw->mac.get_link_status;
2399 case e1000_media_type_fiber:
2400 ret_val = hw->mac.ops.check_for_link(hw);
2401 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2403 case e1000_media_type_internal_serdes:
2404 ret_val = hw->mac.ops.check_for_link(hw);
2405 link_active = hw->mac.serdes_has_link;
2408 case e1000_media_type_unknown:
2416 * igb_watchdog - Timer Call-back
2417 * @data: pointer to adapter cast into an unsigned long
2419 static void igb_watchdog(unsigned long data)
2421 struct igb_adapter *adapter = (struct igb_adapter *)data;
2422 /* Do the rest outside of interrupt context */
2423 schedule_work(&adapter->watchdog_task);
2426 static void igb_watchdog_task(struct work_struct *work)
2428 struct igb_adapter *adapter = container_of(work,
2429 struct igb_adapter, watchdog_task);
2430 struct e1000_hw *hw = &adapter->hw;
2431 struct net_device *netdev = adapter->netdev;
2432 struct igb_ring *tx_ring = adapter->tx_ring;
2437 link = igb_has_link(adapter);
2438 if ((netif_carrier_ok(netdev)) && link)
2442 if (!netif_carrier_ok(netdev)) {
2444 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2445 &adapter->link_speed,
2446 &adapter->link_duplex);
2448 ctrl = rd32(E1000_CTRL);
2449 /* Links status message must follow this format */
2450 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2451 "Flow Control: %s\n",
2453 adapter->link_speed,
2454 adapter->link_duplex == FULL_DUPLEX ?
2455 "Full Duplex" : "Half Duplex",
2456 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2457 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2458 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2459 E1000_CTRL_TFCE) ? "TX" : "None")));
2461 /* tweak tx_queue_len according to speed/duplex and
2462 * adjust the timeout factor */
2463 netdev->tx_queue_len = adapter->tx_queue_len;
2464 adapter->tx_timeout_factor = 1;
2465 switch (adapter->link_speed) {
2467 netdev->tx_queue_len = 10;
2468 adapter->tx_timeout_factor = 14;
2471 netdev->tx_queue_len = 100;
2472 /* maybe add some timeout factor ? */
2476 netif_carrier_on(netdev);
2477 netif_tx_wake_all_queues(netdev);
2479 /* link state has changed, schedule phy info update */
2480 if (!test_bit(__IGB_DOWN, &adapter->state))
2481 mod_timer(&adapter->phy_info_timer,
2482 round_jiffies(jiffies + 2 * HZ));
2485 if (netif_carrier_ok(netdev)) {
2486 adapter->link_speed = 0;
2487 adapter->link_duplex = 0;
2488 /* Links status message must follow this format */
2489 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2491 netif_carrier_off(netdev);
2492 netif_tx_stop_all_queues(netdev);
2494 /* link state has changed, schedule phy info update */
2495 if (!test_bit(__IGB_DOWN, &adapter->state))
2496 mod_timer(&adapter->phy_info_timer,
2497 round_jiffies(jiffies + 2 * HZ));
2502 igb_update_stats(adapter);
2504 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2505 adapter->tpt_old = adapter->stats.tpt;
2506 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2507 adapter->colc_old = adapter->stats.colc;
2509 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2510 adapter->gorc_old = adapter->stats.gorc;
2511 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2512 adapter->gotc_old = adapter->stats.gotc;
2514 igb_update_adaptive(&adapter->hw);
2516 if (!netif_carrier_ok(netdev)) {
2517 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2518 /* We've lost link, so the controller stops DMA,
2519 * but we've got queued Tx work that's never going
2520 * to get done, so reset controller to flush Tx.
2521 * (Do the reset outside of interrupt context). */
2522 adapter->tx_timeout_count++;
2523 schedule_work(&adapter->reset_task);
2527 /* Cause software interrupt to ensure rx ring is cleaned */
2528 if (adapter->msix_entries) {
2529 for (i = 0; i < adapter->num_rx_queues; i++)
2530 eics |= adapter->rx_ring[i].eims_value;
2531 wr32(E1000_EICS, eics);
2533 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2536 /* Force detection of hung controller every watchdog period */
2537 tx_ring->detect_tx_hung = true;
2539 /* Reset the timer */
2540 if (!test_bit(__IGB_DOWN, &adapter->state))
2541 mod_timer(&adapter->watchdog_timer,
2542 round_jiffies(jiffies + 2 * HZ));
2545 enum latency_range {
2549 latency_invalid = 255
2554 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2556 * Stores a new ITR value based on strictly on packet size. This
2557 * algorithm is less sophisticated than that used in igb_update_itr,
2558 * due to the difficulty of synchronizing statistics across multiple
2559 * receive rings. The divisors and thresholds used by this fuction
2560 * were determined based on theoretical maximum wire speed and testing
2561 * data, in order to minimize response time while increasing bulk
2563 * This functionality is controlled by the InterruptThrottleRate module
2564 * parameter (see igb_param.c)
2565 * NOTE: This function is called only when operating in a multiqueue
2566 * receive environment.
2567 * @rx_ring: pointer to ring
2569 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2571 int new_val = rx_ring->itr_val;
2572 int avg_wire_size = 0;
2573 struct igb_adapter *adapter = rx_ring->adapter;
2575 if (!rx_ring->total_packets)
2576 goto clear_counts; /* no packets, so don't do anything */
2578 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2579 * ints/sec - ITR timer value of 120 ticks.
2581 if (adapter->link_speed != SPEED_1000) {
2585 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2587 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2588 avg_wire_size += 24;
2590 /* Don't starve jumbo frames */
2591 avg_wire_size = min(avg_wire_size, 3000);
2593 /* Give a little boost to mid-size frames */
2594 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2595 new_val = avg_wire_size / 3;
2597 new_val = avg_wire_size / 2;
2600 if (new_val != rx_ring->itr_val) {
2601 rx_ring->itr_val = new_val;
2602 rx_ring->set_itr = 1;
2605 rx_ring->total_bytes = 0;
2606 rx_ring->total_packets = 0;
2610 * igb_update_itr - update the dynamic ITR value based on statistics
2611 * Stores a new ITR value based on packets and byte
2612 * counts during the last interrupt. The advantage of per interrupt
2613 * computation is faster updates and more accurate ITR for the current
2614 * traffic pattern. Constants in this function were computed
2615 * based on theoretical maximum wire speed and thresholds were set based
2616 * on testing data as well as attempting to minimize response time
2617 * while increasing bulk throughput.
2618 * this functionality is controlled by the InterruptThrottleRate module
2619 * parameter (see igb_param.c)
2620 * NOTE: These calculations are only valid when operating in a single-
2621 * queue environment.
2622 * @adapter: pointer to adapter
2623 * @itr_setting: current adapter->itr
2624 * @packets: the number of packets during this measurement interval
2625 * @bytes: the number of bytes during this measurement interval
2627 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2628 int packets, int bytes)
2630 unsigned int retval = itr_setting;
2633 goto update_itr_done;
2635 switch (itr_setting) {
2636 case lowest_latency:
2637 /* handle TSO and jumbo frames */
2638 if (bytes/packets > 8000)
2639 retval = bulk_latency;
2640 else if ((packets < 5) && (bytes > 512))
2641 retval = low_latency;
2643 case low_latency: /* 50 usec aka 20000 ints/s */
2644 if (bytes > 10000) {
2645 /* this if handles the TSO accounting */
2646 if (bytes/packets > 8000) {
2647 retval = bulk_latency;
2648 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2649 retval = bulk_latency;
2650 } else if ((packets > 35)) {
2651 retval = lowest_latency;
2653 } else if (bytes/packets > 2000) {
2654 retval = bulk_latency;
2655 } else if (packets <= 2 && bytes < 512) {
2656 retval = lowest_latency;
2659 case bulk_latency: /* 250 usec aka 4000 ints/s */
2660 if (bytes > 25000) {
2662 retval = low_latency;
2663 } else if (bytes < 1500) {
2664 retval = low_latency;
2673 static void igb_set_itr(struct igb_adapter *adapter)
2676 u32 new_itr = adapter->itr;
2678 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2679 if (adapter->link_speed != SPEED_1000) {
2685 adapter->rx_itr = igb_update_itr(adapter,
2687 adapter->rx_ring->total_packets,
2688 adapter->rx_ring->total_bytes);
2690 if (adapter->rx_ring->buddy) {
2691 adapter->tx_itr = igb_update_itr(adapter,
2693 adapter->tx_ring->total_packets,
2694 adapter->tx_ring->total_bytes);
2695 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2697 current_itr = adapter->rx_itr;
2700 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2701 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2702 current_itr = low_latency;
2704 switch (current_itr) {
2705 /* counts and packets in update_itr are dependent on these numbers */
2706 case lowest_latency:
2710 new_itr = 20000; /* aka hwitr = ~200 */
2720 adapter->rx_ring->total_bytes = 0;
2721 adapter->rx_ring->total_packets = 0;
2722 if (adapter->rx_ring->buddy) {
2723 adapter->rx_ring->buddy->total_bytes = 0;
2724 adapter->rx_ring->buddy->total_packets = 0;
2727 if (new_itr != adapter->itr) {
2728 /* this attempts to bias the interrupt rate towards Bulk
2729 * by adding intermediate steps when interrupt rate is
2731 new_itr = new_itr > adapter->itr ?
2732 min(adapter->itr + (new_itr >> 2), new_itr) :
2734 /* Don't write the value here; it resets the adapter's
2735 * internal timer, and causes us to delay far longer than
2736 * we should between interrupts. Instead, we write the ITR
2737 * value at the beginning of the next interrupt so the timing
2738 * ends up being correct.
2740 adapter->itr = new_itr;
2741 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2742 adapter->rx_ring->set_itr = 1;
2749 #define IGB_TX_FLAGS_CSUM 0x00000001
2750 #define IGB_TX_FLAGS_VLAN 0x00000002
2751 #define IGB_TX_FLAGS_TSO 0x00000004
2752 #define IGB_TX_FLAGS_IPV4 0x00000008
2753 #define IGB_TX_FLAGS_TSTAMP 0x00000010
2754 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2755 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2757 static inline int igb_tso_adv(struct igb_adapter *adapter,
2758 struct igb_ring *tx_ring,
2759 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2761 struct e1000_adv_tx_context_desc *context_desc;
2764 struct igb_buffer *buffer_info;
2765 u32 info = 0, tu_cmd = 0;
2766 u32 mss_l4len_idx, l4len;
2769 if (skb_header_cloned(skb)) {
2770 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2775 l4len = tcp_hdrlen(skb);
2778 if (skb->protocol == htons(ETH_P_IP)) {
2779 struct iphdr *iph = ip_hdr(skb);
2782 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2786 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2787 ipv6_hdr(skb)->payload_len = 0;
2788 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2789 &ipv6_hdr(skb)->daddr,
2793 i = tx_ring->next_to_use;
2795 buffer_info = &tx_ring->buffer_info[i];
2796 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2797 /* VLAN MACLEN IPLEN */
2798 if (tx_flags & IGB_TX_FLAGS_VLAN)
2799 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2800 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2801 *hdr_len += skb_network_offset(skb);
2802 info |= skb_network_header_len(skb);
2803 *hdr_len += skb_network_header_len(skb);
2804 context_desc->vlan_macip_lens = cpu_to_le32(info);
2806 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2807 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2809 if (skb->protocol == htons(ETH_P_IP))
2810 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2811 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2813 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2816 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2817 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2819 /* For 82575, context index must be unique per ring. */
2820 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2821 mss_l4len_idx |= tx_ring->queue_index << 4;
2823 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2824 context_desc->seqnum_seed = 0;
2826 buffer_info->time_stamp = jiffies;
2827 buffer_info->next_to_watch = i;
2828 buffer_info->dma = 0;
2830 if (i == tx_ring->count)
2833 tx_ring->next_to_use = i;
2838 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2839 struct igb_ring *tx_ring,
2840 struct sk_buff *skb, u32 tx_flags)
2842 struct e1000_adv_tx_context_desc *context_desc;
2844 struct igb_buffer *buffer_info;
2845 u32 info = 0, tu_cmd = 0;
2847 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2848 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2849 i = tx_ring->next_to_use;
2850 buffer_info = &tx_ring->buffer_info[i];
2851 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2853 if (tx_flags & IGB_TX_FLAGS_VLAN)
2854 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2855 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2856 if (skb->ip_summed == CHECKSUM_PARTIAL)
2857 info |= skb_network_header_len(skb);
2859 context_desc->vlan_macip_lens = cpu_to_le32(info);
2861 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2863 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2864 switch (skb->protocol) {
2865 case cpu_to_be16(ETH_P_IP):
2866 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2867 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2868 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2870 case cpu_to_be16(ETH_P_IPV6):
2871 /* XXX what about other V6 headers?? */
2872 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2873 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2876 if (unlikely(net_ratelimit()))
2877 dev_warn(&adapter->pdev->dev,
2878 "partial checksum but proto=%x!\n",
2884 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2885 context_desc->seqnum_seed = 0;
2886 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2887 context_desc->mss_l4len_idx =
2888 cpu_to_le32(tx_ring->queue_index << 4);
2890 context_desc->mss_l4len_idx = 0;
2892 buffer_info->time_stamp = jiffies;
2893 buffer_info->next_to_watch = i;
2894 buffer_info->dma = 0;
2897 if (i == tx_ring->count)
2899 tx_ring->next_to_use = i;
2906 #define IGB_MAX_TXD_PWR 16
2907 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2909 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2910 struct igb_ring *tx_ring, struct sk_buff *skb,
2913 struct igb_buffer *buffer_info;
2914 unsigned int len = skb_headlen(skb);
2915 unsigned int count = 0, i;
2918 i = tx_ring->next_to_use;
2920 buffer_info = &tx_ring->buffer_info[i];
2921 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2922 buffer_info->length = len;
2923 /* set time_stamp *before* dma to help avoid a possible race */
2924 buffer_info->time_stamp = jiffies;
2925 buffer_info->next_to_watch = i;
2926 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2930 if (i == tx_ring->count)
2933 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2934 struct skb_frag_struct *frag;
2936 frag = &skb_shinfo(skb)->frags[f];
2939 buffer_info = &tx_ring->buffer_info[i];
2940 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2941 buffer_info->length = len;
2942 buffer_info->time_stamp = jiffies;
2943 buffer_info->next_to_watch = i;
2944 buffer_info->dma = pci_map_page(adapter->pdev,
2952 if (i == tx_ring->count)
2956 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
2957 tx_ring->buffer_info[i].skb = skb;
2958 tx_ring->buffer_info[first].next_to_watch = i;
2963 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2964 struct igb_ring *tx_ring,
2965 int tx_flags, int count, u32 paylen,
2968 union e1000_adv_tx_desc *tx_desc = NULL;
2969 struct igb_buffer *buffer_info;
2970 u32 olinfo_status = 0, cmd_type_len;
2973 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2974 E1000_ADVTXD_DCMD_DEXT);
2976 if (tx_flags & IGB_TX_FLAGS_VLAN)
2977 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2979 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
2980 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
2982 if (tx_flags & IGB_TX_FLAGS_TSO) {
2983 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2985 /* insert tcp checksum */
2986 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2988 /* insert ip checksum */
2989 if (tx_flags & IGB_TX_FLAGS_IPV4)
2990 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2992 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2993 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2996 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2997 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2998 IGB_TX_FLAGS_VLAN)))
2999 olinfo_status |= tx_ring->queue_index << 4;
3001 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3003 i = tx_ring->next_to_use;
3005 buffer_info = &tx_ring->buffer_info[i];
3006 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3007 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3008 tx_desc->read.cmd_type_len =
3009 cpu_to_le32(cmd_type_len | buffer_info->length);
3010 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3012 if (i == tx_ring->count)
3016 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3017 /* Force memory writes to complete before letting h/w
3018 * know there are new descriptors to fetch. (Only
3019 * applicable for weak-ordered memory model archs,
3020 * such as IA-64). */
3023 tx_ring->next_to_use = i;
3024 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3025 /* we need this if more than one processor can write to our tail
3026 * at a time, it syncronizes IO on IA64/Altix systems */
3030 static int __igb_maybe_stop_tx(struct net_device *netdev,
3031 struct igb_ring *tx_ring, int size)
3033 struct igb_adapter *adapter = netdev_priv(netdev);
3035 netif_stop_subqueue(netdev, tx_ring->queue_index);
3037 /* Herbert's original patch had:
3038 * smp_mb__after_netif_stop_queue();
3039 * but since that doesn't exist yet, just open code it. */
3042 /* We need to check again in a case another CPU has just
3043 * made room available. */
3044 if (IGB_DESC_UNUSED(tx_ring) < size)
3048 netif_wake_subqueue(netdev, tx_ring->queue_index);
3049 ++adapter->restart_queue;
3053 static int igb_maybe_stop_tx(struct net_device *netdev,
3054 struct igb_ring *tx_ring, int size)
3056 if (IGB_DESC_UNUSED(tx_ring) >= size)
3058 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3061 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
3063 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3064 struct net_device *netdev,
3065 struct igb_ring *tx_ring)
3067 struct igb_adapter *adapter = netdev_priv(netdev);
3069 unsigned int tx_flags = 0;
3072 union skb_shared_tx *shtx;
3074 if (test_bit(__IGB_DOWN, &adapter->state)) {
3075 dev_kfree_skb_any(skb);
3076 return NETDEV_TX_OK;
3079 if (skb->len <= 0) {
3080 dev_kfree_skb_any(skb);
3081 return NETDEV_TX_OK;
3084 /* need: 1 descriptor per page,
3085 * + 2 desc gap to keep tail from touching head,
3086 * + 1 desc for skb->data,
3087 * + 1 desc for context descriptor,
3088 * otherwise try next time */
3089 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3090 /* this is a hard error */
3091 return NETDEV_TX_BUSY;
3095 * TODO: check that there currently is no other packet with
3096 * time stamping in the queue
3098 * When doing time stamping, keep the connection to the socket
3099 * a while longer: it is still needed by skb_hwtstamp_tx(),
3100 * called either in igb_tx_hwtstamp() or by our caller when
3101 * doing software time stamping.
3104 if (unlikely(shtx->hardware)) {
3105 shtx->in_progress = 1;
3106 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3107 } else if (likely(!shtx->software)) {
3109 * TODO: can this be solved in dev.c:dev_hard_start_xmit()?
3110 * There are probably unmodified driver which do something
3111 * like this and thus don't work in combination with
3112 * SOF_TIMESTAMPING_TX_SOFTWARE.
3117 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3118 tx_flags |= IGB_TX_FLAGS_VLAN;
3119 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3122 if (skb->protocol == htons(ETH_P_IP))
3123 tx_flags |= IGB_TX_FLAGS_IPV4;
3125 first = tx_ring->next_to_use;
3126 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3130 dev_kfree_skb_any(skb);
3131 return NETDEV_TX_OK;
3135 tx_flags |= IGB_TX_FLAGS_TSO;
3136 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3137 if (skb->ip_summed == CHECKSUM_PARTIAL)
3138 tx_flags |= IGB_TX_FLAGS_CSUM;
3140 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3141 igb_tx_map_adv(adapter, tx_ring, skb, first),
3144 netdev->trans_start = jiffies;
3146 /* Make sure there is space in the ring for the next send. */
3147 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3149 return NETDEV_TX_OK;
3152 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3154 struct igb_adapter *adapter = netdev_priv(netdev);
3155 struct igb_ring *tx_ring;
3158 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3159 tx_ring = adapter->multi_tx_table[r_idx];
3161 /* This goes back to the question of how to logically map a tx queue
3162 * to a flow. Right now, performance is impacted slightly negatively
3163 * if using multiple tx queues. If the stack breaks away from a
3164 * single qdisc implementation, we can look at this again. */
3165 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3169 * igb_tx_timeout - Respond to a Tx Hang
3170 * @netdev: network interface device structure
3172 static void igb_tx_timeout(struct net_device *netdev)
3174 struct igb_adapter *adapter = netdev_priv(netdev);
3175 struct e1000_hw *hw = &adapter->hw;
3177 /* Do the reset outside of interrupt context */
3178 adapter->tx_timeout_count++;
3179 schedule_work(&adapter->reset_task);
3181 (adapter->eims_enable_mask & ~adapter->eims_other));
3184 static void igb_reset_task(struct work_struct *work)
3186 struct igb_adapter *adapter;
3187 adapter = container_of(work, struct igb_adapter, reset_task);
3189 igb_reinit_locked(adapter);
3193 * igb_get_stats - Get System Network Statistics
3194 * @netdev: network interface device structure
3196 * Returns the address of the device statistics structure.
3197 * The statistics are actually updated from the timer callback.
3199 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3201 struct igb_adapter *adapter = netdev_priv(netdev);
3203 /* only return the current stats */
3204 return &adapter->net_stats;
3208 * igb_change_mtu - Change the Maximum Transfer Unit
3209 * @netdev: network interface device structure
3210 * @new_mtu: new value for maximum frame size
3212 * Returns 0 on success, negative on failure
3214 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3216 struct igb_adapter *adapter = netdev_priv(netdev);
3217 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3219 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3220 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3221 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3225 #define MAX_STD_JUMBO_FRAME_SIZE 9234
3226 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3227 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3231 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3234 /* igb_down has a dependency on max_frame_size */
3235 adapter->max_frame_size = max_frame;
3236 if (netif_running(netdev))
3239 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3240 * means we reserve 2 more, this pushes us to allocate from the next
3242 * i.e. RXBUFFER_2048 --> size-4096 slab
3245 if (max_frame <= IGB_RXBUFFER_256)
3246 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3247 else if (max_frame <= IGB_RXBUFFER_512)
3248 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3249 else if (max_frame <= IGB_RXBUFFER_1024)
3250 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3251 else if (max_frame <= IGB_RXBUFFER_2048)
3252 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3254 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3255 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3257 adapter->rx_buffer_len = PAGE_SIZE / 2;
3259 /* adjust allocation if LPE protects us, and we aren't using SBP */
3260 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3261 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3262 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3264 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3265 netdev->mtu, new_mtu);
3266 netdev->mtu = new_mtu;
3268 if (netif_running(netdev))
3273 clear_bit(__IGB_RESETTING, &adapter->state);
3279 * igb_update_stats - Update the board statistics counters
3280 * @adapter: board private structure
3283 void igb_update_stats(struct igb_adapter *adapter)
3285 struct e1000_hw *hw = &adapter->hw;
3286 struct pci_dev *pdev = adapter->pdev;
3289 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3292 * Prevent stats update while adapter is being reset, or if the pci
3293 * connection is down.
3295 if (adapter->link_speed == 0)
3297 if (pci_channel_offline(pdev))
3300 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3301 adapter->stats.gprc += rd32(E1000_GPRC);
3302 adapter->stats.gorc += rd32(E1000_GORCL);
3303 rd32(E1000_GORCH); /* clear GORCL */
3304 adapter->stats.bprc += rd32(E1000_BPRC);
3305 adapter->stats.mprc += rd32(E1000_MPRC);
3306 adapter->stats.roc += rd32(E1000_ROC);
3308 adapter->stats.prc64 += rd32(E1000_PRC64);
3309 adapter->stats.prc127 += rd32(E1000_PRC127);
3310 adapter->stats.prc255 += rd32(E1000_PRC255);
3311 adapter->stats.prc511 += rd32(E1000_PRC511);
3312 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3313 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3314 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3315 adapter->stats.sec += rd32(E1000_SEC);
3317 adapter->stats.mpc += rd32(E1000_MPC);
3318 adapter->stats.scc += rd32(E1000_SCC);
3319 adapter->stats.ecol += rd32(E1000_ECOL);
3320 adapter->stats.mcc += rd32(E1000_MCC);
3321 adapter->stats.latecol += rd32(E1000_LATECOL);
3322 adapter->stats.dc += rd32(E1000_DC);
3323 adapter->stats.rlec += rd32(E1000_RLEC);
3324 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3325 adapter->stats.xontxc += rd32(E1000_XONTXC);
3326 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3327 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3328 adapter->stats.fcruc += rd32(E1000_FCRUC);
3329 adapter->stats.gptc += rd32(E1000_GPTC);
3330 adapter->stats.gotc += rd32(E1000_GOTCL);
3331 rd32(E1000_GOTCH); /* clear GOTCL */
3332 adapter->stats.rnbc += rd32(E1000_RNBC);
3333 adapter->stats.ruc += rd32(E1000_RUC);
3334 adapter->stats.rfc += rd32(E1000_RFC);
3335 adapter->stats.rjc += rd32(E1000_RJC);
3336 adapter->stats.tor += rd32(E1000_TORH);
3337 adapter->stats.tot += rd32(E1000_TOTH);
3338 adapter->stats.tpr += rd32(E1000_TPR);
3340 adapter->stats.ptc64 += rd32(E1000_PTC64);
3341 adapter->stats.ptc127 += rd32(E1000_PTC127);
3342 adapter->stats.ptc255 += rd32(E1000_PTC255);
3343 adapter->stats.ptc511 += rd32(E1000_PTC511);
3344 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3345 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3347 adapter->stats.mptc += rd32(E1000_MPTC);
3348 adapter->stats.bptc += rd32(E1000_BPTC);
3350 /* used for adaptive IFS */
3352 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3353 adapter->stats.tpt += hw->mac.tx_packet_delta;
3354 hw->mac.collision_delta = rd32(E1000_COLC);
3355 adapter->stats.colc += hw->mac.collision_delta;
3357 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3358 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3359 adapter->stats.tncrs += rd32(E1000_TNCRS);
3360 adapter->stats.tsctc += rd32(E1000_TSCTC);
3361 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3363 adapter->stats.iac += rd32(E1000_IAC);
3364 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3365 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3366 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3367 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3368 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3369 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3370 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3371 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3373 /* Fill out the OS statistics structure */
3374 adapter->net_stats.multicast = adapter->stats.mprc;
3375 adapter->net_stats.collisions = adapter->stats.colc;
3379 /* RLEC on some newer hardware can be incorrect so build
3380 * our own version based on RUC and ROC */
3381 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3382 adapter->stats.crcerrs + adapter->stats.algnerrc +
3383 adapter->stats.ruc + adapter->stats.roc +
3384 adapter->stats.cexterr;
3385 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3387 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3388 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3389 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3392 adapter->net_stats.tx_errors = adapter->stats.ecol +
3393 adapter->stats.latecol;
3394 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3395 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3396 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3398 /* Tx Dropped needs to be maintained elsewhere */
3401 if (hw->phy.media_type == e1000_media_type_copper) {
3402 if ((adapter->link_speed == SPEED_1000) &&
3403 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3404 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3405 adapter->phy_stats.idle_errors += phy_tmp;
3409 /* Management Stats */
3410 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3411 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3412 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3415 static irqreturn_t igb_msix_other(int irq, void *data)
3417 struct net_device *netdev = data;
3418 struct igb_adapter *adapter = netdev_priv(netdev);
3419 struct e1000_hw *hw = &adapter->hw;
3420 u32 icr = rd32(E1000_ICR);
3422 /* reading ICR causes bit 31 of EICR to be cleared */
3424 if(icr & E1000_ICR_DOUTSYNC) {
3425 /* HW is reporting DMA is out of sync */
3426 adapter->stats.doosync++;
3428 if (!(icr & E1000_ICR_LSC))
3429 goto no_link_interrupt;
3430 hw->mac.get_link_status = 1;
3431 /* guard against interrupt when we're going down */
3432 if (!test_bit(__IGB_DOWN, &adapter->state))
3433 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3436 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
3437 wr32(E1000_EIMS, adapter->eims_other);
3442 static irqreturn_t igb_msix_tx(int irq, void *data)
3444 struct igb_ring *tx_ring = data;
3445 struct igb_adapter *adapter = tx_ring->adapter;
3446 struct e1000_hw *hw = &adapter->hw;
3448 #ifdef CONFIG_IGB_DCA
3449 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3450 igb_update_tx_dca(tx_ring);
3453 tx_ring->total_bytes = 0;
3454 tx_ring->total_packets = 0;
3456 /* auto mask will automatically reenable the interrupt when we write
3458 if (!igb_clean_tx_irq(tx_ring))
3459 /* Ring was not completely cleaned, so fire another interrupt */
3460 wr32(E1000_EICS, tx_ring->eims_value);
3462 wr32(E1000_EIMS, tx_ring->eims_value);
3467 static void igb_write_itr(struct igb_ring *ring)
3469 struct e1000_hw *hw = &ring->adapter->hw;
3470 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3471 switch (hw->mac.type) {
3473 wr32(ring->itr_register, ring->itr_val |
3477 wr32(ring->itr_register, ring->itr_val |
3478 (ring->itr_val << 16));
3485 static irqreturn_t igb_msix_rx(int irq, void *data)
3487 struct igb_ring *rx_ring = data;
3489 /* Write the ITR value calculated at the end of the
3490 * previous interrupt.
3493 igb_write_itr(rx_ring);
3495 if (napi_schedule_prep(&rx_ring->napi))
3496 __napi_schedule(&rx_ring->napi);
3498 #ifdef CONFIG_IGB_DCA
3499 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3500 igb_update_rx_dca(rx_ring);
3505 #ifdef CONFIG_IGB_DCA
3506 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3509 struct igb_adapter *adapter = rx_ring->adapter;
3510 struct e1000_hw *hw = &adapter->hw;
3511 int cpu = get_cpu();
3512 int q = rx_ring->reg_idx;
3514 if (rx_ring->cpu != cpu) {
3515 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3516 if (hw->mac.type == e1000_82576) {
3517 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3518 dca_rxctrl |= dca_get_tag(cpu) <<
3519 E1000_DCA_RXCTRL_CPUID_SHIFT;
3521 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3522 dca_rxctrl |= dca_get_tag(cpu);
3524 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3525 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3526 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3527 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3533 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3536 struct igb_adapter *adapter = tx_ring->adapter;
3537 struct e1000_hw *hw = &adapter->hw;
3538 int cpu = get_cpu();
3539 int q = tx_ring->reg_idx;
3541 if (tx_ring->cpu != cpu) {
3542 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3543 if (hw->mac.type == e1000_82576) {
3544 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3545 dca_txctrl |= dca_get_tag(cpu) <<
3546 E1000_DCA_TXCTRL_CPUID_SHIFT;
3548 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3549 dca_txctrl |= dca_get_tag(cpu);
3551 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3552 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3558 static void igb_setup_dca(struct igb_adapter *adapter)
3562 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3565 for (i = 0; i < adapter->num_tx_queues; i++) {
3566 adapter->tx_ring[i].cpu = -1;
3567 igb_update_tx_dca(&adapter->tx_ring[i]);
3569 for (i = 0; i < adapter->num_rx_queues; i++) {
3570 adapter->rx_ring[i].cpu = -1;
3571 igb_update_rx_dca(&adapter->rx_ring[i]);
3575 static int __igb_notify_dca(struct device *dev, void *data)
3577 struct net_device *netdev = dev_get_drvdata(dev);
3578 struct igb_adapter *adapter = netdev_priv(netdev);
3579 struct e1000_hw *hw = &adapter->hw;
3580 unsigned long event = *(unsigned long *)data;
3583 case DCA_PROVIDER_ADD:
3584 /* if already enabled, don't do it again */
3585 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3587 /* Always use CB2 mode, difference is masked
3588 * in the CB driver. */
3589 wr32(E1000_DCA_CTRL, 2);
3590 if (dca_add_requester(dev) == 0) {
3591 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3592 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3593 igb_setup_dca(adapter);
3596 /* Fall Through since DCA is disabled. */
3597 case DCA_PROVIDER_REMOVE:
3598 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3599 /* without this a class_device is left
3600 * hanging around in the sysfs model */
3601 dca_remove_requester(dev);
3602 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3603 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3604 wr32(E1000_DCA_CTRL, 1);
3612 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3617 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3620 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3622 #endif /* CONFIG_IGB_DCA */
3625 * igb_intr_msi - Interrupt Handler
3626 * @irq: interrupt number
3627 * @data: pointer to a network interface device structure
3629 static irqreturn_t igb_intr_msi(int irq, void *data)
3631 struct net_device *netdev = data;
3632 struct igb_adapter *adapter = netdev_priv(netdev);
3633 struct e1000_hw *hw = &adapter->hw;
3634 /* read ICR disables interrupts using IAM */
3635 u32 icr = rd32(E1000_ICR);
3637 igb_write_itr(adapter->rx_ring);
3639 if(icr & E1000_ICR_DOUTSYNC) {
3640 /* HW is reporting DMA is out of sync */
3641 adapter->stats.doosync++;
3644 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3645 hw->mac.get_link_status = 1;
3646 if (!test_bit(__IGB_DOWN, &adapter->state))
3647 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3650 napi_schedule(&adapter->rx_ring[0].napi);
3656 * igb_intr - Legacy Interrupt Handler
3657 * @irq: interrupt number
3658 * @data: pointer to a network interface device structure
3660 static irqreturn_t igb_intr(int irq, void *data)
3662 struct net_device *netdev = data;
3663 struct igb_adapter *adapter = netdev_priv(netdev);
3664 struct e1000_hw *hw = &adapter->hw;
3665 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3666 * need for the IMC write */
3667 u32 icr = rd32(E1000_ICR);
3669 return IRQ_NONE; /* Not our interrupt */
3671 igb_write_itr(adapter->rx_ring);
3673 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3674 * not set, then the adapter didn't send an interrupt */
3675 if (!(icr & E1000_ICR_INT_ASSERTED))
3678 if(icr & E1000_ICR_DOUTSYNC) {
3679 /* HW is reporting DMA is out of sync */
3680 adapter->stats.doosync++;
3683 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3684 hw->mac.get_link_status = 1;
3685 /* guard against interrupt when we're going down */
3686 if (!test_bit(__IGB_DOWN, &adapter->state))
3687 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3690 napi_schedule(&adapter->rx_ring[0].napi);
3696 * igb_poll - NAPI Rx polling callback
3697 * @napi: napi polling structure
3698 * @budget: count of how many packets we should handle
3700 static int igb_poll(struct napi_struct *napi, int budget)
3702 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3703 struct igb_adapter *adapter = rx_ring->adapter;
3704 struct net_device *netdev = adapter->netdev;
3705 int tx_clean_complete, work_done = 0;
3707 /* this poll routine only supports one tx and one rx queue */
3708 #ifdef CONFIG_IGB_DCA
3709 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3710 igb_update_tx_dca(&adapter->tx_ring[0]);
3712 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3714 #ifdef CONFIG_IGB_DCA
3715 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3716 igb_update_rx_dca(&adapter->rx_ring[0]);
3718 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3720 /* If no Tx and not enough Rx work done, exit the polling mode */
3721 if ((tx_clean_complete && (work_done < budget)) ||
3722 !netif_running(netdev)) {
3723 if (adapter->itr_setting & 3)
3724 igb_set_itr(adapter);
3725 napi_complete(napi);
3726 if (!test_bit(__IGB_DOWN, &adapter->state))
3727 igb_irq_enable(adapter);
3734 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3736 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3737 struct igb_adapter *adapter = rx_ring->adapter;
3738 struct e1000_hw *hw = &adapter->hw;
3739 struct net_device *netdev = adapter->netdev;
3742 #ifdef CONFIG_IGB_DCA
3743 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3744 igb_update_rx_dca(rx_ring);
3746 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3748 /* If not enough Rx work done, exit the polling mode */
3749 if ((work_done == 0) || !netif_running(netdev)) {
3750 napi_complete(napi);
3752 if (adapter->itr_setting & 3) {
3753 if (adapter->num_rx_queues == 1)
3754 igb_set_itr(adapter);
3756 igb_update_ring_itr(rx_ring);
3758 if (!test_bit(__IGB_DOWN, &adapter->state))
3759 wr32(E1000_EIMS, rx_ring->eims_value);
3768 * igb_hwtstamp - utility function which checks for TX time stamp
3769 * @adapter: board private structure
3770 * @skb: packet that was just sent
3772 * If we were asked to do hardware stamping and such a time stamp is
3773 * available, then it must have been for this skb here because we only
3774 * allow only one such packet into the queue.
3776 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
3778 union skb_shared_tx *shtx = skb_tx(skb);
3779 struct e1000_hw *hw = &adapter->hw;
3781 if (unlikely(shtx->hardware)) {
3782 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
3784 u64 regval = rd32(E1000_TXSTMPL);
3786 struct skb_shared_hwtstamps shhwtstamps;
3788 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3789 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
3790 ns = timecounter_cyc2time(&adapter->clock,
3792 timecompare_update(&adapter->compare, ns);
3793 shhwtstamps.hwtstamp = ns_to_ktime(ns);
3794 shhwtstamps.syststamp =
3795 timecompare_transform(&adapter->compare, ns);
3796 skb_tstamp_tx(skb, &shhwtstamps);
3799 /* delayed orphaning: skb_tstamp_tx() needs the socket */
3805 * igb_clean_tx_irq - Reclaim resources after transmit completes
3806 * @adapter: board private structure
3807 * returns true if ring is completely cleaned
3809 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3811 struct igb_adapter *adapter = tx_ring->adapter;
3812 struct net_device *netdev = adapter->netdev;
3813 struct e1000_hw *hw = &adapter->hw;
3814 struct igb_buffer *buffer_info;
3815 struct sk_buff *skb;
3816 union e1000_adv_tx_desc *tx_desc, *eop_desc;
3817 unsigned int total_bytes = 0, total_packets = 0;
3818 unsigned int i, eop, count = 0;
3819 bool cleaned = false;
3821 i = tx_ring->next_to_clean;
3822 eop = tx_ring->buffer_info[i].next_to_watch;
3823 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3825 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3826 (count < tx_ring->count)) {
3827 for (cleaned = false; !cleaned; count++) {
3828 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3829 buffer_info = &tx_ring->buffer_info[i];
3830 cleaned = (i == eop);
3831 skb = buffer_info->skb;
3834 unsigned int segs, bytecount;
3835 /* gso_segs is currently only valid for tcp */
3836 segs = skb_shinfo(skb)->gso_segs ?: 1;
3837 /* multiply data chunks by size of headers */
3838 bytecount = ((segs - 1) * skb_headlen(skb)) +
3840 total_packets += segs;
3841 total_bytes += bytecount;
3843 igb_tx_hwtstamp(adapter, skb);
3846 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3847 tx_desc->wb.status = 0;
3850 if (i == tx_ring->count)
3853 eop = tx_ring->buffer_info[i].next_to_watch;
3854 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3857 tx_ring->next_to_clean = i;
3859 if (unlikely(count &&
3860 netif_carrier_ok(netdev) &&
3861 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3862 /* Make sure that anybody stopping the queue after this
3863 * sees the new next_to_clean.
3866 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3867 !(test_bit(__IGB_DOWN, &adapter->state))) {
3868 netif_wake_subqueue(netdev, tx_ring->queue_index);
3869 ++adapter->restart_queue;
3873 if (tx_ring->detect_tx_hung) {
3874 /* Detect a transmit hang in hardware, this serializes the
3875 * check with the clearing of time_stamp and movement of i */
3876 tx_ring->detect_tx_hung = false;
3877 if (tx_ring->buffer_info[i].time_stamp &&
3878 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3879 (adapter->tx_timeout_factor * HZ))
3880 && !(rd32(E1000_STATUS) &
3881 E1000_STATUS_TXOFF)) {
3883 /* detected Tx unit hang */
3884 dev_err(&adapter->pdev->dev,
3885 "Detected Tx Unit Hang\n"
3889 " next_to_use <%x>\n"
3890 " next_to_clean <%x>\n"
3891 "buffer_info[next_to_clean]\n"
3892 " time_stamp <%lx>\n"
3893 " next_to_watch <%x>\n"
3895 " desc.status <%x>\n",
3896 tx_ring->queue_index,
3897 readl(adapter->hw.hw_addr + tx_ring->head),
3898 readl(adapter->hw.hw_addr + tx_ring->tail),
3899 tx_ring->next_to_use,
3900 tx_ring->next_to_clean,
3901 tx_ring->buffer_info[i].time_stamp,
3904 eop_desc->wb.status);
3905 netif_stop_subqueue(netdev, tx_ring->queue_index);
3908 tx_ring->total_bytes += total_bytes;
3909 tx_ring->total_packets += total_packets;
3910 tx_ring->tx_stats.bytes += total_bytes;
3911 tx_ring->tx_stats.packets += total_packets;
3912 adapter->net_stats.tx_bytes += total_bytes;
3913 adapter->net_stats.tx_packets += total_packets;
3914 return (count < tx_ring->count);
3918 * igb_receive_skb - helper function to handle rx indications
3919 * @ring: pointer to receive ring receving this packet
3920 * @status: descriptor status field as written by hardware
3921 * @rx_desc: receive descriptor containing vlan and type information.
3922 * @skb: pointer to sk_buff to be indicated to stack
3924 static void igb_receive_skb(struct igb_ring *ring, u8 status,
3925 union e1000_adv_rx_desc * rx_desc,
3926 struct sk_buff *skb)
3928 struct igb_adapter * adapter = ring->adapter;
3929 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3931 skb_record_rx_queue(skb, ring->queue_index);
3932 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
3934 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3935 le16_to_cpu(rx_desc->wb.upper.vlan),
3938 napi_gro_receive(&ring->napi, skb);
3941 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3942 le16_to_cpu(rx_desc->wb.upper.vlan));
3944 netif_receive_skb(skb);
3948 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3949 u32 status_err, struct sk_buff *skb)
3951 skb->ip_summed = CHECKSUM_NONE;
3953 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3954 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3956 /* TCP/UDP checksum error bit is set */
3958 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3959 /* let the stack verify checksum errors */
3960 adapter->hw_csum_err++;
3963 /* It must be a TCP or UDP packet with a valid checksum */
3964 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3965 skb->ip_summed = CHECKSUM_UNNECESSARY;
3967 adapter->hw_csum_good++;
3970 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3971 int *work_done, int budget)
3973 struct igb_adapter *adapter = rx_ring->adapter;
3974 struct net_device *netdev = adapter->netdev;
3975 struct e1000_hw *hw = &adapter->hw;
3976 struct pci_dev *pdev = adapter->pdev;
3977 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3978 struct igb_buffer *buffer_info , *next_buffer;
3979 struct sk_buff *skb;
3980 bool cleaned = false;
3981 int cleaned_count = 0;
3982 unsigned int total_bytes = 0, total_packets = 0;
3984 u32 length, hlen, staterr;
3986 i = rx_ring->next_to_clean;
3987 buffer_info = &rx_ring->buffer_info[i];
3988 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3989 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3991 while (staterr & E1000_RXD_STAT_DD) {
3992 if (*work_done >= budget)
3996 skb = buffer_info->skb;
3997 prefetch(skb->data - NET_IP_ALIGN);
3998 buffer_info->skb = NULL;
4001 if (i == rx_ring->count)
4003 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4005 next_buffer = &rx_ring->buffer_info[i];
4007 length = le16_to_cpu(rx_desc->wb.upper.length);
4011 if (!adapter->rx_ps_hdr_size) {
4012 pci_unmap_single(pdev, buffer_info->dma,
4013 adapter->rx_buffer_len +
4015 PCI_DMA_FROMDEVICE);
4016 skb_put(skb, length);
4020 /* HW will not DMA in data larger than the given buffer, even
4021 * if it parses the (NFS, of course) header to be larger. In
4022 * that case, it fills the header buffer and spills the rest
4025 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4026 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4027 if (hlen > adapter->rx_ps_hdr_size)
4028 hlen = adapter->rx_ps_hdr_size;
4030 if (!skb_shinfo(skb)->nr_frags) {
4031 pci_unmap_single(pdev, buffer_info->dma,
4032 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4033 PCI_DMA_FROMDEVICE);
4038 pci_unmap_page(pdev, buffer_info->page_dma,
4039 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4040 buffer_info->page_dma = 0;
4042 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4044 buffer_info->page_offset,
4047 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4048 (page_count(buffer_info->page) != 1))
4049 buffer_info->page = NULL;
4051 get_page(buffer_info->page);
4054 skb->data_len += length;
4056 skb->truesize += length;
4059 if (!(staterr & E1000_RXD_STAT_EOP)) {
4060 buffer_info->skb = next_buffer->skb;
4061 buffer_info->dma = next_buffer->dma;
4062 next_buffer->skb = skb;
4063 next_buffer->dma = 0;
4068 * If this bit is set, then the RX registers contain
4069 * the time stamp. No other packet will be time
4070 * stamped until we read these registers, so read the
4071 * registers to make them available again. Because
4072 * only one packet can be time stamped at a time, we
4073 * know that the register values must belong to this
4074 * one here and therefore we don't need to compare
4075 * any of the additional attributes stored for it.
4077 * If nothing went wrong, then it should have a
4078 * skb_shared_tx that we can turn into a
4079 * skb_shared_hwtstamps.
4081 * TODO: can time stamping be triggered (thus locking
4082 * the registers) without the packet reaching this point
4083 * here? In that case RX time stamping would get stuck.
4085 * TODO: in "time stamp all packets" mode this bit is
4086 * not set. Need a global flag for this mode and then
4087 * always read the registers. Cannot be done without
4090 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4093 struct skb_shared_hwtstamps *shhwtstamps =
4096 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4097 "igb: no RX time stamp available for time stamped packet");
4098 regval = rd32(E1000_RXSTMPL);
4099 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4100 ns = timecounter_cyc2time(&adapter->clock, regval);
4101 timecompare_update(&adapter->compare, ns);
4102 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4103 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4104 shhwtstamps->syststamp =
4105 timecompare_transform(&adapter->compare, ns);
4108 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4109 dev_kfree_skb_irq(skb);
4113 total_bytes += skb->len;
4116 igb_rx_checksum_adv(adapter, staterr, skb);
4118 skb->protocol = eth_type_trans(skb, netdev);
4120 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4123 rx_desc->wb.upper.status_error = 0;
4125 /* return some buffers to hardware, one at a time is too slow */
4126 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4127 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4131 /* use prefetched values */
4133 buffer_info = next_buffer;
4134 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4137 rx_ring->next_to_clean = i;
4138 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4141 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4143 rx_ring->total_packets += total_packets;
4144 rx_ring->total_bytes += total_bytes;
4145 rx_ring->rx_stats.packets += total_packets;
4146 rx_ring->rx_stats.bytes += total_bytes;
4147 adapter->net_stats.rx_bytes += total_bytes;
4148 adapter->net_stats.rx_packets += total_packets;
4153 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4154 * @adapter: address of board private structure
4156 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4159 struct igb_adapter *adapter = rx_ring->adapter;
4160 struct net_device *netdev = adapter->netdev;
4161 struct pci_dev *pdev = adapter->pdev;
4162 union e1000_adv_rx_desc *rx_desc;
4163 struct igb_buffer *buffer_info;
4164 struct sk_buff *skb;
4168 i = rx_ring->next_to_use;
4169 buffer_info = &rx_ring->buffer_info[i];
4171 if (adapter->rx_ps_hdr_size)
4172 bufsz = adapter->rx_ps_hdr_size;
4174 bufsz = adapter->rx_buffer_len;
4175 bufsz += NET_IP_ALIGN;
4177 while (cleaned_count--) {
4178 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4180 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4181 if (!buffer_info->page) {
4182 buffer_info->page = alloc_page(GFP_ATOMIC);
4183 if (!buffer_info->page) {
4184 adapter->alloc_rx_buff_failed++;
4187 buffer_info->page_offset = 0;
4189 buffer_info->page_offset ^= PAGE_SIZE / 2;
4191 buffer_info->page_dma =
4192 pci_map_page(pdev, buffer_info->page,
4193 buffer_info->page_offset,
4195 PCI_DMA_FROMDEVICE);
4198 if (!buffer_info->skb) {
4199 skb = netdev_alloc_skb(netdev, bufsz);
4201 adapter->alloc_rx_buff_failed++;
4205 /* Make buffer alignment 2 beyond a 16 byte boundary
4206 * this will result in a 16 byte aligned IP header after
4207 * the 14 byte MAC header is removed
4209 skb_reserve(skb, NET_IP_ALIGN);
4211 buffer_info->skb = skb;
4212 buffer_info->dma = pci_map_single(pdev, skb->data,
4214 PCI_DMA_FROMDEVICE);
4216 /* Refresh the desc even if buffer_addrs didn't change because
4217 * each write-back erases this info. */
4218 if (adapter->rx_ps_hdr_size) {
4219 rx_desc->read.pkt_addr =
4220 cpu_to_le64(buffer_info->page_dma);
4221 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4223 rx_desc->read.pkt_addr =
4224 cpu_to_le64(buffer_info->dma);
4225 rx_desc->read.hdr_addr = 0;
4229 if (i == rx_ring->count)
4231 buffer_info = &rx_ring->buffer_info[i];
4235 if (rx_ring->next_to_use != i) {
4236 rx_ring->next_to_use = i;
4238 i = (rx_ring->count - 1);
4242 /* Force memory writes to complete before letting h/w
4243 * know there are new descriptors to fetch. (Only
4244 * applicable for weak-ordered memory model archs,
4245 * such as IA-64). */
4247 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4257 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4259 struct igb_adapter *adapter = netdev_priv(netdev);
4260 struct mii_ioctl_data *data = if_mii(ifr);
4262 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4267 data->phy_id = adapter->hw.phy.addr;
4270 if (!capable(CAP_NET_ADMIN))
4272 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4284 * igb_hwtstamp_ioctl - control hardware time stamping
4289 * Outgoing time stamping can be enabled and disabled. Play nice and
4290 * disable it when requested, although it shouldn't case any overhead
4291 * when no packet needs it. At most one packet in the queue may be
4292 * marked for time stamping, otherwise it would be impossible to tell
4293 * for sure to which packet the hardware time stamp belongs.
4295 * Incoming time stamping has to be configured via the hardware
4296 * filters. Not all combinations are supported, in particular event
4297 * type has to be specified. Matching the kind of event packet is
4298 * not supported, with the exception of "all V2 events regardless of
4302 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4303 struct ifreq *ifr, int cmd)
4305 struct igb_adapter *adapter = netdev_priv(netdev);
4306 struct e1000_hw *hw = &adapter->hw;
4307 struct hwtstamp_config config;
4308 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4309 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4310 u32 tsync_rx_ctl_type = 0;
4311 u32 tsync_rx_cfg = 0;
4314 short port = 319; /* PTP */
4317 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4320 /* reserved for future extensions */
4324 switch (config.tx_type) {
4325 case HWTSTAMP_TX_OFF:
4326 tsync_tx_ctl_bit = 0;
4328 case HWTSTAMP_TX_ON:
4329 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4335 switch (config.rx_filter) {
4336 case HWTSTAMP_FILTER_NONE:
4337 tsync_rx_ctl_bit = 0;
4339 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4340 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4341 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4342 case HWTSTAMP_FILTER_ALL:
4344 * register TSYNCRXCFG must be set, therefore it is not
4345 * possible to time stamp both Sync and Delay_Req messages
4346 * => fall back to time stamping all packets
4348 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4349 config.rx_filter = HWTSTAMP_FILTER_ALL;
4351 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4352 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4353 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4356 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4357 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4358 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4361 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4362 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4363 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4364 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4367 config.rx_filter = HWTSTAMP_FILTER_SOME;
4369 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4370 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4371 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4372 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4375 config.rx_filter = HWTSTAMP_FILTER_SOME;
4377 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4378 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4379 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4380 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4381 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4388 /* enable/disable TX */
4389 regval = rd32(E1000_TSYNCTXCTL);
4390 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4391 wr32(E1000_TSYNCTXCTL, regval);
4393 /* enable/disable RX, define which PTP packets are time stamped */
4394 regval = rd32(E1000_TSYNCRXCTL);
4395 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4396 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4397 wr32(E1000_TSYNCRXCTL, regval);
4398 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4401 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4402 * (Ethertype to filter on)
4403 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4404 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4406 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4408 /* L4 Queue Filter[0]: only filter by source and destination port */
4409 wr32(E1000_SPQF0, htons(port));
4410 wr32(E1000_IMIREXT(0), is_l4 ?
4411 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4412 wr32(E1000_IMIR(0), is_l4 ?
4414 | (0<<16) /* immediate interrupt disabled */
4415 | 0 /* (1<<17) bit cleared: do not bypass
4416 destination port check */)
4418 wr32(E1000_FTQF0, is_l4 ?
4420 | (1<<15) /* VF not compared */
4421 | (1<<27) /* Enable Timestamping */
4422 | (7<<28) /* only source port filter enabled,
4423 source/target address and protocol
4425 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4430 adapter->hwtstamp_config = config;
4432 /* clear TX/RX time stamp registers, just to be sure */
4433 regval = rd32(E1000_TXSTMPH);
4434 regval = rd32(E1000_RXSTMPH);
4436 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4446 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4452 return igb_mii_ioctl(netdev, ifr, cmd);
4454 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4460 static void igb_vlan_rx_register(struct net_device *netdev,
4461 struct vlan_group *grp)
4463 struct igb_adapter *adapter = netdev_priv(netdev);
4464 struct e1000_hw *hw = &adapter->hw;
4467 igb_irq_disable(adapter);
4468 adapter->vlgrp = grp;
4471 /* enable VLAN tag insert/strip */
4472 ctrl = rd32(E1000_CTRL);
4473 ctrl |= E1000_CTRL_VME;
4474 wr32(E1000_CTRL, ctrl);
4476 /* enable VLAN receive filtering */
4477 rctl = rd32(E1000_RCTL);
4478 rctl &= ~E1000_RCTL_CFIEN;
4479 wr32(E1000_RCTL, rctl);
4480 igb_update_mng_vlan(adapter);
4482 adapter->max_frame_size + VLAN_TAG_SIZE);
4484 /* disable VLAN tag insert/strip */
4485 ctrl = rd32(E1000_CTRL);
4486 ctrl &= ~E1000_CTRL_VME;
4487 wr32(E1000_CTRL, ctrl);
4489 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4490 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4491 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4494 adapter->max_frame_size);
4497 if (!test_bit(__IGB_DOWN, &adapter->state))
4498 igb_irq_enable(adapter);
4501 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4503 struct igb_adapter *adapter = netdev_priv(netdev);
4504 struct e1000_hw *hw = &adapter->hw;
4507 if ((hw->mng_cookie.status &
4508 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4509 (vid == adapter->mng_vlan_id))
4511 /* add VID to filter table */
4512 index = (vid >> 5) & 0x7F;
4513 vfta = array_rd32(E1000_VFTA, index);
4514 vfta |= (1 << (vid & 0x1F));
4515 igb_write_vfta(&adapter->hw, index, vfta);
4518 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4520 struct igb_adapter *adapter = netdev_priv(netdev);
4521 struct e1000_hw *hw = &adapter->hw;
4524 igb_irq_disable(adapter);
4525 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4527 if (!test_bit(__IGB_DOWN, &adapter->state))
4528 igb_irq_enable(adapter);
4530 if ((adapter->hw.mng_cookie.status &
4531 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4532 (vid == adapter->mng_vlan_id)) {
4533 /* release control to f/w */
4534 igb_release_hw_control(adapter);
4538 /* remove VID from filter table */
4539 index = (vid >> 5) & 0x7F;
4540 vfta = array_rd32(E1000_VFTA, index);
4541 vfta &= ~(1 << (vid & 0x1F));
4542 igb_write_vfta(&adapter->hw, index, vfta);
4545 static void igb_restore_vlan(struct igb_adapter *adapter)
4547 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4549 if (adapter->vlgrp) {
4551 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4552 if (!vlan_group_get_device(adapter->vlgrp, vid))
4554 igb_vlan_rx_add_vid(adapter->netdev, vid);
4559 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4561 struct e1000_mac_info *mac = &adapter->hw.mac;
4565 /* Fiber NICs only allow 1000 gbps Full duplex */
4566 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4567 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4568 dev_err(&adapter->pdev->dev,
4569 "Unsupported Speed/Duplex configuration\n");
4574 case SPEED_10 + DUPLEX_HALF:
4575 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4577 case SPEED_10 + DUPLEX_FULL:
4578 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4580 case SPEED_100 + DUPLEX_HALF:
4581 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4583 case SPEED_100 + DUPLEX_FULL:
4584 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4586 case SPEED_1000 + DUPLEX_FULL:
4588 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4590 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4592 dev_err(&adapter->pdev->dev,
4593 "Unsupported Speed/Duplex configuration\n");
4599 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4601 struct net_device *netdev = pci_get_drvdata(pdev);
4602 struct igb_adapter *adapter = netdev_priv(netdev);
4603 struct e1000_hw *hw = &adapter->hw;
4604 u32 ctrl, rctl, status;
4605 u32 wufc = adapter->wol;
4610 netif_device_detach(netdev);
4612 if (netif_running(netdev))
4615 igb_reset_interrupt_capability(adapter);
4617 igb_free_queues(adapter);
4620 retval = pci_save_state(pdev);
4625 status = rd32(E1000_STATUS);
4626 if (status & E1000_STATUS_LU)
4627 wufc &= ~E1000_WUFC_LNKC;
4630 igb_setup_rctl(adapter);
4631 igb_set_multi(netdev);
4633 /* turn on all-multi mode if wake on multicast is enabled */
4634 if (wufc & E1000_WUFC_MC) {
4635 rctl = rd32(E1000_RCTL);
4636 rctl |= E1000_RCTL_MPE;
4637 wr32(E1000_RCTL, rctl);
4640 ctrl = rd32(E1000_CTRL);
4641 /* advertise wake from D3Cold */
4642 #define E1000_CTRL_ADVD3WUC 0x00100000
4643 /* phy power management enable */
4644 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4645 ctrl |= E1000_CTRL_ADVD3WUC;
4646 wr32(E1000_CTRL, ctrl);
4648 /* Allow time for pending master requests to run */
4649 igb_disable_pcie_master(&adapter->hw);
4651 wr32(E1000_WUC, E1000_WUC_PME_EN);
4652 wr32(E1000_WUFC, wufc);
4655 wr32(E1000_WUFC, 0);
4658 /* make sure adapter isn't asleep if manageability/wol is enabled */
4659 if (wufc || adapter->en_mng_pt) {
4660 pci_enable_wake(pdev, PCI_D3hot, 1);
4661 pci_enable_wake(pdev, PCI_D3cold, 1);
4663 igb_shutdown_fiber_serdes_link_82575(hw);
4664 pci_enable_wake(pdev, PCI_D3hot, 0);
4665 pci_enable_wake(pdev, PCI_D3cold, 0);
4668 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4669 * would have already happened in close and is redundant. */
4670 igb_release_hw_control(adapter);
4672 pci_disable_device(pdev);
4674 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4680 static int igb_resume(struct pci_dev *pdev)
4682 struct net_device *netdev = pci_get_drvdata(pdev);
4683 struct igb_adapter *adapter = netdev_priv(netdev);
4684 struct e1000_hw *hw = &adapter->hw;
4687 pci_set_power_state(pdev, PCI_D0);
4688 pci_restore_state(pdev);
4690 err = pci_enable_device_mem(pdev);
4693 "igb: Cannot enable PCI device from suspend\n");
4696 pci_set_master(pdev);
4698 pci_enable_wake(pdev, PCI_D3hot, 0);
4699 pci_enable_wake(pdev, PCI_D3cold, 0);
4701 igb_set_interrupt_capability(adapter);
4703 if (igb_alloc_queues(adapter)) {
4704 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4708 /* e1000_power_up_phy(adapter); */
4712 /* let the f/w know that the h/w is now under the control of the
4714 igb_get_hw_control(adapter);
4716 wr32(E1000_WUS, ~0);
4718 if (netif_running(netdev)) {
4719 err = igb_open(netdev);
4724 netif_device_attach(netdev);
4730 static void igb_shutdown(struct pci_dev *pdev)
4732 igb_suspend(pdev, PMSG_SUSPEND);
4735 #ifdef CONFIG_NET_POLL_CONTROLLER
4737 * Polling 'interrupt' - used by things like netconsole to send skbs
4738 * without having to re-enable interrupts. It's not called while
4739 * the interrupt routine is executing.
4741 static void igb_netpoll(struct net_device *netdev)
4743 struct igb_adapter *adapter = netdev_priv(netdev);
4744 struct e1000_hw *hw = &adapter->hw;
4747 if (!adapter->msix_entries) {
4748 igb_irq_disable(adapter);
4749 napi_schedule(&adapter->rx_ring[0].napi);
4753 for (i = 0; i < adapter->num_tx_queues; i++) {
4754 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4755 wr32(E1000_EIMC, tx_ring->eims_value);
4756 igb_clean_tx_irq(tx_ring);
4757 wr32(E1000_EIMS, tx_ring->eims_value);
4760 for (i = 0; i < adapter->num_rx_queues; i++) {
4761 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4762 wr32(E1000_EIMC, rx_ring->eims_value);
4763 napi_schedule(&rx_ring->napi);
4766 #endif /* CONFIG_NET_POLL_CONTROLLER */
4769 * igb_io_error_detected - called when PCI error is detected
4770 * @pdev: Pointer to PCI device
4771 * @state: The current pci connection state
4773 * This function is called after a PCI bus error affecting
4774 * this device has been detected.
4776 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4777 pci_channel_state_t state)
4779 struct net_device *netdev = pci_get_drvdata(pdev);
4780 struct igb_adapter *adapter = netdev_priv(netdev);
4782 netif_device_detach(netdev);
4784 if (netif_running(netdev))
4786 pci_disable_device(pdev);
4788 /* Request a slot slot reset. */
4789 return PCI_ERS_RESULT_NEED_RESET;
4793 * igb_io_slot_reset - called after the pci bus has been reset.
4794 * @pdev: Pointer to PCI device
4796 * Restart the card from scratch, as if from a cold-boot. Implementation
4797 * resembles the first-half of the igb_resume routine.
4799 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4801 struct net_device *netdev = pci_get_drvdata(pdev);
4802 struct igb_adapter *adapter = netdev_priv(netdev);
4803 struct e1000_hw *hw = &adapter->hw;
4804 pci_ers_result_t result;
4807 if (pci_enable_device_mem(pdev)) {
4809 "Cannot re-enable PCI device after reset.\n");
4810 result = PCI_ERS_RESULT_DISCONNECT;
4812 pci_set_master(pdev);
4813 pci_restore_state(pdev);
4815 pci_enable_wake(pdev, PCI_D3hot, 0);
4816 pci_enable_wake(pdev, PCI_D3cold, 0);
4819 wr32(E1000_WUS, ~0);
4820 result = PCI_ERS_RESULT_RECOVERED;
4823 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4825 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4826 "failed 0x%0x\n", err);
4827 /* non-fatal, continue */
4834 * igb_io_resume - called when traffic can start flowing again.
4835 * @pdev: Pointer to PCI device
4837 * This callback is called when the error recovery driver tells us that
4838 * its OK to resume normal operation. Implementation resembles the
4839 * second-half of the igb_resume routine.
4841 static void igb_io_resume(struct pci_dev *pdev)
4843 struct net_device *netdev = pci_get_drvdata(pdev);
4844 struct igb_adapter *adapter = netdev_priv(netdev);
4846 if (netif_running(netdev)) {
4847 if (igb_up(adapter)) {
4848 dev_err(&pdev->dev, "igb_up failed after reset\n");
4853 netif_device_attach(netdev);
4855 /* let the f/w know that the h/w is now under the control of the
4857 igb_get_hw_control(adapter);