88e13f7e566fb79dd65d6dad330bcb096336625d
[safe/jmp/linux-2.6] / drivers / net / igb / igb_ethtool.c
1 /*******************************************************************************
2
3   Intel(R) Gigabit Ethernet Linux driver
4   Copyright(c) 2007-2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37 #include <linux/sched.h>
38
39 #include "igb.h"
40
41 struct igb_stats {
42         char stat_string[ETH_GSTRING_LEN];
43         int sizeof_stat;
44         int stat_offset;
45 };
46
47 #define IGB_STAT(_name, _stat) { \
48         .stat_string = _name, \
49         .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50         .stat_offset = offsetof(struct igb_adapter, _stat) \
51 }
52 static const struct igb_stats igb_gstrings_stats[] = {
53         IGB_STAT("rx_packets", stats.gprc),
54         IGB_STAT("tx_packets", stats.gptc),
55         IGB_STAT("rx_bytes", stats.gorc),
56         IGB_STAT("tx_bytes", stats.gotc),
57         IGB_STAT("rx_broadcast", stats.bprc),
58         IGB_STAT("tx_broadcast", stats.bptc),
59         IGB_STAT("rx_multicast", stats.mprc),
60         IGB_STAT("tx_multicast", stats.mptc),
61         IGB_STAT("multicast", stats.mprc),
62         IGB_STAT("collisions", stats.colc),
63         IGB_STAT("rx_crc_errors", stats.crcerrs),
64         IGB_STAT("rx_no_buffer_count", stats.rnbc),
65         IGB_STAT("rx_missed_errors", stats.mpc),
66         IGB_STAT("tx_aborted_errors", stats.ecol),
67         IGB_STAT("tx_carrier_errors", stats.tncrs),
68         IGB_STAT("tx_window_errors", stats.latecol),
69         IGB_STAT("tx_abort_late_coll", stats.latecol),
70         IGB_STAT("tx_deferred_ok", stats.dc),
71         IGB_STAT("tx_single_coll_ok", stats.scc),
72         IGB_STAT("tx_multi_coll_ok", stats.mcc),
73         IGB_STAT("tx_timeout_count", tx_timeout_count),
74         IGB_STAT("rx_long_length_errors", stats.roc),
75         IGB_STAT("rx_short_length_errors", stats.ruc),
76         IGB_STAT("rx_align_errors", stats.algnerrc),
77         IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78         IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79         IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80         IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81         IGB_STAT("tx_flow_control_xon", stats.xontxc),
82         IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83         IGB_STAT("rx_long_byte_count", stats.gorc),
84         IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85         IGB_STAT("tx_smbus", stats.mgptc),
86         IGB_STAT("rx_smbus", stats.mgprc),
87         IGB_STAT("dropped_smbus", stats.mgpdc),
88 };
89
90 #define IGB_NETDEV_STAT(_net_stat) { \
91         .stat_string = __stringify(_net_stat), \
92         .sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \
93         .stat_offset = offsetof(struct net_device_stats, _net_stat) \
94 }
95 static const struct igb_stats igb_gstrings_net_stats[] = {
96         IGB_NETDEV_STAT(rx_errors),
97         IGB_NETDEV_STAT(tx_errors),
98         IGB_NETDEV_STAT(tx_dropped),
99         IGB_NETDEV_STAT(rx_length_errors),
100         IGB_NETDEV_STAT(rx_over_errors),
101         IGB_NETDEV_STAT(rx_frame_errors),
102         IGB_NETDEV_STAT(rx_fifo_errors),
103         IGB_NETDEV_STAT(tx_fifo_errors),
104         IGB_NETDEV_STAT(tx_heartbeat_errors)
105 };
106
107 #define IGB_GLOBAL_STATS_LEN    \
108         (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
109 #define IGB_NETDEV_STATS_LEN    \
110         (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
111 #define IGB_RX_QUEUE_STATS_LEN \
112         (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
113 #define IGB_TX_QUEUE_STATS_LEN \
114         (sizeof(struct igb_tx_queue_stats) / sizeof(u64))
115 #define IGB_QUEUE_STATS_LEN \
116         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
117           IGB_RX_QUEUE_STATS_LEN) + \
118          (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
119           IGB_TX_QUEUE_STATS_LEN))
120 #define IGB_STATS_LEN \
121         (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
122
123 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
124         "Register test  (offline)", "Eeprom test    (offline)",
125         "Interrupt test (offline)", "Loopback test  (offline)",
126         "Link test   (on/offline)"
127 };
128 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
129
130 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
131 {
132         struct igb_adapter *adapter = netdev_priv(netdev);
133         struct e1000_hw *hw = &adapter->hw;
134         u32 status;
135
136         if (hw->phy.media_type == e1000_media_type_copper) {
137
138                 ecmd->supported = (SUPPORTED_10baseT_Half |
139                                    SUPPORTED_10baseT_Full |
140                                    SUPPORTED_100baseT_Half |
141                                    SUPPORTED_100baseT_Full |
142                                    SUPPORTED_1000baseT_Full|
143                                    SUPPORTED_Autoneg |
144                                    SUPPORTED_TP);
145                 ecmd->advertising = ADVERTISED_TP;
146
147                 if (hw->mac.autoneg == 1) {
148                         ecmd->advertising |= ADVERTISED_Autoneg;
149                         /* the e1000 autoneg seems to match ethtool nicely */
150                         ecmd->advertising |= hw->phy.autoneg_advertised;
151                 }
152
153                 ecmd->port = PORT_TP;
154                 ecmd->phy_address = hw->phy.addr;
155         } else {
156                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
157                                      SUPPORTED_FIBRE |
158                                      SUPPORTED_Autoneg);
159
160                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
161                                      ADVERTISED_FIBRE |
162                                      ADVERTISED_Autoneg);
163
164                 ecmd->port = PORT_FIBRE;
165         }
166
167         ecmd->transceiver = XCVR_INTERNAL;
168
169         status = rd32(E1000_STATUS);
170
171         if (status & E1000_STATUS_LU) {
172
173                 if ((status & E1000_STATUS_SPEED_1000) ||
174                     hw->phy.media_type != e1000_media_type_copper)
175                         ecmd->speed = SPEED_1000;
176                 else if (status & E1000_STATUS_SPEED_100)
177                         ecmd->speed = SPEED_100;
178                 else
179                         ecmd->speed = SPEED_10;
180
181                 if ((status & E1000_STATUS_FD) ||
182                     hw->phy.media_type != e1000_media_type_copper)
183                         ecmd->duplex = DUPLEX_FULL;
184                 else
185                         ecmd->duplex = DUPLEX_HALF;
186         } else {
187                 ecmd->speed = -1;
188                 ecmd->duplex = -1;
189         }
190
191         ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
192         return 0;
193 }
194
195 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
196 {
197         struct igb_adapter *adapter = netdev_priv(netdev);
198         struct e1000_hw *hw = &adapter->hw;
199
200         /* When SoL/IDER sessions are active, autoneg/speed/duplex
201          * cannot be changed */
202         if (igb_check_reset_block(hw)) {
203                 dev_err(&adapter->pdev->dev, "Cannot change link "
204                         "characteristics when SoL/IDER is active.\n");
205                 return -EINVAL;
206         }
207
208         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
209                 msleep(1);
210
211         if (ecmd->autoneg == AUTONEG_ENABLE) {
212                 hw->mac.autoneg = 1;
213                 hw->phy.autoneg_advertised = ecmd->advertising |
214                                              ADVERTISED_TP |
215                                              ADVERTISED_Autoneg;
216                 ecmd->advertising = hw->phy.autoneg_advertised;
217                 if (adapter->fc_autoneg)
218                         hw->fc.requested_mode = e1000_fc_default;
219         } else {
220                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
221                         clear_bit(__IGB_RESETTING, &adapter->state);
222                         return -EINVAL;
223                 }
224         }
225
226         /* reset the link */
227         if (netif_running(adapter->netdev)) {
228                 igb_down(adapter);
229                 igb_up(adapter);
230         } else
231                 igb_reset(adapter);
232
233         clear_bit(__IGB_RESETTING, &adapter->state);
234         return 0;
235 }
236
237 static void igb_get_pauseparam(struct net_device *netdev,
238                                struct ethtool_pauseparam *pause)
239 {
240         struct igb_adapter *adapter = netdev_priv(netdev);
241         struct e1000_hw *hw = &adapter->hw;
242
243         pause->autoneg =
244                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
245
246         if (hw->fc.current_mode == e1000_fc_rx_pause)
247                 pause->rx_pause = 1;
248         else if (hw->fc.current_mode == e1000_fc_tx_pause)
249                 pause->tx_pause = 1;
250         else if (hw->fc.current_mode == e1000_fc_full) {
251                 pause->rx_pause = 1;
252                 pause->tx_pause = 1;
253         }
254 }
255
256 static int igb_set_pauseparam(struct net_device *netdev,
257                               struct ethtool_pauseparam *pause)
258 {
259         struct igb_adapter *adapter = netdev_priv(netdev);
260         struct e1000_hw *hw = &adapter->hw;
261         int retval = 0;
262
263         adapter->fc_autoneg = pause->autoneg;
264
265         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
266                 msleep(1);
267
268         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
269                 hw->fc.requested_mode = e1000_fc_default;
270                 if (netif_running(adapter->netdev)) {
271                         igb_down(adapter);
272                         igb_up(adapter);
273                 } else {
274                         igb_reset(adapter);
275                 }
276         } else {
277                 if (pause->rx_pause && pause->tx_pause)
278                         hw->fc.requested_mode = e1000_fc_full;
279                 else if (pause->rx_pause && !pause->tx_pause)
280                         hw->fc.requested_mode = e1000_fc_rx_pause;
281                 else if (!pause->rx_pause && pause->tx_pause)
282                         hw->fc.requested_mode = e1000_fc_tx_pause;
283                 else if (!pause->rx_pause && !pause->tx_pause)
284                         hw->fc.requested_mode = e1000_fc_none;
285
286                 hw->fc.current_mode = hw->fc.requested_mode;
287
288                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
289                           igb_force_mac_fc(hw) : igb_setup_link(hw));
290         }
291
292         clear_bit(__IGB_RESETTING, &adapter->state);
293         return retval;
294 }
295
296 static u32 igb_get_rx_csum(struct net_device *netdev)
297 {
298         struct igb_adapter *adapter = netdev_priv(netdev);
299         return !!(adapter->rx_ring[0].flags & IGB_RING_FLAG_RX_CSUM);
300 }
301
302 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
303 {
304         struct igb_adapter *adapter = netdev_priv(netdev);
305         int i;
306
307         for (i = 0; i < adapter->num_rx_queues; i++) {
308                 if (data)
309                         adapter->rx_ring[i].flags |= IGB_RING_FLAG_RX_CSUM;
310                 else
311                         adapter->rx_ring[i].flags &= ~IGB_RING_FLAG_RX_CSUM;
312         }
313
314         return 0;
315 }
316
317 static u32 igb_get_tx_csum(struct net_device *netdev)
318 {
319         return (netdev->features & NETIF_F_IP_CSUM) != 0;
320 }
321
322 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
323 {
324         struct igb_adapter *adapter = netdev_priv(netdev);
325
326         if (data) {
327                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
328                 if (adapter->hw.mac.type >= e1000_82576)
329                         netdev->features |= NETIF_F_SCTP_CSUM;
330         } else {
331                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
332                                       NETIF_F_SCTP_CSUM);
333         }
334
335         return 0;
336 }
337
338 static int igb_set_tso(struct net_device *netdev, u32 data)
339 {
340         struct igb_adapter *adapter = netdev_priv(netdev);
341
342         if (data) {
343                 netdev->features |= NETIF_F_TSO;
344                 netdev->features |= NETIF_F_TSO6;
345         } else {
346                 netdev->features &= ~NETIF_F_TSO;
347                 netdev->features &= ~NETIF_F_TSO6;
348         }
349
350         dev_info(&adapter->pdev->dev, "TSO is %s\n",
351                  data ? "Enabled" : "Disabled");
352         return 0;
353 }
354
355 static u32 igb_get_msglevel(struct net_device *netdev)
356 {
357         struct igb_adapter *adapter = netdev_priv(netdev);
358         return adapter->msg_enable;
359 }
360
361 static void igb_set_msglevel(struct net_device *netdev, u32 data)
362 {
363         struct igb_adapter *adapter = netdev_priv(netdev);
364         adapter->msg_enable = data;
365 }
366
367 static int igb_get_regs_len(struct net_device *netdev)
368 {
369 #define IGB_REGS_LEN 551
370         return IGB_REGS_LEN * sizeof(u32);
371 }
372
373 static void igb_get_regs(struct net_device *netdev,
374                          struct ethtool_regs *regs, void *p)
375 {
376         struct igb_adapter *adapter = netdev_priv(netdev);
377         struct e1000_hw *hw = &adapter->hw;
378         u32 *regs_buff = p;
379         u8 i;
380
381         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
382
383         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
384
385         /* General Registers */
386         regs_buff[0] = rd32(E1000_CTRL);
387         regs_buff[1] = rd32(E1000_STATUS);
388         regs_buff[2] = rd32(E1000_CTRL_EXT);
389         regs_buff[3] = rd32(E1000_MDIC);
390         regs_buff[4] = rd32(E1000_SCTL);
391         regs_buff[5] = rd32(E1000_CONNSW);
392         regs_buff[6] = rd32(E1000_VET);
393         regs_buff[7] = rd32(E1000_LEDCTL);
394         regs_buff[8] = rd32(E1000_PBA);
395         regs_buff[9] = rd32(E1000_PBS);
396         regs_buff[10] = rd32(E1000_FRTIMER);
397         regs_buff[11] = rd32(E1000_TCPTIMER);
398
399         /* NVM Register */
400         regs_buff[12] = rd32(E1000_EECD);
401
402         /* Interrupt */
403         /* Reading EICS for EICR because they read the
404          * same but EICS does not clear on read */
405         regs_buff[13] = rd32(E1000_EICS);
406         regs_buff[14] = rd32(E1000_EICS);
407         regs_buff[15] = rd32(E1000_EIMS);
408         regs_buff[16] = rd32(E1000_EIMC);
409         regs_buff[17] = rd32(E1000_EIAC);
410         regs_buff[18] = rd32(E1000_EIAM);
411         /* Reading ICS for ICR because they read the
412          * same but ICS does not clear on read */
413         regs_buff[19] = rd32(E1000_ICS);
414         regs_buff[20] = rd32(E1000_ICS);
415         regs_buff[21] = rd32(E1000_IMS);
416         regs_buff[22] = rd32(E1000_IMC);
417         regs_buff[23] = rd32(E1000_IAC);
418         regs_buff[24] = rd32(E1000_IAM);
419         regs_buff[25] = rd32(E1000_IMIRVP);
420
421         /* Flow Control */
422         regs_buff[26] = rd32(E1000_FCAL);
423         regs_buff[27] = rd32(E1000_FCAH);
424         regs_buff[28] = rd32(E1000_FCTTV);
425         regs_buff[29] = rd32(E1000_FCRTL);
426         regs_buff[30] = rd32(E1000_FCRTH);
427         regs_buff[31] = rd32(E1000_FCRTV);
428
429         /* Receive */
430         regs_buff[32] = rd32(E1000_RCTL);
431         regs_buff[33] = rd32(E1000_RXCSUM);
432         regs_buff[34] = rd32(E1000_RLPML);
433         regs_buff[35] = rd32(E1000_RFCTL);
434         regs_buff[36] = rd32(E1000_MRQC);
435         regs_buff[37] = rd32(E1000_VT_CTL);
436
437         /* Transmit */
438         regs_buff[38] = rd32(E1000_TCTL);
439         regs_buff[39] = rd32(E1000_TCTL_EXT);
440         regs_buff[40] = rd32(E1000_TIPG);
441         regs_buff[41] = rd32(E1000_DTXCTL);
442
443         /* Wake Up */
444         regs_buff[42] = rd32(E1000_WUC);
445         regs_buff[43] = rd32(E1000_WUFC);
446         regs_buff[44] = rd32(E1000_WUS);
447         regs_buff[45] = rd32(E1000_IPAV);
448         regs_buff[46] = rd32(E1000_WUPL);
449
450         /* MAC */
451         regs_buff[47] = rd32(E1000_PCS_CFG0);
452         regs_buff[48] = rd32(E1000_PCS_LCTL);
453         regs_buff[49] = rd32(E1000_PCS_LSTAT);
454         regs_buff[50] = rd32(E1000_PCS_ANADV);
455         regs_buff[51] = rd32(E1000_PCS_LPAB);
456         regs_buff[52] = rd32(E1000_PCS_NPTX);
457         regs_buff[53] = rd32(E1000_PCS_LPABNP);
458
459         /* Statistics */
460         regs_buff[54] = adapter->stats.crcerrs;
461         regs_buff[55] = adapter->stats.algnerrc;
462         regs_buff[56] = adapter->stats.symerrs;
463         regs_buff[57] = adapter->stats.rxerrc;
464         regs_buff[58] = adapter->stats.mpc;
465         regs_buff[59] = adapter->stats.scc;
466         regs_buff[60] = adapter->stats.ecol;
467         regs_buff[61] = adapter->stats.mcc;
468         regs_buff[62] = adapter->stats.latecol;
469         regs_buff[63] = adapter->stats.colc;
470         regs_buff[64] = adapter->stats.dc;
471         regs_buff[65] = adapter->stats.tncrs;
472         regs_buff[66] = adapter->stats.sec;
473         regs_buff[67] = adapter->stats.htdpmc;
474         regs_buff[68] = adapter->stats.rlec;
475         regs_buff[69] = adapter->stats.xonrxc;
476         regs_buff[70] = adapter->stats.xontxc;
477         regs_buff[71] = adapter->stats.xoffrxc;
478         regs_buff[72] = adapter->stats.xofftxc;
479         regs_buff[73] = adapter->stats.fcruc;
480         regs_buff[74] = adapter->stats.prc64;
481         regs_buff[75] = adapter->stats.prc127;
482         regs_buff[76] = adapter->stats.prc255;
483         regs_buff[77] = adapter->stats.prc511;
484         regs_buff[78] = adapter->stats.prc1023;
485         regs_buff[79] = adapter->stats.prc1522;
486         regs_buff[80] = adapter->stats.gprc;
487         regs_buff[81] = adapter->stats.bprc;
488         regs_buff[82] = adapter->stats.mprc;
489         regs_buff[83] = adapter->stats.gptc;
490         regs_buff[84] = adapter->stats.gorc;
491         regs_buff[86] = adapter->stats.gotc;
492         regs_buff[88] = adapter->stats.rnbc;
493         regs_buff[89] = adapter->stats.ruc;
494         regs_buff[90] = adapter->stats.rfc;
495         regs_buff[91] = adapter->stats.roc;
496         regs_buff[92] = adapter->stats.rjc;
497         regs_buff[93] = adapter->stats.mgprc;
498         regs_buff[94] = adapter->stats.mgpdc;
499         regs_buff[95] = adapter->stats.mgptc;
500         regs_buff[96] = adapter->stats.tor;
501         regs_buff[98] = adapter->stats.tot;
502         regs_buff[100] = adapter->stats.tpr;
503         regs_buff[101] = adapter->stats.tpt;
504         regs_buff[102] = adapter->stats.ptc64;
505         regs_buff[103] = adapter->stats.ptc127;
506         regs_buff[104] = adapter->stats.ptc255;
507         regs_buff[105] = adapter->stats.ptc511;
508         regs_buff[106] = adapter->stats.ptc1023;
509         regs_buff[107] = adapter->stats.ptc1522;
510         regs_buff[108] = adapter->stats.mptc;
511         regs_buff[109] = adapter->stats.bptc;
512         regs_buff[110] = adapter->stats.tsctc;
513         regs_buff[111] = adapter->stats.iac;
514         regs_buff[112] = adapter->stats.rpthc;
515         regs_buff[113] = adapter->stats.hgptc;
516         regs_buff[114] = adapter->stats.hgorc;
517         regs_buff[116] = adapter->stats.hgotc;
518         regs_buff[118] = adapter->stats.lenerrs;
519         regs_buff[119] = adapter->stats.scvpc;
520         regs_buff[120] = adapter->stats.hrmpc;
521
522         for (i = 0; i < 4; i++)
523                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
524         for (i = 0; i < 4; i++)
525                 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
526         for (i = 0; i < 4; i++)
527                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
528         for (i = 0; i < 4; i++)
529                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
530         for (i = 0; i < 4; i++)
531                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
532         for (i = 0; i < 4; i++)
533                 regs_buff[141 + i] = rd32(E1000_RDH(i));
534         for (i = 0; i < 4; i++)
535                 regs_buff[145 + i] = rd32(E1000_RDT(i));
536         for (i = 0; i < 4; i++)
537                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
538
539         for (i = 0; i < 10; i++)
540                 regs_buff[153 + i] = rd32(E1000_EITR(i));
541         for (i = 0; i < 8; i++)
542                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
543         for (i = 0; i < 8; i++)
544                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
545         for (i = 0; i < 16; i++)
546                 regs_buff[179 + i] = rd32(E1000_RAL(i));
547         for (i = 0; i < 16; i++)
548                 regs_buff[195 + i] = rd32(E1000_RAH(i));
549
550         for (i = 0; i < 4; i++)
551                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
552         for (i = 0; i < 4; i++)
553                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
554         for (i = 0; i < 4; i++)
555                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
556         for (i = 0; i < 4; i++)
557                 regs_buff[223 + i] = rd32(E1000_TDH(i));
558         for (i = 0; i < 4; i++)
559                 regs_buff[227 + i] = rd32(E1000_TDT(i));
560         for (i = 0; i < 4; i++)
561                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
562         for (i = 0; i < 4; i++)
563                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
564         for (i = 0; i < 4; i++)
565                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
566         for (i = 0; i < 4; i++)
567                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
568
569         for (i = 0; i < 4; i++)
570                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
571         for (i = 0; i < 4; i++)
572                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
573         for (i = 0; i < 32; i++)
574                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
575         for (i = 0; i < 128; i++)
576                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
577         for (i = 0; i < 128; i++)
578                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
579         for (i = 0; i < 4; i++)
580                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
581
582         regs_buff[547] = rd32(E1000_TDFH);
583         regs_buff[548] = rd32(E1000_TDFT);
584         regs_buff[549] = rd32(E1000_TDFHS);
585         regs_buff[550] = rd32(E1000_TDFPC);
586
587 }
588
589 static int igb_get_eeprom_len(struct net_device *netdev)
590 {
591         struct igb_adapter *adapter = netdev_priv(netdev);
592         return adapter->hw.nvm.word_size * 2;
593 }
594
595 static int igb_get_eeprom(struct net_device *netdev,
596                           struct ethtool_eeprom *eeprom, u8 *bytes)
597 {
598         struct igb_adapter *adapter = netdev_priv(netdev);
599         struct e1000_hw *hw = &adapter->hw;
600         u16 *eeprom_buff;
601         int first_word, last_word;
602         int ret_val = 0;
603         u16 i;
604
605         if (eeprom->len == 0)
606                 return -EINVAL;
607
608         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
609
610         first_word = eeprom->offset >> 1;
611         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
612
613         eeprom_buff = kmalloc(sizeof(u16) *
614                         (last_word - first_word + 1), GFP_KERNEL);
615         if (!eeprom_buff)
616                 return -ENOMEM;
617
618         if (hw->nvm.type == e1000_nvm_eeprom_spi)
619                 ret_val = hw->nvm.ops.read(hw, first_word,
620                                             last_word - first_word + 1,
621                                             eeprom_buff);
622         else {
623                 for (i = 0; i < last_word - first_word + 1; i++) {
624                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
625                                                     &eeprom_buff[i]);
626                         if (ret_val)
627                                 break;
628                 }
629         }
630
631         /* Device's eeprom is always little-endian, word addressable */
632         for (i = 0; i < last_word - first_word + 1; i++)
633                 le16_to_cpus(&eeprom_buff[i]);
634
635         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
636                         eeprom->len);
637         kfree(eeprom_buff);
638
639         return ret_val;
640 }
641
642 static int igb_set_eeprom(struct net_device *netdev,
643                           struct ethtool_eeprom *eeprom, u8 *bytes)
644 {
645         struct igb_adapter *adapter = netdev_priv(netdev);
646         struct e1000_hw *hw = &adapter->hw;
647         u16 *eeprom_buff;
648         void *ptr;
649         int max_len, first_word, last_word, ret_val = 0;
650         u16 i;
651
652         if (eeprom->len == 0)
653                 return -EOPNOTSUPP;
654
655         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
656                 return -EFAULT;
657
658         max_len = hw->nvm.word_size * 2;
659
660         first_word = eeprom->offset >> 1;
661         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
662         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
663         if (!eeprom_buff)
664                 return -ENOMEM;
665
666         ptr = (void *)eeprom_buff;
667
668         if (eeprom->offset & 1) {
669                 /* need read/modify/write of first changed EEPROM word */
670                 /* only the second byte of the word is being modified */
671                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
672                                             &eeprom_buff[0]);
673                 ptr++;
674         }
675         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
676                 /* need read/modify/write of last changed EEPROM word */
677                 /* only the first byte of the word is being modified */
678                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
679                                    &eeprom_buff[last_word - first_word]);
680         }
681
682         /* Device's eeprom is always little-endian, word addressable */
683         for (i = 0; i < last_word - first_word + 1; i++)
684                 le16_to_cpus(&eeprom_buff[i]);
685
686         memcpy(ptr, bytes, eeprom->len);
687
688         for (i = 0; i < last_word - first_word + 1; i++)
689                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
690
691         ret_val = hw->nvm.ops.write(hw, first_word,
692                                      last_word - first_word + 1, eeprom_buff);
693
694         /* Update the checksum over the first part of the EEPROM if needed
695          * and flush shadow RAM for 82573 controllers */
696         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
697                 igb_update_nvm_checksum(hw);
698
699         kfree(eeprom_buff);
700         return ret_val;
701 }
702
703 static void igb_get_drvinfo(struct net_device *netdev,
704                             struct ethtool_drvinfo *drvinfo)
705 {
706         struct igb_adapter *adapter = netdev_priv(netdev);
707         char firmware_version[32];
708         u16 eeprom_data;
709
710         strncpy(drvinfo->driver,  igb_driver_name, 32);
711         strncpy(drvinfo->version, igb_driver_version, 32);
712
713         /* EEPROM image version # is reported as firmware version # for
714          * 82575 controllers */
715         adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
716         sprintf(firmware_version, "%d.%d-%d",
717                 (eeprom_data & 0xF000) >> 12,
718                 (eeprom_data & 0x0FF0) >> 4,
719                 eeprom_data & 0x000F);
720
721         strncpy(drvinfo->fw_version, firmware_version, 32);
722         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
723         drvinfo->n_stats = IGB_STATS_LEN;
724         drvinfo->testinfo_len = IGB_TEST_LEN;
725         drvinfo->regdump_len = igb_get_regs_len(netdev);
726         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
727 }
728
729 static void igb_get_ringparam(struct net_device *netdev,
730                               struct ethtool_ringparam *ring)
731 {
732         struct igb_adapter *adapter = netdev_priv(netdev);
733
734         ring->rx_max_pending = IGB_MAX_RXD;
735         ring->tx_max_pending = IGB_MAX_TXD;
736         ring->rx_mini_max_pending = 0;
737         ring->rx_jumbo_max_pending = 0;
738         ring->rx_pending = adapter->rx_ring_count;
739         ring->tx_pending = adapter->tx_ring_count;
740         ring->rx_mini_pending = 0;
741         ring->rx_jumbo_pending = 0;
742 }
743
744 static int igb_set_ringparam(struct net_device *netdev,
745                              struct ethtool_ringparam *ring)
746 {
747         struct igb_adapter *adapter = netdev_priv(netdev);
748         struct igb_ring *temp_ring;
749         int i, err = 0;
750         u16 new_rx_count, new_tx_count;
751
752         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
753                 return -EINVAL;
754
755         new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
756         new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
757         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
758
759         new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
760         new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
761         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
762
763         if ((new_tx_count == adapter->tx_ring_count) &&
764             (new_rx_count == adapter->rx_ring_count)) {
765                 /* nothing to do */
766                 return 0;
767         }
768
769         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
770                 msleep(1);
771
772         if (!netif_running(adapter->netdev)) {
773                 for (i = 0; i < adapter->num_tx_queues; i++)
774                         adapter->tx_ring[i].count = new_tx_count;
775                 for (i = 0; i < adapter->num_rx_queues; i++)
776                         adapter->rx_ring[i].count = new_rx_count;
777                 adapter->tx_ring_count = new_tx_count;
778                 adapter->rx_ring_count = new_rx_count;
779                 goto clear_reset;
780         }
781
782         if (adapter->num_tx_queues > adapter->num_rx_queues)
783                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
784         else
785                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
786
787         if (!temp_ring) {
788                 err = -ENOMEM;
789                 goto clear_reset;
790         }
791
792         igb_down(adapter);
793
794         /*
795          * We can't just free everything and then setup again,
796          * because the ISRs in MSI-X mode get passed pointers
797          * to the tx and rx ring structs.
798          */
799         if (new_tx_count != adapter->tx_ring_count) {
800                 memcpy(temp_ring, adapter->tx_ring,
801                        adapter->num_tx_queues * sizeof(struct igb_ring));
802
803                 for (i = 0; i < adapter->num_tx_queues; i++) {
804                         temp_ring[i].count = new_tx_count;
805                         err = igb_setup_tx_resources(&temp_ring[i]);
806                         if (err) {
807                                 while (i) {
808                                         i--;
809                                         igb_free_tx_resources(&temp_ring[i]);
810                                 }
811                                 goto err_setup;
812                         }
813                 }
814
815                 for (i = 0; i < adapter->num_tx_queues; i++)
816                         igb_free_tx_resources(&adapter->tx_ring[i]);
817
818                 memcpy(adapter->tx_ring, temp_ring,
819                        adapter->num_tx_queues * sizeof(struct igb_ring));
820
821                 adapter->tx_ring_count = new_tx_count;
822         }
823
824         if (new_rx_count != adapter->rx_ring->count) {
825                 memcpy(temp_ring, adapter->rx_ring,
826                        adapter->num_rx_queues * sizeof(struct igb_ring));
827
828                 for (i = 0; i < adapter->num_rx_queues; i++) {
829                         temp_ring[i].count = new_rx_count;
830                         err = igb_setup_rx_resources(&temp_ring[i]);
831                         if (err) {
832                                 while (i) {
833                                         i--;
834                                         igb_free_rx_resources(&temp_ring[i]);
835                                 }
836                                 goto err_setup;
837                         }
838
839                 }
840
841                 for (i = 0; i < adapter->num_rx_queues; i++)
842                         igb_free_rx_resources(&adapter->rx_ring[i]);
843
844                 memcpy(adapter->rx_ring, temp_ring,
845                        adapter->num_rx_queues * sizeof(struct igb_ring));
846
847                 adapter->rx_ring_count = new_rx_count;
848         }
849 err_setup:
850         igb_up(adapter);
851         vfree(temp_ring);
852 clear_reset:
853         clear_bit(__IGB_RESETTING, &adapter->state);
854         return err;
855 }
856
857 /* ethtool register test data */
858 struct igb_reg_test {
859         u16 reg;
860         u16 reg_offset;
861         u16 array_len;
862         u16 test_type;
863         u32 mask;
864         u32 write;
865 };
866
867 /* In the hardware, registers are laid out either singly, in arrays
868  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
869  * most tests take place on arrays or single registers (handled
870  * as a single-element array) and special-case the tables.
871  * Table tests are always pattern tests.
872  *
873  * We also make provision for some required setup steps by specifying
874  * registers to be written without any read-back testing.
875  */
876
877 #define PATTERN_TEST    1
878 #define SET_READ_TEST   2
879 #define WRITE_NO_TEST   3
880 #define TABLE32_TEST    4
881 #define TABLE64_TEST_LO 5
882 #define TABLE64_TEST_HI 6
883
884 /* 82576 reg test */
885 static struct igb_reg_test reg_test_82576[] = {
886         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
887         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
888         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
889         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
890         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
891         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
892         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
893         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
894         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
895         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
896         /* Enable all RX queues before testing. */
897         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
898         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
899         /* RDH is read-only for 82576, only test RDT. */
900         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
901         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
902         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
903         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
904         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
905         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
906         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
907         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
908         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
909         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
910         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
911         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
912         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
913         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
914         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
915         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
916         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
917         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
918         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
919         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
920         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
921         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
922         { 0, 0, 0, 0 }
923 };
924
925 /* 82575 register test */
926 static struct igb_reg_test reg_test_82575[] = {
927         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
928         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
929         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
930         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
931         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
932         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
933         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
934         /* Enable all four RX queues before testing. */
935         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
936         /* RDH is read-only for 82575, only test RDT. */
937         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
938         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
939         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
940         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
941         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
942         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
943         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
944         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
945         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
946         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
947         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
948         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
949         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
950         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
951         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
952         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
953         { 0, 0, 0, 0 }
954 };
955
956 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
957                              int reg, u32 mask, u32 write)
958 {
959         struct e1000_hw *hw = &adapter->hw;
960         u32 pat, val;
961         static const u32 _test[] =
962                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
963         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
964                 wr32(reg, (_test[pat] & write));
965                 val = rd32(reg);
966                 if (val != (_test[pat] & write & mask)) {
967                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
968                                 "failed: got 0x%08X expected 0x%08X\n",
969                                 reg, val, (_test[pat] & write & mask));
970                         *data = reg;
971                         return 1;
972                 }
973         }
974
975         return 0;
976 }
977
978 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
979                               int reg, u32 mask, u32 write)
980 {
981         struct e1000_hw *hw = &adapter->hw;
982         u32 val;
983         wr32(reg, write & mask);
984         val = rd32(reg);
985         if ((write & mask) != (val & mask)) {
986                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
987                         " got 0x%08X expected 0x%08X\n", reg,
988                         (val & mask), (write & mask));
989                 *data = reg;
990                 return 1;
991         }
992
993         return 0;
994 }
995
996 #define REG_PATTERN_TEST(reg, mask, write) \
997         do { \
998                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
999                         return 1; \
1000         } while (0)
1001
1002 #define REG_SET_AND_CHECK(reg, mask, write) \
1003         do { \
1004                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1005                         return 1; \
1006         } while (0)
1007
1008 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1009 {
1010         struct e1000_hw *hw = &adapter->hw;
1011         struct igb_reg_test *test;
1012         u32 value, before, after;
1013         u32 i, toggle;
1014
1015         switch (adapter->hw.mac.type) {
1016         case e1000_82576:
1017                 test = reg_test_82576;
1018                 toggle = 0x7FFFF3FF;
1019                 break;
1020         default:
1021                 test = reg_test_82575;
1022                 toggle = 0x7FFFF3FF;
1023                 break;
1024         }
1025
1026         /* Because the status register is such a special case,
1027          * we handle it separately from the rest of the register
1028          * tests.  Some bits are read-only, some toggle, and some
1029          * are writable on newer MACs.
1030          */
1031         before = rd32(E1000_STATUS);
1032         value = (rd32(E1000_STATUS) & toggle);
1033         wr32(E1000_STATUS, toggle);
1034         after = rd32(E1000_STATUS) & toggle;
1035         if (value != after) {
1036                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1037                         "got: 0x%08X expected: 0x%08X\n", after, value);
1038                 *data = 1;
1039                 return 1;
1040         }
1041         /* restore previous status */
1042         wr32(E1000_STATUS, before);
1043
1044         /* Perform the remainder of the register test, looping through
1045          * the test table until we either fail or reach the null entry.
1046          */
1047         while (test->reg) {
1048                 for (i = 0; i < test->array_len; i++) {
1049                         switch (test->test_type) {
1050                         case PATTERN_TEST:
1051                                 REG_PATTERN_TEST(test->reg +
1052                                                 (i * test->reg_offset),
1053                                                 test->mask,
1054                                                 test->write);
1055                                 break;
1056                         case SET_READ_TEST:
1057                                 REG_SET_AND_CHECK(test->reg +
1058                                                 (i * test->reg_offset),
1059                                                 test->mask,
1060                                                 test->write);
1061                                 break;
1062                         case WRITE_NO_TEST:
1063                                 writel(test->write,
1064                                     (adapter->hw.hw_addr + test->reg)
1065                                         + (i * test->reg_offset));
1066                                 break;
1067                         case TABLE32_TEST:
1068                                 REG_PATTERN_TEST(test->reg + (i * 4),
1069                                                 test->mask,
1070                                                 test->write);
1071                                 break;
1072                         case TABLE64_TEST_LO:
1073                                 REG_PATTERN_TEST(test->reg + (i * 8),
1074                                                 test->mask,
1075                                                 test->write);
1076                                 break;
1077                         case TABLE64_TEST_HI:
1078                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1079                                                 test->mask,
1080                                                 test->write);
1081                                 break;
1082                         }
1083                 }
1084                 test++;
1085         }
1086
1087         *data = 0;
1088         return 0;
1089 }
1090
1091 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1092 {
1093         u16 temp;
1094         u16 checksum = 0;
1095         u16 i;
1096
1097         *data = 0;
1098         /* Read and add up the contents of the EEPROM */
1099         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1100                 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
1101                         *data = 1;
1102                         break;
1103                 }
1104                 checksum += temp;
1105         }
1106
1107         /* If Checksum is not Correct return error else test passed */
1108         if ((checksum != (u16) NVM_SUM) && !(*data))
1109                 *data = 2;
1110
1111         return *data;
1112 }
1113
1114 static irqreturn_t igb_test_intr(int irq, void *data)
1115 {
1116         struct igb_adapter *adapter = (struct igb_adapter *) data;
1117         struct e1000_hw *hw = &adapter->hw;
1118
1119         adapter->test_icr |= rd32(E1000_ICR);
1120
1121         return IRQ_HANDLED;
1122 }
1123
1124 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1125 {
1126         struct e1000_hw *hw = &adapter->hw;
1127         struct net_device *netdev = adapter->netdev;
1128         u32 mask, ics_mask, i = 0, shared_int = true;
1129         u32 irq = adapter->pdev->irq;
1130
1131         *data = 0;
1132
1133         /* Hook up test interrupt handler just for this test */
1134         if (adapter->msix_entries) {
1135                 if (request_irq(adapter->msix_entries[0].vector,
1136                                 &igb_test_intr, 0, netdev->name, adapter)) {
1137                         *data = 1;
1138                         return -1;
1139                 }
1140         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1141                 shared_int = false;
1142                 if (request_irq(irq,
1143                                 &igb_test_intr, 0, netdev->name, adapter)) {
1144                         *data = 1;
1145                         return -1;
1146                 }
1147         } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1148                                 netdev->name, adapter)) {
1149                 shared_int = false;
1150         } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1151                  netdev->name, adapter)) {
1152                 *data = 1;
1153                 return -1;
1154         }
1155         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1156                 (shared_int ? "shared" : "unshared"));
1157
1158         /* Disable all the interrupts */
1159         wr32(E1000_IMC, ~0);
1160         msleep(10);
1161
1162         /* Define all writable bits for ICS */
1163         switch (hw->mac.type) {
1164         case e1000_82575:
1165                 ics_mask = 0x37F47EDD;
1166                 break;
1167         case e1000_82576:
1168                 ics_mask = 0x77D4FBFD;
1169                 break;
1170         default:
1171                 ics_mask = 0x7FFFFFFF;
1172                 break;
1173         }
1174
1175         /* Test each interrupt */
1176         for (; i < 31; i++) {
1177                 /* Interrupt to test */
1178                 mask = 1 << i;
1179
1180                 if (!(mask & ics_mask))
1181                         continue;
1182
1183                 if (!shared_int) {
1184                         /* Disable the interrupt to be reported in
1185                          * the cause register and then force the same
1186                          * interrupt and see if one gets posted.  If
1187                          * an interrupt was posted to the bus, the
1188                          * test failed.
1189                          */
1190                         adapter->test_icr = 0;
1191
1192                         /* Flush any pending interrupts */
1193                         wr32(E1000_ICR, ~0);
1194
1195                         wr32(E1000_IMC, mask);
1196                         wr32(E1000_ICS, mask);
1197                         msleep(10);
1198
1199                         if (adapter->test_icr & mask) {
1200                                 *data = 3;
1201                                 break;
1202                         }
1203                 }
1204
1205                 /* Enable the interrupt to be reported in
1206                  * the cause register and then force the same
1207                  * interrupt and see if one gets posted.  If
1208                  * an interrupt was not posted to the bus, the
1209                  * test failed.
1210                  */
1211                 adapter->test_icr = 0;
1212
1213                 /* Flush any pending interrupts */
1214                 wr32(E1000_ICR, ~0);
1215
1216                 wr32(E1000_IMS, mask);
1217                 wr32(E1000_ICS, mask);
1218                 msleep(10);
1219
1220                 if (!(adapter->test_icr & mask)) {
1221                         *data = 4;
1222                         break;
1223                 }
1224
1225                 if (!shared_int) {
1226                         /* Disable the other interrupts to be reported in
1227                          * the cause register and then force the other
1228                          * interrupts and see if any get posted.  If
1229                          * an interrupt was posted to the bus, the
1230                          * test failed.
1231                          */
1232                         adapter->test_icr = 0;
1233
1234                         /* Flush any pending interrupts */
1235                         wr32(E1000_ICR, ~0);
1236
1237                         wr32(E1000_IMC, ~mask);
1238                         wr32(E1000_ICS, ~mask);
1239                         msleep(10);
1240
1241                         if (adapter->test_icr & mask) {
1242                                 *data = 5;
1243                                 break;
1244                         }
1245                 }
1246         }
1247
1248         /* Disable all the interrupts */
1249         wr32(E1000_IMC, ~0);
1250         msleep(10);
1251
1252         /* Unhook test interrupt handler */
1253         if (adapter->msix_entries)
1254                 free_irq(adapter->msix_entries[0].vector, adapter);
1255         else
1256                 free_irq(irq, adapter);
1257
1258         return *data;
1259 }
1260
1261 static void igb_free_desc_rings(struct igb_adapter *adapter)
1262 {
1263         igb_free_tx_resources(&adapter->test_tx_ring);
1264         igb_free_rx_resources(&adapter->test_rx_ring);
1265 }
1266
1267 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1268 {
1269         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1270         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1271         struct e1000_hw *hw = &adapter->hw;
1272         int ret_val;
1273
1274         /* Setup Tx descriptor ring and Tx buffers */
1275         tx_ring->count = IGB_DEFAULT_TXD;
1276         tx_ring->pdev = adapter->pdev;
1277         tx_ring->netdev = adapter->netdev;
1278         tx_ring->reg_idx = adapter->vfs_allocated_count;
1279
1280         if (igb_setup_tx_resources(tx_ring)) {
1281                 ret_val = 1;
1282                 goto err_nomem;
1283         }
1284
1285         igb_setup_tctl(adapter);
1286         igb_configure_tx_ring(adapter, tx_ring);
1287
1288         /* Setup Rx descriptor ring and Rx buffers */
1289         rx_ring->count = IGB_DEFAULT_RXD;
1290         rx_ring->pdev = adapter->pdev;
1291         rx_ring->netdev = adapter->netdev;
1292         rx_ring->rx_buffer_len = IGB_RXBUFFER_2048;
1293         rx_ring->reg_idx = adapter->vfs_allocated_count;
1294
1295         if (igb_setup_rx_resources(rx_ring)) {
1296                 ret_val = 3;
1297                 goto err_nomem;
1298         }
1299
1300         /* set the default queue to queue 0 of PF */
1301         wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1302
1303         /* enable receive ring */
1304         igb_setup_rctl(adapter);
1305         igb_configure_rx_ring(adapter, rx_ring);
1306
1307         igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring));
1308
1309         return 0;
1310
1311 err_nomem:
1312         igb_free_desc_rings(adapter);
1313         return ret_val;
1314 }
1315
1316 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1317 {
1318         struct e1000_hw *hw = &adapter->hw;
1319
1320         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1321         igb_write_phy_reg(hw, 29, 0x001F);
1322         igb_write_phy_reg(hw, 30, 0x8FFC);
1323         igb_write_phy_reg(hw, 29, 0x001A);
1324         igb_write_phy_reg(hw, 30, 0x8FF0);
1325 }
1326
1327 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1328 {
1329         struct e1000_hw *hw = &adapter->hw;
1330         u32 ctrl_reg = 0;
1331
1332         hw->mac.autoneg = false;
1333
1334         if (hw->phy.type == e1000_phy_m88) {
1335                 /* Auto-MDI/MDIX Off */
1336                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1337                 /* reset to update Auto-MDI/MDIX */
1338                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1339                 /* autoneg off */
1340                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1341         }
1342
1343         ctrl_reg = rd32(E1000_CTRL);
1344
1345         /* force 1000, set loopback */
1346         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1347
1348         /* Now set up the MAC to the same speed/duplex as the PHY. */
1349         ctrl_reg = rd32(E1000_CTRL);
1350         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1351         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1352                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1353                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1354                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1355                      E1000_CTRL_SLU);    /* Set link up enable bit */
1356
1357         if (hw->phy.type == e1000_phy_m88)
1358                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1359
1360         wr32(E1000_CTRL, ctrl_reg);
1361
1362         /* Disable the receiver on the PHY so when a cable is plugged in, the
1363          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1364          */
1365         if (hw->phy.type == e1000_phy_m88)
1366                 igb_phy_disable_receiver(adapter);
1367
1368         udelay(500);
1369
1370         return 0;
1371 }
1372
1373 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1374 {
1375         return igb_integrated_phy_loopback(adapter);
1376 }
1377
1378 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1379 {
1380         struct e1000_hw *hw = &adapter->hw;
1381         u32 reg;
1382
1383         reg = rd32(E1000_CTRL_EXT);
1384
1385         /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1386         if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1387                 reg = rd32(E1000_RCTL);
1388                 reg |= E1000_RCTL_LBM_TCVR;
1389                 wr32(E1000_RCTL, reg);
1390
1391                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1392
1393                 reg = rd32(E1000_CTRL);
1394                 reg &= ~(E1000_CTRL_RFCE |
1395                          E1000_CTRL_TFCE |
1396                          E1000_CTRL_LRST);
1397                 reg |= E1000_CTRL_SLU |
1398                        E1000_CTRL_FD;
1399                 wr32(E1000_CTRL, reg);
1400
1401                 /* Unset switch control to serdes energy detect */
1402                 reg = rd32(E1000_CONNSW);
1403                 reg &= ~E1000_CONNSW_ENRGSRC;
1404                 wr32(E1000_CONNSW, reg);
1405
1406                 /* Set PCS register for forced speed */
1407                 reg = rd32(E1000_PCS_LCTL);
1408                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1409                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1410                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1411                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1412                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1413                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1414                 wr32(E1000_PCS_LCTL, reg);
1415
1416                 return 0;
1417         }
1418
1419         return igb_set_phy_loopback(adapter);
1420 }
1421
1422 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1423 {
1424         struct e1000_hw *hw = &adapter->hw;
1425         u32 rctl;
1426         u16 phy_reg;
1427
1428         rctl = rd32(E1000_RCTL);
1429         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1430         wr32(E1000_RCTL, rctl);
1431
1432         hw->mac.autoneg = true;
1433         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1434         if (phy_reg & MII_CR_LOOPBACK) {
1435                 phy_reg &= ~MII_CR_LOOPBACK;
1436                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1437                 igb_phy_sw_reset(hw);
1438         }
1439 }
1440
1441 static void igb_create_lbtest_frame(struct sk_buff *skb,
1442                                     unsigned int frame_size)
1443 {
1444         memset(skb->data, 0xFF, frame_size);
1445         frame_size /= 2;
1446         memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1447         memset(&skb->data[frame_size + 10], 0xBE, 1);
1448         memset(&skb->data[frame_size + 12], 0xAF, 1);
1449 }
1450
1451 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1452 {
1453         frame_size /= 2;
1454         if (*(skb->data + 3) == 0xFF) {
1455                 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1456                    (*(skb->data + frame_size + 12) == 0xAF)) {
1457                         return 0;
1458                 }
1459         }
1460         return 13;
1461 }
1462
1463 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1464                                 struct igb_ring *tx_ring,
1465                                 unsigned int size)
1466 {
1467         union e1000_adv_rx_desc *rx_desc;
1468         struct igb_buffer *buffer_info;
1469         int rx_ntc, tx_ntc, count = 0;
1470         u32 staterr;
1471
1472         /* initialize next to clean and descriptor values */
1473         rx_ntc = rx_ring->next_to_clean;
1474         tx_ntc = tx_ring->next_to_clean;
1475         rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1476         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1477
1478         while (staterr & E1000_RXD_STAT_DD) {
1479                 /* check rx buffer */
1480                 buffer_info = &rx_ring->buffer_info[rx_ntc];
1481
1482                 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
1483                 pci_unmap_single(rx_ring->pdev,
1484                                  buffer_info->dma,
1485                                  rx_ring->rx_buffer_len,
1486                                  PCI_DMA_FROMDEVICE);
1487                 buffer_info->dma = 0;
1488
1489                 /* verify contents of skb */
1490                 if (!igb_check_lbtest_frame(buffer_info->skb, size))
1491                         count++;
1492
1493                 /* unmap buffer on tx side */
1494                 buffer_info = &tx_ring->buffer_info[tx_ntc];
1495                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
1496
1497                 /* increment rx/tx next to clean counters */
1498                 rx_ntc++;
1499                 if (rx_ntc == rx_ring->count)
1500                         rx_ntc = 0;
1501                 tx_ntc++;
1502                 if (tx_ntc == tx_ring->count)
1503                         tx_ntc = 0;
1504
1505                 /* fetch next descriptor */
1506                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1507                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1508         }
1509
1510         /* re-map buffers to ring, store next to clean values */
1511         igb_alloc_rx_buffers_adv(rx_ring, count);
1512         rx_ring->next_to_clean = rx_ntc;
1513         tx_ring->next_to_clean = tx_ntc;
1514
1515         return count;
1516 }
1517
1518 static int igb_run_loopback_test(struct igb_adapter *adapter)
1519 {
1520         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1521         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1522         int i, j, lc, good_cnt, ret_val = 0;
1523         unsigned int size = 1024;
1524         netdev_tx_t tx_ret_val;
1525         struct sk_buff *skb;
1526
1527         /* allocate test skb */
1528         skb = alloc_skb(size, GFP_KERNEL);
1529         if (!skb)
1530                 return 11;
1531
1532         /* place data into test skb */
1533         igb_create_lbtest_frame(skb, size);
1534         skb_put(skb, size);
1535
1536         /*
1537          * Calculate the loop count based on the largest descriptor ring
1538          * The idea is to wrap the largest ring a number of times using 64
1539          * send/receive pairs during each loop
1540          */
1541
1542         if (rx_ring->count <= tx_ring->count)
1543                 lc = ((tx_ring->count / 64) * 2) + 1;
1544         else
1545                 lc = ((rx_ring->count / 64) * 2) + 1;
1546
1547         for (j = 0; j <= lc; j++) { /* loop count loop */
1548                 /* reset count of good packets */
1549                 good_cnt = 0;
1550
1551                 /* place 64 packets on the transmit queue*/
1552                 for (i = 0; i < 64; i++) {
1553                         skb_get(skb);
1554                         tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring);
1555                         if (tx_ret_val == NETDEV_TX_OK)
1556                                 good_cnt++;
1557                 }
1558
1559                 if (good_cnt != 64) {
1560                         ret_val = 12;
1561                         break;
1562                 }
1563
1564                 /* allow 200 milliseconds for packets to go from tx to rx */
1565                 msleep(200);
1566
1567                 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1568                 if (good_cnt != 64) {
1569                         ret_val = 13;
1570                         break;
1571                 }
1572         } /* end loop count loop */
1573
1574         /* free the original skb */
1575         kfree_skb(skb);
1576
1577         return ret_val;
1578 }
1579
1580 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1581 {
1582         /* PHY loopback cannot be performed if SoL/IDER
1583          * sessions are active */
1584         if (igb_check_reset_block(&adapter->hw)) {
1585                 dev_err(&adapter->pdev->dev,
1586                         "Cannot do PHY loopback test "
1587                         "when SoL/IDER is active.\n");
1588                 *data = 0;
1589                 goto out;
1590         }
1591         *data = igb_setup_desc_rings(adapter);
1592         if (*data)
1593                 goto out;
1594         *data = igb_setup_loopback_test(adapter);
1595         if (*data)
1596                 goto err_loopback;
1597         *data = igb_run_loopback_test(adapter);
1598         igb_loopback_cleanup(adapter);
1599
1600 err_loopback:
1601         igb_free_desc_rings(adapter);
1602 out:
1603         return *data;
1604 }
1605
1606 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1607 {
1608         struct e1000_hw *hw = &adapter->hw;
1609         *data = 0;
1610         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1611                 int i = 0;
1612                 hw->mac.serdes_has_link = false;
1613
1614                 /* On some blade server designs, link establishment
1615                  * could take as long as 2-3 minutes */
1616                 do {
1617                         hw->mac.ops.check_for_link(&adapter->hw);
1618                         if (hw->mac.serdes_has_link)
1619                                 return *data;
1620                         msleep(20);
1621                 } while (i++ < 3750);
1622
1623                 *data = 1;
1624         } else {
1625                 hw->mac.ops.check_for_link(&adapter->hw);
1626                 if (hw->mac.autoneg)
1627                         msleep(4000);
1628
1629                 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1630                         *data = 1;
1631         }
1632         return *data;
1633 }
1634
1635 static void igb_diag_test(struct net_device *netdev,
1636                           struct ethtool_test *eth_test, u64 *data)
1637 {
1638         struct igb_adapter *adapter = netdev_priv(netdev);
1639         u16 autoneg_advertised;
1640         u8 forced_speed_duplex, autoneg;
1641         bool if_running = netif_running(netdev);
1642
1643         set_bit(__IGB_TESTING, &adapter->state);
1644         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1645                 /* Offline tests */
1646
1647                 /* save speed, duplex, autoneg settings */
1648                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1649                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1650                 autoneg = adapter->hw.mac.autoneg;
1651
1652                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1653
1654                 /* Link test performed before hardware reset so autoneg doesn't
1655                  * interfere with test result */
1656                 if (igb_link_test(adapter, &data[4]))
1657                         eth_test->flags |= ETH_TEST_FL_FAILED;
1658
1659                 if (if_running)
1660                         /* indicate we're in test mode */
1661                         dev_close(netdev);
1662                 else
1663                         igb_reset(adapter);
1664
1665                 if (igb_reg_test(adapter, &data[0]))
1666                         eth_test->flags |= ETH_TEST_FL_FAILED;
1667
1668                 igb_reset(adapter);
1669                 if (igb_eeprom_test(adapter, &data[1]))
1670                         eth_test->flags |= ETH_TEST_FL_FAILED;
1671
1672                 igb_reset(adapter);
1673                 if (igb_intr_test(adapter, &data[2]))
1674                         eth_test->flags |= ETH_TEST_FL_FAILED;
1675
1676                 igb_reset(adapter);
1677                 if (igb_loopback_test(adapter, &data[3]))
1678                         eth_test->flags |= ETH_TEST_FL_FAILED;
1679
1680                 /* restore speed, duplex, autoneg settings */
1681                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1682                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1683                 adapter->hw.mac.autoneg = autoneg;
1684
1685                 /* force this routine to wait until autoneg complete/timeout */
1686                 adapter->hw.phy.autoneg_wait_to_complete = true;
1687                 igb_reset(adapter);
1688                 adapter->hw.phy.autoneg_wait_to_complete = false;
1689
1690                 clear_bit(__IGB_TESTING, &adapter->state);
1691                 if (if_running)
1692                         dev_open(netdev);
1693         } else {
1694                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1695                 /* Online tests */
1696                 if (igb_link_test(adapter, &data[4]))
1697                         eth_test->flags |= ETH_TEST_FL_FAILED;
1698
1699                 /* Online tests aren't run; pass by default */
1700                 data[0] = 0;
1701                 data[1] = 0;
1702                 data[2] = 0;
1703                 data[3] = 0;
1704
1705                 clear_bit(__IGB_TESTING, &adapter->state);
1706         }
1707         msleep_interruptible(4 * 1000);
1708 }
1709
1710 static int igb_wol_exclusion(struct igb_adapter *adapter,
1711                              struct ethtool_wolinfo *wol)
1712 {
1713         struct e1000_hw *hw = &adapter->hw;
1714         int retval = 1; /* fail by default */
1715
1716         switch (hw->device_id) {
1717         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1718                 /* WoL not supported */
1719                 wol->supported = 0;
1720                 break;
1721         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1722         case E1000_DEV_ID_82576_FIBER:
1723         case E1000_DEV_ID_82576_SERDES:
1724                 /* Wake events not supported on port B */
1725                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1726                         wol->supported = 0;
1727                         break;
1728                 }
1729                 /* return success for non excluded adapter ports */
1730                 retval = 0;
1731                 break;
1732         case E1000_DEV_ID_82576_QUAD_COPPER:
1733                 /* quad port adapters only support WoL on port A */
1734                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1735                         wol->supported = 0;
1736                         break;
1737                 }
1738                 /* return success for non excluded adapter ports */
1739                 retval = 0;
1740                 break;
1741         default:
1742                 /* dual port cards only support WoL on port A from now on
1743                  * unless it was enabled in the eeprom for port B
1744                  * so exclude FUNC_1 ports from having WoL enabled */
1745                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1746                     !adapter->eeprom_wol) {
1747                         wol->supported = 0;
1748                         break;
1749                 }
1750
1751                 retval = 0;
1752         }
1753
1754         return retval;
1755 }
1756
1757 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1758 {
1759         struct igb_adapter *adapter = netdev_priv(netdev);
1760
1761         wol->supported = WAKE_UCAST | WAKE_MCAST |
1762                          WAKE_BCAST | WAKE_MAGIC;
1763         wol->wolopts = 0;
1764
1765         /* this function will set ->supported = 0 and return 1 if wol is not
1766          * supported by this hardware */
1767         if (igb_wol_exclusion(adapter, wol) ||
1768             !device_can_wakeup(&adapter->pdev->dev))
1769                 return;
1770
1771         /* apply any specific unsupported masks here */
1772         switch (adapter->hw.device_id) {
1773         default:
1774                 break;
1775         }
1776
1777         if (adapter->wol & E1000_WUFC_EX)
1778                 wol->wolopts |= WAKE_UCAST;
1779         if (adapter->wol & E1000_WUFC_MC)
1780                 wol->wolopts |= WAKE_MCAST;
1781         if (adapter->wol & E1000_WUFC_BC)
1782                 wol->wolopts |= WAKE_BCAST;
1783         if (adapter->wol & E1000_WUFC_MAG)
1784                 wol->wolopts |= WAKE_MAGIC;
1785
1786         return;
1787 }
1788
1789 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1790 {
1791         struct igb_adapter *adapter = netdev_priv(netdev);
1792
1793         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1794                 return -EOPNOTSUPP;
1795
1796         if (igb_wol_exclusion(adapter, wol) ||
1797             !device_can_wakeup(&adapter->pdev->dev))
1798                 return wol->wolopts ? -EOPNOTSUPP : 0;
1799
1800         /* these settings will always override what we currently have */
1801         adapter->wol = 0;
1802
1803         if (wol->wolopts & WAKE_UCAST)
1804                 adapter->wol |= E1000_WUFC_EX;
1805         if (wol->wolopts & WAKE_MCAST)
1806                 adapter->wol |= E1000_WUFC_MC;
1807         if (wol->wolopts & WAKE_BCAST)
1808                 adapter->wol |= E1000_WUFC_BC;
1809         if (wol->wolopts & WAKE_MAGIC)
1810                 adapter->wol |= E1000_WUFC_MAG;
1811         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1812
1813         return 0;
1814 }
1815
1816 /* bit defines for adapter->led_status */
1817 #define IGB_LED_ON              0
1818
1819 static int igb_phys_id(struct net_device *netdev, u32 data)
1820 {
1821         struct igb_adapter *adapter = netdev_priv(netdev);
1822         struct e1000_hw *hw = &adapter->hw;
1823         unsigned long timeout;
1824
1825         timeout = data * 1000;
1826
1827         /*
1828          *  msleep_interruptable only accepts unsigned int so we are limited
1829          * in how long a duration we can wait
1830          */
1831         if (!timeout || timeout > UINT_MAX)
1832                 timeout = UINT_MAX;
1833
1834         igb_blink_led(hw);
1835         msleep_interruptible(timeout);
1836
1837         igb_led_off(hw);
1838         clear_bit(IGB_LED_ON, &adapter->led_status);
1839         igb_cleanup_led(hw);
1840
1841         return 0;
1842 }
1843
1844 static int igb_set_coalesce(struct net_device *netdev,
1845                             struct ethtool_coalesce *ec)
1846 {
1847         struct igb_adapter *adapter = netdev_priv(netdev);
1848         int i;
1849
1850         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1851             ((ec->rx_coalesce_usecs > 3) &&
1852              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1853             (ec->rx_coalesce_usecs == 2))
1854                 return -EINVAL;
1855
1856         if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1857             ((ec->tx_coalesce_usecs > 3) &&
1858              (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1859             (ec->tx_coalesce_usecs == 2))
1860                 return -EINVAL;
1861
1862         if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
1863                 return -EINVAL;
1864
1865         /* convert to rate of irq's per second */
1866         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
1867                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
1868         else
1869                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
1870
1871         /* convert to rate of irq's per second */
1872         if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
1873                 adapter->tx_itr_setting = adapter->rx_itr_setting;
1874         else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
1875                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
1876         else
1877                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
1878
1879         for (i = 0; i < adapter->num_q_vectors; i++) {
1880                 struct igb_q_vector *q_vector = adapter->q_vector[i];
1881                 if (q_vector->rx_ring)
1882                         q_vector->itr_val = adapter->rx_itr_setting;
1883                 else
1884                         q_vector->itr_val = adapter->tx_itr_setting;
1885                 if (q_vector->itr_val && q_vector->itr_val <= 3)
1886                         q_vector->itr_val = IGB_START_ITR;
1887                 q_vector->set_itr = 1;
1888         }
1889
1890         return 0;
1891 }
1892
1893 static int igb_get_coalesce(struct net_device *netdev,
1894                             struct ethtool_coalesce *ec)
1895 {
1896         struct igb_adapter *adapter = netdev_priv(netdev);
1897
1898         if (adapter->rx_itr_setting <= 3)
1899                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
1900         else
1901                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
1902
1903         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
1904                 if (adapter->tx_itr_setting <= 3)
1905                         ec->tx_coalesce_usecs = adapter->tx_itr_setting;
1906                 else
1907                         ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
1908         }
1909
1910         return 0;
1911 }
1912
1913 static int igb_nway_reset(struct net_device *netdev)
1914 {
1915         struct igb_adapter *adapter = netdev_priv(netdev);
1916         if (netif_running(netdev))
1917                 igb_reinit_locked(adapter);
1918         return 0;
1919 }
1920
1921 static int igb_get_sset_count(struct net_device *netdev, int sset)
1922 {
1923         switch (sset) {
1924         case ETH_SS_STATS:
1925                 return IGB_STATS_LEN;
1926         case ETH_SS_TEST:
1927                 return IGB_TEST_LEN;
1928         default:
1929                 return -ENOTSUPP;
1930         }
1931 }
1932
1933 static void igb_get_ethtool_stats(struct net_device *netdev,
1934                                   struct ethtool_stats *stats, u64 *data)
1935 {
1936         struct igb_adapter *adapter = netdev_priv(netdev);
1937         struct net_device_stats *net_stats = &netdev->stats;
1938         u64 *queue_stat;
1939         int i, j, k;
1940         char *p;
1941
1942         igb_update_stats(adapter);
1943
1944         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1945                 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
1946                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1947                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1948         }
1949         for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
1950                 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
1951                 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
1952                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1953         }
1954         for (j = 0; j < adapter->num_tx_queues; j++) {
1955                 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1956                 for (k = 0; k < IGB_TX_QUEUE_STATS_LEN; k++, i++)
1957                         data[i] = queue_stat[k];
1958         }
1959         for (j = 0; j < adapter->num_rx_queues; j++) {
1960                 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1961                 for (k = 0; k < IGB_RX_QUEUE_STATS_LEN; k++, i++)
1962                         data[i] = queue_stat[k];
1963         }
1964 }
1965
1966 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1967 {
1968         struct igb_adapter *adapter = netdev_priv(netdev);
1969         u8 *p = data;
1970         int i;
1971
1972         switch (stringset) {
1973         case ETH_SS_TEST:
1974                 memcpy(data, *igb_gstrings_test,
1975                         IGB_TEST_LEN*ETH_GSTRING_LEN);
1976                 break;
1977         case ETH_SS_STATS:
1978                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1979                         memcpy(p, igb_gstrings_stats[i].stat_string,
1980                                ETH_GSTRING_LEN);
1981                         p += ETH_GSTRING_LEN;
1982                 }
1983                 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
1984                         memcpy(p, igb_gstrings_net_stats[i].stat_string,
1985                                ETH_GSTRING_LEN);
1986                         p += ETH_GSTRING_LEN;
1987                 }
1988                 for (i = 0; i < adapter->num_tx_queues; i++) {
1989                         sprintf(p, "tx_queue_%u_packets", i);
1990                         p += ETH_GSTRING_LEN;
1991                         sprintf(p, "tx_queue_%u_bytes", i);
1992                         p += ETH_GSTRING_LEN;
1993                         sprintf(p, "tx_queue_%u_restart", i);
1994                         p += ETH_GSTRING_LEN;
1995                 }
1996                 for (i = 0; i < adapter->num_rx_queues; i++) {
1997                         sprintf(p, "rx_queue_%u_packets", i);
1998                         p += ETH_GSTRING_LEN;
1999                         sprintf(p, "rx_queue_%u_bytes", i);
2000                         p += ETH_GSTRING_LEN;
2001                         sprintf(p, "rx_queue_%u_drops", i);
2002                         p += ETH_GSTRING_LEN;
2003                         sprintf(p, "rx_queue_%u_csum_err", i);
2004                         p += ETH_GSTRING_LEN;
2005                         sprintf(p, "rx_queue_%u_alloc_failed", i);
2006                         p += ETH_GSTRING_LEN;
2007                 }
2008 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2009                 break;
2010         }
2011 }
2012
2013 static const struct ethtool_ops igb_ethtool_ops = {
2014         .get_settings           = igb_get_settings,
2015         .set_settings           = igb_set_settings,
2016         .get_drvinfo            = igb_get_drvinfo,
2017         .get_regs_len           = igb_get_regs_len,
2018         .get_regs               = igb_get_regs,
2019         .get_wol                = igb_get_wol,
2020         .set_wol                = igb_set_wol,
2021         .get_msglevel           = igb_get_msglevel,
2022         .set_msglevel           = igb_set_msglevel,
2023         .nway_reset             = igb_nway_reset,
2024         .get_link               = ethtool_op_get_link,
2025         .get_eeprom_len         = igb_get_eeprom_len,
2026         .get_eeprom             = igb_get_eeprom,
2027         .set_eeprom             = igb_set_eeprom,
2028         .get_ringparam          = igb_get_ringparam,
2029         .set_ringparam          = igb_set_ringparam,
2030         .get_pauseparam         = igb_get_pauseparam,
2031         .set_pauseparam         = igb_set_pauseparam,
2032         .get_rx_csum            = igb_get_rx_csum,
2033         .set_rx_csum            = igb_set_rx_csum,
2034         .get_tx_csum            = igb_get_tx_csum,
2035         .set_tx_csum            = igb_set_tx_csum,
2036         .get_sg                 = ethtool_op_get_sg,
2037         .set_sg                 = ethtool_op_set_sg,
2038         .get_tso                = ethtool_op_get_tso,
2039         .set_tso                = igb_set_tso,
2040         .self_test              = igb_diag_test,
2041         .get_strings            = igb_get_strings,
2042         .phys_id                = igb_phys_id,
2043         .get_sset_count         = igb_get_sset_count,
2044         .get_ethtool_stats      = igb_get_ethtool_stats,
2045         .get_coalesce           = igb_get_coalesce,
2046         .set_coalesce           = igb_set_coalesce,
2047 };
2048
2049 void igb_set_ethtool_ops(struct net_device *netdev)
2050 {
2051         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2052 }