1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _E1000_82575_H_
29 #define _E1000_82575_H_
31 void igb_update_mc_addr_list(struct e1000_hw*, u8*, u32, u32, u32);
32 extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
33 extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
35 #define E1000_RAR_ENTRIES_82575 16
36 #define E1000_RAR_ENTRIES_82576 24
38 /* SRRCTL bit definitions */
39 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
40 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
41 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
42 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
44 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
45 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
46 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
47 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
49 #define E1000_EICR_TX_QUEUE ( \
50 E1000_EICR_TX_QUEUE0 | \
51 E1000_EICR_TX_QUEUE1 | \
52 E1000_EICR_TX_QUEUE2 | \
55 #define E1000_EICR_RX_QUEUE ( \
56 E1000_EICR_RX_QUEUE0 | \
57 E1000_EICR_RX_QUEUE1 | \
58 E1000_EICR_RX_QUEUE2 | \
61 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
63 /* Receive Descriptor - Advanced */
64 union e1000_adv_rx_desc {
66 __le64 pkt_addr; /* Packet buffer address */
67 __le64 hdr_addr; /* Header buffer address */
72 __le16 pkt_info; /* RSS type, Packet type */
73 __le16 hdr_info; /* Split Header,
74 * header buffer length */
77 __le32 rss; /* RSS Hash */
79 __le16 ip_id; /* IP id */
80 __le16 csum; /* Packet Checksum */
85 __le32 status_error; /* ext status/error */
86 __le16 length; /* Packet length */
87 __le16 vlan; /* VLAN tag */
92 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
93 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
95 /* Transmit Descriptor - Advanced */
96 union e1000_adv_tx_desc {
98 __le64 buffer_addr; /* Address of descriptor's data buf */
100 __le32 olinfo_status;
103 __le64 rsvd; /* Reserved */
109 /* Adv Transmit Descriptor Config Masks */
110 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
111 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
112 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
113 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
114 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
115 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
116 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
117 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
119 /* Context descriptors */
120 struct e1000_adv_tx_context_desc {
121 __le32 vlan_macip_lens;
123 __le32 type_tucmd_mlhl;
124 __le32 mss_l4len_idx;
127 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
128 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
129 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
130 /* IPSec Encrypt Enable for ESP */
131 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
132 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
133 /* Adv ctxt IPSec SA IDX mask */
134 /* Adv ctxt IPSec ESP len mask */
136 /* Additional Transmit Descriptor Control definitions */
137 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
138 /* Tx Queue Arbitration Priority 0=low, 1=high */
140 /* Additional Receive Descriptor Control definitions */
141 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
143 /* Direct Cache Access (DCA) definitions */
144 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
145 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
147 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
148 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
149 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
150 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
152 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
153 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
154 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
156 /* Additional DCA related definitions, note change in position of CPUID */
157 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
158 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
159 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
160 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */