2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. Without NAPI, the packet(s) will be handled
48 * immediately. Both methods will start at the last known empty
49 * descriptor, and process every subsequent descriptor until there
50 * are none left with data (NAPI will stop after a set number of
51 * packets to give time to other tasks, but will eventually
52 * process all the packets). The data arrives inside a
53 * pre-allocated skb, and so after the skb is passed up to the
54 * stack, a new skb must be allocated, and the address field in
55 * the buffer descriptor must be updated to indicate this new
58 * When the kernel requests that a packet be transmitted, the
59 * driver starts where it left off last time, and points the
60 * descriptor at the buffer which was passed in. The driver
61 * then informs the DMA engine that there are packets ready to
62 * be transmitted. Once the controller is finished transmitting
63 * the packet, an interrupt may be triggered (under the same
64 * conditions as for reception, but depending on the TXF bit).
65 * The driver then cleans up the buffer.
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
82 #include <linux/platform_device.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
98 #include "gianfar_mii.h"
100 #define TX_TIMEOUT (1*HZ)
101 #define SKB_ALLOC_TIMEOUT 1000000
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
105 #ifdef CONFIG_GFAR_NAPI
106 #define RECEIVE(x) netif_receive_skb(x)
108 #define RECEIVE(x) netif_rx(x)
111 const char gfar_driver_name[] = "Gianfar Ethernet";
112 const char gfar_driver_version[] = "1.3";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_timeout(struct net_device *dev);
117 static int gfar_close(struct net_device *dev);
118 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
119 static int gfar_set_mac_address(struct net_device *dev);
120 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
121 static irqreturn_t gfar_error(int irq, void *dev_id);
122 static irqreturn_t gfar_transmit(int irq, void *dev_id);
123 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
124 static void adjust_link(struct net_device *dev);
125 static void init_registers(struct net_device *dev);
126 static int init_phy(struct net_device *dev);
127 static int gfar_probe(struct platform_device *pdev);
128 static int gfar_remove(struct platform_device *pdev);
129 static void free_skb_resources(struct gfar_private *priv);
130 static void gfar_set_multi(struct net_device *dev);
131 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
132 static void gfar_configure_serdes(struct net_device *dev);
133 extern int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id, int regnum, u16 value);
134 extern int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum);
135 #ifdef CONFIG_GFAR_NAPI
136 static int gfar_poll(struct napi_struct *napi, int budget);
138 #ifdef CONFIG_NET_POLL_CONTROLLER
139 static void gfar_netpoll(struct net_device *dev);
141 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
142 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
143 static void gfar_vlan_rx_register(struct net_device *netdev,
144 struct vlan_group *grp);
145 void gfar_halt(struct net_device *dev);
146 void gfar_start(struct net_device *dev);
147 static void gfar_clear_exact_match(struct net_device *dev);
148 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
150 extern const struct ethtool_ops gfar_ethtool_ops;
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
156 /* Returns 1 if incoming frames use an FCB */
157 static inline int gfar_uses_fcb(struct gfar_private *priv)
159 return (priv->vlan_enable || priv->rx_csum_enable);
162 /* Set up the ethernet device structure, private data,
163 * and anything else we need before we start */
164 static int gfar_probe(struct platform_device *pdev)
167 struct net_device *dev = NULL;
168 struct gfar_private *priv = NULL;
169 struct gianfar_platform_data *einfo;
172 DECLARE_MAC_BUF(mac);
174 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
177 printk(KERN_ERR "gfar %d: Missing additional data!\n",
183 /* Create an ethernet device instance */
184 dev = alloc_etherdev(sizeof (*priv));
189 priv = netdev_priv(dev);
192 /* Set the info in the priv to the current info */
195 /* fill out IRQ fields */
196 if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
197 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
198 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
199 priv->interruptError = platform_get_irq_byname(pdev, "error");
200 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
203 priv->interruptTransmit = platform_get_irq(pdev, 0);
204 if (priv->interruptTransmit < 0)
208 /* get a pointer to the register memory */
209 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
210 priv->regs = ioremap(r->start, sizeof (struct gfar));
212 if (NULL == priv->regs) {
217 spin_lock_init(&priv->txlock);
218 spin_lock_init(&priv->rxlock);
220 platform_set_drvdata(pdev, dev);
222 /* Stop the DMA engine now, in case it was running before */
223 /* (The firmware could have used it, and left it running). */
224 /* To do this, we write Graceful Receive Stop and Graceful */
225 /* Transmit Stop, and then wait until the corresponding bits */
226 /* in IEVENT indicate the stops have completed. */
227 tempval = gfar_read(&priv->regs->dmactrl);
228 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
229 gfar_write(&priv->regs->dmactrl, tempval);
231 tempval = gfar_read(&priv->regs->dmactrl);
232 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
233 gfar_write(&priv->regs->dmactrl, tempval);
235 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
238 /* Reset MAC layer */
239 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
241 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
242 gfar_write(&priv->regs->maccfg1, tempval);
244 /* Initialize MACCFG2. */
245 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
247 /* Initialize ECNTRL */
248 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
250 /* Copy the station address into the dev structure, */
251 memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
253 /* Set the dev->base_addr to the gfar reg region */
254 dev->base_addr = (unsigned long) (priv->regs);
256 SET_NETDEV_DEV(dev, &pdev->dev);
258 /* Fill in the dev structure */
259 dev->open = gfar_enet_open;
260 dev->hard_start_xmit = gfar_start_xmit;
261 dev->tx_timeout = gfar_timeout;
262 dev->watchdog_timeo = TX_TIMEOUT;
263 #ifdef CONFIG_GFAR_NAPI
264 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267 dev->poll_controller = gfar_netpoll;
269 dev->stop = gfar_close;
270 dev->change_mtu = gfar_change_mtu;
272 dev->set_multicast_list = gfar_set_multi;
274 dev->ethtool_ops = &gfar_ethtool_ops;
276 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
277 priv->rx_csum_enable = 1;
278 dev->features |= NETIF_F_IP_CSUM;
280 priv->rx_csum_enable = 0;
284 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
285 dev->vlan_rx_register = gfar_vlan_rx_register;
287 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
289 priv->vlan_enable = 1;
292 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
293 priv->extended_hash = 1;
294 priv->hash_width = 9;
296 priv->hash_regs[0] = &priv->regs->igaddr0;
297 priv->hash_regs[1] = &priv->regs->igaddr1;
298 priv->hash_regs[2] = &priv->regs->igaddr2;
299 priv->hash_regs[3] = &priv->regs->igaddr3;
300 priv->hash_regs[4] = &priv->regs->igaddr4;
301 priv->hash_regs[5] = &priv->regs->igaddr5;
302 priv->hash_regs[6] = &priv->regs->igaddr6;
303 priv->hash_regs[7] = &priv->regs->igaddr7;
304 priv->hash_regs[8] = &priv->regs->gaddr0;
305 priv->hash_regs[9] = &priv->regs->gaddr1;
306 priv->hash_regs[10] = &priv->regs->gaddr2;
307 priv->hash_regs[11] = &priv->regs->gaddr3;
308 priv->hash_regs[12] = &priv->regs->gaddr4;
309 priv->hash_regs[13] = &priv->regs->gaddr5;
310 priv->hash_regs[14] = &priv->regs->gaddr6;
311 priv->hash_regs[15] = &priv->regs->gaddr7;
314 priv->extended_hash = 0;
315 priv->hash_width = 8;
317 priv->hash_regs[0] = &priv->regs->gaddr0;
318 priv->hash_regs[1] = &priv->regs->gaddr1;
319 priv->hash_regs[2] = &priv->regs->gaddr2;
320 priv->hash_regs[3] = &priv->regs->gaddr3;
321 priv->hash_regs[4] = &priv->regs->gaddr4;
322 priv->hash_regs[5] = &priv->regs->gaddr5;
323 priv->hash_regs[6] = &priv->regs->gaddr6;
324 priv->hash_regs[7] = &priv->regs->gaddr7;
327 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
328 priv->padding = DEFAULT_PADDING;
332 if (dev->features & NETIF_F_IP_CSUM)
333 dev->hard_header_len += GMAC_FCB_LEN;
335 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
336 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
337 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
339 priv->txcoalescing = DEFAULT_TX_COALESCE;
340 priv->txcount = DEFAULT_TXCOUNT;
341 priv->txtime = DEFAULT_TXTIME;
342 priv->rxcoalescing = DEFAULT_RX_COALESCE;
343 priv->rxcount = DEFAULT_RXCOUNT;
344 priv->rxtime = DEFAULT_RXTIME;
346 /* Enable most messages by default */
347 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
349 err = register_netdev(dev);
352 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
357 /* Create all the sysfs files */
358 gfar_init_sysfs(dev);
360 /* Print out the device info */
361 printk(KERN_INFO DEVICE_NAME "%s\n",
362 dev->name, print_mac(mac, dev->dev_addr));
364 /* Even more device info helps when determining which kernel */
365 /* provided which set of benchmarks. */
366 #ifdef CONFIG_GFAR_NAPI
367 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
369 printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
371 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
372 dev->name, priv->rx_ring_size, priv->tx_ring_size);
383 static int gfar_remove(struct platform_device *pdev)
385 struct net_device *dev = platform_get_drvdata(pdev);
386 struct gfar_private *priv = netdev_priv(dev);
388 platform_set_drvdata(pdev, NULL);
397 /* Reads the controller's registers to determine what interface
398 * connects it to the PHY.
400 static phy_interface_t gfar_get_interface(struct net_device *dev)
402 struct gfar_private *priv = netdev_priv(dev);
403 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
405 if (ecntrl & ECNTRL_SGMII_MODE)
406 return PHY_INTERFACE_MODE_SGMII;
408 if (ecntrl & ECNTRL_TBI_MODE) {
409 if (ecntrl & ECNTRL_REDUCED_MODE)
410 return PHY_INTERFACE_MODE_RTBI;
412 return PHY_INTERFACE_MODE_TBI;
415 if (ecntrl & ECNTRL_REDUCED_MODE) {
416 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
417 return PHY_INTERFACE_MODE_RMII;
419 phy_interface_t interface = priv->einfo->interface;
422 * This isn't autodetected right now, so it must
423 * be set by the device tree or platform code.
425 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
426 return PHY_INTERFACE_MODE_RGMII_ID;
428 return PHY_INTERFACE_MODE_RGMII;
432 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
433 return PHY_INTERFACE_MODE_GMII;
435 return PHY_INTERFACE_MODE_MII;
439 /* Initializes driver's PHY state, and attaches to the PHY.
440 * Returns 0 on success.
442 static int init_phy(struct net_device *dev)
444 struct gfar_private *priv = netdev_priv(dev);
445 uint gigabit_support =
446 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
447 SUPPORTED_1000baseT_Full : 0;
448 struct phy_device *phydev;
449 char phy_id[BUS_ID_SIZE];
450 phy_interface_t interface;
454 priv->oldduplex = -1;
456 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
458 interface = gfar_get_interface(dev);
460 phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
462 if (interface == PHY_INTERFACE_MODE_SGMII)
463 gfar_configure_serdes(dev);
465 if (IS_ERR(phydev)) {
466 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
467 return PTR_ERR(phydev);
470 /* Remove any features not supported by the controller */
471 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
472 phydev->advertising = phydev->supported;
474 priv->phydev = phydev;
479 static void gfar_configure_serdes(struct net_device *dev)
481 struct gfar_private *priv = netdev_priv(dev);
482 struct gfar_mii __iomem *regs =
483 (void __iomem *)&priv->regs->gfar_mii_regs;
485 /* Initialise TBI i/f to communicate with serdes (lynx phy) */
487 /* Single clk mode, mii mode off(for aerdes communication) */
488 gfar_local_mdio_write(regs, TBIPA_VALUE, MII_TBICON, TBICON_CLK_SELECT);
490 /* Supported pause and full-duplex, no half-duplex */
491 gfar_local_mdio_write(regs, TBIPA_VALUE, MII_ADVERTISE,
492 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
493 ADVERTISE_1000XPSE_ASYM);
495 /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
496 gfar_local_mdio_write(regs, TBIPA_VALUE, MII_BMCR, BMCR_ANENABLE |
497 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
500 static void init_registers(struct net_device *dev)
502 struct gfar_private *priv = netdev_priv(dev);
505 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
507 /* Initialize IMASK */
508 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
510 /* Init hash registers to zero */
511 gfar_write(&priv->regs->igaddr0, 0);
512 gfar_write(&priv->regs->igaddr1, 0);
513 gfar_write(&priv->regs->igaddr2, 0);
514 gfar_write(&priv->regs->igaddr3, 0);
515 gfar_write(&priv->regs->igaddr4, 0);
516 gfar_write(&priv->regs->igaddr5, 0);
517 gfar_write(&priv->regs->igaddr6, 0);
518 gfar_write(&priv->regs->igaddr7, 0);
520 gfar_write(&priv->regs->gaddr0, 0);
521 gfar_write(&priv->regs->gaddr1, 0);
522 gfar_write(&priv->regs->gaddr2, 0);
523 gfar_write(&priv->regs->gaddr3, 0);
524 gfar_write(&priv->regs->gaddr4, 0);
525 gfar_write(&priv->regs->gaddr5, 0);
526 gfar_write(&priv->regs->gaddr6, 0);
527 gfar_write(&priv->regs->gaddr7, 0);
529 /* Zero out the rmon mib registers if it has them */
530 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
531 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
533 /* Mask off the CAM interrupts */
534 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
535 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
538 /* Initialize the max receive buffer length */
539 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
541 /* Initialize the Minimum Frame Length Register */
542 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
544 /* Assign the TBI an address which won't conflict with the PHYs */
545 gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
549 /* Halt the receive and transmit queues */
550 void gfar_halt(struct net_device *dev)
552 struct gfar_private *priv = netdev_priv(dev);
553 struct gfar __iomem *regs = priv->regs;
556 /* Mask all interrupts */
557 gfar_write(®s->imask, IMASK_INIT_CLEAR);
559 /* Clear all interrupts */
560 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
562 /* Stop the DMA, and wait for it to stop */
563 tempval = gfar_read(&priv->regs->dmactrl);
564 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
565 != (DMACTRL_GRS | DMACTRL_GTS)) {
566 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
567 gfar_write(&priv->regs->dmactrl, tempval);
569 while (!(gfar_read(&priv->regs->ievent) &
570 (IEVENT_GRSC | IEVENT_GTSC)))
574 /* Disable Rx and Tx */
575 tempval = gfar_read(®s->maccfg1);
576 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
577 gfar_write(®s->maccfg1, tempval);
580 void stop_gfar(struct net_device *dev)
582 struct gfar_private *priv = netdev_priv(dev);
583 struct gfar __iomem *regs = priv->regs;
586 phy_stop(priv->phydev);
589 spin_lock_irqsave(&priv->txlock, flags);
590 spin_lock(&priv->rxlock);
594 spin_unlock(&priv->rxlock);
595 spin_unlock_irqrestore(&priv->txlock, flags);
598 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
599 free_irq(priv->interruptError, dev);
600 free_irq(priv->interruptTransmit, dev);
601 free_irq(priv->interruptReceive, dev);
603 free_irq(priv->interruptTransmit, dev);
606 free_skb_resources(priv);
608 dma_free_coherent(NULL,
609 sizeof(struct txbd8)*priv->tx_ring_size
610 + sizeof(struct rxbd8)*priv->rx_ring_size,
612 gfar_read(®s->tbase0));
615 /* If there are any tx skbs or rx skbs still around, free them.
616 * Then free tx_skbuff and rx_skbuff */
617 static void free_skb_resources(struct gfar_private *priv)
623 /* Go through all the buffer descriptors and free their data buffers */
624 txbdp = priv->tx_bd_base;
626 for (i = 0; i < priv->tx_ring_size; i++) {
628 if (priv->tx_skbuff[i]) {
629 dma_unmap_single(NULL, txbdp->bufPtr,
632 dev_kfree_skb_any(priv->tx_skbuff[i]);
633 priv->tx_skbuff[i] = NULL;
637 kfree(priv->tx_skbuff);
639 rxbdp = priv->rx_bd_base;
641 /* rx_skbuff is not guaranteed to be allocated, so only
642 * free it and its contents if it is allocated */
643 if(priv->rx_skbuff != NULL) {
644 for (i = 0; i < priv->rx_ring_size; i++) {
645 if (priv->rx_skbuff[i]) {
646 dma_unmap_single(NULL, rxbdp->bufPtr,
647 priv->rx_buffer_size,
650 dev_kfree_skb_any(priv->rx_skbuff[i]);
651 priv->rx_skbuff[i] = NULL;
661 kfree(priv->rx_skbuff);
665 void gfar_start(struct net_device *dev)
667 struct gfar_private *priv = netdev_priv(dev);
668 struct gfar __iomem *regs = priv->regs;
671 /* Enable Rx and Tx in MACCFG1 */
672 tempval = gfar_read(®s->maccfg1);
673 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
674 gfar_write(®s->maccfg1, tempval);
676 /* Initialize DMACTRL to have WWR and WOP */
677 tempval = gfar_read(&priv->regs->dmactrl);
678 tempval |= DMACTRL_INIT_SETTINGS;
679 gfar_write(&priv->regs->dmactrl, tempval);
681 /* Make sure we aren't stopped */
682 tempval = gfar_read(&priv->regs->dmactrl);
683 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
684 gfar_write(&priv->regs->dmactrl, tempval);
686 /* Clear THLT/RHLT, so that the DMA starts polling now */
687 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
688 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
690 /* Unmask the interrupts we look for */
691 gfar_write(®s->imask, IMASK_DEFAULT);
694 /* Bring the controller up and running */
695 int startup_gfar(struct net_device *dev)
702 struct gfar_private *priv = netdev_priv(dev);
703 struct gfar __iomem *regs = priv->regs;
708 gfar_write(®s->imask, IMASK_INIT_CLEAR);
710 /* Allocate memory for the buffer descriptors */
711 vaddr = (unsigned long) dma_alloc_coherent(NULL,
712 sizeof (struct txbd8) * priv->tx_ring_size +
713 sizeof (struct rxbd8) * priv->rx_ring_size,
717 if (netif_msg_ifup(priv))
718 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
723 priv->tx_bd_base = (struct txbd8 *) vaddr;
725 /* enet DMA only understands physical addresses */
726 gfar_write(®s->tbase0, addr);
728 /* Start the rx descriptor ring where the tx ring leaves off */
729 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
730 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
731 priv->rx_bd_base = (struct rxbd8 *) vaddr;
732 gfar_write(®s->rbase0, addr);
734 /* Setup the skbuff rings */
736 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
737 priv->tx_ring_size, GFP_KERNEL);
739 if (NULL == priv->tx_skbuff) {
740 if (netif_msg_ifup(priv))
741 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
747 for (i = 0; i < priv->tx_ring_size; i++)
748 priv->tx_skbuff[i] = NULL;
751 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
752 priv->rx_ring_size, GFP_KERNEL);
754 if (NULL == priv->rx_skbuff) {
755 if (netif_msg_ifup(priv))
756 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
762 for (i = 0; i < priv->rx_ring_size; i++)
763 priv->rx_skbuff[i] = NULL;
765 /* Initialize some variables in our dev structure */
766 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
767 priv->cur_rx = priv->rx_bd_base;
768 priv->skb_curtx = priv->skb_dirtytx = 0;
771 /* Initialize Transmit Descriptor Ring */
772 txbdp = priv->tx_bd_base;
773 for (i = 0; i < priv->tx_ring_size; i++) {
780 /* Set the last descriptor in the ring to indicate wrap */
782 txbdp->status |= TXBD_WRAP;
784 rxbdp = priv->rx_bd_base;
785 for (i = 0; i < priv->rx_ring_size; i++) {
786 struct sk_buff *skb = NULL;
790 skb = gfar_new_skb(dev, rxbdp);
792 priv->rx_skbuff[i] = skb;
797 /* Set the last descriptor in the ring to wrap */
799 rxbdp->status |= RXBD_WRAP;
801 /* If the device has multiple interrupts, register for
802 * them. Otherwise, only register for the one */
803 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
804 /* Install our interrupt handlers for Error,
805 * Transmit, and Receive */
806 if (request_irq(priv->interruptError, gfar_error,
807 0, "enet_error", dev) < 0) {
808 if (netif_msg_intr(priv))
809 printk(KERN_ERR "%s: Can't get IRQ %d\n",
810 dev->name, priv->interruptError);
816 if (request_irq(priv->interruptTransmit, gfar_transmit,
817 0, "enet_tx", dev) < 0) {
818 if (netif_msg_intr(priv))
819 printk(KERN_ERR "%s: Can't get IRQ %d\n",
820 dev->name, priv->interruptTransmit);
827 if (request_irq(priv->interruptReceive, gfar_receive,
828 0, "enet_rx", dev) < 0) {
829 if (netif_msg_intr(priv))
830 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
831 dev->name, priv->interruptReceive);
837 if (request_irq(priv->interruptTransmit, gfar_interrupt,
838 0, "gfar_interrupt", dev) < 0) {
839 if (netif_msg_intr(priv))
840 printk(KERN_ERR "%s: Can't get IRQ %d\n",
841 dev->name, priv->interruptError);
848 phy_start(priv->phydev);
850 /* Configure the coalescing support */
851 if (priv->txcoalescing)
852 gfar_write(®s->txic,
853 mk_ic_value(priv->txcount, priv->txtime));
855 gfar_write(®s->txic, 0);
857 if (priv->rxcoalescing)
858 gfar_write(®s->rxic,
859 mk_ic_value(priv->rxcount, priv->rxtime));
861 gfar_write(®s->rxic, 0);
863 if (priv->rx_csum_enable)
864 rctrl |= RCTRL_CHECKSUMMING;
866 if (priv->extended_hash) {
867 rctrl |= RCTRL_EXTHASH;
869 gfar_clear_exact_match(dev);
873 if (priv->vlan_enable)
877 rctrl &= ~RCTRL_PAL_MASK;
878 rctrl |= RCTRL_PADDING(priv->padding);
881 /* Init rctrl based on our settings */
882 gfar_write(&priv->regs->rctrl, rctrl);
884 if (dev->features & NETIF_F_IP_CSUM)
885 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
887 /* Set the extraction length and index */
888 attrs = ATTRELI_EL(priv->rx_stash_size) |
889 ATTRELI_EI(priv->rx_stash_index);
891 gfar_write(&priv->regs->attreli, attrs);
893 /* Start with defaults, and add stashing or locking
894 * depending on the approprate variables */
895 attrs = ATTR_INIT_SETTINGS;
897 if (priv->bd_stash_en)
898 attrs |= ATTR_BDSTASH;
900 if (priv->rx_stash_size != 0)
901 attrs |= ATTR_BUFSTASH;
903 gfar_write(&priv->regs->attr, attrs);
905 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
906 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
907 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
909 /* Start the controller */
915 free_irq(priv->interruptTransmit, dev);
917 free_irq(priv->interruptError, dev);
920 free_skb_resources(priv);
922 dma_free_coherent(NULL,
923 sizeof(struct txbd8)*priv->tx_ring_size
924 + sizeof(struct rxbd8)*priv->rx_ring_size,
926 gfar_read(®s->tbase0));
931 /* Called when something needs to use the ethernet device */
932 /* Returns 0 for success. */
933 static int gfar_enet_open(struct net_device *dev)
935 struct gfar_private *priv = netdev_priv(dev);
938 napi_enable(&priv->napi);
940 /* Initialize a bunch of registers */
943 gfar_set_mac_address(dev);
948 napi_disable(&priv->napi);
952 err = startup_gfar(dev);
954 napi_disable(&priv->napi);
956 netif_start_queue(dev);
961 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
963 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
965 memset(fcb, 0, GMAC_FCB_LEN);
970 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
974 /* If we're here, it's a IP packet with a TCP or UDP
975 * payload. We set it to checksum, using a pseudo-header
978 flags = TXFCB_DEFAULT;
980 /* Tell the controller what the protocol is */
981 /* And provide the already calculated phcs */
982 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
984 fcb->phcs = udp_hdr(skb)->check;
986 fcb->phcs = tcp_hdr(skb)->check;
988 /* l3os is the distance between the start of the
989 * frame (skb->data) and the start of the IP hdr.
990 * l4os is the distance between the start of the
991 * l3 hdr and the l4 hdr */
992 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
993 fcb->l4os = skb_network_header_len(skb);
998 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1000 fcb->flags |= TXFCB_VLN;
1001 fcb->vlctl = vlan_tx_tag_get(skb);
1004 /* This is called by the kernel when a frame is ready for transmission. */
1005 /* It is pointed to by the dev->hard_start_xmit function pointer */
1006 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1008 struct gfar_private *priv = netdev_priv(dev);
1009 struct txfcb *fcb = NULL;
1010 struct txbd8 *txbdp;
1012 unsigned long flags;
1014 /* Update transmit stats */
1015 dev->stats.tx_bytes += skb->len;
1018 spin_lock_irqsave(&priv->txlock, flags);
1020 /* Point at the first free tx descriptor */
1021 txbdp = priv->cur_tx;
1023 /* Clear all but the WRAP status flags */
1024 status = txbdp->status & TXBD_WRAP;
1026 /* Set up checksumming */
1027 if (likely((dev->features & NETIF_F_IP_CSUM)
1028 && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1029 fcb = gfar_add_fcb(skb, txbdp);
1031 gfar_tx_checksum(skb, fcb);
1034 if (priv->vlan_enable &&
1035 unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1036 if (unlikely(NULL == fcb)) {
1037 fcb = gfar_add_fcb(skb, txbdp);
1041 gfar_tx_vlan(skb, fcb);
1044 /* Set buffer length and pointer */
1045 txbdp->length = skb->len;
1046 txbdp->bufPtr = dma_map_single(NULL, skb->data,
1047 skb->len, DMA_TO_DEVICE);
1049 /* Save the skb pointer so we can free it later */
1050 priv->tx_skbuff[priv->skb_curtx] = skb;
1052 /* Update the current skb pointer (wrapping if this was the last) */
1054 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1056 /* Flag the BD as interrupt-causing */
1057 status |= TXBD_INTERRUPT;
1059 /* Flag the BD as ready to go, last in frame, and */
1060 /* in need of CRC */
1061 status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1063 dev->trans_start = jiffies;
1065 /* The powerpc-specific eieio() is used, as wmb() has too strong
1066 * semantics (it requires synchronization between cacheable and
1067 * uncacheable mappings, which eieio doesn't provide and which we
1068 * don't need), thus requiring a more expensive sync instruction. At
1069 * some point, the set of architecture-independent barrier functions
1070 * should be expanded to include weaker barriers.
1074 txbdp->status = status;
1076 /* If this was the last BD in the ring, the next one */
1077 /* is at the beginning of the ring */
1078 if (txbdp->status & TXBD_WRAP)
1079 txbdp = priv->tx_bd_base;
1083 /* If the next BD still needs to be cleaned up, then the bds
1084 are full. We need to tell the kernel to stop sending us stuff. */
1085 if (txbdp == priv->dirty_tx) {
1086 netif_stop_queue(dev);
1088 dev->stats.tx_fifo_errors++;
1091 /* Update the current txbd to the next one */
1092 priv->cur_tx = txbdp;
1094 /* Tell the DMA to go go go */
1095 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1098 spin_unlock_irqrestore(&priv->txlock, flags);
1103 /* Stops the kernel queue, and halts the controller */
1104 static int gfar_close(struct net_device *dev)
1106 struct gfar_private *priv = netdev_priv(dev);
1108 napi_disable(&priv->napi);
1112 /* Disconnect from the PHY */
1113 phy_disconnect(priv->phydev);
1114 priv->phydev = NULL;
1116 netif_stop_queue(dev);
1121 /* Changes the mac address if the controller is not running. */
1122 int gfar_set_mac_address(struct net_device *dev)
1124 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1130 /* Enables and disables VLAN insertion/extraction */
1131 static void gfar_vlan_rx_register(struct net_device *dev,
1132 struct vlan_group *grp)
1134 struct gfar_private *priv = netdev_priv(dev);
1135 unsigned long flags;
1138 spin_lock_irqsave(&priv->rxlock, flags);
1143 /* Enable VLAN tag insertion */
1144 tempval = gfar_read(&priv->regs->tctrl);
1145 tempval |= TCTRL_VLINS;
1147 gfar_write(&priv->regs->tctrl, tempval);
1149 /* Enable VLAN tag extraction */
1150 tempval = gfar_read(&priv->regs->rctrl);
1151 tempval |= RCTRL_VLEX;
1152 gfar_write(&priv->regs->rctrl, tempval);
1154 /* Disable VLAN tag insertion */
1155 tempval = gfar_read(&priv->regs->tctrl);
1156 tempval &= ~TCTRL_VLINS;
1157 gfar_write(&priv->regs->tctrl, tempval);
1159 /* Disable VLAN tag extraction */
1160 tempval = gfar_read(&priv->regs->rctrl);
1161 tempval &= ~RCTRL_VLEX;
1162 gfar_write(&priv->regs->rctrl, tempval);
1165 spin_unlock_irqrestore(&priv->rxlock, flags);
1168 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1170 int tempsize, tempval;
1171 struct gfar_private *priv = netdev_priv(dev);
1172 int oldsize = priv->rx_buffer_size;
1173 int frame_size = new_mtu + ETH_HLEN;
1175 if (priv->vlan_enable)
1176 frame_size += VLAN_ETH_HLEN;
1178 if (gfar_uses_fcb(priv))
1179 frame_size += GMAC_FCB_LEN;
1181 frame_size += priv->padding;
1183 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1184 if (netif_msg_drv(priv))
1185 printk(KERN_ERR "%s: Invalid MTU setting\n",
1191 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1192 INCREMENTAL_BUFFER_SIZE;
1194 /* Only stop and start the controller if it isn't already
1195 * stopped, and we changed something */
1196 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1199 priv->rx_buffer_size = tempsize;
1203 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1204 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1206 /* If the mtu is larger than the max size for standard
1207 * ethernet frames (ie, a jumbo frame), then set maccfg2
1208 * to allow huge frames, and to check the length */
1209 tempval = gfar_read(&priv->regs->maccfg2);
1211 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1212 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1214 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1216 gfar_write(&priv->regs->maccfg2, tempval);
1218 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1224 /* gfar_timeout gets called when a packet has not been
1225 * transmitted after a set amount of time.
1226 * For now, assume that clearing out all the structures, and
1227 * starting over will fix the problem. */
1228 static void gfar_timeout(struct net_device *dev)
1230 struct gfar_private *priv = netdev_priv(dev);
1232 dev->stats.tx_errors++;
1234 if (dev->flags & IFF_UP) {
1239 netif_schedule(dev);
1242 /* Interrupt Handler for Transmit complete */
1243 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1245 struct net_device *dev = (struct net_device *) dev_id;
1246 struct gfar_private *priv = netdev_priv(dev);
1250 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1253 spin_lock(&priv->txlock);
1254 bdp = priv->dirty_tx;
1255 while ((bdp->status & TXBD_READY) == 0) {
1256 /* If dirty_tx and cur_tx are the same, then either the */
1257 /* ring is empty or full now (it could only be full in the beginning, */
1258 /* obviously). If it is empty, we are done. */
1259 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1262 dev->stats.tx_packets++;
1264 /* Deferred means some collisions occurred during transmit, */
1265 /* but we eventually sent the packet. */
1266 if (bdp->status & TXBD_DEF)
1267 dev->stats.collisions++;
1269 /* Free the sk buffer associated with this TxBD */
1270 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1271 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1273 (priv->skb_dirtytx +
1274 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1276 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1277 if (bdp->status & TXBD_WRAP)
1278 bdp = priv->tx_bd_base;
1282 /* Move dirty_tx to be the next bd */
1283 priv->dirty_tx = bdp;
1285 /* We freed a buffer, so now we can restart transmission */
1286 if (netif_queue_stopped(dev))
1287 netif_wake_queue(dev);
1288 } /* while ((bdp->status & TXBD_READY) == 0) */
1290 /* If we are coalescing the interrupts, reset the timer */
1291 /* Otherwise, clear it */
1292 if (priv->txcoalescing)
1293 gfar_write(&priv->regs->txic,
1294 mk_ic_value(priv->txcount, priv->txtime));
1296 gfar_write(&priv->regs->txic, 0);
1298 spin_unlock(&priv->txlock);
1303 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1305 unsigned int alignamount;
1306 struct gfar_private *priv = netdev_priv(dev);
1307 struct sk_buff *skb = NULL;
1308 unsigned int timeout = SKB_ALLOC_TIMEOUT;
1310 /* We have to allocate the skb, so keep trying till we succeed */
1311 while ((!skb) && timeout--)
1312 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1317 alignamount = RXBUF_ALIGNMENT -
1318 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1320 /* We need the data buffer to be aligned properly. We will reserve
1321 * as many bytes as needed to align the data properly
1323 skb_reserve(skb, alignamount);
1325 bdp->bufPtr = dma_map_single(NULL, skb->data,
1326 priv->rx_buffer_size, DMA_FROM_DEVICE);
1330 /* Mark the buffer empty */
1332 bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1337 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1339 struct net_device_stats *stats = &dev->stats;
1340 struct gfar_extra_stats *estats = &priv->extra_stats;
1342 /* If the packet was truncated, none of the other errors
1344 if (status & RXBD_TRUNCATED) {
1345 stats->rx_length_errors++;
1351 /* Count the errors, if there were any */
1352 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1353 stats->rx_length_errors++;
1355 if (status & RXBD_LARGE)
1360 if (status & RXBD_NONOCTET) {
1361 stats->rx_frame_errors++;
1362 estats->rx_nonoctet++;
1364 if (status & RXBD_CRCERR) {
1365 estats->rx_crcerr++;
1366 stats->rx_crc_errors++;
1368 if (status & RXBD_OVERRUN) {
1369 estats->rx_overrun++;
1370 stats->rx_crc_errors++;
1374 irqreturn_t gfar_receive(int irq, void *dev_id)
1376 struct net_device *dev = (struct net_device *) dev_id;
1377 struct gfar_private *priv = netdev_priv(dev);
1378 #ifdef CONFIG_GFAR_NAPI
1381 unsigned long flags;
1384 /* Clear IEVENT, so rx interrupt isn't called again
1385 * because of this interrupt */
1386 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1389 #ifdef CONFIG_GFAR_NAPI
1390 if (netif_rx_schedule_prep(dev, &priv->napi)) {
1391 tempval = gfar_read(&priv->regs->imask);
1392 tempval &= IMASK_RX_DISABLED;
1393 gfar_write(&priv->regs->imask, tempval);
1395 __netif_rx_schedule(dev, &priv->napi);
1397 if (netif_msg_rx_err(priv))
1398 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1399 dev->name, gfar_read(&priv->regs->ievent),
1400 gfar_read(&priv->regs->imask));
1404 spin_lock_irqsave(&priv->rxlock, flags);
1405 gfar_clean_rx_ring(dev, priv->rx_ring_size);
1407 /* If we are coalescing interrupts, update the timer */
1408 /* Otherwise, clear it */
1409 if (priv->rxcoalescing)
1410 gfar_write(&priv->regs->rxic,
1411 mk_ic_value(priv->rxcount, priv->rxtime));
1413 gfar_write(&priv->regs->rxic, 0);
1415 spin_unlock_irqrestore(&priv->rxlock, flags);
1421 static inline int gfar_rx_vlan(struct sk_buff *skb,
1422 struct vlan_group *vlgrp, unsigned short vlctl)
1424 #ifdef CONFIG_GFAR_NAPI
1425 return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1427 return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1431 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1433 /* If valid headers were found, and valid sums
1434 * were verified, then we tell the kernel that no
1435 * checksumming is necessary. Otherwise, it is */
1436 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1437 skb->ip_summed = CHECKSUM_UNNECESSARY;
1439 skb->ip_summed = CHECKSUM_NONE;
1443 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1445 struct rxfcb *fcb = (struct rxfcb *)skb->data;
1447 /* Remove the FCB from the skb */
1448 skb_pull(skb, GMAC_FCB_LEN);
1453 /* gfar_process_frame() -- handle one incoming packet if skb
1455 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1458 struct gfar_private *priv = netdev_priv(dev);
1459 struct rxfcb *fcb = NULL;
1462 if (netif_msg_rx_err(priv))
1463 printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1464 dev->stats.rx_dropped++;
1465 priv->extra_stats.rx_skbmissing++;
1469 /* Prep the skb for the packet */
1470 skb_put(skb, length);
1472 /* Grab the FCB if there is one */
1473 if (gfar_uses_fcb(priv))
1474 fcb = gfar_get_fcb(skb);
1476 /* Remove the padded bytes, if there are any */
1478 skb_pull(skb, priv->padding);
1480 if (priv->rx_csum_enable)
1481 gfar_rx_checksum(skb, fcb);
1483 /* Tell the skb what kind of packet this is */
1484 skb->protocol = eth_type_trans(skb, dev);
1486 /* Send the packet up the stack */
1487 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1488 ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1492 if (NET_RX_DROP == ret)
1493 priv->extra_stats.kernel_dropped++;
1499 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1500 * until the budget/quota has been reached. Returns the number
1503 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1506 struct sk_buff *skb;
1509 struct gfar_private *priv = netdev_priv(dev);
1511 /* Get the first full descriptor */
1514 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1516 skb = priv->rx_skbuff[priv->skb_currx];
1519 (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1520 | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1521 /* Increment the number of packets */
1522 dev->stats.rx_packets++;
1525 /* Remove the FCS from the packet length */
1526 pkt_len = bdp->length - 4;
1528 gfar_process_frame(dev, skb, pkt_len);
1530 dev->stats.rx_bytes += pkt_len;
1532 count_errors(bdp->status, priv);
1535 dev_kfree_skb_any(skb);
1537 priv->rx_skbuff[priv->skb_currx] = NULL;
1540 dev->last_rx = jiffies;
1542 /* Clear the status flags for this buffer */
1543 bdp->status &= ~RXBD_STATS;
1545 /* Add another skb for the future */
1546 skb = gfar_new_skb(dev, bdp);
1547 priv->rx_skbuff[priv->skb_currx] = skb;
1549 /* Update to the next pointer */
1550 if (bdp->status & RXBD_WRAP)
1551 bdp = priv->rx_bd_base;
1555 /* update to point at the next skb */
1558 1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1562 /* Update the current rxbd pointer to be the next one */
1568 #ifdef CONFIG_GFAR_NAPI
1569 static int gfar_poll(struct napi_struct *napi, int budget)
1571 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1572 struct net_device *dev = priv->dev;
1575 howmany = gfar_clean_rx_ring(dev, budget);
1577 if (howmany < budget) {
1578 netif_rx_complete(dev, napi);
1580 /* Clear the halt bit in RSTAT */
1581 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1583 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1585 /* If we are coalescing interrupts, update the timer */
1586 /* Otherwise, clear it */
1587 if (priv->rxcoalescing)
1588 gfar_write(&priv->regs->rxic,
1589 mk_ic_value(priv->rxcount, priv->rxtime));
1591 gfar_write(&priv->regs->rxic, 0);
1598 #ifdef CONFIG_NET_POLL_CONTROLLER
1600 * Polling 'interrupt' - used by things like netconsole to send skbs
1601 * without having to re-enable interrupts. It's not called while
1602 * the interrupt routine is executing.
1604 static void gfar_netpoll(struct net_device *dev)
1606 struct gfar_private *priv = netdev_priv(dev);
1608 /* If the device has multiple interrupts, run tx/rx */
1609 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1610 disable_irq(priv->interruptTransmit);
1611 disable_irq(priv->interruptReceive);
1612 disable_irq(priv->interruptError);
1613 gfar_interrupt(priv->interruptTransmit, dev);
1614 enable_irq(priv->interruptError);
1615 enable_irq(priv->interruptReceive);
1616 enable_irq(priv->interruptTransmit);
1618 disable_irq(priv->interruptTransmit);
1619 gfar_interrupt(priv->interruptTransmit, dev);
1620 enable_irq(priv->interruptTransmit);
1625 /* The interrupt handler for devices with one interrupt */
1626 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1628 struct net_device *dev = dev_id;
1629 struct gfar_private *priv = netdev_priv(dev);
1631 /* Save ievent for future reference */
1632 u32 events = gfar_read(&priv->regs->ievent);
1634 /* Check for reception */
1635 if (events & IEVENT_RX_MASK)
1636 gfar_receive(irq, dev_id);
1638 /* Check for transmit completion */
1639 if (events & IEVENT_TX_MASK)
1640 gfar_transmit(irq, dev_id);
1642 /* Check for errors */
1643 if (events & IEVENT_ERR_MASK)
1644 gfar_error(irq, dev_id);
1649 /* Called every time the controller might need to be made
1650 * aware of new link state. The PHY code conveys this
1651 * information through variables in the phydev structure, and this
1652 * function converts those variables into the appropriate
1653 * register values, and can bring down the device if needed.
1655 static void adjust_link(struct net_device *dev)
1657 struct gfar_private *priv = netdev_priv(dev);
1658 struct gfar __iomem *regs = priv->regs;
1659 unsigned long flags;
1660 struct phy_device *phydev = priv->phydev;
1663 spin_lock_irqsave(&priv->txlock, flags);
1665 u32 tempval = gfar_read(®s->maccfg2);
1666 u32 ecntrl = gfar_read(®s->ecntrl);
1668 /* Now we make sure that we can be in full duplex mode.
1669 * If not, we operate in half-duplex mode. */
1670 if (phydev->duplex != priv->oldduplex) {
1672 if (!(phydev->duplex))
1673 tempval &= ~(MACCFG2_FULL_DUPLEX);
1675 tempval |= MACCFG2_FULL_DUPLEX;
1677 priv->oldduplex = phydev->duplex;
1680 if (phydev->speed != priv->oldspeed) {
1682 switch (phydev->speed) {
1685 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1690 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1692 /* Reduced mode distinguishes
1693 * between 10 and 100 */
1694 if (phydev->speed == SPEED_100)
1695 ecntrl |= ECNTRL_R100;
1697 ecntrl &= ~(ECNTRL_R100);
1700 if (netif_msg_link(priv))
1702 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1703 dev->name, phydev->speed);
1707 priv->oldspeed = phydev->speed;
1710 gfar_write(®s->maccfg2, tempval);
1711 gfar_write(®s->ecntrl, ecntrl);
1713 if (!priv->oldlink) {
1716 netif_schedule(dev);
1718 } else if (priv->oldlink) {
1722 priv->oldduplex = -1;
1725 if (new_state && netif_msg_link(priv))
1726 phy_print_status(phydev);
1728 spin_unlock_irqrestore(&priv->txlock, flags);
1731 /* Update the hash table based on the current list of multicast
1732 * addresses we subscribe to. Also, change the promiscuity of
1733 * the device based on the flags (this function is called
1734 * whenever dev->flags is changed */
1735 static void gfar_set_multi(struct net_device *dev)
1737 struct dev_mc_list *mc_ptr;
1738 struct gfar_private *priv = netdev_priv(dev);
1739 struct gfar __iomem *regs = priv->regs;
1742 if(dev->flags & IFF_PROMISC) {
1743 /* Set RCTRL to PROM */
1744 tempval = gfar_read(®s->rctrl);
1745 tempval |= RCTRL_PROM;
1746 gfar_write(®s->rctrl, tempval);
1748 /* Set RCTRL to not PROM */
1749 tempval = gfar_read(®s->rctrl);
1750 tempval &= ~(RCTRL_PROM);
1751 gfar_write(®s->rctrl, tempval);
1754 if(dev->flags & IFF_ALLMULTI) {
1755 /* Set the hash to rx all multicast frames */
1756 gfar_write(®s->igaddr0, 0xffffffff);
1757 gfar_write(®s->igaddr1, 0xffffffff);
1758 gfar_write(®s->igaddr2, 0xffffffff);
1759 gfar_write(®s->igaddr3, 0xffffffff);
1760 gfar_write(®s->igaddr4, 0xffffffff);
1761 gfar_write(®s->igaddr5, 0xffffffff);
1762 gfar_write(®s->igaddr6, 0xffffffff);
1763 gfar_write(®s->igaddr7, 0xffffffff);
1764 gfar_write(®s->gaddr0, 0xffffffff);
1765 gfar_write(®s->gaddr1, 0xffffffff);
1766 gfar_write(®s->gaddr2, 0xffffffff);
1767 gfar_write(®s->gaddr3, 0xffffffff);
1768 gfar_write(®s->gaddr4, 0xffffffff);
1769 gfar_write(®s->gaddr5, 0xffffffff);
1770 gfar_write(®s->gaddr6, 0xffffffff);
1771 gfar_write(®s->gaddr7, 0xffffffff);
1776 /* zero out the hash */
1777 gfar_write(®s->igaddr0, 0x0);
1778 gfar_write(®s->igaddr1, 0x0);
1779 gfar_write(®s->igaddr2, 0x0);
1780 gfar_write(®s->igaddr3, 0x0);
1781 gfar_write(®s->igaddr4, 0x0);
1782 gfar_write(®s->igaddr5, 0x0);
1783 gfar_write(®s->igaddr6, 0x0);
1784 gfar_write(®s->igaddr7, 0x0);
1785 gfar_write(®s->gaddr0, 0x0);
1786 gfar_write(®s->gaddr1, 0x0);
1787 gfar_write(®s->gaddr2, 0x0);
1788 gfar_write(®s->gaddr3, 0x0);
1789 gfar_write(®s->gaddr4, 0x0);
1790 gfar_write(®s->gaddr5, 0x0);
1791 gfar_write(®s->gaddr6, 0x0);
1792 gfar_write(®s->gaddr7, 0x0);
1794 /* If we have extended hash tables, we need to
1795 * clear the exact match registers to prepare for
1797 if (priv->extended_hash) {
1798 em_num = GFAR_EM_NUM + 1;
1799 gfar_clear_exact_match(dev);
1806 if(dev->mc_count == 0)
1809 /* Parse the list, and set the appropriate bits */
1810 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1812 gfar_set_mac_for_addr(dev, idx,
1816 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1824 /* Clears each of the exact match registers to zero, so they
1825 * don't interfere with normal reception */
1826 static void gfar_clear_exact_match(struct net_device *dev)
1829 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1831 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1832 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1835 /* Set the appropriate hash bit for the given addr */
1836 /* The algorithm works like so:
1837 * 1) Take the Destination Address (ie the multicast address), and
1838 * do a CRC on it (little endian), and reverse the bits of the
1840 * 2) Use the 8 most significant bits as a hash into a 256-entry
1841 * table. The table is controlled through 8 32-bit registers:
1842 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1843 * gaddr7. This means that the 3 most significant bits in the
1844 * hash index which gaddr register to use, and the 5 other bits
1845 * indicate which bit (assuming an IBM numbering scheme, which
1846 * for PowerPC (tm) is usually the case) in the register holds
1848 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1851 struct gfar_private *priv = netdev_priv(dev);
1852 u32 result = ether_crc(MAC_ADDR_LEN, addr);
1853 int width = priv->hash_width;
1854 u8 whichbit = (result >> (32 - width)) & 0x1f;
1855 u8 whichreg = result >> (32 - width + 5);
1856 u32 value = (1 << (31-whichbit));
1858 tempval = gfar_read(priv->hash_regs[whichreg]);
1860 gfar_write(priv->hash_regs[whichreg], tempval);
1866 /* There are multiple MAC Address register pairs on some controllers
1867 * This function sets the numth pair to a given address
1869 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1871 struct gfar_private *priv = netdev_priv(dev);
1873 char tmpbuf[MAC_ADDR_LEN];
1875 u32 __iomem *macptr = &priv->regs->macstnaddr1;
1879 /* Now copy it into the mac registers backwards, cuz */
1880 /* little endian is silly */
1881 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1882 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1884 gfar_write(macptr, *((u32 *) (tmpbuf)));
1886 tempval = *((u32 *) (tmpbuf + 4));
1888 gfar_write(macptr+1, tempval);
1891 /* GFAR error interrupt handler */
1892 static irqreturn_t gfar_error(int irq, void *dev_id)
1894 struct net_device *dev = dev_id;
1895 struct gfar_private *priv = netdev_priv(dev);
1897 /* Save ievent for future reference */
1898 u32 events = gfar_read(&priv->regs->ievent);
1901 gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1904 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1905 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1906 dev->name, events, gfar_read(&priv->regs->imask));
1908 /* Update the error counters */
1909 if (events & IEVENT_TXE) {
1910 dev->stats.tx_errors++;
1912 if (events & IEVENT_LC)
1913 dev->stats.tx_window_errors++;
1914 if (events & IEVENT_CRL)
1915 dev->stats.tx_aborted_errors++;
1916 if (events & IEVENT_XFUN) {
1917 if (netif_msg_tx_err(priv))
1918 printk(KERN_DEBUG "%s: TX FIFO underrun, "
1919 "packet dropped.\n", dev->name);
1920 dev->stats.tx_dropped++;
1921 priv->extra_stats.tx_underrun++;
1923 /* Reactivate the Tx Queues */
1924 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1926 if (netif_msg_tx_err(priv))
1927 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1929 if (events & IEVENT_BSY) {
1930 dev->stats.rx_errors++;
1931 priv->extra_stats.rx_bsy++;
1933 gfar_receive(irq, dev_id);
1935 #ifndef CONFIG_GFAR_NAPI
1936 /* Clear the halt bit in RSTAT */
1937 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1940 if (netif_msg_rx_err(priv))
1941 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
1942 dev->name, gfar_read(&priv->regs->rstat));
1944 if (events & IEVENT_BABR) {
1945 dev->stats.rx_errors++;
1946 priv->extra_stats.rx_babr++;
1948 if (netif_msg_rx_err(priv))
1949 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1951 if (events & IEVENT_EBERR) {
1952 priv->extra_stats.eberr++;
1953 if (netif_msg_rx_err(priv))
1954 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1956 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1957 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1959 if (events & IEVENT_BABT) {
1960 priv->extra_stats.tx_babt++;
1961 if (netif_msg_tx_err(priv))
1962 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1967 /* Structure for a device driver */
1968 static struct platform_driver gfar_driver = {
1969 .probe = gfar_probe,
1970 .remove = gfar_remove,
1972 .name = "fsl-gianfar",
1976 static int __init gfar_init(void)
1978 int err = gfar_mdio_init();
1983 err = platform_driver_register(&gfar_driver);
1991 static void __exit gfar_exit(void)
1993 platform_driver_unregister(&gfar_driver);
1997 module_init(gfar_init);
1998 module_exit(gfar_exit);