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   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #include <linux/kernel.h>
  65 #include <linux/string.h>
  66 #include <linux/errno.h>
  67 #include <linux/unistd.h>
  68 #include <linux/slab.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/init.h>
  71 #include <linux/delay.h>
  72 #include <linux/netdevice.h>
  73 #include <linux/etherdevice.h>
  74 #include <linux/skbuff.h>
  75 #include <linux/if_vlan.h>
  76 #include <linux/spinlock.h>
  77 #include <linux/mm.h>
  78 #include <linux/of_platform.h>
  79 #include <linux/ip.h>
  80 #include <linux/tcp.h>
  81 #include <linux/udp.h>
  82 #include <linux/in.h>
  83
  84 #include <asm/io.h>
  85 #include <asm/irq.h>
  86 #include <asm/uaccess.h>
  87 #include <linux/module.h>
  88 #include <linux/dma-mapping.h>
  89 #include <linux/crc32.h>
  90 #include <linux/mii.h>
  91 #include <linux/phy.h>
  92 #include <linux/phy_fixed.h>
  93 #include <linux/of.h>
  94
  95 #include "gianfar.h"
  96 #include "gianfar_mii.h"
  97
  98 #define TX_TIMEOUT      (1*HZ)
  99 #undef BRIEF_GFAR_ERRORS
 100 #undef VERBOSE_GFAR_ERRORS
 101
 102 const char gfar_driver_name[] = "Gianfar Ethernet";
 103 const char gfar_driver_version[] = "1.3";
 104
 105 static int gfar_enet_open(struct net_device *dev);
 106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 107 static void gfar_reset_task(struct work_struct *work);
 108 static void gfar_timeout(struct net_device *dev);
 109 static int gfar_close(struct net_device *dev);
 110 struct sk_buff *gfar_new_skb(struct net_device *dev);
 111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 112                 struct sk_buff *skb);
 113 static int gfar_set_mac_address(struct net_device *dev);
 114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 115 static irqreturn_t gfar_error(int irq, void *dev_id);
 116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 118 static void adjust_link(struct net_device *dev);
 119 static void init_registers(struct net_device *dev);
 120 static int init_phy(struct net_device *dev);
 121 static int gfar_probe(struct of_device *ofdev,
 122                 const struct of_device_id *match);
 123 static int gfar_remove(struct of_device *ofdev);
 124 static void free_skb_resources(struct gfar_private *priv);
 125 static void gfar_set_multi(struct net_device *dev);
 126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 127 static void gfar_configure_serdes(struct net_device *dev);
 128 static int gfar_poll(struct napi_struct *napi, int budget);
 129 #ifdef CONFIG_NET_POLL_CONTROLLER
 130 static void gfar_netpoll(struct net_device *dev);
 131 #endif
 132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 133 static int gfar_clean_tx_ring(struct net_device *dev);
 134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 135                               int amount_pull);
 136 static void gfar_vlan_rx_register(struct net_device *netdev,
 137                                 struct vlan_group *grp);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 143
 144 extern const struct ethtool_ops gfar_ethtool_ops;
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 /* Returns 1 if incoming frames use an FCB */
 151 static inline int gfar_uses_fcb(struct gfar_private *priv)
 152 {
 153         return priv->vlgrp || priv->rx_csum_enable;
 154 }
 155
 156 static int gfar_of_init(struct net_device *dev)
 157 {
 158         struct device_node *phy, *mdio;
 159         const unsigned int *id;
 160         const char *model;
 161         const char *ctype;
 162         const void *mac_addr;
 163         const phandle *ph;
 164         u64 addr, size;
 165         int err = 0;
 166         struct gfar_private *priv = netdev_priv(dev);
 167         struct device_node *np = priv->node;
 168         char bus_name[MII_BUS_ID_SIZE];
 169
 170         if (!np || !of_device_is_available(np))
 171                 return -ENODEV;
 172
 173         /* get a pointer to the register memory */
 174         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
 175         priv->regs = ioremap(addr, size);
 176
 177         if (priv->regs == NULL)
 178                 return -ENOMEM;
 179
 180         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
 181
 182         model = of_get_property(np, "model", NULL);
 183
 184         /* If we aren't the FEC we have multiple interrupts */
 185         if (model && strcasecmp(model, "FEC")) {
 186                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
 187
 188                 priv->interruptError = irq_of_parse_and_map(np, 2);
 189
 190                 if (priv->interruptTransmit < 0 ||
 191                                 priv->interruptReceive < 0 ||
 192                                 priv->interruptError < 0) {
 193                         err = -EINVAL;
 194                         goto err_out;
 195                 }
 196         }
 197
 198         mac_addr = of_get_mac_address(np);
 199         if (mac_addr)
 200                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 201
 202         if (model && !strcasecmp(model, "TSEC"))
 203                 priv->device_flags =
 204                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 205                         FSL_GIANFAR_DEV_HAS_COALESCE |
 206                         FSL_GIANFAR_DEV_HAS_RMON |
 207                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 208         if (model && !strcasecmp(model, "eTSEC"))
 209                 priv->device_flags =
 210                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 211                         FSL_GIANFAR_DEV_HAS_COALESCE |
 212                         FSL_GIANFAR_DEV_HAS_RMON |
 213                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 214                         FSL_GIANFAR_DEV_HAS_PADDING |
 215                         FSL_GIANFAR_DEV_HAS_CSUM |
 216                         FSL_GIANFAR_DEV_HAS_VLAN |
 217                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 218                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 219
 220         ctype = of_get_property(np, "phy-connection-type", NULL);
 221
 222         /* We only care about rgmii-id.  The rest are autodetected */
 223         if (ctype && !strcmp(ctype, "rgmii-id"))
 224                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 225         else
 226                 priv->interface = PHY_INTERFACE_MODE_MII;
 227
 228         if (of_get_property(np, "fsl,magic-packet", NULL))
 229                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 230
 231         ph = of_get_property(np, "phy-handle", NULL);
 232         if (ph == NULL) {
 233                 u32 *fixed_link;
 234
 235                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
 236                 if (!fixed_link) {
 237                         err = -ENODEV;
 238                         goto err_out;
 239                 }
 240
 241                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, PHY_ID_FMT, "0",
 242                                 fixed_link[0]);
 243         } else {
 244                 phy = of_find_node_by_phandle(*ph);
 245
 246                 if (phy == NULL) {
 247                         err = -ENODEV;
 248                         goto err_out;
 249                 }
 250
 251                 mdio = of_get_parent(phy);
 252
 253                 id = of_get_property(phy, "reg", NULL);
 254
 255                 of_node_put(phy);
 256                 of_node_put(mdio);
 257
 258                 gfar_mdio_bus_name(bus_name, mdio);
 259                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, "%s:%02x",
 260                                 bus_name, *id);
 261         }
 262
 263         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 264         ph = of_get_property(np, "tbi-handle", NULL);
 265         if (ph) {
 266                 struct device_node *tbi = of_find_node_by_phandle(*ph);
 267                 struct of_device *ofdev;
 268                 struct mii_bus *bus;
 269
 270                 if (!tbi)
 271                         return 0;
 272
 273                 mdio = of_get_parent(tbi);
 274                 if (!mdio)
 275                         return 0;
 276
 277                 ofdev = of_find_device_by_node(mdio);
 278
 279                 of_node_put(mdio);
 280
 281                 id = of_get_property(tbi, "reg", NULL);
 282                 if (!id)
 283                         return 0;
 284
 285                 of_node_put(tbi);
 286
 287                 bus = dev_get_drvdata(&ofdev->dev);
 288
 289                 priv->tbiphy = bus->phy_map[*id];
 290         }
 291
 292         return 0;
 293
 294 err_out:
 295         iounmap(priv->regs);
 296         return err;
 297 }
 298
 299 /* Set up the ethernet device structure, private data,
 300  * and anything else we need before we start */
 301 static int gfar_probe(struct of_device *ofdev,
 302                 const struct of_device_id *match)
 303 {
 304         u32 tempval;
 305         struct net_device *dev = NULL;
 306         struct gfar_private *priv = NULL;
 307         int err = 0;
 308         DECLARE_MAC_BUF(mac);
 309
 310         /* Create an ethernet device instance */
 311         dev = alloc_etherdev(sizeof (*priv));
 312
 313         if (NULL == dev)
 314                 return -ENOMEM;
 315
 316         priv = netdev_priv(dev);
 317         priv->dev = dev;
 318         priv->node = ofdev->node;
 319
 320         err = gfar_of_init(dev);
 321
 322         if (err)
 323                 goto regs_fail;
 324
 325         spin_lock_init(&priv->txlock);
 326         spin_lock_init(&priv->rxlock);
 327         spin_lock_init(&priv->bflock);
 328         INIT_WORK(&priv->reset_task, gfar_reset_task);
 329
 330         dev_set_drvdata(&ofdev->dev, priv);
 331
 332         /* Stop the DMA engine now, in case it was running before */
 333         /* (The firmware could have used it, and left it running). */
 334         gfar_halt(dev);
 335
 336         /* Reset MAC layer */
 337         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 338
 339         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 340         gfar_write(&priv->regs->maccfg1, tempval);
 341
 342         /* Initialize MACCFG2. */
 343         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 344
 345         /* Initialize ECNTRL */
 346         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 347
 348         /* Set the dev->base_addr to the gfar reg region */
 349         dev->base_addr = (unsigned long) (priv->regs);
 350
 351         SET_NETDEV_DEV(dev, &ofdev->dev);
 352
 353         /* Fill in the dev structure */
 354         dev->open = gfar_enet_open;
 355         dev->hard_start_xmit = gfar_start_xmit;
 356         dev->tx_timeout = gfar_timeout;
 357         dev->watchdog_timeo = TX_TIMEOUT;
 358         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 359 #ifdef CONFIG_NET_POLL_CONTROLLER
 360         dev->poll_controller = gfar_netpoll;
 361 #endif
 362         dev->stop = gfar_close;
 363         dev->change_mtu = gfar_change_mtu;
 364         dev->mtu = 1500;
 365         dev->set_multicast_list = gfar_set_multi;
 366
 367         dev->ethtool_ops = &gfar_ethtool_ops;
 368
 369         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 370                 priv->rx_csum_enable = 1;
 371                 dev->features |= NETIF_F_IP_CSUM;
 372         } else
 373                 priv->rx_csum_enable = 0;
 374
 375         priv->vlgrp = NULL;
 376
 377         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 378                 dev->vlan_rx_register = gfar_vlan_rx_register;
 379
 380                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 381         }
 382
 383         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 384                 priv->extended_hash = 1;
 385                 priv->hash_width = 9;
 386
 387                 priv->hash_regs[0] = &priv->regs->igaddr0;
 388                 priv->hash_regs[1] = &priv->regs->igaddr1;
 389                 priv->hash_regs[2] = &priv->regs->igaddr2;
 390                 priv->hash_regs[3] = &priv->regs->igaddr3;
 391                 priv->hash_regs[4] = &priv->regs->igaddr4;
 392                 priv->hash_regs[5] = &priv->regs->igaddr5;
 393                 priv->hash_regs[6] = &priv->regs->igaddr6;
 394                 priv->hash_regs[7] = &priv->regs->igaddr7;
 395                 priv->hash_regs[8] = &priv->regs->gaddr0;
 396                 priv->hash_regs[9] = &priv->regs->gaddr1;
 397                 priv->hash_regs[10] = &priv->regs->gaddr2;
 398                 priv->hash_regs[11] = &priv->regs->gaddr3;
 399                 priv->hash_regs[12] = &priv->regs->gaddr4;
 400                 priv->hash_regs[13] = &priv->regs->gaddr5;
 401                 priv->hash_regs[14] = &priv->regs->gaddr6;
 402                 priv->hash_regs[15] = &priv->regs->gaddr7;
 403
 404         } else {
 405                 priv->extended_hash = 0;
 406                 priv->hash_width = 8;
 407
 408                 priv->hash_regs[0] = &priv->regs->gaddr0;
 409                 priv->hash_regs[1] = &priv->regs->gaddr1;
 410                 priv->hash_regs[2] = &priv->regs->gaddr2;
 411                 priv->hash_regs[3] = &priv->regs->gaddr3;
 412                 priv->hash_regs[4] = &priv->regs->gaddr4;
 413                 priv->hash_regs[5] = &priv->regs->gaddr5;
 414                 priv->hash_regs[6] = &priv->regs->gaddr6;
 415                 priv->hash_regs[7] = &priv->regs->gaddr7;
 416         }
 417
 418         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 419                 priv->padding = DEFAULT_PADDING;
 420         else
 421                 priv->padding = 0;
 422
 423         if (dev->features & NETIF_F_IP_CSUM)
 424                 dev->hard_header_len += GMAC_FCB_LEN;
 425
 426         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 427         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 428         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 429
 430         priv->txcoalescing = DEFAULT_TX_COALESCE;
 431         priv->txic = DEFAULT_TXIC;
 432         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 433         priv->rxic = DEFAULT_RXIC;
 434
 435         /* Enable most messages by default */
 436         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 437
 438         /* Carrier starts down, phylib will bring it up */
 439         netif_carrier_off(dev);
 440
 441         err = register_netdev(dev);
 442
 443         if (err) {
 444                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 445                                 dev->name);
 446                 goto register_fail;
 447         }
 448
 449         /* Create all the sysfs files */
 450         gfar_init_sysfs(dev);
 451
 452         /* Print out the device info */
 453         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
 454
 455         /* Even more device info helps when determining which kernel */
 456         /* provided which set of benchmarks. */
 457         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 458         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 459                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 460
 461         return 0;
 462
 463 register_fail:
 464         iounmap(priv->regs);
 465 regs_fail:
 466         free_netdev(dev);
 467         return err;
 468 }
 469
 470 static int gfar_remove(struct of_device *ofdev)
 471 {
 472         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 473
 474         dev_set_drvdata(&ofdev->dev, NULL);
 475
 476         iounmap(priv->regs);
 477         free_netdev(priv->dev);
 478
 479         return 0;
 480 }
 481
 482 #ifdef CONFIG_PM
 483 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
 484 {
 485         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 486         struct net_device *dev = priv->dev;
 487         unsigned long flags;
 488         u32 tempval;
 489
 490         int magic_packet = priv->wol_en &&
 491                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 492
 493         netif_device_detach(dev);
 494
 495         if (netif_running(dev)) {
 496                 spin_lock_irqsave(&priv->txlock, flags);
 497                 spin_lock(&priv->rxlock);
 498
 499                 gfar_halt_nodisable(dev);
 500
 501                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 502                 tempval = gfar_read(&priv->regs->maccfg1);
 503
 504                 tempval &= ~MACCFG1_TX_EN;
 505
 506                 if (!magic_packet)
 507                         tempval &= ~MACCFG1_RX_EN;
 508
 509                 gfar_write(&priv->regs->maccfg1, tempval);
 510
 511                 spin_unlock(&priv->rxlock);
 512                 spin_unlock_irqrestore(&priv->txlock, flags);
 513
 514                 napi_disable(&priv->napi);
 515
 516                 if (magic_packet) {
 517                         /* Enable interrupt on Magic Packet */
 518                         gfar_write(&priv->regs->imask, IMASK_MAG);
 519
 520                         /* Enable Magic Packet mode */
 521                         tempval = gfar_read(&priv->regs->maccfg2);
 522                         tempval |= MACCFG2_MPEN;
 523                         gfar_write(&priv->regs->maccfg2, tempval);
 524                 } else {
 525                         phy_stop(priv->phydev);
 526                 }
 527         }
 528
 529         return 0;
 530 }
 531
 532 static int gfar_resume(struct of_device *ofdev)
 533 {
 534         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 535         struct net_device *dev = priv->dev;
 536         unsigned long flags;
 537         u32 tempval;
 538         int magic_packet = priv->wol_en &&
 539                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 540
 541         if (!netif_running(dev)) {
 542                 netif_device_attach(dev);
 543                 return 0;
 544         }
 545
 546         if (!magic_packet && priv->phydev)
 547                 phy_start(priv->phydev);
 548
 549         /* Disable Magic Packet mode, in case something
 550          * else woke us up.
 551          */
 552
 553         spin_lock_irqsave(&priv->txlock, flags);
 554         spin_lock(&priv->rxlock);
 555
 556         tempval = gfar_read(&priv->regs->maccfg2);
 557         tempval &= ~MACCFG2_MPEN;
 558         gfar_write(&priv->regs->maccfg2, tempval);
 559
 560         gfar_start(dev);
 561
 562         spin_unlock(&priv->rxlock);
 563         spin_unlock_irqrestore(&priv->txlock, flags);
 564
 565         netif_device_attach(dev);
 566
 567         napi_enable(&priv->napi);
 568
 569         return 0;
 570 }
 571 #else
 572 #define gfar_suspend NULL
 573 #define gfar_resume NULL
 574 #endif
 575
 576 /* Reads the controller's registers to determine what interface
 577  * connects it to the PHY.
 578  */
 579 static phy_interface_t gfar_get_interface(struct net_device *dev)
 580 {
 581         struct gfar_private *priv = netdev_priv(dev);
 582         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 583
 584         if (ecntrl & ECNTRL_SGMII_MODE)
 585                 return PHY_INTERFACE_MODE_SGMII;
 586
 587         if (ecntrl & ECNTRL_TBI_MODE) {
 588                 if (ecntrl & ECNTRL_REDUCED_MODE)
 589                         return PHY_INTERFACE_MODE_RTBI;
 590                 else
 591                         return PHY_INTERFACE_MODE_TBI;
 592         }
 593
 594         if (ecntrl & ECNTRL_REDUCED_MODE) {
 595                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 596                         return PHY_INTERFACE_MODE_RMII;
 597                 else {
 598                         phy_interface_t interface = priv->interface;
 599
 600                         /*
 601                          * This isn't autodetected right now, so it must
 602                          * be set by the device tree or platform code.
 603                          */
 604                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 605                                 return PHY_INTERFACE_MODE_RGMII_ID;
 606
 607                         return PHY_INTERFACE_MODE_RGMII;
 608                 }
 609         }
 610
 611         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 612                 return PHY_INTERFACE_MODE_GMII;
 613
 614         return PHY_INTERFACE_MODE_MII;
 615 }
 616
 617
 618 /* Initializes driver's PHY state, and attaches to the PHY.
 619  * Returns 0 on success.
 620  */
 621 static int init_phy(struct net_device *dev)
 622 {
 623         struct gfar_private *priv = netdev_priv(dev);
 624         uint gigabit_support =
 625                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 626                 SUPPORTED_1000baseT_Full : 0;
 627         struct phy_device *phydev;
 628         phy_interface_t interface;
 629
 630         priv->oldlink = 0;
 631         priv->oldspeed = 0;
 632         priv->oldduplex = -1;
 633
 634         interface = gfar_get_interface(dev);
 635
 636         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
 637
 638         if (interface == PHY_INTERFACE_MODE_SGMII)
 639                 gfar_configure_serdes(dev);
 640
 641         if (IS_ERR(phydev)) {
 642                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 643                 return PTR_ERR(phydev);
 644         }
 645
 646         /* Remove any features not supported by the controller */
 647         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 648         phydev->advertising = phydev->supported;
 649
 650         priv->phydev = phydev;
 651
 652         return 0;
 653 }
 654
 655 /*
 656  * Initialize TBI PHY interface for communicating with the
 657  * SERDES lynx PHY on the chip.  We communicate with this PHY
 658  * through the MDIO bus on each controller, treating it as a
 659  * "normal" PHY at the address found in the TBIPA register.  We assume
 660  * that the TBIPA register is valid.  Either the MDIO bus code will set
 661  * it to a value that doesn't conflict with other PHYs on the bus, or the
 662  * value doesn't matter, as there are no other PHYs on the bus.
 663  */
 664 static void gfar_configure_serdes(struct net_device *dev)
 665 {
 666         struct gfar_private *priv = netdev_priv(dev);
 667
 668         if (!priv->tbiphy) {
 669                 printk(KERN_WARNING "SGMII mode requires that the device "
 670                                 "tree specify a tbi-handle\n");
 671                 return;
 672         }
 673
 674         /*
 675          * If the link is already up, we must already be ok, and don't need to
 676          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
 677          * everything for us?  Resetting it takes the link down and requires
 678          * several seconds for it to come back.
 679          */
 680         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
 681                 return;
 682
 683         /* Single clk mode, mii mode off(for serdes communication) */
 684         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
 685
 686         phy_write(priv->tbiphy, MII_ADVERTISE,
 687                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 688                         ADVERTISE_1000XPSE_ASYM);
 689
 690         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
 691                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 692 }
 693
 694 static void init_registers(struct net_device *dev)
 695 {
 696         struct gfar_private *priv = netdev_priv(dev);
 697
 698         /* Clear IEVENT */
 699         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 700
 701         /* Initialize IMASK */
 702         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 703
 704         /* Init hash registers to zero */
 705         gfar_write(&priv->regs->igaddr0, 0);
 706         gfar_write(&priv->regs->igaddr1, 0);
 707         gfar_write(&priv->regs->igaddr2, 0);
 708         gfar_write(&priv->regs->igaddr3, 0);
 709         gfar_write(&priv->regs->igaddr4, 0);
 710         gfar_write(&priv->regs->igaddr5, 0);
 711         gfar_write(&priv->regs->igaddr6, 0);
 712         gfar_write(&priv->regs->igaddr7, 0);
 713
 714         gfar_write(&priv->regs->gaddr0, 0);
 715         gfar_write(&priv->regs->gaddr1, 0);
 716         gfar_write(&priv->regs->gaddr2, 0);
 717         gfar_write(&priv->regs->gaddr3, 0);
 718         gfar_write(&priv->regs->gaddr4, 0);
 719         gfar_write(&priv->regs->gaddr5, 0);
 720         gfar_write(&priv->regs->gaddr6, 0);
 721         gfar_write(&priv->regs->gaddr7, 0);
 722
 723         /* Zero out the rmon mib registers if it has them */
 724         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 725                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 726
 727                 /* Mask off the CAM interrupts */
 728                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 729                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 730         }
 731
 732         /* Initialize the max receive buffer length */
 733         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 734
 735         /* Initialize the Minimum Frame Length Register */
 736         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 737 }
 738
 739
 740 /* Halt the receive and transmit queues */
 741 static void gfar_halt_nodisable(struct net_device *dev)
 742 {
 743         struct gfar_private *priv = netdev_priv(dev);
 744         struct gfar __iomem *regs = priv->regs;
 745         u32 tempval;
 746
 747         /* Mask all interrupts */
 748         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 749
 750         /* Clear all interrupts */
 751         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 752
 753         /* Stop the DMA, and wait for it to stop */
 754         tempval = gfar_read(&priv->regs->dmactrl);
 755         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 756             != (DMACTRL_GRS | DMACTRL_GTS)) {
 757                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 758                 gfar_write(&priv->regs->dmactrl, tempval);
 759
 760                 while (!(gfar_read(&priv->regs->ievent) &
 761                          (IEVENT_GRSC | IEVENT_GTSC)))
 762                         cpu_relax();
 763         }
 764 }
 765
 766 /* Halt the receive and transmit queues */
 767 void gfar_halt(struct net_device *dev)
 768 {
 769         struct gfar_private *priv = netdev_priv(dev);
 770         struct gfar __iomem *regs = priv->regs;
 771         u32 tempval;
 772
 773         gfar_halt_nodisable(dev);
 774
 775         /* Disable Rx and Tx */
 776         tempval = gfar_read(&regs->maccfg1);
 777         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 778         gfar_write(&regs->maccfg1, tempval);
 779 }
 780
 781 void stop_gfar(struct net_device *dev)
 782 {
 783         struct gfar_private *priv = netdev_priv(dev);
 784         struct gfar __iomem *regs = priv->regs;
 785         unsigned long flags;
 786
 787         phy_stop(priv->phydev);
 788
 789         /* Lock it down */
 790         spin_lock_irqsave(&priv->txlock, flags);
 791         spin_lock(&priv->rxlock);
 792
 793         gfar_halt(dev);
 794
 795         spin_unlock(&priv->rxlock);
 796         spin_unlock_irqrestore(&priv->txlock, flags);
 797
 798         /* Free the IRQs */
 799         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 800                 free_irq(priv->interruptError, dev);
 801                 free_irq(priv->interruptTransmit, dev);
 802                 free_irq(priv->interruptReceive, dev);
 803         } else {
 804                 free_irq(priv->interruptTransmit, dev);
 805         }
 806
 807         free_skb_resources(priv);
 808
 809         dma_free_coherent(&dev->dev,
 810                         sizeof(struct txbd8)*priv->tx_ring_size
 811                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 812                         priv->tx_bd_base,
 813                         gfar_read(&regs->tbase0));
 814 }
 815
 816 /* If there are any tx skbs or rx skbs still around, free them.
 817  * Then free tx_skbuff and rx_skbuff */
 818 static void free_skb_resources(struct gfar_private *priv)
 819 {
 820         struct rxbd8 *rxbdp;
 821         struct txbd8 *txbdp;
 822         int i;
 823
 824         /* Go through all the buffer descriptors and free their data buffers */
 825         txbdp = priv->tx_bd_base;
 826
 827         for (i = 0; i < priv->tx_ring_size; i++) {
 828
 829                 if (priv->tx_skbuff[i]) {
 830                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
 831                                         txbdp->length,
 832                                         DMA_TO_DEVICE);
 833                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 834                         priv->tx_skbuff[i] = NULL;
 835                 }
 836
 837                 txbdp++;
 838         }
 839
 840         kfree(priv->tx_skbuff);
 841
 842         rxbdp = priv->rx_bd_base;
 843
 844         /* rx_skbuff is not guaranteed to be allocated, so only
 845          * free it and its contents if it is allocated */
 846         if(priv->rx_skbuff != NULL) {
 847                 for (i = 0; i < priv->rx_ring_size; i++) {
 848                         if (priv->rx_skbuff[i]) {
 849                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
 850                                                 priv->rx_buffer_size,
 851                                                 DMA_FROM_DEVICE);
 852
 853                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 854                                 priv->rx_skbuff[i] = NULL;
 855                         }
 856
 857                         rxbdp->lstatus = 0;
 858                         rxbdp->bufPtr = 0;
 859
 860                         rxbdp++;
 861                 }
 862
 863                 kfree(priv->rx_skbuff);
 864         }
 865 }
 866
 867 void gfar_start(struct net_device *dev)
 868 {
 869         struct gfar_private *priv = netdev_priv(dev);
 870         struct gfar __iomem *regs = priv->regs;
 871         u32 tempval;
 872
 873         /* Enable Rx and Tx in MACCFG1 */
 874         tempval = gfar_read(&regs->maccfg1);
 875         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 876         gfar_write(&regs->maccfg1, tempval);
 877
 878         /* Initialize DMACTRL to have WWR and WOP */
 879         tempval = gfar_read(&priv->regs->dmactrl);
 880         tempval |= DMACTRL_INIT_SETTINGS;
 881         gfar_write(&priv->regs->dmactrl, tempval);
 882
 883         /* Make sure we aren't stopped */
 884         tempval = gfar_read(&priv->regs->dmactrl);
 885         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 886         gfar_write(&priv->regs->dmactrl, tempval);
 887
 888         /* Clear THLT/RHLT, so that the DMA starts polling now */
 889         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 890         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 891
 892         /* Unmask the interrupts we look for */
 893         gfar_write(&regs->imask, IMASK_DEFAULT);
 894
 895         dev->trans_start = jiffies;
 896 }
 897
 898 /* Bring the controller up and running */
 899 int startup_gfar(struct net_device *dev)
 900 {
 901         struct txbd8 *txbdp;
 902         struct rxbd8 *rxbdp;
 903         dma_addr_t addr = 0;
 904         unsigned long vaddr;
 905         int i;
 906         struct gfar_private *priv = netdev_priv(dev);
 907         struct gfar __iomem *regs = priv->regs;
 908         int err = 0;
 909         u32 rctrl = 0;
 910         u32 attrs = 0;
 911
 912         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 913
 914         /* Allocate memory for the buffer descriptors */
 915         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
 916                         sizeof (struct txbd8) * priv->tx_ring_size +
 917                         sizeof (struct rxbd8) * priv->rx_ring_size,
 918                         &addr, GFP_KERNEL);
 919
 920         if (vaddr == 0) {
 921                 if (netif_msg_ifup(priv))
 922                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 923                                         dev->name);
 924                 return -ENOMEM;
 925         }
 926
 927         priv->tx_bd_base = (struct txbd8 *) vaddr;
 928
 929         /* enet DMA only understands physical addresses */
 930         gfar_write(&regs->tbase0, addr);
 931
 932         /* Start the rx descriptor ring where the tx ring leaves off */
 933         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 934         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 935         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 936         gfar_write(&regs->rbase0, addr);
 937
 938         /* Setup the skbuff rings */
 939         priv->tx_skbuff =
 940             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 941                                         priv->tx_ring_size, GFP_KERNEL);
 942
 943         if (NULL == priv->tx_skbuff) {
 944                 if (netif_msg_ifup(priv))
 945                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 946                                         dev->name);
 947                 err = -ENOMEM;
 948                 goto tx_skb_fail;
 949         }
 950
 951         for (i = 0; i < priv->tx_ring_size; i++)
 952                 priv->tx_skbuff[i] = NULL;
 953
 954         priv->rx_skbuff =
 955             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 956                                         priv->rx_ring_size, GFP_KERNEL);
 957
 958         if (NULL == priv->rx_skbuff) {
 959                 if (netif_msg_ifup(priv))
 960                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 961                                         dev->name);
 962                 err = -ENOMEM;
 963                 goto rx_skb_fail;
 964         }
 965
 966         for (i = 0; i < priv->rx_ring_size; i++)
 967                 priv->rx_skbuff[i] = NULL;
 968
 969         /* Initialize some variables in our dev structure */
 970         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 971         priv->cur_rx = priv->rx_bd_base;
 972         priv->skb_curtx = priv->skb_dirtytx = 0;
 973         priv->skb_currx = 0;
 974
 975         /* Initialize Transmit Descriptor Ring */
 976         txbdp = priv->tx_bd_base;
 977         for (i = 0; i < priv->tx_ring_size; i++) {
 978                 txbdp->lstatus = 0;
 979                 txbdp->bufPtr = 0;
 980                 txbdp++;
 981         }
 982
 983         /* Set the last descriptor in the ring to indicate wrap */
 984         txbdp--;
 985         txbdp->status |= TXBD_WRAP;
 986
 987         rxbdp = priv->rx_bd_base;
 988         for (i = 0; i < priv->rx_ring_size; i++) {
 989                 struct sk_buff *skb;
 990
 991                 skb = gfar_new_skb(dev);
 992
 993                 if (!skb) {
 994                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
 995                                         dev->name);
 996
 997                         goto err_rxalloc_fail;
 998                 }
 999
1000                 priv->rx_skbuff[i] = skb;
1001
1002                 gfar_new_rxbdp(dev, rxbdp, skb);
1003
1004                 rxbdp++;
1005         }
1006
1007         /* Set the last descriptor in the ring to wrap */
1008         rxbdp--;
1009         rxbdp->status |= RXBD_WRAP;
1010
1011         /* If the device has multiple interrupts, register for
1012          * them.  Otherwise, only register for the one */
1013         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1014                 /* Install our interrupt handlers for Error,
1015                  * Transmit, and Receive */
1016                 if (request_irq(priv->interruptError, gfar_error,
1017                                 0, "enet_error", dev) < 0) {
1018                         if (netif_msg_intr(priv))
1019                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1020                                         dev->name, priv->interruptError);
1021
1022                         err = -1;
1023                         goto err_irq_fail;
1024                 }
1025
1026                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1027                                 0, "enet_tx", dev) < 0) {
1028                         if (netif_msg_intr(priv))
1029                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1030                                         dev->name, priv->interruptTransmit);
1031
1032                         err = -1;
1033
1034                         goto tx_irq_fail;
1035                 }
1036
1037                 if (request_irq(priv->interruptReceive, gfar_receive,
1038                                 0, "enet_rx", dev) < 0) {
1039                         if (netif_msg_intr(priv))
1040                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1041                                                 dev->name, priv->interruptReceive);
1042
1043                         err = -1;
1044                         goto rx_irq_fail;
1045                 }
1046         } else {
1047                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1048                                 0, "gfar_interrupt", dev) < 0) {
1049                         if (netif_msg_intr(priv))
1050                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1051                                         dev->name, priv->interruptError);
1052
1053                         err = -1;
1054                         goto err_irq_fail;
1055                 }
1056         }
1057
1058         phy_start(priv->phydev);
1059
1060         /* Configure the coalescing support */
1061         gfar_write(&regs->txic, 0);
1062         if (priv->txcoalescing)
1063                 gfar_write(&regs->txic, priv->txic);
1064
1065         gfar_write(&regs->rxic, 0);
1066         if (priv->rxcoalescing)
1067                 gfar_write(&regs->rxic, priv->rxic);
1068
1069         if (priv->rx_csum_enable)
1070                 rctrl |= RCTRL_CHECKSUMMING;
1071
1072         if (priv->extended_hash) {
1073                 rctrl |= RCTRL_EXTHASH;
1074
1075                 gfar_clear_exact_match(dev);
1076                 rctrl |= RCTRL_EMEN;
1077         }
1078
1079         if (priv->padding) {
1080                 rctrl &= ~RCTRL_PAL_MASK;
1081                 rctrl |= RCTRL_PADDING(priv->padding);
1082         }
1083
1084         /* Init rctrl based on our settings */
1085         gfar_write(&priv->regs->rctrl, rctrl);
1086
1087         if (dev->features & NETIF_F_IP_CSUM)
1088                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1089
1090         /* Set the extraction length and index */
1091         attrs = ATTRELI_EL(priv->rx_stash_size) |
1092                 ATTRELI_EI(priv->rx_stash_index);
1093
1094         gfar_write(&priv->regs->attreli, attrs);
1095
1096         /* Start with defaults, and add stashing or locking
1097          * depending on the approprate variables */
1098         attrs = ATTR_INIT_SETTINGS;
1099
1100         if (priv->bd_stash_en)
1101                 attrs |= ATTR_BDSTASH;
1102
1103         if (priv->rx_stash_size != 0)
1104                 attrs |= ATTR_BUFSTASH;
1105
1106         gfar_write(&priv->regs->attr, attrs);
1107
1108         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1109         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1110         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1111
1112         /* Start the controller */
1113         gfar_start(dev);
1114
1115         return 0;
1116
1117 rx_irq_fail:
1118         free_irq(priv->interruptTransmit, dev);
1119 tx_irq_fail:
1120         free_irq(priv->interruptError, dev);
1121 err_irq_fail:
1122 err_rxalloc_fail:
1123 rx_skb_fail:
1124         free_skb_resources(priv);
1125 tx_skb_fail:
1126         dma_free_coherent(&dev->dev,
1127                         sizeof(struct txbd8)*priv->tx_ring_size
1128                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1129                         priv->tx_bd_base,
1130                         gfar_read(&regs->tbase0));
1131
1132         return err;
1133 }
1134
1135 /* Called when something needs to use the ethernet device */
1136 /* Returns 0 for success. */
1137 static int gfar_enet_open(struct net_device *dev)
1138 {
1139         struct gfar_private *priv = netdev_priv(dev);
1140         int err;
1141
1142         napi_enable(&priv->napi);
1143
1144         /* Initialize a bunch of registers */
1145         init_registers(dev);
1146
1147         gfar_set_mac_address(dev);
1148
1149         err = init_phy(dev);
1150
1151         if(err) {
1152                 napi_disable(&priv->napi);
1153                 return err;
1154         }
1155
1156         err = startup_gfar(dev);
1157         if (err) {
1158                 napi_disable(&priv->napi);
1159                 return err;
1160         }
1161
1162         netif_start_queue(dev);
1163
1164         return err;
1165 }
1166
1167 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1168 {
1169         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1170
1171         cacheable_memzero(fcb, GMAC_FCB_LEN);
1172
1173         return fcb;
1174 }
1175
1176 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1177 {
1178         u8 flags = 0;
1179
1180         /* If we're here, it's a IP packet with a TCP or UDP
1181          * payload.  We set it to checksum, using a pseudo-header
1182          * we provide
1183          */
1184         flags = TXFCB_DEFAULT;
1185
1186         /* Tell the controller what the protocol is */
1187         /* And provide the already calculated phcs */
1188         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1189                 flags |= TXFCB_UDP;
1190                 fcb->phcs = udp_hdr(skb)->check;
1191         } else
1192                 fcb->phcs = tcp_hdr(skb)->check;
1193
1194         /* l3os is the distance between the start of the
1195          * frame (skb->data) and the start of the IP hdr.
1196          * l4os is the distance between the start of the
1197          * l3 hdr and the l4 hdr */
1198         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1199         fcb->l4os = skb_network_header_len(skb);
1200
1201         fcb->flags = flags;
1202 }
1203
1204 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1205 {
1206         fcb->flags |= TXFCB_VLN;
1207         fcb->vlctl = vlan_tx_tag_get(skb);
1208 }
1209
1210 /* This is called by the kernel when a frame is ready for transmission. */
1211 /* It is pointed to by the dev->hard_start_xmit function pointer */
1212 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1213 {
1214         struct gfar_private *priv = netdev_priv(dev);
1215         struct txfcb *fcb = NULL;
1216         struct txbd8 *txbdp, *base;
1217         u32 lstatus;
1218         unsigned long flags;
1219
1220         /* Update transmit stats */
1221         dev->stats.tx_bytes += skb->len;
1222
1223         /* Lock priv now */
1224         spin_lock_irqsave(&priv->txlock, flags);
1225
1226         /* Point at the first free tx descriptor */
1227         txbdp = priv->cur_tx;
1228         base = priv->tx_bd_base;
1229
1230         /* Clear all but the WRAP status flags */
1231         lstatus = txbdp->lstatus & BD_LFLAG(TXBD_WRAP);
1232
1233         /* Set up checksumming */
1234         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1235                 fcb = gfar_add_fcb(skb);
1236                 lstatus |= BD_LFLAG(TXBD_TOE);
1237                 gfar_tx_checksum(skb, fcb);
1238         }
1239
1240         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1241                 if (unlikely(NULL == fcb)) {
1242                         fcb = gfar_add_fcb(skb);
1243                         lstatus |= BD_LFLAG(TXBD_TOE);
1244                 }
1245
1246                 gfar_tx_vlan(skb, fcb);
1247         }
1248
1249         /* Set buffer length and pointer */
1250         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1251                         skb->len, DMA_TO_DEVICE);
1252
1253         /* Save the skb pointer so we can free it later */
1254         priv->tx_skbuff[priv->skb_curtx] = skb;
1255
1256         /* Update the current skb pointer (wrapping if this was the last) */
1257         priv->skb_curtx =
1258             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1259
1260         /* Flag the BD as ready, interrupt-causing, last, and in need of CRC */
1261         lstatus |=
1262                 BD_LFLAG(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT) |
1263                 skb->len;
1264
1265         dev->trans_start = jiffies;
1266
1267         /* The powerpc-specific eieio() is used, as wmb() has too strong
1268          * semantics (it requires synchronization between cacheable and
1269          * uncacheable mappings, which eieio doesn't provide and which we
1270          * don't need), thus requiring a more expensive sync instruction.  At
1271          * some point, the set of architecture-independent barrier functions
1272          * should be expanded to include weaker barriers.
1273          */
1274
1275         eieio();
1276         txbdp->lstatus = lstatus;
1277
1278         txbdp = next_bd(txbdp, base, priv->tx_ring_size);
1279
1280         /* If the next BD still needs to be cleaned up, then the bds
1281            are full.  We need to tell the kernel to stop sending us stuff. */
1282         if (txbdp == priv->dirty_tx) {
1283                 netif_stop_queue(dev);
1284
1285                 dev->stats.tx_fifo_errors++;
1286         }
1287
1288         /* Update the current txbd to the next one */
1289         priv->cur_tx = txbdp;
1290
1291         /* Tell the DMA to go go go */
1292         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1293
1294         /* Unlock priv */
1295         spin_unlock_irqrestore(&priv->txlock, flags);
1296
1297         return 0;
1298 }
1299
1300 /* Stops the kernel queue, and halts the controller */
1301 static int gfar_close(struct net_device *dev)
1302 {
1303         struct gfar_private *priv = netdev_priv(dev);
1304
1305         napi_disable(&priv->napi);
1306
1307         cancel_work_sync(&priv->reset_task);
1308         stop_gfar(dev);
1309
1310         /* Disconnect from the PHY */
1311         phy_disconnect(priv->phydev);
1312         priv->phydev = NULL;
1313
1314         netif_stop_queue(dev);
1315
1316         return 0;
1317 }
1318
1319 /* Changes the mac address if the controller is not running. */
1320 static int gfar_set_mac_address(struct net_device *dev)
1321 {
1322         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1323
1324         return 0;
1325 }
1326
1327
1328 /* Enables and disables VLAN insertion/extraction */
1329 static void gfar_vlan_rx_register(struct net_device *dev,
1330                 struct vlan_group *grp)
1331 {
1332         struct gfar_private *priv = netdev_priv(dev);
1333         unsigned long flags;
1334         struct vlan_group *old_grp;
1335         u32 tempval;
1336
1337         spin_lock_irqsave(&priv->rxlock, flags);
1338
1339         old_grp = priv->vlgrp;
1340
1341         if (old_grp == grp)
1342                 return;
1343
1344         if (grp) {
1345                 /* Enable VLAN tag insertion */
1346                 tempval = gfar_read(&priv->regs->tctrl);
1347                 tempval |= TCTRL_VLINS;
1348
1349                 gfar_write(&priv->regs->tctrl, tempval);
1350
1351                 /* Enable VLAN tag extraction */
1352                 tempval = gfar_read(&priv->regs->rctrl);
1353                 tempval |= RCTRL_VLEX;
1354                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1355                 gfar_write(&priv->regs->rctrl, tempval);
1356         } else {
1357                 /* Disable VLAN tag insertion */
1358                 tempval = gfar_read(&priv->regs->tctrl);
1359                 tempval &= ~TCTRL_VLINS;
1360                 gfar_write(&priv->regs->tctrl, tempval);
1361
1362                 /* Disable VLAN tag extraction */
1363                 tempval = gfar_read(&priv->regs->rctrl);
1364                 tempval &= ~RCTRL_VLEX;
1365                 /* If parse is no longer required, then disable parser */
1366                 if (tempval & RCTRL_REQ_PARSER)
1367                         tempval |= RCTRL_PRSDEP_INIT;
1368                 else
1369                         tempval &= ~RCTRL_PRSDEP_INIT;
1370                 gfar_write(&priv->regs->rctrl, tempval);
1371         }
1372
1373         gfar_change_mtu(dev, dev->mtu);
1374
1375         spin_unlock_irqrestore(&priv->rxlock, flags);
1376 }
1377
1378 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1379 {
1380         int tempsize, tempval;
1381         struct gfar_private *priv = netdev_priv(dev);
1382         int oldsize = priv->rx_buffer_size;
1383         int frame_size = new_mtu + ETH_HLEN;
1384
1385         if (priv->vlgrp)
1386                 frame_size += VLAN_HLEN;
1387
1388         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1389                 if (netif_msg_drv(priv))
1390                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1391                                         dev->name);
1392                 return -EINVAL;
1393         }
1394
1395         if (gfar_uses_fcb(priv))
1396                 frame_size += GMAC_FCB_LEN;
1397
1398         frame_size += priv->padding;
1399
1400         tempsize =
1401             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1402             INCREMENTAL_BUFFER_SIZE;
1403
1404         /* Only stop and start the controller if it isn't already
1405          * stopped, and we changed something */
1406         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1407                 stop_gfar(dev);
1408
1409         priv->rx_buffer_size = tempsize;
1410
1411         dev->mtu = new_mtu;
1412
1413         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1414         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1415
1416         /* If the mtu is larger than the max size for standard
1417          * ethernet frames (ie, a jumbo frame), then set maccfg2
1418          * to allow huge frames, and to check the length */
1419         tempval = gfar_read(&priv->regs->maccfg2);
1420
1421         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1422                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1423         else
1424                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1425
1426         gfar_write(&priv->regs->maccfg2, tempval);
1427
1428         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1429                 startup_gfar(dev);
1430
1431         return 0;
1432 }
1433
1434 /* gfar_reset_task gets scheduled when a packet has not been
1435  * transmitted after a set amount of time.
1436  * For now, assume that clearing out all the structures, and
1437  * starting over will fix the problem.
1438  */
1439 static void gfar_reset_task(struct work_struct *work)
1440 {
1441         struct gfar_private *priv = container_of(work, struct gfar_private,
1442                         reset_task);
1443         struct net_device *dev = priv->dev;
1444
1445         if (dev->flags & IFF_UP) {
1446                 stop_gfar(dev);
1447                 startup_gfar(dev);
1448         }
1449
1450         netif_tx_schedule_all(dev);
1451 }
1452
1453 static void gfar_timeout(struct net_device *dev)
1454 {
1455         struct gfar_private *priv = netdev_priv(dev);
1456
1457         dev->stats.tx_errors++;
1458         schedule_work(&priv->reset_task);
1459 }
1460
1461 /* Interrupt Handler for Transmit complete */
1462 static int gfar_clean_tx_ring(struct net_device *dev)
1463 {
1464         struct txbd8 *bdp, *base;
1465         struct gfar_private *priv = netdev_priv(dev);
1466         int howmany = 0;
1467
1468         bdp = priv->dirty_tx;
1469         base = priv->tx_bd_base;
1470         while ((bdp->status & TXBD_READY) == 0) {
1471                 /* If dirty_tx and cur_tx are the same, then either the */
1472                 /* ring is empty or full now (it could only be full in the beginning, */
1473                 /* obviously).  If it is empty, we are done. */
1474                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1475                         break;
1476
1477                 howmany++;
1478
1479                 /* Deferred means some collisions occurred during transmit, */
1480                 /* but we eventually sent the packet. */
1481                 if (bdp->status & TXBD_DEF)
1482                         dev->stats.collisions++;
1483
1484                 /* Unmap the DMA memory */
1485                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1486                                 bdp->length, DMA_TO_DEVICE);
1487
1488                 /* Free the sk buffer associated with this TxBD */
1489                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1490
1491                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1492                 priv->skb_dirtytx =
1493                     (priv->skb_dirtytx +
1494                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1495
1496                 /* Clean BD length for empty detection */
1497                 bdp->length = 0;
1498
1499                 bdp = next_bd(bdp, base, priv->tx_ring_size);
1500
1501                 /* Move dirty_tx to be the next bd */
1502                 priv->dirty_tx = bdp;
1503
1504                 /* We freed a buffer, so now we can restart transmission */
1505                 if (netif_queue_stopped(dev))
1506                         netif_wake_queue(dev);
1507         } /* while ((bdp->status & TXBD_READY) == 0) */
1508
1509         dev->stats.tx_packets += howmany;
1510
1511         return howmany;
1512 }
1513
1514 /* Interrupt Handler for Transmit complete */
1515 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1516 {
1517         struct net_device *dev = (struct net_device *) dev_id;
1518         struct gfar_private *priv = netdev_priv(dev);
1519
1520         /* Clear IEVENT */
1521         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1522
1523         /* Lock priv */
1524         spin_lock(&priv->txlock);
1525
1526         gfar_clean_tx_ring(dev);
1527
1528         /* If we are coalescing the interrupts, reset the timer */
1529         /* Otherwise, clear it */
1530         if (likely(priv->txcoalescing)) {
1531                 gfar_write(&priv->regs->txic, 0);
1532                 gfar_write(&priv->regs->txic, priv->txic);
1533         }
1534
1535         spin_unlock(&priv->txlock);
1536
1537         return IRQ_HANDLED;
1538 }
1539
1540 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1541                 struct sk_buff *skb)
1542 {
1543         struct gfar_private *priv = netdev_priv(dev);
1544         u32 lstatus;
1545
1546         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1547                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1548
1549         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1550
1551         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1552                 lstatus |= BD_LFLAG(RXBD_WRAP);
1553
1554         eieio();
1555
1556         bdp->lstatus = lstatus;
1557 }
1558
1559
1560 struct sk_buff * gfar_new_skb(struct net_device *dev)
1561 {
1562         unsigned int alignamount;
1563         struct gfar_private *priv = netdev_priv(dev);
1564         struct sk_buff *skb = NULL;
1565
1566         /* We have to allocate the skb, so keep trying till we succeed */
1567         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1568
1569         if (!skb)
1570                 return NULL;
1571
1572         alignamount = RXBUF_ALIGNMENT -
1573                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1574
1575         /* We need the data buffer to be aligned properly.  We will reserve
1576          * as many bytes as needed to align the data properly
1577          */
1578         skb_reserve(skb, alignamount);
1579
1580         return skb;
1581 }
1582
1583 static inline void count_errors(unsigned short status, struct net_device *dev)
1584 {
1585         struct gfar_private *priv = netdev_priv(dev);
1586         struct net_device_stats *stats = &dev->stats;
1587         struct gfar_extra_stats *estats = &priv->extra_stats;
1588
1589         /* If the packet was truncated, none of the other errors
1590          * matter */
1591         if (status & RXBD_TRUNCATED) {
1592                 stats->rx_length_errors++;
1593
1594                 estats->rx_trunc++;
1595
1596                 return;
1597         }
1598         /* Count the errors, if there were any */
1599         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1600                 stats->rx_length_errors++;
1601
1602                 if (status & RXBD_LARGE)
1603                         estats->rx_large++;
1604                 else
1605                         estats->rx_short++;
1606         }
1607         if (status & RXBD_NONOCTET) {
1608                 stats->rx_frame_errors++;
1609                 estats->rx_nonoctet++;
1610         }
1611         if (status & RXBD_CRCERR) {
1612                 estats->rx_crcerr++;
1613                 stats->rx_crc_errors++;
1614         }
1615         if (status & RXBD_OVERRUN) {
1616                 estats->rx_overrun++;
1617                 stats->rx_crc_errors++;
1618         }
1619 }
1620
1621 irqreturn_t gfar_receive(int irq, void *dev_id)
1622 {
1623         struct net_device *dev = (struct net_device *) dev_id;
1624         struct gfar_private *priv = netdev_priv(dev);
1625         u32 tempval;
1626
1627         /* support NAPI */
1628         /* Clear IEVENT, so interrupts aren't called again
1629          * because of the packets that have already arrived */
1630         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1631
1632         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1633                 tempval = gfar_read(&priv->regs->imask);
1634                 tempval &= IMASK_RTX_DISABLED;
1635                 gfar_write(&priv->regs->imask, tempval);
1636
1637                 __netif_rx_schedule(dev, &priv->napi);
1638         } else {
1639                 if (netif_msg_rx_err(priv))
1640                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1641                                 dev->name, gfar_read(&priv->regs->ievent),
1642                                 gfar_read(&priv->regs->imask));
1643         }
1644
1645         return IRQ_HANDLED;
1646 }
1647
1648 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1649 {
1650         /* If valid headers were found, and valid sums
1651          * were verified, then we tell the kernel that no
1652          * checksumming is necessary.  Otherwise, it is */
1653         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1654                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1655         else
1656                 skb->ip_summed = CHECKSUM_NONE;
1657 }
1658
1659
1660 /* gfar_process_frame() -- handle one incoming packet if skb
1661  * isn't NULL.  */
1662 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1663                               int amount_pull)
1664 {
1665         struct gfar_private *priv = netdev_priv(dev);
1666         struct rxfcb *fcb = NULL;
1667
1668         int ret;
1669
1670         /* fcb is at the beginning if exists */
1671         fcb = (struct rxfcb *)skb->data;
1672
1673         /* Remove the FCB from the skb */
1674         /* Remove the padded bytes, if there are any */
1675         if (amount_pull)
1676                 skb_pull(skb, amount_pull);
1677
1678         if (priv->rx_csum_enable)
1679                 gfar_rx_checksum(skb, fcb);
1680
1681         /* Tell the skb what kind of packet this is */
1682         skb->protocol = eth_type_trans(skb, dev);
1683
1684         /* Send the packet up the stack */
1685         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1686                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1687         else
1688                 ret = netif_receive_skb(skb);
1689
1690         if (NET_RX_DROP == ret)
1691                 priv->extra_stats.kernel_dropped++;
1692
1693         return 0;
1694 }
1695
1696 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1697  *   until the budget/quota has been reached. Returns the number
1698  *   of frames handled
1699  */
1700 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1701 {
1702         struct rxbd8 *bdp, *base;
1703         struct sk_buff *skb;
1704         int pkt_len;
1705         int amount_pull;
1706         int howmany = 0;
1707         struct gfar_private *priv = netdev_priv(dev);
1708
1709         /* Get the first full descriptor */
1710         bdp = priv->cur_rx;
1711         base = priv->rx_bd_base;
1712
1713         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1714                 priv->padding;
1715
1716         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1717                 struct sk_buff *newskb;
1718                 rmb();
1719
1720                 /* Add another skb for the future */
1721                 newskb = gfar_new_skb(dev);
1722
1723                 skb = priv->rx_skbuff[priv->skb_currx];
1724
1725                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1726                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1727
1728                 /* We drop the frame if we failed to allocate a new buffer */
1729                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1730                                  bdp->status & RXBD_ERR)) {
1731                         count_errors(bdp->status, dev);
1732
1733                         if (unlikely(!newskb))
1734                                 newskb = skb;
1735
1736                         if (skb)
1737                                 dev_kfree_skb_any(skb);
1738                 } else {
1739                         /* Increment the number of packets */
1740                         dev->stats.rx_packets++;
1741                         howmany++;
1742
1743                         if (likely(skb)) {
1744                                 pkt_len = bdp->length - ETH_FCS_LEN;
1745                                 /* Remove the FCS from the packet length */
1746                                 skb_put(skb, pkt_len);
1747                                 dev->stats.rx_bytes += pkt_len;
1748
1749                                 gfar_process_frame(dev, skb, amount_pull);
1750
1751                         } else {
1752                                 if (netif_msg_rx_err(priv))
1753                                         printk(KERN_WARNING
1754                                                "%s: Missing skb!\n", dev->name);
1755                                 dev->stats.rx_dropped++;
1756                                 priv->extra_stats.rx_skbmissing++;
1757                         }
1758
1759                 }
1760
1761                 priv->rx_skbuff[priv->skb_currx] = newskb;
1762
1763                 /* Setup the new bdp */
1764                 gfar_new_rxbdp(dev, bdp, newskb);
1765
1766                 /* Update to the next pointer */
1767                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1768
1769                 /* update to point at the next skb */
1770                 priv->skb_currx =
1771                     (priv->skb_currx + 1) &
1772                     RX_RING_MOD_MASK(priv->rx_ring_size);
1773         }
1774
1775         /* Update the current rxbd pointer to be the next one */
1776         priv->cur_rx = bdp;
1777
1778         return howmany;
1779 }
1780
1781 static int gfar_poll(struct napi_struct *napi, int budget)
1782 {
1783         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1784         struct net_device *dev = priv->dev;
1785         int howmany;
1786         unsigned long flags;
1787
1788         /* If we fail to get the lock, don't bother with the TX BDs */
1789         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1790                 gfar_clean_tx_ring(dev);
1791                 spin_unlock_irqrestore(&priv->txlock, flags);
1792         }
1793
1794         howmany = gfar_clean_rx_ring(dev, budget);
1795
1796         if (howmany < budget) {
1797                 netif_rx_complete(dev, napi);
1798
1799                 /* Clear the halt bit in RSTAT */
1800                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1801
1802                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1803
1804                 /* If we are coalescing interrupts, update the timer */
1805                 /* Otherwise, clear it */
1806                 if (likely(priv->rxcoalescing)) {
1807                         gfar_write(&priv->regs->rxic, 0);
1808                         gfar_write(&priv->regs->rxic, priv->rxic);
1809                 }
1810         }
1811
1812         return howmany;
1813 }
1814
1815 #ifdef CONFIG_NET_POLL_CONTROLLER
1816 /*
1817  * Polling 'interrupt' - used by things like netconsole to send skbs
1818  * without having to re-enable interrupts. It's not called while
1819  * the interrupt routine is executing.
1820  */
1821 static void gfar_netpoll(struct net_device *dev)
1822 {
1823         struct gfar_private *priv = netdev_priv(dev);
1824
1825         /* If the device has multiple interrupts, run tx/rx */
1826         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1827                 disable_irq(priv->interruptTransmit);
1828                 disable_irq(priv->interruptReceive);
1829                 disable_irq(priv->interruptError);
1830                 gfar_interrupt(priv->interruptTransmit, dev);
1831                 enable_irq(priv->interruptError);
1832                 enable_irq(priv->interruptReceive);
1833                 enable_irq(priv->interruptTransmit);
1834         } else {
1835                 disable_irq(priv->interruptTransmit);
1836                 gfar_interrupt(priv->interruptTransmit, dev);
1837                 enable_irq(priv->interruptTransmit);
1838         }
1839 }
1840 #endif
1841
1842 /* The interrupt handler for devices with one interrupt */
1843 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1844 {
1845         struct net_device *dev = dev_id;
1846         struct gfar_private *priv = netdev_priv(dev);
1847
1848         /* Save ievent for future reference */
1849         u32 events = gfar_read(&priv->regs->ievent);
1850
1851         /* Check for reception */
1852         if (events & IEVENT_RX_MASK)
1853                 gfar_receive(irq, dev_id);
1854
1855         /* Check for transmit completion */
1856         if (events & IEVENT_TX_MASK)
1857                 gfar_transmit(irq, dev_id);
1858
1859         /* Check for errors */
1860         if (events & IEVENT_ERR_MASK)
1861                 gfar_error(irq, dev_id);
1862
1863         return IRQ_HANDLED;
1864 }
1865
1866 /* Called every time the controller might need to be made
1867  * aware of new link state.  The PHY code conveys this
1868  * information through variables in the phydev structure, and this
1869  * function converts those variables into the appropriate
1870  * register values, and can bring down the device if needed.
1871  */
1872 static void adjust_link(struct net_device *dev)
1873 {
1874         struct gfar_private *priv = netdev_priv(dev);
1875         struct gfar __iomem *regs = priv->regs;
1876         unsigned long flags;
1877         struct phy_device *phydev = priv->phydev;
1878         int new_state = 0;
1879
1880         spin_lock_irqsave(&priv->txlock, flags);
1881         if (phydev->link) {
1882                 u32 tempval = gfar_read(&regs->maccfg2);
1883                 u32 ecntrl = gfar_read(&regs->ecntrl);
1884
1885                 /* Now we make sure that we can be in full duplex mode.
1886                  * If not, we operate in half-duplex mode. */
1887                 if (phydev->duplex != priv->oldduplex) {
1888                         new_state = 1;
1889                         if (!(phydev->duplex))
1890                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1891                         else
1892                                 tempval |= MACCFG2_FULL_DUPLEX;
1893
1894                         priv->oldduplex = phydev->duplex;
1895                 }
1896
1897                 if (phydev->speed != priv->oldspeed) {
1898                         new_state = 1;
1899                         switch (phydev->speed) {
1900                         case 1000:
1901                                 tempval =
1902                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1903                                 break;
1904                         case 100:
1905                         case 10:
1906                                 tempval =
1907                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1908
1909                                 /* Reduced mode distinguishes
1910                                  * between 10 and 100 */
1911                                 if (phydev->speed == SPEED_100)
1912                                         ecntrl |= ECNTRL_R100;
1913                                 else
1914                                         ecntrl &= ~(ECNTRL_R100);
1915                                 break;
1916                         default:
1917                                 if (netif_msg_link(priv))
1918                                         printk(KERN_WARNING
1919                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1920                                                 dev->name, phydev->speed);
1921                                 break;
1922                         }
1923
1924                         priv->oldspeed = phydev->speed;
1925                 }
1926
1927                 gfar_write(&regs->maccfg2, tempval);
1928                 gfar_write(&regs->ecntrl, ecntrl);
1929
1930                 if (!priv->oldlink) {
1931                         new_state = 1;
1932                         priv->oldlink = 1;
1933                 }
1934         } else if (priv->oldlink) {
1935                 new_state = 1;
1936                 priv->oldlink = 0;
1937                 priv->oldspeed = 0;
1938                 priv->oldduplex = -1;
1939         }
1940
1941         if (new_state && netif_msg_link(priv))
1942                 phy_print_status(phydev);
1943
1944         spin_unlock_irqrestore(&priv->txlock, flags);
1945 }
1946
1947 /* Update the hash table based on the current list of multicast
1948  * addresses we subscribe to.  Also, change the promiscuity of
1949  * the device based on the flags (this function is called
1950  * whenever dev->flags is changed */
1951 static void gfar_set_multi(struct net_device *dev)
1952 {
1953         struct dev_mc_list *mc_ptr;
1954         struct gfar_private *priv = netdev_priv(dev);
1955         struct gfar __iomem *regs = priv->regs;
1956         u32 tempval;
1957
1958         if(dev->flags & IFF_PROMISC) {
1959                 /* Set RCTRL to PROM */
1960                 tempval = gfar_read(&regs->rctrl);
1961                 tempval |= RCTRL_PROM;
1962                 gfar_write(&regs->rctrl, tempval);
1963         } else {
1964                 /* Set RCTRL to not PROM */
1965                 tempval = gfar_read(&regs->rctrl);
1966                 tempval &= ~(RCTRL_PROM);
1967                 gfar_write(&regs->rctrl, tempval);
1968         }
1969
1970         if(dev->flags & IFF_ALLMULTI) {
1971                 /* Set the hash to rx all multicast frames */
1972                 gfar_write(&regs->igaddr0, 0xffffffff);
1973                 gfar_write(&regs->igaddr1, 0xffffffff);
1974                 gfar_write(&regs->igaddr2, 0xffffffff);
1975                 gfar_write(&regs->igaddr3, 0xffffffff);
1976                 gfar_write(&regs->igaddr4, 0xffffffff);
1977                 gfar_write(&regs->igaddr5, 0xffffffff);
1978                 gfar_write(&regs->igaddr6, 0xffffffff);
1979                 gfar_write(&regs->igaddr7, 0xffffffff);
1980                 gfar_write(&regs->gaddr0, 0xffffffff);
1981                 gfar_write(&regs->gaddr1, 0xffffffff);
1982                 gfar_write(&regs->gaddr2, 0xffffffff);
1983                 gfar_write(&regs->gaddr3, 0xffffffff);
1984                 gfar_write(&regs->gaddr4, 0xffffffff);
1985                 gfar_write(&regs->gaddr5, 0xffffffff);
1986                 gfar_write(&regs->gaddr6, 0xffffffff);
1987                 gfar_write(&regs->gaddr7, 0xffffffff);
1988         } else {
1989                 int em_num;
1990                 int idx;
1991
1992                 /* zero out the hash */
1993                 gfar_write(&regs->igaddr0, 0x0);
1994                 gfar_write(&regs->igaddr1, 0x0);
1995                 gfar_write(&regs->igaddr2, 0x0);
1996                 gfar_write(&regs->igaddr3, 0x0);
1997                 gfar_write(&regs->igaddr4, 0x0);
1998                 gfar_write(&regs->igaddr5, 0x0);
1999                 gfar_write(&regs->igaddr6, 0x0);
2000                 gfar_write(&regs->igaddr7, 0x0);
2001                 gfar_write(&regs->gaddr0, 0x0);
2002                 gfar_write(&regs->gaddr1, 0x0);
2003                 gfar_write(&regs->gaddr2, 0x0);
2004                 gfar_write(&regs->gaddr3, 0x0);
2005                 gfar_write(&regs->gaddr4, 0x0);
2006                 gfar_write(&regs->gaddr5, 0x0);
2007                 gfar_write(&regs->gaddr6, 0x0);
2008                 gfar_write(&regs->gaddr7, 0x0);
2009
2010                 /* If we have extended hash tables, we need to
2011                  * clear the exact match registers to prepare for
2012                  * setting them */
2013                 if (priv->extended_hash) {
2014                         em_num = GFAR_EM_NUM + 1;
2015                         gfar_clear_exact_match(dev);
2016                         idx = 1;
2017                 } else {
2018                         idx = 0;
2019                         em_num = 0;
2020                 }
2021
2022                 if(dev->mc_count == 0)
2023                         return;
2024
2025                 /* Parse the list, and set the appropriate bits */
2026                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2027                         if (idx < em_num) {
2028                                 gfar_set_mac_for_addr(dev, idx,
2029                                                 mc_ptr->dmi_addr);
2030                                 idx++;
2031                         } else
2032                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2033                 }
2034         }
2035
2036         return;
2037 }
2038
2039
2040 /* Clears each of the exact match registers to zero, so they
2041  * don't interfere with normal reception */
2042 static void gfar_clear_exact_match(struct net_device *dev)
2043 {
2044         int idx;
2045         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2046
2047         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2048                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2049 }
2050
2051 /* Set the appropriate hash bit for the given addr */
2052 /* The algorithm works like so:
2053  * 1) Take the Destination Address (ie the multicast address), and
2054  * do a CRC on it (little endian), and reverse the bits of the
2055  * result.
2056  * 2) Use the 8 most significant bits as a hash into a 256-entry
2057  * table.  The table is controlled through 8 32-bit registers:
2058  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2059  * gaddr7.  This means that the 3 most significant bits in the
2060  * hash index which gaddr register to use, and the 5 other bits
2061  * indicate which bit (assuming an IBM numbering scheme, which
2062  * for PowerPC (tm) is usually the case) in the register holds
2063  * the entry. */
2064 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2065 {
2066         u32 tempval;
2067         struct gfar_private *priv = netdev_priv(dev);
2068         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2069         int width = priv->hash_width;
2070         u8 whichbit = (result >> (32 - width)) & 0x1f;
2071         u8 whichreg = result >> (32 - width + 5);
2072         u32 value = (1 << (31-whichbit));
2073
2074         tempval = gfar_read(priv->hash_regs[whichreg]);
2075         tempval |= value;
2076         gfar_write(priv->hash_regs[whichreg], tempval);
2077
2078         return;
2079 }
2080
2081
2082 /* There are multiple MAC Address register pairs on some controllers
2083  * This function sets the numth pair to a given address
2084  */
2085 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2086 {
2087         struct gfar_private *priv = netdev_priv(dev);
2088         int idx;
2089         char tmpbuf[MAC_ADDR_LEN];
2090         u32 tempval;
2091         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2092
2093         macptr += num*2;
2094
2095         /* Now copy it into the mac registers backwards, cuz */
2096         /* little endian is silly */
2097         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2098                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2099
2100         gfar_write(macptr, *((u32 *) (tmpbuf)));
2101
2102         tempval = *((u32 *) (tmpbuf + 4));
2103
2104         gfar_write(macptr+1, tempval);
2105 }
2106
2107 /* GFAR error interrupt handler */
2108 static irqreturn_t gfar_error(int irq, void *dev_id)
2109 {
2110         struct net_device *dev = dev_id;
2111         struct gfar_private *priv = netdev_priv(dev);
2112
2113         /* Save ievent for future reference */
2114         u32 events = gfar_read(&priv->regs->ievent);
2115
2116         /* Clear IEVENT */
2117         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2118
2119         /* Magic Packet is not an error. */
2120         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2121             (events & IEVENT_MAG))
2122                 events &= ~IEVENT_MAG;
2123
2124         /* Hmm... */
2125         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2126                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2127                        dev->name, events, gfar_read(&priv->regs->imask));
2128
2129         /* Update the error counters */
2130         if (events & IEVENT_TXE) {
2131                 dev->stats.tx_errors++;
2132
2133                 if (events & IEVENT_LC)
2134                         dev->stats.tx_window_errors++;
2135                 if (events & IEVENT_CRL)
2136                         dev->stats.tx_aborted_errors++;
2137                 if (events & IEVENT_XFUN) {
2138                         if (netif_msg_tx_err(priv))
2139                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2140                                        "packet dropped.\n", dev->name);
2141                         dev->stats.tx_dropped++;
2142                         priv->extra_stats.tx_underrun++;
2143
2144                         /* Reactivate the Tx Queues */
2145                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2146                 }
2147                 if (netif_msg_tx_err(priv))
2148                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2149         }
2150         if (events & IEVENT_BSY) {
2151                 dev->stats.rx_errors++;
2152                 priv->extra_stats.rx_bsy++;
2153
2154                 gfar_receive(irq, dev_id);
2155
2156                 if (netif_msg_rx_err(priv))
2157                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2158                                dev->name, gfar_read(&priv->regs->rstat));
2159         }
2160         if (events & IEVENT_BABR) {
2161                 dev->stats.rx_errors++;
2162                 priv->extra_stats.rx_babr++;
2163
2164                 if (netif_msg_rx_err(priv))
2165                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2166         }
2167         if (events & IEVENT_EBERR) {
2168                 priv->extra_stats.eberr++;
2169                 if (netif_msg_rx_err(priv))
2170                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2171         }
2172         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2173                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2174
2175         if (events & IEVENT_BABT) {
2176                 priv->extra_stats.tx_babt++;
2177                 if (netif_msg_tx_err(priv))
2178                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2179         }
2180         return IRQ_HANDLED;
2181 }
2182
2183 /* work with hotplug and coldplug */
2184 MODULE_ALIAS("platform:fsl-gianfar");
2185
2186 static struct of_device_id gfar_match[] =
2187 {
2188         {
2189                 .type = "network",
2190                 .compatible = "gianfar",
2191         },
2192         {},
2193 };
2194
2195 /* Structure for a device driver */
2196 static struct of_platform_driver gfar_driver = {
2197         .name = "fsl-gianfar",
2198         .match_table = gfar_match,
2199
2200         .probe = gfar_probe,
2201         .remove = gfar_remove,
2202         .suspend = gfar_suspend,
2203         .resume = gfar_resume,
2204 };
2205
2206 static int __init gfar_init(void)
2207 {
2208         int err = gfar_mdio_init();
2209
2210         if (err)
2211                 return err;
2212
2213         err = of_register_platform_driver(&gfar_driver);
2214
2215         if (err)
2216                 gfar_mdio_exit();
2217
2218         return err;
2219 }
2220
2221 static void __exit gfar_exit(void)
2222 {
2223         of_unregister_platform_driver(&gfar_driver);
2224         gfar_mdio_exit();
2225 }
2226
2227 module_init(gfar_init);
2228 module_exit(gfar_exit);
2229