2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
42 #define FORCEDETH_VERSION "0.63"
43 #define DRV_NAME "forcedeth"
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
68 #define dprintk printk
70 #define dprintk(x...) do { } while (0)
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
80 #define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x000040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x000600 /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3 0x000e00 /* device supports hw statistics version 3 */
92 #define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */
100 #define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */
103 NvRegIrqStatus = 0x000,
104 #define NVREG_IRQSTAT_MIIEVENT 0x040
105 #define NVREG_IRQSTAT_MASK 0x83ff
106 NvRegIrqMask = 0x004,
107 #define NVREG_IRQ_RX_ERROR 0x0001
108 #define NVREG_IRQ_RX 0x0002
109 #define NVREG_IRQ_RX_NOBUF 0x0004
110 #define NVREG_IRQ_TX_ERR 0x0008
111 #define NVREG_IRQ_TX_OK 0x0010
112 #define NVREG_IRQ_TIMER 0x0020
113 #define NVREG_IRQ_LINK 0x0040
114 #define NVREG_IRQ_RX_FORCED 0x0080
115 #define NVREG_IRQ_TX_FORCED 0x0100
116 #define NVREG_IRQ_RECOVER_ERROR 0x8200
117 #define NVREG_IRQMASK_THROUGHPUT 0x00df
118 #define NVREG_IRQMASK_CPU 0x0060
119 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
121 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
123 NvRegUnknownSetupReg6 = 0x008,
124 #define NVREG_UNKSETUP6_VAL 3
127 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
128 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
130 NvRegPollingInterval = 0x00c,
131 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
132 #define NVREG_POLL_DEFAULT_CPU 13
133 NvRegMSIMap0 = 0x020,
134 NvRegMSIMap1 = 0x024,
135 NvRegMSIIrqMask = 0x030,
136 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
138 #define NVREG_MISC1_PAUSE_TX 0x01
139 #define NVREG_MISC1_HD 0x02
140 #define NVREG_MISC1_FORCE 0x3b0f3c
142 NvRegMacReset = 0x34,
143 #define NVREG_MAC_RESET_ASSERT 0x0F3
144 NvRegTransmitterControl = 0x084,
145 #define NVREG_XMITCTL_START 0x01
146 #define NVREG_XMITCTL_MGMT_ST 0x40000000
147 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
148 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
149 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
150 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
151 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
152 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
153 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
154 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
155 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
156 #define NVREG_XMITCTL_DATA_START 0x00100000
157 #define NVREG_XMITCTL_DATA_READY 0x00010000
158 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
159 NvRegTransmitterStatus = 0x088,
160 #define NVREG_XMITSTAT_BUSY 0x01
162 NvRegPacketFilterFlags = 0x8c,
163 #define NVREG_PFF_PAUSE_RX 0x08
164 #define NVREG_PFF_ALWAYS 0x7F0000
165 #define NVREG_PFF_PROMISC 0x80
166 #define NVREG_PFF_MYADDR 0x20
167 #define NVREG_PFF_LOOPBACK 0x10
169 NvRegOffloadConfig = 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY 0x601
171 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
172 NvRegReceiverControl = 0x094,
173 #define NVREG_RCVCTL_START 0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175 NvRegReceiverStatus = 0x98,
176 #define NVREG_RCVSTAT_BUSY 0x01
178 NvRegSlotTime = 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
182 #define NVREG_SLOTTIME_HALF 0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
184 #define NVREG_SLOTTIME_MASK 0x000000ff
186 NvRegTxDeferral = 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
193 NvRegRxDeferral = 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
195 NvRegMacAddrA = 0xA8,
196 NvRegMacAddrB = 0xAC,
197 NvRegMulticastAddrA = 0xB0,
198 #define NVREG_MCASTADDRA_FORCE 0x01
199 NvRegMulticastAddrB = 0xB4,
200 NvRegMulticastMaskA = 0xB8,
201 #define NVREG_MCASTMASKA_NONE 0xffffffff
202 NvRegMulticastMaskB = 0xBC,
203 #define NVREG_MCASTMASKB_NONE 0xffff
205 NvRegPhyInterface = 0xC0,
206 #define PHY_RGMII 0x10000000
207 NvRegBackOffControl = 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT 24
211 #define NVREG_BKOFFCTRL_GEAR 12
213 NvRegTxRingPhysAddr = 0x100,
214 NvRegRxRingPhysAddr = 0x104,
215 NvRegRingSizes = 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218 NvRegTransmitPoll = 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220 NvRegLinkSpeed = 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10 1000
223 #define NVREG_LINKSPEED_100 100
224 #define NVREG_LINKSPEED_1000 50
225 #define NVREG_LINKSPEED_MASK (0xFFF)
226 NvRegUnknownSetupReg5 = 0x130,
227 #define NVREG_UNKSETUP5_BIT31 (1<<31)
228 NvRegTxWatermark = 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
232 NvRegTxRxControl = 0x144,
233 #define NVREG_TXRXCTL_KICK 0x0001
234 #define NVREG_TXRXCTL_BIT1 0x0002
235 #define NVREG_TXRXCTL_BIT2 0x0004
236 #define NVREG_TXRXCTL_IDLE 0x0008
237 #define NVREG_TXRXCTL_RESET 0x0010
238 #define NVREG_TXRXCTL_RXCHECK 0x0400
239 #define NVREG_TXRXCTL_DESC_1 0
240 #define NVREG_TXRXCTL_DESC_2 0x002100
241 #define NVREG_TXRXCTL_DESC_3 0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS 0x00080
244 NvRegTxRingPhysAddrHigh = 0x148,
245 NvRegRxRingPhysAddrHigh = 0x14C,
246 NvRegTxPauseFrame = 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
251 NvRegTxPauseFrameLimit = 0x174,
252 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
253 NvRegMIIStatus = 0x180,
254 #define NVREG_MIISTAT_ERROR 0x0001
255 #define NVREG_MIISTAT_LINKCHANGE 0x0008
256 #define NVREG_MIISTAT_MASK_RW 0x0007
257 #define NVREG_MIISTAT_MASK_ALL 0x000f
258 NvRegMIIMask = 0x184,
259 #define NVREG_MII_LINKCHANGE 0x0008
261 NvRegAdapterControl = 0x188,
262 #define NVREG_ADAPTCTL_START 0x02
263 #define NVREG_ADAPTCTL_LINKUP 0x04
264 #define NVREG_ADAPTCTL_PHYVALID 0x40000
265 #define NVREG_ADAPTCTL_RUNNING 0x100000
266 #define NVREG_ADAPTCTL_PHYSHIFT 24
267 NvRegMIISpeed = 0x18c,
268 #define NVREG_MIISPEED_BIT8 (1<<8)
269 #define NVREG_MIIDELAY 5
270 NvRegMIIControl = 0x190,
271 #define NVREG_MIICTL_INUSE 0x08000
272 #define NVREG_MIICTL_WRITE 0x00400
273 #define NVREG_MIICTL_ADDRSHIFT 5
274 NvRegMIIData = 0x194,
275 NvRegTxUnicast = 0x1a0,
276 NvRegTxMulticast = 0x1a4,
277 NvRegTxBroadcast = 0x1a8,
278 NvRegWakeUpFlags = 0x200,
279 #define NVREG_WAKEUPFLAGS_VAL 0x7770
280 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
281 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
282 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
283 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
284 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
285 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
286 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
287 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
288 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
289 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
291 NvRegMgmtUnitGetVersion = 0x204,
292 #define NVREG_MGMTUNITGETVERSION 0x01
293 NvRegMgmtUnitVersion = 0x208,
294 #define NVREG_MGMTUNITVERSION 0x08
295 NvRegPowerCap = 0x268,
296 #define NVREG_POWERCAP_D3SUPP (1<<30)
297 #define NVREG_POWERCAP_D2SUPP (1<<26)
298 #define NVREG_POWERCAP_D1SUPP (1<<25)
299 NvRegPowerState = 0x26c,
300 #define NVREG_POWERSTATE_POWEREDUP 0x8000
301 #define NVREG_POWERSTATE_VALID 0x0100
302 #define NVREG_POWERSTATE_MASK 0x0003
303 #define NVREG_POWERSTATE_D0 0x0000
304 #define NVREG_POWERSTATE_D1 0x0001
305 #define NVREG_POWERSTATE_D2 0x0002
306 #define NVREG_POWERSTATE_D3 0x0003
307 NvRegMgmtUnitControl = 0x278,
308 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
310 NvRegTxZeroReXmt = 0x284,
311 NvRegTxOneReXmt = 0x288,
312 NvRegTxManyReXmt = 0x28c,
313 NvRegTxLateCol = 0x290,
314 NvRegTxUnderflow = 0x294,
315 NvRegTxLossCarrier = 0x298,
316 NvRegTxExcessDef = 0x29c,
317 NvRegTxRetryErr = 0x2a0,
318 NvRegRxFrameErr = 0x2a4,
319 NvRegRxExtraByte = 0x2a8,
320 NvRegRxLateCol = 0x2ac,
322 NvRegRxFrameTooLong = 0x2b4,
323 NvRegRxOverflow = 0x2b8,
324 NvRegRxFCSErr = 0x2bc,
325 NvRegRxFrameAlignErr = 0x2c0,
326 NvRegRxLenErr = 0x2c4,
327 NvRegRxUnicast = 0x2c8,
328 NvRegRxMulticast = 0x2cc,
329 NvRegRxBroadcast = 0x2d0,
331 NvRegTxFrame = 0x2d8,
333 NvRegTxPause = 0x2e0,
334 NvRegRxPause = 0x2e4,
335 NvRegRxDropFrame = 0x2e8,
336 NvRegVlanControl = 0x300,
337 #define NVREG_VLANCONTROL_ENABLE 0x2000
338 NvRegMSIXMap0 = 0x3e0,
339 NvRegMSIXMap1 = 0x3e4,
340 NvRegMSIXIrqStatus = 0x3f0,
342 NvRegPowerState2 = 0x600,
343 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
344 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
345 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
348 /* Big endian: should work, but is untested */
354 struct ring_desc_ex {
362 struct ring_desc* orig;
363 struct ring_desc_ex* ex;
366 #define FLAG_MASK_V1 0xffff0000
367 #define FLAG_MASK_V2 0xffffc000
368 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
369 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
371 #define NV_TX_LASTPACKET (1<<16)
372 #define NV_TX_RETRYERROR (1<<19)
373 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
374 #define NV_TX_FORCED_INTERRUPT (1<<24)
375 #define NV_TX_DEFERRED (1<<26)
376 #define NV_TX_CARRIERLOST (1<<27)
377 #define NV_TX_LATECOLLISION (1<<28)
378 #define NV_TX_UNDERFLOW (1<<29)
379 #define NV_TX_ERROR (1<<30)
380 #define NV_TX_VALID (1<<31)
382 #define NV_TX2_LASTPACKET (1<<29)
383 #define NV_TX2_RETRYERROR (1<<18)
384 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
385 #define NV_TX2_FORCED_INTERRUPT (1<<30)
386 #define NV_TX2_DEFERRED (1<<25)
387 #define NV_TX2_CARRIERLOST (1<<26)
388 #define NV_TX2_LATECOLLISION (1<<27)
389 #define NV_TX2_UNDERFLOW (1<<28)
390 /* error and valid are the same for both */
391 #define NV_TX2_ERROR (1<<30)
392 #define NV_TX2_VALID (1<<31)
393 #define NV_TX2_TSO (1<<28)
394 #define NV_TX2_TSO_SHIFT 14
395 #define NV_TX2_TSO_MAX_SHIFT 14
396 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
397 #define NV_TX2_CHECKSUM_L3 (1<<27)
398 #define NV_TX2_CHECKSUM_L4 (1<<26)
400 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
402 #define NV_RX_DESCRIPTORVALID (1<<16)
403 #define NV_RX_MISSEDFRAME (1<<17)
404 #define NV_RX_SUBSTRACT1 (1<<18)
405 #define NV_RX_ERROR1 (1<<23)
406 #define NV_RX_ERROR2 (1<<24)
407 #define NV_RX_ERROR3 (1<<25)
408 #define NV_RX_ERROR4 (1<<26)
409 #define NV_RX_CRCERR (1<<27)
410 #define NV_RX_OVERFLOW (1<<28)
411 #define NV_RX_FRAMINGERR (1<<29)
412 #define NV_RX_ERROR (1<<30)
413 #define NV_RX_AVAIL (1<<31)
414 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
416 #define NV_RX2_CHECKSUMMASK (0x1C000000)
417 #define NV_RX2_CHECKSUM_IP (0x10000000)
418 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
419 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
420 #define NV_RX2_DESCRIPTORVALID (1<<29)
421 #define NV_RX2_SUBSTRACT1 (1<<25)
422 #define NV_RX2_ERROR1 (1<<18)
423 #define NV_RX2_ERROR2 (1<<19)
424 #define NV_RX2_ERROR3 (1<<20)
425 #define NV_RX2_ERROR4 (1<<21)
426 #define NV_RX2_CRCERR (1<<22)
427 #define NV_RX2_OVERFLOW (1<<23)
428 #define NV_RX2_FRAMINGERR (1<<24)
429 /* error and avail are the same for both */
430 #define NV_RX2_ERROR (1<<30)
431 #define NV_RX2_AVAIL (1<<31)
432 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
434 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
435 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
437 /* Miscelaneous hardware related defines: */
438 #define NV_PCI_REGSZ_VER1 0x270
439 #define NV_PCI_REGSZ_VER2 0x2d4
440 #define NV_PCI_REGSZ_VER3 0x604
441 #define NV_PCI_REGSZ_MAX 0x604
443 /* various timeout delays: all in usec */
444 #define NV_TXRX_RESET_DELAY 4
445 #define NV_TXSTOP_DELAY1 10
446 #define NV_TXSTOP_DELAY1MAX 500000
447 #define NV_TXSTOP_DELAY2 100
448 #define NV_RXSTOP_DELAY1 10
449 #define NV_RXSTOP_DELAY1MAX 500000
450 #define NV_RXSTOP_DELAY2 100
451 #define NV_SETUP5_DELAY 5
452 #define NV_SETUP5_DELAYMAX 50000
453 #define NV_POWERUP_DELAY 5
454 #define NV_POWERUP_DELAYMAX 5000
455 #define NV_MIIBUSY_DELAY 50
456 #define NV_MIIPHY_DELAY 10
457 #define NV_MIIPHY_DELAYMAX 10000
458 #define NV_MAC_RESET_DELAY 64
460 #define NV_WAKEUPPATTERNS 5
461 #define NV_WAKEUPMASKENTRIES 4
463 /* General driver defaults */
464 #define NV_WATCHDOG_TIMEO (5*HZ)
466 #define RX_RING_DEFAULT 128
467 #define TX_RING_DEFAULT 256
468 #define RX_RING_MIN 128
469 #define TX_RING_MIN 64
470 #define RING_MAX_DESC_VER_1 1024
471 #define RING_MAX_DESC_VER_2_3 16384
473 /* rx/tx mac addr + type + vlan + align + slack*/
474 #define NV_RX_HEADERS (64)
475 /* even more slack. */
476 #define NV_RX_ALLOC_PAD (64)
478 /* maximum mtu size */
479 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
480 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
482 #define OOM_REFILL (1+HZ/20)
483 #define POLL_WAIT (1+HZ/100)
484 #define LINK_TIMEOUT (3*HZ)
485 #define STATS_INTERVAL (10*HZ)
489 * The nic supports three different descriptor types:
490 * - DESC_VER_1: Original
491 * - DESC_VER_2: support for jumbo frames.
492 * - DESC_VER_3: 64-bit format.
499 #define PHY_OUI_MARVELL 0x5043
500 #define PHY_OUI_CICADA 0x03f1
501 #define PHY_OUI_VITESSE 0x01c1
502 #define PHY_OUI_REALTEK 0x0732
503 #define PHY_OUI_REALTEK2 0x0020
504 #define PHYID1_OUI_MASK 0x03ff
505 #define PHYID1_OUI_SHFT 6
506 #define PHYID2_OUI_MASK 0xfc00
507 #define PHYID2_OUI_SHFT 10
508 #define PHYID2_MODEL_MASK 0x03f0
509 #define PHY_MODEL_REALTEK_8211 0x0110
510 #define PHY_REV_MASK 0x0001
511 #define PHY_REV_REALTEK_8211B 0x0000
512 #define PHY_REV_REALTEK_8211C 0x0001
513 #define PHY_MODEL_REALTEK_8201 0x0200
514 #define PHY_MODEL_MARVELL_E3016 0x0220
515 #define PHY_MARVELL_E3016_INITMASK 0x0300
516 #define PHY_CICADA_INIT1 0x0f000
517 #define PHY_CICADA_INIT2 0x0e00
518 #define PHY_CICADA_INIT3 0x01000
519 #define PHY_CICADA_INIT4 0x0200
520 #define PHY_CICADA_INIT5 0x0004
521 #define PHY_CICADA_INIT6 0x02000
522 #define PHY_VITESSE_INIT_REG1 0x1f
523 #define PHY_VITESSE_INIT_REG2 0x10
524 #define PHY_VITESSE_INIT_REG3 0x11
525 #define PHY_VITESSE_INIT_REG4 0x12
526 #define PHY_VITESSE_INIT_MSK1 0xc
527 #define PHY_VITESSE_INIT_MSK2 0x0180
528 #define PHY_VITESSE_INIT1 0x52b5
529 #define PHY_VITESSE_INIT2 0xaf8a
530 #define PHY_VITESSE_INIT3 0x8
531 #define PHY_VITESSE_INIT4 0x8f8a
532 #define PHY_VITESSE_INIT5 0xaf86
533 #define PHY_VITESSE_INIT6 0x8f86
534 #define PHY_VITESSE_INIT7 0xaf82
535 #define PHY_VITESSE_INIT8 0x0100
536 #define PHY_VITESSE_INIT9 0x8f82
537 #define PHY_VITESSE_INIT10 0x0
538 #define PHY_REALTEK_INIT_REG1 0x1f
539 #define PHY_REALTEK_INIT_REG2 0x19
540 #define PHY_REALTEK_INIT_REG3 0x13
541 #define PHY_REALTEK_INIT_REG4 0x14
542 #define PHY_REALTEK_INIT_REG5 0x18
543 #define PHY_REALTEK_INIT_REG6 0x11
544 #define PHY_REALTEK_INIT_REG7 0x01
545 #define PHY_REALTEK_INIT1 0x0000
546 #define PHY_REALTEK_INIT2 0x8e00
547 #define PHY_REALTEK_INIT3 0x0001
548 #define PHY_REALTEK_INIT4 0xad17
549 #define PHY_REALTEK_INIT5 0xfb54
550 #define PHY_REALTEK_INIT6 0xf5c7
551 #define PHY_REALTEK_INIT7 0x1000
552 #define PHY_REALTEK_INIT8 0x0003
553 #define PHY_REALTEK_INIT9 0x0008
554 #define PHY_REALTEK_INIT10 0x0005
555 #define PHY_REALTEK_INIT11 0x0200
556 #define PHY_REALTEK_INIT_MSK1 0x0003
558 #define PHY_GIGABIT 0x0100
560 #define PHY_TIMEOUT 0x1
561 #define PHY_ERROR 0x2
565 #define PHY_HALF 0x100
567 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
568 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
569 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
570 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
571 #define NV_PAUSEFRAME_RX_REQ 0x0010
572 #define NV_PAUSEFRAME_TX_REQ 0x0020
573 #define NV_PAUSEFRAME_AUTONEG 0x0040
575 /* MSI/MSI-X defines */
576 #define NV_MSI_X_MAX_VECTORS 8
577 #define NV_MSI_X_VECTORS_MASK 0x000f
578 #define NV_MSI_CAPABLE 0x0010
579 #define NV_MSI_X_CAPABLE 0x0020
580 #define NV_MSI_ENABLED 0x0040
581 #define NV_MSI_X_ENABLED 0x0080
583 #define NV_MSI_X_VECTOR_ALL 0x0
584 #define NV_MSI_X_VECTOR_RX 0x0
585 #define NV_MSI_X_VECTOR_TX 0x1
586 #define NV_MSI_X_VECTOR_OTHER 0x2
588 #define NV_MSI_PRIV_OFFSET 0x68
589 #define NV_MSI_PRIV_VALUE 0xffffffff
591 #define NV_RESTART_TX 0x1
592 #define NV_RESTART_RX 0x2
594 #define NV_TX_LIMIT_COUNT 16
597 struct nv_ethtool_str {
598 char name[ETH_GSTRING_LEN];
601 static const struct nv_ethtool_str nv_estats_str[] = {
606 { "tx_late_collision" },
607 { "tx_fifo_errors" },
608 { "tx_carrier_errors" },
609 { "tx_excess_deferral" },
610 { "tx_retry_error" },
611 { "rx_frame_error" },
613 { "rx_late_collision" },
615 { "rx_frame_too_long" },
616 { "rx_over_errors" },
618 { "rx_frame_align_error" },
619 { "rx_length_error" },
624 { "rx_errors_total" },
625 { "tx_errors_total" },
627 /* version 2 stats */
635 /* version 3 stats */
641 struct nv_ethtool_stats {
646 u64 tx_late_collision;
648 u64 tx_carrier_errors;
649 u64 tx_excess_deferral;
653 u64 rx_late_collision;
655 u64 rx_frame_too_long;
658 u64 rx_frame_align_error;
667 /* version 2 stats */
675 /* version 3 stats */
681 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
682 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
683 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
686 #define NV_TEST_COUNT_BASE 3
687 #define NV_TEST_COUNT_EXTENDED 4
689 static const struct nv_ethtool_str nv_etests_str[] = {
690 { "link (online/offline)" },
691 { "register (offline) " },
692 { "interrupt (offline) " },
693 { "loopback (offline) " }
696 struct register_test {
701 static const struct register_test nv_registers_test[] = {
702 { NvRegUnknownSetupReg6, 0x01 },
703 { NvRegMisc1, 0x03c },
704 { NvRegOffloadConfig, 0x03ff },
705 { NvRegMulticastAddrA, 0xffffffff },
706 { NvRegTxWatermark, 0x0ff },
707 { NvRegWakeUpFlags, 0x07777 },
714 unsigned int dma_len;
715 struct ring_desc_ex *first_tx_desc;
716 struct nv_skb_map *next_tx_ctx;
721 * All hardware access under netdev_priv(dev)->lock, except the performance
723 * - rx is (pseudo-) lockless: it relies on the single-threading provided
724 * by the arch code for interrupts.
725 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
726 * needs netdev_priv(dev)->lock :-(
727 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
730 /* in dev: base, irq */
734 struct net_device *dev;
735 struct napi_struct napi;
738 * Locking: spin_lock(&np->lock); */
739 struct nv_ethtool_stats estats;
747 unsigned int phy_oui;
748 unsigned int phy_model;
749 unsigned int phy_rev;
754 /* General data: RO fields */
755 dma_addr_t ring_addr;
756 struct pci_dev *pci_dev;
773 /* rx specific fields.
774 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
776 union ring_type get_rx, put_rx, first_rx, last_rx;
777 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
778 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
779 struct nv_skb_map *rx_skb;
781 union ring_type rx_ring;
782 unsigned int rx_buf_sz;
783 unsigned int pkt_limit;
784 struct timer_list oom_kick;
785 struct timer_list nic_poll;
786 struct timer_list stats_poll;
790 /* media detection workaround.
791 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
794 unsigned long link_timeout;
796 * tx specific fields.
798 union ring_type get_tx, put_tx, first_tx, last_tx;
799 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
800 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
801 struct nv_skb_map *tx_skb;
803 union ring_type tx_ring;
807 u32 tx_pkts_in_progress;
808 struct nv_skb_map *tx_change_owner;
809 struct nv_skb_map *tx_end_flip;
813 struct vlan_group *vlangrp;
815 /* msi/msi-x fields */
817 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
822 /* power saved state */
823 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
825 /* for different msi-x irq type */
826 char name_rx[IFNAMSIZ + 3]; /* -rx */
827 char name_tx[IFNAMSIZ + 3]; /* -tx */
828 char name_other[IFNAMSIZ + 6]; /* -other */
832 * Maximum number of loops until we assume that a bit in the irq mask
833 * is stuck. Overridable with module param.
835 static int max_interrupt_work = 15;
838 * Optimization can be either throuput mode or cpu mode
840 * Throughput Mode: Every tx and rx packet will generate an interrupt.
841 * CPU Mode: Interrupts are controlled by a timer.
844 NV_OPTIMIZATION_MODE_THROUGHPUT,
845 NV_OPTIMIZATION_MODE_CPU,
846 NV_OPTIMIZATION_MODE_DYNAMIC
848 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
851 * Poll interval for timer irq
853 * This interval determines how frequent an interrupt is generated.
854 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
855 * Min = 0, and Max = 65535
857 static int poll_interval = -1;
866 static int msi = NV_MSI_INT_ENABLED;
872 NV_MSIX_INT_DISABLED,
875 static int msix = NV_MSIX_INT_ENABLED;
881 NV_DMA_64BIT_DISABLED,
884 static int dma_64bit = NV_DMA_64BIT_ENABLED;
887 * Crossover Detection
888 * Realtek 8201 phy + some OEM boards do not work properly.
891 NV_CROSSOVER_DETECTION_DISABLED,
892 NV_CROSSOVER_DETECTION_ENABLED
894 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
896 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
898 return netdev_priv(dev);
901 static inline u8 __iomem *get_hwbase(struct net_device *dev)
903 return ((struct fe_priv *)netdev_priv(dev))->base;
906 static inline void pci_push(u8 __iomem *base)
908 /* force out pending posted writes */
912 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
914 return le32_to_cpu(prd->flaglen)
915 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
918 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
920 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
923 static bool nv_optimized(struct fe_priv *np)
925 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
930 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
931 int delay, int delaymax, const char *msg)
933 u8 __iomem *base = get_hwbase(dev);
944 } while ((readl(base + offset) & mask) != target);
948 #define NV_SETUP_RX_RING 0x01
949 #define NV_SETUP_TX_RING 0x02
951 static inline u32 dma_low(dma_addr_t addr)
956 static inline u32 dma_high(dma_addr_t addr)
958 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
961 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
963 struct fe_priv *np = get_nvpriv(dev);
964 u8 __iomem *base = get_hwbase(dev);
966 if (!nv_optimized(np)) {
967 if (rxtx_flags & NV_SETUP_RX_RING) {
968 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
970 if (rxtx_flags & NV_SETUP_TX_RING) {
971 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
974 if (rxtx_flags & NV_SETUP_RX_RING) {
975 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
976 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
978 if (rxtx_flags & NV_SETUP_TX_RING) {
979 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
980 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
985 static void free_rings(struct net_device *dev)
987 struct fe_priv *np = get_nvpriv(dev);
989 if (!nv_optimized(np)) {
990 if (np->rx_ring.orig)
991 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
992 np->rx_ring.orig, np->ring_addr);
995 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
996 np->rx_ring.ex, np->ring_addr);
1004 static int using_multi_irqs(struct net_device *dev)
1006 struct fe_priv *np = get_nvpriv(dev);
1008 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1009 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1010 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1016 static void nv_enable_irq(struct net_device *dev)
1018 struct fe_priv *np = get_nvpriv(dev);
1020 if (!using_multi_irqs(dev)) {
1021 if (np->msi_flags & NV_MSI_X_ENABLED)
1022 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1024 enable_irq(np->pci_dev->irq);
1026 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1027 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1028 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1032 static void nv_disable_irq(struct net_device *dev)
1034 struct fe_priv *np = get_nvpriv(dev);
1036 if (!using_multi_irqs(dev)) {
1037 if (np->msi_flags & NV_MSI_X_ENABLED)
1038 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1040 disable_irq(np->pci_dev->irq);
1042 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1043 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1044 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1048 /* In MSIX mode, a write to irqmask behaves as XOR */
1049 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1051 u8 __iomem *base = get_hwbase(dev);
1053 writel(mask, base + NvRegIrqMask);
1056 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1058 struct fe_priv *np = get_nvpriv(dev);
1059 u8 __iomem *base = get_hwbase(dev);
1061 if (np->msi_flags & NV_MSI_X_ENABLED) {
1062 writel(mask, base + NvRegIrqMask);
1064 if (np->msi_flags & NV_MSI_ENABLED)
1065 writel(0, base + NvRegMSIIrqMask);
1066 writel(0, base + NvRegIrqMask);
1070 static void nv_napi_enable(struct net_device *dev)
1072 #ifdef CONFIG_FORCEDETH_NAPI
1073 struct fe_priv *np = get_nvpriv(dev);
1075 napi_enable(&np->napi);
1079 static void nv_napi_disable(struct net_device *dev)
1081 #ifdef CONFIG_FORCEDETH_NAPI
1082 struct fe_priv *np = get_nvpriv(dev);
1084 napi_disable(&np->napi);
1088 #define MII_READ (-1)
1089 /* mii_rw: read/write a register on the PHY.
1091 * Caller must guarantee serialization
1093 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1095 u8 __iomem *base = get_hwbase(dev);
1099 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1101 reg = readl(base + NvRegMIIControl);
1102 if (reg & NVREG_MIICTL_INUSE) {
1103 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1104 udelay(NV_MIIBUSY_DELAY);
1107 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1108 if (value != MII_READ) {
1109 writel(value, base + NvRegMIIData);
1110 reg |= NVREG_MIICTL_WRITE;
1112 writel(reg, base + NvRegMIIControl);
1114 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1115 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1116 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1117 dev->name, miireg, addr);
1119 } else if (value != MII_READ) {
1120 /* it was a write operation - fewer failures are detectable */
1121 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1122 dev->name, value, miireg, addr);
1124 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1125 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1126 dev->name, miireg, addr);
1129 retval = readl(base + NvRegMIIData);
1130 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1131 dev->name, miireg, addr, retval);
1137 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1139 struct fe_priv *np = netdev_priv(dev);
1141 unsigned int tries = 0;
1143 miicontrol = BMCR_RESET | bmcr_setup;
1144 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1148 /* wait for 500ms */
1151 /* must wait till reset is deasserted */
1152 while (miicontrol & BMCR_RESET) {
1154 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1155 /* FIXME: 100 tries seem excessive */
1162 static int phy_init(struct net_device *dev)
1164 struct fe_priv *np = get_nvpriv(dev);
1165 u8 __iomem *base = get_hwbase(dev);
1166 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1168 /* phy errata for E3016 phy */
1169 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1170 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1171 reg &= ~PHY_MARVELL_E3016_INITMASK;
1172 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1173 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1177 if (np->phy_oui == PHY_OUI_REALTEK) {
1178 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1179 np->phy_rev == PHY_REV_REALTEK_8211B) {
1180 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1181 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1184 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1185 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1188 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1189 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1192 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1193 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1196 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1197 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1200 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1201 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1204 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1205 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1210 np->phy_rev == PHY_REV_REALTEK_8211C) {
1211 u32 powerstate = readl(base + NvRegPowerState2);
1213 /* need to perform hw phy reset */
1214 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1215 writel(powerstate, base + NvRegPowerState2);
1218 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1219 writel(powerstate, base + NvRegPowerState2);
1222 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1223 reg |= PHY_REALTEK_INIT9;
1224 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1225 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1228 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1229 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1232 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1233 if (!(reg & PHY_REALTEK_INIT11)) {
1234 reg |= PHY_REALTEK_INIT11;
1235 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1236 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1240 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1241 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1245 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1246 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1247 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1248 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1249 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1250 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1251 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1252 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1253 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1254 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1255 phy_reserved |= PHY_REALTEK_INIT7;
1256 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1257 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1264 /* set advertise register */
1265 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1266 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1267 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1268 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1272 /* get phy interface type */
1273 phyinterface = readl(base + NvRegPhyInterface);
1275 /* see if gigabit phy */
1276 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1277 if (mii_status & PHY_GIGABIT) {
1278 np->gigabit = PHY_GIGABIT;
1279 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1280 mii_control_1000 &= ~ADVERTISE_1000HALF;
1281 if (phyinterface & PHY_RGMII)
1282 mii_control_1000 |= ADVERTISE_1000FULL;
1284 mii_control_1000 &= ~ADVERTISE_1000FULL;
1286 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1287 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1294 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1295 mii_control |= BMCR_ANENABLE;
1297 if (np->phy_oui == PHY_OUI_REALTEK &&
1298 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1299 np->phy_rev == PHY_REV_REALTEK_8211C) {
1300 /* start autoneg since we already performed hw reset above */
1301 mii_control |= BMCR_ANRESTART;
1302 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1303 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1308 * (certain phys need bmcr to be setup with reset)
1310 if (phy_reset(dev, mii_control)) {
1311 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1316 /* phy vendor specific configuration */
1317 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1318 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1319 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1320 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1321 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1322 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1325 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1326 phy_reserved |= PHY_CICADA_INIT5;
1327 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1328 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332 if (np->phy_oui == PHY_OUI_CICADA) {
1333 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1334 phy_reserved |= PHY_CICADA_INIT6;
1335 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1336 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1340 if (np->phy_oui == PHY_OUI_VITESSE) {
1341 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1342 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1345 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1346 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1349 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1350 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1351 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1354 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1355 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1356 phy_reserved |= PHY_VITESSE_INIT3;
1357 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1358 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1361 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1362 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1366 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1370 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1371 phy_reserved |= PHY_VITESSE_INIT3;
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1373 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1376 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1377 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1378 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1381 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1382 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1385 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1386 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1389 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1390 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1391 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1394 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1395 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1396 phy_reserved |= PHY_VITESSE_INIT8;
1397 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1398 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1401 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1402 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1405 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1406 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1410 if (np->phy_oui == PHY_OUI_REALTEK) {
1411 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1412 np->phy_rev == PHY_REV_REALTEK_8211B) {
1413 /* reset could have cleared these out, set them back */
1414 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1415 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1418 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1419 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1422 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1423 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1426 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1427 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1430 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1431 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1434 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1435 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1438 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1439 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1443 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1444 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1445 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1446 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1447 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1448 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1449 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1450 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1451 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1452 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1453 phy_reserved |= PHY_REALTEK_INIT7;
1454 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1455 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1459 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1460 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1461 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1464 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1465 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1466 phy_reserved |= PHY_REALTEK_INIT3;
1467 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1468 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1471 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1472 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1479 /* some phys clear out pause advertisment on reset, set it back */
1480 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1482 /* restart auto negotiation, power down phy */
1483 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1484 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN);
1485 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1492 static void nv_start_rx(struct net_device *dev)
1494 struct fe_priv *np = netdev_priv(dev);
1495 u8 __iomem *base = get_hwbase(dev);
1496 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1498 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1499 /* Already running? Stop it. */
1500 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1501 rx_ctrl &= ~NVREG_RCVCTL_START;
1502 writel(rx_ctrl, base + NvRegReceiverControl);
1505 writel(np->linkspeed, base + NvRegLinkSpeed);
1507 rx_ctrl |= NVREG_RCVCTL_START;
1509 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1510 writel(rx_ctrl, base + NvRegReceiverControl);
1511 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1512 dev->name, np->duplex, np->linkspeed);
1516 static void nv_stop_rx(struct net_device *dev)
1518 struct fe_priv *np = netdev_priv(dev);
1519 u8 __iomem *base = get_hwbase(dev);
1520 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1522 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1523 if (!np->mac_in_use)
1524 rx_ctrl &= ~NVREG_RCVCTL_START;
1526 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1527 writel(rx_ctrl, base + NvRegReceiverControl);
1528 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1529 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1530 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1532 udelay(NV_RXSTOP_DELAY2);
1533 if (!np->mac_in_use)
1534 writel(0, base + NvRegLinkSpeed);
1537 static void nv_start_tx(struct net_device *dev)
1539 struct fe_priv *np = netdev_priv(dev);
1540 u8 __iomem *base = get_hwbase(dev);
1541 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1543 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1544 tx_ctrl |= NVREG_XMITCTL_START;
1546 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1547 writel(tx_ctrl, base + NvRegTransmitterControl);
1551 static void nv_stop_tx(struct net_device *dev)
1553 struct fe_priv *np = netdev_priv(dev);
1554 u8 __iomem *base = get_hwbase(dev);
1555 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1557 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1558 if (!np->mac_in_use)
1559 tx_ctrl &= ~NVREG_XMITCTL_START;
1561 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1562 writel(tx_ctrl, base + NvRegTransmitterControl);
1563 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1564 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1565 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1567 udelay(NV_TXSTOP_DELAY2);
1568 if (!np->mac_in_use)
1569 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1570 base + NvRegTransmitPoll);
1573 static void nv_start_rxtx(struct net_device *dev)
1579 static void nv_stop_rxtx(struct net_device *dev)
1585 static void nv_txrx_reset(struct net_device *dev)
1587 struct fe_priv *np = netdev_priv(dev);
1588 u8 __iomem *base = get_hwbase(dev);
1590 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1591 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1593 udelay(NV_TXRX_RESET_DELAY);
1594 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1598 static void nv_mac_reset(struct net_device *dev)
1600 struct fe_priv *np = netdev_priv(dev);
1601 u8 __iomem *base = get_hwbase(dev);
1602 u32 temp1, temp2, temp3;
1604 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1606 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1609 /* save registers since they will be cleared on reset */
1610 temp1 = readl(base + NvRegMacAddrA);
1611 temp2 = readl(base + NvRegMacAddrB);
1612 temp3 = readl(base + NvRegTransmitPoll);
1614 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1616 udelay(NV_MAC_RESET_DELAY);
1617 writel(0, base + NvRegMacReset);
1619 udelay(NV_MAC_RESET_DELAY);
1621 /* restore saved registers */
1622 writel(temp1, base + NvRegMacAddrA);
1623 writel(temp2, base + NvRegMacAddrB);
1624 writel(temp3, base + NvRegTransmitPoll);
1626 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 static void nv_get_hw_stats(struct net_device *dev)
1632 struct fe_priv *np = netdev_priv(dev);
1633 u8 __iomem *base = get_hwbase(dev);
1635 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1636 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1637 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1638 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1639 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1640 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1641 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1642 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1643 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1644 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1645 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1646 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1647 np->estats.rx_runt += readl(base + NvRegRxRunt);
1648 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1649 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1650 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1651 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1652 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1653 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1654 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1655 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1656 np->estats.rx_packets =
1657 np->estats.rx_unicast +
1658 np->estats.rx_multicast +
1659 np->estats.rx_broadcast;
1660 np->estats.rx_errors_total =
1661 np->estats.rx_crc_errors +
1662 np->estats.rx_over_errors +
1663 np->estats.rx_frame_error +
1664 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1665 np->estats.rx_late_collision +
1666 np->estats.rx_runt +
1667 np->estats.rx_frame_too_long;
1668 np->estats.tx_errors_total =
1669 np->estats.tx_late_collision +
1670 np->estats.tx_fifo_errors +
1671 np->estats.tx_carrier_errors +
1672 np->estats.tx_excess_deferral +
1673 np->estats.tx_retry_error;
1675 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1676 np->estats.tx_deferral += readl(base + NvRegTxDef);
1677 np->estats.tx_packets += readl(base + NvRegTxFrame);
1678 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1679 np->estats.tx_pause += readl(base + NvRegTxPause);
1680 np->estats.rx_pause += readl(base + NvRegRxPause);
1681 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1684 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1685 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1686 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1687 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1692 * nv_get_stats: dev->get_stats function
1693 * Get latest stats value from the nic.
1694 * Called with read_lock(&dev_base_lock) held for read -
1695 * only synchronized against unregister_netdevice.
1697 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1699 struct fe_priv *np = netdev_priv(dev);
1701 /* If the nic supports hw counters then retrieve latest values */
1702 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1703 nv_get_hw_stats(dev);
1705 /* copy to net_device stats */
1706 dev->stats.tx_bytes = np->estats.tx_bytes;
1707 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1708 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1709 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1710 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1711 dev->stats.rx_errors = np->estats.rx_errors_total;
1712 dev->stats.tx_errors = np->estats.tx_errors_total;
1719 * nv_alloc_rx: fill rx ring entries.
1720 * Return 1 if the allocations for the skbs failed and the
1721 * rx engine is without Available descriptors
1723 static int nv_alloc_rx(struct net_device *dev)
1725 struct fe_priv *np = netdev_priv(dev);
1726 struct ring_desc* less_rx;
1728 less_rx = np->get_rx.orig;
1729 if (less_rx-- == np->first_rx.orig)
1730 less_rx = np->last_rx.orig;
1732 while (np->put_rx.orig != less_rx) {
1733 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1735 np->put_rx_ctx->skb = skb;
1736 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1739 PCI_DMA_FROMDEVICE);
1740 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1741 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1743 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1744 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1745 np->put_rx.orig = np->first_rx.orig;
1746 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1747 np->put_rx_ctx = np->first_rx_ctx;
1755 static int nv_alloc_rx_optimized(struct net_device *dev)
1757 struct fe_priv *np = netdev_priv(dev);
1758 struct ring_desc_ex* less_rx;
1760 less_rx = np->get_rx.ex;
1761 if (less_rx-- == np->first_rx.ex)
1762 less_rx = np->last_rx.ex;
1764 while (np->put_rx.ex != less_rx) {
1765 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1767 np->put_rx_ctx->skb = skb;
1768 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1771 PCI_DMA_FROMDEVICE);
1772 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1773 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1774 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1776 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1777 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1778 np->put_rx.ex = np->first_rx.ex;
1779 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1780 np->put_rx_ctx = np->first_rx_ctx;
1788 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1789 #ifdef CONFIG_FORCEDETH_NAPI
1790 static void nv_do_rx_refill(unsigned long data)
1792 struct net_device *dev = (struct net_device *) data;
1793 struct fe_priv *np = netdev_priv(dev);
1795 /* Just reschedule NAPI rx processing */
1796 napi_schedule(&np->napi);
1799 static void nv_do_rx_refill(unsigned long data)
1801 struct net_device *dev = (struct net_device *) data;
1802 struct fe_priv *np = netdev_priv(dev);
1805 if (!using_multi_irqs(dev)) {
1806 if (np->msi_flags & NV_MSI_X_ENABLED)
1807 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1809 disable_irq(np->pci_dev->irq);
1811 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1813 if (!nv_optimized(np))
1814 retcode = nv_alloc_rx(dev);
1816 retcode = nv_alloc_rx_optimized(dev);
1818 spin_lock_irq(&np->lock);
1819 if (!np->in_shutdown)
1820 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1821 spin_unlock_irq(&np->lock);
1823 if (!using_multi_irqs(dev)) {
1824 if (np->msi_flags & NV_MSI_X_ENABLED)
1825 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1827 enable_irq(np->pci_dev->irq);
1829 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1834 static void nv_init_rx(struct net_device *dev)
1836 struct fe_priv *np = netdev_priv(dev);
1839 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1841 if (!nv_optimized(np))
1842 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1844 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1845 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1846 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1848 for (i = 0; i < np->rx_ring_size; i++) {
1849 if (!nv_optimized(np)) {
1850 np->rx_ring.orig[i].flaglen = 0;
1851 np->rx_ring.orig[i].buf = 0;
1853 np->rx_ring.ex[i].flaglen = 0;
1854 np->rx_ring.ex[i].txvlan = 0;
1855 np->rx_ring.ex[i].bufhigh = 0;
1856 np->rx_ring.ex[i].buflow = 0;
1858 np->rx_skb[i].skb = NULL;
1859 np->rx_skb[i].dma = 0;
1863 static void nv_init_tx(struct net_device *dev)
1865 struct fe_priv *np = netdev_priv(dev);
1868 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1870 if (!nv_optimized(np))
1871 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1873 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1874 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1875 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1876 np->tx_pkts_in_progress = 0;
1877 np->tx_change_owner = NULL;
1878 np->tx_end_flip = NULL;
1880 for (i = 0; i < np->tx_ring_size; i++) {
1881 if (!nv_optimized(np)) {
1882 np->tx_ring.orig[i].flaglen = 0;
1883 np->tx_ring.orig[i].buf = 0;
1885 np->tx_ring.ex[i].flaglen = 0;
1886 np->tx_ring.ex[i].txvlan = 0;
1887 np->tx_ring.ex[i].bufhigh = 0;
1888 np->tx_ring.ex[i].buflow = 0;
1890 np->tx_skb[i].skb = NULL;
1891 np->tx_skb[i].dma = 0;
1892 np->tx_skb[i].dma_len = 0;
1893 np->tx_skb[i].first_tx_desc = NULL;
1894 np->tx_skb[i].next_tx_ctx = NULL;
1898 static int nv_init_ring(struct net_device *dev)
1900 struct fe_priv *np = netdev_priv(dev);
1905 if (!nv_optimized(np))
1906 return nv_alloc_rx(dev);
1908 return nv_alloc_rx_optimized(dev);
1911 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1913 struct fe_priv *np = netdev_priv(dev);
1916 pci_unmap_page(np->pci_dev, tx_skb->dma,
1922 dev_kfree_skb_any(tx_skb->skb);
1930 static void nv_drain_tx(struct net_device *dev)
1932 struct fe_priv *np = netdev_priv(dev);
1935 for (i = 0; i < np->tx_ring_size; i++) {
1936 if (!nv_optimized(np)) {
1937 np->tx_ring.orig[i].flaglen = 0;
1938 np->tx_ring.orig[i].buf = 0;
1940 np->tx_ring.ex[i].flaglen = 0;
1941 np->tx_ring.ex[i].txvlan = 0;
1942 np->tx_ring.ex[i].bufhigh = 0;
1943 np->tx_ring.ex[i].buflow = 0;
1945 if (nv_release_txskb(dev, &np->tx_skb[i]))
1946 dev->stats.tx_dropped++;
1947 np->tx_skb[i].dma = 0;
1948 np->tx_skb[i].dma_len = 0;
1949 np->tx_skb[i].first_tx_desc = NULL;
1950 np->tx_skb[i].next_tx_ctx = NULL;
1952 np->tx_pkts_in_progress = 0;
1953 np->tx_change_owner = NULL;
1954 np->tx_end_flip = NULL;
1957 static void nv_drain_rx(struct net_device *dev)
1959 struct fe_priv *np = netdev_priv(dev);
1962 for (i = 0; i < np->rx_ring_size; i++) {
1963 if (!nv_optimized(np)) {
1964 np->rx_ring.orig[i].flaglen = 0;
1965 np->rx_ring.orig[i].buf = 0;
1967 np->rx_ring.ex[i].flaglen = 0;
1968 np->rx_ring.ex[i].txvlan = 0;
1969 np->rx_ring.ex[i].bufhigh = 0;
1970 np->rx_ring.ex[i].buflow = 0;
1973 if (np->rx_skb[i].skb) {
1974 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1975 (skb_end_pointer(np->rx_skb[i].skb) -
1976 np->rx_skb[i].skb->data),
1977 PCI_DMA_FROMDEVICE);
1978 dev_kfree_skb(np->rx_skb[i].skb);
1979 np->rx_skb[i].skb = NULL;
1984 static void nv_drain_rxtx(struct net_device *dev)
1990 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1992 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1995 static void nv_legacybackoff_reseed(struct net_device *dev)
1997 u8 __iomem *base = get_hwbase(dev);
2002 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2003 get_random_bytes(&low, sizeof(low));
2004 reg |= low & NVREG_SLOTTIME_MASK;
2006 /* Need to stop tx before change takes effect.
2007 * Caller has already gained np->lock.
2009 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2013 writel(reg, base + NvRegSlotTime);
2019 /* Gear Backoff Seeds */
2020 #define BACKOFF_SEEDSET_ROWS 8
2021 #define BACKOFF_SEEDSET_LFSRS 15
2023 /* Known Good seed sets */
2024 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2025 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2026 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2027 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2028 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2029 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2030 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2031 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2032 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2034 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2035 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2036 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2037 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2038 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2039 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2040 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2041 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2042 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2044 static void nv_gear_backoff_reseed(struct net_device *dev)
2046 u8 __iomem *base = get_hwbase(dev);
2047 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2048 u32 temp, seedset, combinedSeed;
2051 /* Setup seed for free running LFSR */
2052 /* We are going to read the time stamp counter 3 times
2053 and swizzle bits around to increase randomness */
2054 get_random_bytes(&miniseed1, sizeof(miniseed1));
2055 miniseed1 &= 0x0fff;
2059 get_random_bytes(&miniseed2, sizeof(miniseed2));
2060 miniseed2 &= 0x0fff;
2063 miniseed2_reversed =
2064 ((miniseed2 & 0xF00) >> 8) |
2065 (miniseed2 & 0x0F0) |
2066 ((miniseed2 & 0x00F) << 8);
2068 get_random_bytes(&miniseed3, sizeof(miniseed3));
2069 miniseed3 &= 0x0fff;
2072 miniseed3_reversed =
2073 ((miniseed3 & 0xF00) >> 8) |
2074 (miniseed3 & 0x0F0) |
2075 ((miniseed3 & 0x00F) << 8);
2077 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2078 (miniseed2 ^ miniseed3_reversed);
2080 /* Seeds can not be zero */
2081 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2082 combinedSeed |= 0x08;
2083 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2084 combinedSeed |= 0x8000;
2086 /* No need to disable tx here */
2087 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2088 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2089 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2090 writel(temp,base + NvRegBackOffControl);
2092 /* Setup seeds for all gear LFSRs. */
2093 get_random_bytes(&seedset, sizeof(seedset));
2094 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2095 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2097 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2098 temp |= main_seedset[seedset][i-1] & 0x3ff;
2099 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2100 writel(temp, base + NvRegBackOffControl);
2105 * nv_start_xmit: dev->hard_start_xmit function
2106 * Called with netif_tx_lock held.
2108 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2110 struct fe_priv *np = netdev_priv(dev);
2112 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2113 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2117 u32 size = skb->len-skb->data_len;
2118 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2120 struct ring_desc* put_tx;
2121 struct ring_desc* start_tx;
2122 struct ring_desc* prev_tx;
2123 struct nv_skb_map* prev_tx_ctx;
2124 unsigned long flags;
2126 /* add fragments to entries count */
2127 for (i = 0; i < fragments; i++) {
2128 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2129 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2132 spin_lock_irqsave(&np->lock, flags);
2133 empty_slots = nv_get_empty_tx_slots(np);
2134 if (unlikely(empty_slots <= entries)) {
2135 netif_stop_queue(dev);
2137 spin_unlock_irqrestore(&np->lock, flags);
2138 return NETDEV_TX_BUSY;
2140 spin_unlock_irqrestore(&np->lock, flags);
2142 start_tx = put_tx = np->put_tx.orig;
2144 /* setup the header buffer */
2147 prev_tx_ctx = np->put_tx_ctx;
2148 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2149 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2151 np->put_tx_ctx->dma_len = bcnt;
2152 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2153 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2155 tx_flags = np->tx_flags;
2158 if (unlikely(put_tx++ == np->last_tx.orig))
2159 put_tx = np->first_tx.orig;
2160 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2161 np->put_tx_ctx = np->first_tx_ctx;
2164 /* setup the fragments */
2165 for (i = 0; i < fragments; i++) {
2166 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2167 u32 size = frag->size;
2172 prev_tx_ctx = np->put_tx_ctx;
2173 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2174 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2176 np->put_tx_ctx->dma_len = bcnt;
2177 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2178 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2182 if (unlikely(put_tx++ == np->last_tx.orig))
2183 put_tx = np->first_tx.orig;
2184 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2185 np->put_tx_ctx = np->first_tx_ctx;
2189 /* set last fragment flag */
2190 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2192 /* save skb in this slot's context area */
2193 prev_tx_ctx->skb = skb;
2195 if (skb_is_gso(skb))
2196 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2198 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2199 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2201 spin_lock_irqsave(&np->lock, flags);
2204 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2205 np->put_tx.orig = put_tx;
2207 spin_unlock_irqrestore(&np->lock, flags);
2209 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2210 dev->name, entries, tx_flags_extra);
2213 for (j=0; j<64; j++) {
2215 dprintk("\n%03x:", j);
2216 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2221 dev->trans_start = jiffies;
2222 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2223 return NETDEV_TX_OK;
2226 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2228 struct fe_priv *np = netdev_priv(dev);
2231 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2235 u32 size = skb->len-skb->data_len;
2236 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2238 struct ring_desc_ex* put_tx;
2239 struct ring_desc_ex* start_tx;
2240 struct ring_desc_ex* prev_tx;
2241 struct nv_skb_map* prev_tx_ctx;
2242 struct nv_skb_map* start_tx_ctx;
2243 unsigned long flags;
2245 /* add fragments to entries count */
2246 for (i = 0; i < fragments; i++) {
2247 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2248 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2251 spin_lock_irqsave(&np->lock, flags);
2252 empty_slots = nv_get_empty_tx_slots(np);
2253 if (unlikely(empty_slots <= entries)) {
2254 netif_stop_queue(dev);
2256 spin_unlock_irqrestore(&np->lock, flags);
2257 return NETDEV_TX_BUSY;
2259 spin_unlock_irqrestore(&np->lock, flags);
2261 start_tx = put_tx = np->put_tx.ex;
2262 start_tx_ctx = np->put_tx_ctx;
2264 /* setup the header buffer */
2267 prev_tx_ctx = np->put_tx_ctx;
2268 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2269 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2271 np->put_tx_ctx->dma_len = bcnt;
2272 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2273 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2274 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2276 tx_flags = NV_TX2_VALID;
2279 if (unlikely(put_tx++ == np->last_tx.ex))
2280 put_tx = np->first_tx.ex;
2281 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2282 np->put_tx_ctx = np->first_tx_ctx;
2285 /* setup the fragments */
2286 for (i = 0; i < fragments; i++) {
2287 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2288 u32 size = frag->size;
2293 prev_tx_ctx = np->put_tx_ctx;
2294 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2295 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2297 np->put_tx_ctx->dma_len = bcnt;
2298 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2299 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2300 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2304 if (unlikely(put_tx++ == np->last_tx.ex))
2305 put_tx = np->first_tx.ex;
2306 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2307 np->put_tx_ctx = np->first_tx_ctx;
2311 /* set last fragment flag */
2312 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2314 /* save skb in this slot's context area */
2315 prev_tx_ctx->skb = skb;
2317 if (skb_is_gso(skb))
2318 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2320 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2321 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2324 if (likely(!np->vlangrp)) {
2325 start_tx->txvlan = 0;
2327 if (vlan_tx_tag_present(skb))
2328 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2330 start_tx->txvlan = 0;
2333 spin_lock_irqsave(&np->lock, flags);
2336 /* Limit the number of outstanding tx. Setup all fragments, but
2337 * do not set the VALID bit on the first descriptor. Save a pointer
2338 * to that descriptor and also for next skb_map element.
2341 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2342 if (!np->tx_change_owner)
2343 np->tx_change_owner = start_tx_ctx;
2345 /* remove VALID bit */
2346 tx_flags &= ~NV_TX2_VALID;
2347 start_tx_ctx->first_tx_desc = start_tx;
2348 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2349 np->tx_end_flip = np->put_tx_ctx;
2351 np->tx_pkts_in_progress++;
2356 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2357 np->put_tx.ex = put_tx;
2359 spin_unlock_irqrestore(&np->lock, flags);
2361 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2362 dev->name, entries, tx_flags_extra);
2365 for (j=0; j<64; j++) {
2367 dprintk("\n%03x:", j);
2368 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2373 dev->trans_start = jiffies;
2374 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2375 return NETDEV_TX_OK;
2378 static inline void nv_tx_flip_ownership(struct net_device *dev)
2380 struct fe_priv *np = netdev_priv(dev);
2382 np->tx_pkts_in_progress--;
2383 if (np->tx_change_owner) {
2384 np->tx_change_owner->first_tx_desc->flaglen |=
2385 cpu_to_le32(NV_TX2_VALID);
2386 np->tx_pkts_in_progress++;
2388 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2389 if (np->tx_change_owner == np->tx_end_flip)
2390 np->tx_change_owner = NULL;
2392 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2397 * nv_tx_done: check for completed packets, release the skbs.
2399 * Caller must own np->lock.
2401 static int nv_tx_done(struct net_device *dev, int limit)
2403 struct fe_priv *np = netdev_priv(dev);
2406 struct ring_desc* orig_get_tx = np->get_tx.orig;
2408 while ((np->get_tx.orig != np->put_tx.orig) &&
2409 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2410 (tx_work < limit)) {
2412 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2415 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2416 np->get_tx_ctx->dma_len,
2418 np->get_tx_ctx->dma = 0;
2420 if (np->desc_ver == DESC_VER_1) {
2421 if (flags & NV_TX_LASTPACKET) {
2422 if (flags & NV_TX_ERROR) {
2423 if (flags & NV_TX_UNDERFLOW)
2424 dev->stats.tx_fifo_errors++;
2425 if (flags & NV_TX_CARRIERLOST)
2426 dev->stats.tx_carrier_errors++;
2427 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2428 nv_legacybackoff_reseed(dev);
2429 dev->stats.tx_errors++;
2431 dev->stats.tx_packets++;
2432 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2434 dev_kfree_skb_any(np->get_tx_ctx->skb);
2435 np->get_tx_ctx->skb = NULL;
2439 if (flags & NV_TX2_LASTPACKET) {
2440 if (flags & NV_TX2_ERROR) {
2441 if (flags & NV_TX2_UNDERFLOW)
2442 dev->stats.tx_fifo_errors++;
2443 if (flags & NV_TX2_CARRIERLOST)
2444 dev->stats.tx_carrier_errors++;
2445 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2446 nv_legacybackoff_reseed(dev);
2447 dev->stats.tx_errors++;
2449 dev->stats.tx_packets++;
2450 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2452 dev_kfree_skb_any(np->get_tx_ctx->skb);
2453 np->get_tx_ctx->skb = NULL;
2457 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2458 np->get_tx.orig = np->first_tx.orig;
2459 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2460 np->get_tx_ctx = np->first_tx_ctx;
2462 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2464 netif_wake_queue(dev);
2469 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2471 struct fe_priv *np = netdev_priv(dev);
2474 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2476 while ((np->get_tx.ex != np->put_tx.ex) &&
2477 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2478 (tx_work < limit)) {
2480 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2483 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2484 np->get_tx_ctx->dma_len,
2486 np->get_tx_ctx->dma = 0;
2488 if (flags & NV_TX2_LASTPACKET) {
2489 if (!(flags & NV_TX2_ERROR))
2490 dev->stats.tx_packets++;
2492 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2493 if (np->driver_data & DEV_HAS_GEAR_MODE)
2494 nv_gear_backoff_reseed(dev);
2496 nv_legacybackoff_reseed(dev);
2500 dev_kfree_skb_any(np->get_tx_ctx->skb);
2501 np->get_tx_ctx->skb = NULL;
2505 nv_tx_flip_ownership(dev);
2508 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2509 np->get_tx.ex = np->first_tx.ex;
2510 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2511 np->get_tx_ctx = np->first_tx_ctx;
2513 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2515 netif_wake_queue(dev);
2521 * nv_tx_timeout: dev->tx_timeout function
2522 * Called with netif_tx_lock held.
2524 static void nv_tx_timeout(struct net_device *dev)
2526 struct fe_priv *np = netdev_priv(dev);
2527 u8 __iomem *base = get_hwbase(dev);
2530 if (np->msi_flags & NV_MSI_X_ENABLED)
2531 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2533 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2535 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2540 printk(KERN_INFO "%s: Ring at %lx\n",
2541 dev->name, (unsigned long)np->ring_addr);
2542 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2543 for (i=0;i<=np->register_size;i+= 32) {
2544 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2546 readl(base + i + 0), readl(base + i + 4),
2547 readl(base + i + 8), readl(base + i + 12),
2548 readl(base + i + 16), readl(base + i + 20),
2549 readl(base + i + 24), readl(base + i + 28));
2551 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2552 for (i=0;i<np->tx_ring_size;i+= 4) {
2553 if (!nv_optimized(np)) {
2554 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2556 le32_to_cpu(np->tx_ring.orig[i].buf),
2557 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2558 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2559 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2560 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2561 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2562 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2563 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2565 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2567 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2568 le32_to_cpu(np->tx_ring.ex[i].buflow),
2569 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2570 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2571 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2572 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2573 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2574 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2575 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2576 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2577 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2578 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2583 spin_lock_irq(&np->lock);
2585 /* 1) stop tx engine */
2588 /* 2) check that the packets were not sent already: */
2589 if (!nv_optimized(np))
2590 nv_tx_done(dev, np->tx_ring_size);
2592 nv_tx_done_optimized(dev, np->tx_ring_size);
2594 /* 3) if there are dead entries: clear everything */
2595 if (np->get_tx_ctx != np->put_tx_ctx) {
2596 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2599 setup_hw_rings(dev, NV_SETUP_TX_RING);
2602 netif_wake_queue(dev);
2604 /* 4) restart tx engine */
2606 spin_unlock_irq(&np->lock);
2610 * Called when the nic notices a mismatch between the actual data len on the
2611 * wire and the len indicated in the 802 header
2613 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2615 int hdrlen; /* length of the 802 header */
2616 int protolen; /* length as stored in the proto field */
2618 /* 1) calculate len according to header */
2619 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2620 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2623 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2626 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2627 dev->name, datalen, protolen, hdrlen);
2628 if (protolen > ETH_DATA_LEN)
2629 return datalen; /* Value in proto field not a len, no checks possible */
2632 /* consistency checks: */
2633 if (datalen > ETH_ZLEN) {
2634 if (datalen >= protolen) {
2635 /* more data on wire than in 802 header, trim of
2638 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2639 dev->name, protolen);
2642 /* less data on wire than mentioned in header.
2643 * Discard the packet.
2645 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2650 /* short packet. Accept only if 802 values are also short */
2651 if (protolen > ETH_ZLEN) {
2652 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2656 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2657 dev->name, datalen);
2662 static int nv_rx_process(struct net_device *dev, int limit)
2664 struct fe_priv *np = netdev_priv(dev);
2667 struct sk_buff *skb;
2670 while((np->get_rx.orig != np->put_rx.orig) &&
2671 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2672 (rx_work < limit)) {
2674 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2678 * the packet is for us - immediately tear down the pci mapping.
2679 * TODO: check if a prefetch of the first cacheline improves
2682 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2683 np->get_rx_ctx->dma_len,
2684 PCI_DMA_FROMDEVICE);
2685 skb = np->get_rx_ctx->skb;
2686 np->get_rx_ctx->skb = NULL;
2690 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2691 for (j=0; j<64; j++) {
2693 dprintk("\n%03x:", j);
2694 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2698 /* look at what we actually got: */
2699 if (np->desc_ver == DESC_VER_1) {
2700 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2701 len = flags & LEN_MASK_V1;
2702 if (unlikely(flags & NV_RX_ERROR)) {
2703 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2704 len = nv_getlen(dev, skb->data, len);
2706 dev->stats.rx_errors++;
2711 /* framing errors are soft errors */
2712 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2713 if (flags & NV_RX_SUBSTRACT1) {
2717 /* the rest are hard errors */
2719 if (flags & NV_RX_MISSEDFRAME)
2720 dev->stats.rx_missed_errors++;
2721 if (flags & NV_RX_CRCERR)
2722 dev->stats.rx_crc_errors++;
2723 if (flags & NV_RX_OVERFLOW)
2724 dev->stats.rx_over_errors++;
2725 dev->stats.rx_errors++;
2735 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2736 len = flags & LEN_MASK_V2;
2737 if (unlikely(flags & NV_RX2_ERROR)) {
2738 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2739 len = nv_getlen(dev, skb->data, len);
2741 dev->stats.rx_errors++;
2746 /* framing errors are soft errors */
2747 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2748 if (flags & NV_RX2_SUBSTRACT1) {
2752 /* the rest are hard errors */
2754 if (flags & NV_RX2_CRCERR)
2755 dev->stats.rx_crc_errors++;
2756 if (flags & NV_RX2_OVERFLOW)
2757 dev->stats.rx_over_errors++;
2758 dev->stats.rx_errors++;
2763 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2764 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2765 skb->ip_summed = CHECKSUM_UNNECESSARY;
2771 /* got a valid packet - forward it to the network core */
2773 skb->protocol = eth_type_trans(skb, dev);
2774 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2775 dev->name, len, skb->protocol);
2776 #ifdef CONFIG_FORCEDETH_NAPI
2777 netif_receive_skb(skb);
2781 dev->stats.rx_packets++;
2782 dev->stats.rx_bytes += len;
2784 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2785 np->get_rx.orig = np->first_rx.orig;
2786 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2787 np->get_rx_ctx = np->first_rx_ctx;
2795 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2797 struct fe_priv *np = netdev_priv(dev);
2801 struct sk_buff *skb;
2804 while((np->get_rx.ex != np->put_rx.ex) &&
2805 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2806 (rx_work < limit)) {
2808 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2812 * the packet is for us - immediately tear down the pci mapping.
2813 * TODO: check if a prefetch of the first cacheline improves
2816 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2817 np->get_rx_ctx->dma_len,
2818 PCI_DMA_FROMDEVICE);
2819 skb = np->get_rx_ctx->skb;
2820 np->get_rx_ctx->skb = NULL;
2824 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2825 for (j=0; j<64; j++) {
2827 dprintk("\n%03x:", j);
2828 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2832 /* look at what we actually got: */
2833 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2834 len = flags & LEN_MASK_V2;
2835 if (unlikely(flags & NV_RX2_ERROR)) {
2836 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2837 len = nv_getlen(dev, skb->data, len);
2843 /* framing errors are soft errors */
2844 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2845 if (flags & NV_RX2_SUBSTRACT1) {
2849 /* the rest are hard errors */
2856 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2857 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2858 skb->ip_summed = CHECKSUM_UNNECESSARY;
2860 /* got a valid packet - forward it to the network core */
2862 skb->protocol = eth_type_trans(skb, dev);
2863 prefetch(skb->data);
2865 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2866 dev->name, len, skb->protocol);
2868 if (likely(!np->vlangrp)) {
2869 #ifdef CONFIG_FORCEDETH_NAPI
2870 netif_receive_skb(skb);
2875 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2876 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2877 #ifdef CONFIG_FORCEDETH_NAPI
2878 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2879 vlanflags & NV_RX3_VLAN_TAG_MASK);
2881 vlan_hwaccel_rx(skb, np->vlangrp,
2882 vlanflags & NV_RX3_VLAN_TAG_MASK);
2885 #ifdef CONFIG_FORCEDETH_NAPI
2886 netif_receive_skb(skb);
2893 dev->stats.rx_packets++;
2894 dev->stats.rx_bytes += len;
2899 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2900 np->get_rx.ex = np->first_rx.ex;
2901 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2902 np->get_rx_ctx = np->first_rx_ctx;
2910 static void set_bufsize(struct net_device *dev)
2912 struct fe_priv *np = netdev_priv(dev);
2914 if (dev->mtu <= ETH_DATA_LEN)
2915 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2917 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2921 * nv_change_mtu: dev->change_mtu function
2922 * Called with dev_base_lock held for read.
2924 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2926 struct fe_priv *np = netdev_priv(dev);
2929 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2935 /* return early if the buffer sizes will not change */
2936 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2938 if (old_mtu == new_mtu)
2941 /* synchronized against open : rtnl_lock() held by caller */
2942 if (netif_running(dev)) {
2943 u8 __iomem *base = get_hwbase(dev);
2945 * It seems that the nic preloads valid ring entries into an
2946 * internal buffer. The procedure for flushing everything is
2947 * guessed, there is probably a simpler approach.
2948 * Changing the MTU is a rare event, it shouldn't matter.
2950 nv_disable_irq(dev);
2951 nv_napi_disable(dev);
2952 netif_tx_lock_bh(dev);
2953 netif_addr_lock(dev);
2954 spin_lock(&np->lock);
2958 /* drain rx queue */
2960 /* reinit driver view of the rx queue */
2962 if (nv_init_ring(dev)) {
2963 if (!np->in_shutdown)
2964 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2966 /* reinit nic view of the rx queue */
2967 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2968 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2969 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2970 base + NvRegRingSizes);
2972 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2975 /* restart rx engine */
2977 spin_unlock(&np->lock);
2978 netif_addr_unlock(dev);
2979 netif_tx_unlock_bh(dev);
2980 nv_napi_enable(dev);
2986 static void nv_copy_mac_to_hw(struct net_device *dev)
2988 u8 __iomem *base = get_hwbase(dev);
2991 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2992 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2993 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2995 writel(mac[0], base + NvRegMacAddrA);
2996 writel(mac[1], base + NvRegMacAddrB);
3000 * nv_set_mac_address: dev->set_mac_address function
3001 * Called with rtnl_lock() held.
3003 static int nv_set_mac_address(struct net_device *dev, void *addr)
3005 struct fe_priv *np = netdev_priv(dev);
3006 struct sockaddr *macaddr = (struct sockaddr*)addr;
3008 if (!is_valid_ether_addr(macaddr->sa_data))
3009 return -EADDRNOTAVAIL;
3011 /* synchronized against open : rtnl_lock() held by caller */
3012 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3014 if (netif_running(dev)) {
3015 netif_tx_lock_bh(dev);
3016 netif_addr_lock(dev);
3017 spin_lock_irq(&np->lock);
3019 /* stop rx engine */
3022 /* set mac address */
3023 nv_copy_mac_to_hw(dev);
3025 /* restart rx engine */
3027 spin_unlock_irq(&np->lock);
3028 netif_addr_unlock(dev);
3029 netif_tx_unlock_bh(dev);
3031 nv_copy_mac_to_hw(dev);
3037 * nv_set_multicast: dev->set_multicast function
3038 * Called with netif_tx_lock held.
3040 static void nv_set_multicast(struct net_device *dev)
3042 struct fe_priv *np = netdev_priv(dev);
3043 u8 __iomem *base = get_hwbase(dev);
3046 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3048 memset(addr, 0, sizeof(addr));
3049 memset(mask, 0, sizeof(mask));
3051 if (dev->flags & IFF_PROMISC) {
3052 pff |= NVREG_PFF_PROMISC;
3054 pff |= NVREG_PFF_MYADDR;
3056 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3060 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3061 if (dev->flags & IFF_ALLMULTI) {
3062 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3064 struct dev_mc_list *walk;
3066 walk = dev->mc_list;
3067 while (walk != NULL) {
3069 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3070 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3078 addr[0] = alwaysOn[0];
3079 addr[1] = alwaysOn[1];
3080 mask[0] = alwaysOn[0] | alwaysOff[0];
3081 mask[1] = alwaysOn[1] | alwaysOff[1];
3083 mask[0] = NVREG_MCASTMASKA_NONE;
3084 mask[1] = NVREG_MCASTMASKB_NONE;
3087 addr[0] |= NVREG_MCASTADDRA_FORCE;
3088 pff |= NVREG_PFF_ALWAYS;
3089 spin_lock_irq(&np->lock);
3091 writel(addr[0], base + NvRegMulticastAddrA);
3092 writel(addr[1], base + NvRegMulticastAddrB);
3093 writel(mask[0], base + NvRegMulticastMaskA);
3094 writel(mask[1], base + NvRegMulticastMaskB);
3095 writel(pff, base + NvRegPacketFilterFlags);
3096 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3099 spin_unlock_irq(&np->lock);
3102 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3104 struct fe_priv *np = netdev_priv(dev);
3105 u8 __iomem *base = get_hwbase(dev);
3107 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3109 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3110 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3111 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3112 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3113 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3115 writel(pff, base + NvRegPacketFilterFlags);
3118 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3119 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3120 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3121 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3122 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3123 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3124 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3125 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3126 /* limit the number of tx pause frames to a default of 8 */
3127 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3129 writel(pause_enable, base + NvRegTxPauseFrame);
3130 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3131 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3133 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3134 writel(regmisc, base + NvRegMisc1);
3140 * nv_update_linkspeed: Setup the MAC according to the link partner
3141 * @dev: Network device to be configured
3143 * The function queries the PHY and checks if there is a link partner.
3144 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3145 * set to 10 MBit HD.
3147 * The function returns 0 if there is no link partner and 1 if there is
3148 * a good link partner.
3150 static int nv_update_linkspeed(struct net_device *dev)
3152 struct fe_priv *np = netdev_priv(dev);
3153 u8 __iomem *base = get_hwbase(dev);
3156 int adv_lpa, adv_pause, lpa_pause;
3157 int newls = np->linkspeed;
3158 int newdup = np->duplex;
3161 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3165 /* BMSR_LSTATUS is latched, read it twice:
3166 * we want the current value.
3168 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3169 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3171 if (!(mii_status & BMSR_LSTATUS)) {
3172 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3174 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3180 if (np->autoneg == 0) {
3181 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3182 dev->name, np->fixed_mode);
3183 if (np->fixed_mode & LPA_100FULL) {
3184 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3186 } else if (np->fixed_mode & LPA_100HALF) {
3187 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3189 } else if (np->fixed_mode & LPA_10FULL) {
3190 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3193 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3199 /* check auto negotiation is complete */
3200 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3201 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3202 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3205 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3209 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3210 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3211 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3212 dev->name, adv, lpa);
3215 if (np->gigabit == PHY_GIGABIT) {
3216 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3217 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3219 if ((control_1000 & ADVERTISE_1000FULL) &&
3220 (status_1000 & LPA_1000FULL)) {
3221 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3223 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3229 /* FIXME: handle parallel detection properly */
3230 adv_lpa = lpa & adv;
3231 if (adv_lpa & LPA_100FULL) {
3232 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3234 } else if (adv_lpa & LPA_100HALF) {
3235 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3237 } else if (adv_lpa & LPA_10FULL) {
3238 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3240 } else if (adv_lpa & LPA_10HALF) {
3241 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3244 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3245 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3250 if (np->duplex == newdup && np->linkspeed == newls)
3253 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3254 dev->name, np->linkspeed, np->duplex, newls, newdup);
3256 np->duplex = newdup;
3257 np->linkspeed = newls;
3259 /* The transmitter and receiver must be restarted for safe update */
3260 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3261 txrxFlags |= NV_RESTART_TX;
3264 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3265 txrxFlags |= NV_RESTART_RX;
3269 if (np->gigabit == PHY_GIGABIT) {
3270 phyreg = readl(base + NvRegSlotTime);
3271 phyreg &= ~(0x3FF00);
3272 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3273 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3274 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3275 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3276 phyreg |= NVREG_SLOTTIME_1000_FULL;
3277 writel(phyreg, base + NvRegSlotTime);
3280 phyreg = readl(base + NvRegPhyInterface);
3281 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3282 if (np->duplex == 0)
3284 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3286 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3288 writel(phyreg, base + NvRegPhyInterface);
3290 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3291 if (phyreg & PHY_RGMII) {
3292 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3293 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3295 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3296 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3297 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3299 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3301 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3305 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3306 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3308 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3310 writel(txreg, base + NvRegTxDeferral);
3312 if (np->desc_ver == DESC_VER_1) {
3313 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3315 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3316 txreg = NVREG_TX_WM_DESC2_3_1000;
3318 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3320 writel(txreg, base + NvRegTxWatermark);
3322 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3325 writel(np->linkspeed, base + NvRegLinkSpeed);
3329 /* setup pause frame */
3330 if (np->duplex != 0) {
3331 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3332 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3333 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3335 switch (adv_pause) {
3336 case ADVERTISE_PAUSE_CAP:
3337 if (lpa_pause & LPA_PAUSE_CAP) {
3338 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3339 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3340 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3343 case ADVERTISE_PAUSE_ASYM:
3344 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3346 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3349 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3350 if (lpa_pause & LPA_PAUSE_CAP)
3352 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3353 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3354 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3356 if (lpa_pause == LPA_PAUSE_ASYM)
3358 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3363 pause_flags = np->pause_flags;
3366 nv_update_pause(dev, pause_flags);
3368 if (txrxFlags & NV_RESTART_TX)
3370 if (txrxFlags & NV_RESTART_RX)
3376 static void nv_linkchange(struct net_device *dev)
3378 if (nv_update_linkspeed(dev)) {
3379 if (!netif_carrier_ok(dev)) {
3380 netif_carrier_on(dev);
3381 printk(KERN_INFO "%s: link up.\n", dev->name);
3385 if (netif_carrier_ok(dev)) {
3386 netif_carrier_off(dev);
3387 printk(KERN_INFO "%s: link down.\n", dev->name);
3393 static void nv_link_irq(struct net_device *dev)
3395 u8 __iomem *base = get_hwbase(dev);
3398 miistat = readl(base + NvRegMIIStatus);
3399 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3400 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3402 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3404 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3407 static void nv_msi_workaround(struct fe_priv *np)
3410 /* Need to toggle the msi irq mask within the ethernet device,
3411 * otherwise, future interrupts will not be detected.
3413 if (np->msi_flags & NV_MSI_ENABLED) {
3414 u8 __iomem *base = np->base;
3416 writel(0, base + NvRegMSIIrqMask);
3417 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3421 static irqreturn_t nv_nic_irq(int foo, void *data)
3423 struct net_device *dev = (struct net_device *) data;
3424 struct fe_priv *np = netdev_priv(dev);
3425 u8 __iomem *base = get_hwbase(dev);
3427 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3429 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3430 np->events = readl(base + NvRegIrqStatus);
3431 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3433 np->events = readl(base + NvRegMSIXIrqStatus);
3434 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3436 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3437 if (!(np->events & np->irqmask))
3440 nv_msi_workaround(np);
3442 #ifdef CONFIG_FORCEDETH_NAPI
3443 spin_lock(&np->lock);
3444 napi_schedule(&np->napi);
3446 /* Disable furthur irq's
3447 (msix not enabled with napi) */
3448 writel(0, base + NvRegIrqMask);
3450 spin_unlock(&np->lock);
3454 spin_lock(&np->lock);
3455 nv_tx_done(dev, np->tx_ring_size);
3456 spin_unlock(&np->lock);
3458 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3459 if (unlikely(nv_alloc_rx(dev))) {
3460 spin_lock(&np->lock);
3461 if (!np->in_shutdown)
3462 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3463 spin_unlock(&np->lock);
3467 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3468 spin_lock(&np->lock);
3470 spin_unlock(&np->lock);
3472 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3473 spin_lock(&np->lock);
3475 spin_unlock(&np->lock);
3476 np->link_timeout = jiffies + LINK_TIMEOUT;
3478 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3479 spin_lock(&np->lock);
3480 /* disable interrupts on the nic */
3481 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3482 writel(0, base + NvRegIrqMask);
3484 writel(np->irqmask, base + NvRegIrqMask);
3487 if (!np->in_shutdown) {
3488 np->nic_poll_irq = np->irqmask;
3489 np->recover_error = 1;
3490 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3492 spin_unlock(&np->lock);
3495 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3501 * All _optimized functions are used to help increase performance
3502 * (reduce CPU and increase throughput). They use descripter version 3,
3503 * compiler directives, and reduce memory accesses.
3505 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3507 struct net_device *dev = (struct net_device *) data;
3508 struct fe_priv *np = netdev_priv(dev);
3509 u8 __iomem *base = get_hwbase(dev);
3511 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3513 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3514 np->events = readl(base + NvRegIrqStatus);
3515 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3517 np->events = readl(base + NvRegMSIXIrqStatus);
3518 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3520 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3521 if (!(np->events & np->irqmask))
3524 nv_msi_workaround(np);
3526 #ifdef CONFIG_FORCEDETH_NAPI
3527 spin_lock(&np->lock);
3528 napi_schedule(&np->napi);
3530 /* Disable furthur irq's
3531 (msix not enabled with napi) */
3532 writel(0, base + NvRegIrqMask);
3534 spin_unlock(&np->lock);
3538 spin_lock(&np->lock);
3539 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3540 spin_unlock(&np->lock);
3542 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3543 if (unlikely(nv_alloc_rx_optimized(dev))) {
3544 spin_lock(&np->lock);
3545 if (!np->in_shutdown)
3546 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3547 spin_unlock(&np->lock);
3551 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3552 spin_lock(&np->lock);
3554 spin_unlock(&np->lock);
3556 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3557 spin_lock(&np->lock);
3559 spin_unlock(&np->lock);
3560 np->link_timeout = jiffies + LINK_TIMEOUT;
3562 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3563 spin_lock(&np->lock);
3564 /* disable interrupts on the nic */
3565 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3566 writel(0, base + NvRegIrqMask);
3568 writel(np->irqmask, base + NvRegIrqMask);
3571 if (!np->in_shutdown) {
3572 np->nic_poll_irq = np->irqmask;
3573 np->recover_error = 1;
3574 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3576 spin_unlock(&np->lock);
3580 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3585 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3587 struct net_device *dev = (struct net_device *) data;
3588 struct fe_priv *np = netdev_priv(dev);
3589 u8 __iomem *base = get_hwbase(dev);
3592 unsigned long flags;
3594 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3597 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3598 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3599 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3600 if (!(events & np->irqmask))
3603 spin_lock_irqsave(&np->lock, flags);
3604 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3605 spin_unlock_irqrestore(&np->lock, flags);
3607 if (unlikely(i > max_interrupt_work)) {
3608 spin_lock_irqsave(&np->lock, flags);
3609 /* disable interrupts on the nic */
3610 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3613 if (!np->in_shutdown) {
3614 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3615 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3617 spin_unlock_irqrestore(&np->lock, flags);
3618 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3623 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3625 return IRQ_RETVAL(i);
3628 #ifdef CONFIG_FORCEDETH_NAPI
3629 static int nv_napi_poll(struct napi_struct *napi, int budget)
3631 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3632 struct net_device *dev = np->dev;
3633 u8 __iomem *base = get_hwbase(dev);
3634 unsigned long flags;
3637 if (!nv_optimized(np)) {
3638 spin_lock_irqsave(&np->lock, flags);
3639 nv_tx_done(dev, np->tx_ring_size);
3640 spin_unlock_irqrestore(&np->lock, flags);
3642 pkts = nv_rx_process(dev, budget);
3643 retcode = nv_alloc_rx(dev);
3645 spin_lock_irqsave(&np->lock, flags);
3646 nv_tx_done_optimized(dev, np->tx_ring_size);
3647 spin_unlock_irqrestore(&np->lock, flags);
3649 pkts = nv_rx_process_optimized(dev, budget);
3650 retcode = nv_alloc_rx_optimized(dev);
3654 spin_lock_irqsave(&np->lock, flags);
3655 if (!np->in_shutdown)
3656 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3657 spin_unlock_irqrestore(&np->lock, flags);
3660 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3661 spin_lock_irqsave(&np->lock, flags);
3663 spin_unlock_irqrestore(&np->lock, flags);
3665 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3666 spin_lock_irqsave(&np->lock, flags);
3668 spin_unlock_irqrestore(&np->lock, flags);
3669 np->link_timeout = jiffies + LINK_TIMEOUT;
3671 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3672 spin_lock_irqsave(&np->lock, flags);
3673 if (!np->in_shutdown) {
3674 np->nic_poll_irq = np->irqmask;
3675 np->recover_error = 1;
3676 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3678 spin_unlock_irqrestore(&np->lock, flags);
3679 __napi_complete(napi);
3683 if (pkts < budget) {
3684 /* re-enable interrupts
3685 (msix not enabled in napi) */
3686 spin_lock_irqsave(&np->lock, flags);
3688 __napi_complete(napi);
3690 writel(np->irqmask, base + NvRegIrqMask);
3692 spin_unlock_irqrestore(&np->lock, flags);
3698 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3700 struct net_device *dev = (struct net_device *) data;
3701 struct fe_priv *np = netdev_priv(dev);
3702 u8 __iomem *base = get_hwbase(dev);
3705 unsigned long flags;
3707 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3710 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3711 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3712 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3713 if (!(events & np->irqmask))
3716 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3717 if (unlikely(nv_alloc_rx_optimized(dev))) {
3718 spin_lock_irqsave(&np->lock, flags);
3719 if (!np->in_shutdown)
3720 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3721 spin_unlock_irqrestore(&np->lock, flags);
3725 if (unlikely(i > max_interrupt_work)) {
3726 spin_lock_irqsave(&np->lock, flags);
3727 /* disable interrupts on the nic */
3728 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3731 if (!np->in_shutdown) {
3732 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3733 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3735 spin_unlock_irqrestore(&np->lock, flags);
3736 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3740 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3742 return IRQ_RETVAL(i);
3745 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3747 struct net_device *dev = (struct net_device *) data;
3748 struct fe_priv *np = netdev_priv(dev);
3749 u8 __iomem *base = get_hwbase(dev);
3752 unsigned long flags;
3754 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3757 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3758 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3759 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3760 if (!(events & np->irqmask))
3763 /* check tx in case we reached max loop limit in tx isr */
3764 spin_lock_irqsave(&np->lock, flags);
3765 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3766 spin_unlock_irqrestore(&np->lock, flags);
3768 if (events & NVREG_IRQ_LINK) {
3769 spin_lock_irqsave(&np->lock, flags);
3771 spin_unlock_irqrestore(&np->lock, flags);
3773 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3774 spin_lock_irqsave(&np->lock, flags);
3776 spin_unlock_irqrestore(&np->lock, flags);
3777 np->link_timeout = jiffies + LINK_TIMEOUT;
3779 if (events & NVREG_IRQ_RECOVER_ERROR) {
3780 spin_lock_irq(&np->lock);
3781 /* disable interrupts on the nic */
3782 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3785 if (!np->in_shutdown) {
3786 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3787 np->recover_error = 1;
3788 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3790 spin_unlock_irq(&np->lock);
3793 if (unlikely(i > max_interrupt_work)) {
3794 spin_lock_irqsave(&np->lock, flags);
3795 /* disable interrupts on the nic */
3796 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3799 if (!np->in_shutdown) {
3800 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3801 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3803 spin_unlock_irqrestore(&np->lock, flags);
3804 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3809 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3811 return IRQ_RETVAL(i);
3814 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3816 struct net_device *dev = (struct net_device *) data;
3817 struct fe_priv *np = netdev_priv(dev);
3818 u8 __iomem *base = get_hwbase(dev);
3821 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3823 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3824 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3825 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3827 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3828 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3831 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3832 if (!(events & NVREG_IRQ_TIMER))
3833 return IRQ_RETVAL(0);
3835 nv_msi_workaround(np);
3837 spin_lock(&np->lock);
3839 spin_unlock(&np->lock);
3841 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3843 return IRQ_RETVAL(1);
3846 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3848 u8 __iomem *base = get_hwbase(dev);
3852 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3853 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3854 * the remaining 8 interrupts.
3856 for (i = 0; i < 8; i++) {
3857 if ((irqmask >> i) & 0x1) {
3858 msixmap |= vector << (i << 2);
3861 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3864 for (i = 0; i < 8; i++) {
3865 if ((irqmask >> (i + 8)) & 0x1) {
3866 msixmap |= vector << (i << 2);
3869 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3872 static int nv_request_irq(struct net_device *dev, int intr_test)
3874 struct fe_priv *np = get_nvpriv(dev);
3875 u8 __iomem *base = get_hwbase(dev);
3878 irqreturn_t (*handler)(int foo, void *data);
3881 handler = nv_nic_irq_test;
3883 if (nv_optimized(np))
3884 handler = nv_nic_irq_optimized;
3886 handler = nv_nic_irq;
3889 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3890 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3891 np->msi_x_entry[i].entry = i;
3893 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3894 np->msi_flags |= NV_MSI_X_ENABLED;
3895 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3896 /* Request irq for rx handling */
3897 sprintf(np->name_rx, "%s-rx", dev->name);
3898 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3899 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3900 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3901 pci_disable_msix(np->pci_dev);
3902 np->msi_flags &= ~NV_MSI_X_ENABLED;
3905 /* Request irq for tx handling */
3906 sprintf(np->name_tx, "%s-tx", dev->name);
3907 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3908 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3909 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3910 pci_disable_msix(np->pci_dev);
3911 np->msi_flags &= ~NV_MSI_X_ENABLED;
3914 /* Request irq for link and timer handling */
3915 sprintf(np->name_other, "%s-other", dev->name);
3916 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3917 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3918 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3919 pci_disable_msix(np->pci_dev);
3920 np->msi_flags &= ~NV_MSI_X_ENABLED;
3923 /* map interrupts to their respective vector */
3924 writel(0, base + NvRegMSIXMap0);
3925 writel(0, base + NvRegMSIXMap1);
3926 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3927 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3928 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3930 /* Request irq for all interrupts */
3931 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3932 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3933 pci_disable_msix(np->pci_dev);
3934 np->msi_flags &= ~NV_MSI_X_ENABLED;
3938 /* map interrupts to vector 0 */
3939 writel(0, base + NvRegMSIXMap0);
3940 writel(0, base + NvRegMSIXMap1);
3944 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3945 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3946 np->msi_flags |= NV_MSI_ENABLED;
3947 dev->irq = np->pci_dev->irq;
3948 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3949 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3950 pci_disable_msi(np->pci_dev);
3951 np->msi_flags &= ~NV_MSI_ENABLED;
3952 dev->irq = np->pci_dev->irq;
3956 /* map interrupts to vector 0 */
3957 writel(0, base + NvRegMSIMap0);
3958 writel(0, base + NvRegMSIMap1);
3959 /* enable msi vector 0 */
3960 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3964 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3971 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3973 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3978 static void nv_free_irq(struct net_device *dev)
3980 struct fe_priv *np = get_nvpriv(dev);
3983 if (np->msi_flags & NV_MSI_X_ENABLED) {
3984 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3985 free_irq(np->msi_x_entry[i].vector, dev);
3987 pci_disable_msix(np->pci_dev);
3988 np->msi_flags &= ~NV_MSI_X_ENABLED;
3990 free_irq(np->pci_dev->irq, dev);
3991 if (np->msi_flags & NV_MSI_ENABLED) {
3992 pci_disable_msi(np->pci_dev);
3993 np->msi_flags &= ~NV_MSI_ENABLED;
3998 static void nv_do_nic_poll(unsigned long data)
4000 struct net_device *dev = (struct net_device *) data;
4001 struct fe_priv *np = netdev_priv(dev);
4002 u8 __iomem *base = get_hwbase(dev);
4006 * First disable irq(s) and then
4007 * reenable interrupts on the nic, we have to do this before calling
4008 * nv_nic_irq because that may decide to do otherwise
4011 if (!using_multi_irqs(dev)) {
4012 if (np->msi_flags & NV_MSI_X_ENABLED)
4013 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4015 disable_irq_lockdep(np->pci_dev->irq);
4018 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4019 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4020 mask |= NVREG_IRQ_RX_ALL;
4022 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4023 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4024 mask |= NVREG_IRQ_TX_ALL;
4026 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4027 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4028 mask |= NVREG_IRQ_OTHER;
4031 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4033 if (np->recover_error) {
4034 np->recover_error = 0;
4035 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4036 if (netif_running(dev)) {
4037 netif_tx_lock_bh(dev);
4038 netif_addr_lock(dev);
4039 spin_lock(&np->lock);
4042 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4045 /* drain rx queue */
4047 /* reinit driver view of the rx queue */
4049 if (nv_init_ring(dev)) {
4050 if (!np->in_shutdown)
4051 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4053 /* reinit nic view of the rx queue */
4054 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4055 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4056 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4057 base + NvRegRingSizes);
4059 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4061 /* clear interrupts */
4062 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4063 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4065 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4067 /* restart rx engine */
4069 spin_unlock(&np->lock);
4070 netif_addr_unlock(dev);
4071 netif_tx_unlock_bh(dev);
4075 writel(mask, base + NvRegIrqMask);
4078 if (!using_multi_irqs(dev)) {
4079 np->nic_poll_irq = 0;
4080 if (nv_optimized(np))
4081 nv_nic_irq_optimized(0, dev);
4084 if (np->msi_flags & NV_MSI_X_ENABLED)
4085 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4087 enable_irq_lockdep(np->pci_dev->irq);
4089 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4090 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4091 nv_nic_irq_rx(0, dev);
4092 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4094 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4095 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4096 nv_nic_irq_tx(0, dev);
4097 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4099 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4100 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4101 nv_nic_irq_other(0, dev);
4102 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4108 #ifdef CONFIG_NET_POLL_CONTROLLER
4109 static void nv_poll_controller(struct net_device *dev)
4111 nv_do_nic_poll((unsigned long) dev);
4115 static void nv_do_stats_poll(unsigned long data)
4117 struct net_device *dev = (struct net_device *) data;
4118 struct fe_priv *np = netdev_priv(dev);
4120 nv_get_hw_stats(dev);
4122 if (!np->in_shutdown)
4123 mod_timer(&np->stats_poll,
4124 round_jiffies(jiffies + STATS_INTERVAL));
4127 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4129 struct fe_priv *np = netdev_priv(dev);
4130 strcpy(info->driver, DRV_NAME);
4131 strcpy(info->version, FORCEDETH_VERSION);
4132 strcpy(info->bus_info, pci_name(np->pci_dev));
4135 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4137 struct fe_priv *np = netdev_priv(dev);
4138 wolinfo->supported = WAKE_MAGIC;
4140 spin_lock_irq(&np->lock);
4142 wolinfo->wolopts = WAKE_MAGIC;
4143 spin_unlock_irq(&np->lock);
4146 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4148 struct fe_priv *np = netdev_priv(dev);
4149 u8 __iomem *base = get_hwbase(dev);
4152 if (wolinfo->wolopts == 0) {
4154 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4156 flags = NVREG_WAKEUPFLAGS_ENABLE;
4158 if (netif_running(dev)) {
4159 spin_lock_irq(&np->lock);
4160 writel(flags, base + NvRegWakeUpFlags);
4161 spin_unlock_irq(&np->lock);
4166 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4168 struct fe_priv *np = netdev_priv(dev);
4171 spin_lock_irq(&np->lock);
4172 ecmd->port = PORT_MII;
4173 if (!netif_running(dev)) {
4174 /* We do not track link speed / duplex setting if the
4175 * interface is disabled. Force a link check */
4176 if (nv_update_linkspeed(dev)) {
4177 if (!netif_carrier_ok(dev))
4178 netif_carrier_on(dev);
4180 if (netif_carrier_ok(dev))
4181 netif_carrier_off(dev);
4185 if (netif_carrier_ok(dev)) {
4186 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4187 case NVREG_LINKSPEED_10:
4188 ecmd->speed = SPEED_10;
4190 case NVREG_LINKSPEED_100:
4191 ecmd->speed = SPEED_100;
4193 case NVREG_LINKSPEED_1000:
4194 ecmd->speed = SPEED_1000;
4197 ecmd->duplex = DUPLEX_HALF;
4199 ecmd->duplex = DUPLEX_FULL;
4205 ecmd->autoneg = np->autoneg;
4207 ecmd->advertising = ADVERTISED_MII;
4209 ecmd->advertising |= ADVERTISED_Autoneg;
4210 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4211 if (adv & ADVERTISE_10HALF)
4212 ecmd->advertising |= ADVERTISED_10baseT_Half;
4213 if (adv & ADVERTISE_10FULL)
4214 ecmd->advertising |= ADVERTISED_10baseT_Full;
4215 if (adv & ADVERTISE_100HALF)
4216 ecmd->advertising |= ADVERTISED_100baseT_Half;
4217 if (adv & ADVERTISE_100FULL)
4218 ecmd->advertising |= ADVERTISED_100baseT_Full;
4219 if (np->gigabit == PHY_GIGABIT) {
4220 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4221 if (adv & ADVERTISE_1000FULL)
4222 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4225 ecmd->supported = (SUPPORTED_Autoneg |
4226 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4227 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4229 if (np->gigabit == PHY_GIGABIT)
4230 ecmd->supported |= SUPPORTED_1000baseT_Full;
4232 ecmd->phy_address = np->phyaddr;
4233 ecmd->transceiver = XCVR_EXTERNAL;
4235 /* ignore maxtxpkt, maxrxpkt for now */
4236 spin_unlock_irq(&np->lock);
4240 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4242 struct fe_priv *np = netdev_priv(dev);
4244 if (ecmd->port != PORT_MII)
4246 if (ecmd->transceiver != XCVR_EXTERNAL)
4248 if (ecmd->phy_address != np->phyaddr) {
4249 /* TODO: support switching between multiple phys. Should be
4250 * trivial, but not enabled due to lack of test hardware. */
4253 if (ecmd->autoneg == AUTONEG_ENABLE) {
4256 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4257 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4258 if (np->gigabit == PHY_GIGABIT)
4259 mask |= ADVERTISED_1000baseT_Full;
4261 if ((ecmd->advertising & mask) == 0)
4264 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4265 /* Note: autonegotiation disable, speed 1000 intentionally
4266 * forbidden - noone should need that. */
4268 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4270 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4276 netif_carrier_off(dev);
4277 if (netif_running(dev)) {
4278 unsigned long flags;
4280 nv_disable_irq(dev);
4281 netif_tx_lock_bh(dev);
4282 netif_addr_lock(dev);
4283 /* with plain spinlock lockdep complains */
4284 spin_lock_irqsave(&np->lock, flags);
4287 * this can take some time, and interrupts are disabled
4288 * due to spin_lock_irqsave, but let's hope no daemon
4289 * is going to change the settings very often...
4291 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4292 * + some minor delays, which is up to a second approximately
4295 spin_unlock_irqrestore(&np->lock, flags);
4296 netif_addr_unlock(dev);
4297 netif_tx_unlock_bh(dev);
4300 if (ecmd->autoneg == AUTONEG_ENABLE) {
4305 /* advertise only what has been requested */
4306 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4307 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4308 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4309 adv |= ADVERTISE_10HALF;
4310 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4311 adv |= ADVERTISE_10FULL;
4312 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4313 adv |= ADVERTISE_100HALF;
4314 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4315 adv |= ADVERTISE_100FULL;
4316 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4317 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4318 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4319 adv |= ADVERTISE_PAUSE_ASYM;
4320 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4322 if (np->gigabit == PHY_GIGABIT) {
4323 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4324 adv &= ~ADVERTISE_1000FULL;
4325 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4326 adv |= ADVERTISE_1000FULL;
4327 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4330 if (netif_running(dev))
4331 printk(KERN_INFO "%s: link down.\n", dev->name);
4332 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4333 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4334 bmcr |= BMCR_ANENABLE;
4335 /* reset the phy in order for settings to stick,
4336 * and cause autoneg to start */
4337 if (phy_reset(dev, bmcr)) {
4338 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4342 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4343 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4350 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4351 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4352 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4353 adv |= ADVERTISE_10HALF;
4354 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4355 adv |= ADVERTISE_10FULL;
4356 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4357 adv |= ADVERTISE_100HALF;
4358 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4359 adv |= ADVERTISE_100FULL;
4360 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4361 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4362 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4363 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4365 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4366 adv |= ADVERTISE_PAUSE_ASYM;
4367 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4369 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4370 np->fixed_mode = adv;
4372 if (np->gigabit == PHY_GIGABIT) {
4373 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4374 adv &= ~ADVERTISE_1000FULL;
4375 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4378 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4379 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4380 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4381 bmcr |= BMCR_FULLDPLX;
4382 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4383 bmcr |= BMCR_SPEED100;
4384 if (np->phy_oui == PHY_OUI_MARVELL) {
4385 /* reset the phy in order for forced mode settings to stick */
4386 if (phy_reset(dev, bmcr)) {
4387 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4391 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4392 if (netif_running(dev)) {
4393 /* Wait a bit and then reconfigure the nic. */
4400 if (netif_running(dev)) {
4408 #define FORCEDETH_REGS_VER 1
4410 static int nv_get_regs_len(struct net_device *dev)
4412 struct fe_priv *np = netdev_priv(dev);
4413 return np->register_size;
4416 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4418 struct fe_priv *np = netdev_priv(dev);
4419 u8 __iomem *base = get_hwbase(dev);
4423 regs->version = FORCEDETH_REGS_VER;
4424 spin_lock_irq(&np->lock);
4425 for (i = 0;i <= np->register_size/sizeof(u32); i++)
4426 rbuf[i] = readl(base + i*sizeof(u32));
4427 spin_unlock_irq(&np->lock);
4430 static int nv_nway_reset(struct net_device *dev)
4432 struct fe_priv *np = netdev_priv(dev);
4438 netif_carrier_off(dev);
4439 if (netif_running(dev)) {
4440 nv_disable_irq(dev);
4441 netif_tx_lock_bh(dev);
4442 netif_addr_lock(dev);
4443 spin_lock(&np->lock);
4446 spin_unlock(&np->lock);
4447 netif_addr_unlock(dev);
4448 netif_tx_unlock_bh(dev);
4449 printk(KERN_INFO "%s: link down.\n", dev->name);
4452 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4453 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4454 bmcr |= BMCR_ANENABLE;
4455 /* reset the phy in order for settings to stick*/
4456 if (phy_reset(dev, bmcr)) {
4457 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4461 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4462 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4465 if (netif_running(dev)) {
4477 static int nv_set_tso(struct net_device *dev, u32 value)
4479 struct fe_priv *np = netdev_priv(dev);
4481 if ((np->driver_data & DEV_HAS_CHECKSUM))
4482 return ethtool_op_set_tso(dev, value);
4487 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4489 struct fe_priv *np = netdev_priv(dev);
4491 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4492 ring->rx_mini_max_pending = 0;
4493 ring->rx_jumbo_max_pending = 0;
4494 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4496 ring->rx_pending = np->rx_ring_size;
4497 ring->rx_mini_pending = 0;
4498 ring->rx_jumbo_pending = 0;
4499 ring->tx_pending = np->tx_ring_size;
4502 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4504 struct fe_priv *np = netdev_priv(dev);
4505 u8 __iomem *base = get_hwbase(dev);
4506 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4507 dma_addr_t ring_addr;
4509 if (ring->rx_pending < RX_RING_MIN ||
4510 ring->tx_pending < TX_RING_MIN ||
4511 ring->rx_mini_pending != 0 ||
4512 ring->rx_jumbo_pending != 0 ||
4513 (np->desc_ver == DESC_VER_1 &&
4514 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4515 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4516 (np->desc_ver != DESC_VER_1 &&
4517 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4518 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4522 /* allocate new rings */
4523 if (!nv_optimized(np)) {
4524 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4525 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4528 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4529 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4532 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4533 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4534 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4535 /* fall back to old rings */
4536 if (!nv_optimized(np)) {
4538 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4539 rxtx_ring, ring_addr);
4542 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4543 rxtx_ring, ring_addr);
4552 if (netif_running(dev)) {
4553 nv_disable_irq(dev);
4554 nv_napi_disable(dev);
4555 netif_tx_lock_bh(dev);
4556 netif_addr_lock(dev);
4557 spin_lock(&np->lock);
4567 /* set new values */
4568 np->rx_ring_size = ring->rx_pending;
4569 np->tx_ring_size = ring->tx_pending;
4571 if (!nv_optimized(np)) {
4572 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4573 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4575 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4576 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4578 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4579 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4580 np->ring_addr = ring_addr;
4582 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4583 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4585 if (netif_running(dev)) {
4586 /* reinit driver view of the queues */
4588 if (nv_init_ring(dev)) {
4589 if (!np->in_shutdown)
4590 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4593 /* reinit nic view of the queues */
4594 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4595 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4596 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4597 base + NvRegRingSizes);
4599 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4602 /* restart engines */
4604 spin_unlock(&np->lock);
4605 netif_addr_unlock(dev);
4606 netif_tx_unlock_bh(dev);
4607 nv_napi_enable(dev);
4615 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4617 struct fe_priv *np = netdev_priv(dev);
4619 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4620 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4621 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4624 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4626 struct fe_priv *np = netdev_priv(dev);
4629 if ((!np->autoneg && np->duplex == 0) ||
4630 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4631 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4635 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4636 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4640 netif_carrier_off(dev);
4641 if (netif_running(dev)) {
4642 nv_disable_irq(dev);
4643 netif_tx_lock_bh(dev);
4644 netif_addr_lock(dev);
4645 spin_lock(&np->lock);
4648 spin_unlock(&np->lock);
4649 netif_addr_unlock(dev);
4650 netif_tx_unlock_bh(dev);
4653 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4654 if (pause->rx_pause)
4655 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4656 if (pause->tx_pause)
4657 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4659 if (np->autoneg && pause->autoneg) {
4660 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4662 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4663 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4664 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4665 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4666 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4667 adv |= ADVERTISE_PAUSE_ASYM;
4668 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4670 if (netif_running(dev))
4671 printk(KERN_INFO "%s: link down.\n", dev->name);
4672 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4673 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4674 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4676 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4677 if (pause->rx_pause)
4678 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4679 if (pause->tx_pause)
4680 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4682 if (!netif_running(dev))
4683 nv_update_linkspeed(dev);
4685 nv_update_pause(dev, np->pause_flags);
4688 if (netif_running(dev)) {
4695 static u32 nv_get_rx_csum(struct net_device *dev)
4697 struct fe_priv *np = netdev_priv(dev);
4698 return (np->rx_csum) != 0;
4701 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4703 struct fe_priv *np = netdev_priv(dev);
4704 u8 __iomem *base = get_hwbase(dev);
4707 if (np->driver_data & DEV_HAS_CHECKSUM) {
4710 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4713 /* vlan is dependent on rx checksum offload */
4714 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4715 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4717 if (netif_running(dev)) {
4718 spin_lock_irq(&np->lock);
4719 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4720 spin_unlock_irq(&np->lock);
4729 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4731 struct fe_priv *np = netdev_priv(dev);
4733 if (np->driver_data & DEV_HAS_CHECKSUM)
4734 return ethtool_op_set_tx_csum(dev, data);
4739 static int nv_set_sg(struct net_device *dev, u32 data)
4741 struct fe_priv *np = netdev_priv(dev);
4743 if (np->driver_data & DEV_HAS_CHECKSUM)
4744 return ethtool_op_set_sg(dev, data);
4749 static int nv_get_sset_count(struct net_device *dev, int sset)
4751 struct fe_priv *np = netdev_priv(dev);
4755 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4756 return NV_TEST_COUNT_EXTENDED;
4758 return NV_TEST_COUNT_BASE;
4760 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4761 return NV_DEV_STATISTICS_V3_COUNT;
4762 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4763 return NV_DEV_STATISTICS_V2_COUNT;
4764 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4765 return NV_DEV_STATISTICS_V1_COUNT;
4773 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4775 struct fe_priv *np = netdev_priv(dev);
4778 nv_do_stats_poll((unsigned long)dev);
4780 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4783 static int nv_link_test(struct net_device *dev)
4785 struct fe_priv *np = netdev_priv(dev);
4788 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4789 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4791 /* check phy link status */
4792 if (!(mii_status & BMSR_LSTATUS))
4798 static int nv_register_test(struct net_device *dev)
4800 u8 __iomem *base = get_hwbase(dev);
4802 u32 orig_read, new_read;
4805 orig_read = readl(base + nv_registers_test[i].reg);
4807 /* xor with mask to toggle bits */
4808 orig_read ^= nv_registers_test[i].mask;
4810 writel(orig_read, base + nv_registers_test[i].reg);
4812 new_read = readl(base + nv_registers_test[i].reg);
4814 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4817 /* restore original value */
4818 orig_read ^= nv_registers_test[i].mask;
4819 writel(orig_read, base + nv_registers_test[i].reg);
4821 } while (nv_registers_test[++i].reg != 0);
4826 static int nv_interrupt_test(struct net_device *dev)
4828 struct fe_priv *np = netdev_priv(dev);
4829 u8 __iomem *base = get_hwbase(dev);
4832 u32 save_msi_flags, save_poll_interval = 0;
4834 if (netif_running(dev)) {
4835 /* free current irq */
4837 save_poll_interval = readl(base+NvRegPollingInterval);
4840 /* flag to test interrupt handler */
4843 /* setup test irq */
4844 save_msi_flags = np->msi_flags;
4845 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4846 np->msi_flags |= 0x001; /* setup 1 vector */
4847 if (nv_request_irq(dev, 1))
4850 /* setup timer interrupt */
4851 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4852 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4854 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4856 /* wait for at least one interrupt */
4859 spin_lock_irq(&np->lock);
4861 /* flag should be set within ISR */
4862 testcnt = np->intr_test;
4866 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4867 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4868 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4870 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4872 spin_unlock_irq(&np->lock);
4876 np->msi_flags = save_msi_flags;
4878 if (netif_running(dev)) {
4879 writel(save_poll_interval, base + NvRegPollingInterval);
4880 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4881 /* restore original irq */
4882 if (nv_request_irq(dev, 0))
4889 static int nv_loopback_test(struct net_device *dev)
4891 struct fe_priv *np = netdev_priv(dev);
4892 u8 __iomem *base = get_hwbase(dev);
4893 struct sk_buff *tx_skb, *rx_skb;
4894 dma_addr_t test_dma_addr;
4895 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4897 int len, i, pkt_len;
4899 u32 filter_flags = 0;
4900 u32 misc1_flags = 0;
4903 if (netif_running(dev)) {
4904 nv_disable_irq(dev);
4905 filter_flags = readl(base + NvRegPacketFilterFlags);
4906 misc1_flags = readl(base + NvRegMisc1);
4911 /* reinit driver view of the rx queue */
4915 /* setup hardware for loopback */
4916 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4917 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4919 /* reinit nic view of the rx queue */
4920 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4921 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4922 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4923 base + NvRegRingSizes);
4926 /* restart rx engine */
4929 /* setup packet for tx */
4930 pkt_len = ETH_DATA_LEN;
4931 tx_skb = dev_alloc_skb(pkt_len);
4933 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4934 " of %s\n", dev->name);
4938 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4939 skb_tailroom(tx_skb),
4940 PCI_DMA_FROMDEVICE);
4941 pkt_data = skb_put(tx_skb, pkt_len);
4942 for (i = 0; i < pkt_len; i++)
4943 pkt_data[i] = (u8)(i & 0xff);
4945 if (!nv_optimized(np)) {
4946 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4947 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4949 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4950 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4951 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4953 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4954 pci_push(get_hwbase(dev));
4958 /* check for rx of the packet */
4959 if (!nv_optimized(np)) {
4960 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4961 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4964 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4965 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4968 if (flags & NV_RX_AVAIL) {
4970 } else if (np->desc_ver == DESC_VER_1) {
4971 if (flags & NV_RX_ERROR)
4974 if (flags & NV_RX2_ERROR) {
4980 if (len != pkt_len) {
4982 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4983 dev->name, len, pkt_len);
4985 rx_skb = np->rx_skb[0].skb;
4986 for (i = 0; i < pkt_len; i++) {
4987 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4989 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4996 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4999 pci_unmap_page(np->pci_dev, test_dma_addr,
5000 (skb_end_pointer(tx_skb) - tx_skb->data),
5002 dev_kfree_skb_any(tx_skb);
5007 /* drain rx queue */
5010 if (netif_running(dev)) {
5011 writel(misc1_flags, base + NvRegMisc1);
5012 writel(filter_flags, base + NvRegPacketFilterFlags);
5019 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5021 struct fe_priv *np = netdev_priv(dev);
5022 u8 __iomem *base = get_hwbase(dev);
5024 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5026 if (!nv_link_test(dev)) {
5027 test->flags |= ETH_TEST_FL_FAILED;
5031 if (test->flags & ETH_TEST_FL_OFFLINE) {
5032 if (netif_running(dev)) {
5033 netif_stop_queue(dev);
5034 nv_napi_disable(dev);
5035 netif_tx_lock_bh(dev);
5036 netif_addr_lock(dev);
5037 spin_lock_irq(&np->lock);
5038 nv_disable_hw_interrupts(dev, np->irqmask);
5039 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5040 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5042 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5047 /* drain rx queue */
5049 spin_unlock_irq(&np->lock);
5050 netif_addr_unlock(dev);
5051 netif_tx_unlock_bh(dev);
5054 if (!nv_register_test(dev)) {
5055 test->flags |= ETH_TEST_FL_FAILED;
5059 result = nv_interrupt_test(dev);
5061 test->flags |= ETH_TEST_FL_FAILED;
5069 if (!nv_loopback_test(dev)) {
5070 test->flags |= ETH_TEST_FL_FAILED;
5074 if (netif_running(dev)) {
5075 /* reinit driver view of the rx queue */
5077 if (nv_init_ring(dev)) {
5078 if (!np->in_shutdown)
5079 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5081 /* reinit nic view of the rx queue */
5082 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5083 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5084 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5085 base + NvRegRingSizes);
5087 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5089 /* restart rx engine */
5091 netif_start_queue(dev);
5092 nv_napi_enable(dev);
5093 nv_enable_hw_interrupts(dev, np->irqmask);
5098 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5100 switch (stringset) {
5102 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5105 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5110 static const struct ethtool_ops ops = {
5111 .get_drvinfo = nv_get_drvinfo,
5112 .get_link = ethtool_op_get_link,
5113 .get_wol = nv_get_wol,
5114 .set_wol = nv_set_wol,
5115 .get_settings = nv_get_settings,
5116 .set_settings = nv_set_settings,
5117 .get_regs_len = nv_get_regs_len,
5118 .get_regs = nv_get_regs,
5119 .nway_reset = nv_nway_reset,
5120 .set_tso = nv_set_tso,
5121 .get_ringparam = nv_get_ringparam,
5122 .set_ringparam = nv_set_ringparam,
5123 .get_pauseparam = nv_get_pauseparam,
5124 .set_pauseparam = nv_set_pauseparam,
5125 .get_rx_csum = nv_get_rx_csum,
5126 .set_rx_csum = nv_set_rx_csum,
5127 .set_tx_csum = nv_set_tx_csum,
5128 .set_sg = nv_set_sg,
5129 .get_strings = nv_get_strings,
5130 .get_ethtool_stats = nv_get_ethtool_stats,
5131 .get_sset_count = nv_get_sset_count,
5132 .self_test = nv_self_test,
5135 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5137 struct fe_priv *np = get_nvpriv(dev);
5139 spin_lock_irq(&np->lock);
5141 /* save vlan group */
5145 /* enable vlan on MAC */
5146 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5148 /* disable vlan on MAC */
5149 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5150 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5153 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5155 spin_unlock_irq(&np->lock);
5158 /* The mgmt unit and driver use a semaphore to access the phy during init */
5159 static int nv_mgmt_acquire_sema(struct net_device *dev)
5161 struct fe_priv *np = netdev_priv(dev);
5162 u8 __iomem *base = get_hwbase(dev);
5164 u32 tx_ctrl, mgmt_sema;
5166 for (i = 0; i < 10; i++) {
5167 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5168 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5173 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5176 for (i = 0; i < 2; i++) {
5177 tx_ctrl = readl(base + NvRegTransmitterControl);
5178 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5179 writel(tx_ctrl, base + NvRegTransmitterControl);
5181 /* verify that semaphore was acquired */
5182 tx_ctrl = readl(base + NvRegTransmitterControl);
5183 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5184 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5195 static void nv_mgmt_release_sema(struct net_device *dev)
5197 struct fe_priv *np = netdev_priv(dev);
5198 u8 __iomem *base = get_hwbase(dev);
5201 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5202 if (np->mgmt_sema) {
5203 tx_ctrl = readl(base + NvRegTransmitterControl);
5204 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5205 writel(tx_ctrl, base + NvRegTransmitterControl);
5211 static int nv_mgmt_get_version(struct net_device *dev)
5213 struct fe_priv *np = netdev_priv(dev);
5214 u8 __iomem *base = get_hwbase(dev);
5215 u32 data_ready = readl(base + NvRegTransmitterControl);
5216 u32 data_ready2 = 0;
5217 unsigned long start;
5220 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5221 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5223 while (time_before(jiffies, start + 5*HZ)) {
5224 data_ready2 = readl(base + NvRegTransmitterControl);
5225 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5229 schedule_timeout_uninterruptible(1);
5232 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5235 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5240 static int nv_open(struct net_device *dev)
5242 struct fe_priv *np = netdev_priv(dev);
5243 u8 __iomem *base = get_hwbase(dev);
5248 dprintk(KERN_DEBUG "nv_open: begin\n");
5251 mii_rw(dev, np->phyaddr, MII_BMCR,
5252 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5254 /* erase previous misconfiguration */
5255 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5257 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5258 writel(0, base + NvRegMulticastAddrB);
5259 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5260 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5261 writel(0, base + NvRegPacketFilterFlags);
5263 writel(0, base + NvRegTransmitterControl);
5264 writel(0, base + NvRegReceiverControl);
5266 writel(0, base + NvRegAdapterControl);
5268 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5269 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5271 /* initialize descriptor rings */
5273 oom = nv_init_ring(dev);
5275 writel(0, base + NvRegLinkSpeed);
5276 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5278 writel(0, base + NvRegUnknownSetupReg6);
5280 np->in_shutdown = 0;
5283 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5284 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5285 base + NvRegRingSizes);
5287 writel(np->linkspeed, base + NvRegLinkSpeed);
5288 if (np->desc_ver == DESC_VER_1)
5289 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5291 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5292 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5293 writel(np->vlanctl_bits, base + NvRegVlanControl);
5295 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5296 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5297 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5298 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5300 writel(0, base + NvRegMIIMask);
5301 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5302 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5304 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5305 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5306 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5307 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5309 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5311 get_random_bytes(&low, sizeof(low));
5312 low &= NVREG_SLOTTIME_MASK;
5313 if (np->desc_ver == DESC_VER_1) {
5314 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5316 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5317 /* setup legacy backoff */
5318 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5320 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5321 nv_gear_backoff_reseed(dev);
5324 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5325 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5326 if (poll_interval == -1) {
5327 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5328 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5330 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5333 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5334 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5335 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5336 base + NvRegAdapterControl);
5337 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5338 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5340 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5342 i = readl(base + NvRegPowerState);
5343 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5344 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5348 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5350 nv_disable_hw_interrupts(dev, np->irqmask);
5352 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5353 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5356 if (nv_request_irq(dev, 0)) {
5360 /* ask for interrupts */
5361 nv_enable_hw_interrupts(dev, np->irqmask);
5363 spin_lock_irq(&np->lock);
5364 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5365 writel(0, base + NvRegMulticastAddrB);
5366 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5367 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5368 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5369 /* One manual link speed update: Interrupts are enabled, future link
5370 * speed changes cause interrupts and are handled by nv_link_irq().
5374 miistat = readl(base + NvRegMIIStatus);
5375 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5376 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5378 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5381 ret = nv_update_linkspeed(dev);
5383 netif_start_queue(dev);
5384 nv_napi_enable(dev);
5387 netif_carrier_on(dev);
5389 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5390 netif_carrier_off(dev);
5393 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5395 /* start statistics timer */
5396 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5397 mod_timer(&np->stats_poll,
5398 round_jiffies(jiffies + STATS_INTERVAL));
5400 spin_unlock_irq(&np->lock);
5408 static int nv_close(struct net_device *dev)
5410 struct fe_priv *np = netdev_priv(dev);
5413 spin_lock_irq(&np->lock);
5414 np->in_shutdown = 1;
5415 spin_unlock_irq(&np->lock);
5416 nv_napi_disable(dev);
5417 synchronize_irq(np->pci_dev->irq);
5419 del_timer_sync(&np->oom_kick);
5420 del_timer_sync(&np->nic_poll);
5421 del_timer_sync(&np->stats_poll);
5423 netif_stop_queue(dev);
5424 spin_lock_irq(&np->lock);
5428 /* disable interrupts on the nic or we will lock up */
5429 base = get_hwbase(dev);
5430 nv_disable_hw_interrupts(dev, np->irqmask);
5432 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5434 spin_unlock_irq(&np->lock);
5440 if (np->wolenabled) {
5441 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5444 /* power down phy */
5445 mii_rw(dev, np->phyaddr, MII_BMCR,
5446 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5449 /* FIXME: power down nic */
5454 static const struct net_device_ops nv_netdev_ops = {
5455 .ndo_open = nv_open,
5456 .ndo_stop = nv_close,
5457 .ndo_get_stats = nv_get_stats,
5458 .ndo_start_xmit = nv_start_xmit,
5459 .ndo_tx_timeout = nv_tx_timeout,
5460 .ndo_change_mtu = nv_change_mtu,
5461 .ndo_validate_addr = eth_validate_addr,
5462 .ndo_set_mac_address = nv_set_mac_address,
5463 .ndo_set_multicast_list = nv_set_multicast,
5464 .ndo_vlan_rx_register = nv_vlan_rx_register,
5465 #ifdef CONFIG_NET_POLL_CONTROLLER
5466 .ndo_poll_controller = nv_poll_controller,
5470 static const struct net_device_ops nv_netdev_ops_optimized = {
5471 .ndo_open = nv_open,
5472 .ndo_stop = nv_close,
5473 .ndo_get_stats = nv_get_stats,
5474 .ndo_start_xmit = nv_start_xmit_optimized,
5475 .ndo_tx_timeout = nv_tx_timeout,
5476 .ndo_change_mtu = nv_change_mtu,
5477 .ndo_validate_addr = eth_validate_addr,
5478 .ndo_set_mac_address = nv_set_mac_address,
5479 .ndo_set_multicast_list = nv_set_multicast,
5480 .ndo_vlan_rx_register = nv_vlan_rx_register,
5481 #ifdef CONFIG_NET_POLL_CONTROLLER
5482 .ndo_poll_controller = nv_poll_controller,
5486 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5488 struct net_device *dev;
5493 u32 powerstate, txreg;
5494 u32 phystate_orig = 0, phystate;
5495 int phyinitialized = 0;
5496 static int printed_version;
5498 if (!printed_version++)
5499 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5500 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5502 dev = alloc_etherdev(sizeof(struct fe_priv));
5507 np = netdev_priv(dev);
5509 np->pci_dev = pci_dev;
5510 spin_lock_init(&np->lock);
5511 SET_NETDEV_DEV(dev, &pci_dev->dev);
5513 init_timer(&np->oom_kick);
5514 np->oom_kick.data = (unsigned long) dev;
5515 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5516 init_timer(&np->nic_poll);
5517 np->nic_poll.data = (unsigned long) dev;
5518 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
5519 init_timer(&np->stats_poll);
5520 np->stats_poll.data = (unsigned long) dev;
5521 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
5523 err = pci_enable_device(pci_dev);
5527 pci_set_master(pci_dev);
5529 err = pci_request_regions(pci_dev, DRV_NAME);
5533 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5534 np->register_size = NV_PCI_REGSZ_VER3;
5535 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5536 np->register_size = NV_PCI_REGSZ_VER2;
5538 np->register_size = NV_PCI_REGSZ_VER1;
5542 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5543 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5544 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5545 pci_resource_len(pci_dev, i),
5546 pci_resource_flags(pci_dev, i));
5547 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5548 pci_resource_len(pci_dev, i) >= np->register_size) {
5549 addr = pci_resource_start(pci_dev, i);
5553 if (i == DEVICE_COUNT_RESOURCE) {
5554 dev_printk(KERN_INFO, &pci_dev->dev,
5555 "Couldn't find register window\n");
5559 /* copy of driver data */
5560 np->driver_data = id->driver_data;
5561 /* copy of device id */
5562 np->device_id = id->device;
5564 /* handle different descriptor versions */
5565 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5566 /* packet format 3: supports 40-bit addressing */
5567 np->desc_ver = DESC_VER_3;
5568 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5570 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5571 dev_printk(KERN_INFO, &pci_dev->dev,
5572 "64-bit DMA failed, using 32-bit addressing\n");
5574 dev->features |= NETIF_F_HIGHDMA;
5575 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5576 dev_printk(KERN_INFO, &pci_dev->dev,
5577 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5580 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5581 /* packet format 2: supports jumbo frames */
5582 np->desc_ver = DESC_VER_2;
5583 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5585 /* original packet format */
5586 np->desc_ver = DESC_VER_1;
5587 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5590 np->pkt_limit = NV_PKTLIMIT_1;
5591 if (id->driver_data & DEV_HAS_LARGEDESC)
5592 np->pkt_limit = NV_PKTLIMIT_2;
5594 if (id->driver_data & DEV_HAS_CHECKSUM) {
5596 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5597 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5598 dev->features |= NETIF_F_TSO;
5601 np->vlanctl_bits = 0;
5602 if (id->driver_data & DEV_HAS_VLAN) {
5603 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5604 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5607 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5608 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5609 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5610 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5611 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5616 np->base = ioremap(addr, np->register_size);
5619 dev->base_addr = (unsigned long)np->base;
5621 dev->irq = pci_dev->irq;
5623 np->rx_ring_size = RX_RING_DEFAULT;
5624 np->tx_ring_size = TX_RING_DEFAULT;
5626 if (!nv_optimized(np)) {
5627 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5628 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5630 if (!np->rx_ring.orig)
5632 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5634 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5635 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5637 if (!np->rx_ring.ex)
5639 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5641 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5642 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5643 if (!np->rx_skb || !np->tx_skb)
5646 if (!nv_optimized(np))
5647 dev->netdev_ops = &nv_netdev_ops;
5649 dev->netdev_ops = &nv_netdev_ops_optimized;
5651 #ifdef CONFIG_FORCEDETH_NAPI
5652 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5654 SET_ETHTOOL_OPS(dev, &ops);
5655 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5657 pci_set_drvdata(pci_dev, dev);
5659 /* read the mac address */
5660 base = get_hwbase(dev);
5661 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5662 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5664 /* check the workaround bit for correct mac address order */
5665 txreg = readl(base + NvRegTransmitPoll);
5666 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5667 /* mac address is already in correct order */
5668 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5669 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5670 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5671 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5672 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5673 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5674 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5675 /* mac address is already in correct order */
5676 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5677 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5678 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5679 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5680 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5681 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5683 * Set orig mac address back to the reversed version.
5684 * This flag will be cleared during low power transition.
5685 * Therefore, we should always put back the reversed address.
5687 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5688 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5689 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5691 /* need to reverse mac address to correct order */
5692 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5693 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5694 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5695 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5696 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5697 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5698 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5699 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5701 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5703 if (!is_valid_ether_addr(dev->perm_addr)) {
5705 * Bad mac address. At least one bios sets the mac address
5706 * to 01:23:45:67:89:ab
5708 dev_printk(KERN_ERR, &pci_dev->dev,
5709 "Invalid Mac address detected: %pM\n",
5711 dev_printk(KERN_ERR, &pci_dev->dev,
5712 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5713 dev->dev_addr[0] = 0x00;
5714 dev->dev_addr[1] = 0x00;
5715 dev->dev_addr[2] = 0x6c;
5716 get_random_bytes(&dev->dev_addr[3], 3);
5719 dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5720 pci_name(pci_dev), dev->dev_addr);
5722 /* set mac address */
5723 nv_copy_mac_to_hw(dev);
5725 /* Workaround current PCI init glitch: wakeup bits aren't
5726 * being set from PCI PM capability.
5728 device_init_wakeup(&pci_dev->dev, 1);
5731 writel(0, base + NvRegWakeUpFlags);
5734 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5736 /* take phy and nic out of low power mode */
5737 powerstate = readl(base + NvRegPowerState2);
5738 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5739 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5740 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5741 pci_dev->revision >= 0xA3)
5742 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5743 writel(powerstate, base + NvRegPowerState2);
5746 if (np->desc_ver == DESC_VER_1) {
5747 np->tx_flags = NV_TX_VALID;
5749 np->tx_flags = NV_TX2_VALID;
5753 if ((id->driver_data & DEV_HAS_MSI) && msi) {
5754 np->msi_flags |= NV_MSI_CAPABLE;
5756 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5757 /* msix has had reported issues when modifying irqmask
5758 as in the case of napi, therefore, disable for now
5760 #ifndef CONFIG_FORCEDETH_NAPI
5761 np->msi_flags |= NV_MSI_X_CAPABLE;
5765 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5766 np->irqmask = NVREG_IRQMASK_CPU;
5767 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5768 np->msi_flags |= 0x0001;
5769 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5770 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5771 /* start off in throughput mode */
5772 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5773 /* remove support for msix mode */
5774 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5776 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5777 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5778 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5779 np->msi_flags |= 0x0003;
5782 if (id->driver_data & DEV_NEED_TIMERIRQ)
5783 np->irqmask |= NVREG_IRQ_TIMER;
5784 if (id->driver_data & DEV_NEED_LINKTIMER) {
5785 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5786 np->need_linktimer = 1;
5787 np->link_timeout = jiffies + LINK_TIMEOUT;
5789 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5790 np->need_linktimer = 0;
5793 /* Limit the number of tx's outstanding for hw bug */
5794 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5796 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5797 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5798 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5799 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5800 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5801 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5802 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5803 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5804 pci_dev->revision >= 0xA2)
5808 /* clear phy state and temporarily halt phy interrupts */
5809 writel(0, base + NvRegMIIMask);
5810 phystate = readl(base + NvRegAdapterControl);
5811 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5813 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5814 writel(phystate, base + NvRegAdapterControl);
5816 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5818 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5819 /* management unit running on the mac? */
5820 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5821 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5822 nv_mgmt_acquire_sema(dev) &&
5823 nv_mgmt_get_version(dev)) {
5825 if (np->mgmt_version > 0) {
5826 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5828 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5829 pci_name(pci_dev), np->mac_in_use);
5830 /* management unit setup the phy already? */
5831 if (np->mac_in_use &&
5832 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5833 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5834 /* phy is inited by mgmt unit */
5836 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5839 /* we need to init the phy */
5844 /* find a suitable phy */
5845 for (i = 1; i <= 32; i++) {
5847 int phyaddr = i & 0x1F;
5849 spin_lock_irq(&np->lock);
5850 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5851 spin_unlock_irq(&np->lock);
5852 if (id1 < 0 || id1 == 0xffff)
5854 spin_lock_irq(&np->lock);
5855 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5856 spin_unlock_irq(&np->lock);
5857 if (id2 < 0 || id2 == 0xffff)
5860 np->phy_model = id2 & PHYID2_MODEL_MASK;
5861 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5862 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5863 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5864 pci_name(pci_dev), id1, id2, phyaddr);
5865 np->phyaddr = phyaddr;
5866 np->phy_oui = id1 | id2;
5868 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5869 if (np->phy_oui == PHY_OUI_REALTEK2)
5870 np->phy_oui = PHY_OUI_REALTEK;
5871 /* Setup phy revision for Realtek */
5872 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5873 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5878 dev_printk(KERN_INFO, &pci_dev->dev,
5879 "open: Could not find a valid PHY.\n");
5883 if (!phyinitialized) {
5887 /* see if it is a gigabit phy */
5888 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5889 if (mii_status & PHY_GIGABIT) {
5890 np->gigabit = PHY_GIGABIT;
5894 /* set default link speed settings */
5895 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5899 err = register_netdev(dev);
5901 dev_printk(KERN_INFO, &pci_dev->dev,
5902 "unable to register netdev: %d\n", err);
5906 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5907 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5918 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5919 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5920 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5922 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5924 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5925 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5926 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5927 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5928 np->need_linktimer ? "lnktim " : "",
5929 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5930 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5937 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5938 pci_set_drvdata(pci_dev, NULL);
5942 iounmap(get_hwbase(dev));
5944 pci_release_regions(pci_dev);
5946 pci_disable_device(pci_dev);
5953 static void nv_restore_phy(struct net_device *dev)
5955 struct fe_priv *np = netdev_priv(dev);
5956 u16 phy_reserved, mii_control;
5958 if (np->phy_oui == PHY_OUI_REALTEK &&
5959 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5960 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5961 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5962 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5963 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5964 phy_reserved |= PHY_REALTEK_INIT8;
5965 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5966 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5968 /* restart auto negotiation */
5969 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5970 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5971 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5975 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5977 struct net_device *dev = pci_get_drvdata(pci_dev);
5978 struct fe_priv *np = netdev_priv(dev);
5979 u8 __iomem *base = get_hwbase(dev);
5981 /* special op: write back the misordered MAC address - otherwise
5982 * the next nv_probe would see a wrong address.
5984 writel(np->orig_mac[0], base + NvRegMacAddrA);
5985 writel(np->orig_mac[1], base + NvRegMacAddrB);
5986 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5987 base + NvRegTransmitPoll);
5990 static void __devexit nv_remove(struct pci_dev *pci_dev)
5992 struct net_device *dev = pci_get_drvdata(pci_dev);
5994 unregister_netdev(dev);
5996 nv_restore_mac_addr(pci_dev);
5998 /* restore any phy related changes */
5999 nv_restore_phy(dev);
6001 nv_mgmt_release_sema(dev);
6003 /* free all structures */
6005 iounmap(get_hwbase(dev));
6006 pci_release_regions(pci_dev);
6007 pci_disable_device(pci_dev);
6009 pci_set_drvdata(pci_dev, NULL);
6013 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6015 struct net_device *dev = pci_get_drvdata(pdev);
6016 struct fe_priv *np = netdev_priv(dev);
6017 u8 __iomem *base = get_hwbase(dev);
6020 if (netif_running(dev)) {
6024 netif_device_detach(dev);
6026 /* save non-pci configuration space */
6027 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6028 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6030 pci_save_state(pdev);
6031 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6032 pci_disable_device(pdev);
6033 pci_set_power_state(pdev, pci_choose_state(pdev, state));
6037 static int nv_resume(struct pci_dev *pdev)
6039 struct net_device *dev = pci_get_drvdata(pdev);
6040 struct fe_priv *np = netdev_priv(dev);
6041 u8 __iomem *base = get_hwbase(dev);
6044 pci_set_power_state(pdev, PCI_D0);
6045 pci_restore_state(pdev);
6046 /* ack any pending wake events, disable PME */
6047 pci_enable_wake(pdev, PCI_D0, 0);
6049 /* restore non-pci configuration space */
6050 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6051 writel(np->saved_config_space[i], base+i*sizeof(u32));
6053 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6055 netif_device_attach(dev);
6056 if (netif_running(dev)) {
6058 nv_set_multicast(dev);
6063 static void nv_shutdown(struct pci_dev *pdev)
6065 struct net_device *dev = pci_get_drvdata(pdev);
6066 struct fe_priv *np = netdev_priv(dev);
6068 if (netif_running(dev))
6072 * Restore the MAC so a kernel started by kexec won't get confused.
6073 * If we really go for poweroff, we must not restore the MAC,
6074 * otherwise the MAC for WOL will be reversed at least on some boards.
6076 if (system_state != SYSTEM_POWER_OFF) {
6077 nv_restore_mac_addr(pdev);
6080 pci_disable_device(pdev);
6082 * Apparently it is not possible to reinitialise from D3 hot,
6083 * only put the device into D3 if we really go for poweroff.
6085 if (system_state == SYSTEM_POWER_OFF) {
6086 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6087 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6088 pci_set_power_state(pdev, PCI_D3hot);
6092 #define nv_suspend NULL
6093 #define nv_shutdown NULL
6094 #define nv_resume NULL
6095 #endif /* CONFIG_PM */
6097 static struct pci_device_id pci_tbl[] = {
6098 { /* nForce Ethernet Controller */
6099 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
6100 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6102 { /* nForce2 Ethernet Controller */
6103 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
6104 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6106 { /* nForce3 Ethernet Controller */
6107 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
6108 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6110 { /* nForce3 Ethernet Controller */
6111 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
6112 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6114 { /* nForce3 Ethernet Controller */
6115 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
6116 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6118 { /* nForce3 Ethernet Controller */
6119 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
6120 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6122 { /* nForce3 Ethernet Controller */
6123 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
6124 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6126 { /* CK804 Ethernet Controller */
6127 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
6128 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6130 { /* CK804 Ethernet Controller */
6131 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
6132 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6134 { /* MCP04 Ethernet Controller */
6135 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
6136 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6138 { /* MCP04 Ethernet Controller */
6139 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
6140 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6142 { /* MCP51 Ethernet Controller */
6143 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
6144 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6146 { /* MCP51 Ethernet Controller */
6147 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
6148 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6150 { /* MCP55 Ethernet Controller */
6151 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
6152 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6154 { /* MCP55 Ethernet Controller */
6155 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
6156 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6158 { /* MCP61 Ethernet Controller */
6159 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
6160 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6162 { /* MCP61 Ethernet Controller */
6163 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
6164 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6166 { /* MCP61 Ethernet Controller */
6167 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
6168 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6170 { /* MCP61 Ethernet Controller */
6171 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
6172 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6174 { /* MCP65 Ethernet Controller */
6175 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
6176 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6178 { /* MCP65 Ethernet Controller */
6179 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
6180 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6182 { /* MCP65 Ethernet Controller */
6183 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
6184 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6186 { /* MCP65 Ethernet Controller */
6187 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
6188 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6190 { /* MCP67 Ethernet Controller */
6191 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
6192 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6194 { /* MCP67 Ethernet Controller */
6195 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
6196 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6198 { /* MCP67 Ethernet Controller */
6199 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
6200 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6202 { /* MCP67 Ethernet Controller */
6203 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
6204 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6206 { /* MCP73 Ethernet Controller */
6207 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
6208 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6210 { /* MCP73 Ethernet Controller */
6211 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
6212 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6214 { /* MCP73 Ethernet Controller */
6215 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
6216 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6218 { /* MCP73 Ethernet Controller */
6219 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
6220 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6222 { /* MCP77 Ethernet Controller */
6223 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6224 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6226 { /* MCP77 Ethernet Controller */
6227 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6228 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6230 { /* MCP77 Ethernet Controller */
6231 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6232 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6234 { /* MCP77 Ethernet Controller */
6235 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6236 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6238 { /* MCP79 Ethernet Controller */
6239 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6240 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6242 { /* MCP79 Ethernet Controller */
6243 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6244 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6246 { /* MCP79 Ethernet Controller */
6247 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6248 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6250 { /* MCP79 Ethernet Controller */
6251 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6252 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6257 static struct pci_driver driver = {
6259 .id_table = pci_tbl,
6261 .remove = __devexit_p(nv_remove),
6262 .suspend = nv_suspend,
6263 .resume = nv_resume,
6264 .shutdown = nv_shutdown,
6267 static int __init init_nic(void)
6269 return pci_register_driver(&driver);
6272 static void __exit exit_nic(void)
6274 pci_unregister_driver(&driver);
6277 module_param(max_interrupt_work, int, 0);
6278 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6279 module_param(optimization_mode, int, 0);
6280 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6281 module_param(poll_interval, int, 0);
6282 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6283 module_param(msi, int, 0);
6284 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6285 module_param(msix, int, 0);
6286 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6287 module_param(dma_64bit, int, 0);
6288 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6289 module_param(phy_cross, int, 0);
6290 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6292 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6293 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6294 MODULE_LICENSE("GPL");
6296 MODULE_DEVICE_TABLE(pci, pci_tbl);
6298 module_init(init_nic);
6299 module_exit(exit_nic);