SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,5,6 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *      0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
 115  *
 116  * Known bugs:
 117  * We suspect that on some hardware no TX done interrupts are generated.
 118  * This means recovery from netif_stop_queue only happens if the hw timer
 119  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 120  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 121  * If your hardware reliably generates tx done interrupts, then you can remove
 122  * DEV_NEED_TIMERIRQ from the driver_data flags.
 123  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 124  * superfluous timer interrupts from the nic.
 125  */
 126 #ifdef CONFIG_FORCEDETH_NAPI
 127 #define DRIVERNAPI "-NAPI"
 128 #else
 129 #define DRIVERNAPI
 130 #endif
 131 #define FORCEDETH_VERSION               "0.60"
 132 #define DRV_NAME                        "forcedeth"
 133
 134 #include <linux/module.h>
 135 #include <linux/types.h>
 136 #include <linux/pci.h>
 137 #include <linux/interrupt.h>
 138 #include <linux/netdevice.h>
 139 #include <linux/etherdevice.h>
 140 #include <linux/delay.h>
 141 #include <linux/spinlock.h>
 142 #include <linux/ethtool.h>
 143 #include <linux/timer.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/mii.h>
 146 #include <linux/random.h>
 147 #include <linux/init.h>
 148 #include <linux/if_vlan.h>
 149 #include <linux/dma-mapping.h>
 150
 151 #include <asm/irq.h>
 152 #include <asm/io.h>
 153 #include <asm/uaccess.h>
 154 #include <asm/system.h>
 155
 156 #if 0
 157 #define dprintk                 printk
 158 #else
 159 #define dprintk(x...)           do { } while (0)
 160 #endif
 161
 162
 163 /*
 164  * Hardware access:
 165  */
 166
 167 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 168 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 169 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 170 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 171 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 172 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 173 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 174 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 175 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 176 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 177 #define DEV_HAS_STATISTICS_V1   0x0400  /* device supports hw statistics version 1 */
 178 #define DEV_HAS_STATISTICS_V2   0x0800  /* device supports hw statistics version 2 */
 179 #define DEV_HAS_TEST_EXTENDED   0x1000  /* device supports extended diagnostic test */
 180 #define DEV_HAS_MGMT_UNIT       0x2000  /* device supports management unit */
 181
 182 enum {
 183         NvRegIrqStatus = 0x000,
 184 #define NVREG_IRQSTAT_MIIEVENT  0x040
 185 #define NVREG_IRQSTAT_MASK              0x81ff
 186         NvRegIrqMask = 0x004,
 187 #define NVREG_IRQ_RX_ERROR              0x0001
 188 #define NVREG_IRQ_RX                    0x0002
 189 #define NVREG_IRQ_RX_NOBUF              0x0004
 190 #define NVREG_IRQ_TX_ERR                0x0008
 191 #define NVREG_IRQ_TX_OK                 0x0010
 192 #define NVREG_IRQ_TIMER                 0x0020
 193 #define NVREG_IRQ_LINK                  0x0040
 194 #define NVREG_IRQ_RX_FORCED             0x0080
 195 #define NVREG_IRQ_TX_FORCED             0x0100
 196 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 197 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 198 #define NVREG_IRQMASK_CPU               0x0040
 199 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 200 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 201 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 202
 203 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 204                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 205                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 206
 207         NvRegUnknownSetupReg6 = 0x008,
 208 #define NVREG_UNKSETUP6_VAL             3
 209
 210 /*
 211  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 212  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 213  */
 214         NvRegPollingInterval = 0x00c,
 215 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 216 #define NVREG_POLL_DEFAULT_CPU  13
 217         NvRegMSIMap0 = 0x020,
 218         NvRegMSIMap1 = 0x024,
 219         NvRegMSIIrqMask = 0x030,
 220 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 221         NvRegMisc1 = 0x080,
 222 #define NVREG_MISC1_PAUSE_TX    0x01
 223 #define NVREG_MISC1_HD          0x02
 224 #define NVREG_MISC1_FORCE       0x3b0f3c
 225
 226         NvRegMacReset = 0x3c,
 227 #define NVREG_MAC_RESET_ASSERT  0x0F3
 228         NvRegTransmitterControl = 0x084,
 229 #define NVREG_XMITCTL_START     0x01
 230 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 231 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 232 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 233 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 234 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 235 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 236 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 237 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 238 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 239 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 240         NvRegTransmitterStatus = 0x088,
 241 #define NVREG_XMITSTAT_BUSY     0x01
 242
 243         NvRegPacketFilterFlags = 0x8c,
 244 #define NVREG_PFF_PAUSE_RX      0x08
 245 #define NVREG_PFF_ALWAYS        0x7F0000
 246 #define NVREG_PFF_PROMISC       0x80
 247 #define NVREG_PFF_MYADDR        0x20
 248 #define NVREG_PFF_LOOPBACK      0x10
 249
 250         NvRegOffloadConfig = 0x90,
 251 #define NVREG_OFFLOAD_HOMEPHY   0x601
 252 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 253         NvRegReceiverControl = 0x094,
 254 #define NVREG_RCVCTL_START      0x01
 255 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 256         NvRegReceiverStatus = 0x98,
 257 #define NVREG_RCVSTAT_BUSY      0x01
 258
 259         NvRegRandomSeed = 0x9c,
 260 #define NVREG_RNDSEED_MASK      0x00ff
 261 #define NVREG_RNDSEED_FORCE     0x7f00
 262 #define NVREG_RNDSEED_FORCE2    0x2d00
 263 #define NVREG_RNDSEED_FORCE3    0x7400
 264
 265         NvRegTxDeferral = 0xA0,
 266 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 267 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 268 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 269         NvRegRxDeferral = 0xA4,
 270 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 271         NvRegMacAddrA = 0xA8,
 272         NvRegMacAddrB = 0xAC,
 273         NvRegMulticastAddrA = 0xB0,
 274 #define NVREG_MCASTADDRA_FORCE  0x01
 275         NvRegMulticastAddrB = 0xB4,
 276         NvRegMulticastMaskA = 0xB8,
 277         NvRegMulticastMaskB = 0xBC,
 278
 279         NvRegPhyInterface = 0xC0,
 280 #define PHY_RGMII               0x10000000
 281
 282         NvRegTxRingPhysAddr = 0x100,
 283         NvRegRxRingPhysAddr = 0x104,
 284         NvRegRingSizes = 0x108,
 285 #define NVREG_RINGSZ_TXSHIFT 0
 286 #define NVREG_RINGSZ_RXSHIFT 16
 287         NvRegTransmitPoll = 0x10c,
 288 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 289         NvRegLinkSpeed = 0x110,
 290 #define NVREG_LINKSPEED_FORCE 0x10000
 291 #define NVREG_LINKSPEED_10      1000
 292 #define NVREG_LINKSPEED_100     100
 293 #define NVREG_LINKSPEED_1000    50
 294 #define NVREG_LINKSPEED_MASK    (0xFFF)
 295         NvRegUnknownSetupReg5 = 0x130,
 296 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 297         NvRegTxWatermark = 0x13c,
 298 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 299 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 300 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 301         NvRegTxRxControl = 0x144,
 302 #define NVREG_TXRXCTL_KICK      0x0001
 303 #define NVREG_TXRXCTL_BIT1      0x0002
 304 #define NVREG_TXRXCTL_BIT2      0x0004
 305 #define NVREG_TXRXCTL_IDLE      0x0008
 306 #define NVREG_TXRXCTL_RESET     0x0010
 307 #define NVREG_TXRXCTL_RXCHECK   0x0400
 308 #define NVREG_TXRXCTL_DESC_1    0
 309 #define NVREG_TXRXCTL_DESC_2    0x002100
 310 #define NVREG_TXRXCTL_DESC_3    0xc02200
 311 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 312 #define NVREG_TXRXCTL_VLANINS   0x00080
 313         NvRegTxRingPhysAddrHigh = 0x148,
 314         NvRegRxRingPhysAddrHigh = 0x14C,
 315         NvRegTxPauseFrame = 0x170,
 316 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 317 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 318         NvRegMIIStatus = 0x180,
 319 #define NVREG_MIISTAT_ERROR             0x0001
 320 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 321 #define NVREG_MIISTAT_MASK              0x000f
 322 #define NVREG_MIISTAT_MASK2             0x000f
 323         NvRegMIIMask = 0x184,
 324 #define NVREG_MII_LINKCHANGE            0x0008
 325
 326         NvRegAdapterControl = 0x188,
 327 #define NVREG_ADAPTCTL_START    0x02
 328 #define NVREG_ADAPTCTL_LINKUP   0x04
 329 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 330 #define NVREG_ADAPTCTL_RUNNING  0x100000
 331 #define NVREG_ADAPTCTL_PHYSHIFT 24
 332         NvRegMIISpeed = 0x18c,
 333 #define NVREG_MIISPEED_BIT8     (1<<8)
 334 #define NVREG_MIIDELAY  5
 335         NvRegMIIControl = 0x190,
 336 #define NVREG_MIICTL_INUSE      0x08000
 337 #define NVREG_MIICTL_WRITE      0x00400
 338 #define NVREG_MIICTL_ADDRSHIFT  5
 339         NvRegMIIData = 0x194,
 340         NvRegWakeUpFlags = 0x200,
 341 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 342 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 343 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 344 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 345 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 346 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 347 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 348 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 349 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 350 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 351 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 352
 353         NvRegPatternCRC = 0x204,
 354         NvRegPatternMask = 0x208,
 355         NvRegPowerCap = 0x268,
 356 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 357 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 358 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 359         NvRegPowerState = 0x26c,
 360 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 361 #define NVREG_POWERSTATE_VALID          0x0100
 362 #define NVREG_POWERSTATE_MASK           0x0003
 363 #define NVREG_POWERSTATE_D0             0x0000
 364 #define NVREG_POWERSTATE_D1             0x0001
 365 #define NVREG_POWERSTATE_D2             0x0002
 366 #define NVREG_POWERSTATE_D3             0x0003
 367         NvRegTxCnt = 0x280,
 368         NvRegTxZeroReXmt = 0x284,
 369         NvRegTxOneReXmt = 0x288,
 370         NvRegTxManyReXmt = 0x28c,
 371         NvRegTxLateCol = 0x290,
 372         NvRegTxUnderflow = 0x294,
 373         NvRegTxLossCarrier = 0x298,
 374         NvRegTxExcessDef = 0x29c,
 375         NvRegTxRetryErr = 0x2a0,
 376         NvRegRxFrameErr = 0x2a4,
 377         NvRegRxExtraByte = 0x2a8,
 378         NvRegRxLateCol = 0x2ac,
 379         NvRegRxRunt = 0x2b0,
 380         NvRegRxFrameTooLong = 0x2b4,
 381         NvRegRxOverflow = 0x2b8,
 382         NvRegRxFCSErr = 0x2bc,
 383         NvRegRxFrameAlignErr = 0x2c0,
 384         NvRegRxLenErr = 0x2c4,
 385         NvRegRxUnicast = 0x2c8,
 386         NvRegRxMulticast = 0x2cc,
 387         NvRegRxBroadcast = 0x2d0,
 388         NvRegTxDef = 0x2d4,
 389         NvRegTxFrame = 0x2d8,
 390         NvRegRxCnt = 0x2dc,
 391         NvRegTxPause = 0x2e0,
 392         NvRegRxPause = 0x2e4,
 393         NvRegRxDropFrame = 0x2e8,
 394         NvRegVlanControl = 0x300,
 395 #define NVREG_VLANCONTROL_ENABLE        0x2000
 396         NvRegMSIXMap0 = 0x3e0,
 397         NvRegMSIXMap1 = 0x3e4,
 398         NvRegMSIXIrqStatus = 0x3f0,
 399
 400         NvRegPowerState2 = 0x600,
 401 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 402 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 403 };
 404
 405 /* Big endian: should work, but is untested */
 406 struct ring_desc {
 407         __le32 buf;
 408         __le32 flaglen;
 409 };
 410
 411 struct ring_desc_ex {
 412         __le32 bufhigh;
 413         __le32 buflow;
 414         __le32 txvlan;
 415         __le32 flaglen;
 416 };
 417
 418 union ring_type {
 419         struct ring_desc* orig;
 420         struct ring_desc_ex* ex;
 421 };
 422
 423 #define FLAG_MASK_V1 0xffff0000
 424 #define FLAG_MASK_V2 0xffffc000
 425 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 426 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 427
 428 #define NV_TX_LASTPACKET        (1<<16)
 429 #define NV_TX_RETRYERROR        (1<<19)
 430 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 431 #define NV_TX_DEFERRED          (1<<26)
 432 #define NV_TX_CARRIERLOST       (1<<27)
 433 #define NV_TX_LATECOLLISION     (1<<28)
 434 #define NV_TX_UNDERFLOW         (1<<29)
 435 #define NV_TX_ERROR             (1<<30)
 436 #define NV_TX_VALID             (1<<31)
 437
 438 #define NV_TX2_LASTPACKET       (1<<29)
 439 #define NV_TX2_RETRYERROR       (1<<18)
 440 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 441 #define NV_TX2_DEFERRED         (1<<25)
 442 #define NV_TX2_CARRIERLOST      (1<<26)
 443 #define NV_TX2_LATECOLLISION    (1<<27)
 444 #define NV_TX2_UNDERFLOW        (1<<28)
 445 /* error and valid are the same for both */
 446 #define NV_TX2_ERROR            (1<<30)
 447 #define NV_TX2_VALID            (1<<31)
 448 #define NV_TX2_TSO              (1<<28)
 449 #define NV_TX2_TSO_SHIFT        14
 450 #define NV_TX2_TSO_MAX_SHIFT    14
 451 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 452 #define NV_TX2_CHECKSUM_L3      (1<<27)
 453 #define NV_TX2_CHECKSUM_L4      (1<<26)
 454
 455 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 456
 457 #define NV_RX_DESCRIPTORVALID   (1<<16)
 458 #define NV_RX_MISSEDFRAME       (1<<17)
 459 #define NV_RX_SUBSTRACT1        (1<<18)
 460 #define NV_RX_ERROR1            (1<<23)
 461 #define NV_RX_ERROR2            (1<<24)
 462 #define NV_RX_ERROR3            (1<<25)
 463 #define NV_RX_ERROR4            (1<<26)
 464 #define NV_RX_CRCERR            (1<<27)
 465 #define NV_RX_OVERFLOW          (1<<28)
 466 #define NV_RX_FRAMINGERR        (1<<29)
 467 #define NV_RX_ERROR             (1<<30)
 468 #define NV_RX_AVAIL             (1<<31)
 469
 470 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 471 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 472 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 473 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 474 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 475 #define NV_RX2_SUBSTRACT1       (1<<25)
 476 #define NV_RX2_ERROR1           (1<<18)
 477 #define NV_RX2_ERROR2           (1<<19)
 478 #define NV_RX2_ERROR3           (1<<20)
 479 #define NV_RX2_ERROR4           (1<<21)
 480 #define NV_RX2_CRCERR           (1<<22)
 481 #define NV_RX2_OVERFLOW         (1<<23)
 482 #define NV_RX2_FRAMINGERR       (1<<24)
 483 /* error and avail are the same for both */
 484 #define NV_RX2_ERROR            (1<<30)
 485 #define NV_RX2_AVAIL            (1<<31)
 486
 487 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 488 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 489
 490 /* Miscelaneous hardware related defines: */
 491 #define NV_PCI_REGSZ_VER1       0x270
 492 #define NV_PCI_REGSZ_VER2       0x2d4
 493 #define NV_PCI_REGSZ_VER3       0x604
 494
 495 /* various timeout delays: all in usec */
 496 #define NV_TXRX_RESET_DELAY     4
 497 #define NV_TXSTOP_DELAY1        10
 498 #define NV_TXSTOP_DELAY1MAX     500000
 499 #define NV_TXSTOP_DELAY2        100
 500 #define NV_RXSTOP_DELAY1        10
 501 #define NV_RXSTOP_DELAY1MAX     500000
 502 #define NV_RXSTOP_DELAY2        100
 503 #define NV_SETUP5_DELAY         5
 504 #define NV_SETUP5_DELAYMAX      50000
 505 #define NV_POWERUP_DELAY        5
 506 #define NV_POWERUP_DELAYMAX     5000
 507 #define NV_MIIBUSY_DELAY        50
 508 #define NV_MIIPHY_DELAY 10
 509 #define NV_MIIPHY_DELAYMAX      10000
 510 #define NV_MAC_RESET_DELAY      64
 511
 512 #define NV_WAKEUPPATTERNS       5
 513 #define NV_WAKEUPMASKENTRIES    4
 514
 515 /* General driver defaults */
 516 #define NV_WATCHDOG_TIMEO       (5*HZ)
 517
 518 #define RX_RING_DEFAULT         128
 519 #define TX_RING_DEFAULT         256
 520 #define RX_RING_MIN             128
 521 #define TX_RING_MIN             64
 522 #define RING_MAX_DESC_VER_1     1024
 523 #define RING_MAX_DESC_VER_2_3   16384
 524
 525 /* rx/tx mac addr + type + vlan + align + slack*/
 526 #define NV_RX_HEADERS           (64)
 527 /* even more slack. */
 528 #define NV_RX_ALLOC_PAD         (64)
 529
 530 /* maximum mtu size */
 531 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 532 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 533
 534 #define OOM_REFILL      (1+HZ/20)
 535 #define POLL_WAIT       (1+HZ/100)
 536 #define LINK_TIMEOUT    (3*HZ)
 537 #define STATS_INTERVAL  (10*HZ)
 538
 539 /*
 540  * desc_ver values:
 541  * The nic supports three different descriptor types:
 542  * - DESC_VER_1: Original
 543  * - DESC_VER_2: support for jumbo frames.
 544  * - DESC_VER_3: 64-bit format.
 545  */
 546 #define DESC_VER_1      1
 547 #define DESC_VER_2      2
 548 #define DESC_VER_3      3
 549
 550 /* PHY defines */
 551 #define PHY_OUI_MARVELL 0x5043
 552 #define PHY_OUI_CICADA  0x03f1
 553 #define PHYID1_OUI_MASK 0x03ff
 554 #define PHYID1_OUI_SHFT 6
 555 #define PHYID2_OUI_MASK 0xfc00
 556 #define PHYID2_OUI_SHFT 10
 557 #define PHYID2_MODEL_MASK               0x03f0
 558 #define PHY_MODEL_MARVELL_E3016         0x220
 559 #define PHY_MARVELL_E3016_INITMASK      0x0300
 560 #define PHY_INIT1       0x0f000
 561 #define PHY_INIT2       0x0e00
 562 #define PHY_INIT3       0x01000
 563 #define PHY_INIT4       0x0200
 564 #define PHY_INIT5       0x0004
 565 #define PHY_INIT6       0x02000
 566 #define PHY_GIGABIT     0x0100
 567
 568 #define PHY_TIMEOUT     0x1
 569 #define PHY_ERROR       0x2
 570
 571 #define PHY_100 0x1
 572 #define PHY_1000        0x2
 573 #define PHY_HALF        0x100
 574
 575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 577 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 578 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 579 #define NV_PAUSEFRAME_RX_REQ     0x0010
 580 #define NV_PAUSEFRAME_TX_REQ     0x0020
 581 #define NV_PAUSEFRAME_AUTONEG    0x0040
 582
 583 /* MSI/MSI-X defines */
 584 #define NV_MSI_X_MAX_VECTORS  8
 585 #define NV_MSI_X_VECTORS_MASK 0x000f
 586 #define NV_MSI_CAPABLE        0x0010
 587 #define NV_MSI_X_CAPABLE      0x0020
 588 #define NV_MSI_ENABLED        0x0040
 589 #define NV_MSI_X_ENABLED      0x0080
 590
 591 #define NV_MSI_X_VECTOR_ALL   0x0
 592 #define NV_MSI_X_VECTOR_RX    0x0
 593 #define NV_MSI_X_VECTOR_TX    0x1
 594 #define NV_MSI_X_VECTOR_OTHER 0x2
 595
 596 /* statistics */
 597 struct nv_ethtool_str {
 598         char name[ETH_GSTRING_LEN];
 599 };
 600
 601 static const struct nv_ethtool_str nv_estats_str[] = {
 602         { "tx_bytes" },
 603         { "tx_zero_rexmt" },
 604         { "tx_one_rexmt" },
 605         { "tx_many_rexmt" },
 606         { "tx_late_collision" },
 607         { "tx_fifo_errors" },
 608         { "tx_carrier_errors" },
 609         { "tx_excess_deferral" },
 610         { "tx_retry_error" },
 611         { "rx_frame_error" },
 612         { "rx_extra_byte" },
 613         { "rx_late_collision" },
 614         { "rx_runt" },
 615         { "rx_frame_too_long" },
 616         { "rx_over_errors" },
 617         { "rx_crc_errors" },
 618         { "rx_frame_align_error" },
 619         { "rx_length_error" },
 620         { "rx_unicast" },
 621         { "rx_multicast" },
 622         { "rx_broadcast" },
 623         { "rx_packets" },
 624         { "rx_errors_total" },
 625         { "tx_errors_total" },
 626
 627         /* version 2 stats */
 628         { "tx_deferral" },
 629         { "tx_packets" },
 630         { "rx_bytes" },
 631         { "tx_pause" },
 632         { "rx_pause" },
 633         { "rx_drop_frame" }
 634 };
 635
 636 struct nv_ethtool_stats {
 637         u64 tx_bytes;
 638         u64 tx_zero_rexmt;
 639         u64 tx_one_rexmt;
 640         u64 tx_many_rexmt;
 641         u64 tx_late_collision;
 642         u64 tx_fifo_errors;
 643         u64 tx_carrier_errors;
 644         u64 tx_excess_deferral;
 645         u64 tx_retry_error;
 646         u64 rx_frame_error;
 647         u64 rx_extra_byte;
 648         u64 rx_late_collision;
 649         u64 rx_runt;
 650         u64 rx_frame_too_long;
 651         u64 rx_over_errors;
 652         u64 rx_crc_errors;
 653         u64 rx_frame_align_error;
 654         u64 rx_length_error;
 655         u64 rx_unicast;
 656         u64 rx_multicast;
 657         u64 rx_broadcast;
 658         u64 rx_packets;
 659         u64 rx_errors_total;
 660         u64 tx_errors_total;
 661
 662         /* version 2 stats */
 663         u64 tx_deferral;
 664         u64 tx_packets;
 665         u64 rx_bytes;
 666         u64 tx_pause;
 667         u64 rx_pause;
 668         u64 rx_drop_frame;
 669 };
 670
 671 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 672 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 673
 674 /* diagnostics */
 675 #define NV_TEST_COUNT_BASE 3
 676 #define NV_TEST_COUNT_EXTENDED 4
 677
 678 static const struct nv_ethtool_str nv_etests_str[] = {
 679         { "link      (online/offline)" },
 680         { "register  (offline)       " },
 681         { "interrupt (offline)       " },
 682         { "loopback  (offline)       " }
 683 };
 684
 685 struct register_test {
 686         __le32 reg;
 687         __le32 mask;
 688 };
 689
 690 static const struct register_test nv_registers_test[] = {
 691         { NvRegUnknownSetupReg6, 0x01 },
 692         { NvRegMisc1, 0x03c },
 693         { NvRegOffloadConfig, 0x03ff },
 694         { NvRegMulticastAddrA, 0xffffffff },
 695         { NvRegTxWatermark, 0x0ff },
 696         { NvRegWakeUpFlags, 0x07777 },
 697         { 0,0 }
 698 };
 699
 700 struct nv_skb_map {
 701         struct sk_buff *skb;
 702         dma_addr_t dma;
 703         unsigned int dma_len;
 704 };
 705
 706 /*
 707  * SMP locking:
 708  * All hardware access under dev->priv->lock, except the performance
 709  * critical parts:
 710  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 711  *      by the arch code for interrupts.
 712  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 713  *      needs dev->priv->lock :-(
 714  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 715  */
 716
 717 /* in dev: base, irq */
 718 struct fe_priv {
 719         spinlock_t lock;
 720
 721         /* General data:
 722          * Locking: spin_lock(&np->lock); */
 723         struct net_device_stats stats;
 724         struct nv_ethtool_stats estats;
 725         int in_shutdown;
 726         u32 linkspeed;
 727         int duplex;
 728         int autoneg;
 729         int fixed_mode;
 730         int phyaddr;
 731         int wolenabled;
 732         unsigned int phy_oui;
 733         unsigned int phy_model;
 734         u16 gigabit;
 735         int intr_test;
 736         int recover_error;
 737
 738         /* General data: RO fields */
 739         dma_addr_t ring_addr;
 740         struct pci_dev *pci_dev;
 741         u32 orig_mac[2];
 742         u32 irqmask;
 743         u32 desc_ver;
 744         u32 txrxctl_bits;
 745         u32 vlanctl_bits;
 746         u32 driver_data;
 747         u32 register_size;
 748         int rx_csum;
 749         u32 mac_in_use;
 750
 751         void __iomem *base;
 752
 753         /* rx specific fields.
 754          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 755          */
 756         union ring_type get_rx, put_rx, first_rx, last_rx;
 757         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 758         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 759         struct nv_skb_map *rx_skb;
 760
 761         union ring_type rx_ring;
 762         unsigned int rx_buf_sz;
 763         unsigned int pkt_limit;
 764         struct timer_list oom_kick;
 765         struct timer_list nic_poll;
 766         struct timer_list stats_poll;
 767         u32 nic_poll_irq;
 768         int rx_ring_size;
 769
 770         /* media detection workaround.
 771          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 772          */
 773         int need_linktimer;
 774         unsigned long link_timeout;
 775         /*
 776          * tx specific fields.
 777          */
 778         union ring_type get_tx, put_tx, first_tx, last_tx;
 779         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 780         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 781         struct nv_skb_map *tx_skb;
 782
 783         union ring_type tx_ring;
 784         u32 tx_flags;
 785         int tx_ring_size;
 786         int tx_stop;
 787
 788         /* vlan fields */
 789         struct vlan_group *vlangrp;
 790
 791         /* msi/msi-x fields */
 792         u32 msi_flags;
 793         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 794
 795         /* flow control */
 796         u32 pause_flags;
 797 };
 798
 799 /*
 800  * Maximum number of loops until we assume that a bit in the irq mask
 801  * is stuck. Overridable with module param.
 802  */
 803 static int max_interrupt_work = 5;
 804
 805 /*
 806  * Optimization can be either throuput mode or cpu mode
 807  *
 808  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 809  * CPU Mode: Interrupts are controlled by a timer.
 810  */
 811 enum {
 812         NV_OPTIMIZATION_MODE_THROUGHPUT,
 813         NV_OPTIMIZATION_MODE_CPU
 814 };
 815 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 816
 817 /*
 818  * Poll interval for timer irq
 819  *
 820  * This interval determines how frequent an interrupt is generated.
 821  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 822  * Min = 0, and Max = 65535
 823  */
 824 static int poll_interval = -1;
 825
 826 /*
 827  * MSI interrupts
 828  */
 829 enum {
 830         NV_MSI_INT_DISABLED,
 831         NV_MSI_INT_ENABLED
 832 };
 833 static int msi = NV_MSI_INT_ENABLED;
 834
 835 /*
 836  * MSIX interrupts
 837  */
 838 enum {
 839         NV_MSIX_INT_DISABLED,
 840         NV_MSIX_INT_ENABLED
 841 };
 842 static int msix = NV_MSIX_INT_DISABLED;
 843
 844 /*
 845  * DMA 64bit
 846  */
 847 enum {
 848         NV_DMA_64BIT_DISABLED,
 849         NV_DMA_64BIT_ENABLED
 850 };
 851 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 852
 853 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 854 {
 855         return netdev_priv(dev);
 856 }
 857
 858 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 859 {
 860         return ((struct fe_priv *)netdev_priv(dev))->base;
 861 }
 862
 863 static inline void pci_push(u8 __iomem *base)
 864 {
 865         /* force out pending posted writes */
 866         readl(base);
 867 }
 868
 869 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 870 {
 871         return le32_to_cpu(prd->flaglen)
 872                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 873 }
 874
 875 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 876 {
 877         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 878 }
 879
 880 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 881                                 int delay, int delaymax, const char *msg)
 882 {
 883         u8 __iomem *base = get_hwbase(dev);
 884
 885         pci_push(base);
 886         do {
 887                 udelay(delay);
 888                 delaymax -= delay;
 889                 if (delaymax < 0) {
 890                         if (msg)
 891                                 printk(msg);
 892                         return 1;
 893                 }
 894         } while ((readl(base + offset) & mask) != target);
 895         return 0;
 896 }
 897
 898 #define NV_SETUP_RX_RING 0x01
 899 #define NV_SETUP_TX_RING 0x02
 900
 901 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 902 {
 903         struct fe_priv *np = get_nvpriv(dev);
 904         u8 __iomem *base = get_hwbase(dev);
 905
 906         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 907                 if (rxtx_flags & NV_SETUP_RX_RING) {
 908                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 909                 }
 910                 if (rxtx_flags & NV_SETUP_TX_RING) {
 911                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 912                 }
 913         } else {
 914                 if (rxtx_flags & NV_SETUP_RX_RING) {
 915                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 916                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 917                 }
 918                 if (rxtx_flags & NV_SETUP_TX_RING) {
 919                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 920                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 921                 }
 922         }
 923 }
 924
 925 static void free_rings(struct net_device *dev)
 926 {
 927         struct fe_priv *np = get_nvpriv(dev);
 928
 929         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 930                 if (np->rx_ring.orig)
 931                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 932                                             np->rx_ring.orig, np->ring_addr);
 933         } else {
 934                 if (np->rx_ring.ex)
 935                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 936                                             np->rx_ring.ex, np->ring_addr);
 937         }
 938         if (np->rx_skb)
 939                 kfree(np->rx_skb);
 940         if (np->tx_skb)
 941                 kfree(np->tx_skb);
 942 }
 943
 944 static int using_multi_irqs(struct net_device *dev)
 945 {
 946         struct fe_priv *np = get_nvpriv(dev);
 947
 948         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 949             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 950              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 951                 return 0;
 952         else
 953                 return 1;
 954 }
 955
 956 static void nv_enable_irq(struct net_device *dev)
 957 {
 958         struct fe_priv *np = get_nvpriv(dev);
 959
 960         if (!using_multi_irqs(dev)) {
 961                 if (np->msi_flags & NV_MSI_X_ENABLED)
 962                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 963                 else
 964                         enable_irq(dev->irq);
 965         } else {
 966                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 967                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 968                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 969         }
 970 }
 971
 972 static void nv_disable_irq(struct net_device *dev)
 973 {
 974         struct fe_priv *np = get_nvpriv(dev);
 975
 976         if (!using_multi_irqs(dev)) {
 977                 if (np->msi_flags & NV_MSI_X_ENABLED)
 978                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 979                 else
 980                         disable_irq(dev->irq);
 981         } else {
 982                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 983                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 984                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 985         }
 986 }
 987
 988 /* In MSIX mode, a write to irqmask behaves as XOR */
 989 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 990 {
 991         u8 __iomem *base = get_hwbase(dev);
 992
 993         writel(mask, base + NvRegIrqMask);
 994 }
 995
 996 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 997 {
 998         struct fe_priv *np = get_nvpriv(dev);
 999         u8 __iomem *base = get_hwbase(dev);
1000
1001         if (np->msi_flags & NV_MSI_X_ENABLED) {
1002                 writel(mask, base + NvRegIrqMask);
1003         } else {
1004                 if (np->msi_flags & NV_MSI_ENABLED)
1005                         writel(0, base + NvRegMSIIrqMask);
1006                 writel(0, base + NvRegIrqMask);
1007         }
1008 }
1009
1010 #define MII_READ        (-1)
1011 /* mii_rw: read/write a register on the PHY.
1012  *
1013  * Caller must guarantee serialization
1014  */
1015 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1016 {
1017         u8 __iomem *base = get_hwbase(dev);
1018         u32 reg;
1019         int retval;
1020
1021         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1022
1023         reg = readl(base + NvRegMIIControl);
1024         if (reg & NVREG_MIICTL_INUSE) {
1025                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1026                 udelay(NV_MIIBUSY_DELAY);
1027         }
1028
1029         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1030         if (value != MII_READ) {
1031                 writel(value, base + NvRegMIIData);
1032                 reg |= NVREG_MIICTL_WRITE;
1033         }
1034         writel(reg, base + NvRegMIIControl);
1035
1036         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1037                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1038                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1039                                 dev->name, miireg, addr);
1040                 retval = -1;
1041         } else if (value != MII_READ) {
1042                 /* it was a write operation - fewer failures are detectable */
1043                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1044                                 dev->name, value, miireg, addr);
1045                 retval = 0;
1046         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1047                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1048                                 dev->name, miireg, addr);
1049                 retval = -1;
1050         } else {
1051                 retval = readl(base + NvRegMIIData);
1052                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1053                                 dev->name, miireg, addr, retval);
1054         }
1055
1056         return retval;
1057 }
1058
1059 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1060 {
1061         struct fe_priv *np = netdev_priv(dev);
1062         u32 miicontrol;
1063         unsigned int tries = 0;
1064
1065         miicontrol = BMCR_RESET | bmcr_setup;
1066         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1067                 return -1;
1068         }
1069
1070         /* wait for 500ms */
1071         msleep(500);
1072
1073         /* must wait till reset is deasserted */
1074         while (miicontrol & BMCR_RESET) {
1075                 msleep(10);
1076                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1077                 /* FIXME: 100 tries seem excessive */
1078                 if (tries++ > 100)
1079                         return -1;
1080         }
1081         return 0;
1082 }
1083
1084 static int phy_init(struct net_device *dev)
1085 {
1086         struct fe_priv *np = get_nvpriv(dev);
1087         u8 __iomem *base = get_hwbase(dev);
1088         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1089
1090         /* phy errata for E3016 phy */
1091         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1092                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1093                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1094                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1095                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1096                         return PHY_ERROR;
1097                 }
1098         }
1099
1100         /* set advertise register */
1101         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1102         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1103         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1104                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1105                 return PHY_ERROR;
1106         }
1107
1108         /* get phy interface type */
1109         phyinterface = readl(base + NvRegPhyInterface);
1110
1111         /* see if gigabit phy */
1112         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1113         if (mii_status & PHY_GIGABIT) {
1114                 np->gigabit = PHY_GIGABIT;
1115                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1116                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1117                 if (phyinterface & PHY_RGMII)
1118                         mii_control_1000 |= ADVERTISE_1000FULL;
1119                 else
1120                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1121
1122                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1123                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1124                         return PHY_ERROR;
1125                 }
1126         }
1127         else
1128                 np->gigabit = 0;
1129
1130         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1131         mii_control |= BMCR_ANENABLE;
1132
1133         /* reset the phy
1134          * (certain phys need bmcr to be setup with reset)
1135          */
1136         if (phy_reset(dev, mii_control)) {
1137                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1138                 return PHY_ERROR;
1139         }
1140
1141         /* phy vendor specific configuration */
1142         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1143                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1144                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1145                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1146                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1147                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1148                         return PHY_ERROR;
1149                 }
1150                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1151                 phy_reserved |= PHY_INIT5;
1152                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1153                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1154                         return PHY_ERROR;
1155                 }
1156         }
1157         if (np->phy_oui == PHY_OUI_CICADA) {
1158                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1159                 phy_reserved |= PHY_INIT6;
1160                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1161                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1162                         return PHY_ERROR;
1163                 }
1164         }
1165         /* some phys clear out pause advertisment on reset, set it back */
1166         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1167
1168         /* restart auto negotiation */
1169         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1170         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1171         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1172                 return PHY_ERROR;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static void nv_start_rx(struct net_device *dev)
1179 {
1180         struct fe_priv *np = netdev_priv(dev);
1181         u8 __iomem *base = get_hwbase(dev);
1182         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1183
1184         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1185         /* Already running? Stop it. */
1186         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1187                 rx_ctrl &= ~NVREG_RCVCTL_START;
1188                 writel(rx_ctrl, base + NvRegReceiverControl);
1189                 pci_push(base);
1190         }
1191         writel(np->linkspeed, base + NvRegLinkSpeed);
1192         pci_push(base);
1193         rx_ctrl |= NVREG_RCVCTL_START;
1194         if (np->mac_in_use)
1195                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1196         writel(rx_ctrl, base + NvRegReceiverControl);
1197         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1198                                 dev->name, np->duplex, np->linkspeed);
1199         pci_push(base);
1200 }
1201
1202 static void nv_stop_rx(struct net_device *dev)
1203 {
1204         struct fe_priv *np = netdev_priv(dev);
1205         u8 __iomem *base = get_hwbase(dev);
1206         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1207
1208         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1209         if (!np->mac_in_use)
1210                 rx_ctrl &= ~NVREG_RCVCTL_START;
1211         else
1212                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1213         writel(rx_ctrl, base + NvRegReceiverControl);
1214         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1215                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1216                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1217
1218         udelay(NV_RXSTOP_DELAY2);
1219         if (!np->mac_in_use)
1220                 writel(0, base + NvRegLinkSpeed);
1221 }
1222
1223 static void nv_start_tx(struct net_device *dev)
1224 {
1225         struct fe_priv *np = netdev_priv(dev);
1226         u8 __iomem *base = get_hwbase(dev);
1227         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1228
1229         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1230         tx_ctrl |= NVREG_XMITCTL_START;
1231         if (np->mac_in_use)
1232                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1233         writel(tx_ctrl, base + NvRegTransmitterControl);
1234         pci_push(base);
1235 }
1236
1237 static void nv_stop_tx(struct net_device *dev)
1238 {
1239         struct fe_priv *np = netdev_priv(dev);
1240         u8 __iomem *base = get_hwbase(dev);
1241         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1242
1243         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1244         if (!np->mac_in_use)
1245                 tx_ctrl &= ~NVREG_XMITCTL_START;
1246         else
1247                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1248         writel(tx_ctrl, base + NvRegTransmitterControl);
1249         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1250                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1251                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1252
1253         udelay(NV_TXSTOP_DELAY2);
1254         if (!np->mac_in_use)
1255                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1256                        base + NvRegTransmitPoll);
1257 }
1258
1259 static void nv_txrx_reset(struct net_device *dev)
1260 {
1261         struct fe_priv *np = netdev_priv(dev);
1262         u8 __iomem *base = get_hwbase(dev);
1263
1264         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1265         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1266         pci_push(base);
1267         udelay(NV_TXRX_RESET_DELAY);
1268         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1269         pci_push(base);
1270 }
1271
1272 static void nv_mac_reset(struct net_device *dev)
1273 {
1274         struct fe_priv *np = netdev_priv(dev);
1275         u8 __iomem *base = get_hwbase(dev);
1276
1277         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1278         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1279         pci_push(base);
1280         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1281         pci_push(base);
1282         udelay(NV_MAC_RESET_DELAY);
1283         writel(0, base + NvRegMacReset);
1284         pci_push(base);
1285         udelay(NV_MAC_RESET_DELAY);
1286         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1287         pci_push(base);
1288 }
1289
1290 static void nv_get_hw_stats(struct net_device *dev)
1291 {
1292         struct fe_priv *np = netdev_priv(dev);
1293         u8 __iomem *base = get_hwbase(dev);
1294
1295         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1296         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1297         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1298         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1299         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1300         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1301         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1302         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1303         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1304         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1305         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1306         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1307         np->estats.rx_runt += readl(base + NvRegRxRunt);
1308         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1309         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1310         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1311         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1312         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1313         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1314         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1315         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1316         np->estats.rx_packets =
1317                 np->estats.rx_unicast +
1318                 np->estats.rx_multicast +
1319                 np->estats.rx_broadcast;
1320         np->estats.rx_errors_total =
1321                 np->estats.rx_crc_errors +
1322                 np->estats.rx_over_errors +
1323                 np->estats.rx_frame_error +
1324                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1325                 np->estats.rx_late_collision +
1326                 np->estats.rx_runt +
1327                 np->estats.rx_frame_too_long;
1328         np->estats.tx_errors_total =
1329                 np->estats.tx_late_collision +
1330                 np->estats.tx_fifo_errors +
1331                 np->estats.tx_carrier_errors +
1332                 np->estats.tx_excess_deferral +
1333                 np->estats.tx_retry_error;
1334
1335         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1336                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1337                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1338                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1339                 np->estats.tx_pause += readl(base + NvRegTxPause);
1340                 np->estats.rx_pause += readl(base + NvRegRxPause);
1341                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1342         }
1343 }
1344
1345 /*
1346  * nv_get_stats: dev->get_stats function
1347  * Get latest stats value from the nic.
1348  * Called with read_lock(&dev_base_lock) held for read -
1349  * only synchronized against unregister_netdevice.
1350  */
1351 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1352 {
1353         struct fe_priv *np = netdev_priv(dev);
1354
1355         /* If the nic supports hw counters then retrieve latest values */
1356         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1357                 nv_get_hw_stats(dev);
1358
1359                 /* copy to net_device stats */
1360                 np->stats.tx_bytes = np->estats.tx_bytes;
1361                 np->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1362                 np->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1363                 np->stats.rx_crc_errors = np->estats.rx_crc_errors;
1364                 np->stats.rx_over_errors = np->estats.rx_over_errors;
1365                 np->stats.rx_errors = np->estats.rx_errors_total;
1366                 np->stats.tx_errors = np->estats.tx_errors_total;
1367         }
1368         return &np->stats;
1369 }
1370
1371 /*
1372  * nv_alloc_rx: fill rx ring entries.
1373  * Return 1 if the allocations for the skbs failed and the
1374  * rx engine is without Available descriptors
1375  */
1376 static int nv_alloc_rx(struct net_device *dev)
1377 {
1378         struct fe_priv *np = netdev_priv(dev);
1379         struct ring_desc* less_rx;
1380
1381         less_rx = np->get_rx.orig;
1382         if (less_rx-- == np->first_rx.orig)
1383                 less_rx = np->last_rx.orig;
1384
1385         while (np->put_rx.orig != less_rx) {
1386                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1387                 if (skb) {
1388                         np->put_rx_ctx->skb = skb;
1389                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1390                                                              skb->data,
1391                                                         (skb_end_pointer(skb) -
1392                                                          skb->data),
1393                                                              PCI_DMA_FROMDEVICE);
1394                         np->put_rx_ctx->dma_len = (skb_end_pointer(skb) -
1395                                                    skb->data);
1396                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1397                         wmb();
1398                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1399                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1400                                 np->put_rx.orig = np->first_rx.orig;
1401                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1402                                 np->put_rx_ctx = np->first_rx_ctx;
1403                 } else {
1404                         return 1;
1405                 }
1406         }
1407         return 0;
1408 }
1409
1410 static int nv_alloc_rx_optimized(struct net_device *dev)
1411 {
1412         struct fe_priv *np = netdev_priv(dev);
1413         struct ring_desc_ex* less_rx;
1414
1415         less_rx = np->get_rx.ex;
1416         if (less_rx-- == np->first_rx.ex)
1417                 less_rx = np->last_rx.ex;
1418
1419         while (np->put_rx.ex != less_rx) {
1420                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1421                 if (skb) {
1422                         np->put_rx_ctx->skb = skb;
1423                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1424                                                              skb->data,
1425                                                              (skb_end_pointer(skb) -
1426                                                               skb->data),
1427                                                              PCI_DMA_FROMDEVICE);
1428                         np->put_rx_ctx->dma_len = (skb_end_pointer(skb) -
1429                                                    skb->data);
1430                         np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1431                         np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1432                         wmb();
1433                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1434                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1435                                 np->put_rx.ex = np->first_rx.ex;
1436                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1437                                 np->put_rx_ctx = np->first_rx_ctx;
1438                 } else {
1439                         return 1;
1440                 }
1441         }
1442         return 0;
1443 }
1444
1445 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1446 #ifdef CONFIG_FORCEDETH_NAPI
1447 static void nv_do_rx_refill(unsigned long data)
1448 {
1449         struct net_device *dev = (struct net_device *) data;
1450
1451         /* Just reschedule NAPI rx processing */
1452         netif_rx_schedule(dev);
1453 }
1454 #else
1455 static void nv_do_rx_refill(unsigned long data)
1456 {
1457         struct net_device *dev = (struct net_device *) data;
1458         struct fe_priv *np = netdev_priv(dev);
1459         int retcode;
1460
1461         if (!using_multi_irqs(dev)) {
1462                 if (np->msi_flags & NV_MSI_X_ENABLED)
1463                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1464                 else
1465                         disable_irq(dev->irq);
1466         } else {
1467                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1468         }
1469         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1470                 retcode = nv_alloc_rx(dev);
1471         else
1472                 retcode = nv_alloc_rx_optimized(dev);
1473         if (retcode) {
1474                 spin_lock_irq(&np->lock);
1475                 if (!np->in_shutdown)
1476                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1477                 spin_unlock_irq(&np->lock);
1478         }
1479         if (!using_multi_irqs(dev)) {
1480                 if (np->msi_flags & NV_MSI_X_ENABLED)
1481                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1482                 else
1483                         enable_irq(dev->irq);
1484         } else {
1485                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1486         }
1487 }
1488 #endif
1489
1490 static void nv_init_rx(struct net_device *dev)
1491 {
1492         struct fe_priv *np = netdev_priv(dev);
1493         int i;
1494         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1495         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1496                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1497         else
1498                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1499         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1500         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1501
1502         for (i = 0; i < np->rx_ring_size; i++) {
1503                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1504                         np->rx_ring.orig[i].flaglen = 0;
1505                         np->rx_ring.orig[i].buf = 0;
1506                 } else {
1507                         np->rx_ring.ex[i].flaglen = 0;
1508                         np->rx_ring.ex[i].txvlan = 0;
1509                         np->rx_ring.ex[i].bufhigh = 0;
1510                         np->rx_ring.ex[i].buflow = 0;
1511                 }
1512                 np->rx_skb[i].skb = NULL;
1513                 np->rx_skb[i].dma = 0;
1514         }
1515 }
1516
1517 static void nv_init_tx(struct net_device *dev)
1518 {
1519         struct fe_priv *np = netdev_priv(dev);
1520         int i;
1521         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1522         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1523                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1524         else
1525                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1526         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1527         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1528
1529         for (i = 0; i < np->tx_ring_size; i++) {
1530                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1531                         np->tx_ring.orig[i].flaglen = 0;
1532                         np->tx_ring.orig[i].buf = 0;
1533                 } else {
1534                         np->tx_ring.ex[i].flaglen = 0;
1535                         np->tx_ring.ex[i].txvlan = 0;
1536                         np->tx_ring.ex[i].bufhigh = 0;
1537                         np->tx_ring.ex[i].buflow = 0;
1538                 }
1539                 np->tx_skb[i].skb = NULL;
1540                 np->tx_skb[i].dma = 0;
1541         }
1542 }
1543
1544 static int nv_init_ring(struct net_device *dev)
1545 {
1546         struct fe_priv *np = netdev_priv(dev);
1547
1548         nv_init_tx(dev);
1549         nv_init_rx(dev);
1550         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1551                 return nv_alloc_rx(dev);
1552         else
1553                 return nv_alloc_rx_optimized(dev);
1554 }
1555
1556 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1557 {
1558         struct fe_priv *np = netdev_priv(dev);
1559
1560         if (tx_skb->dma) {
1561                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1562                                tx_skb->dma_len,
1563                                PCI_DMA_TODEVICE);
1564                 tx_skb->dma = 0;
1565         }
1566         if (tx_skb->skb) {
1567                 dev_kfree_skb_any(tx_skb->skb);
1568                 tx_skb->skb = NULL;
1569                 return 1;
1570         } else {
1571                 return 0;
1572         }
1573 }
1574
1575 static void nv_drain_tx(struct net_device *dev)
1576 {
1577         struct fe_priv *np = netdev_priv(dev);
1578         unsigned int i;
1579
1580         for (i = 0; i < np->tx_ring_size; i++) {
1581                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1582                         np->tx_ring.orig[i].flaglen = 0;
1583                         np->tx_ring.orig[i].buf = 0;
1584                 } else {
1585                         np->tx_ring.ex[i].flaglen = 0;
1586                         np->tx_ring.ex[i].txvlan = 0;
1587                         np->tx_ring.ex[i].bufhigh = 0;
1588                         np->tx_ring.ex[i].buflow = 0;
1589                 }
1590                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1591                         np->stats.tx_dropped++;
1592         }
1593 }
1594
1595 static void nv_drain_rx(struct net_device *dev)
1596 {
1597         struct fe_priv *np = netdev_priv(dev);
1598         int i;
1599
1600         for (i = 0; i < np->rx_ring_size; i++) {
1601                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1602                         np->rx_ring.orig[i].flaglen = 0;
1603                         np->rx_ring.orig[i].buf = 0;
1604                 } else {
1605                         np->rx_ring.ex[i].flaglen = 0;
1606                         np->rx_ring.ex[i].txvlan = 0;
1607                         np->rx_ring.ex[i].bufhigh = 0;
1608                         np->rx_ring.ex[i].buflow = 0;
1609                 }
1610                 wmb();
1611                 if (np->rx_skb[i].skb) {
1612                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1613                                          (skb_end_pointer(np->rx_skb[i].skb) -
1614                                           np->rx_skb[i].skb->data),
1615                                          PCI_DMA_FROMDEVICE);
1616                         dev_kfree_skb(np->rx_skb[i].skb);
1617                         np->rx_skb[i].skb = NULL;
1618                 }
1619         }
1620 }
1621
1622 static void drain_ring(struct net_device *dev)
1623 {
1624         nv_drain_tx(dev);
1625         nv_drain_rx(dev);
1626 }
1627
1628 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1629 {
1630         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1631 }
1632
1633 /*
1634  * nv_start_xmit: dev->hard_start_xmit function
1635  * Called with netif_tx_lock held.
1636  */
1637 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1638 {
1639         struct fe_priv *np = netdev_priv(dev);
1640         u32 tx_flags = 0;
1641         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1642         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1643         unsigned int i;
1644         u32 offset = 0;
1645         u32 bcnt;
1646         u32 size = skb->len-skb->data_len;
1647         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1648         u32 empty_slots;
1649         struct ring_desc* put_tx;
1650         struct ring_desc* start_tx;
1651         struct ring_desc* prev_tx;
1652         struct nv_skb_map* prev_tx_ctx;
1653
1654         /* add fragments to entries count */
1655         for (i = 0; i < fragments; i++) {
1656                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1657                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1658         }
1659
1660         empty_slots = nv_get_empty_tx_slots(np);
1661         if (unlikely(empty_slots <= entries)) {
1662                 spin_lock_irq(&np->lock);
1663                 netif_stop_queue(dev);
1664                 np->tx_stop = 1;
1665                 spin_unlock_irq(&np->lock);
1666                 return NETDEV_TX_BUSY;
1667         }
1668
1669         start_tx = put_tx = np->put_tx.orig;
1670
1671         /* setup the header buffer */
1672         do {
1673                 prev_tx = put_tx;
1674                 prev_tx_ctx = np->put_tx_ctx;
1675                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1676                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1677                                                 PCI_DMA_TODEVICE);
1678                 np->put_tx_ctx->dma_len = bcnt;
1679                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1680                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1681
1682                 tx_flags = np->tx_flags;
1683                 offset += bcnt;
1684                 size -= bcnt;
1685                 if (unlikely(put_tx++ == np->last_tx.orig))
1686                         put_tx = np->first_tx.orig;
1687                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1688                         np->put_tx_ctx = np->first_tx_ctx;
1689         } while (size);
1690
1691         /* setup the fragments */
1692         for (i = 0; i < fragments; i++) {
1693                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1694                 u32 size = frag->size;
1695                 offset = 0;
1696
1697                 do {
1698                         prev_tx = put_tx;
1699                         prev_tx_ctx = np->put_tx_ctx;
1700                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1701                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1702                                                            PCI_DMA_TODEVICE);
1703                         np->put_tx_ctx->dma_len = bcnt;
1704                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1705                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1706
1707                         offset += bcnt;
1708                         size -= bcnt;
1709                         if (unlikely(put_tx++ == np->last_tx.orig))
1710                                 put_tx = np->first_tx.orig;
1711                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1712                                 np->put_tx_ctx = np->first_tx_ctx;
1713                 } while (size);
1714         }
1715
1716         /* set last fragment flag  */
1717         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1718
1719         /* save skb in this slot's context area */
1720         prev_tx_ctx->skb = skb;
1721
1722         if (skb_is_gso(skb))
1723                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1724         else
1725                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1726                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1727
1728         spin_lock_irq(&np->lock);
1729
1730         /* set tx flags */
1731         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1732         np->put_tx.orig = put_tx;
1733
1734         spin_unlock_irq(&np->lock);
1735
1736         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1737                 dev->name, entries, tx_flags_extra);
1738         {
1739                 int j;
1740                 for (j=0; j<64; j++) {
1741                         if ((j%16) == 0)
1742                                 dprintk("\n%03x:", j);
1743                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1744                 }
1745                 dprintk("\n");
1746         }
1747
1748         dev->trans_start = jiffies;
1749         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1750         return NETDEV_TX_OK;
1751 }
1752
1753 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1754 {
1755         struct fe_priv *np = netdev_priv(dev);
1756         u32 tx_flags = 0;
1757         u32 tx_flags_extra;
1758         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1759         unsigned int i;
1760         u32 offset = 0;
1761         u32 bcnt;
1762         u32 size = skb->len-skb->data_len;
1763         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1764         u32 empty_slots;
1765         struct ring_desc_ex* put_tx;
1766         struct ring_desc_ex* start_tx;
1767         struct ring_desc_ex* prev_tx;
1768         struct nv_skb_map* prev_tx_ctx;
1769
1770         /* add fragments to entries count */
1771         for (i = 0; i < fragments; i++) {
1772                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1773                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1774         }
1775
1776         empty_slots = nv_get_empty_tx_slots(np);
1777         if (unlikely(empty_slots <= entries)) {
1778                 spin_lock_irq(&np->lock);
1779                 netif_stop_queue(dev);
1780                 np->tx_stop = 1;
1781                 spin_unlock_irq(&np->lock);
1782                 return NETDEV_TX_BUSY;
1783         }
1784
1785         start_tx = put_tx = np->put_tx.ex;
1786
1787         /* setup the header buffer */
1788         do {
1789                 prev_tx = put_tx;
1790                 prev_tx_ctx = np->put_tx_ctx;
1791                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1792                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1793                                                 PCI_DMA_TODEVICE);
1794                 np->put_tx_ctx->dma_len = bcnt;
1795                 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1796                 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1797                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1798
1799                 tx_flags = NV_TX2_VALID;
1800                 offset += bcnt;
1801                 size -= bcnt;
1802                 if (unlikely(put_tx++ == np->last_tx.ex))
1803                         put_tx = np->first_tx.ex;
1804                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1805                         np->put_tx_ctx = np->first_tx_ctx;
1806         } while (size);
1807
1808         /* setup the fragments */
1809         for (i = 0; i < fragments; i++) {
1810                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1811                 u32 size = frag->size;
1812                 offset = 0;
1813
1814                 do {
1815                         prev_tx = put_tx;
1816                         prev_tx_ctx = np->put_tx_ctx;
1817                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1818                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1819                                                            PCI_DMA_TODEVICE);
1820                         np->put_tx_ctx->dma_len = bcnt;
1821                         put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1822                         put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1823                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1824
1825                         offset += bcnt;
1826                         size -= bcnt;
1827                         if (unlikely(put_tx++ == np->last_tx.ex))
1828                                 put_tx = np->first_tx.ex;
1829                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1830                                 np->put_tx_ctx = np->first_tx_ctx;
1831                 } while (size);
1832         }
1833
1834         /* set last fragment flag  */
1835         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1836
1837         /* save skb in this slot's context area */
1838         prev_tx_ctx->skb = skb;
1839
1840         if (skb_is_gso(skb))
1841                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1842         else
1843                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1844                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1845
1846         /* vlan tag */
1847         if (likely(!np->vlangrp)) {
1848                 start_tx->txvlan = 0;
1849         } else {
1850                 if (vlan_tx_tag_present(skb))
1851                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1852                 else
1853                         start_tx->txvlan = 0;
1854         }
1855
1856         spin_lock_irq(&np->lock);
1857
1858         /* set tx flags */
1859         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1860         np->put_tx.ex = put_tx;
1861
1862         spin_unlock_irq(&np->lock);
1863
1864         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
1865                 dev->name, entries, tx_flags_extra);
1866         {
1867                 int j;
1868                 for (j=0; j<64; j++) {
1869                         if ((j%16) == 0)
1870                                 dprintk("\n%03x:", j);
1871                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1872                 }
1873                 dprintk("\n");
1874         }
1875
1876         dev->trans_start = jiffies;
1877         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1878         return NETDEV_TX_OK;
1879 }
1880
1881 /*
1882  * nv_tx_done: check for completed packets, release the skbs.
1883  *
1884  * Caller must own np->lock.
1885  */
1886 static void nv_tx_done(struct net_device *dev)
1887 {
1888         struct fe_priv *np = netdev_priv(dev);
1889         u32 flags;
1890         struct ring_desc* orig_get_tx = np->get_tx.orig;
1891
1892         while ((np->get_tx.orig != np->put_tx.orig) &&
1893                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
1894
1895                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1896                                         dev->name, flags);
1897
1898                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1899                                np->get_tx_ctx->dma_len,
1900                                PCI_DMA_TODEVICE);
1901                 np->get_tx_ctx->dma = 0;
1902
1903                 if (np->desc_ver == DESC_VER_1) {
1904                         if (flags & NV_TX_LASTPACKET) {
1905                                 if (flags & NV_TX_ERROR) {
1906                                         if (flags & NV_TX_UNDERFLOW)
1907                                                 np->stats.tx_fifo_errors++;
1908                                         if (flags & NV_TX_CARRIERLOST)
1909                                                 np->stats.tx_carrier_errors++;
1910                                         np->stats.tx_errors++;
1911                                 } else {
1912                                         np->stats.tx_packets++;
1913                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1914                                 }
1915                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1916                                 np->get_tx_ctx->skb = NULL;
1917                         }
1918                 } else {
1919                         if (flags & NV_TX2_LASTPACKET) {
1920                                 if (flags & NV_TX2_ERROR) {
1921                                         if (flags & NV_TX2_UNDERFLOW)
1922                                                 np->stats.tx_fifo_errors++;
1923                                         if (flags & NV_TX2_CARRIERLOST)
1924                                                 np->stats.tx_carrier_errors++;
1925                                         np->stats.tx_errors++;
1926                                 } else {
1927                                         np->stats.tx_packets++;
1928                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1929                                 }
1930                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1931                                 np->get_tx_ctx->skb = NULL;
1932                         }
1933                 }
1934                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
1935                         np->get_tx.orig = np->first_tx.orig;
1936                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1937                         np->get_tx_ctx = np->first_tx_ctx;
1938         }
1939         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
1940                 np->tx_stop = 0;
1941                 netif_wake_queue(dev);
1942         }
1943 }
1944
1945 static void nv_tx_done_optimized(struct net_device *dev, int limit)
1946 {
1947         struct fe_priv *np = netdev_priv(dev);
1948         u32 flags;
1949         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
1950
1951         while ((np->get_tx.ex != np->put_tx.ex) &&
1952                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
1953                (limit-- > 0)) {
1954
1955                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
1956                                         dev->name, flags);
1957
1958                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1959                                np->get_tx_ctx->dma_len,
1960                                PCI_DMA_TODEVICE);
1961                 np->get_tx_ctx->dma = 0;
1962
1963                 if (flags & NV_TX2_LASTPACKET) {
1964                         if (!(flags & NV_TX2_ERROR))
1965                                 np->stats.tx_packets++;
1966                         dev_kfree_skb_any(np->get_tx_ctx->skb);
1967                         np->get_tx_ctx->skb = NULL;
1968                 }
1969                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
1970                         np->get_tx.ex = np->first_tx.ex;
1971                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1972                         np->get_tx_ctx = np->first_tx_ctx;
1973         }
1974         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
1975                 np->tx_stop = 0;
1976                 netif_wake_queue(dev);
1977         }
1978 }
1979
1980 /*
1981  * nv_tx_timeout: dev->tx_timeout function
1982  * Called with netif_tx_lock held.
1983  */
1984 static void nv_tx_timeout(struct net_device *dev)
1985 {
1986         struct fe_priv *np = netdev_priv(dev);
1987         u8 __iomem *base = get_hwbase(dev);
1988         u32 status;
1989
1990         if (np->msi_flags & NV_MSI_X_ENABLED)
1991                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1992         else
1993                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1994
1995         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1996
1997         {
1998                 int i;
1999
2000                 printk(KERN_INFO "%s: Ring at %lx\n",
2001                        dev->name, (unsigned long)np->ring_addr);
2002                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2003                 for (i=0;i<=np->register_size;i+= 32) {
2004                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2005                                         i,
2006                                         readl(base + i + 0), readl(base + i + 4),
2007                                         readl(base + i + 8), readl(base + i + 12),
2008                                         readl(base + i + 16), readl(base + i + 20),
2009                                         readl(base + i + 24), readl(base + i + 28));
2010                 }
2011                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2012                 for (i=0;i<np->tx_ring_size;i+= 4) {
2013                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2014                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2015                                        i,
2016                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2017                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2018                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2019                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2020                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2021                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2022                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2023                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2024                         } else {
2025                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2026                                        i,
2027                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2028                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2029                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2030                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2031                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2032                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2033                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2034                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2035                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2036                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2037                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2038                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2039                         }
2040                 }
2041         }
2042
2043         spin_lock_irq(&np->lock);
2044
2045         /* 1) stop tx engine */
2046         nv_stop_tx(dev);
2047
2048         /* 2) check that the packets were not sent already: */
2049         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2050                 nv_tx_done(dev);
2051         else
2052                 nv_tx_done_optimized(dev, np->tx_ring_size);
2053
2054         /* 3) if there are dead entries: clear everything */
2055         if (np->get_tx_ctx != np->put_tx_ctx) {
2056                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2057                 nv_drain_tx(dev);
2058                 nv_init_tx(dev);
2059                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2060         }
2061
2062         netif_wake_queue(dev);
2063
2064         /* 4) restart tx engine */
2065         nv_start_tx(dev);
2066         spin_unlock_irq(&np->lock);
2067 }
2068
2069 /*
2070  * Called when the nic notices a mismatch between the actual data len on the
2071  * wire and the len indicated in the 802 header
2072  */
2073 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2074 {
2075         int hdrlen;     /* length of the 802 header */
2076         int protolen;   /* length as stored in the proto field */
2077
2078         /* 1) calculate len according to header */
2079         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2080                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2081                 hdrlen = VLAN_HLEN;
2082         } else {
2083                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2084                 hdrlen = ETH_HLEN;
2085         }
2086         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2087                                 dev->name, datalen, protolen, hdrlen);
2088         if (protolen > ETH_DATA_LEN)
2089                 return datalen; /* Value in proto field not a len, no checks possible */
2090
2091         protolen += hdrlen;
2092         /* consistency checks: */
2093         if (datalen > ETH_ZLEN) {
2094                 if (datalen >= protolen) {
2095                         /* more data on wire than in 802 header, trim of
2096                          * additional data.
2097                          */
2098                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2099                                         dev->name, protolen);
2100                         return protolen;
2101                 } else {
2102                         /* less data on wire than mentioned in header.
2103                          * Discard the packet.
2104                          */
2105                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2106                                         dev->name);
2107                         return -1;
2108                 }
2109         } else {
2110                 /* short packet. Accept only if 802 values are also short */
2111                 if (protolen > ETH_ZLEN) {
2112                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2113                                         dev->name);
2114                         return -1;
2115                 }
2116                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2117                                 dev->name, datalen);
2118                 return datalen;
2119         }
2120 }
2121
2122 static int nv_rx_process(struct net_device *dev, int limit)
2123 {
2124         struct fe_priv *np = netdev_priv(dev);
2125         u32 flags;
2126         u32 rx_processed_cnt = 0;
2127         struct sk_buff *skb;
2128         int len;
2129
2130         while((np->get_rx.orig != np->put_rx.orig) &&
2131               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2132                 (rx_processed_cnt++ < limit)) {
2133
2134                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2135                                         dev->name, flags);
2136
2137                 /*
2138                  * the packet is for us - immediately tear down the pci mapping.
2139                  * TODO: check if a prefetch of the first cacheline improves
2140                  * the performance.
2141                  */
2142                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2143                                 np->get_rx_ctx->dma_len,
2144                                 PCI_DMA_FROMDEVICE);
2145                 skb = np->get_rx_ctx->skb;
2146                 np->get_rx_ctx->skb = NULL;
2147
2148                 {
2149                         int j;
2150                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2151                         for (j=0; j<64; j++) {
2152                                 if ((j%16) == 0)
2153                                         dprintk("\n%03x:", j);
2154                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2155                         }
2156                         dprintk("\n");
2157                 }
2158                 /* look at what we actually got: */
2159                 if (np->desc_ver == DESC_VER_1) {
2160                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2161                                 len = flags & LEN_MASK_V1;
2162                                 if (unlikely(flags & NV_RX_ERROR)) {
2163                                         if (flags & NV_RX_ERROR4) {
2164                                                 len = nv_getlen(dev, skb->data, len);
2165                                                 if (len < 0) {
2166                                                         np->stats.rx_errors++;
2167                                                         dev_kfree_skb(skb);
2168                                                         goto next_pkt;
2169                                                 }
2170                                         }
2171                                         /* framing errors are soft errors */
2172                                         else if (flags & NV_RX_FRAMINGERR) {
2173                                                 if (flags & NV_RX_SUBSTRACT1) {
2174                                                         len--;
2175                                                 }
2176                                         }
2177                                         /* the rest are hard errors */
2178                                         else {
2179                                                 if (flags & NV_RX_MISSEDFRAME)
2180                                                         np->stats.rx_missed_errors++;
2181                                                 if (flags & NV_RX_CRCERR)
2182                                                         np->stats.rx_crc_errors++;
2183                                                 if (flags & NV_RX_OVERFLOW)
2184                                                         np->stats.rx_over_errors++;
2185                                                 np->stats.rx_errors++;
2186                                                 dev_kfree_skb(skb);
2187                                                 goto next_pkt;
2188                                         }
2189                                 }
2190                         } else {
2191                                 dev_kfree_skb(skb);
2192                                 goto next_pkt;
2193                         }
2194                 } else {
2195                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2196                                 len = flags & LEN_MASK_V2;
2197                                 if (unlikely(flags & NV_RX2_ERROR)) {
2198                                         if (flags & NV_RX2_ERROR4) {
2199                                                 len = nv_getlen(dev, skb->data, len);
2200                                                 if (len < 0) {
2201                                                         np->stats.rx_errors++;
2202                                                         dev_kfree_skb(skb);
2203                                                         goto next_pkt;
2204                                                 }
2205                                         }
2206                                         /* framing errors are soft errors */
2207                                         else if (flags & NV_RX2_FRAMINGERR) {
2208                                                 if (flags & NV_RX2_SUBSTRACT1) {
2209                                                         len--;
2210                                                 }
2211                                         }
2212                                         /* the rest are hard errors */
2213                                         else {
2214                                                 if (flags & NV_RX2_CRCERR)
2215                                                         np->stats.rx_crc_errors++;
2216                                                 if (flags & NV_RX2_OVERFLOW)
2217                                                         np->stats.rx_over_errors++;
2218                                                 np->stats.rx_errors++;
2219                                                 dev_kfree_skb(skb);
2220                                                 goto next_pkt;
2221                                         }
2222                                 }
2223                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2224                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2225                                 } else {
2226                                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2227                                             (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2228                                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2229                                         }
2230                                 }
2231                         } else {
2232                                 dev_kfree_skb(skb);
2233                                 goto next_pkt;
2234                         }
2235                 }
2236                 /* got a valid packet - forward it to the network core */
2237                 skb_put(skb, len);
2238                 skb->protocol = eth_type_trans(skb, dev);
2239                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2240                                         dev->name, len, skb->protocol);
2241 #ifdef CONFIG_FORCEDETH_NAPI
2242                 netif_receive_skb(skb);
2243 #else
2244                 netif_rx(skb);
2245 #endif
2246                 dev->last_rx = jiffies;
2247                 np->stats.rx_packets++;
2248                 np->stats.rx_bytes += len;
2249 next_pkt:
2250                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2251                         np->get_rx.orig = np->first_rx.orig;
2252                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2253                         np->get_rx_ctx = np->first_rx_ctx;
2254         }
2255
2256         return rx_processed_cnt;
2257 }
2258
2259 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2260 {
2261         struct fe_priv *np = netdev_priv(dev);
2262         u32 flags;
2263         u32 vlanflags = 0;
2264         u32 rx_processed_cnt = 0;
2265         struct sk_buff *skb;
2266         int len;
2267
2268         while((np->get_rx.ex != np->put_rx.ex) &&
2269               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2270               (rx_processed_cnt++ < limit)) {
2271
2272                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2273                                         dev->name, flags);
2274
2275                 /*
2276                  * the packet is for us - immediately tear down the pci mapping.
2277                  * TODO: check if a prefetch of the first cacheline improves
2278                  * the performance.
2279                  */
2280                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2281                                 np->get_rx_ctx->dma_len,
2282                                 PCI_DMA_FROMDEVICE);
2283                 skb = np->get_rx_ctx->skb;
2284                 np->get_rx_ctx->skb = NULL;
2285
2286                 {
2287                         int j;
2288                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2289                         for (j=0; j<64; j++) {
2290                                 if ((j%16) == 0)
2291                                         dprintk("\n%03x:", j);
2292                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2293                         }
2294                         dprintk("\n");
2295                 }
2296                 /* look at what we actually got: */
2297                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2298                         len = flags & LEN_MASK_V2;
2299                         if (unlikely(flags & NV_RX2_ERROR)) {
2300                                 if (flags & NV_RX2_ERROR4) {
2301                                         len = nv_getlen(dev, skb->data, len);
2302                                         if (len < 0) {
2303                                                 dev_kfree_skb(skb);
2304                                                 goto next_pkt;
2305                                         }
2306                                 }
2307                                 /* framing errors are soft errors */
2308                                 else if (flags & NV_RX2_FRAMINGERR) {
2309                                         if (flags & NV_RX2_SUBSTRACT1) {
2310                                                 len--;
2311                                         }
2312                                 }
2313                                 /* the rest are hard errors */
2314                                 else {
2315                                         dev_kfree_skb(skb);
2316                                         goto next_pkt;
2317                                 }
2318                         }
2319
2320                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2321                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2322                         } else {
2323                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2324                                     (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2325                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2326                                 }
2327                         }
2328
2329                         /* got a valid packet - forward it to the network core */
2330                         skb_put(skb, len);
2331                         skb->protocol = eth_type_trans(skb, dev);
2332                         prefetch(skb->data);
2333
2334                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2335                                 dev->name, len, skb->protocol);
2336
2337                         if (likely(!np->vlangrp)) {
2338 #ifdef CONFIG_FORCEDETH_NAPI
2339                                 netif_receive_skb(skb);
2340 #else
2341                                 netif_rx(skb);
2342 #endif
2343                         } else {
2344                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2345                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2346 #ifdef CONFIG_FORCEDETH_NAPI
2347                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2348                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2349 #else
2350                                         vlan_hwaccel_rx(skb, np->vlangrp,
2351                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2352 #endif
2353                                 } else {
2354 #ifdef CONFIG_FORCEDETH_NAPI
2355                                         netif_receive_skb(skb);
2356 #else
2357                                         netif_rx(skb);
2358 #endif
2359                                 }
2360                         }
2361
2362                         dev->last_rx = jiffies;
2363                         np->stats.rx_packets++;
2364                         np->stats.rx_bytes += len;
2365                 } else {
2366                         dev_kfree_skb(skb);
2367                 }
2368 next_pkt:
2369                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2370                         np->get_rx.ex = np->first_rx.ex;
2371                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2372                         np->get_rx_ctx = np->first_rx_ctx;
2373         }
2374
2375         return rx_processed_cnt;
2376 }
2377
2378 static void set_bufsize(struct net_device *dev)
2379 {
2380         struct fe_priv *np = netdev_priv(dev);
2381
2382         if (dev->mtu <= ETH_DATA_LEN)
2383                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2384         else
2385                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2386 }
2387
2388 /*
2389  * nv_change_mtu: dev->change_mtu function
2390  * Called with dev_base_lock held for read.
2391  */
2392 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2393 {
2394         struct fe_priv *np = netdev_priv(dev);
2395         int old_mtu;
2396
2397         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2398                 return -EINVAL;
2399
2400         old_mtu = dev->mtu;
2401         dev->mtu = new_mtu;
2402
2403         /* return early if the buffer sizes will not change */
2404         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2405                 return 0;
2406         if (old_mtu == new_mtu)
2407                 return 0;
2408
2409         /* synchronized against open : rtnl_lock() held by caller */
2410         if (netif_running(dev)) {
2411                 u8 __iomem *base = get_hwbase(dev);
2412                 /*
2413                  * It seems that the nic preloads valid ring entries into an
2414                  * internal buffer. The procedure for flushing everything is
2415                  * guessed, there is probably a simpler approach.
2416                  * Changing the MTU is a rare event, it shouldn't matter.
2417                  */
2418                 nv_disable_irq(dev);
2419                 netif_tx_lock_bh(dev);
2420                 spin_lock(&np->lock);
2421                 /* stop engines */
2422                 nv_stop_rx(dev);
2423                 nv_stop_tx(dev);
2424                 nv_txrx_reset(dev);
2425                 /* drain rx queue */
2426                 nv_drain_rx(dev);
2427                 nv_drain_tx(dev);
2428                 /* reinit driver view of the rx queue */
2429                 set_bufsize(dev);
2430                 if (nv_init_ring(dev)) {
2431                         if (!np->in_shutdown)
2432                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2433                 }
2434                 /* reinit nic view of the rx queue */
2435                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2436                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2437                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2438                         base + NvRegRingSizes);
2439                 pci_push(base);
2440                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2441                 pci_push(base);
2442
2443                 /* restart rx engine */
2444                 nv_start_rx(dev);
2445                 nv_start_tx(dev);
2446                 spin_unlock(&np->lock);
2447                 netif_tx_unlock_bh(dev);
2448                 nv_enable_irq(dev);
2449         }
2450         return 0;
2451 }
2452
2453 static void nv_copy_mac_to_hw(struct net_device *dev)
2454 {
2455         u8 __iomem *base = get_hwbase(dev);
2456         u32 mac[2];
2457
2458         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2459                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2460         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2461
2462         writel(mac[0], base + NvRegMacAddrA);
2463         writel(mac[1], base + NvRegMacAddrB);
2464 }
2465
2466 /*
2467  * nv_set_mac_address: dev->set_mac_address function
2468  * Called with rtnl_lock() held.
2469  */
2470 static int nv_set_mac_address(struct net_device *dev, void *addr)
2471 {
2472         struct fe_priv *np = netdev_priv(dev);
2473         struct sockaddr *macaddr = (struct sockaddr*)addr;
2474
2475         if (!is_valid_ether_addr(macaddr->sa_data))
2476                 return -EADDRNOTAVAIL;
2477
2478         /* synchronized against open : rtnl_lock() held by caller */
2479         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2480
2481         if (netif_running(dev)) {
2482                 netif_tx_lock_bh(dev);
2483                 spin_lock_irq(&np->lock);
2484
2485                 /* stop rx engine */
2486                 nv_stop_rx(dev);
2487
2488                 /* set mac address */
2489                 nv_copy_mac_to_hw(dev);
2490
2491                 /* restart rx engine */
2492                 nv_start_rx(dev);
2493                 spin_unlock_irq(&np->lock);
2494                 netif_tx_unlock_bh(dev);
2495         } else {
2496                 nv_copy_mac_to_hw(dev);
2497         }
2498         return 0;
2499 }
2500
2501 /*
2502  * nv_set_multicast: dev->set_multicast function
2503  * Called with netif_tx_lock held.
2504  */
2505 static void nv_set_multicast(struct net_device *dev)
2506 {
2507         struct fe_priv *np = netdev_priv(dev);
2508         u8 __iomem *base = get_hwbase(dev);
2509         u32 addr[2];
2510         u32 mask[2];
2511         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2512
2513         memset(addr, 0, sizeof(addr));
2514         memset(mask, 0, sizeof(mask));
2515
2516         if (dev->flags & IFF_PROMISC) {
2517                 pff |= NVREG_PFF_PROMISC;
2518         } else {
2519                 pff |= NVREG_PFF_MYADDR;
2520
2521                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2522                         u32 alwaysOff[2];
2523                         u32 alwaysOn[2];
2524
2525                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2526                         if (dev->flags & IFF_ALLMULTI) {
2527                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2528                         } else {
2529                                 struct dev_mc_list *walk;
2530
2531                                 walk = dev->mc_list;
2532                                 while (walk != NULL) {
2533                                         u32 a, b;
2534                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2535                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2536                                         alwaysOn[0] &= a;
2537                                         alwaysOff[0] &= ~a;
2538                                         alwaysOn[1] &= b;
2539                                         alwaysOff[1] &= ~b;
2540                                         walk = walk->next;
2541                                 }
2542                         }
2543                         addr[0] = alwaysOn[0];
2544                         addr[1] = alwaysOn[1];
2545                         mask[0] = alwaysOn[0] | alwaysOff[0];
2546                         mask[1] = alwaysOn[1] | alwaysOff[1];
2547                 }
2548         }
2549         addr[0] |= NVREG_MCASTADDRA_FORCE;
2550         pff |= NVREG_PFF_ALWAYS;
2551         spin_lock_irq(&np->lock);
2552         nv_stop_rx(dev);
2553         writel(addr[0], base + NvRegMulticastAddrA);
2554         writel(addr[1], base + NvRegMulticastAddrB);
2555         writel(mask[0], base + NvRegMulticastMaskA);
2556         writel(mask[1], base + NvRegMulticastMaskB);
2557         writel(pff, base + NvRegPacketFilterFlags);
2558         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2559                 dev->name);
2560         nv_start_rx(dev);
2561         spin_unlock_irq(&np->lock);
2562 }
2563
2564 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2565 {
2566         struct fe_priv *np = netdev_priv(dev);
2567         u8 __iomem *base = get_hwbase(dev);
2568
2569         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2570
2571         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2572                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2573                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2574                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2575                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2576                 } else {
2577                         writel(pff, base + NvRegPacketFilterFlags);
2578                 }
2579         }
2580         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2581                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2582                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2583                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2584                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2585                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2586                 } else {
2587                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2588                         writel(regmisc, base + NvRegMisc1);
2589                 }
2590         }
2591 }
2592
2593 /**
2594  * nv_update_linkspeed: Setup the MAC according to the link partner
2595  * @dev: Network device to be configured
2596  *
2597  * The function queries the PHY and checks if there is a link partner.
2598  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2599  * set to 10 MBit HD.
2600  *
2601  * The function returns 0 if there is no link partner and 1 if there is
2602  * a good link partner.
2603  */
2604 static int nv_update_linkspeed(struct net_device *dev)
2605 {
2606         struct fe_priv *np = netdev_priv(dev);
2607         u8 __iomem *base = get_hwbase(dev);
2608         int adv = 0;
2609         int lpa = 0;
2610         int adv_lpa, adv_pause, lpa_pause;
2611         int newls = np->linkspeed;
2612         int newdup = np->duplex;
2613         int mii_status;
2614         int retval = 0;
2615         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2616
2617         /* BMSR_LSTATUS is latched, read it twice:
2618          * we want the current value.
2619          */
2620         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2621         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2622
2623         if (!(mii_status & BMSR_LSTATUS)) {
2624                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2625                                 dev->name);
2626                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2627                 newdup = 0;
2628                 retval = 0;
2629                 goto set_speed;
2630         }
2631
2632         if (np->autoneg == 0) {
2633                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2634                                 dev->name, np->fixed_mode);
2635                 if (np->fixed_mode & LPA_100FULL) {
2636                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2637                         newdup = 1;
2638                 } else if (np->fixed_mode & LPA_100HALF) {
2639                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2640                         newdup = 0;
2641                 } else if (np->fixed_mode & LPA_10FULL) {
2642                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2643                         newdup = 1;
2644                 } else {
2645                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2646                         newdup = 0;
2647                 }
2648                 retval = 1;
2649                 goto set_speed;
2650         }
2651         /* check auto negotiation is complete */
2652         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2653                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2654                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2655                 newdup = 0;
2656                 retval = 0;
2657                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2658                 goto set_speed;
2659         }
2660
2661         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2662         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2663         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2664                                 dev->name, adv, lpa);
2665
2666         retval = 1;
2667         if (np->gigabit == PHY_GIGABIT) {
2668                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2669                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2670
2671                 if ((control_1000 & ADVERTISE_1000FULL) &&
2672                         (status_1000 & LPA_1000FULL)) {
2673                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2674                                 dev->name);
2675                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2676                         newdup = 1;
2677                         goto set_speed;
2678                 }
2679         }
2680
2681         /* FIXME: handle parallel detection properly */
2682         adv_lpa = lpa & adv;
2683         if (adv_lpa & LPA_100FULL) {
2684                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2685                 newdup = 1;
2686         } else if (adv_lpa & LPA_100HALF) {
2687                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2688                 newdup = 0;
2689         } else if (adv_lpa & LPA_10FULL) {
2690                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2691                 newdup = 1;
2692         } else if (adv_lpa & LPA_10HALF) {
2693                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2694                 newdup = 0;
2695         } else {
2696                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2697                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2698                 newdup = 0;
2699         }
2700
2701 set_speed:
2702         if (np->duplex == newdup && np->linkspeed == newls)
2703                 return retval;
2704
2705         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2706                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2707
2708         np->duplex = newdup;
2709         np->linkspeed = newls;
2710
2711         if (np->gigabit == PHY_GIGABIT) {
2712                 phyreg = readl(base + NvRegRandomSeed);
2713                 phyreg &= ~(0x3FF00);
2714                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2715                         phyreg |= NVREG_RNDSEED_FORCE3;
2716                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2717                         phyreg |= NVREG_RNDSEED_FORCE2;
2718                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2719                         phyreg |= NVREG_RNDSEED_FORCE;
2720                 writel(phyreg, base + NvRegRandomSeed);
2721         }
2722
2723         phyreg = readl(base + NvRegPhyInterface);
2724         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2725         if (np->duplex == 0)
2726                 phyreg |= PHY_HALF;
2727         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2728                 phyreg |= PHY_100;
2729         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2730                 phyreg |= PHY_1000;
2731         writel(phyreg, base + NvRegPhyInterface);
2732
2733         if (phyreg & PHY_RGMII) {
2734                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2735                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2736                 else
2737                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2738         } else {
2739                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2740         }
2741         writel(txreg, base + NvRegTxDeferral);
2742
2743         if (np->desc_ver == DESC_VER_1) {
2744                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2745         } else {
2746                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2747                         txreg = NVREG_TX_WM_DESC2_3_1000;
2748                 else
2749                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2750         }
2751         writel(txreg, base + NvRegTxWatermark);
2752
2753         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2754                 base + NvRegMisc1);
2755         pci_push(base);
2756         writel(np->linkspeed, base + NvRegLinkSpeed);
2757         pci_push(base);
2758
2759         pause_flags = 0;
2760         /* setup pause frame */
2761         if (np->duplex != 0) {
2762                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2763                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2764                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2765
2766                         switch (adv_pause) {
2767                         case ADVERTISE_PAUSE_CAP:
2768                                 if (lpa_pause & LPA_PAUSE_CAP) {
2769                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2770                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2771                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2772                                 }
2773                                 break;
2774                         case ADVERTISE_PAUSE_ASYM:
2775                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2776                                 {
2777                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2778                                 }
2779                                 break;
2780                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2781                                 if (lpa_pause & LPA_PAUSE_CAP)
2782                                 {
2783                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2784                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2785                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2786                                 }
2787                                 if (lpa_pause == LPA_PAUSE_ASYM)
2788                                 {
2789                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2790                                 }
2791                                 break;
2792                         }
2793                 } else {
2794                         pause_flags = np->pause_flags;
2795                 }
2796         }
2797         nv_update_pause(dev, pause_flags);
2798
2799         return retval;
2800 }
2801
2802 static void nv_linkchange(struct net_device *dev)
2803 {
2804         if (nv_update_linkspeed(dev)) {
2805                 if (!netif_carrier_ok(dev)) {
2806                         netif_carrier_on(dev);
2807                         printk(KERN_INFO "%s: link up.\n", dev->name);
2808                         nv_start_rx(dev);
2809                 }
2810         } else {
2811                 if (netif_carrier_ok(dev)) {
2812                         netif_carrier_off(dev);
2813                         printk(KERN_INFO "%s: link down.\n", dev->name);
2814                         nv_stop_rx(dev);
2815                 }
2816         }
2817 }
2818
2819 static void nv_link_irq(struct net_device *dev)
2820 {
2821         u8 __iomem *base = get_hwbase(dev);
2822         u32 miistat;
2823
2824         miistat = readl(base + NvRegMIIStatus);
2825         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2826         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2827
2828         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2829                 nv_linkchange(dev);
2830         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2831 }
2832
2833 static irqreturn_t nv_nic_irq(int foo, void *data)
2834 {
2835         struct net_device *dev = (struct net_device *) data;
2836         struct fe_priv *np = netdev_priv(dev);
2837         u8 __iomem *base = get_hwbase(dev);
2838         u32 events;
2839         int i;
2840
2841         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2842
2843         for (i=0; ; i++) {
2844                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2845                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2846                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2847                 } else {
2848                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2849                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2850                 }
2851                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2852                 if (!(events & np->irqmask))
2853                         break;
2854
2855                 spin_lock(&np->lock);
2856                 nv_tx_done(dev);
2857                 spin_unlock(&np->lock);
2858
2859 #ifdef CONFIG_FORCEDETH_NAPI
2860                 if (events & NVREG_IRQ_RX_ALL) {
2861                         netif_rx_schedule(dev);
2862
2863                         /* Disable furthur receive irq's */
2864                         spin_lock(&np->lock);
2865                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2866
2867                         if (np->msi_flags & NV_MSI_X_ENABLED)
2868                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2869                         else
2870                                 writel(np->irqmask, base + NvRegIrqMask);
2871                         spin_unlock(&np->lock);
2872                 }
2873 #else
2874                 if (nv_rx_process(dev, dev->weight)) {
2875                         if (unlikely(nv_alloc_rx(dev))) {
2876                                 spin_lock(&np->lock);
2877                                 if (!np->in_shutdown)
2878                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2879                                 spin_unlock(&np->lock);
2880                         }
2881                 }
2882 #endif
2883                 if (unlikely(events & NVREG_IRQ_LINK)) {
2884                         spin_lock(&np->lock);
2885                         nv_link_irq(dev);
2886                         spin_unlock(&np->lock);
2887                 }
2888                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2889                         spin_lock(&np->lock);
2890                         nv_linkchange(dev);
2891                         spin_unlock(&np->lock);
2892                         np->link_timeout = jiffies + LINK_TIMEOUT;
2893                 }
2894                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
2895                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2896                                                 dev->name, events);
2897                 }
2898                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
2899                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2900                                                 dev->name, events);
2901                 }
2902                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2903                         spin_lock(&np->lock);
2904                         /* disable interrupts on the nic */
2905                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2906                                 writel(0, base + NvRegIrqMask);
2907                         else
2908                                 writel(np->irqmask, base + NvRegIrqMask);
2909                         pci_push(base);
2910
2911                         if (!np->in_shutdown) {
2912                                 np->nic_poll_irq = np->irqmask;
2913                                 np->recover_error = 1;
2914                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2915                         }
2916                         spin_unlock(&np->lock);
2917                         break;
2918                 }
2919                 if (unlikely(i > max_interrupt_work)) {
2920                         spin_lock(&np->lock);
2921                         /* disable interrupts on the nic */
2922                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2923                                 writel(0, base + NvRegIrqMask);
2924                         else
2925                                 writel(np->irqmask, base + NvRegIrqMask);
2926                         pci_push(base);
2927
2928                         if (!np->in_shutdown) {
2929                                 np->nic_poll_irq = np->irqmask;
2930                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2931                         }
2932                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2933                         spin_unlock(&np->lock);
2934                         break;
2935                 }
2936
2937         }
2938         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2939
2940         return IRQ_RETVAL(i);
2941 }
2942
2943 #define TX_WORK_PER_LOOP  64
2944 #define RX_WORK_PER_LOOP  64
2945 /**
2946  * All _optimized functions are used to help increase performance
2947  * (reduce CPU and increase throughput). They use descripter version 3,
2948  * compiler directives, and reduce memory accesses.
2949  */
2950 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
2951 {
2952         struct net_device *dev = (struct net_device *) data;
2953         struct fe_priv *np = netdev_priv(dev);
2954         u8 __iomem *base = get_hwbase(dev);
2955         u32 events;
2956         int i;
2957
2958         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
2959
2960         for (i=0; ; i++) {
2961                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2962                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2963                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2964                 } else {
2965                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2966                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2967                 }
2968                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2969                 if (!(events & np->irqmask))
2970                         break;
2971
2972                 spin_lock(&np->lock);
2973                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
2974                 spin_unlock(&np->lock);
2975
2976 #ifdef CONFIG_FORCEDETH_NAPI
2977                 if (events & NVREG_IRQ_RX_ALL) {
2978                         netif_rx_schedule(dev);
2979
2980                         /* Disable furthur receive irq's */
2981                         spin_lock(&np->lock);
2982                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2983
2984                         if (np->msi_flags & NV_MSI_X_ENABLED)
2985                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2986                         else
2987                                 writel(np->irqmask, base + NvRegIrqMask);
2988                         spin_unlock(&np->lock);
2989                 }
2990 #else
2991                 if (nv_rx_process_optimized(dev, dev->weight)) {
2992                         if (unlikely(nv_alloc_rx_optimized(dev))) {
2993                                 spin_lock(&np->lock);
2994                                 if (!np->in_shutdown)
2995                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2996                                 spin_unlock(&np->lock);
2997                         }
2998                 }
2999 #endif
3000                 if (unlikely(events & NVREG_IRQ_LINK)) {
3001                         spin_lock(&np->lock);
3002                         nv_link_irq(dev);
3003                         spin_unlock(&np->lock);
3004                 }
3005                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3006                         spin_lock(&np->lock);
3007                         nv_linkchange(dev);
3008                         spin_unlock(&np->lock);
3009                         np->link_timeout = jiffies + LINK_TIMEOUT;
3010                 }
3011                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3012                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3013                                                 dev->name, events);
3014                 }
3015                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3016                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3017                                                 dev->name, events);
3018                 }
3019                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3020                         spin_lock(&np->lock);
3021                         /* disable interrupts on the nic */
3022                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3023                                 writel(0, base + NvRegIrqMask);
3024                         else
3025                                 writel(np->irqmask, base + NvRegIrqMask);
3026                         pci_push(base);
3027
3028                         if (!np->in_shutdown) {
3029                                 np->nic_poll_irq = np->irqmask;
3030                                 np->recover_error = 1;
3031                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3032                         }
3033                         spin_unlock(&np->lock);
3034                         break;
3035                 }
3036
3037                 if (unlikely(i > max_interrupt_work)) {
3038                         spin_lock(&np->lock);
3039                         /* disable interrupts on the nic */
3040                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3041                                 writel(0, base + NvRegIrqMask);
3042                         else
3043                                 writel(np->irqmask, base + NvRegIrqMask);
3044                         pci_push(base);
3045
3046                         if (!np->in_shutdown) {
3047                                 np->nic_poll_irq = np->irqmask;
3048                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3049                         }
3050                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3051                         spin_unlock(&np->lock);
3052                         break;
3053                 }
3054
3055         }
3056         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3057
3058         return IRQ_RETVAL(i);
3059 }
3060
3061 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3062 {
3063         struct net_device *dev = (struct net_device *) data;
3064         struct fe_priv *np = netdev_priv(dev);
3065         u8 __iomem *base = get_hwbase(dev);
3066         u32 events;
3067         int i;
3068         unsigned long flags;
3069
3070         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3071
3072         for (i=0; ; i++) {
3073                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3074                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3075                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3076                 if (!(events & np->irqmask))
3077                         break;
3078
3079                 spin_lock_irqsave(&np->lock, flags);
3080                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3081                 spin_unlock_irqrestore(&np->lock, flags);
3082
3083                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3084                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3085                                                 dev->name, events);
3086                 }
3087                 if (unlikely(i > max_interrupt_work)) {
3088                         spin_lock_irqsave(&np->lock, flags);
3089                         /* disable interrupts on the nic */
3090                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3091                         pci_push(base);
3092
3093                         if (!np->in_shutdown) {
3094                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3095                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3096                         }
3097                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3098                         spin_unlock_irqrestore(&np->lock, flags);
3099                         break;
3100                 }
3101
3102         }
3103         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3104
3105         return IRQ_RETVAL(i);
3106 }
3107
3108 #ifdef CONFIG_FORCEDETH_NAPI
3109 static int nv_napi_poll(struct net_device *dev, int *budget)
3110 {
3111         int pkts, limit = min(*budget, dev->quota);
3112         struct fe_priv *np = netdev_priv(dev);
3113         u8 __iomem *base = get_hwbase(dev);
3114         unsigned long flags;
3115         int retcode;
3116
3117         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3118                 pkts = nv_rx_process(dev, limit);
3119                 retcode = nv_alloc_rx(dev);
3120         } else {
3121                 pkts = nv_rx_process_optimized(dev, limit);
3122                 retcode = nv_alloc_rx_optimized(dev);
3123         }
3124
3125         if (retcode) {
3126                 spin_lock_irqsave(&np->lock, flags);
3127                 if (!np->in_shutdown)
3128                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3129                 spin_unlock_irqrestore(&np->lock, flags);
3130         }
3131
3132         if (pkts < limit) {
3133                 /* all done, no more packets present */
3134                 netif_rx_complete(dev);
3135
3136                 /* re-enable receive interrupts */
3137                 spin_lock_irqsave(&np->lock, flags);
3138
3139                 np->irqmask |= NVREG_IRQ_RX_ALL;
3140                 if (np->msi_flags & NV_MSI_X_ENABLED)
3141                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3142                 else
3143                         writel(np->irqmask, base + NvRegIrqMask);
3144
3145                 spin_unlock_irqrestore(&np->lock, flags);
3146                 return 0;
3147         } else {
3148                 /* used up our quantum, so reschedule */
3149                 dev->quota -= pkts;
3150                 *budget -= pkts;
3151                 return 1;
3152         }
3153 }
3154 #endif
3155
3156 #ifdef CONFIG_FORCEDETH_NAPI
3157 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3158 {
3159         struct net_device *dev = (struct net_device *) data;
3160         u8 __iomem *base = get_hwbase(dev);
3161         u32 events;
3162
3163         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3164         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3165
3166         if (events) {
3167                 netif_rx_schedule(dev);
3168                 /* disable receive interrupts on the nic */
3169                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3170                 pci_push(base);
3171         }
3172         return IRQ_HANDLED;
3173 }
3174 #else
3175 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3176 {
3177         struct net_device *dev = (struct net_device *) data;
3178         struct fe_priv *np = netdev_priv(dev);
3179         u8 __iomem *base = get_hwbase(dev);
3180         u32 events;
3181         int i;
3182         unsigned long flags;
3183
3184         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3185
3186         for (i=0; ; i++) {
3187                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3188                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3189                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3190                 if (!(events & np->irqmask))
3191                         break;
3192
3193                 if (nv_rx_process_optimized(dev, dev->weight)) {
3194                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3195                                 spin_lock_irqsave(&np->lock, flags);
3196                                 if (!np->in_shutdown)
3197                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3198                                 spin_unlock_irqrestore(&np->lock, flags);
3199                         }
3200                 }
3201
3202                 if (unlikely(i > max_interrupt_work)) {
3203                         spin_lock_irqsave(&np->lock, flags);
3204                         /* disable interrupts on the nic */
3205                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3206                         pci_push(base);
3207
3208                         if (!np->in_shutdown) {
3209                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3210                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3211                         }
3212                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3213                         spin_unlock_irqrestore(&np->lock, flags);
3214                         break;
3215                 }
3216         }
3217         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3218
3219         return IRQ_RETVAL(i);
3220 }
3221 #endif
3222
3223 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3224 {
3225         struct net_device *dev = (struct net_device *) data;
3226         struct fe_priv *np = netdev_priv(dev);
3227         u8 __iomem *base = get_hwbase(dev);
3228         u32 events;
3229         int i;
3230         unsigned long flags;
3231
3232         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3233
3234         for (i=0; ; i++) {
3235                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3236                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3237                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3238                 if (!(events & np->irqmask))
3239                         break;
3240
3241                 /* check tx in case we reached max loop limit in tx isr */
3242                 spin_lock_irqsave(&np->lock, flags);
3243                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3244                 spin_unlock_irqrestore(&np->lock, flags);
3245
3246                 if (events & NVREG_IRQ_LINK) {
3247                         spin_lock_irqsave(&np->lock, flags);
3248                         nv_link_irq(dev);
3249                         spin_unlock_irqrestore(&np->lock, flags);
3250                 }
3251                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3252                         spin_lock_irqsave(&np->lock, flags);
3253                         nv_linkchange(dev);
3254                         spin_unlock_irqrestore(&np->lock, flags);
3255                         np->link_timeout = jiffies + LINK_TIMEOUT;
3256                 }
3257                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3258                         spin_lock_irq(&np->lock);
3259                         /* disable interrupts on the nic */
3260                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3261                         pci_push(base);
3262
3263                         if (!np->in_shutdown) {
3264                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3265                                 np->recover_error = 1;
3266                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3267                         }
3268                         spin_unlock_irq(&np->lock);
3269                         break;
3270                 }
3271                 if (events & (NVREG_IRQ_UNKNOWN)) {
3272                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3273                                                 dev->name, events);
3274                 }
3275                 if (unlikely(i > max_interrupt_work)) {
3276                         spin_lock_irqsave(&np->lock, flags);
3277                         /* disable interrupts on the nic */
3278                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3279                         pci_push(base);
3280
3281                         if (!np->in_shutdown) {
3282                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3283                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3284                         }
3285                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3286                         spin_unlock_irqrestore(&np->lock, flags);
3287                         break;
3288                 }
3289
3290         }
3291         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3292
3293         return IRQ_RETVAL(i);
3294 }
3295
3296 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3297 {
3298         struct net_device *dev = (struct net_device *) data;
3299         struct fe_priv *np = netdev_priv(dev);
3300         u8 __iomem *base = get_hwbase(dev);
3301         u32 events;
3302
3303         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3304
3305         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3306                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3307                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3308         } else {
3309                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3310                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3311         }
3312         pci_push(base);
3313         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3314         if (!(events & NVREG_IRQ_TIMER))
3315                 return IRQ_RETVAL(0);
3316
3317         spin_lock(&np->lock);
3318         np->intr_test = 1;
3319         spin_unlock(&np->lock);
3320
3321         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3322
3323         return IRQ_RETVAL(1);
3324 }
3325
3326 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3327 {
3328         u8 __iomem *base = get_hwbase(dev);
3329         int i;
3330         u32 msixmap = 0;
3331
3332         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3333          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3334          * the remaining 8 interrupts.
3335          */
3336         for (i = 0; i < 8; i++) {
3337                 if ((irqmask >> i) & 0x1) {
3338                         msixmap |= vector << (i << 2);
3339                 }
3340         }
3341         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3342
3343         msixmap = 0;
3344         for (i = 0; i < 8; i++) {
3345                 if ((irqmask >> (i + 8)) & 0x1) {
3346                         msixmap |= vector << (i << 2);
3347                 }
3348         }
3349         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3350 }
3351
3352 static int nv_request_irq(struct net_device *dev, int intr_test)
3353 {
3354         struct fe_priv *np = get_nvpriv(dev);
3355         u8 __iomem *base = get_hwbase(dev);
3356         int ret = 1;
3357         int i;
3358         irqreturn_t (*handler)(int foo, void *data);
3359
3360         if (intr_test) {
3361                 handler = nv_nic_irq_test;
3362         } else {
3363                 if (np->desc_ver == DESC_VER_3)
3364                         handler = nv_nic_irq_optimized;
3365                 else
3366                         handler = nv_nic_irq;
3367         }
3368
3369         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3370                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3371                         np->msi_x_entry[i].entry = i;
3372                 }
3373                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3374                         np->msi_flags |= NV_MSI_X_ENABLED;
3375                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3376                                 /* Request irq for rx handling */
3377                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3378                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3379                                         pci_disable_msix(np->pci_dev);
3380                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3381                                         goto out_err;
3382                                 }
3383                                 /* Request irq for tx handling */
3384                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3385                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3386                                         pci_disable_msix(np->pci_dev);
3387                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3388                                         goto out_free_rx;
3389                                 }
3390                                 /* Request irq for link and timer handling */
3391                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3392                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3393                                         pci_disable_msix(np->pci_dev);
3394                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3395                                         goto out_free_tx;
3396                                 }
3397                                 /* map interrupts to their respective vector */
3398                                 writel(0, base + NvRegMSIXMap0);
3399                                 writel(0, base + NvRegMSIXMap1);
3400                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3401                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3402                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3403                         } else {
3404                                 /* Request irq for all interrupts */
3405                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3406                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3407                                         pci_disable_msix(np->pci_dev);
3408                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3409                                         goto out_err;
3410                                 }
3411
3412                                 /* map interrupts to vector 0 */
3413                                 writel(0, base + NvRegMSIXMap0);
3414                                 writel(0, base + NvRegMSIXMap1);
3415                         }
3416                 }
3417         }
3418         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3419                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3420                         np->msi_flags |= NV_MSI_ENABLED;
3421                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3422                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3423                                 pci_disable_msi(np->pci_dev);
3424                                 np->msi_flags &= ~NV_MSI_ENABLED;
3425                                 goto out_err;
3426                         }
3427
3428                         /* map interrupts to vector 0 */
3429                         writel(0, base + NvRegMSIMap0);
3430                         writel(0, base + NvRegMSIMap1);
3431                         /* enable msi vector 0 */
3432                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3433                 }
3434         }
3435         if (ret != 0) {
3436                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3437                         goto out_err;
3438
3439         }
3440
3441         return 0;
3442 out_free_tx:
3443         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3444 out_free_rx:
3445         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3446 out_err:
3447         return 1;
3448 }
3449
3450 static void nv_free_irq(struct net_device *dev)
3451 {
3452         struct fe_priv *np = get_nvpriv(dev);
3453         int i;
3454
3455         if (np->msi_flags & NV_MSI_X_ENABLED) {
3456                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3457                         free_irq(np->msi_x_entry[i].vector, dev);
3458                 }
3459                 pci_disable_msix(np->pci_dev);
3460                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3461         } else {
3462                 free_irq(np->pci_dev->irq, dev);
3463                 if (np->msi_flags & NV_MSI_ENABLED) {
3464                         pci_disable_msi(np->pci_dev);
3465                         np->msi_flags &= ~NV_MSI_ENABLED;
3466                 }
3467         }
3468 }
3469
3470 static void nv_do_nic_poll(unsigned long data)
3471 {
3472         struct net_device *dev = (struct net_device *) data;
3473         struct fe_priv *np = netdev_priv(dev);
3474         u8 __iomem *base = get_hwbase(dev);
3475         u32 mask = 0;
3476
3477         /*
3478          * First disable irq(s) and then
3479          * reenable interrupts on the nic, we have to do this before calling
3480          * nv_nic_irq because that may decide to do otherwise
3481          */
3482
3483         if (!using_multi_irqs(dev)) {
3484                 if (np->msi_flags & NV_MSI_X_ENABLED)
3485                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3486                 else
3487                         disable_irq_lockdep(dev->irq);
3488                 mask = np->irqmask;
3489         } else {
3490                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3491                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3492                         mask |= NVREG_IRQ_RX_ALL;
3493                 }
3494                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3495                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3496                         mask |= NVREG_IRQ_TX_ALL;
3497                 }
3498                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3499                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3500                         mask |= NVREG_IRQ_OTHER;
3501                 }
3502         }
3503         np->nic_poll_irq = 0;
3504
3505         if (np->recover_error) {
3506                 np->recover_error = 0;
3507                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3508                 if (netif_running(dev)) {
3509                         netif_tx_lock_bh(dev);
3510                         spin_lock(&np->lock);
3511                         /* stop engines */
3512                         nv_stop_rx(dev);
3513                         nv_stop_tx(dev);
3514                         nv_txrx_reset(dev);
3515                         /* drain rx queue */
3516                         nv_drain_rx(dev);
3517                         nv_drain_tx(dev);
3518                         /* reinit driver view of the rx queue */
3519                         set_bufsize(dev);
3520                         if (nv_init_ring(dev)) {
3521                                 if (!np->in_shutdown)
3522                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3523                         }
3524                         /* reinit nic view of the rx queue */
3525                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3526                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3527                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3528                                 base + NvRegRingSizes);
3529                         pci_push(base);
3530                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3531                         pci_push(base);
3532
3533                         /* restart rx engine */
3534                         nv_start_rx(dev);
3535                         nv_start_tx(dev);
3536                         spin_unlock(&np->lock);
3537                         netif_tx_unlock_bh(dev);
3538                 }
3539         }
3540
3541         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3542
3543         writel(mask, base + NvRegIrqMask);
3544         pci_push(base);
3545
3546         if (!using_multi_irqs(dev)) {
3547                 if (np->desc_ver == DESC_VER_3)
3548                         nv_nic_irq_optimized(0, dev);
3549                 else
3550                         nv_nic_irq(0, dev);
3551                 if (np->msi_flags & NV_MSI_X_ENABLED)
3552                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3553                 else
3554                         enable_irq_lockdep(dev->irq);
3555         } else {
3556                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3557                         nv_nic_irq_rx(0, dev);
3558                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3559                 }
3560                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3561                         nv_nic_irq_tx(0, dev);
3562                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3563                 }
3564                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3565                         nv_nic_irq_other(0, dev);
3566                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3567                 }
3568         }
3569 }
3570
3571 #ifdef CONFIG_NET_POLL_CONTROLLER
3572 static void nv_poll_controller(struct net_device *dev)
3573 {
3574         nv_do_nic_poll((unsigned long) dev);
3575 }
3576 #endif
3577
3578 static void nv_do_stats_poll(unsigned long data)
3579 {
3580         struct net_device *dev = (struct net_device *) data;
3581         struct fe_priv *np = netdev_priv(dev);
3582
3583         nv_get_hw_stats(dev);
3584
3585         if (!np->in_shutdown)
3586                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3587 }
3588
3589 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3590 {
3591         struct fe_priv *np = netdev_priv(dev);
3592         strcpy(info->driver, "forcedeth");
3593         strcpy(info->version, FORCEDETH_VERSION);
3594         strcpy(info->bus_info, pci_name(np->pci_dev));
3595 }
3596
3597 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3598 {
3599         struct fe_priv *np = netdev_priv(dev);
3600         wolinfo->supported = WAKE_MAGIC;
3601
3602         spin_lock_irq(&np->lock);
3603         if (np->wolenabled)
3604                 wolinfo->wolopts = WAKE_MAGIC;
3605         spin_unlock_irq(&np->lock);
3606 }
3607
3608 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3609 {
3610         struct fe_priv *np = netdev_priv(dev);
3611         u8 __iomem *base = get_hwbase(dev);
3612         u32 flags = 0;
3613
3614         if (wolinfo->wolopts == 0) {
3615                 np->wolenabled = 0;
3616         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3617                 np->wolenabled = 1;
3618                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3619         }
3620         if (netif_running(dev)) {
3621                 spin_lock_irq(&np->lock);
3622                 writel(flags, base + NvRegWakeUpFlags);
3623                 spin_unlock_irq(&np->lock);
3624         }
3625         return 0;
3626 }
3627
3628 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3629 {
3630         struct fe_priv *np = netdev_priv(dev);
3631         int adv;
3632
3633         spin_lock_irq(&np->lock);
3634         ecmd->port = PORT_MII;
3635         if (!netif_running(dev)) {
3636                 /* We do not track link speed / duplex setting if the
3637                  * interface is disabled. Force a link check */
3638                 if (nv_update_linkspeed(dev)) {
3639                         if (!netif_carrier_ok(dev))
3640                                 netif_carrier_on(dev);
3641                 } else {
3642                         if (netif_carrier_ok(dev))
3643                                 netif_carrier_off(dev);
3644                 }
3645         }
3646
3647         if (netif_carrier_ok(dev)) {
3648                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3649                 case NVREG_LINKSPEED_10:
3650                         ecmd->speed = SPEED_10;
3651                         break;
3652                 case NVREG_LINKSPEED_100:
3653                         ecmd->speed = SPEED_100;
3654                         break;
3655                 case NVREG_LINKSPEED_1000:
3656                         ecmd->speed = SPEED_1000;
3657                         break;
3658                 }
3659                 ecmd->duplex = DUPLEX_HALF;
3660                 if (np->duplex)
3661                         ecmd->duplex = DUPLEX_FULL;
3662         } else {
3663                 ecmd->speed = -1;
3664                 ecmd->duplex = -1;
3665         }
3666
3667         ecmd->autoneg = np->autoneg;
3668
3669         ecmd->advertising = ADVERTISED_MII;
3670         if (np->autoneg) {
3671                 ecmd->advertising |= ADVERTISED_Autoneg;
3672                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3673                 if (adv & ADVERTISE_10HALF)
3674                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3675                 if (adv & ADVERTISE_10FULL)
3676                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3677                 if (adv & ADVERTISE_100HALF)
3678                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3679                 if (adv & ADVERTISE_100FULL)
3680                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3681                 if (np->gigabit == PHY_GIGABIT) {
3682                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3683                         if (adv & ADVERTISE_1000FULL)
3684                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3685                 }
3686         }
3687         ecmd->supported = (SUPPORTED_Autoneg |
3688                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3689                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3690                 SUPPORTED_MII);
3691         if (np->gigabit == PHY_GIGABIT)
3692                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3693
3694         ecmd->phy_address = np->phyaddr;
3695         ecmd->transceiver = XCVR_EXTERNAL;
3696
3697         /* ignore maxtxpkt, maxrxpkt for now */
3698         spin_unlock_irq(&np->lock);
3699         return 0;
3700 }
3701
3702 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3703 {
3704         struct fe_priv *np = netdev_priv(dev);
3705
3706         if (ecmd->port != PORT_MII)
3707                 return -EINVAL;
3708         if (ecmd->transceiver != XCVR_EXTERNAL)
3709                 return -EINVAL;
3710         if (ecmd->phy_address != np->phyaddr) {
3711                 /* TODO: support switching between multiple phys. Should be
3712                  * trivial, but not enabled due to lack of test hardware. */
3713                 return -EINVAL;
3714         }
3715         if (ecmd->autoneg == AUTONEG_ENABLE) {
3716                 u32 mask;
3717
3718                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3719                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3720                 if (np->gigabit == PHY_GIGABIT)
3721                         mask |= ADVERTISED_1000baseT_Full;
3722
3723                 if ((ecmd->advertising & mask) == 0)
3724                         return -EINVAL;
3725
3726         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3727                 /* Note: autonegotiation disable, speed 1000 intentionally
3728                  * forbidden - noone should need that. */
3729
3730                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3731                         return -EINVAL;
3732                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3733                         return -EINVAL;
3734         } else {
3735                 return -EINVAL;
3736         }
3737
3738         netif_carrier_off(dev);
3739         if (netif_running(dev)) {
3740                 nv_disable_irq(dev);
3741                 netif_tx_lock_bh(dev);
3742                 spin_lock(&np->lock);
3743                 /* stop engines */
3744                 nv_stop_rx(dev);
3745                 nv_stop_tx(dev);
3746                 spin_unlock(&np->lock);
3747                 netif_tx_unlock_bh(dev);
3748         }
3749
3750         if (ecmd->autoneg == AUTONEG_ENABLE) {
3751                 int adv, bmcr;
3752
3753                 np->autoneg = 1;
3754
3755                 /* advertise only what has been requested */
3756                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3757                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3758                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3759                         adv |= ADVERTISE_10HALF;
3760                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3761                         adv |= ADVERTISE_10FULL;
3762                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3763                         adv |= ADVERTISE_100HALF;
3764                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3765                         adv |= ADVERTISE_100FULL;
3766                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3767                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3768                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3769                         adv |=  ADVERTISE_PAUSE_ASYM;
3770                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3771
3772                 if (np->gigabit == PHY_GIGABIT) {
3773                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3774                         adv &= ~ADVERTISE_1000FULL;
3775                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3776                                 adv |= ADVERTISE_1000FULL;
3777                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3778                 }
3779
3780                 if (netif_running(dev))
3781                         printk(KERN_INFO "%s: link down.\n", dev->name);
3782                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3783                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3784                         bmcr |= BMCR_ANENABLE;
3785                         /* reset the phy in order for settings to stick,
3786                          * and cause autoneg to start */
3787                         if (phy_reset(dev, bmcr)) {
3788                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3789                                 return -EINVAL;
3790                         }
3791                 } else {
3792                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3793                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3794                 }
3795         } else {
3796                 int adv, bmcr;
3797
3798                 np->autoneg = 0;
3799
3800                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3801                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3802                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3803                         adv |= ADVERTISE_10HALF;
3804                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3805                         adv |= ADVERTISE_10FULL;
3806                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3807                         adv |= ADVERTISE_100HALF;
3808                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3809                         adv |= ADVERTISE_100FULL;
3810                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3811                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3812                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3813                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3814                 }
3815                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3816                         adv |=  ADVERTISE_PAUSE_ASYM;
3817                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3818                 }
3819                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3820                 np->fixed_mode = adv;
3821
3822                 if (np->gigabit == PHY_GIGABIT) {
3823                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3824                         adv &= ~ADVERTISE_1000FULL;
3825                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3826                 }
3827
3828                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3829                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3830                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3831                         bmcr |= BMCR_FULLDPLX;
3832                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3833                         bmcr |= BMCR_SPEED100;
3834                 if (np->phy_oui == PHY_OUI_MARVELL) {
3835                         /* reset the phy in order for forced mode settings to stick */
3836                         if (phy_reset(dev, bmcr)) {
3837                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3838                                 return -EINVAL;
3839                         }
3840                 } else {
3841                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3842                         if (netif_running(dev)) {
3843                                 /* Wait a bit and then reconfigure the nic. */
3844                                 udelay(10);
3845                                 nv_linkchange(dev);
3846                         }
3847                 }
3848         }
3849
3850         if (netif_running(dev)) {
3851                 nv_start_rx(dev);
3852                 nv_start_tx(dev);
3853                 nv_enable_irq(dev);
3854         }
3855
3856         return 0;
3857 }
3858
3859 #define FORCEDETH_REGS_VER      1
3860
3861 static int nv_get_regs_len(struct net_device *dev)
3862 {
3863         struct fe_priv *np = netdev_priv(dev);
3864         return np->register_size;
3865 }
3866
3867 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3868 {
3869         struct fe_priv *np = netdev_priv(dev);
3870         u8 __iomem *base = get_hwbase(dev);
3871         u32 *rbuf = buf;
3872         int i;
3873
3874         regs->version = FORCEDETH_REGS_VER;
3875         spin_lock_irq(&np->lock);
3876         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3877                 rbuf[i] = readl(base + i*sizeof(u32));
3878         spin_unlock_irq(&np->lock);
3879 }
3880
3881 static int nv_nway_reset(struct net_device *dev)
3882 {
3883         struct fe_priv *np = netdev_priv(dev);
3884         int ret;
3885
3886         if (np->autoneg) {
3887                 int bmcr;
3888
3889                 netif_carrier_off(dev);
3890                 if (netif_running(dev)) {
3891                         nv_disable_irq(dev);
3892                         netif_tx_lock_bh(dev);
3893                         spin_lock(&np->lock);
3894                         /* stop engines */
3895                         nv_stop_rx(dev);
3896                         nv_stop_tx(dev);
3897                         spin_unlock(&np->lock);
3898                         netif_tx_unlock_bh(dev);
3899                         printk(KERN_INFO "%s: link down.\n", dev->name);
3900                 }
3901
3902                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3903                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3904                         bmcr |= BMCR_ANENABLE;
3905                         /* reset the phy in order for settings to stick*/
3906                         if (phy_reset(dev, bmcr)) {
3907                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3908                                 return -EINVAL;
3909                         }
3910                 } else {
3911                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3912                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3913                 }
3914
3915                 if (netif_running(dev)) {
3916                         nv_start_rx(dev);
3917                         nv_start_tx(dev);
3918                         nv_enable_irq(dev);
3919                 }
3920                 ret = 0;
3921         } else {
3922                 ret = -EINVAL;
3923         }
3924
3925         return ret;
3926 }
3927
3928 static int nv_set_tso(struct net_device *dev, u32 value)
3929 {
3930         struct fe_priv *np = netdev_priv(dev);
3931
3932         if ((np->driver_data & DEV_HAS_CHECKSUM))
3933                 return ethtool_op_set_tso(dev, value);
3934         else
3935                 return -EOPNOTSUPP;
3936 }
3937
3938 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3939 {
3940         struct fe_priv *np = netdev_priv(dev);
3941
3942         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3943         ring->rx_mini_max_pending = 0;
3944         ring->rx_jumbo_max_pending = 0;
3945         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3946
3947         ring->rx_pending = np->rx_ring_size;
3948         ring->rx_mini_pending = 0;
3949         ring->rx_jumbo_pending = 0;
3950         ring->tx_pending = np->tx_ring_size;
3951 }
3952
3953 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3954 {
3955         struct fe_priv *np = netdev_priv(dev);
3956         u8 __iomem *base = get_hwbase(dev);
3957         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3958         dma_addr_t ring_addr;
3959
3960         if (ring->rx_pending < RX_RING_MIN ||
3961             ring->tx_pending < TX_RING_MIN ||
3962             ring->rx_mini_pending != 0 ||
3963             ring->rx_jumbo_pending != 0 ||
3964             (np->desc_ver == DESC_VER_1 &&
3965              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3966               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3967             (np->desc_ver != DESC_VER_1 &&
3968              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3969               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3970                 return -EINVAL;
3971         }
3972
3973         /* allocate new rings */
3974         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3975                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3976                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3977                                             &ring_addr);
3978         } else {
3979                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3980                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3981                                             &ring_addr);
3982         }
3983         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3984         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3985         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3986                 /* fall back to old rings */
3987                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3988                         if (rxtx_ring)
3989                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3990                                                     rxtx_ring, ring_addr);
3991                 } else {
3992                         if (rxtx_ring)
3993                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3994                                                     rxtx_ring, ring_addr);
3995                 }
3996                 if (rx_skbuff)
3997                         kfree(rx_skbuff);
3998                 if (tx_skbuff)
3999                         kfree(tx_skbuff);
4000                 goto exit;
4001         }
4002
4003         if (netif_running(dev)) {
4004                 nv_disable_irq(dev);
4005                 netif_tx_lock_bh(dev);
4006                 spin_lock(&np->lock);
4007                 /* stop engines */
4008                 nv_stop_rx(dev);
4009                 nv_stop_tx(dev);
4010                 nv_txrx_reset(dev);
4011                 /* drain queues */
4012                 nv_drain_rx(dev);
4013                 nv_drain_tx(dev);
4014                 /* delete queues */
4015                 free_rings(dev);
4016         }
4017
4018         /* set new values */
4019         np->rx_ring_size = ring->rx_pending;
4020         np->tx_ring_size = ring->tx_pending;
4021         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4022                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4023                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4024         } else {
4025                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4026                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4027         }
4028         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4029         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4030         np->ring_addr = ring_addr;
4031
4032         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4033         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4034
4035         if (netif_running(dev)) {
4036                 /* reinit driver view of the queues */
4037                 set_bufsize(dev);
4038                 if (nv_init_ring(dev)) {
4039                         if (!np->in_shutdown)
4040                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4041                 }
4042
4043                 /* reinit nic view of the queues */
4044                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4045                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4046                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4047                         base + NvRegRingSizes);
4048                 pci_push(base);
4049                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4050                 pci_push(base);
4051
4052                 /* restart engines */
4053                 nv_start_rx(dev);
4054                 nv_start_tx(dev);
4055                 spin_unlock(&np->lock);
4056                 netif_tx_unlock_bh(dev);
4057                 nv_enable_irq(dev);
4058         }
4059         return 0;
4060 exit:
4061         return -ENOMEM;
4062 }
4063
4064 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4065 {
4066         struct fe_priv *np = netdev_priv(dev);
4067
4068         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4069         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4070         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4071 }
4072
4073 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4074 {
4075         struct fe_priv *np = netdev_priv(dev);
4076         int adv, bmcr;
4077
4078         if ((!np->autoneg && np->duplex == 0) ||
4079             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4080                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4081                        dev->name);
4082                 return -EINVAL;
4083         }
4084         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4085                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4086                 return -EINVAL;
4087         }
4088
4089         netif_carrier_off(dev);
4090         if (netif_running(dev)) {
4091                 nv_disable_irq(dev);
4092                 netif_tx_lock_bh(dev);
4093                 spin_lock(&np->lock);
4094                 /* stop engines */
4095                 nv_stop_rx(dev);
4096                 nv_stop_tx(dev);
4097                 spin_unlock(&np->lock);
4098                 netif_tx_unlock_bh(dev);
4099         }
4100
4101         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4102         if (pause->rx_pause)
4103                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4104         if (pause->tx_pause)
4105                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4106
4107         if (np->autoneg && pause->autoneg) {
4108                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4109
4110                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4111                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4112                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4113                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4114                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4115                         adv |=  ADVERTISE_PAUSE_ASYM;
4116                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4117
4118                 if (netif_running(dev))
4119                         printk(KERN_INFO "%s: link down.\n", dev->name);
4120                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4121                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4122                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4123         } else {
4124                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4125                 if (pause->rx_pause)
4126                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4127                 if (pause->tx_pause)
4128                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4129
4130                 if (!netif_running(dev))
4131                         nv_update_linkspeed(dev);
4132                 else
4133                         nv_update_pause(dev, np->pause_flags);
4134         }
4135
4136         if (netif_running(dev)) {
4137                 nv_start_rx(dev);
4138                 nv_start_tx(dev);
4139                 nv_enable_irq(dev);
4140         }
4141         return 0;
4142 }
4143
4144 static u32 nv_get_rx_csum(struct net_device *dev)
4145 {
4146         struct fe_priv *np = netdev_priv(dev);
4147         return (np->rx_csum) != 0;
4148 }
4149
4150 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4151 {
4152         struct fe_priv *np = netdev_priv(dev);
4153         u8 __iomem *base = get_hwbase(dev);
4154         int retcode = 0;
4155
4156         if (np->driver_data & DEV_HAS_CHECKSUM) {
4157                 if (data) {
4158                         np->rx_csum = 1;
4159                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4160                 } else {
4161                         np->rx_csum = 0;
4162                         /* vlan is dependent on rx checksum offload */
4163                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4164                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4165                 }
4166                 if (netif_running(dev)) {
4167                         spin_lock_irq(&np->lock);
4168                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4169                         spin_unlock_irq(&np->lock);
4170                 }
4171         } else {
4172                 return -EINVAL;
4173         }
4174
4175         return retcode;
4176 }
4177
4178 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4179 {
4180         struct fe_priv *np = netdev_priv(dev);
4181
4182         if (np->driver_data & DEV_HAS_CHECKSUM)
4183                 return ethtool_op_set_tx_hw_csum(dev, data);
4184         else
4185                 return -EOPNOTSUPP;
4186 }
4187
4188 static int nv_set_sg(struct net_device *dev, u32 data)
4189 {
4190         struct fe_priv *np = netdev_priv(dev);
4191
4192         if (np->driver_data & DEV_HAS_CHECKSUM)
4193                 return ethtool_op_set_sg(dev, data);
4194         else
4195                 return -EOPNOTSUPP;
4196 }
4197
4198 static int nv_get_stats_count(struct net_device *dev)
4199 {
4200         struct fe_priv *np = netdev_priv(dev);
4201
4202         if (np->driver_data & DEV_HAS_STATISTICS_V1)
4203                 return NV_DEV_STATISTICS_V1_COUNT;
4204         else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4205                 return NV_DEV_STATISTICS_V2_COUNT;
4206         else
4207                 return 0;
4208 }
4209
4210 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4211 {
4212         struct fe_priv *np = netdev_priv(dev);
4213
4214         /* update stats */
4215         nv_do_stats_poll((unsigned long)dev);
4216
4217         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
4218 }
4219
4220 static int nv_self_test_count(struct net_device *dev)
4221 {
4222         struct fe_priv *np = netdev_priv(dev);
4223
4224         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4225                 return NV_TEST_COUNT_EXTENDED;
4226         else
4227                 return NV_TEST_COUNT_BASE;
4228 }
4229
4230 static int nv_link_test(struct net_device *dev)
4231 {
4232         struct fe_priv *np = netdev_priv(dev);
4233         int mii_status;
4234
4235         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4236         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4237
4238         /* check phy link status */
4239         if (!(mii_status & BMSR_LSTATUS))
4240                 return 0;
4241         else
4242                 return 1;
4243 }
4244
4245 static int nv_register_test(struct net_device *dev)
4246 {
4247         u8 __iomem *base = get_hwbase(dev);
4248         int i = 0;
4249         u32 orig_read, new_read;
4250
4251         do {
4252                 orig_read = readl(base + nv_registers_test[i].reg);
4253
4254                 /* xor with mask to toggle bits */
4255                 orig_read ^= nv_registers_test[i].mask;
4256
4257                 writel(orig_read, base + nv_registers_test[i].reg);
4258
4259                 new_read = readl(base + nv_registers_test[i].reg);
4260
4261                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4262                         return 0;
4263
4264                 /* restore original value */
4265                 orig_read ^= nv_registers_test[i].mask;
4266                 writel(orig_read, base + nv_registers_test[i].reg);
4267
4268         } while (nv_registers_test[++i].reg != 0);
4269
4270         return 1;
4271 }
4272
4273 static int nv_interrupt_test(struct net_device *dev)
4274 {
4275         struct fe_priv *np = netdev_priv(dev);
4276         u8 __iomem *base = get_hwbase(dev);
4277         int ret = 1;
4278         int testcnt;
4279         u32 save_msi_flags, save_poll_interval = 0;
4280
4281         if (netif_running(dev)) {
4282                 /* free current irq */
4283                 nv_free_irq(dev);
4284                 save_poll_interval = readl(base+NvRegPollingInterval);
4285         }
4286
4287         /* flag to test interrupt handler */
4288         np->intr_test = 0;
4289
4290         /* setup test irq */
4291         save_msi_flags = np->msi_flags;
4292         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4293         np->msi_flags |= 0x001; /* setup 1 vector */
4294         if (nv_request_irq(dev, 1))
4295                 return 0;
4296
4297         /* setup timer interrupt */
4298         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4299         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4300
4301         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4302
4303         /* wait for at least one interrupt */
4304         msleep(100);
4305
4306         spin_lock_irq(&np->lock);
4307
4308         /* flag should be set within ISR */
4309         testcnt = np->intr_test;
4310         if (!testcnt)
4311                 ret = 2;
4312
4313         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4314         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4315                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4316         else
4317                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4318
4319         spin_unlock_irq(&np->lock);
4320
4321         nv_free_irq(dev);
4322
4323         np->msi_flags = save_msi_flags;
4324
4325         if (netif_running(dev)) {
4326                 writel(save_poll_interval, base + NvRegPollingInterval);
4327                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4328                 /* restore original irq */
4329                 if (nv_request_irq(dev, 0))
4330                         return 0;
4331         }
4332
4333         return ret;
4334 }
4335
4336 static int nv_loopback_test(struct net_device *dev)
4337 {
4338         struct fe_priv *np = netdev_priv(dev);
4339         u8 __iomem *base = get_hwbase(dev);
4340         struct sk_buff *tx_skb, *rx_skb;
4341         dma_addr_t test_dma_addr;
4342         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4343         u32 flags;
4344         int len, i, pkt_len;
4345         u8 *pkt_data;
4346         u32 filter_flags = 0;
4347         u32 misc1_flags = 0;
4348         int ret = 1;
4349
4350         if (netif_running(dev)) {
4351                 nv_disable_irq(dev);
4352                 filter_flags = readl(base + NvRegPacketFilterFlags);
4353                 misc1_flags = readl(base + NvRegMisc1);
4354         } else {
4355                 nv_txrx_reset(dev);
4356         }
4357
4358         /* reinit driver view of the rx queue */
4359         set_bufsize(dev);
4360         nv_init_ring(dev);
4361
4362         /* setup hardware for loopback */
4363         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4364         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4365
4366         /* reinit nic view of the rx queue */
4367         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4368         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4369         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4370                 base + NvRegRingSizes);
4371         pci_push(base);
4372
4373         /* restart rx engine */
4374         nv_start_rx(dev);
4375         nv_start_tx(dev);
4376
4377         /* setup packet for tx */
4378         pkt_len = ETH_DATA_LEN;
4379         tx_skb = dev_alloc_skb(pkt_len);
4380         if (!tx_skb) {
4381                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4382                          " of %s\n", dev->name);
4383                 ret = 0;
4384                 goto out;
4385         }
4386         pkt_data = skb_put(tx_skb, pkt_len);
4387         for (i = 0; i < pkt_len; i++)
4388                 pkt_data[i] = (u8)(i & 0xff);
4389         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4390                                        (skb_end_pointer(tx_skb) -
4391                                         tx_skb->data), PCI_DMA_FROMDEVICE);
4392
4393         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4394                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4395                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4396         } else {
4397                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4398                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4399                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4400         }
4401         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4402         pci_push(get_hwbase(dev));
4403
4404         msleep(500);
4405
4406         /* check for rx of the packet */
4407         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4408                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4409                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4410
4411         } else {
4412                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4413                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4414         }
4415
4416         if (flags & NV_RX_AVAIL) {
4417                 ret = 0;
4418         } else if (np->desc_ver == DESC_VER_1) {
4419                 if (flags & NV_RX_ERROR)
4420                         ret = 0;
4421         } else {
4422                 if (flags & NV_RX2_ERROR) {
4423                         ret = 0;
4424                 }
4425         }
4426
4427         if (ret) {
4428                 if (len != pkt_len) {
4429                         ret = 0;
4430                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4431                                 dev->name, len, pkt_len);
4432                 } else {
4433                         rx_skb = np->rx_skb[0].skb;
4434                         for (i = 0; i < pkt_len; i++) {
4435                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4436                                         ret = 0;
4437                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4438                                                 dev->name, i);
4439                                         break;
4440                                 }
4441                         }
4442                 }
4443         } else {
4444                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4445         }
4446
4447         pci_unmap_page(np->pci_dev, test_dma_addr,
4448                        (skb_end_pointer(tx_skb) - tx_skb->data),
4449                        PCI_DMA_TODEVICE);
4450         dev_kfree_skb_any(tx_skb);
4451  out:
4452         /* stop engines */
4453         nv_stop_rx(dev);
4454         nv_stop_tx(dev);
4455         nv_txrx_reset(dev);
4456         /* drain rx queue */
4457         nv_drain_rx(dev);
4458         nv_drain_tx(dev);
4459
4460         if (netif_running(dev)) {
4461                 writel(misc1_flags, base + NvRegMisc1);
4462                 writel(filter_flags, base + NvRegPacketFilterFlags);
4463                 nv_enable_irq(dev);
4464         }
4465
4466         return ret;
4467 }
4468
4469 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4470 {
4471         struct fe_priv *np = netdev_priv(dev);
4472         u8 __iomem *base = get_hwbase(dev);
4473         int result;
4474         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4475
4476         if (!nv_link_test(dev)) {
4477                 test->flags |= ETH_TEST_FL_FAILED;
4478                 buffer[0] = 1;
4479         }
4480
4481         if (test->flags & ETH_TEST_FL_OFFLINE) {
4482                 if (netif_running(dev)) {
4483                         netif_stop_queue(dev);
4484                         netif_poll_disable(dev);
4485                         netif_tx_lock_bh(dev);
4486                         spin_lock_irq(&np->lock);
4487                         nv_disable_hw_interrupts(dev, np->irqmask);
4488                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4489                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4490                         } else {
4491                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4492                         }
4493                         /* stop engines */
4494                         nv_stop_rx(dev);
4495                         nv_stop_tx(dev);
4496                         nv_txrx_reset(dev);
4497                         /* drain rx queue */
4498                         nv_drain_rx(dev);
4499                         nv_drain_tx(dev);
4500                         spin_unlock_irq(&np->lock);
4501                         netif_tx_unlock_bh(dev);
4502                 }
4503
4504                 if (!nv_register_test(dev)) {
4505                         test->flags |= ETH_TEST_FL_FAILED;
4506                         buffer[1] = 1;
4507                 }
4508
4509                 result = nv_interrupt_test(dev);
4510                 if (result != 1) {
4511                         test->flags |= ETH_TEST_FL_FAILED;
4512                         buffer[2] = 1;
4513                 }
4514                 if (result == 0) {
4515                         /* bail out */
4516                         return;
4517                 }
4518
4519                 if (!nv_loopback_test(dev)) {
4520                         test->flags |= ETH_TEST_FL_FAILED;
4521                         buffer[3] = 1;
4522                 }
4523
4524                 if (netif_running(dev)) {
4525                         /* reinit driver view of the rx queue */
4526                         set_bufsize(dev);
4527                         if (nv_init_ring(dev)) {
4528                                 if (!np->in_shutdown)
4529                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4530                         }
4531                         /* reinit nic view of the rx queue */
4532                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4533                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4534                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4535                                 base + NvRegRingSizes);
4536                         pci_push(base);
4537                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4538                         pci_push(base);
4539                         /* restart rx engine */
4540                         nv_start_rx(dev);
4541                         nv_start_tx(dev);
4542                         netif_start_queue(dev);
4543                         netif_poll_enable(dev);
4544                         nv_enable_hw_interrupts(dev, np->irqmask);
4545                 }
4546         }
4547 }
4548
4549 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4550 {
4551         switch (stringset) {
4552         case ETH_SS_STATS:
4553                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4554                 break;
4555         case ETH_SS_TEST:
4556                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4557                 break;
4558         }
4559 }
4560
4561 static const struct ethtool_ops ops = {
4562         .get_drvinfo = nv_get_drvinfo,
4563         .get_link = ethtool_op_get_link,
4564         .get_wol = nv_get_wol,
4565         .set_wol = nv_set_wol,
4566         .get_settings = nv_get_settings,
4567         .set_settings = nv_set_settings,
4568         .get_regs_len = nv_get_regs_len,
4569         .get_regs = nv_get_regs,
4570         .nway_reset = nv_nway_reset,
4571         .get_perm_addr = ethtool_op_get_perm_addr,
4572         .get_tso = ethtool_op_get_tso,
4573         .set_tso = nv_set_tso,
4574         .get_ringparam = nv_get_ringparam,
4575         .set_ringparam = nv_set_ringparam,
4576         .get_pauseparam = nv_get_pauseparam,
4577         .set_pauseparam = nv_set_pauseparam,
4578         .get_rx_csum = nv_get_rx_csum,
4579         .set_rx_csum = nv_set_rx_csum,
4580         .get_tx_csum = ethtool_op_get_tx_csum,
4581         .set_tx_csum = nv_set_tx_csum,
4582         .get_sg = ethtool_op_get_sg,
4583         .set_sg = nv_set_sg,
4584         .get_strings = nv_get_strings,
4585         .get_stats_count = nv_get_stats_count,
4586         .get_ethtool_stats = nv_get_ethtool_stats,
4587         .self_test_count = nv_self_test_count,
4588         .self_test = nv_self_test,
4589 };
4590
4591 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4592 {
4593         struct fe_priv *np = get_nvpriv(dev);
4594
4595         spin_lock_irq(&np->lock);
4596
4597         /* save vlan group */
4598         np->vlangrp = grp;
4599
4600         if (grp) {
4601                 /* enable vlan on MAC */
4602                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4603         } else {
4604                 /* disable vlan on MAC */
4605                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4606                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4607         }
4608
4609         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4610
4611         spin_unlock_irq(&np->lock);
4612 };
4613
4614 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4615 {
4616         /* nothing to do */
4617 };
4618
4619 /* The mgmt unit and driver use a semaphore to access the phy during init */
4620 static int nv_mgmt_acquire_sema(struct net_device *dev)
4621 {
4622         u8 __iomem *base = get_hwbase(dev);
4623         int i;
4624         u32 tx_ctrl, mgmt_sema;
4625
4626         for (i = 0; i < 10; i++) {
4627                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4628                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4629                         break;
4630                 msleep(500);
4631         }
4632
4633         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4634                 return 0;
4635
4636         for (i = 0; i < 2; i++) {
4637                 tx_ctrl = readl(base + NvRegTransmitterControl);
4638                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4639                 writel(tx_ctrl, base + NvRegTransmitterControl);
4640
4641                 /* verify that semaphore was acquired */
4642                 tx_ctrl = readl(base + NvRegTransmitterControl);
4643                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4644                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4645                         return 1;
4646                 else
4647                         udelay(50);
4648         }
4649
4650         return 0;
4651 }
4652
4653 static int nv_open(struct net_device *dev)
4654 {
4655         struct fe_priv *np = netdev_priv(dev);
4656         u8 __iomem *base = get_hwbase(dev);
4657         int ret = 1;
4658         int oom, i;
4659
4660         dprintk(KERN_DEBUG "nv_open: begin\n");
4661
4662         /* erase previous misconfiguration */
4663         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4664                 nv_mac_reset(dev);
4665         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4666         writel(0, base + NvRegMulticastAddrB);
4667         writel(0, base + NvRegMulticastMaskA);
4668         writel(0, base + NvRegMulticastMaskB);
4669         writel(0, base + NvRegPacketFilterFlags);
4670
4671         writel(0, base + NvRegTransmitterControl);
4672         writel(0, base + NvRegReceiverControl);
4673
4674         writel(0, base + NvRegAdapterControl);
4675
4676         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4677                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4678
4679         /* initialize descriptor rings */
4680         set_bufsize(dev);
4681         oom = nv_init_ring(dev);
4682
4683         writel(0, base + NvRegLinkSpeed);
4684         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4685         nv_txrx_reset(dev);
4686         writel(0, base + NvRegUnknownSetupReg6);
4687
4688         np->in_shutdown = 0;
4689
4690         /* give hw rings */
4691         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4692         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4693                 base + NvRegRingSizes);
4694
4695         writel(np->linkspeed, base + NvRegLinkSpeed);
4696         if (np->desc_ver == DESC_VER_1)
4697                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4698         else
4699                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4700         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4701         writel(np->vlanctl_bits, base + NvRegVlanControl);
4702         pci_push(base);
4703         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4704         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4705                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4706                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4707
4708         writel(0, base + NvRegMIIMask);
4709         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4710         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4711
4712         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4713         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4714         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4715         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4716
4717         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4718         get_random_bytes(&i, sizeof(i));
4719         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4720         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4721         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4722         if (poll_interval == -1) {
4723                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4724                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4725                 else
4726                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4727         }
4728         else
4729                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4730         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4731         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4732                         base + NvRegAdapterControl);
4733         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4734         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4735         if (np->wolenabled)
4736                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4737
4738         i = readl(base + NvRegPowerState);
4739         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4740                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4741
4742         pci_push(base);
4743         udelay(10);
4744         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4745
4746         nv_disable_hw_interrupts(dev, np->irqmask);
4747         pci_push(base);
4748         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4749         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4750         pci_push(base);
4751
4752         if (nv_request_irq(dev, 0)) {
4753                 goto out_drain;
4754         }
4755
4756         /* ask for interrupts */
4757         nv_enable_hw_interrupts(dev, np->irqmask);
4758
4759         spin_lock_irq(&np->lock);
4760         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4761         writel(0, base + NvRegMulticastAddrB);
4762         writel(0, base + NvRegMulticastMaskA);
4763         writel(0, base + NvRegMulticastMaskB);
4764         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4765         /* One manual link speed update: Interrupts are enabled, future link
4766          * speed changes cause interrupts and are handled by nv_link_irq().
4767          */
4768         {
4769                 u32 miistat;
4770                 miistat = readl(base + NvRegMIIStatus);
4771                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4772                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4773         }
4774         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4775          * to init hw */
4776         np->linkspeed = 0;
4777         ret = nv_update_linkspeed(dev);
4778         nv_start_rx(dev);
4779         nv_start_tx(dev);
4780         netif_start_queue(dev);
4781         netif_poll_enable(dev);
4782
4783         if (ret) {
4784                 netif_carrier_on(dev);
4785         } else {
4786                 printk("%s: no link during initialization.\n", dev->name);
4787                 netif_carrier_off(dev);
4788         }
4789         if (oom)
4790                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4791
4792         /* start statistics timer */
4793         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
4794                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4795
4796         spin_unlock_irq(&np->lock);
4797
4798         return 0;
4799 out_drain:
4800         drain_ring(dev);
4801         return ret;
4802 }
4803
4804 static int nv_close(struct net_device *dev)
4805 {
4806         struct fe_priv *np = netdev_priv(dev);
4807         u8 __iomem *base;
4808
4809         spin_lock_irq(&np->lock);
4810         np->in_shutdown = 1;
4811         spin_unlock_irq(&np->lock);
4812         netif_poll_disable(dev);
4813         synchronize_irq(dev->irq);
4814
4815         del_timer_sync(&np->oom_kick);
4816         del_timer_sync(&np->nic_poll);
4817         del_timer_sync(&np->stats_poll);
4818
4819         netif_stop_queue(dev);
4820         spin_lock_irq(&np->lock);
4821         nv_stop_tx(dev);
4822         nv_stop_rx(dev);
4823         nv_txrx_reset(dev);
4824
4825         /* disable interrupts on the nic or we will lock up */
4826         base = get_hwbase(dev);
4827         nv_disable_hw_interrupts(dev, np->irqmask);
4828         pci_push(base);
4829         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4830
4831         spin_unlock_irq(&np->lock);
4832
4833         nv_free_irq(dev);
4834
4835         drain_ring(dev);
4836
4837         if (np->wolenabled)
4838                 nv_start_rx(dev);
4839
4840         /* FIXME: power down nic */
4841
4842         return 0;
4843 }
4844
4845 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4846 {
4847         struct net_device *dev;
4848         struct fe_priv *np;
4849         unsigned long addr;
4850         u8 __iomem *base;
4851         int err, i;
4852         u32 powerstate, txreg;
4853         u32 phystate_orig = 0, phystate;
4854         int phyinitialized = 0;
4855
4856         dev = alloc_etherdev(sizeof(struct fe_priv));
4857         err = -ENOMEM;
4858         if (!dev)
4859                 goto out;
4860
4861         np = netdev_priv(dev);
4862         np->pci_dev = pci_dev;
4863         spin_lock_init(&np->lock);
4864         SET_MODULE_OWNER(dev);
4865         SET_NETDEV_DEV(dev, &pci_dev->dev);
4866
4867         init_timer(&np->oom_kick);
4868         np->oom_kick.data = (unsigned long) dev;
4869         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4870         init_timer(&np->nic_poll);
4871         np->nic_poll.data = (unsigned long) dev;
4872         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4873         init_timer(&np->stats_poll);
4874         np->stats_poll.data = (unsigned long) dev;
4875         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4876
4877         err = pci_enable_device(pci_dev);
4878         if (err) {
4879                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4880                                 err, pci_name(pci_dev));
4881                 goto out_free;
4882         }
4883
4884         pci_set_master(pci_dev);
4885
4886         err = pci_request_regions(pci_dev, DRV_NAME);
4887         if (err < 0)
4888                 goto out_disable;
4889
4890         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
4891                 np->register_size = NV_PCI_REGSZ_VER3;
4892         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
4893                 np->register_size = NV_PCI_REGSZ_VER2;
4894         else
4895                 np->register_size = NV_PCI_REGSZ_VER1;
4896
4897         err = -EINVAL;
4898         addr = 0;
4899         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4900                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4901                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4902                                 pci_resource_len(pci_dev, i),
4903                                 pci_resource_flags(pci_dev, i));
4904                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4905                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4906                         addr = pci_resource_start(pci_dev, i);
4907                         break;
4908                 }
4909         }
4910         if (i == DEVICE_COUNT_RESOURCE) {
4911                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4912                                         pci_name(pci_dev));
4913                 goto out_relreg;
4914         }
4915
4916         /* copy of driver data */
4917         np->driver_data = id->driver_data;
4918
4919         /* handle different descriptor versions */
4920         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4921                 /* packet format 3: supports 40-bit addressing */
4922                 np->desc_ver = DESC_VER_3;
4923                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4924                 if (dma_64bit) {
4925                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4926                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4927                                        pci_name(pci_dev));
4928                         } else {
4929                                 dev->features |= NETIF_F_HIGHDMA;
4930                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4931                         }
4932                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4933                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4934                                        pci_name(pci_dev));
4935                         }
4936                 }
4937         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4938                 /* packet format 2: supports jumbo frames */
4939                 np->desc_ver = DESC_VER_2;
4940                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4941         } else {
4942                 /* original packet format */
4943                 np->desc_ver = DESC_VER_1;
4944                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4945         }
4946
4947         np->pkt_limit = NV_PKTLIMIT_1;
4948         if (id->driver_data & DEV_HAS_LARGEDESC)
4949                 np->pkt_limit = NV_PKTLIMIT_2;
4950
4951         if (id->driver_data & DEV_HAS_CHECKSUM) {
4952                 np->rx_csum = 1;
4953                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4954                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4955                 dev->features |= NETIF_F_TSO;
4956         }
4957
4958         np->vlanctl_bits = 0;
4959         if (id->driver_data & DEV_HAS_VLAN) {
4960                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4961                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4962                 dev->vlan_rx_register = nv_vlan_rx_register;
4963                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4964         }
4965
4966         np->msi_flags = 0;
4967         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4968                 np->msi_flags |= NV_MSI_CAPABLE;
4969         }
4970         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4971                 np->msi_flags |= NV_MSI_X_CAPABLE;
4972         }
4973
4974         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4975         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4976                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4977         }
4978
4979
4980         err = -ENOMEM;
4981         np->base = ioremap(addr, np->register_size);
4982         if (!np->base)
4983                 goto out_relreg;
4984         dev->base_addr = (unsigned long)np->base;
4985
4986         dev->irq = pci_dev->irq;
4987
4988         np->rx_ring_size = RX_RING_DEFAULT;
4989         np->tx_ring_size = TX_RING_DEFAULT;
4990
4991         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4992                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4993                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4994                                         &np->ring_addr);
4995                 if (!np->rx_ring.orig)
4996                         goto out_unmap;
4997                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4998         } else {
4999                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5000                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5001                                         &np->ring_addr);
5002                 if (!np->rx_ring.ex)
5003                         goto out_unmap;
5004                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5005         }
5006         np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
5007         np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
5008         if (!np->rx_skb || !np->tx_skb)
5009                 goto out_freering;
5010         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
5011         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
5012
5013         dev->open = nv_open;
5014         dev->stop = nv_close;
5015         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5016                 dev->hard_start_xmit = nv_start_xmit;
5017         else
5018                 dev->hard_start_xmit = nv_start_xmit_optimized;
5019         dev->get_stats = nv_get_stats;
5020         dev->change_mtu = nv_change_mtu;
5021         dev->set_mac_address = nv_set_mac_address;
5022         dev->set_multicast_list = nv_set_multicast;
5023 #ifdef CONFIG_NET_POLL_CONTROLLER
5024         dev->poll_controller = nv_poll_controller;
5025 #endif
5026         dev->weight = RX_WORK_PER_LOOP;
5027 #ifdef CONFIG_FORCEDETH_NAPI
5028         dev->poll = nv_napi_poll;
5029 #endif
5030         SET_ETHTOOL_OPS(dev, &ops);
5031         dev->tx_timeout = nv_tx_timeout;
5032         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5033
5034         pci_set_drvdata(pci_dev, dev);
5035
5036         /* read the mac address */
5037         base = get_hwbase(dev);
5038         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5039         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5040
5041         /* check the workaround bit for correct mac address order */
5042         txreg = readl(base + NvRegTransmitPoll);
5043         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5044                 /* mac address is already in correct order */
5045                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5046                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5047                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5048                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5049                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5050                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5051         } else {
5052                 /* need to reverse mac address to correct order */
5053                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5054                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5055                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5056                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5057                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5058                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5059                 /* set permanent address to be correct aswell */
5060                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
5061                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
5062                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
5063                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5064         }
5065         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5066
5067         if (!is_valid_ether_addr(dev->perm_addr)) {
5068                 /*
5069                  * Bad mac address. At least one bios sets the mac address
5070                  * to 01:23:45:67:89:ab
5071                  */
5072                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
5073                         pci_name(pci_dev),
5074                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5075                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5076                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
5077                 dev->dev_addr[0] = 0x00;
5078                 dev->dev_addr[1] = 0x00;
5079                 dev->dev_addr[2] = 0x6c;
5080                 get_random_bytes(&dev->dev_addr[3], 3);
5081         }
5082
5083         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
5084                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5085                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5086
5087         /* set mac address */
5088         nv_copy_mac_to_hw(dev);
5089
5090         /* disable WOL */
5091         writel(0, base + NvRegWakeUpFlags);
5092         np->wolenabled = 0;
5093
5094         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5095                 u8 revision_id;
5096                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
5097
5098                 /* take phy and nic out of low power mode */
5099                 powerstate = readl(base + NvRegPowerState2);
5100                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5101                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5102                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5103                     revision_id >= 0xA3)
5104                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5105                 writel(powerstate, base + NvRegPowerState2);
5106         }
5107
5108         if (np->desc_ver == DESC_VER_1) {
5109                 np->tx_flags = NV_TX_VALID;
5110         } else {
5111                 np->tx_flags = NV_TX2_VALID;
5112         }
5113         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5114                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5115                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5116                         np->msi_flags |= 0x0003;
5117         } else {
5118                 np->irqmask = NVREG_IRQMASK_CPU;
5119                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5120                         np->msi_flags |= 0x0001;
5121         }
5122
5123         if (id->driver_data & DEV_NEED_TIMERIRQ)
5124                 np->irqmask |= NVREG_IRQ_TIMER;
5125         if (id->driver_data & DEV_NEED_LINKTIMER) {
5126                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5127                 np->need_linktimer = 1;
5128                 np->link_timeout = jiffies + LINK_TIMEOUT;
5129         } else {
5130                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5131                 np->need_linktimer = 0;
5132         }
5133
5134         /* clear phy state and temporarily halt phy interrupts */
5135         writel(0, base + NvRegMIIMask);
5136         phystate = readl(base + NvRegAdapterControl);
5137         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5138                 phystate_orig = 1;
5139                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5140                 writel(phystate, base + NvRegAdapterControl);
5141         }
5142         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
5143
5144         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5145                 /* management unit running on the mac? */
5146                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5147                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5148                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5149                         for (i = 0; i < 5000; i++) {
5150                                 msleep(1);
5151                                 if (nv_mgmt_acquire_sema(dev)) {
5152                                         /* management unit setup the phy already? */
5153                                         if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5154                                             NVREG_XMITCTL_SYNC_PHY_INIT) {
5155                                                 /* phy is inited by mgmt unit */
5156                                                 phyinitialized = 1;
5157                                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5158                                         } else {
5159                                                 /* we need to init the phy */
5160                                         }
5161                                         break;
5162                                 }
5163                         }
5164                 }
5165         }
5166
5167         /* find a suitable phy */
5168         for (i = 1; i <= 32; i++) {
5169                 int id1, id2;
5170                 int phyaddr = i & 0x1F;
5171
5172                 spin_lock_irq(&np->lock);
5173                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5174                 spin_unlock_irq(&np->lock);
5175                 if (id1 < 0 || id1 == 0xffff)
5176                         continue;
5177                 spin_lock_irq(&np->lock);
5178                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5179                 spin_unlock_irq(&np->lock);
5180                 if (id2 < 0 || id2 == 0xffff)
5181                         continue;
5182
5183                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5184                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5185                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5186                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5187                         pci_name(pci_dev), id1, id2, phyaddr);
5188                 np->phyaddr = phyaddr;
5189                 np->phy_oui = id1 | id2;
5190                 break;
5191         }
5192         if (i == 33) {
5193                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
5194                        pci_name(pci_dev));
5195                 goto out_error;
5196         }
5197
5198         if (!phyinitialized) {
5199                 /* reset it */
5200                 phy_init(dev);
5201         } else {
5202                 /* see if it is a gigabit phy */
5203                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5204                 if (mii_status & PHY_GIGABIT) {
5205                         np->gigabit = PHY_GIGABIT;
5206                 }
5207         }
5208
5209         /* set default link speed settings */
5210         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5211         np->duplex = 0;
5212         np->autoneg = 1;
5213
5214         err = register_netdev(dev);
5215         if (err) {
5216                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
5217                 goto out_error;
5218         }
5219         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
5220                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
5221                         pci_name(pci_dev));
5222
5223         return 0;
5224
5225 out_error:
5226         if (phystate_orig)
5227                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5228         pci_set_drvdata(pci_dev, NULL);
5229 out_freering:
5230         free_rings(dev);
5231 out_unmap:
5232         iounmap(get_hwbase(dev));
5233 out_relreg:
5234         pci_release_regions(pci_dev);
5235 out_disable:
5236         pci_disable_device(pci_dev);
5237 out_free:
5238         free_netdev(dev);
5239 out:
5240         return err;
5241 }
5242
5243 static void __devexit nv_remove(struct pci_dev *pci_dev)
5244 {
5245         struct net_device *dev = pci_get_drvdata(pci_dev);
5246         struct fe_priv *np = netdev_priv(dev);
5247         u8 __iomem *base = get_hwbase(dev);
5248
5249         unregister_netdev(dev);
5250
5251         /* special op: write back the misordered MAC address - otherwise
5252          * the next nv_probe would see a wrong address.
5253          */
5254         writel(np->orig_mac[0], base + NvRegMacAddrA);
5255         writel(np->orig_mac[1], base + NvRegMacAddrB);
5256
5257         /* free all structures */
5258         free_rings(dev);
5259         iounmap(get_hwbase(dev));
5260         pci_release_regions(pci_dev);
5261         pci_disable_device(pci_dev);
5262         free_netdev(dev);
5263         pci_set_drvdata(pci_dev, NULL);
5264 }
5265
5266 #ifdef CONFIG_PM
5267 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5268 {
5269         struct net_device *dev = pci_get_drvdata(pdev);
5270         struct fe_priv *np = netdev_priv(dev);
5271
5272         if (!netif_running(dev))
5273                 goto out;
5274
5275         netif_device_detach(dev);
5276
5277         // Gross.
5278         nv_close(dev);
5279
5280         pci_save_state(pdev);
5281         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5282         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5283 out:
5284         return 0;
5285 }
5286
5287 static int nv_resume(struct pci_dev *pdev)
5288 {
5289         struct net_device *dev = pci_get_drvdata(pdev);
5290         int rc = 0;
5291
5292         if (!netif_running(dev))
5293                 goto out;
5294
5295         netif_device_attach(dev);
5296
5297         pci_set_power_state(pdev, PCI_D0);
5298         pci_restore_state(pdev);
5299         pci_enable_wake(pdev, PCI_D0, 0);
5300
5301         rc = nv_open(dev);
5302 out:
5303         return rc;
5304 }
5305 #else
5306 #define nv_suspend NULL
5307 #define nv_resume NULL
5308 #endif /* CONFIG_PM */
5309
5310 static struct pci_device_id pci_tbl[] = {
5311         {       /* nForce Ethernet Controller */
5312                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5313                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5314         },
5315         {       /* nForce2 Ethernet Controller */
5316                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5317                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5318         },
5319         {       /* nForce3 Ethernet Controller */
5320                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5321                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5322         },
5323         {       /* nForce3 Ethernet Controller */
5324                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5325                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5326         },
5327         {       /* nForce3 Ethernet Controller */
5328                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5329                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5330         },
5331         {       /* nForce3 Ethernet Controller */
5332                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5333                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5334         },
5335         {       /* nForce3 Ethernet Controller */
5336                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5337                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5338         },
5339         {       /* CK804 Ethernet Controller */
5340                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5341                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5342         },
5343         {       /* CK804 Ethernet Controller */
5344                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5345                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5346         },
5347         {       /* MCP04 Ethernet Controller */
5348                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5349                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5350         },
5351         {       /* MCP04 Ethernet Controller */
5352                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5353                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5354         },
5355         {       /* MCP51 Ethernet Controller */
5356                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5357                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5358         },
5359         {       /* MCP51 Ethernet Controller */
5360                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5361                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5362         },
5363         {       /* MCP55 Ethernet Controller */
5364                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5365                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5366         },
5367         {       /* MCP55 Ethernet Controller */
5368                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5369                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5370         },
5371         {       /* MCP61 Ethernet Controller */
5372                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5373                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5374         },
5375         {       /* MCP61 Ethernet Controller */
5376                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5377                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5378         },
5379         {       /* MCP61 Ethernet Controller */
5380                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5381                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5382         },
5383         {       /* MCP61 Ethernet Controller */
5384                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5385                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5386         },
5387         {       /* MCP65 Ethernet Controller */
5388                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5389                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5390         },
5391         {       /* MCP65 Ethernet Controller */
5392                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5393                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5394         },
5395         {       /* MCP65 Ethernet Controller */
5396                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5397                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5398         },
5399         {       /* MCP65 Ethernet Controller */
5400                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5401                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5402         },
5403         {       /* MCP67 Ethernet Controller */
5404                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5405                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5406         },
5407         {       /* MCP67 Ethernet Controller */
5408                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5409                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5410         },
5411         {       /* MCP67 Ethernet Controller */
5412                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5413                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5414         },
5415         {       /* MCP67 Ethernet Controller */
5416                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5417                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5418         },
5419         {0,},
5420 };
5421
5422 static struct pci_driver driver = {
5423         .name = "forcedeth",
5424         .id_table = pci_tbl,
5425         .probe = nv_probe,
5426         .remove = __devexit_p(nv_remove),
5427         .suspend = nv_suspend,
5428         .resume = nv_resume,
5429 };
5430
5431 static int __init init_nic(void)
5432 {
5433         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5434         return pci_register_driver(&driver);
5435 }
5436
5437 static void __exit exit_nic(void)
5438 {
5439         pci_unregister_driver(&driver);
5440 }
5441
5442 module_param(max_interrupt_work, int, 0);
5443 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5444 module_param(optimization_mode, int, 0);
5445 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5446 module_param(poll_interval, int, 0);
5447 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5448 module_param(msi, int, 0);
5449 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5450 module_param(msix, int, 0);
5451 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5452 module_param(dma_64bit, int, 0);
5453 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5454
5455 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5456 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5457 MODULE_LICENSE("GPL");
5458
5459 MODULE_DEVICE_TABLE(pci, pci_tbl);
5460
5461 module_init(init_nic);
5462 module_exit(exit_nic);