SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *      0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
 115  *
 116  * Known bugs:
 117  * We suspect that on some hardware no TX done interrupts are generated.
 118  * This means recovery from netif_stop_queue only happens if the hw timer
 119  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 120  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 121  * If your hardware reliably generates tx done interrupts, then you can remove
 122  * DEV_NEED_TIMERIRQ from the driver_data flags.
 123  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 124  * superfluous timer interrupts from the nic.
 125  */
 126 #ifdef CONFIG_FORCEDETH_NAPI
 127 #define DRIVERNAPI "-NAPI"
 128 #else
 129 #define DRIVERNAPI
 130 #endif
 131 #define FORCEDETH_VERSION               "0.61"
 132 #define DRV_NAME                        "forcedeth"
 133
 134 #include <linux/module.h>
 135 #include <linux/types.h>
 136 #include <linux/pci.h>
 137 #include <linux/interrupt.h>
 138 #include <linux/netdevice.h>
 139 #include <linux/etherdevice.h>
 140 #include <linux/delay.h>
 141 #include <linux/spinlock.h>
 142 #include <linux/ethtool.h>
 143 #include <linux/timer.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/mii.h>
 146 #include <linux/random.h>
 147 #include <linux/init.h>
 148 #include <linux/if_vlan.h>
 149 #include <linux/dma-mapping.h>
 150
 151 #include <asm/irq.h>
 152 #include <asm/io.h>
 153 #include <asm/uaccess.h>
 154 #include <asm/system.h>
 155
 156 #if 0
 157 #define dprintk                 printk
 158 #else
 159 #define dprintk(x...)           do { } while (0)
 160 #endif
 161
 162 #define TX_WORK_PER_LOOP  64
 163 #define RX_WORK_PER_LOOP  64
 164
 165 /*
 166  * Hardware access:
 167  */
 168
 169 #define DEV_NEED_TIMERIRQ          0x00001  /* set the timer irq flag in the irq mask */
 170 #define DEV_NEED_LINKTIMER         0x00002  /* poll link settings. Relies on the timer irq */
 171 #define DEV_HAS_LARGEDESC          0x00004  /* device supports jumbo frames and needs packet format 2 */
 172 #define DEV_HAS_HIGH_DMA           0x00008  /* device supports 64bit dma */
 173 #define DEV_HAS_CHECKSUM           0x00010  /* device supports tx and rx checksum offloads */
 174 #define DEV_HAS_VLAN               0x00020  /* device supports vlan tagging and striping */
 175 #define DEV_HAS_MSI                0x00040  /* device supports MSI */
 176 #define DEV_HAS_MSI_X              0x00080  /* device supports MSI-X */
 177 #define DEV_HAS_POWER_CNTRL        0x00100  /* device supports power savings */
 178 #define DEV_HAS_STATISTICS_V1      0x00200  /* device supports hw statistics version 1 */
 179 #define DEV_HAS_STATISTICS_V2      0x00400  /* device supports hw statistics version 2 */
 180 #define DEV_HAS_TEST_EXTENDED      0x00800  /* device supports extended diagnostic test */
 181 #define DEV_HAS_MGMT_UNIT          0x01000  /* device supports management unit */
 182 #define DEV_HAS_CORRECT_MACADDR    0x02000  /* device supports correct mac address order */
 183 #define DEV_HAS_COLLISION_FIX      0x04000  /* device supports tx collision fix */
 184 #define DEV_HAS_PAUSEFRAME_TX_V1   0x08000  /* device supports tx pause frames version 1 */
 185 #define DEV_HAS_PAUSEFRAME_TX_V2   0x10000  /* device supports tx pause frames version 2 */
 186 #define DEV_HAS_PAUSEFRAME_TX_V3   0x20000  /* device supports tx pause frames version 3 */
 187 #define DEV_NEED_TX_LIMIT          0x40000  /* device needs to limit tx */
 188
 189 enum {
 190         NvRegIrqStatus = 0x000,
 191 #define NVREG_IRQSTAT_MIIEVENT  0x040
 192 #define NVREG_IRQSTAT_MASK              0x81ff
 193         NvRegIrqMask = 0x004,
 194 #define NVREG_IRQ_RX_ERROR              0x0001
 195 #define NVREG_IRQ_RX                    0x0002
 196 #define NVREG_IRQ_RX_NOBUF              0x0004
 197 #define NVREG_IRQ_TX_ERR                0x0008
 198 #define NVREG_IRQ_TX_OK                 0x0010
 199 #define NVREG_IRQ_TIMER                 0x0020
 200 #define NVREG_IRQ_LINK                  0x0040
 201 #define NVREG_IRQ_RX_FORCED             0x0080
 202 #define NVREG_IRQ_TX_FORCED             0x0100
 203 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 204 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 205 #define NVREG_IRQMASK_CPU               0x0060
 206 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 207 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 208 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 209
 210 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 211                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 212                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 213
 214         NvRegUnknownSetupReg6 = 0x008,
 215 #define NVREG_UNKSETUP6_VAL             3
 216
 217 /*
 218  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 219  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 220  */
 221         NvRegPollingInterval = 0x00c,
 222 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 223 #define NVREG_POLL_DEFAULT_CPU  13
 224         NvRegMSIMap0 = 0x020,
 225         NvRegMSIMap1 = 0x024,
 226         NvRegMSIIrqMask = 0x030,
 227 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 228         NvRegMisc1 = 0x080,
 229 #define NVREG_MISC1_PAUSE_TX    0x01
 230 #define NVREG_MISC1_HD          0x02
 231 #define NVREG_MISC1_FORCE       0x3b0f3c
 232
 233         NvRegMacReset = 0x34,
 234 #define NVREG_MAC_RESET_ASSERT  0x0F3
 235         NvRegTransmitterControl = 0x084,
 236 #define NVREG_XMITCTL_START     0x01
 237 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 238 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 239 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 240 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 241 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 242 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 243 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 244 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 245 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 246 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 247         NvRegTransmitterStatus = 0x088,
 248 #define NVREG_XMITSTAT_BUSY     0x01
 249
 250         NvRegPacketFilterFlags = 0x8c,
 251 #define NVREG_PFF_PAUSE_RX      0x08
 252 #define NVREG_PFF_ALWAYS        0x7F0000
 253 #define NVREG_PFF_PROMISC       0x80
 254 #define NVREG_PFF_MYADDR        0x20
 255 #define NVREG_PFF_LOOPBACK      0x10
 256
 257         NvRegOffloadConfig = 0x90,
 258 #define NVREG_OFFLOAD_HOMEPHY   0x601
 259 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 260         NvRegReceiverControl = 0x094,
 261 #define NVREG_RCVCTL_START      0x01
 262 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 263         NvRegReceiverStatus = 0x98,
 264 #define NVREG_RCVSTAT_BUSY      0x01
 265
 266         NvRegRandomSeed = 0x9c,
 267 #define NVREG_RNDSEED_MASK      0x00ff
 268 #define NVREG_RNDSEED_FORCE     0x7f00
 269 #define NVREG_RNDSEED_FORCE2    0x2d00
 270 #define NVREG_RNDSEED_FORCE3    0x7400
 271
 272         NvRegTxDeferral = 0xA0,
 273 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 274 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 275 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 276 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 277 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 278 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 279         NvRegRxDeferral = 0xA4,
 280 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 281         NvRegMacAddrA = 0xA8,
 282         NvRegMacAddrB = 0xAC,
 283         NvRegMulticastAddrA = 0xB0,
 284 #define NVREG_MCASTADDRA_FORCE  0x01
 285         NvRegMulticastAddrB = 0xB4,
 286         NvRegMulticastMaskA = 0xB8,
 287 #define NVREG_MCASTMASKA_NONE           0xffffffff
 288         NvRegMulticastMaskB = 0xBC,
 289 #define NVREG_MCASTMASKB_NONE           0xffff
 290
 291         NvRegPhyInterface = 0xC0,
 292 #define PHY_RGMII               0x10000000
 293
 294         NvRegTxRingPhysAddr = 0x100,
 295         NvRegRxRingPhysAddr = 0x104,
 296         NvRegRingSizes = 0x108,
 297 #define NVREG_RINGSZ_TXSHIFT 0
 298 #define NVREG_RINGSZ_RXSHIFT 16
 299         NvRegTransmitPoll = 0x10c,
 300 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 301         NvRegLinkSpeed = 0x110,
 302 #define NVREG_LINKSPEED_FORCE 0x10000
 303 #define NVREG_LINKSPEED_10      1000
 304 #define NVREG_LINKSPEED_100     100
 305 #define NVREG_LINKSPEED_1000    50
 306 #define NVREG_LINKSPEED_MASK    (0xFFF)
 307         NvRegUnknownSetupReg5 = 0x130,
 308 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 309         NvRegTxWatermark = 0x13c,
 310 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 311 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 312 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 313         NvRegTxRxControl = 0x144,
 314 #define NVREG_TXRXCTL_KICK      0x0001
 315 #define NVREG_TXRXCTL_BIT1      0x0002
 316 #define NVREG_TXRXCTL_BIT2      0x0004
 317 #define NVREG_TXRXCTL_IDLE      0x0008
 318 #define NVREG_TXRXCTL_RESET     0x0010
 319 #define NVREG_TXRXCTL_RXCHECK   0x0400
 320 #define NVREG_TXRXCTL_DESC_1    0
 321 #define NVREG_TXRXCTL_DESC_2    0x002100
 322 #define NVREG_TXRXCTL_DESC_3    0xc02200
 323 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 324 #define NVREG_TXRXCTL_VLANINS   0x00080
 325         NvRegTxRingPhysAddrHigh = 0x148,
 326         NvRegRxRingPhysAddrHigh = 0x14C,
 327         NvRegTxPauseFrame = 0x170,
 328 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 329 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 330 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 331 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 332         NvRegMIIStatus = 0x180,
 333 #define NVREG_MIISTAT_ERROR             0x0001
 334 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 335 #define NVREG_MIISTAT_MASK_RW           0x0007
 336 #define NVREG_MIISTAT_MASK_ALL          0x000f
 337         NvRegMIIMask = 0x184,
 338 #define NVREG_MII_LINKCHANGE            0x0008
 339
 340         NvRegAdapterControl = 0x188,
 341 #define NVREG_ADAPTCTL_START    0x02
 342 #define NVREG_ADAPTCTL_LINKUP   0x04
 343 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 344 #define NVREG_ADAPTCTL_RUNNING  0x100000
 345 #define NVREG_ADAPTCTL_PHYSHIFT 24
 346         NvRegMIISpeed = 0x18c,
 347 #define NVREG_MIISPEED_BIT8     (1<<8)
 348 #define NVREG_MIIDELAY  5
 349         NvRegMIIControl = 0x190,
 350 #define NVREG_MIICTL_INUSE      0x08000
 351 #define NVREG_MIICTL_WRITE      0x00400
 352 #define NVREG_MIICTL_ADDRSHIFT  5
 353         NvRegMIIData = 0x194,
 354         NvRegWakeUpFlags = 0x200,
 355 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 356 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 357 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 358 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 359 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 360 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 361 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 362 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 363 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 364 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 365 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 366
 367         NvRegPatternCRC = 0x204,
 368         NvRegPatternMask = 0x208,
 369         NvRegPowerCap = 0x268,
 370 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 371 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 372 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 373         NvRegPowerState = 0x26c,
 374 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 375 #define NVREG_POWERSTATE_VALID          0x0100
 376 #define NVREG_POWERSTATE_MASK           0x0003
 377 #define NVREG_POWERSTATE_D0             0x0000
 378 #define NVREG_POWERSTATE_D1             0x0001
 379 #define NVREG_POWERSTATE_D2             0x0002
 380 #define NVREG_POWERSTATE_D3             0x0003
 381         NvRegTxCnt = 0x280,
 382         NvRegTxZeroReXmt = 0x284,
 383         NvRegTxOneReXmt = 0x288,
 384         NvRegTxManyReXmt = 0x28c,
 385         NvRegTxLateCol = 0x290,
 386         NvRegTxUnderflow = 0x294,
 387         NvRegTxLossCarrier = 0x298,
 388         NvRegTxExcessDef = 0x29c,
 389         NvRegTxRetryErr = 0x2a0,
 390         NvRegRxFrameErr = 0x2a4,
 391         NvRegRxExtraByte = 0x2a8,
 392         NvRegRxLateCol = 0x2ac,
 393         NvRegRxRunt = 0x2b0,
 394         NvRegRxFrameTooLong = 0x2b4,
 395         NvRegRxOverflow = 0x2b8,
 396         NvRegRxFCSErr = 0x2bc,
 397         NvRegRxFrameAlignErr = 0x2c0,
 398         NvRegRxLenErr = 0x2c4,
 399         NvRegRxUnicast = 0x2c8,
 400         NvRegRxMulticast = 0x2cc,
 401         NvRegRxBroadcast = 0x2d0,
 402         NvRegTxDef = 0x2d4,
 403         NvRegTxFrame = 0x2d8,
 404         NvRegRxCnt = 0x2dc,
 405         NvRegTxPause = 0x2e0,
 406         NvRegRxPause = 0x2e4,
 407         NvRegRxDropFrame = 0x2e8,
 408         NvRegVlanControl = 0x300,
 409 #define NVREG_VLANCONTROL_ENABLE        0x2000
 410         NvRegMSIXMap0 = 0x3e0,
 411         NvRegMSIXMap1 = 0x3e4,
 412         NvRegMSIXIrqStatus = 0x3f0,
 413
 414         NvRegPowerState2 = 0x600,
 415 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 416 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 417 };
 418
 419 /* Big endian: should work, but is untested */
 420 struct ring_desc {
 421         __le32 buf;
 422         __le32 flaglen;
 423 };
 424
 425 struct ring_desc_ex {
 426         __le32 bufhigh;
 427         __le32 buflow;
 428         __le32 txvlan;
 429         __le32 flaglen;
 430 };
 431
 432 union ring_type {
 433         struct ring_desc* orig;
 434         struct ring_desc_ex* ex;
 435 };
 436
 437 #define FLAG_MASK_V1 0xffff0000
 438 #define FLAG_MASK_V2 0xffffc000
 439 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 440 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 441
 442 #define NV_TX_LASTPACKET        (1<<16)
 443 #define NV_TX_RETRYERROR        (1<<19)
 444 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 445 #define NV_TX_DEFERRED          (1<<26)
 446 #define NV_TX_CARRIERLOST       (1<<27)
 447 #define NV_TX_LATECOLLISION     (1<<28)
 448 #define NV_TX_UNDERFLOW         (1<<29)
 449 #define NV_TX_ERROR             (1<<30)
 450 #define NV_TX_VALID             (1<<31)
 451
 452 #define NV_TX2_LASTPACKET       (1<<29)
 453 #define NV_TX2_RETRYERROR       (1<<18)
 454 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 455 #define NV_TX2_DEFERRED         (1<<25)
 456 #define NV_TX2_CARRIERLOST      (1<<26)
 457 #define NV_TX2_LATECOLLISION    (1<<27)
 458 #define NV_TX2_UNDERFLOW        (1<<28)
 459 /* error and valid are the same for both */
 460 #define NV_TX2_ERROR            (1<<30)
 461 #define NV_TX2_VALID            (1<<31)
 462 #define NV_TX2_TSO              (1<<28)
 463 #define NV_TX2_TSO_SHIFT        14
 464 #define NV_TX2_TSO_MAX_SHIFT    14
 465 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 466 #define NV_TX2_CHECKSUM_L3      (1<<27)
 467 #define NV_TX2_CHECKSUM_L4      (1<<26)
 468
 469 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 470
 471 #define NV_RX_DESCRIPTORVALID   (1<<16)
 472 #define NV_RX_MISSEDFRAME       (1<<17)
 473 #define NV_RX_SUBSTRACT1        (1<<18)
 474 #define NV_RX_ERROR1            (1<<23)
 475 #define NV_RX_ERROR2            (1<<24)
 476 #define NV_RX_ERROR3            (1<<25)
 477 #define NV_RX_ERROR4            (1<<26)
 478 #define NV_RX_CRCERR            (1<<27)
 479 #define NV_RX_OVERFLOW          (1<<28)
 480 #define NV_RX_FRAMINGERR        (1<<29)
 481 #define NV_RX_ERROR             (1<<30)
 482 #define NV_RX_AVAIL             (1<<31)
 483
 484 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 485 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 486 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 487 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 488 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 489 #define NV_RX2_SUBSTRACT1       (1<<25)
 490 #define NV_RX2_ERROR1           (1<<18)
 491 #define NV_RX2_ERROR2           (1<<19)
 492 #define NV_RX2_ERROR3           (1<<20)
 493 #define NV_RX2_ERROR4           (1<<21)
 494 #define NV_RX2_CRCERR           (1<<22)
 495 #define NV_RX2_OVERFLOW         (1<<23)
 496 #define NV_RX2_FRAMINGERR       (1<<24)
 497 /* error and avail are the same for both */
 498 #define NV_RX2_ERROR            (1<<30)
 499 #define NV_RX2_AVAIL            (1<<31)
 500
 501 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 502 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 503
 504 /* Miscelaneous hardware related defines: */
 505 #define NV_PCI_REGSZ_VER1       0x270
 506 #define NV_PCI_REGSZ_VER2       0x2d4
 507 #define NV_PCI_REGSZ_VER3       0x604
 508
 509 /* various timeout delays: all in usec */
 510 #define NV_TXRX_RESET_DELAY     4
 511 #define NV_TXSTOP_DELAY1        10
 512 #define NV_TXSTOP_DELAY1MAX     500000
 513 #define NV_TXSTOP_DELAY2        100
 514 #define NV_RXSTOP_DELAY1        10
 515 #define NV_RXSTOP_DELAY1MAX     500000
 516 #define NV_RXSTOP_DELAY2        100
 517 #define NV_SETUP5_DELAY         5
 518 #define NV_SETUP5_DELAYMAX      50000
 519 #define NV_POWERUP_DELAY        5
 520 #define NV_POWERUP_DELAYMAX     5000
 521 #define NV_MIIBUSY_DELAY        50
 522 #define NV_MIIPHY_DELAY 10
 523 #define NV_MIIPHY_DELAYMAX      10000
 524 #define NV_MAC_RESET_DELAY      64
 525
 526 #define NV_WAKEUPPATTERNS       5
 527 #define NV_WAKEUPMASKENTRIES    4
 528
 529 /* General driver defaults */
 530 #define NV_WATCHDOG_TIMEO       (5*HZ)
 531
 532 #define RX_RING_DEFAULT         128
 533 #define TX_RING_DEFAULT         256
 534 #define RX_RING_MIN             128
 535 #define TX_RING_MIN             64
 536 #define RING_MAX_DESC_VER_1     1024
 537 #define RING_MAX_DESC_VER_2_3   16384
 538
 539 /* rx/tx mac addr + type + vlan + align + slack*/
 540 #define NV_RX_HEADERS           (64)
 541 /* even more slack. */
 542 #define NV_RX_ALLOC_PAD         (64)
 543
 544 /* maximum mtu size */
 545 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 546 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 547
 548 #define OOM_REFILL      (1+HZ/20)
 549 #define POLL_WAIT       (1+HZ/100)
 550 #define LINK_TIMEOUT    (3*HZ)
 551 #define STATS_INTERVAL  (10*HZ)
 552
 553 /*
 554  * desc_ver values:
 555  * The nic supports three different descriptor types:
 556  * - DESC_VER_1: Original
 557  * - DESC_VER_2: support for jumbo frames.
 558  * - DESC_VER_3: 64-bit format.
 559  */
 560 #define DESC_VER_1      1
 561 #define DESC_VER_2      2
 562 #define DESC_VER_3      3
 563
 564 /* PHY defines */
 565 #define PHY_OUI_MARVELL 0x5043
 566 #define PHY_OUI_CICADA  0x03f1
 567 #define PHY_OUI_VITESSE 0x01c1
 568 #define PHY_OUI_REALTEK 0x0732
 569 #define PHYID1_OUI_MASK 0x03ff
 570 #define PHYID1_OUI_SHFT 6
 571 #define PHYID2_OUI_MASK 0xfc00
 572 #define PHYID2_OUI_SHFT 10
 573 #define PHYID2_MODEL_MASK               0x03f0
 574 #define PHY_MODEL_MARVELL_E3016         0x220
 575 #define PHY_MARVELL_E3016_INITMASK      0x0300
 576 #define PHY_CICADA_INIT1        0x0f000
 577 #define PHY_CICADA_INIT2        0x0e00
 578 #define PHY_CICADA_INIT3        0x01000
 579 #define PHY_CICADA_INIT4        0x0200
 580 #define PHY_CICADA_INIT5        0x0004
 581 #define PHY_CICADA_INIT6        0x02000
 582 #define PHY_VITESSE_INIT_REG1   0x1f
 583 #define PHY_VITESSE_INIT_REG2   0x10
 584 #define PHY_VITESSE_INIT_REG3   0x11
 585 #define PHY_VITESSE_INIT_REG4   0x12
 586 #define PHY_VITESSE_INIT_MSK1   0xc
 587 #define PHY_VITESSE_INIT_MSK2   0x0180
 588 #define PHY_VITESSE_INIT1       0x52b5
 589 #define PHY_VITESSE_INIT2       0xaf8a
 590 #define PHY_VITESSE_INIT3       0x8
 591 #define PHY_VITESSE_INIT4       0x8f8a
 592 #define PHY_VITESSE_INIT5       0xaf86
 593 #define PHY_VITESSE_INIT6       0x8f86
 594 #define PHY_VITESSE_INIT7       0xaf82
 595 #define PHY_VITESSE_INIT8       0x0100
 596 #define PHY_VITESSE_INIT9       0x8f82
 597 #define PHY_VITESSE_INIT10      0x0
 598 #define PHY_REALTEK_INIT_REG1   0x1f
 599 #define PHY_REALTEK_INIT_REG2   0x19
 600 #define PHY_REALTEK_INIT_REG3   0x13
 601 #define PHY_REALTEK_INIT1       0x0000
 602 #define PHY_REALTEK_INIT2       0x8e00
 603 #define PHY_REALTEK_INIT3       0x0001
 604 #define PHY_REALTEK_INIT4       0xad17
 605
 606 #define PHY_GIGABIT     0x0100
 607
 608 #define PHY_TIMEOUT     0x1
 609 #define PHY_ERROR       0x2
 610
 611 #define PHY_100 0x1
 612 #define PHY_1000        0x2
 613 #define PHY_HALF        0x100
 614
 615 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 616 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 617 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 618 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 619 #define NV_PAUSEFRAME_RX_REQ     0x0010
 620 #define NV_PAUSEFRAME_TX_REQ     0x0020
 621 #define NV_PAUSEFRAME_AUTONEG    0x0040
 622
 623 /* MSI/MSI-X defines */
 624 #define NV_MSI_X_MAX_VECTORS  8
 625 #define NV_MSI_X_VECTORS_MASK 0x000f
 626 #define NV_MSI_CAPABLE        0x0010
 627 #define NV_MSI_X_CAPABLE      0x0020
 628 #define NV_MSI_ENABLED        0x0040
 629 #define NV_MSI_X_ENABLED      0x0080
 630
 631 #define NV_MSI_X_VECTOR_ALL   0x0
 632 #define NV_MSI_X_VECTOR_RX    0x0
 633 #define NV_MSI_X_VECTOR_TX    0x1
 634 #define NV_MSI_X_VECTOR_OTHER 0x2
 635
 636 #define NV_RESTART_TX         0x1
 637 #define NV_RESTART_RX         0x2
 638
 639 #define NV_TX_LIMIT_COUNT     16
 640
 641 /* statistics */
 642 struct nv_ethtool_str {
 643         char name[ETH_GSTRING_LEN];
 644 };
 645
 646 static const struct nv_ethtool_str nv_estats_str[] = {
 647         { "tx_bytes" },
 648         { "tx_zero_rexmt" },
 649         { "tx_one_rexmt" },
 650         { "tx_many_rexmt" },
 651         { "tx_late_collision" },
 652         { "tx_fifo_errors" },
 653         { "tx_carrier_errors" },
 654         { "tx_excess_deferral" },
 655         { "tx_retry_error" },
 656         { "rx_frame_error" },
 657         { "rx_extra_byte" },
 658         { "rx_late_collision" },
 659         { "rx_runt" },
 660         { "rx_frame_too_long" },
 661         { "rx_over_errors" },
 662         { "rx_crc_errors" },
 663         { "rx_frame_align_error" },
 664         { "rx_length_error" },
 665         { "rx_unicast" },
 666         { "rx_multicast" },
 667         { "rx_broadcast" },
 668         { "rx_packets" },
 669         { "rx_errors_total" },
 670         { "tx_errors_total" },
 671
 672         /* version 2 stats */
 673         { "tx_deferral" },
 674         { "tx_packets" },
 675         { "rx_bytes" },
 676         { "tx_pause" },
 677         { "rx_pause" },
 678         { "rx_drop_frame" }
 679 };
 680
 681 struct nv_ethtool_stats {
 682         u64 tx_bytes;
 683         u64 tx_zero_rexmt;
 684         u64 tx_one_rexmt;
 685         u64 tx_many_rexmt;
 686         u64 tx_late_collision;
 687         u64 tx_fifo_errors;
 688         u64 tx_carrier_errors;
 689         u64 tx_excess_deferral;
 690         u64 tx_retry_error;
 691         u64 rx_frame_error;
 692         u64 rx_extra_byte;
 693         u64 rx_late_collision;
 694         u64 rx_runt;
 695         u64 rx_frame_too_long;
 696         u64 rx_over_errors;
 697         u64 rx_crc_errors;
 698         u64 rx_frame_align_error;
 699         u64 rx_length_error;
 700         u64 rx_unicast;
 701         u64 rx_multicast;
 702         u64 rx_broadcast;
 703         u64 rx_packets;
 704         u64 rx_errors_total;
 705         u64 tx_errors_total;
 706
 707         /* version 2 stats */
 708         u64 tx_deferral;
 709         u64 tx_packets;
 710         u64 rx_bytes;
 711         u64 tx_pause;
 712         u64 rx_pause;
 713         u64 rx_drop_frame;
 714 };
 715
 716 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 717 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 718
 719 /* diagnostics */
 720 #define NV_TEST_COUNT_BASE 3
 721 #define NV_TEST_COUNT_EXTENDED 4
 722
 723 static const struct nv_ethtool_str nv_etests_str[] = {
 724         { "link      (online/offline)" },
 725         { "register  (offline)       " },
 726         { "interrupt (offline)       " },
 727         { "loopback  (offline)       " }
 728 };
 729
 730 struct register_test {
 731         __u32 reg;
 732         __u32 mask;
 733 };
 734
 735 static const struct register_test nv_registers_test[] = {
 736         { NvRegUnknownSetupReg6, 0x01 },
 737         { NvRegMisc1, 0x03c },
 738         { NvRegOffloadConfig, 0x03ff },
 739         { NvRegMulticastAddrA, 0xffffffff },
 740         { NvRegTxWatermark, 0x0ff },
 741         { NvRegWakeUpFlags, 0x07777 },
 742         { 0,0 }
 743 };
 744
 745 struct nv_skb_map {
 746         struct sk_buff *skb;
 747         dma_addr_t dma;
 748         unsigned int dma_len;
 749         struct ring_desc_ex *first_tx_desc;
 750         struct nv_skb_map *next_tx_ctx;
 751 };
 752
 753 /*
 754  * SMP locking:
 755  * All hardware access under dev->priv->lock, except the performance
 756  * critical parts:
 757  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 758  *      by the arch code for interrupts.
 759  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 760  *      needs dev->priv->lock :-(
 761  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 762  */
 763
 764 /* in dev: base, irq */
 765 struct fe_priv {
 766         spinlock_t lock;
 767
 768         struct net_device *dev;
 769         struct napi_struct napi;
 770
 771         /* General data:
 772          * Locking: spin_lock(&np->lock); */
 773         struct nv_ethtool_stats estats;
 774         int in_shutdown;
 775         u32 linkspeed;
 776         int duplex;
 777         int autoneg;
 778         int fixed_mode;
 779         int phyaddr;
 780         int wolenabled;
 781         unsigned int phy_oui;
 782         unsigned int phy_model;
 783         u16 gigabit;
 784         int intr_test;
 785         int recover_error;
 786
 787         /* General data: RO fields */
 788         dma_addr_t ring_addr;
 789         struct pci_dev *pci_dev;
 790         u32 orig_mac[2];
 791         u32 irqmask;
 792         u32 desc_ver;
 793         u32 txrxctl_bits;
 794         u32 vlanctl_bits;
 795         u32 driver_data;
 796         u32 register_size;
 797         int rx_csum;
 798         u32 mac_in_use;
 799
 800         void __iomem *base;
 801
 802         /* rx specific fields.
 803          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 804          */
 805         union ring_type get_rx, put_rx, first_rx, last_rx;
 806         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 807         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 808         struct nv_skb_map *rx_skb;
 809
 810         union ring_type rx_ring;
 811         unsigned int rx_buf_sz;
 812         unsigned int pkt_limit;
 813         struct timer_list oom_kick;
 814         struct timer_list nic_poll;
 815         struct timer_list stats_poll;
 816         u32 nic_poll_irq;
 817         int rx_ring_size;
 818
 819         /* media detection workaround.
 820          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 821          */
 822         int need_linktimer;
 823         unsigned long link_timeout;
 824         /*
 825          * tx specific fields.
 826          */
 827         union ring_type get_tx, put_tx, first_tx, last_tx;
 828         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 829         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 830         struct nv_skb_map *tx_skb;
 831
 832         union ring_type tx_ring;
 833         u32 tx_flags;
 834         int tx_ring_size;
 835         int tx_limit;
 836         u32 tx_pkts_in_progress;
 837         struct nv_skb_map *tx_change_owner;
 838         struct nv_skb_map *tx_end_flip;
 839         int tx_stop;
 840
 841         /* vlan fields */
 842         struct vlan_group *vlangrp;
 843
 844         /* msi/msi-x fields */
 845         u32 msi_flags;
 846         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 847
 848         /* flow control */
 849         u32 pause_flags;
 850 };
 851
 852 /*
 853  * Maximum number of loops until we assume that a bit in the irq mask
 854  * is stuck. Overridable with module param.
 855  */
 856 static int max_interrupt_work = 5;
 857
 858 /*
 859  * Optimization can be either throuput mode or cpu mode
 860  *
 861  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 862  * CPU Mode: Interrupts are controlled by a timer.
 863  */
 864 enum {
 865         NV_OPTIMIZATION_MODE_THROUGHPUT,
 866         NV_OPTIMIZATION_MODE_CPU
 867 };
 868 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 869
 870 /*
 871  * Poll interval for timer irq
 872  *
 873  * This interval determines how frequent an interrupt is generated.
 874  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 875  * Min = 0, and Max = 65535
 876  */
 877 static int poll_interval = -1;
 878
 879 /*
 880  * MSI interrupts
 881  */
 882 enum {
 883         NV_MSI_INT_DISABLED,
 884         NV_MSI_INT_ENABLED
 885 };
 886 static int msi = NV_MSI_INT_ENABLED;
 887
 888 /*
 889  * MSIX interrupts
 890  */
 891 enum {
 892         NV_MSIX_INT_DISABLED,
 893         NV_MSIX_INT_ENABLED
 894 };
 895 static int msix = NV_MSIX_INT_DISABLED;
 896
 897 /*
 898  * DMA 64bit
 899  */
 900 enum {
 901         NV_DMA_64BIT_DISABLED,
 902         NV_DMA_64BIT_ENABLED
 903 };
 904 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 905
 906 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 907 {
 908         return netdev_priv(dev);
 909 }
 910
 911 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 912 {
 913         return ((struct fe_priv *)netdev_priv(dev))->base;
 914 }
 915
 916 static inline void pci_push(u8 __iomem *base)
 917 {
 918         /* force out pending posted writes */
 919         readl(base);
 920 }
 921
 922 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 923 {
 924         return le32_to_cpu(prd->flaglen)
 925                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 926 }
 927
 928 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 929 {
 930         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 931 }
 932
 933 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 934                                 int delay, int delaymax, const char *msg)
 935 {
 936         u8 __iomem *base = get_hwbase(dev);
 937
 938         pci_push(base);
 939         do {
 940                 udelay(delay);
 941                 delaymax -= delay;
 942                 if (delaymax < 0) {
 943                         if (msg)
 944                                 printk(msg);
 945                         return 1;
 946                 }
 947         } while ((readl(base + offset) & mask) != target);
 948         return 0;
 949 }
 950
 951 #define NV_SETUP_RX_RING 0x01
 952 #define NV_SETUP_TX_RING 0x02
 953
 954 static inline u32 dma_low(dma_addr_t addr)
 955 {
 956         return addr;
 957 }
 958
 959 static inline u32 dma_high(dma_addr_t addr)
 960 {
 961         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 962 }
 963
 964 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 965 {
 966         struct fe_priv *np = get_nvpriv(dev);
 967         u8 __iomem *base = get_hwbase(dev);
 968
 969         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 970                 if (rxtx_flags & NV_SETUP_RX_RING) {
 971                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 972                 }
 973                 if (rxtx_flags & NV_SETUP_TX_RING) {
 974                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 975                 }
 976         } else {
 977                 if (rxtx_flags & NV_SETUP_RX_RING) {
 978                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 979                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 980                 }
 981                 if (rxtx_flags & NV_SETUP_TX_RING) {
 982                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 983                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 984                 }
 985         }
 986 }
 987
 988 static void free_rings(struct net_device *dev)
 989 {
 990         struct fe_priv *np = get_nvpriv(dev);
 991
 992         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 993                 if (np->rx_ring.orig)
 994                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 995                                             np->rx_ring.orig, np->ring_addr);
 996         } else {
 997                 if (np->rx_ring.ex)
 998                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 999                                             np->rx_ring.ex, np->ring_addr);
1000         }
1001         if (np->rx_skb)
1002                 kfree(np->rx_skb);
1003         if (np->tx_skb)
1004                 kfree(np->tx_skb);
1005 }
1006
1007 static int using_multi_irqs(struct net_device *dev)
1008 {
1009         struct fe_priv *np = get_nvpriv(dev);
1010
1011         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1012             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1013              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1014                 return 0;
1015         else
1016                 return 1;
1017 }
1018
1019 static void nv_enable_irq(struct net_device *dev)
1020 {
1021         struct fe_priv *np = get_nvpriv(dev);
1022
1023         if (!using_multi_irqs(dev)) {
1024                 if (np->msi_flags & NV_MSI_X_ENABLED)
1025                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1026                 else
1027                         enable_irq(np->pci_dev->irq);
1028         } else {
1029                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1030                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1031                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1032         }
1033 }
1034
1035 static void nv_disable_irq(struct net_device *dev)
1036 {
1037         struct fe_priv *np = get_nvpriv(dev);
1038
1039         if (!using_multi_irqs(dev)) {
1040                 if (np->msi_flags & NV_MSI_X_ENABLED)
1041                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1042                 else
1043                         disable_irq(np->pci_dev->irq);
1044         } else {
1045                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1046                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1047                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1048         }
1049 }
1050
1051 /* In MSIX mode, a write to irqmask behaves as XOR */
1052 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1053 {
1054         u8 __iomem *base = get_hwbase(dev);
1055
1056         writel(mask, base + NvRegIrqMask);
1057 }
1058
1059 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1060 {
1061         struct fe_priv *np = get_nvpriv(dev);
1062         u8 __iomem *base = get_hwbase(dev);
1063
1064         if (np->msi_flags & NV_MSI_X_ENABLED) {
1065                 writel(mask, base + NvRegIrqMask);
1066         } else {
1067                 if (np->msi_flags & NV_MSI_ENABLED)
1068                         writel(0, base + NvRegMSIIrqMask);
1069                 writel(0, base + NvRegIrqMask);
1070         }
1071 }
1072
1073 #define MII_READ        (-1)
1074 /* mii_rw: read/write a register on the PHY.
1075  *
1076  * Caller must guarantee serialization
1077  */
1078 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1079 {
1080         u8 __iomem *base = get_hwbase(dev);
1081         u32 reg;
1082         int retval;
1083
1084         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1085
1086         reg = readl(base + NvRegMIIControl);
1087         if (reg & NVREG_MIICTL_INUSE) {
1088                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1089                 udelay(NV_MIIBUSY_DELAY);
1090         }
1091
1092         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1093         if (value != MII_READ) {
1094                 writel(value, base + NvRegMIIData);
1095                 reg |= NVREG_MIICTL_WRITE;
1096         }
1097         writel(reg, base + NvRegMIIControl);
1098
1099         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1100                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1101                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1102                                 dev->name, miireg, addr);
1103                 retval = -1;
1104         } else if (value != MII_READ) {
1105                 /* it was a write operation - fewer failures are detectable */
1106                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1107                                 dev->name, value, miireg, addr);
1108                 retval = 0;
1109         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1110                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1111                                 dev->name, miireg, addr);
1112                 retval = -1;
1113         } else {
1114                 retval = readl(base + NvRegMIIData);
1115                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1116                                 dev->name, miireg, addr, retval);
1117         }
1118
1119         return retval;
1120 }
1121
1122 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1123 {
1124         struct fe_priv *np = netdev_priv(dev);
1125         u32 miicontrol;
1126         unsigned int tries = 0;
1127
1128         miicontrol = BMCR_RESET | bmcr_setup;
1129         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1130                 return -1;
1131         }
1132
1133         /* wait for 500ms */
1134         msleep(500);
1135
1136         /* must wait till reset is deasserted */
1137         while (miicontrol & BMCR_RESET) {
1138                 msleep(10);
1139                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1140                 /* FIXME: 100 tries seem excessive */
1141                 if (tries++ > 100)
1142                         return -1;
1143         }
1144         return 0;
1145 }
1146
1147 static int phy_init(struct net_device *dev)
1148 {
1149         struct fe_priv *np = get_nvpriv(dev);
1150         u8 __iomem *base = get_hwbase(dev);
1151         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1152
1153         /* phy errata for E3016 phy */
1154         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1155                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1156                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1157                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1158                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1159                         return PHY_ERROR;
1160                 }
1161         }
1162         if (np->phy_oui == PHY_OUI_REALTEK) {
1163                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1164                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165                         return PHY_ERROR;
1166                 }
1167                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1168                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1169                         return PHY_ERROR;
1170                 }
1171                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1172                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1173                         return PHY_ERROR;
1174                 }
1175                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1176                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1177                         return PHY_ERROR;
1178                 }
1179                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1180                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1181                         return PHY_ERROR;
1182                 }
1183         }
1184
1185         /* set advertise register */
1186         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1187         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1188         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1189                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1190                 return PHY_ERROR;
1191         }
1192
1193         /* get phy interface type */
1194         phyinterface = readl(base + NvRegPhyInterface);
1195
1196         /* see if gigabit phy */
1197         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1198         if (mii_status & PHY_GIGABIT) {
1199                 np->gigabit = PHY_GIGABIT;
1200                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1201                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1202                 if (phyinterface & PHY_RGMII)
1203                         mii_control_1000 |= ADVERTISE_1000FULL;
1204                 else
1205                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1206
1207                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1208                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209                         return PHY_ERROR;
1210                 }
1211         }
1212         else
1213                 np->gigabit = 0;
1214
1215         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1216         mii_control |= BMCR_ANENABLE;
1217
1218         /* reset the phy
1219          * (certain phys need bmcr to be setup with reset)
1220          */
1221         if (phy_reset(dev, mii_control)) {
1222                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1223                 return PHY_ERROR;
1224         }
1225
1226         /* phy vendor specific configuration */
1227         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1228                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1229                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1230                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1231                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1232                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233                         return PHY_ERROR;
1234                 }
1235                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1236                 phy_reserved |= PHY_CICADA_INIT5;
1237                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1238                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239                         return PHY_ERROR;
1240                 }
1241         }
1242         if (np->phy_oui == PHY_OUI_CICADA) {
1243                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1244                 phy_reserved |= PHY_CICADA_INIT6;
1245                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1246                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1247                         return PHY_ERROR;
1248                 }
1249         }
1250         if (np->phy_oui == PHY_OUI_VITESSE) {
1251                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1252                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1253                         return PHY_ERROR;
1254                 }
1255                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1256                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1257                         return PHY_ERROR;
1258                 }
1259                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1260                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1261                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1262                         return PHY_ERROR;
1263                 }
1264                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1265                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1266                 phy_reserved |= PHY_VITESSE_INIT3;
1267                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1268                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1269                         return PHY_ERROR;
1270                 }
1271                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1272                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1273                         return PHY_ERROR;
1274                 }
1275                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1276                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1277                         return PHY_ERROR;
1278                 }
1279                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1280                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1281                 phy_reserved |= PHY_VITESSE_INIT3;
1282                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1283                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284                         return PHY_ERROR;
1285                 }
1286                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1287                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1288                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1289                         return PHY_ERROR;
1290                 }
1291                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1292                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1293                         return PHY_ERROR;
1294                 }
1295                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1296                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1297                         return PHY_ERROR;
1298                 }
1299                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1300                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1301                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1302                         return PHY_ERROR;
1303                 }
1304                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1305                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1306                 phy_reserved |= PHY_VITESSE_INIT8;
1307                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1308                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1309                         return PHY_ERROR;
1310                 }
1311                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1312                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1313                         return PHY_ERROR;
1314                 }
1315                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1316                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1317                         return PHY_ERROR;
1318                 }
1319         }
1320         if (np->phy_oui == PHY_OUI_REALTEK) {
1321                 /* reset could have cleared these out, set them back */
1322                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1323                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324                         return PHY_ERROR;
1325                 }
1326                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1327                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328                         return PHY_ERROR;
1329                 }
1330                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1331                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332                         return PHY_ERROR;
1333                 }
1334                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1335                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336                         return PHY_ERROR;
1337                 }
1338                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1339                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1340                         return PHY_ERROR;
1341                 }
1342         }
1343
1344         /* some phys clear out pause advertisment on reset, set it back */
1345         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1346
1347         /* restart auto negotiation */
1348         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1349         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1350         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1351                 return PHY_ERROR;
1352         }
1353
1354         return 0;
1355 }
1356
1357 static void nv_start_rx(struct net_device *dev)
1358 {
1359         struct fe_priv *np = netdev_priv(dev);
1360         u8 __iomem *base = get_hwbase(dev);
1361         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1362
1363         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1364         /* Already running? Stop it. */
1365         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1366                 rx_ctrl &= ~NVREG_RCVCTL_START;
1367                 writel(rx_ctrl, base + NvRegReceiverControl);
1368                 pci_push(base);
1369         }
1370         writel(np->linkspeed, base + NvRegLinkSpeed);
1371         pci_push(base);
1372         rx_ctrl |= NVREG_RCVCTL_START;
1373         if (np->mac_in_use)
1374                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1375         writel(rx_ctrl, base + NvRegReceiverControl);
1376         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1377                                 dev->name, np->duplex, np->linkspeed);
1378         pci_push(base);
1379 }
1380
1381 static void nv_stop_rx(struct net_device *dev)
1382 {
1383         struct fe_priv *np = netdev_priv(dev);
1384         u8 __iomem *base = get_hwbase(dev);
1385         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1386
1387         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1388         if (!np->mac_in_use)
1389                 rx_ctrl &= ~NVREG_RCVCTL_START;
1390         else
1391                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1392         writel(rx_ctrl, base + NvRegReceiverControl);
1393         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1394                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1395                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1396
1397         udelay(NV_RXSTOP_DELAY2);
1398         if (!np->mac_in_use)
1399                 writel(0, base + NvRegLinkSpeed);
1400 }
1401
1402 static void nv_start_tx(struct net_device *dev)
1403 {
1404         struct fe_priv *np = netdev_priv(dev);
1405         u8 __iomem *base = get_hwbase(dev);
1406         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1407
1408         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1409         tx_ctrl |= NVREG_XMITCTL_START;
1410         if (np->mac_in_use)
1411                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1412         writel(tx_ctrl, base + NvRegTransmitterControl);
1413         pci_push(base);
1414 }
1415
1416 static void nv_stop_tx(struct net_device *dev)
1417 {
1418         struct fe_priv *np = netdev_priv(dev);
1419         u8 __iomem *base = get_hwbase(dev);
1420         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1421
1422         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1423         if (!np->mac_in_use)
1424                 tx_ctrl &= ~NVREG_XMITCTL_START;
1425         else
1426                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1427         writel(tx_ctrl, base + NvRegTransmitterControl);
1428         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1429                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1430                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1431
1432         udelay(NV_TXSTOP_DELAY2);
1433         if (!np->mac_in_use)
1434                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1435                        base + NvRegTransmitPoll);
1436 }
1437
1438 static void nv_txrx_reset(struct net_device *dev)
1439 {
1440         struct fe_priv *np = netdev_priv(dev);
1441         u8 __iomem *base = get_hwbase(dev);
1442
1443         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1444         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1445         pci_push(base);
1446         udelay(NV_TXRX_RESET_DELAY);
1447         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1448         pci_push(base);
1449 }
1450
1451 static void nv_mac_reset(struct net_device *dev)
1452 {
1453         struct fe_priv *np = netdev_priv(dev);
1454         u8 __iomem *base = get_hwbase(dev);
1455         u32 temp1, temp2, temp3;
1456
1457         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1458
1459         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1460         pci_push(base);
1461
1462         /* save registers since they will be cleared on reset */
1463         temp1 = readl(base + NvRegMacAddrA);
1464         temp2 = readl(base + NvRegMacAddrB);
1465         temp3 = readl(base + NvRegTransmitPoll);
1466
1467         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1468         pci_push(base);
1469         udelay(NV_MAC_RESET_DELAY);
1470         writel(0, base + NvRegMacReset);
1471         pci_push(base);
1472         udelay(NV_MAC_RESET_DELAY);
1473
1474         /* restore saved registers */
1475         writel(temp1, base + NvRegMacAddrA);
1476         writel(temp2, base + NvRegMacAddrB);
1477         writel(temp3, base + NvRegTransmitPoll);
1478
1479         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1480         pci_push(base);
1481 }
1482
1483 static void nv_get_hw_stats(struct net_device *dev)
1484 {
1485         struct fe_priv *np = netdev_priv(dev);
1486         u8 __iomem *base = get_hwbase(dev);
1487
1488         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1489         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1490         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1491         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1492         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1493         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1494         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1495         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1496         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1497         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1498         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1499         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1500         np->estats.rx_runt += readl(base + NvRegRxRunt);
1501         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1502         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1503         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1504         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1505         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1506         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1507         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1508         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1509         np->estats.rx_packets =
1510                 np->estats.rx_unicast +
1511                 np->estats.rx_multicast +
1512                 np->estats.rx_broadcast;
1513         np->estats.rx_errors_total =
1514                 np->estats.rx_crc_errors +
1515                 np->estats.rx_over_errors +
1516                 np->estats.rx_frame_error +
1517                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1518                 np->estats.rx_late_collision +
1519                 np->estats.rx_runt +
1520                 np->estats.rx_frame_too_long;
1521         np->estats.tx_errors_total =
1522                 np->estats.tx_late_collision +
1523                 np->estats.tx_fifo_errors +
1524                 np->estats.tx_carrier_errors +
1525                 np->estats.tx_excess_deferral +
1526                 np->estats.tx_retry_error;
1527
1528         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1529                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1530                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1531                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1532                 np->estats.tx_pause += readl(base + NvRegTxPause);
1533                 np->estats.rx_pause += readl(base + NvRegRxPause);
1534                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1535         }
1536 }
1537
1538 /*
1539  * nv_get_stats: dev->get_stats function
1540  * Get latest stats value from the nic.
1541  * Called with read_lock(&dev_base_lock) held for read -
1542  * only synchronized against unregister_netdevice.
1543  */
1544 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1545 {
1546         struct fe_priv *np = netdev_priv(dev);
1547
1548         /* If the nic supports hw counters then retrieve latest values */
1549         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1550                 nv_get_hw_stats(dev);
1551
1552                 /* copy to net_device stats */
1553                 dev->stats.tx_bytes = np->estats.tx_bytes;
1554                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1555                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1556                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1557                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1558                 dev->stats.rx_errors = np->estats.rx_errors_total;
1559                 dev->stats.tx_errors = np->estats.tx_errors_total;
1560         }
1561
1562         return &dev->stats;
1563 }
1564
1565 /*
1566  * nv_alloc_rx: fill rx ring entries.
1567  * Return 1 if the allocations for the skbs failed and the
1568  * rx engine is without Available descriptors
1569  */
1570 static int nv_alloc_rx(struct net_device *dev)
1571 {
1572         struct fe_priv *np = netdev_priv(dev);
1573         struct ring_desc* less_rx;
1574
1575         less_rx = np->get_rx.orig;
1576         if (less_rx-- == np->first_rx.orig)
1577                 less_rx = np->last_rx.orig;
1578
1579         while (np->put_rx.orig != less_rx) {
1580                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1581                 if (skb) {
1582                         np->put_rx_ctx->skb = skb;
1583                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1584                                                              skb->data,
1585                                                              skb_tailroom(skb),
1586                                                              PCI_DMA_FROMDEVICE);
1587                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1588                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1589                         wmb();
1590                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1591                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1592                                 np->put_rx.orig = np->first_rx.orig;
1593                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1594                                 np->put_rx_ctx = np->first_rx_ctx;
1595                 } else {
1596                         return 1;
1597                 }
1598         }
1599         return 0;
1600 }
1601
1602 static int nv_alloc_rx_optimized(struct net_device *dev)
1603 {
1604         struct fe_priv *np = netdev_priv(dev);
1605         struct ring_desc_ex* less_rx;
1606
1607         less_rx = np->get_rx.ex;
1608         if (less_rx-- == np->first_rx.ex)
1609                 less_rx = np->last_rx.ex;
1610
1611         while (np->put_rx.ex != less_rx) {
1612                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1613                 if (skb) {
1614                         np->put_rx_ctx->skb = skb;
1615                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1616                                                              skb->data,
1617                                                              skb_tailroom(skb),
1618                                                              PCI_DMA_FROMDEVICE);
1619                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1620                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1621                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1622                         wmb();
1623                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1624                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1625                                 np->put_rx.ex = np->first_rx.ex;
1626                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1627                                 np->put_rx_ctx = np->first_rx_ctx;
1628                 } else {
1629                         return 1;
1630                 }
1631         }
1632         return 0;
1633 }
1634
1635 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1636 #ifdef CONFIG_FORCEDETH_NAPI
1637 static void nv_do_rx_refill(unsigned long data)
1638 {
1639         struct net_device *dev = (struct net_device *) data;
1640         struct fe_priv *np = netdev_priv(dev);
1641
1642         /* Just reschedule NAPI rx processing */
1643         netif_rx_schedule(dev, &np->napi);
1644 }
1645 #else
1646 static void nv_do_rx_refill(unsigned long data)
1647 {
1648         struct net_device *dev = (struct net_device *) data;
1649         struct fe_priv *np = netdev_priv(dev);
1650         int retcode;
1651
1652         if (!using_multi_irqs(dev)) {
1653                 if (np->msi_flags & NV_MSI_X_ENABLED)
1654                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1655                 else
1656                         disable_irq(np->pci_dev->irq);
1657         } else {
1658                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1659         }
1660         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1661                 retcode = nv_alloc_rx(dev);
1662         else
1663                 retcode = nv_alloc_rx_optimized(dev);
1664         if (retcode) {
1665                 spin_lock_irq(&np->lock);
1666                 if (!np->in_shutdown)
1667                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1668                 spin_unlock_irq(&np->lock);
1669         }
1670         if (!using_multi_irqs(dev)) {
1671                 if (np->msi_flags & NV_MSI_X_ENABLED)
1672                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1673                 else
1674                         enable_irq(np->pci_dev->irq);
1675         } else {
1676                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1677         }
1678 }
1679 #endif
1680
1681 static void nv_init_rx(struct net_device *dev)
1682 {
1683         struct fe_priv *np = netdev_priv(dev);
1684         int i;
1685         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1686         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1687                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1688         else
1689                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1690         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1691         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1692
1693         for (i = 0; i < np->rx_ring_size; i++) {
1694                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1695                         np->rx_ring.orig[i].flaglen = 0;
1696                         np->rx_ring.orig[i].buf = 0;
1697                 } else {
1698                         np->rx_ring.ex[i].flaglen = 0;
1699                         np->rx_ring.ex[i].txvlan = 0;
1700                         np->rx_ring.ex[i].bufhigh = 0;
1701                         np->rx_ring.ex[i].buflow = 0;
1702                 }
1703                 np->rx_skb[i].skb = NULL;
1704                 np->rx_skb[i].dma = 0;
1705         }
1706 }
1707
1708 static void nv_init_tx(struct net_device *dev)
1709 {
1710         struct fe_priv *np = netdev_priv(dev);
1711         int i;
1712         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1713         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1714                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1715         else
1716                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1717         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1718         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1719         np->tx_pkts_in_progress = 0;
1720         np->tx_change_owner = NULL;
1721         np->tx_end_flip = NULL;
1722
1723         for (i = 0; i < np->tx_ring_size; i++) {
1724                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1725                         np->tx_ring.orig[i].flaglen = 0;
1726                         np->tx_ring.orig[i].buf = 0;
1727                 } else {
1728                         np->tx_ring.ex[i].flaglen = 0;
1729                         np->tx_ring.ex[i].txvlan = 0;
1730                         np->tx_ring.ex[i].bufhigh = 0;
1731                         np->tx_ring.ex[i].buflow = 0;
1732                 }
1733                 np->tx_skb[i].skb = NULL;
1734                 np->tx_skb[i].dma = 0;
1735                 np->tx_skb[i].dma_len = 0;
1736                 np->tx_skb[i].first_tx_desc = NULL;
1737                 np->tx_skb[i].next_tx_ctx = NULL;
1738         }
1739 }
1740
1741 static int nv_init_ring(struct net_device *dev)
1742 {
1743         struct fe_priv *np = netdev_priv(dev);
1744
1745         nv_init_tx(dev);
1746         nv_init_rx(dev);
1747         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1748                 return nv_alloc_rx(dev);
1749         else
1750                 return nv_alloc_rx_optimized(dev);
1751 }
1752
1753 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1754 {
1755         struct fe_priv *np = netdev_priv(dev);
1756
1757         if (tx_skb->dma) {
1758                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1759                                tx_skb->dma_len,
1760                                PCI_DMA_TODEVICE);
1761                 tx_skb->dma = 0;
1762         }
1763         if (tx_skb->skb) {
1764                 dev_kfree_skb_any(tx_skb->skb);
1765                 tx_skb->skb = NULL;
1766                 return 1;
1767         } else {
1768                 return 0;
1769         }
1770 }
1771
1772 static void nv_drain_tx(struct net_device *dev)
1773 {
1774         struct fe_priv *np = netdev_priv(dev);
1775         unsigned int i;
1776
1777         for (i = 0; i < np->tx_ring_size; i++) {
1778                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1779                         np->tx_ring.orig[i].flaglen = 0;
1780                         np->tx_ring.orig[i].buf = 0;
1781                 } else {
1782                         np->tx_ring.ex[i].flaglen = 0;
1783                         np->tx_ring.ex[i].txvlan = 0;
1784                         np->tx_ring.ex[i].bufhigh = 0;
1785                         np->tx_ring.ex[i].buflow = 0;
1786                 }
1787                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1788                         dev->stats.tx_dropped++;
1789                 np->tx_skb[i].dma = 0;
1790                 np->tx_skb[i].dma_len = 0;
1791                 np->tx_skb[i].first_tx_desc = NULL;
1792                 np->tx_skb[i].next_tx_ctx = NULL;
1793         }
1794         np->tx_pkts_in_progress = 0;
1795         np->tx_change_owner = NULL;
1796         np->tx_end_flip = NULL;
1797 }
1798
1799 static void nv_drain_rx(struct net_device *dev)
1800 {
1801         struct fe_priv *np = netdev_priv(dev);
1802         int i;
1803
1804         for (i = 0; i < np->rx_ring_size; i++) {
1805                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1806                         np->rx_ring.orig[i].flaglen = 0;
1807                         np->rx_ring.orig[i].buf = 0;
1808                 } else {
1809                         np->rx_ring.ex[i].flaglen = 0;
1810                         np->rx_ring.ex[i].txvlan = 0;
1811                         np->rx_ring.ex[i].bufhigh = 0;
1812                         np->rx_ring.ex[i].buflow = 0;
1813                 }
1814                 wmb();
1815                 if (np->rx_skb[i].skb) {
1816                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1817                                          (skb_end_pointer(np->rx_skb[i].skb) -
1818                                           np->rx_skb[i].skb->data),
1819                                          PCI_DMA_FROMDEVICE);
1820                         dev_kfree_skb(np->rx_skb[i].skb);
1821                         np->rx_skb[i].skb = NULL;
1822                 }
1823         }
1824 }
1825
1826 static void drain_ring(struct net_device *dev)
1827 {
1828         nv_drain_tx(dev);
1829         nv_drain_rx(dev);
1830 }
1831
1832 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1833 {
1834         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1835 }
1836
1837 /*
1838  * nv_start_xmit: dev->hard_start_xmit function
1839  * Called with netif_tx_lock held.
1840  */
1841 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1842 {
1843         struct fe_priv *np = netdev_priv(dev);
1844         u32 tx_flags = 0;
1845         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1846         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1847         unsigned int i;
1848         u32 offset = 0;
1849         u32 bcnt;
1850         u32 size = skb->len-skb->data_len;
1851         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1852         u32 empty_slots;
1853         struct ring_desc* put_tx;
1854         struct ring_desc* start_tx;
1855         struct ring_desc* prev_tx;
1856         struct nv_skb_map* prev_tx_ctx;
1857
1858         /* add fragments to entries count */
1859         for (i = 0; i < fragments; i++) {
1860                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1861                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1862         }
1863
1864         empty_slots = nv_get_empty_tx_slots(np);
1865         if (unlikely(empty_slots <= entries)) {
1866                 spin_lock_irq(&np->lock);
1867                 netif_stop_queue(dev);
1868                 np->tx_stop = 1;
1869                 spin_unlock_irq(&np->lock);
1870                 return NETDEV_TX_BUSY;
1871         }
1872
1873         start_tx = put_tx = np->put_tx.orig;
1874
1875         /* setup the header buffer */
1876         do {
1877                 prev_tx = put_tx;
1878                 prev_tx_ctx = np->put_tx_ctx;
1879                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1880                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1881                                                 PCI_DMA_TODEVICE);
1882                 np->put_tx_ctx->dma_len = bcnt;
1883                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1884                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1885
1886                 tx_flags = np->tx_flags;
1887                 offset += bcnt;
1888                 size -= bcnt;
1889                 if (unlikely(put_tx++ == np->last_tx.orig))
1890                         put_tx = np->first_tx.orig;
1891                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1892                         np->put_tx_ctx = np->first_tx_ctx;
1893         } while (size);
1894
1895         /* setup the fragments */
1896         for (i = 0; i < fragments; i++) {
1897                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1898                 u32 size = frag->size;
1899                 offset = 0;
1900
1901                 do {
1902                         prev_tx = put_tx;
1903                         prev_tx_ctx = np->put_tx_ctx;
1904                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1905                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1906                                                            PCI_DMA_TODEVICE);
1907                         np->put_tx_ctx->dma_len = bcnt;
1908                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1909                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1910
1911                         offset += bcnt;
1912                         size -= bcnt;
1913                         if (unlikely(put_tx++ == np->last_tx.orig))
1914                                 put_tx = np->first_tx.orig;
1915                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1916                                 np->put_tx_ctx = np->first_tx_ctx;
1917                 } while (size);
1918         }
1919
1920         /* set last fragment flag  */
1921         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1922
1923         /* save skb in this slot's context area */
1924         prev_tx_ctx->skb = skb;
1925
1926         if (skb_is_gso(skb))
1927                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1928         else
1929                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1930                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1931
1932         spin_lock_irq(&np->lock);
1933
1934         /* set tx flags */
1935         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1936         np->put_tx.orig = put_tx;
1937
1938         spin_unlock_irq(&np->lock);
1939
1940         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1941                 dev->name, entries, tx_flags_extra);
1942         {
1943                 int j;
1944                 for (j=0; j<64; j++) {
1945                         if ((j%16) == 0)
1946                                 dprintk("\n%03x:", j);
1947                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1948                 }
1949                 dprintk("\n");
1950         }
1951
1952         dev->trans_start = jiffies;
1953         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1954         return NETDEV_TX_OK;
1955 }
1956
1957 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1958 {
1959         struct fe_priv *np = netdev_priv(dev);
1960         u32 tx_flags = 0;
1961         u32 tx_flags_extra;
1962         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1963         unsigned int i;
1964         u32 offset = 0;
1965         u32 bcnt;
1966         u32 size = skb->len-skb->data_len;
1967         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1968         u32 empty_slots;
1969         struct ring_desc_ex* put_tx;
1970         struct ring_desc_ex* start_tx;
1971         struct ring_desc_ex* prev_tx;
1972         struct nv_skb_map* prev_tx_ctx;
1973         struct nv_skb_map* start_tx_ctx;
1974
1975         /* add fragments to entries count */
1976         for (i = 0; i < fragments; i++) {
1977                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1978                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1979         }
1980
1981         empty_slots = nv_get_empty_tx_slots(np);
1982         if (unlikely(empty_slots <= entries)) {
1983                 spin_lock_irq(&np->lock);
1984                 netif_stop_queue(dev);
1985                 np->tx_stop = 1;
1986                 spin_unlock_irq(&np->lock);
1987                 return NETDEV_TX_BUSY;
1988         }
1989
1990         start_tx = put_tx = np->put_tx.ex;
1991         start_tx_ctx = np->put_tx_ctx;
1992
1993         /* setup the header buffer */
1994         do {
1995                 prev_tx = put_tx;
1996                 prev_tx_ctx = np->put_tx_ctx;
1997                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1998                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1999                                                 PCI_DMA_TODEVICE);
2000                 np->put_tx_ctx->dma_len = bcnt;
2001                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2002                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2003                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2004
2005                 tx_flags = NV_TX2_VALID;
2006                 offset += bcnt;
2007                 size -= bcnt;
2008                 if (unlikely(put_tx++ == np->last_tx.ex))
2009                         put_tx = np->first_tx.ex;
2010                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2011                         np->put_tx_ctx = np->first_tx_ctx;
2012         } while (size);
2013
2014         /* setup the fragments */
2015         for (i = 0; i < fragments; i++) {
2016                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2017                 u32 size = frag->size;
2018                 offset = 0;
2019
2020                 do {
2021                         prev_tx = put_tx;
2022                         prev_tx_ctx = np->put_tx_ctx;
2023                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2024                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2025                                                            PCI_DMA_TODEVICE);
2026                         np->put_tx_ctx->dma_len = bcnt;
2027                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2028                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2029                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2030
2031                         offset += bcnt;
2032                         size -= bcnt;
2033                         if (unlikely(put_tx++ == np->last_tx.ex))
2034                                 put_tx = np->first_tx.ex;
2035                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2036                                 np->put_tx_ctx = np->first_tx_ctx;
2037                 } while (size);
2038         }
2039
2040         /* set last fragment flag  */
2041         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2042
2043         /* save skb in this slot's context area */
2044         prev_tx_ctx->skb = skb;
2045
2046         if (skb_is_gso(skb))
2047                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2048         else
2049                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2050                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2051
2052         /* vlan tag */
2053         if (likely(!np->vlangrp)) {
2054                 start_tx->txvlan = 0;
2055         } else {
2056                 if (vlan_tx_tag_present(skb))
2057                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2058                 else
2059                         start_tx->txvlan = 0;
2060         }
2061
2062         spin_lock_irq(&np->lock);
2063
2064         if (np->tx_limit) {
2065                 /* Limit the number of outstanding tx. Setup all fragments, but
2066                  * do not set the VALID bit on the first descriptor. Save a pointer
2067                  * to that descriptor and also for next skb_map element.
2068                  */
2069
2070                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2071                         if (!np->tx_change_owner)
2072                                 np->tx_change_owner = start_tx_ctx;
2073
2074                         /* remove VALID bit */
2075                         tx_flags &= ~NV_TX2_VALID;
2076                         start_tx_ctx->first_tx_desc = start_tx;
2077                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2078                         np->tx_end_flip = np->put_tx_ctx;
2079                 } else {
2080                         np->tx_pkts_in_progress++;
2081                 }
2082         }
2083
2084         /* set tx flags */
2085         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2086         np->put_tx.ex = put_tx;
2087
2088         spin_unlock_irq(&np->lock);
2089
2090         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2091                 dev->name, entries, tx_flags_extra);
2092         {
2093                 int j;
2094                 for (j=0; j<64; j++) {
2095                         if ((j%16) == 0)
2096                                 dprintk("\n%03x:", j);
2097                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2098                 }
2099                 dprintk("\n");
2100         }
2101
2102         dev->trans_start = jiffies;
2103         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2104         return NETDEV_TX_OK;
2105 }
2106
2107 static inline void nv_tx_flip_ownership(struct net_device *dev)
2108 {
2109         struct fe_priv *np = netdev_priv(dev);
2110
2111         np->tx_pkts_in_progress--;
2112         if (np->tx_change_owner) {
2113                 __le32 flaglen = le32_to_cpu(np->tx_change_owner->first_tx_desc->flaglen);
2114                 flaglen |= NV_TX2_VALID;
2115                 np->tx_change_owner->first_tx_desc->flaglen = cpu_to_le32(flaglen);
2116                 np->tx_pkts_in_progress++;
2117
2118                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2119                 if (np->tx_change_owner == np->tx_end_flip)
2120                         np->tx_change_owner = NULL;
2121
2122                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2123         }
2124 }
2125
2126 /*
2127  * nv_tx_done: check for completed packets, release the skbs.
2128  *
2129  * Caller must own np->lock.
2130  */
2131 static void nv_tx_done(struct net_device *dev)
2132 {
2133         struct fe_priv *np = netdev_priv(dev);
2134         u32 flags;
2135         struct ring_desc* orig_get_tx = np->get_tx.orig;
2136
2137         while ((np->get_tx.orig != np->put_tx.orig) &&
2138                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2139
2140                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2141                                         dev->name, flags);
2142
2143                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2144                                np->get_tx_ctx->dma_len,
2145                                PCI_DMA_TODEVICE);
2146                 np->get_tx_ctx->dma = 0;
2147
2148                 if (np->desc_ver == DESC_VER_1) {
2149                         if (flags & NV_TX_LASTPACKET) {
2150                                 if (flags & NV_TX_ERROR) {
2151                                         if (flags & NV_TX_UNDERFLOW)
2152                                                 dev->stats.tx_fifo_errors++;
2153                                         if (flags & NV_TX_CARRIERLOST)
2154                                                 dev->stats.tx_carrier_errors++;
2155                                         dev->stats.tx_errors++;
2156                                 } else {
2157                                         dev->stats.tx_packets++;
2158                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2159                                 }
2160                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2161                                 np->get_tx_ctx->skb = NULL;
2162                         }
2163                 } else {
2164                         if (flags & NV_TX2_LASTPACKET) {
2165                                 if (flags & NV_TX2_ERROR) {
2166                                         if (flags & NV_TX2_UNDERFLOW)
2167                                                 dev->stats.tx_fifo_errors++;
2168                                         if (flags & NV_TX2_CARRIERLOST)
2169                                                 dev->stats.tx_carrier_errors++;
2170                                         dev->stats.tx_errors++;
2171                                 } else {
2172                                         dev->stats.tx_packets++;
2173                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2174                                 }
2175                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2176                                 np->get_tx_ctx->skb = NULL;
2177                         }
2178                 }
2179                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2180                         np->get_tx.orig = np->first_tx.orig;
2181                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2182                         np->get_tx_ctx = np->first_tx_ctx;
2183         }
2184         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2185                 np->tx_stop = 0;
2186                 netif_wake_queue(dev);
2187         }
2188 }
2189
2190 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2191 {
2192         struct fe_priv *np = netdev_priv(dev);
2193         u32 flags;
2194         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2195
2196         while ((np->get_tx.ex != np->put_tx.ex) &&
2197                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2198                (limit-- > 0)) {
2199
2200                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2201                                         dev->name, flags);
2202
2203                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2204                                np->get_tx_ctx->dma_len,
2205                                PCI_DMA_TODEVICE);
2206                 np->get_tx_ctx->dma = 0;
2207
2208                 if (flags & NV_TX2_LASTPACKET) {
2209                         if (!(flags & NV_TX2_ERROR))
2210                                 dev->stats.tx_packets++;
2211                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2212                         np->get_tx_ctx->skb = NULL;
2213
2214                         if (np->tx_limit) {
2215                                 nv_tx_flip_ownership(dev);
2216                         }
2217                 }
2218                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2219                         np->get_tx.ex = np->first_tx.ex;
2220                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2221                         np->get_tx_ctx = np->first_tx_ctx;
2222         }
2223         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2224                 np->tx_stop = 0;
2225                 netif_wake_queue(dev);
2226         }
2227 }
2228
2229 /*
2230  * nv_tx_timeout: dev->tx_timeout function
2231  * Called with netif_tx_lock held.
2232  */
2233 static void nv_tx_timeout(struct net_device *dev)
2234 {
2235         struct fe_priv *np = netdev_priv(dev);
2236         u8 __iomem *base = get_hwbase(dev);
2237         u32 status;
2238
2239         if (np->msi_flags & NV_MSI_X_ENABLED)
2240                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2241         else
2242                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2243
2244         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2245
2246         {
2247                 int i;
2248
2249                 printk(KERN_INFO "%s: Ring at %lx\n",
2250                        dev->name, (unsigned long)np->ring_addr);
2251                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2252                 for (i=0;i<=np->register_size;i+= 32) {
2253                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2254                                         i,
2255                                         readl(base + i + 0), readl(base + i + 4),
2256                                         readl(base + i + 8), readl(base + i + 12),
2257                                         readl(base + i + 16), readl(base + i + 20),
2258                                         readl(base + i + 24), readl(base + i + 28));
2259                 }
2260                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2261                 for (i=0;i<np->tx_ring_size;i+= 4) {
2262                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2263                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2264                                        i,
2265                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2266                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2267                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2268                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2269                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2270                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2271                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2272                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2273                         } else {
2274                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2275                                        i,
2276                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2277                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2278                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2279                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2280                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2281                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2282                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2283                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2284                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2285                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2286                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2287                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2288                         }
2289                 }
2290         }
2291
2292         spin_lock_irq(&np->lock);
2293
2294         /* 1) stop tx engine */
2295         nv_stop_tx(dev);
2296
2297         /* 2) check that the packets were not sent already: */
2298         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2299                 nv_tx_done(dev);
2300         else
2301                 nv_tx_done_optimized(dev, np->tx_ring_size);
2302
2303         /* 3) if there are dead entries: clear everything */
2304         if (np->get_tx_ctx != np->put_tx_ctx) {
2305                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2306                 nv_drain_tx(dev);
2307                 nv_init_tx(dev);
2308                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2309         }
2310
2311         netif_wake_queue(dev);
2312
2313         /* 4) restart tx engine */
2314         nv_start_tx(dev);
2315         spin_unlock_irq(&np->lock);
2316 }
2317
2318 /*
2319  * Called when the nic notices a mismatch between the actual data len on the
2320  * wire and the len indicated in the 802 header
2321  */
2322 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2323 {
2324         int hdrlen;     /* length of the 802 header */
2325         int protolen;   /* length as stored in the proto field */
2326
2327         /* 1) calculate len according to header */
2328         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2329                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2330                 hdrlen = VLAN_HLEN;
2331         } else {
2332                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2333                 hdrlen = ETH_HLEN;
2334         }
2335         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2336                                 dev->name, datalen, protolen, hdrlen);
2337         if (protolen > ETH_DATA_LEN)
2338                 return datalen; /* Value in proto field not a len, no checks possible */
2339
2340         protolen += hdrlen;
2341         /* consistency checks: */
2342         if (datalen > ETH_ZLEN) {
2343                 if (datalen >= protolen) {
2344                         /* more data on wire than in 802 header, trim of
2345                          * additional data.
2346                          */
2347                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2348                                         dev->name, protolen);
2349                         return protolen;
2350                 } else {
2351                         /* less data on wire than mentioned in header.
2352                          * Discard the packet.
2353                          */
2354                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2355                                         dev->name);
2356                         return -1;
2357                 }
2358         } else {
2359                 /* short packet. Accept only if 802 values are also short */
2360                 if (protolen > ETH_ZLEN) {
2361                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2362                                         dev->name);
2363                         return -1;
2364                 }
2365                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2366                                 dev->name, datalen);
2367                 return datalen;
2368         }
2369 }
2370
2371 static int nv_rx_process(struct net_device *dev, int limit)
2372 {
2373         struct fe_priv *np = netdev_priv(dev);
2374         u32 flags;
2375         int rx_work = 0;
2376         struct sk_buff *skb;
2377         int len;
2378
2379         while((np->get_rx.orig != np->put_rx.orig) &&
2380               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2381                 (rx_work < limit)) {
2382
2383                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2384                                         dev->name, flags);
2385
2386                 /*
2387                  * the packet is for us - immediately tear down the pci mapping.
2388                  * TODO: check if a prefetch of the first cacheline improves
2389                  * the performance.
2390                  */
2391                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2392                                 np->get_rx_ctx->dma_len,
2393                                 PCI_DMA_FROMDEVICE);
2394                 skb = np->get_rx_ctx->skb;
2395                 np->get_rx_ctx->skb = NULL;
2396
2397                 {
2398                         int j;
2399                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2400                         for (j=0; j<64; j++) {
2401                                 if ((j%16) == 0)
2402                                         dprintk("\n%03x:", j);
2403                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2404                         }
2405                         dprintk("\n");
2406                 }
2407                 /* look at what we actually got: */
2408                 if (np->desc_ver == DESC_VER_1) {
2409                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2410                                 len = flags & LEN_MASK_V1;
2411                                 if (unlikely(flags & NV_RX_ERROR)) {
2412                                         if (flags & NV_RX_ERROR4) {
2413                                                 len = nv_getlen(dev, skb->data, len);
2414                                                 if (len < 0) {
2415                                                         dev->stats.rx_errors++;
2416                                                         dev_kfree_skb(skb);
2417                                                         goto next_pkt;
2418                                                 }
2419                                         }
2420                                         /* framing errors are soft errors */
2421                                         else if (flags & NV_RX_FRAMINGERR) {
2422                                                 if (flags & NV_RX_SUBSTRACT1) {
2423                                                         len--;
2424                                                 }
2425                                         }
2426                                         /* the rest are hard errors */
2427                                         else {
2428                                                 if (flags & NV_RX_MISSEDFRAME)
2429                                                         dev->stats.rx_missed_errors++;
2430                                                 if (flags & NV_RX_CRCERR)
2431                                                         dev->stats.rx_crc_errors++;
2432                                                 if (flags & NV_RX_OVERFLOW)
2433                                                         dev->stats.rx_over_errors++;
2434                                                 dev->stats.rx_errors++;
2435                                                 dev_kfree_skb(skb);
2436                                                 goto next_pkt;
2437                                         }
2438                                 }
2439                         } else {
2440                                 dev_kfree_skb(skb);
2441                                 goto next_pkt;
2442                         }
2443                 } else {
2444                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2445                                 len = flags & LEN_MASK_V2;
2446                                 if (unlikely(flags & NV_RX2_ERROR)) {
2447                                         if (flags & NV_RX2_ERROR4) {
2448                                                 len = nv_getlen(dev, skb->data, len);
2449                                                 if (len < 0) {
2450                                                         dev->stats.rx_errors++;
2451                                                         dev_kfree_skb(skb);
2452                                                         goto next_pkt;
2453                                                 }
2454                                         }
2455                                         /* framing errors are soft errors */
2456                                         else if (flags & NV_RX2_FRAMINGERR) {
2457                                                 if (flags & NV_RX2_SUBSTRACT1) {
2458                                                         len--;
2459                                                 }
2460                                         }
2461                                         /* the rest are hard errors */
2462                                         else {
2463                                                 if (flags & NV_RX2_CRCERR)
2464                                                         dev->stats.rx_crc_errors++;
2465                                                 if (flags & NV_RX2_OVERFLOW)
2466                                                         dev->stats.rx_over_errors++;
2467                                                 dev->stats.rx_errors++;
2468                                                 dev_kfree_skb(skb);
2469                                                 goto next_pkt;
2470                                         }
2471                                 }
2472                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2473                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2474                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2475                         } else {
2476                                 dev_kfree_skb(skb);
2477                                 goto next_pkt;
2478                         }
2479                 }
2480                 /* got a valid packet - forward it to the network core */
2481                 skb_put(skb, len);
2482                 skb->protocol = eth_type_trans(skb, dev);
2483                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2484                                         dev->name, len, skb->protocol);
2485 #ifdef CONFIG_FORCEDETH_NAPI
2486                 netif_receive_skb(skb);
2487 #else
2488                 netif_rx(skb);
2489 #endif
2490                 dev->last_rx = jiffies;
2491                 dev->stats.rx_packets++;
2492                 dev->stats.rx_bytes += len;
2493 next_pkt:
2494                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2495                         np->get_rx.orig = np->first_rx.orig;
2496                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2497                         np->get_rx_ctx = np->first_rx_ctx;
2498
2499                 rx_work++;
2500         }
2501
2502         return rx_work;
2503 }
2504
2505 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2506 {
2507         struct fe_priv *np = netdev_priv(dev);
2508         u32 flags;
2509         u32 vlanflags = 0;
2510         int rx_work = 0;
2511         struct sk_buff *skb;
2512         int len;
2513
2514         while((np->get_rx.ex != np->put_rx.ex) &&
2515               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2516               (rx_work < limit)) {
2517
2518                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2519                                         dev->name, flags);
2520
2521                 /*
2522                  * the packet is for us - immediately tear down the pci mapping.
2523                  * TODO: check if a prefetch of the first cacheline improves
2524                  * the performance.
2525                  */
2526                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2527                                 np->get_rx_ctx->dma_len,
2528                                 PCI_DMA_FROMDEVICE);
2529                 skb = np->get_rx_ctx->skb;
2530                 np->get_rx_ctx->skb = NULL;
2531
2532                 {
2533                         int j;
2534                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2535                         for (j=0; j<64; j++) {
2536                                 if ((j%16) == 0)
2537                                         dprintk("\n%03x:", j);
2538                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2539                         }
2540                         dprintk("\n");
2541                 }
2542                 /* look at what we actually got: */
2543                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2544                         len = flags & LEN_MASK_V2;
2545                         if (unlikely(flags & NV_RX2_ERROR)) {
2546                                 if (flags & NV_RX2_ERROR4) {
2547                                         len = nv_getlen(dev, skb->data, len);
2548                                         if (len < 0) {
2549                                                 dev_kfree_skb(skb);
2550                                                 goto next_pkt;
2551                                         }
2552                                 }
2553                                 /* framing errors are soft errors */
2554                                 else if (flags & NV_RX2_FRAMINGERR) {
2555                                         if (flags & NV_RX2_SUBSTRACT1) {
2556                                                 len--;
2557                                         }
2558                                 }
2559                                 /* the rest are hard errors */
2560                                 else {
2561                                         dev_kfree_skb(skb);
2562                                         goto next_pkt;
2563                                 }
2564                         }
2565
2566                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2567                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2568                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2569
2570                         /* got a valid packet - forward it to the network core */
2571                         skb_put(skb, len);
2572                         skb->protocol = eth_type_trans(skb, dev);
2573                         prefetch(skb->data);
2574
2575                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2576                                 dev->name, len, skb->protocol);
2577
2578                         if (likely(!np->vlangrp)) {
2579 #ifdef CONFIG_FORCEDETH_NAPI
2580                                 netif_receive_skb(skb);
2581 #else
2582                                 netif_rx(skb);
2583 #endif
2584                         } else {
2585                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2586                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2587 #ifdef CONFIG_FORCEDETH_NAPI
2588                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2589                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2590 #else
2591                                         vlan_hwaccel_rx(skb, np->vlangrp,
2592                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2593 #endif
2594                                 } else {
2595 #ifdef CONFIG_FORCEDETH_NAPI
2596                                         netif_receive_skb(skb);
2597 #else
2598                                         netif_rx(skb);
2599 #endif
2600                                 }
2601                         }
2602
2603                         dev->last_rx = jiffies;
2604                         dev->stats.rx_packets++;
2605                         dev->stats.rx_bytes += len;
2606                 } else {
2607                         dev_kfree_skb(skb);
2608                 }
2609 next_pkt:
2610                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2611                         np->get_rx.ex = np->first_rx.ex;
2612                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2613                         np->get_rx_ctx = np->first_rx_ctx;
2614
2615                 rx_work++;
2616         }
2617
2618         return rx_work;
2619 }
2620
2621 static void set_bufsize(struct net_device *dev)
2622 {
2623         struct fe_priv *np = netdev_priv(dev);
2624
2625         if (dev->mtu <= ETH_DATA_LEN)
2626                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2627         else
2628                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2629 }
2630
2631 /*
2632  * nv_change_mtu: dev->change_mtu function
2633  * Called with dev_base_lock held for read.
2634  */
2635 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2636 {
2637         struct fe_priv *np = netdev_priv(dev);
2638         int old_mtu;
2639
2640         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2641                 return -EINVAL;
2642
2643         old_mtu = dev->mtu;
2644         dev->mtu = new_mtu;
2645
2646         /* return early if the buffer sizes will not change */
2647         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2648                 return 0;
2649         if (old_mtu == new_mtu)
2650                 return 0;
2651
2652         /* synchronized against open : rtnl_lock() held by caller */
2653         if (netif_running(dev)) {
2654                 u8 __iomem *base = get_hwbase(dev);
2655                 /*
2656                  * It seems that the nic preloads valid ring entries into an
2657                  * internal buffer. The procedure for flushing everything is
2658                  * guessed, there is probably a simpler approach.
2659                  * Changing the MTU is a rare event, it shouldn't matter.
2660                  */
2661                 nv_disable_irq(dev);
2662                 netif_tx_lock_bh(dev);
2663                 spin_lock(&np->lock);
2664                 /* stop engines */
2665                 nv_stop_rx(dev);
2666                 nv_stop_tx(dev);
2667                 nv_txrx_reset(dev);
2668                 /* drain rx queue */
2669                 nv_drain_rx(dev);
2670                 nv_drain_tx(dev);
2671                 /* reinit driver view of the rx queue */
2672                 set_bufsize(dev);
2673                 if (nv_init_ring(dev)) {
2674                         if (!np->in_shutdown)
2675                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2676                 }
2677                 /* reinit nic view of the rx queue */
2678                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2679                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2680                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2681                         base + NvRegRingSizes);
2682                 pci_push(base);
2683                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2684                 pci_push(base);
2685
2686                 /* restart rx engine */
2687                 nv_start_rx(dev);
2688                 nv_start_tx(dev);
2689                 spin_unlock(&np->lock);
2690                 netif_tx_unlock_bh(dev);
2691                 nv_enable_irq(dev);
2692         }
2693         return 0;
2694 }
2695
2696 static void nv_copy_mac_to_hw(struct net_device *dev)
2697 {
2698         u8 __iomem *base = get_hwbase(dev);
2699         u32 mac[2];
2700
2701         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2702                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2703         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2704
2705         writel(mac[0], base + NvRegMacAddrA);
2706         writel(mac[1], base + NvRegMacAddrB);
2707 }
2708
2709 /*
2710  * nv_set_mac_address: dev->set_mac_address function
2711  * Called with rtnl_lock() held.
2712  */
2713 static int nv_set_mac_address(struct net_device *dev, void *addr)
2714 {
2715         struct fe_priv *np = netdev_priv(dev);
2716         struct sockaddr *macaddr = (struct sockaddr*)addr;
2717
2718         if (!is_valid_ether_addr(macaddr->sa_data))
2719                 return -EADDRNOTAVAIL;
2720
2721         /* synchronized against open : rtnl_lock() held by caller */
2722         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2723
2724         if (netif_running(dev)) {
2725                 netif_tx_lock_bh(dev);
2726                 spin_lock_irq(&np->lock);
2727
2728                 /* stop rx engine */
2729                 nv_stop_rx(dev);
2730
2731                 /* set mac address */
2732                 nv_copy_mac_to_hw(dev);
2733
2734                 /* restart rx engine */
2735                 nv_start_rx(dev);
2736                 spin_unlock_irq(&np->lock);
2737                 netif_tx_unlock_bh(dev);
2738         } else {
2739                 nv_copy_mac_to_hw(dev);
2740         }
2741         return 0;
2742 }
2743
2744 /*
2745  * nv_set_multicast: dev->set_multicast function
2746  * Called with netif_tx_lock held.
2747  */
2748 static void nv_set_multicast(struct net_device *dev)
2749 {
2750         struct fe_priv *np = netdev_priv(dev);
2751         u8 __iomem *base = get_hwbase(dev);
2752         u32 addr[2];
2753         u32 mask[2];
2754         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2755
2756         memset(addr, 0, sizeof(addr));
2757         memset(mask, 0, sizeof(mask));
2758
2759         if (dev->flags & IFF_PROMISC) {
2760                 pff |= NVREG_PFF_PROMISC;
2761         } else {
2762                 pff |= NVREG_PFF_MYADDR;
2763
2764                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2765                         u32 alwaysOff[2];
2766                         u32 alwaysOn[2];
2767
2768                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2769                         if (dev->flags & IFF_ALLMULTI) {
2770                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2771                         } else {
2772                                 struct dev_mc_list *walk;
2773
2774                                 walk = dev->mc_list;
2775                                 while (walk != NULL) {
2776                                         u32 a, b;
2777                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2778                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2779                                         alwaysOn[0] &= a;
2780                                         alwaysOff[0] &= ~a;
2781                                         alwaysOn[1] &= b;
2782                                         alwaysOff[1] &= ~b;
2783                                         walk = walk->next;
2784                                 }
2785                         }
2786                         addr[0] = alwaysOn[0];
2787                         addr[1] = alwaysOn[1];
2788                         mask[0] = alwaysOn[0] | alwaysOff[0];
2789                         mask[1] = alwaysOn[1] | alwaysOff[1];
2790                 } else {
2791                         mask[0] = NVREG_MCASTMASKA_NONE;
2792                         mask[1] = NVREG_MCASTMASKB_NONE;
2793                 }
2794         }
2795         addr[0] |= NVREG_MCASTADDRA_FORCE;
2796         pff |= NVREG_PFF_ALWAYS;
2797         spin_lock_irq(&np->lock);
2798         nv_stop_rx(dev);
2799         writel(addr[0], base + NvRegMulticastAddrA);
2800         writel(addr[1], base + NvRegMulticastAddrB);
2801         writel(mask[0], base + NvRegMulticastMaskA);
2802         writel(mask[1], base + NvRegMulticastMaskB);
2803         writel(pff, base + NvRegPacketFilterFlags);
2804         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2805                 dev->name);
2806         nv_start_rx(dev);
2807         spin_unlock_irq(&np->lock);
2808 }
2809
2810 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2811 {
2812         struct fe_priv *np = netdev_priv(dev);
2813         u8 __iomem *base = get_hwbase(dev);
2814
2815         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2816
2817         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2818                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2819                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2820                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2821                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2822                 } else {
2823                         writel(pff, base + NvRegPacketFilterFlags);
2824                 }
2825         }
2826         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2827                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2828                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2829                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
2830                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
2831                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
2832                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
2833                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
2834                         writel(pause_enable,  base + NvRegTxPauseFrame);
2835                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2836                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2837                 } else {
2838                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2839                         writel(regmisc, base + NvRegMisc1);
2840                 }
2841         }
2842 }
2843
2844 /**
2845  * nv_update_linkspeed: Setup the MAC according to the link partner
2846  * @dev: Network device to be configured
2847  *
2848  * The function queries the PHY and checks if there is a link partner.
2849  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2850  * set to 10 MBit HD.
2851  *
2852  * The function returns 0 if there is no link partner and 1 if there is
2853  * a good link partner.
2854  */
2855 static int nv_update_linkspeed(struct net_device *dev)
2856 {
2857         struct fe_priv *np = netdev_priv(dev);
2858         u8 __iomem *base = get_hwbase(dev);
2859         int adv = 0;
2860         int lpa = 0;
2861         int adv_lpa, adv_pause, lpa_pause;
2862         int newls = np->linkspeed;
2863         int newdup = np->duplex;
2864         int mii_status;
2865         int retval = 0;
2866         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2867         u32 txrxFlags = 0;
2868         u32 phy_exp;
2869
2870         /* BMSR_LSTATUS is latched, read it twice:
2871          * we want the current value.
2872          */
2873         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2874         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2875
2876         if (!(mii_status & BMSR_LSTATUS)) {
2877                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2878                                 dev->name);
2879                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2880                 newdup = 0;
2881                 retval = 0;
2882                 goto set_speed;
2883         }
2884
2885         if (np->autoneg == 0) {
2886                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2887                                 dev->name, np->fixed_mode);
2888                 if (np->fixed_mode & LPA_100FULL) {
2889                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2890                         newdup = 1;
2891                 } else if (np->fixed_mode & LPA_100HALF) {
2892                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2893                         newdup = 0;
2894                 } else if (np->fixed_mode & LPA_10FULL) {
2895                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2896                         newdup = 1;
2897                 } else {
2898                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2899                         newdup = 0;
2900                 }
2901                 retval = 1;
2902                 goto set_speed;
2903         }
2904         /* check auto negotiation is complete */
2905         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2906                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2907                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2908                 newdup = 0;
2909                 retval = 0;
2910                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2911                 goto set_speed;
2912         }
2913
2914         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2915         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2916         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2917                                 dev->name, adv, lpa);
2918
2919         retval = 1;
2920         if (np->gigabit == PHY_GIGABIT) {
2921                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2922                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2923
2924                 if ((control_1000 & ADVERTISE_1000FULL) &&
2925                         (status_1000 & LPA_1000FULL)) {
2926                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2927                                 dev->name);
2928                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2929                         newdup = 1;
2930                         goto set_speed;
2931                 }
2932         }
2933
2934         /* FIXME: handle parallel detection properly */
2935         adv_lpa = lpa & adv;
2936         if (adv_lpa & LPA_100FULL) {
2937                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2938                 newdup = 1;
2939         } else if (adv_lpa & LPA_100HALF) {
2940                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2941                 newdup = 0;
2942         } else if (adv_lpa & LPA_10FULL) {
2943                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2944                 newdup = 1;
2945         } else if (adv_lpa & LPA_10HALF) {
2946                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2947                 newdup = 0;
2948         } else {
2949                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2950                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2951                 newdup = 0;
2952         }
2953
2954 set_speed:
2955         if (np->duplex == newdup && np->linkspeed == newls)
2956                 return retval;
2957
2958         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2959                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2960
2961         np->duplex = newdup;
2962         np->linkspeed = newls;
2963
2964         /* The transmitter and receiver must be restarted for safe update */
2965         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
2966                 txrxFlags |= NV_RESTART_TX;
2967                 nv_stop_tx(dev);
2968         }
2969         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
2970                 txrxFlags |= NV_RESTART_RX;
2971                 nv_stop_rx(dev);
2972         }
2973
2974         if (np->gigabit == PHY_GIGABIT) {
2975                 phyreg = readl(base + NvRegRandomSeed);
2976                 phyreg &= ~(0x3FF00);
2977                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2978                         phyreg |= NVREG_RNDSEED_FORCE3;
2979                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2980                         phyreg |= NVREG_RNDSEED_FORCE2;
2981                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2982                         phyreg |= NVREG_RNDSEED_FORCE;
2983                 writel(phyreg, base + NvRegRandomSeed);
2984         }
2985
2986         phyreg = readl(base + NvRegPhyInterface);
2987         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2988         if (np->duplex == 0)
2989                 phyreg |= PHY_HALF;
2990         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2991                 phyreg |= PHY_100;
2992         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2993                 phyreg |= PHY_1000;
2994         writel(phyreg, base + NvRegPhyInterface);
2995
2996         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
2997         if (phyreg & PHY_RGMII) {
2998                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
2999                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3000                 } else {
3001                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3002                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3003                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3004                                 else
3005                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3006                         } else {
3007                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3008                         }
3009                 }
3010         } else {
3011                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3012                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3013                 else
3014                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3015         }
3016         writel(txreg, base + NvRegTxDeferral);
3017
3018         if (np->desc_ver == DESC_VER_1) {
3019                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3020         } else {
3021                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3022                         txreg = NVREG_TX_WM_DESC2_3_1000;
3023                 else
3024                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3025         }
3026         writel(txreg, base + NvRegTxWatermark);
3027
3028         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3029                 base + NvRegMisc1);
3030         pci_push(base);
3031         writel(np->linkspeed, base + NvRegLinkSpeed);
3032         pci_push(base);
3033
3034         pause_flags = 0;
3035         /* setup pause frame */
3036         if (np->duplex != 0) {
3037                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3038                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3039                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3040
3041                         switch (adv_pause) {
3042                         case ADVERTISE_PAUSE_CAP:
3043                                 if (lpa_pause & LPA_PAUSE_CAP) {
3044                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3045                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3046                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3047                                 }
3048                                 break;
3049                         case ADVERTISE_PAUSE_ASYM:
3050                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3051                                 {
3052                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3053                                 }
3054                                 break;
3055                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3056                                 if (lpa_pause & LPA_PAUSE_CAP)
3057                                 {
3058                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3059                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3060                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3061                                 }
3062                                 if (lpa_pause == LPA_PAUSE_ASYM)
3063                                 {
3064                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3065                                 }
3066                                 break;
3067                         }
3068                 } else {
3069                         pause_flags = np->pause_flags;
3070                 }
3071         }
3072         nv_update_pause(dev, pause_flags);
3073
3074         if (txrxFlags & NV_RESTART_TX)
3075                 nv_start_tx(dev);
3076         if (txrxFlags & NV_RESTART_RX)
3077                 nv_start_rx(dev);
3078
3079         return retval;
3080 }
3081
3082 static void nv_linkchange(struct net_device *dev)
3083 {
3084         if (nv_update_linkspeed(dev)) {
3085                 if (!netif_carrier_ok(dev)) {
3086                         netif_carrier_on(dev);
3087                         printk(KERN_INFO "%s: link up.\n", dev->name);
3088                         nv_start_rx(dev);
3089                 }
3090         } else {
3091                 if (netif_carrier_ok(dev)) {
3092                         netif_carrier_off(dev);
3093                         printk(KERN_INFO "%s: link down.\n", dev->name);
3094                         nv_stop_rx(dev);
3095                 }
3096         }
3097 }
3098
3099 static void nv_link_irq(struct net_device *dev)
3100 {
3101         u8 __iomem *base = get_hwbase(dev);
3102         u32 miistat;
3103
3104         miistat = readl(base + NvRegMIIStatus);
3105         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3106         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3107
3108         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3109                 nv_linkchange(dev);
3110         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3111 }
3112
3113 static irqreturn_t nv_nic_irq(int foo, void *data)
3114 {
3115         struct net_device *dev = (struct net_device *) data;
3116         struct fe_priv *np = netdev_priv(dev);
3117         u8 __iomem *base = get_hwbase(dev);
3118         u32 events;
3119         int i;
3120
3121         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3122
3123         for (i=0; ; i++) {
3124                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3125                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3126                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3127                 } else {
3128                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3129                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3130                 }
3131                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3132                 if (!(events & np->irqmask))
3133                         break;
3134
3135                 spin_lock(&np->lock);
3136                 nv_tx_done(dev);
3137                 spin_unlock(&np->lock);
3138
3139 #ifdef CONFIG_FORCEDETH_NAPI
3140                 if (events & NVREG_IRQ_RX_ALL) {
3141                         netif_rx_schedule(dev, &np->napi);
3142
3143                         /* Disable furthur receive irq's */
3144                         spin_lock(&np->lock);
3145                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3146
3147                         if (np->msi_flags & NV_MSI_X_ENABLED)
3148                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3149                         else
3150                                 writel(np->irqmask, base + NvRegIrqMask);
3151                         spin_unlock(&np->lock);
3152                 }
3153 #else
3154                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3155                         if (unlikely(nv_alloc_rx(dev))) {
3156                                 spin_lock(&np->lock);
3157                                 if (!np->in_shutdown)
3158                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3159                                 spin_unlock(&np->lock);
3160                         }
3161                 }
3162 #endif
3163                 if (unlikely(events & NVREG_IRQ_LINK)) {
3164                         spin_lock(&np->lock);
3165                         nv_link_irq(dev);
3166                         spin_unlock(&np->lock);
3167                 }
3168                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3169                         spin_lock(&np->lock);
3170                         nv_linkchange(dev);
3171                         spin_unlock(&np->lock);
3172                         np->link_timeout = jiffies + LINK_TIMEOUT;
3173                 }
3174                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3175                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3176                                                 dev->name, events);
3177                 }
3178                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3179                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3180                                                 dev->name, events);
3181                 }
3182                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3183                         spin_lock(&np->lock);
3184                         /* disable interrupts on the nic */
3185                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3186                                 writel(0, base + NvRegIrqMask);
3187                         else
3188                                 writel(np->irqmask, base + NvRegIrqMask);
3189                         pci_push(base);
3190
3191                         if (!np->in_shutdown) {
3192                                 np->nic_poll_irq = np->irqmask;
3193                                 np->recover_error = 1;
3194                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3195                         }
3196                         spin_unlock(&np->lock);
3197                         break;
3198                 }
3199                 if (unlikely(i > max_interrupt_work)) {
3200                         spin_lock(&np->lock);
3201                         /* disable interrupts on the nic */
3202                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3203                                 writel(0, base + NvRegIrqMask);
3204                         else
3205                                 writel(np->irqmask, base + NvRegIrqMask);
3206                         pci_push(base);
3207
3208                         if (!np->in_shutdown) {
3209                                 np->nic_poll_irq = np->irqmask;
3210                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3211                         }
3212                         spin_unlock(&np->lock);
3213                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3214                         break;
3215                 }
3216
3217         }
3218         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3219
3220         return IRQ_RETVAL(i);
3221 }
3222
3223 /**
3224  * All _optimized functions are used to help increase performance
3225  * (reduce CPU and increase throughput). They use descripter version 3,
3226  * compiler directives, and reduce memory accesses.
3227  */
3228 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3229 {
3230         struct net_device *dev = (struct net_device *) data;
3231         struct fe_priv *np = netdev_priv(dev);
3232         u8 __iomem *base = get_hwbase(dev);
3233         u32 events;
3234         int i;
3235
3236         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3237
3238         for (i=0; ; i++) {
3239                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3240                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3241                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3242                 } else {
3243                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3244                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3245                 }
3246                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3247                 if (!(events & np->irqmask))
3248                         break;
3249
3250                 spin_lock(&np->lock);
3251                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3252                 spin_unlock(&np->lock);
3253
3254 #ifdef CONFIG_FORCEDETH_NAPI
3255                 if (events & NVREG_IRQ_RX_ALL) {
3256                         netif_rx_schedule(dev, &np->napi);
3257
3258                         /* Disable furthur receive irq's */
3259                         spin_lock(&np->lock);
3260                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3261
3262                         if (np->msi_flags & NV_MSI_X_ENABLED)
3263                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3264                         else
3265                                 writel(np->irqmask, base + NvRegIrqMask);
3266                         spin_unlock(&np->lock);
3267                 }
3268 #else
3269                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3270                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3271                                 spin_lock(&np->lock);
3272                                 if (!np->in_shutdown)
3273                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3274                                 spin_unlock(&np->lock);
3275                         }
3276                 }
3277 #endif
3278                 if (unlikely(events & NVREG_IRQ_LINK)) {
3279                         spin_lock(&np->lock);
3280                         nv_link_irq(dev);
3281                         spin_unlock(&np->lock);
3282                 }
3283                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3284                         spin_lock(&np->lock);
3285                         nv_linkchange(dev);
3286                         spin_unlock(&np->lock);
3287                         np->link_timeout = jiffies + LINK_TIMEOUT;
3288                 }
3289                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3290                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3291                                                 dev->name, events);
3292                 }
3293                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3294                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3295                                                 dev->name, events);
3296                 }
3297                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3298                         spin_lock(&np->lock);
3299                         /* disable interrupts on the nic */
3300                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3301                                 writel(0, base + NvRegIrqMask);
3302                         else
3303                                 writel(np->irqmask, base + NvRegIrqMask);
3304                         pci_push(base);
3305
3306                         if (!np->in_shutdown) {
3307                                 np->nic_poll_irq = np->irqmask;
3308                                 np->recover_error = 1;
3309                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3310                         }
3311                         spin_unlock(&np->lock);
3312                         break;
3313                 }
3314
3315                 if (unlikely(i > max_interrupt_work)) {
3316                         spin_lock(&np->lock);
3317                         /* disable interrupts on the nic */
3318                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3319                                 writel(0, base + NvRegIrqMask);
3320                         else
3321                                 writel(np->irqmask, base + NvRegIrqMask);
3322                         pci_push(base);
3323
3324                         if (!np->in_shutdown) {
3325                                 np->nic_poll_irq = np->irqmask;
3326                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3327                         }
3328                         spin_unlock(&np->lock);
3329                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3330                         break;
3331                 }
3332
3333         }
3334         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3335
3336         return IRQ_RETVAL(i);
3337 }
3338
3339 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3340 {
3341         struct net_device *dev = (struct net_device *) data;
3342         struct fe_priv *np = netdev_priv(dev);
3343         u8 __iomem *base = get_hwbase(dev);
3344         u32 events;
3345         int i;
3346         unsigned long flags;
3347
3348         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3349
3350         for (i=0; ; i++) {
3351                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3352                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3353                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3354                 if (!(events & np->irqmask))
3355                         break;
3356
3357                 spin_lock_irqsave(&np->lock, flags);
3358                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3359                 spin_unlock_irqrestore(&np->lock, flags);
3360
3361                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3362                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3363                                                 dev->name, events);
3364                 }
3365                 if (unlikely(i > max_interrupt_work)) {
3366                         spin_lock_irqsave(&np->lock, flags);
3367                         /* disable interrupts on the nic */
3368                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3369                         pci_push(base);
3370
3371                         if (!np->in_shutdown) {
3372                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3373                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3374                         }
3375                         spin_unlock_irqrestore(&np->lock, flags);
3376                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3377                         break;
3378                 }
3379
3380         }
3381         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3382
3383         return IRQ_RETVAL(i);
3384 }
3385
3386 #ifdef CONFIG_FORCEDETH_NAPI
3387 static int nv_napi_poll(struct napi_struct *napi, int budget)
3388 {
3389         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3390         struct net_device *dev = np->dev;
3391         u8 __iomem *base = get_hwbase(dev);
3392         unsigned long flags;
3393         int pkts, retcode;
3394
3395         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3396                 pkts = nv_rx_process(dev, budget);
3397                 retcode = nv_alloc_rx(dev);
3398         } else {
3399                 pkts = nv_rx_process_optimized(dev, budget);
3400                 retcode = nv_alloc_rx_optimized(dev);
3401         }
3402
3403         if (retcode) {
3404                 spin_lock_irqsave(&np->lock, flags);
3405                 if (!np->in_shutdown)
3406                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3407                 spin_unlock_irqrestore(&np->lock, flags);
3408         }
3409
3410         if (pkts < budget) {
3411                 /* re-enable receive interrupts */
3412                 spin_lock_irqsave(&np->lock, flags);
3413
3414                 __netif_rx_complete(dev, napi);
3415
3416                 np->irqmask |= NVREG_IRQ_RX_ALL;
3417                 if (np->msi_flags & NV_MSI_X_ENABLED)
3418                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3419                 else
3420                         writel(np->irqmask, base + NvRegIrqMask);
3421
3422                 spin_unlock_irqrestore(&np->lock, flags);
3423         }
3424         return pkts;
3425 }
3426 #endif
3427
3428 #ifdef CONFIG_FORCEDETH_NAPI
3429 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3430 {
3431         struct net_device *dev = (struct net_device *) data;
3432         struct fe_priv *np = netdev_priv(dev);
3433         u8 __iomem *base = get_hwbase(dev);
3434         u32 events;
3435
3436         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3437         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3438
3439         if (events) {
3440                 netif_rx_schedule(dev, &np->napi);
3441                 /* disable receive interrupts on the nic */
3442                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3443                 pci_push(base);
3444         }
3445         return IRQ_HANDLED;
3446 }
3447 #else
3448 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3449 {
3450         struct net_device *dev = (struct net_device *) data;
3451         struct fe_priv *np = netdev_priv(dev);
3452         u8 __iomem *base = get_hwbase(dev);
3453         u32 events;
3454         int i;
3455         unsigned long flags;
3456
3457         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3458
3459         for (i=0; ; i++) {
3460                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3461                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3462                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3463                 if (!(events & np->irqmask))
3464                         break;
3465
3466                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3467                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3468                                 spin_lock_irqsave(&np->lock, flags);
3469                                 if (!np->in_shutdown)
3470                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3471                                 spin_unlock_irqrestore(&np->lock, flags);
3472                         }
3473                 }
3474
3475                 if (unlikely(i > max_interrupt_work)) {
3476                         spin_lock_irqsave(&np->lock, flags);
3477                         /* disable interrupts on the nic */
3478                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3479                         pci_push(base);
3480
3481                         if (!np->in_shutdown) {
3482                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3483                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3484                         }
3485                         spin_unlock_irqrestore(&np->lock, flags);
3486                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3487                         break;
3488                 }
3489         }
3490         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3491
3492         return IRQ_RETVAL(i);
3493 }
3494 #endif
3495
3496 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3497 {
3498         struct net_device *dev = (struct net_device *) data;
3499         struct fe_priv *np = netdev_priv(dev);
3500         u8 __iomem *base = get_hwbase(dev);
3501         u32 events;
3502         int i;
3503         unsigned long flags;
3504
3505         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3506
3507         for (i=0; ; i++) {
3508                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3509                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3510                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3511                 if (!(events & np->irqmask))
3512                         break;
3513
3514                 /* check tx in case we reached max loop limit in tx isr */
3515                 spin_lock_irqsave(&np->lock, flags);
3516                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3517                 spin_unlock_irqrestore(&np->lock, flags);
3518
3519                 if (events & NVREG_IRQ_LINK) {
3520                         spin_lock_irqsave(&np->lock, flags);
3521                         nv_link_irq(dev);
3522                         spin_unlock_irqrestore(&np->lock, flags);
3523                 }
3524                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3525                         spin_lock_irqsave(&np->lock, flags);
3526                         nv_linkchange(dev);
3527                         spin_unlock_irqrestore(&np->lock, flags);
3528                         np->link_timeout = jiffies + LINK_TIMEOUT;
3529                 }
3530                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3531                         spin_lock_irq(&np->lock);
3532                         /* disable interrupts on the nic */
3533                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3534                         pci_push(base);
3535
3536                         if (!np->in_shutdown) {
3537                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3538                                 np->recover_error = 1;
3539                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3540                         }
3541                         spin_unlock_irq(&np->lock);
3542                         break;
3543                 }
3544                 if (events & (NVREG_IRQ_UNKNOWN)) {
3545                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3546                                                 dev->name, events);
3547                 }
3548                 if (unlikely(i > max_interrupt_work)) {
3549                         spin_lock_irqsave(&np->lock, flags);
3550                         /* disable interrupts on the nic */
3551                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3552                         pci_push(base);
3553
3554                         if (!np->in_shutdown) {
3555                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3556                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3557                         }
3558                         spin_unlock_irqrestore(&np->lock, flags);
3559                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3560                         break;
3561                 }
3562
3563         }
3564         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3565
3566         return IRQ_RETVAL(i);
3567 }
3568
3569 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3570 {
3571         struct net_device *dev = (struct net_device *) data;
3572         struct fe_priv *np = netdev_priv(dev);
3573         u8 __iomem *base = get_hwbase(dev);
3574         u32 events;
3575
3576         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3577
3578         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3579                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3580                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3581         } else {
3582                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3583                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3584         }
3585         pci_push(base);
3586         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3587         if (!(events & NVREG_IRQ_TIMER))
3588                 return IRQ_RETVAL(0);
3589
3590         spin_lock(&np->lock);
3591         np->intr_test = 1;
3592         spin_unlock(&np->lock);
3593
3594         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3595
3596         return IRQ_RETVAL(1);
3597 }
3598
3599 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3600 {
3601         u8 __iomem *base = get_hwbase(dev);
3602         int i;
3603         u32 msixmap = 0;
3604
3605         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3606          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3607          * the remaining 8 interrupts.
3608          */
3609         for (i = 0; i < 8; i++) {
3610                 if ((irqmask >> i) & 0x1) {
3611                         msixmap |= vector << (i << 2);
3612                 }
3613         }
3614         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3615
3616         msixmap = 0;
3617         for (i = 0; i < 8; i++) {
3618                 if ((irqmask >> (i + 8)) & 0x1) {
3619                         msixmap |= vector << (i << 2);
3620                 }
3621         }
3622         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3623 }
3624
3625 static int nv_request_irq(struct net_device *dev, int intr_test)
3626 {
3627         struct fe_priv *np = get_nvpriv(dev);
3628         u8 __iomem *base = get_hwbase(dev);
3629         int ret = 1;
3630         int i;
3631         irqreturn_t (*handler)(int foo, void *data);
3632
3633         if (intr_test) {
3634                 handler = nv_nic_irq_test;
3635         } else {
3636                 if (np->desc_ver == DESC_VER_3)
3637                         handler = nv_nic_irq_optimized;
3638                 else
3639                         handler = nv_nic_irq;
3640         }
3641
3642         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3643                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3644                         np->msi_x_entry[i].entry = i;
3645                 }
3646                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3647                         np->msi_flags |= NV_MSI_X_ENABLED;
3648                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3649                                 /* Request irq for rx handling */
3650                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3651                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3652                                         pci_disable_msix(np->pci_dev);
3653                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3654                                         goto out_err;
3655                                 }
3656                                 /* Request irq for tx handling */
3657                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3658                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3659                                         pci_disable_msix(np->pci_dev);
3660                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3661                                         goto out_free_rx;
3662                                 }
3663                                 /* Request irq for link and timer handling */
3664                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3665                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3666                                         pci_disable_msix(np->pci_dev);
3667                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3668                                         goto out_free_tx;
3669                                 }
3670                                 /* map interrupts to their respective vector */
3671                                 writel(0, base + NvRegMSIXMap0);
3672                                 writel(0, base + NvRegMSIXMap1);
3673                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3674                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3675                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3676                         } else {
3677                                 /* Request irq for all interrupts */
3678                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3679                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3680                                         pci_disable_msix(np->pci_dev);
3681                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3682                                         goto out_err;
3683                                 }
3684
3685                                 /* map interrupts to vector 0 */
3686                                 writel(0, base + NvRegMSIXMap0);
3687                                 writel(0, base + NvRegMSIXMap1);
3688                         }
3689                 }
3690         }
3691         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3692                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3693                         np->msi_flags |= NV_MSI_ENABLED;
3694                         dev->irq = np->pci_dev->irq;
3695                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3696                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3697                                 pci_disable_msi(np->pci_dev);
3698                                 np->msi_flags &= ~NV_MSI_ENABLED;
3699                                 dev->irq = np->pci_dev->irq;
3700                                 goto out_err;
3701                         }
3702
3703                         /* map interrupts to vector 0 */
3704                         writel(0, base + NvRegMSIMap0);
3705                         writel(0, base + NvRegMSIMap1);
3706                         /* enable msi vector 0 */
3707                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3708                 }
3709         }
3710         if (ret != 0) {
3711                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3712                         goto out_err;
3713
3714         }
3715
3716         return 0;
3717 out_free_tx:
3718         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3719 out_free_rx:
3720         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3721 out_err:
3722         return 1;
3723 }
3724
3725 static void nv_free_irq(struct net_device *dev)
3726 {
3727         struct fe_priv *np = get_nvpriv(dev);
3728         int i;
3729
3730         if (np->msi_flags & NV_MSI_X_ENABLED) {
3731                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3732                         free_irq(np->msi_x_entry[i].vector, dev);
3733                 }
3734                 pci_disable_msix(np->pci_dev);
3735                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3736         } else {
3737                 free_irq(np->pci_dev->irq, dev);
3738                 if (np->msi_flags & NV_MSI_ENABLED) {
3739                         pci_disable_msi(np->pci_dev);
3740                         np->msi_flags &= ~NV_MSI_ENABLED;
3741                 }
3742         }
3743 }
3744
3745 static void nv_do_nic_poll(unsigned long data)
3746 {
3747         struct net_device *dev = (struct net_device *) data;
3748         struct fe_priv *np = netdev_priv(dev);
3749         u8 __iomem *base = get_hwbase(dev);
3750         u32 mask = 0;
3751
3752         /*
3753          * First disable irq(s) and then
3754          * reenable interrupts on the nic, we have to do this before calling
3755          * nv_nic_irq because that may decide to do otherwise
3756          */
3757
3758         if (!using_multi_irqs(dev)) {
3759                 if (np->msi_flags & NV_MSI_X_ENABLED)
3760                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3761                 else
3762                         disable_irq_lockdep(np->pci_dev->irq);
3763                 mask = np->irqmask;
3764         } else {
3765                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3766                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3767                         mask |= NVREG_IRQ_RX_ALL;
3768                 }
3769                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3770                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3771                         mask |= NVREG_IRQ_TX_ALL;
3772                 }
3773                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3774                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3775                         mask |= NVREG_IRQ_OTHER;
3776                 }
3777         }
3778         np->nic_poll_irq = 0;
3779
3780         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3781
3782         if (np->recover_error) {
3783                 np->recover_error = 0;
3784                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3785                 if (netif_running(dev)) {
3786                         netif_tx_lock_bh(dev);
3787                         spin_lock(&np->lock);
3788                         /* stop engines */
3789                         nv_stop_rx(dev);
3790                         nv_stop_tx(dev);
3791                         nv_txrx_reset(dev);
3792                         /* drain rx queue */
3793                         nv_drain_rx(dev);
3794                         nv_drain_tx(dev);
3795                         /* reinit driver view of the rx queue */
3796                         set_bufsize(dev);
3797                         if (nv_init_ring(dev)) {
3798                                 if (!np->in_shutdown)
3799                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3800                         }
3801                         /* reinit nic view of the rx queue */
3802                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3803                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3804                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3805                                 base + NvRegRingSizes);
3806                         pci_push(base);
3807                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3808                         pci_push(base);
3809
3810                         /* restart rx engine */
3811                         nv_start_rx(dev);
3812                         nv_start_tx(dev);
3813                         spin_unlock(&np->lock);
3814                         netif_tx_unlock_bh(dev);
3815                 }
3816         }
3817
3818
3819         writel(mask, base + NvRegIrqMask);
3820         pci_push(base);
3821
3822         if (!using_multi_irqs(dev)) {
3823                 if (np->desc_ver == DESC_VER_3)
3824                         nv_nic_irq_optimized(0, dev);
3825                 else
3826                         nv_nic_irq(0, dev);
3827                 if (np->msi_flags & NV_MSI_X_ENABLED)
3828                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3829                 else
3830                         enable_irq_lockdep(np->pci_dev->irq);
3831         } else {
3832                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3833                         nv_nic_irq_rx(0, dev);
3834                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3835                 }
3836                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3837                         nv_nic_irq_tx(0, dev);
3838                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3839                 }
3840                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3841                         nv_nic_irq_other(0, dev);
3842                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3843                 }
3844         }
3845 }
3846
3847 #ifdef CONFIG_NET_POLL_CONTROLLER
3848 static void nv_poll_controller(struct net_device *dev)
3849 {
3850         nv_do_nic_poll((unsigned long) dev);
3851 }
3852 #endif
3853
3854 static void nv_do_stats_poll(unsigned long data)
3855 {
3856         struct net_device *dev = (struct net_device *) data;
3857         struct fe_priv *np = netdev_priv(dev);
3858
3859         nv_get_hw_stats(dev);
3860
3861         if (!np->in_shutdown)
3862                 mod_timer(&np->stats_poll,
3863                         round_jiffies(jiffies + STATS_INTERVAL));
3864 }
3865
3866 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3867 {
3868         struct fe_priv *np = netdev_priv(dev);
3869         strcpy(info->driver, DRV_NAME);
3870         strcpy(info->version, FORCEDETH_VERSION);
3871         strcpy(info->bus_info, pci_name(np->pci_dev));
3872 }
3873
3874 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3875 {
3876         struct fe_priv *np = netdev_priv(dev);
3877         wolinfo->supported = WAKE_MAGIC;
3878
3879         spin_lock_irq(&np->lock);
3880         if (np->wolenabled)
3881                 wolinfo->wolopts = WAKE_MAGIC;
3882         spin_unlock_irq(&np->lock);
3883 }
3884
3885 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3886 {
3887         struct fe_priv *np = netdev_priv(dev);
3888         u8 __iomem *base = get_hwbase(dev);
3889         u32 flags = 0;
3890
3891         if (wolinfo->wolopts == 0) {
3892                 np->wolenabled = 0;
3893         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3894                 np->wolenabled = 1;
3895                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3896         }
3897         if (netif_running(dev)) {
3898                 spin_lock_irq(&np->lock);
3899                 writel(flags, base + NvRegWakeUpFlags);
3900                 spin_unlock_irq(&np->lock);
3901         }
3902         return 0;
3903 }
3904
3905 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3906 {
3907         struct fe_priv *np = netdev_priv(dev);
3908         int adv;
3909
3910         spin_lock_irq(&np->lock);
3911         ecmd->port = PORT_MII;
3912         if (!netif_running(dev)) {
3913                 /* We do not track link speed / duplex setting if the
3914                  * interface is disabled. Force a link check */
3915                 if (nv_update_linkspeed(dev)) {
3916                         if (!netif_carrier_ok(dev))
3917                                 netif_carrier_on(dev);
3918                 } else {
3919                         if (netif_carrier_ok(dev))
3920                                 netif_carrier_off(dev);
3921                 }
3922         }
3923
3924         if (netif_carrier_ok(dev)) {
3925                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3926                 case NVREG_LINKSPEED_10:
3927                         ecmd->speed = SPEED_10;
3928                         break;
3929                 case NVREG_LINKSPEED_100:
3930                         ecmd->speed = SPEED_100;
3931                         break;
3932                 case NVREG_LINKSPEED_1000:
3933                         ecmd->speed = SPEED_1000;
3934                         break;
3935                 }
3936                 ecmd->duplex = DUPLEX_HALF;
3937                 if (np->duplex)
3938                         ecmd->duplex = DUPLEX_FULL;
3939         } else {
3940                 ecmd->speed = -1;
3941                 ecmd->duplex = -1;
3942         }
3943
3944         ecmd->autoneg = np->autoneg;
3945
3946         ecmd->advertising = ADVERTISED_MII;
3947         if (np->autoneg) {
3948                 ecmd->advertising |= ADVERTISED_Autoneg;
3949                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3950                 if (adv & ADVERTISE_10HALF)
3951                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3952                 if (adv & ADVERTISE_10FULL)
3953                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3954                 if (adv & ADVERTISE_100HALF)
3955                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3956                 if (adv & ADVERTISE_100FULL)
3957                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3958                 if (np->gigabit == PHY_GIGABIT) {
3959                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3960                         if (adv & ADVERTISE_1000FULL)
3961                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3962                 }
3963         }
3964         ecmd->supported = (SUPPORTED_Autoneg |
3965                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3966                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3967                 SUPPORTED_MII);
3968         if (np->gigabit == PHY_GIGABIT)
3969                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3970
3971         ecmd->phy_address = np->phyaddr;
3972         ecmd->transceiver = XCVR_EXTERNAL;
3973
3974         /* ignore maxtxpkt, maxrxpkt for now */
3975         spin_unlock_irq(&np->lock);
3976         return 0;
3977 }
3978
3979 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3980 {
3981         struct fe_priv *np = netdev_priv(dev);
3982
3983         if (ecmd->port != PORT_MII)
3984                 return -EINVAL;
3985         if (ecmd->transceiver != XCVR_EXTERNAL)
3986                 return -EINVAL;
3987         if (ecmd->phy_address != np->phyaddr) {
3988                 /* TODO: support switching between multiple phys. Should be
3989                  * trivial, but not enabled due to lack of test hardware. */
3990                 return -EINVAL;
3991         }
3992         if (ecmd->autoneg == AUTONEG_ENABLE) {
3993                 u32 mask;
3994
3995                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3996                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3997                 if (np->gigabit == PHY_GIGABIT)
3998                         mask |= ADVERTISED_1000baseT_Full;
3999
4000                 if ((ecmd->advertising & mask) == 0)
4001                         return -EINVAL;
4002
4003         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4004                 /* Note: autonegotiation disable, speed 1000 intentionally
4005                  * forbidden - noone should need that. */
4006
4007                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4008                         return -EINVAL;
4009                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4010                         return -EINVAL;
4011         } else {
4012                 return -EINVAL;
4013         }
4014
4015         netif_carrier_off(dev);
4016         if (netif_running(dev)) {
4017                 nv_disable_irq(dev);
4018                 netif_tx_lock_bh(dev);
4019                 spin_lock(&np->lock);
4020                 /* stop engines */
4021                 nv_stop_rx(dev);
4022                 nv_stop_tx(dev);
4023                 spin_unlock(&np->lock);
4024                 netif_tx_unlock_bh(dev);
4025         }
4026
4027         if (ecmd->autoneg == AUTONEG_ENABLE) {
4028                 int adv, bmcr;
4029
4030                 np->autoneg = 1;
4031
4032                 /* advertise only what has been requested */
4033                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4034                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4035                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4036                         adv |= ADVERTISE_10HALF;
4037                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4038                         adv |= ADVERTISE_10FULL;
4039                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4040                         adv |= ADVERTISE_100HALF;
4041                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4042                         adv |= ADVERTISE_100FULL;
4043                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4044                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4045                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4046                         adv |=  ADVERTISE_PAUSE_ASYM;
4047                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4048
4049                 if (np->gigabit == PHY_GIGABIT) {
4050                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4051                         adv &= ~ADVERTISE_1000FULL;
4052                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4053                                 adv |= ADVERTISE_1000FULL;
4054                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4055                 }
4056
4057                 if (netif_running(dev))
4058                         printk(KERN_INFO "%s: link down.\n", dev->name);
4059                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4060                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4061                         bmcr |= BMCR_ANENABLE;
4062                         /* reset the phy in order for settings to stick,
4063                          * and cause autoneg to start */
4064                         if (phy_reset(dev, bmcr)) {
4065                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4066                                 return -EINVAL;
4067                         }
4068                 } else {
4069                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4070                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4071                 }
4072         } else {
4073                 int adv, bmcr;
4074
4075                 np->autoneg = 0;
4076
4077                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4078                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4079                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4080                         adv |= ADVERTISE_10HALF;
4081                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4082                         adv |= ADVERTISE_10FULL;
4083                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4084                         adv |= ADVERTISE_100HALF;
4085                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4086                         adv |= ADVERTISE_100FULL;
4087                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4088                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4089                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4090                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4091                 }
4092                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4093                         adv |=  ADVERTISE_PAUSE_ASYM;
4094                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4095                 }
4096                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4097                 np->fixed_mode = adv;
4098
4099                 if (np->gigabit == PHY_GIGABIT) {
4100                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4101                         adv &= ~ADVERTISE_1000FULL;
4102                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4103                 }
4104
4105                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4106                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4107                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4108                         bmcr |= BMCR_FULLDPLX;
4109                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4110                         bmcr |= BMCR_SPEED100;
4111                 if (np->phy_oui == PHY_OUI_MARVELL) {
4112                         /* reset the phy in order for forced mode settings to stick */
4113                         if (phy_reset(dev, bmcr)) {
4114                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4115                                 return -EINVAL;
4116                         }
4117                 } else {
4118                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4119                         if (netif_running(dev)) {
4120                                 /* Wait a bit and then reconfigure the nic. */
4121                                 udelay(10);
4122                                 nv_linkchange(dev);
4123                         }
4124                 }
4125         }
4126
4127         if (netif_running(dev)) {
4128                 nv_start_rx(dev);
4129                 nv_start_tx(dev);
4130                 nv_enable_irq(dev);
4131         }
4132
4133         return 0;
4134 }
4135
4136 #define FORCEDETH_REGS_VER      1
4137
4138 static int nv_get_regs_len(struct net_device *dev)
4139 {
4140         struct fe_priv *np = netdev_priv(dev);
4141         return np->register_size;
4142 }
4143
4144 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4145 {
4146         struct fe_priv *np = netdev_priv(dev);
4147         u8 __iomem *base = get_hwbase(dev);
4148         u32 *rbuf = buf;
4149         int i;
4150
4151         regs->version = FORCEDETH_REGS_VER;
4152         spin_lock_irq(&np->lock);
4153         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4154                 rbuf[i] = readl(base + i*sizeof(u32));
4155         spin_unlock_irq(&np->lock);
4156 }
4157
4158 static int nv_nway_reset(struct net_device *dev)
4159 {
4160         struct fe_priv *np = netdev_priv(dev);
4161         int ret;
4162
4163         if (np->autoneg) {
4164                 int bmcr;
4165
4166                 netif_carrier_off(dev);
4167                 if (netif_running(dev)) {
4168                         nv_disable_irq(dev);
4169                         netif_tx_lock_bh(dev);
4170                         spin_lock(&np->lock);
4171                         /* stop engines */
4172                         nv_stop_rx(dev);
4173                         nv_stop_tx(dev);
4174                         spin_unlock(&np->lock);
4175                         netif_tx_unlock_bh(dev);
4176                         printk(KERN_INFO "%s: link down.\n", dev->name);
4177                 }
4178
4179                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4180                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4181                         bmcr |= BMCR_ANENABLE;
4182                         /* reset the phy in order for settings to stick*/
4183                         if (phy_reset(dev, bmcr)) {
4184                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4185                                 return -EINVAL;
4186                         }
4187                 } else {
4188                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4189                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4190                 }
4191
4192                 if (netif_running(dev)) {
4193                         nv_start_rx(dev);
4194                         nv_start_tx(dev);
4195                         nv_enable_irq(dev);
4196                 }
4197                 ret = 0;
4198         } else {
4199                 ret = -EINVAL;
4200         }
4201
4202         return ret;
4203 }
4204
4205 static int nv_set_tso(struct net_device *dev, u32 value)
4206 {
4207         struct fe_priv *np = netdev_priv(dev);
4208
4209         if ((np->driver_data & DEV_HAS_CHECKSUM))
4210                 return ethtool_op_set_tso(dev, value);
4211         else
4212                 return -EOPNOTSUPP;
4213 }
4214
4215 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4216 {
4217         struct fe_priv *np = netdev_priv(dev);
4218
4219         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4220         ring->rx_mini_max_pending = 0;
4221         ring->rx_jumbo_max_pending = 0;
4222         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4223
4224         ring->rx_pending = np->rx_ring_size;
4225         ring->rx_mini_pending = 0;
4226         ring->rx_jumbo_pending = 0;
4227         ring->tx_pending = np->tx_ring_size;
4228 }
4229
4230 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4231 {
4232         struct fe_priv *np = netdev_priv(dev);
4233         u8 __iomem *base = get_hwbase(dev);
4234         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4235         dma_addr_t ring_addr;
4236
4237         if (ring->rx_pending < RX_RING_MIN ||
4238             ring->tx_pending < TX_RING_MIN ||
4239             ring->rx_mini_pending != 0 ||
4240             ring->rx_jumbo_pending != 0 ||
4241             (np->desc_ver == DESC_VER_1 &&
4242              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4243               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4244             (np->desc_ver != DESC_VER_1 &&
4245              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4246               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4247                 return -EINVAL;
4248         }
4249
4250         /* allocate new rings */
4251         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4252                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4253                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4254                                             &ring_addr);
4255         } else {
4256                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4257                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4258                                             &ring_addr);
4259         }
4260         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4261         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4262         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4263                 /* fall back to old rings */
4264                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4265                         if (rxtx_ring)
4266                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4267                                                     rxtx_ring, ring_addr);
4268                 } else {
4269                         if (rxtx_ring)
4270                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4271                                                     rxtx_ring, ring_addr);
4272                 }
4273                 if (rx_skbuff)
4274                         kfree(rx_skbuff);
4275                 if (tx_skbuff)
4276                         kfree(tx_skbuff);
4277                 goto exit;
4278         }
4279
4280         if (netif_running(dev)) {
4281                 nv_disable_irq(dev);
4282                 netif_tx_lock_bh(dev);
4283                 spin_lock(&np->lock);
4284                 /* stop engines */
4285                 nv_stop_rx(dev);
4286                 nv_stop_tx(dev);
4287                 nv_txrx_reset(dev);
4288                 /* drain queues */
4289                 nv_drain_rx(dev);
4290                 nv_drain_tx(dev);
4291                 /* delete queues */
4292                 free_rings(dev);
4293         }
4294
4295         /* set new values */
4296         np->rx_ring_size = ring->rx_pending;
4297         np->tx_ring_size = ring->tx_pending;
4298         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4299                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4300                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4301         } else {
4302                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4303                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4304         }
4305         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4306         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4307         np->ring_addr = ring_addr;
4308
4309         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4310         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4311
4312         if (netif_running(dev)) {
4313                 /* reinit driver view of the queues */
4314                 set_bufsize(dev);
4315                 if (nv_init_ring(dev)) {
4316                         if (!np->in_shutdown)
4317                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4318                 }
4319
4320                 /* reinit nic view of the queues */
4321                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4322                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4323                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4324                         base + NvRegRingSizes);
4325                 pci_push(base);
4326                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4327                 pci_push(base);
4328
4329                 /* restart engines */
4330                 nv_start_rx(dev);
4331                 nv_start_tx(dev);
4332                 spin_unlock(&np->lock);
4333                 netif_tx_unlock_bh(dev);
4334                 nv_enable_irq(dev);
4335         }
4336         return 0;
4337 exit:
4338         return -ENOMEM;
4339 }
4340
4341 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4342 {
4343         struct fe_priv *np = netdev_priv(dev);
4344
4345         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4346         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4347         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4348 }
4349
4350 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4351 {
4352         struct fe_priv *np = netdev_priv(dev);
4353         int adv, bmcr;
4354
4355         if ((!np->autoneg && np->duplex == 0) ||
4356             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4357                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4358                        dev->name);
4359                 return -EINVAL;
4360         }
4361         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4362                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4363                 return -EINVAL;
4364         }
4365
4366         netif_carrier_off(dev);
4367         if (netif_running(dev)) {
4368                 nv_disable_irq(dev);
4369                 netif_tx_lock_bh(dev);
4370                 spin_lock(&np->lock);
4371                 /* stop engines */
4372                 nv_stop_rx(dev);
4373                 nv_stop_tx(dev);
4374                 spin_unlock(&np->lock);
4375                 netif_tx_unlock_bh(dev);
4376         }
4377
4378         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4379         if (pause->rx_pause)
4380                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4381         if (pause->tx_pause)
4382                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4383
4384         if (np->autoneg && pause->autoneg) {
4385                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4386
4387                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4388                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4389                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4390                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4391                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4392                         adv |=  ADVERTISE_PAUSE_ASYM;
4393                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4394
4395                 if (netif_running(dev))
4396                         printk(KERN_INFO "%s: link down.\n", dev->name);
4397                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4398                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4399                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4400         } else {
4401                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4402                 if (pause->rx_pause)
4403                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4404                 if (pause->tx_pause)
4405                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4406
4407                 if (!netif_running(dev))
4408                         nv_update_linkspeed(dev);
4409                 else
4410                         nv_update_pause(dev, np->pause_flags);
4411         }
4412
4413         if (netif_running(dev)) {
4414                 nv_start_rx(dev);
4415                 nv_start_tx(dev);
4416                 nv_enable_irq(dev);
4417         }
4418         return 0;
4419 }
4420
4421 static u32 nv_get_rx_csum(struct net_device *dev)
4422 {
4423         struct fe_priv *np = netdev_priv(dev);
4424         return (np->rx_csum) != 0;
4425 }
4426
4427 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4428 {
4429         struct fe_priv *np = netdev_priv(dev);
4430         u8 __iomem *base = get_hwbase(dev);
4431         int retcode = 0;
4432
4433         if (np->driver_data & DEV_HAS_CHECKSUM) {
4434                 if (data) {
4435                         np->rx_csum = 1;
4436                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4437                 } else {
4438                         np->rx_csum = 0;
4439                         /* vlan is dependent on rx checksum offload */
4440                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4441                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4442                 }
4443                 if (netif_running(dev)) {
4444                         spin_lock_irq(&np->lock);
4445                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4446                         spin_unlock_irq(&np->lock);
4447                 }
4448         } else {
4449                 return -EINVAL;
4450         }
4451
4452         return retcode;
4453 }
4454
4455 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4456 {
4457         struct fe_priv *np = netdev_priv(dev);
4458
4459         if (np->driver_data & DEV_HAS_CHECKSUM)
4460                 return ethtool_op_set_tx_hw_csum(dev, data);
4461         else
4462                 return -EOPNOTSUPP;
4463 }
4464
4465 static int nv_set_sg(struct net_device *dev, u32 data)
4466 {
4467         struct fe_priv *np = netdev_priv(dev);
4468
4469         if (np->driver_data & DEV_HAS_CHECKSUM)
4470                 return ethtool_op_set_sg(dev, data);
4471         else
4472                 return -EOPNOTSUPP;
4473 }
4474
4475 static int nv_get_sset_count(struct net_device *dev, int sset)
4476 {
4477         struct fe_priv *np = netdev_priv(dev);
4478
4479         switch (sset) {
4480         case ETH_SS_TEST:
4481                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4482                         return NV_TEST_COUNT_EXTENDED;
4483                 else
4484                         return NV_TEST_COUNT_BASE;
4485         case ETH_SS_STATS:
4486                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4487                         return NV_DEV_STATISTICS_V1_COUNT;
4488                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4489                         return NV_DEV_STATISTICS_V2_COUNT;
4490                 else
4491                         return 0;
4492         default:
4493                 return -EOPNOTSUPP;
4494         }
4495 }
4496
4497 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4498 {
4499         struct fe_priv *np = netdev_priv(dev);
4500
4501         /* update stats */
4502         nv_do_stats_poll((unsigned long)dev);
4503
4504         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4505 }
4506
4507 static int nv_link_test(struct net_device *dev)
4508 {
4509         struct fe_priv *np = netdev_priv(dev);
4510         int mii_status;
4511
4512         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4513         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4514
4515         /* check phy link status */
4516         if (!(mii_status & BMSR_LSTATUS))
4517                 return 0;
4518         else
4519                 return 1;
4520 }
4521
4522 static int nv_register_test(struct net_device *dev)
4523 {
4524         u8 __iomem *base = get_hwbase(dev);
4525         int i = 0;
4526         u32 orig_read, new_read;
4527
4528         do {
4529                 orig_read = readl(base + nv_registers_test[i].reg);
4530
4531                 /* xor with mask to toggle bits */
4532                 orig_read ^= nv_registers_test[i].mask;
4533
4534                 writel(orig_read, base + nv_registers_test[i].reg);
4535
4536                 new_read = readl(base + nv_registers_test[i].reg);
4537
4538                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4539                         return 0;
4540
4541                 /* restore original value */
4542                 orig_read ^= nv_registers_test[i].mask;
4543                 writel(orig_read, base + nv_registers_test[i].reg);
4544
4545         } while (nv_registers_test[++i].reg != 0);
4546
4547         return 1;
4548 }
4549
4550 static int nv_interrupt_test(struct net_device *dev)
4551 {
4552         struct fe_priv *np = netdev_priv(dev);
4553         u8 __iomem *base = get_hwbase(dev);
4554         int ret = 1;
4555         int testcnt;
4556         u32 save_msi_flags, save_poll_interval = 0;
4557
4558         if (netif_running(dev)) {
4559                 /* free current irq */
4560                 nv_free_irq(dev);
4561                 save_poll_interval = readl(base+NvRegPollingInterval);
4562         }
4563
4564         /* flag to test interrupt handler */
4565         np->intr_test = 0;
4566
4567         /* setup test irq */
4568         save_msi_flags = np->msi_flags;
4569         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4570         np->msi_flags |= 0x001; /* setup 1 vector */
4571         if (nv_request_irq(dev, 1))
4572                 return 0;
4573
4574         /* setup timer interrupt */
4575         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4576         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4577
4578         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4579
4580         /* wait for at least one interrupt */
4581         msleep(100);
4582
4583         spin_lock_irq(&np->lock);
4584
4585         /* flag should be set within ISR */
4586         testcnt = np->intr_test;
4587         if (!testcnt)
4588                 ret = 2;
4589
4590         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4591         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4592                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4593         else
4594                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4595
4596         spin_unlock_irq(&np->lock);
4597
4598         nv_free_irq(dev);
4599
4600         np->msi_flags = save_msi_flags;
4601
4602         if (netif_running(dev)) {
4603                 writel(save_poll_interval, base + NvRegPollingInterval);
4604                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4605                 /* restore original irq */
4606                 if (nv_request_irq(dev, 0))
4607                         return 0;
4608         }
4609
4610         return ret;
4611 }
4612
4613 static int nv_loopback_test(struct net_device *dev)
4614 {
4615         struct fe_priv *np = netdev_priv(dev);
4616         u8 __iomem *base = get_hwbase(dev);
4617         struct sk_buff *tx_skb, *rx_skb;
4618         dma_addr_t test_dma_addr;
4619         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4620         u32 flags;
4621         int len, i, pkt_len;
4622         u8 *pkt_data;
4623         u32 filter_flags = 0;
4624         u32 misc1_flags = 0;
4625         int ret = 1;
4626
4627         if (netif_running(dev)) {
4628                 nv_disable_irq(dev);
4629                 filter_flags = readl(base + NvRegPacketFilterFlags);
4630                 misc1_flags = readl(base + NvRegMisc1);
4631         } else {
4632                 nv_txrx_reset(dev);
4633         }
4634
4635         /* reinit driver view of the rx queue */
4636         set_bufsize(dev);
4637         nv_init_ring(dev);
4638
4639         /* setup hardware for loopback */
4640         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4641         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4642
4643         /* reinit nic view of the rx queue */
4644         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4645         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4646         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4647                 base + NvRegRingSizes);
4648         pci_push(base);
4649
4650         /* restart rx engine */
4651         nv_start_rx(dev);
4652         nv_start_tx(dev);
4653
4654         /* setup packet for tx */
4655         pkt_len = ETH_DATA_LEN;
4656         tx_skb = dev_alloc_skb(pkt_len);
4657         if (!tx_skb) {
4658                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4659                          " of %s\n", dev->name);
4660                 ret = 0;
4661                 goto out;
4662         }
4663         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4664                                        skb_tailroom(tx_skb),
4665                                        PCI_DMA_FROMDEVICE);
4666         pkt_data = skb_put(tx_skb, pkt_len);
4667         for (i = 0; i < pkt_len; i++)
4668                 pkt_data[i] = (u8)(i & 0xff);
4669
4670         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4671                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4672                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4673         } else {
4674                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4675                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4676                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4677         }
4678         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4679         pci_push(get_hwbase(dev));
4680
4681         msleep(500);
4682
4683         /* check for rx of the packet */
4684         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4685                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4686                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4687
4688         } else {
4689                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4690                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4691         }
4692
4693         if (flags & NV_RX_AVAIL) {
4694                 ret = 0;
4695         } else if (np->desc_ver == DESC_VER_1) {
4696                 if (flags & NV_RX_ERROR)
4697                         ret = 0;
4698         } else {
4699                 if (flags & NV_RX2_ERROR) {
4700                         ret = 0;
4701                 }
4702         }
4703
4704         if (ret) {
4705                 if (len != pkt_len) {
4706                         ret = 0;
4707                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4708                                 dev->name, len, pkt_len);
4709                 } else {
4710                         rx_skb = np->rx_skb[0].skb;
4711                         for (i = 0; i < pkt_len; i++) {
4712                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4713                                         ret = 0;
4714                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4715                                                 dev->name, i);
4716                                         break;
4717                                 }
4718                         }
4719                 }
4720         } else {
4721                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4722         }
4723
4724         pci_unmap_page(np->pci_dev, test_dma_addr,
4725                        (skb_end_pointer(tx_skb) - tx_skb->data),
4726                        PCI_DMA_TODEVICE);
4727         dev_kfree_skb_any(tx_skb);
4728  out:
4729         /* stop engines */
4730         nv_stop_rx(dev);
4731         nv_stop_tx(dev);
4732         nv_txrx_reset(dev);
4733         /* drain rx queue */
4734         nv_drain_rx(dev);
4735         nv_drain_tx(dev);
4736
4737         if (netif_running(dev)) {
4738                 writel(misc1_flags, base + NvRegMisc1);
4739                 writel(filter_flags, base + NvRegPacketFilterFlags);
4740                 nv_enable_irq(dev);
4741         }
4742
4743         return ret;
4744 }
4745
4746 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4747 {
4748         struct fe_priv *np = netdev_priv(dev);
4749         u8 __iomem *base = get_hwbase(dev);
4750         int result;
4751         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4752
4753         if (!nv_link_test(dev)) {
4754                 test->flags |= ETH_TEST_FL_FAILED;
4755                 buffer[0] = 1;
4756         }
4757
4758         if (test->flags & ETH_TEST_FL_OFFLINE) {
4759                 if (netif_running(dev)) {
4760                         netif_stop_queue(dev);
4761 #ifdef CONFIG_FORCEDETH_NAPI
4762                         napi_disable(&np->napi);
4763 #endif
4764                         netif_tx_lock_bh(dev);
4765                         spin_lock_irq(&np->lock);
4766                         nv_disable_hw_interrupts(dev, np->irqmask);
4767                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4768                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4769                         } else {
4770                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4771                         }
4772                         /* stop engines */
4773                         nv_stop_rx(dev);
4774                         nv_stop_tx(dev);
4775                         nv_txrx_reset(dev);
4776                         /* drain rx queue */
4777                         nv_drain_rx(dev);
4778                         nv_drain_tx(dev);
4779                         spin_unlock_irq(&np->lock);
4780                         netif_tx_unlock_bh(dev);
4781                 }
4782
4783                 if (!nv_register_test(dev)) {
4784                         test->flags |= ETH_TEST_FL_FAILED;
4785                         buffer[1] = 1;
4786                 }
4787
4788                 result = nv_interrupt_test(dev);
4789                 if (result != 1) {
4790                         test->flags |= ETH_TEST_FL_FAILED;
4791                         buffer[2] = 1;
4792                 }
4793                 if (result == 0) {
4794                         /* bail out */
4795                         return;
4796                 }
4797
4798                 if (!nv_loopback_test(dev)) {
4799                         test->flags |= ETH_TEST_FL_FAILED;
4800                         buffer[3] = 1;
4801                 }
4802
4803                 if (netif_running(dev)) {
4804                         /* reinit driver view of the rx queue */
4805                         set_bufsize(dev);
4806                         if (nv_init_ring(dev)) {
4807                                 if (!np->in_shutdown)
4808                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4809                         }
4810                         /* reinit nic view of the rx queue */
4811                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4812                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4813                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4814                                 base + NvRegRingSizes);
4815                         pci_push(base);
4816                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4817                         pci_push(base);
4818                         /* restart rx engine */
4819                         nv_start_rx(dev);
4820                         nv_start_tx(dev);
4821                         netif_start_queue(dev);
4822 #ifdef CONFIG_FORCEDETH_NAPI
4823                         napi_enable(&np->napi);
4824 #endif
4825                         nv_enable_hw_interrupts(dev, np->irqmask);
4826                 }
4827         }
4828 }
4829
4830 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4831 {
4832         switch (stringset) {
4833         case ETH_SS_STATS:
4834                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4835                 break;
4836         case ETH_SS_TEST:
4837                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4838                 break;
4839         }
4840 }
4841
4842 static const struct ethtool_ops ops = {
4843         .get_drvinfo = nv_get_drvinfo,
4844         .get_link = ethtool_op_get_link,
4845         .get_wol = nv_get_wol,
4846         .set_wol = nv_set_wol,
4847         .get_settings = nv_get_settings,
4848         .set_settings = nv_set_settings,
4849         .get_regs_len = nv_get_regs_len,
4850         .get_regs = nv_get_regs,
4851         .nway_reset = nv_nway_reset,
4852         .set_tso = nv_set_tso,
4853         .get_ringparam = nv_get_ringparam,
4854         .set_ringparam = nv_set_ringparam,
4855         .get_pauseparam = nv_get_pauseparam,
4856         .set_pauseparam = nv_set_pauseparam,
4857         .get_rx_csum = nv_get_rx_csum,
4858         .set_rx_csum = nv_set_rx_csum,
4859         .set_tx_csum = nv_set_tx_csum,
4860         .set_sg = nv_set_sg,
4861         .get_strings = nv_get_strings,
4862         .get_ethtool_stats = nv_get_ethtool_stats,
4863         .get_sset_count = nv_get_sset_count,
4864         .self_test = nv_self_test,
4865 };
4866
4867 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4868 {
4869         struct fe_priv *np = get_nvpriv(dev);
4870
4871         spin_lock_irq(&np->lock);
4872
4873         /* save vlan group */
4874         np->vlangrp = grp;
4875
4876         if (grp) {
4877                 /* enable vlan on MAC */
4878                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4879         } else {
4880                 /* disable vlan on MAC */
4881                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4882                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4883         }
4884
4885         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4886
4887         spin_unlock_irq(&np->lock);
4888 }
4889
4890 /* The mgmt unit and driver use a semaphore to access the phy during init */
4891 static int nv_mgmt_acquire_sema(struct net_device *dev)
4892 {
4893         u8 __iomem *base = get_hwbase(dev);
4894         int i;
4895         u32 tx_ctrl, mgmt_sema;
4896
4897         for (i = 0; i < 10; i++) {
4898                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4899                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4900                         break;
4901                 msleep(500);
4902         }
4903
4904         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4905                 return 0;
4906
4907         for (i = 0; i < 2; i++) {
4908                 tx_ctrl = readl(base + NvRegTransmitterControl);
4909                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4910                 writel(tx_ctrl, base + NvRegTransmitterControl);
4911
4912                 /* verify that semaphore was acquired */
4913                 tx_ctrl = readl(base + NvRegTransmitterControl);
4914                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4915                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4916                         return 1;
4917                 else
4918                         udelay(50);
4919         }
4920
4921         return 0;
4922 }
4923
4924 static int nv_open(struct net_device *dev)
4925 {
4926         struct fe_priv *np = netdev_priv(dev);
4927         u8 __iomem *base = get_hwbase(dev);
4928         int ret = 1;
4929         int oom, i;
4930
4931         dprintk(KERN_DEBUG "nv_open: begin\n");
4932
4933         /* erase previous misconfiguration */
4934         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4935                 nv_mac_reset(dev);
4936         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4937         writel(0, base + NvRegMulticastAddrB);
4938         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4939         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4940         writel(0, base + NvRegPacketFilterFlags);
4941
4942         writel(0, base + NvRegTransmitterControl);
4943         writel(0, base + NvRegReceiverControl);
4944
4945         writel(0, base + NvRegAdapterControl);
4946
4947         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4948                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4949
4950         /* initialize descriptor rings */
4951         set_bufsize(dev);
4952         oom = nv_init_ring(dev);
4953
4954         writel(0, base + NvRegLinkSpeed);
4955         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4956         nv_txrx_reset(dev);
4957         writel(0, base + NvRegUnknownSetupReg6);
4958
4959         np->in_shutdown = 0;
4960
4961         /* give hw rings */
4962         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4963         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4964                 base + NvRegRingSizes);
4965
4966         writel(np->linkspeed, base + NvRegLinkSpeed);
4967         if (np->desc_ver == DESC_VER_1)
4968                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4969         else
4970                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4971         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4972         writel(np->vlanctl_bits, base + NvRegVlanControl);
4973         pci_push(base);
4974         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4975         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4976                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4977                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4978
4979         writel(0, base + NvRegMIIMask);
4980         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4981         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4982
4983         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4984         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4985         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4986         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4987
4988         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4989         get_random_bytes(&i, sizeof(i));
4990         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4991         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4992         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4993         if (poll_interval == -1) {
4994                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4995                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4996                 else
4997                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4998         }
4999         else
5000                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5001         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5002         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5003                         base + NvRegAdapterControl);
5004         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5005         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5006         if (np->wolenabled)
5007                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5008
5009         i = readl(base + NvRegPowerState);
5010         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5011                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5012
5013         pci_push(base);
5014         udelay(10);
5015         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5016
5017         nv_disable_hw_interrupts(dev, np->irqmask);
5018         pci_push(base);
5019         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5020         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5021         pci_push(base);
5022
5023         if (nv_request_irq(dev, 0)) {
5024                 goto out_drain;
5025         }
5026
5027         /* ask for interrupts */
5028         nv_enable_hw_interrupts(dev, np->irqmask);
5029
5030         spin_lock_irq(&np->lock);
5031         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5032         writel(0, base + NvRegMulticastAddrB);
5033         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5034         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5035         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5036         /* One manual link speed update: Interrupts are enabled, future link
5037          * speed changes cause interrupts and are handled by nv_link_irq().
5038          */
5039         {
5040                 u32 miistat;
5041                 miistat = readl(base + NvRegMIIStatus);
5042                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5043                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5044         }
5045         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5046          * to init hw */
5047         np->linkspeed = 0;
5048         ret = nv_update_linkspeed(dev);
5049         nv_start_rx(dev);
5050         nv_start_tx(dev);
5051         netif_start_queue(dev);
5052 #ifdef CONFIG_FORCEDETH_NAPI
5053         napi_enable(&np->napi);
5054 #endif
5055
5056         if (ret) {
5057                 netif_carrier_on(dev);
5058         } else {
5059                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5060                 netif_carrier_off(dev);
5061         }
5062         if (oom)
5063                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5064
5065         /* start statistics timer */
5066         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
5067                 mod_timer(&np->stats_poll,
5068                         round_jiffies(jiffies + STATS_INTERVAL));
5069
5070         spin_unlock_irq(&np->lock);
5071
5072         return 0;
5073 out_drain:
5074         drain_ring(dev);
5075         return ret;
5076 }
5077
5078 static int nv_close(struct net_device *dev)
5079 {
5080         struct fe_priv *np = netdev_priv(dev);
5081         u8 __iomem *base;
5082
5083         spin_lock_irq(&np->lock);
5084         np->in_shutdown = 1;
5085         spin_unlock_irq(&np->lock);
5086 #ifdef CONFIG_FORCEDETH_NAPI
5087         napi_disable(&np->napi);
5088 #endif
5089         synchronize_irq(np->pci_dev->irq);
5090
5091         del_timer_sync(&np->oom_kick);
5092         del_timer_sync(&np->nic_poll);
5093         del_timer_sync(&np->stats_poll);
5094
5095         netif_stop_queue(dev);
5096         spin_lock_irq(&np->lock);
5097         nv_stop_tx(dev);
5098         nv_stop_rx(dev);
5099         nv_txrx_reset(dev);
5100
5101         /* disable interrupts on the nic or we will lock up */
5102         base = get_hwbase(dev);
5103         nv_disable_hw_interrupts(dev, np->irqmask);
5104         pci_push(base);
5105         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5106
5107         spin_unlock_irq(&np->lock);
5108
5109         nv_free_irq(dev);
5110
5111         drain_ring(dev);
5112
5113         if (np->wolenabled) {
5114                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5115                 nv_start_rx(dev);
5116         }
5117
5118         /* FIXME: power down nic */
5119
5120         return 0;
5121 }
5122
5123 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5124 {
5125         struct net_device *dev;
5126         struct fe_priv *np;
5127         unsigned long addr;
5128         u8 __iomem *base;
5129         int err, i;
5130         u32 powerstate, txreg;
5131         u32 phystate_orig = 0, phystate;
5132         int phyinitialized = 0;
5133         DECLARE_MAC_BUF(mac);
5134         static int printed_version;
5135
5136         if (!printed_version++)
5137                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5138                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5139
5140         dev = alloc_etherdev(sizeof(struct fe_priv));
5141         err = -ENOMEM;
5142         if (!dev)
5143                 goto out;
5144
5145         np = netdev_priv(dev);
5146         np->dev = dev;
5147         np->pci_dev = pci_dev;
5148         spin_lock_init(&np->lock);
5149         SET_NETDEV_DEV(dev, &pci_dev->dev);
5150
5151         init_timer(&np->oom_kick);
5152         np->oom_kick.data = (unsigned long) dev;
5153         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5154         init_timer(&np->nic_poll);
5155         np->nic_poll.data = (unsigned long) dev;
5156         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5157         init_timer(&np->stats_poll);
5158         np->stats_poll.data = (unsigned long) dev;
5159         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5160
5161         err = pci_enable_device(pci_dev);
5162         if (err)
5163                 goto out_free;
5164
5165         pci_set_master(pci_dev);
5166
5167         err = pci_request_regions(pci_dev, DRV_NAME);
5168         if (err < 0)
5169                 goto out_disable;
5170
5171         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5172                 np->register_size = NV_PCI_REGSZ_VER3;
5173         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5174                 np->register_size = NV_PCI_REGSZ_VER2;
5175         else
5176                 np->register_size = NV_PCI_REGSZ_VER1;
5177
5178         err = -EINVAL;
5179         addr = 0;
5180         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5181                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5182                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5183                                 pci_resource_len(pci_dev, i),
5184                                 pci_resource_flags(pci_dev, i));
5185                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5186                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5187                         addr = pci_resource_start(pci_dev, i);
5188                         break;
5189                 }
5190         }
5191         if (i == DEVICE_COUNT_RESOURCE) {
5192                 dev_printk(KERN_INFO, &pci_dev->dev,
5193                            "Couldn't find register window\n");
5194                 goto out_relreg;
5195         }
5196
5197         /* copy of driver data */
5198         np->driver_data = id->driver_data;
5199
5200         /* handle different descriptor versions */
5201         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5202                 /* packet format 3: supports 40-bit addressing */
5203                 np->desc_ver = DESC_VER_3;
5204                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5205                 if (dma_64bit) {
5206                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5207                                 dev_printk(KERN_INFO, &pci_dev->dev,
5208                                         "64-bit DMA failed, using 32-bit addressing\n");
5209                         else
5210                                 dev->features |= NETIF_F_HIGHDMA;
5211                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5212                                 dev_printk(KERN_INFO, &pci_dev->dev,
5213                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5214                         }
5215                 }
5216         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5217                 /* packet format 2: supports jumbo frames */
5218                 np->desc_ver = DESC_VER_2;
5219                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5220         } else {
5221                 /* original packet format */
5222                 np->desc_ver = DESC_VER_1;
5223                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5224         }
5225
5226         np->pkt_limit = NV_PKTLIMIT_1;
5227         if (id->driver_data & DEV_HAS_LARGEDESC)
5228                 np->pkt_limit = NV_PKTLIMIT_2;
5229
5230         if (id->driver_data & DEV_HAS_CHECKSUM) {
5231                 np->rx_csum = 1;
5232                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5233                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5234                 dev->features |= NETIF_F_TSO;
5235         }
5236
5237         np->vlanctl_bits = 0;
5238         if (id->driver_data & DEV_HAS_VLAN) {
5239                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5240                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5241                 dev->vlan_rx_register = nv_vlan_rx_register;
5242         }
5243
5244         np->msi_flags = 0;
5245         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5246                 np->msi_flags |= NV_MSI_CAPABLE;
5247         }
5248         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5249                 np->msi_flags |= NV_MSI_X_CAPABLE;
5250         }
5251
5252         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5253         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5254             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5255             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5256                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5257         }
5258
5259
5260         err = -ENOMEM;
5261         np->base = ioremap(addr, np->register_size);
5262         if (!np->base)
5263                 goto out_relreg;
5264         dev->base_addr = (unsigned long)np->base;
5265
5266         dev->irq = pci_dev->irq;
5267
5268         np->rx_ring_size = RX_RING_DEFAULT;
5269         np->tx_ring_size = TX_RING_DEFAULT;
5270
5271         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
5272                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5273                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5274                                         &np->ring_addr);
5275                 if (!np->rx_ring.orig)
5276                         goto out_unmap;
5277                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5278         } else {
5279                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5280                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5281                                         &np->ring_addr);
5282                 if (!np->rx_ring.ex)
5283                         goto out_unmap;
5284                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5285         }
5286         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5287         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5288         if (!np->rx_skb || !np->tx_skb)
5289                 goto out_freering;
5290
5291         dev->open = nv_open;
5292         dev->stop = nv_close;
5293         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5294                 dev->hard_start_xmit = nv_start_xmit;
5295         else
5296                 dev->hard_start_xmit = nv_start_xmit_optimized;
5297         dev->get_stats = nv_get_stats;
5298         dev->change_mtu = nv_change_mtu;
5299         dev->set_mac_address = nv_set_mac_address;
5300         dev->set_multicast_list = nv_set_multicast;
5301 #ifdef CONFIG_NET_POLL_CONTROLLER
5302         dev->poll_controller = nv_poll_controller;
5303 #endif
5304 #ifdef CONFIG_FORCEDETH_NAPI
5305         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5306 #endif
5307         SET_ETHTOOL_OPS(dev, &ops);
5308         dev->tx_timeout = nv_tx_timeout;
5309         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5310
5311         pci_set_drvdata(pci_dev, dev);
5312
5313         /* read the mac address */
5314         base = get_hwbase(dev);
5315         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5316         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5317
5318         /* check the workaround bit for correct mac address order */
5319         txreg = readl(base + NvRegTransmitPoll);
5320         if ((txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) ||
5321             (id->driver_data & DEV_HAS_CORRECT_MACADDR)) {
5322                 /* mac address is already in correct order */
5323                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5324                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5325                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5326                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5327                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5328                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5329         } else {
5330                 /* need to reverse mac address to correct order */
5331                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5332                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5333                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5334                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5335                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5336                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5337                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5338         }
5339         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5340
5341         if (!is_valid_ether_addr(dev->perm_addr)) {
5342                 /*
5343                  * Bad mac address. At least one bios sets the mac address
5344                  * to 01:23:45:67:89:ab
5345                  */
5346                 dev_printk(KERN_ERR, &pci_dev->dev,
5347                         "Invalid Mac address detected: %s\n",
5348                         print_mac(mac, dev->dev_addr));
5349                 dev_printk(KERN_ERR, &pci_dev->dev,
5350                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5351                 dev->dev_addr[0] = 0x00;
5352                 dev->dev_addr[1] = 0x00;
5353                 dev->dev_addr[2] = 0x6c;
5354                 get_random_bytes(&dev->dev_addr[3], 3);
5355         }
5356
5357         dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5358                 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
5359
5360         /* set mac address */
5361         nv_copy_mac_to_hw(dev);
5362
5363         /* disable WOL */
5364         writel(0, base + NvRegWakeUpFlags);
5365         np->wolenabled = 0;
5366
5367         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5368
5369                 /* take phy and nic out of low power mode */
5370                 powerstate = readl(base + NvRegPowerState2);
5371                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5372                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5373                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5374                     pci_dev->revision >= 0xA3)
5375                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5376                 writel(powerstate, base + NvRegPowerState2);
5377         }
5378
5379         if (np->desc_ver == DESC_VER_1) {
5380                 np->tx_flags = NV_TX_VALID;
5381         } else {
5382                 np->tx_flags = NV_TX2_VALID;
5383         }
5384         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5385                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5386                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5387                         np->msi_flags |= 0x0003;
5388         } else {
5389                 np->irqmask = NVREG_IRQMASK_CPU;
5390                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5391                         np->msi_flags |= 0x0001;
5392         }
5393
5394         if (id->driver_data & DEV_NEED_TIMERIRQ)
5395                 np->irqmask |= NVREG_IRQ_TIMER;
5396         if (id->driver_data & DEV_NEED_LINKTIMER) {
5397                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5398                 np->need_linktimer = 1;
5399                 np->link_timeout = jiffies + LINK_TIMEOUT;
5400         } else {
5401                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5402                 np->need_linktimer = 0;
5403         }
5404
5405         /* Limit the number of tx's outstanding for hw bug */
5406         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5407                 np->tx_limit = 1;
5408                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5409                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5410                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5411                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5412                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5413                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5414                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5415                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5416                     pci_dev->revision >= 0xA2)
5417                         np->tx_limit = 0;
5418         }
5419
5420         /* clear phy state and temporarily halt phy interrupts */
5421         writel(0, base + NvRegMIIMask);
5422         phystate = readl(base + NvRegAdapterControl);
5423         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5424                 phystate_orig = 1;
5425                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5426                 writel(phystate, base + NvRegAdapterControl);
5427         }
5428         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5429
5430         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5431                 /* management unit running on the mac? */
5432                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5433                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5434                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5435                         if (nv_mgmt_acquire_sema(dev)) {
5436                                 /* management unit setup the phy already? */
5437                                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5438                                     NVREG_XMITCTL_SYNC_PHY_INIT) {
5439                                         /* phy is inited by mgmt unit */
5440                                         phyinitialized = 1;
5441                                         dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5442                                 } else {
5443                                         /* we need to init the phy */
5444                                 }
5445                         }
5446                 }
5447         }
5448
5449         /* find a suitable phy */
5450         for (i = 1; i <= 32; i++) {
5451                 int id1, id2;
5452                 int phyaddr = i & 0x1F;
5453
5454                 spin_lock_irq(&np->lock);
5455                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5456                 spin_unlock_irq(&np->lock);
5457                 if (id1 < 0 || id1 == 0xffff)
5458                         continue;
5459                 spin_lock_irq(&np->lock);
5460                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5461                 spin_unlock_irq(&np->lock);
5462                 if (id2 < 0 || id2 == 0xffff)
5463                         continue;
5464
5465                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5466                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5467                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5468                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5469                         pci_name(pci_dev), id1, id2, phyaddr);
5470                 np->phyaddr = phyaddr;
5471                 np->phy_oui = id1 | id2;
5472                 break;
5473         }
5474         if (i == 33) {
5475                 dev_printk(KERN_INFO, &pci_dev->dev,
5476                         "open: Could not find a valid PHY.\n");
5477                 goto out_error;
5478         }
5479
5480         if (!phyinitialized) {
5481                 /* reset it */
5482                 phy_init(dev);
5483         } else {
5484                 /* see if it is a gigabit phy */
5485                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5486                 if (mii_status & PHY_GIGABIT) {
5487                         np->gigabit = PHY_GIGABIT;
5488                 }
5489         }
5490
5491         /* set default link speed settings */
5492         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5493         np->duplex = 0;
5494         np->autoneg = 1;
5495
5496         err = register_netdev(dev);
5497         if (err) {
5498                 dev_printk(KERN_INFO, &pci_dev->dev,
5499                            "unable to register netdev: %d\n", err);
5500                 goto out_error;
5501         }
5502
5503         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5504                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5505                    dev->name,
5506                    np->phy_oui,
5507                    np->phyaddr,
5508                    dev->dev_addr[0],
5509                    dev->dev_addr[1],
5510                    dev->dev_addr[2],
5511                    dev->dev_addr[3],
5512                    dev->dev_addr[4],
5513                    dev->dev_addr[5]);
5514
5515         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5516                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5517                    dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5518                         "csum " : "",
5519                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5520                         "vlan " : "",
5521                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5522                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5523                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5524                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5525                    np->need_linktimer ? "lnktim " : "",
5526                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5527                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5528                    np->desc_ver);
5529
5530         return 0;
5531
5532 out_error:
5533         if (phystate_orig)
5534                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5535         pci_set_drvdata(pci_dev, NULL);
5536 out_freering:
5537         free_rings(dev);
5538 out_unmap:
5539         iounmap(get_hwbase(dev));
5540 out_relreg:
5541         pci_release_regions(pci_dev);
5542 out_disable:
5543         pci_disable_device(pci_dev);
5544 out_free:
5545         free_netdev(dev);
5546 out:
5547         return err;
5548 }
5549
5550 static void __devexit nv_remove(struct pci_dev *pci_dev)
5551 {
5552         struct net_device *dev = pci_get_drvdata(pci_dev);
5553         struct fe_priv *np = netdev_priv(dev);
5554         u8 __iomem *base = get_hwbase(dev);
5555
5556         unregister_netdev(dev);
5557
5558         /* special op: write back the misordered MAC address - otherwise
5559          * the next nv_probe would see a wrong address.
5560          */
5561         writel(np->orig_mac[0], base + NvRegMacAddrA);
5562         writel(np->orig_mac[1], base + NvRegMacAddrB);
5563         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5564                base + NvRegTransmitPoll);
5565
5566         /* free all structures */
5567         free_rings(dev);
5568         iounmap(get_hwbase(dev));
5569         pci_release_regions(pci_dev);
5570         pci_disable_device(pci_dev);
5571         free_netdev(dev);
5572         pci_set_drvdata(pci_dev, NULL);
5573 }
5574
5575 #ifdef CONFIG_PM
5576 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5577 {
5578         struct net_device *dev = pci_get_drvdata(pdev);
5579         struct fe_priv *np = netdev_priv(dev);
5580
5581         if (!netif_running(dev))
5582                 goto out;
5583
5584         netif_device_detach(dev);
5585
5586         // Gross.
5587         nv_close(dev);
5588
5589         pci_save_state(pdev);
5590         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5591         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5592 out:
5593         return 0;
5594 }
5595
5596 static int nv_resume(struct pci_dev *pdev)
5597 {
5598         struct net_device *dev = pci_get_drvdata(pdev);
5599         int rc = 0;
5600
5601         if (!netif_running(dev))
5602                 goto out;
5603
5604         netif_device_attach(dev);
5605
5606         pci_set_power_state(pdev, PCI_D0);
5607         pci_restore_state(pdev);
5608         pci_enable_wake(pdev, PCI_D0, 0);
5609
5610         rc = nv_open(dev);
5611 out:
5612         return rc;
5613 }
5614 #else
5615 #define nv_suspend NULL
5616 #define nv_resume NULL
5617 #endif /* CONFIG_PM */
5618
5619 static struct pci_device_id pci_tbl[] = {
5620         {       /* nForce Ethernet Controller */
5621                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5622                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5623         },
5624         {       /* nForce2 Ethernet Controller */
5625                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5626                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5627         },
5628         {       /* nForce3 Ethernet Controller */
5629                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5630                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5631         },
5632         {       /* nForce3 Ethernet Controller */
5633                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5634                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5635         },
5636         {       /* nForce3 Ethernet Controller */
5637                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5638                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5639         },
5640         {       /* nForce3 Ethernet Controller */
5641                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5642                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5643         },
5644         {       /* nForce3 Ethernet Controller */
5645                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5646                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5647         },
5648         {       /* CK804 Ethernet Controller */
5649                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5650                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5651         },
5652         {       /* CK804 Ethernet Controller */
5653                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5654                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5655         },
5656         {       /* MCP04 Ethernet Controller */
5657                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5658                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5659         },
5660         {       /* MCP04 Ethernet Controller */
5661                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5662                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5663         },
5664         {       /* MCP51 Ethernet Controller */
5665                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5666                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5667         },
5668         {       /* MCP51 Ethernet Controller */
5669                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5670                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5671         },
5672         {       /* MCP55 Ethernet Controller */
5673                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5674                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5675         },
5676         {       /* MCP55 Ethernet Controller */
5677                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5678                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5679         },
5680         {       /* MCP61 Ethernet Controller */
5681                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5682                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5683         },
5684         {       /* MCP61 Ethernet Controller */
5685                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5686                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5687         },
5688         {       /* MCP61 Ethernet Controller */
5689                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5690                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5691         },
5692         {       /* MCP61 Ethernet Controller */
5693                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5694                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5695         },
5696         {       /* MCP65 Ethernet Controller */
5697                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5698                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT,
5699         },
5700         {       /* MCP65 Ethernet Controller */
5701                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5702                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5703         },
5704         {       /* MCP65 Ethernet Controller */
5705                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5706                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5707         },
5708         {       /* MCP65 Ethernet Controller */
5709                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5710                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5711         },
5712         {       /* MCP67 Ethernet Controller */
5713                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5714                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5715         },
5716         {       /* MCP67 Ethernet Controller */
5717                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5718                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5719         },
5720         {       /* MCP67 Ethernet Controller */
5721                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5722                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5723         },
5724         {       /* MCP67 Ethernet Controller */
5725                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5726                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5727         },
5728         {       /* MCP73 Ethernet Controller */
5729                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
5730                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5731         },
5732         {       /* MCP73 Ethernet Controller */
5733                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
5734                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5735         },
5736         {       /* MCP73 Ethernet Controller */
5737                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
5738                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5739         },
5740         {       /* MCP73 Ethernet Controller */
5741                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
5742                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5743         },
5744         {       /* MCP77 Ethernet Controller */
5745                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
5746                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5747         },
5748         {       /* MCP77 Ethernet Controller */
5749                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
5750                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5751         },
5752         {       /* MCP77 Ethernet Controller */
5753                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
5754                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5755         },
5756         {       /* MCP77 Ethernet Controller */
5757                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
5758                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5759         },
5760         {       /* MCP79 Ethernet Controller */
5761                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
5762                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5763         },
5764         {       /* MCP79 Ethernet Controller */
5765                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
5766                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5767         },
5768         {       /* MCP79 Ethernet Controller */
5769                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
5770                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5771         },
5772         {       /* MCP79 Ethernet Controller */
5773                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
5774                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5775         },
5776         {0,},
5777 };
5778
5779 static struct pci_driver driver = {
5780         .name           = DRV_NAME,
5781         .id_table       = pci_tbl,
5782         .probe          = nv_probe,
5783         .remove         = __devexit_p(nv_remove),
5784         .suspend        = nv_suspend,
5785         .resume         = nv_resume,
5786 };
5787
5788 static int __init init_nic(void)
5789 {
5790         return pci_register_driver(&driver);
5791 }
5792
5793 static void __exit exit_nic(void)
5794 {
5795         pci_unregister_driver(&driver);
5796 }
5797
5798 module_param(max_interrupt_work, int, 0);
5799 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5800 module_param(optimization_mode, int, 0);
5801 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5802 module_param(poll_interval, int, 0);
5803 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5804 module_param(msi, int, 0);
5805 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5806 module_param(msix, int, 0);
5807 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5808 module_param(dma_64bit, int, 0);
5809 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5810
5811 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5812 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5813 MODULE_LICENSE("GPL");
5814
5815 MODULE_DEVICE_TABLE(pci, pci_tbl);
5816
5817 module_init(init_nic);
5818 module_exit(exit_nic);