2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
44 #include <asm/cacheflush.h>
46 #ifndef CONFIG_ARCH_MXC
47 #include <asm/coldfire.h>
48 #include <asm/mcfsim.h>
53 #ifdef CONFIG_ARCH_MXC
54 #include <mach/hardware.h>
55 #define FEC_ALIGNMENT 0xf
57 #define FEC_ALIGNMENT 0x3
61 * Define the fixed address of the FEC hardware.
63 #if defined(CONFIG_M5272)
64 #define HAVE_mii_link_interrupt
66 static unsigned char fec_mac_default[] = {
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
71 * Some hardware gets it MAC address out of local flash memory.
72 * if this is non-zero then assume it is the address to get MAC from.
74 #if defined(CONFIG_NETtel)
75 #define FEC_FLASHMAC 0xf0006006
76 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
77 #define FEC_FLASHMAC 0xf0006000
78 #elif defined(CONFIG_CANCam)
79 #define FEC_FLASHMAC 0xf0020000
80 #elif defined (CONFIG_M5272C3)
81 #define FEC_FLASHMAC (0xffe04000 + 4)
82 #elif defined(CONFIG_MOD5272)
83 #define FEC_FLASHMAC 0xffc0406b
85 #define FEC_FLASHMAC 0
87 #endif /* CONFIG_M5272 */
89 /* Forward declarations of some structures to support different PHYs */
93 void (*funct)(uint mii_reg, struct net_device *dev);
100 const phy_cmd_t *config;
101 const phy_cmd_t *startup;
102 const phy_cmd_t *ack_int;
103 const phy_cmd_t *shutdown;
106 /* The number of Tx and Rx buffers. These are allocated from the page
107 * pool. The code may assume these are power of two, so it it best
108 * to keep them that size.
109 * We don't need to allocate pages for the transmitter. We just use
110 * the skbuffer directly.
112 #define FEC_ENET_RX_PAGES 8
113 #define FEC_ENET_RX_FRSIZE 2048
114 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
115 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
116 #define FEC_ENET_TX_FRSIZE 2048
117 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
118 #define TX_RING_SIZE 16 /* Must be power of two */
119 #define TX_RING_MOD_MASK 15 /* for this to work */
121 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
122 #error "FEC: descriptor ring size constants too large"
125 /* Interrupt events/masks. */
126 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
127 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
128 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
129 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
130 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
131 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
132 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
133 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
134 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
135 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
137 /* The FEC stores dest/src/type, data, and checksum for receive packets.
139 #define PKT_MAXBUF_SIZE 1518
140 #define PKT_MINBUF_SIZE 64
141 #define PKT_MAXBLR_SIZE 1520
145 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
146 * size bits. Other FEC hardware does not, so we need to take that into
147 * account when setting it.
149 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
151 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
153 #define OPT_FRAME_SIZE 0
156 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
157 * tx_bd_base always point to the base of the buffer descriptors. The
158 * cur_rx and cur_tx point to the currently available buffer.
159 * The dirty_tx tracks the current buffer that is being sent by the
160 * controller. The cur_tx and dirty_tx are equal under both completely
161 * empty and completely full conditions. The empty/ready indicator in
162 * the buffer descriptor determines the actual condition.
164 struct fec_enet_private {
165 /* Hardware registers of the FEC device */
168 struct net_device *netdev;
172 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
173 unsigned char *tx_bounce[TX_RING_SIZE];
174 struct sk_buff* tx_skbuff[TX_RING_SIZE];
178 /* CPM dual port RAM relative addresses */
180 /* Address of Rx and Tx buffers */
181 struct bufdesc *rx_bd_base;
182 struct bufdesc *tx_bd_base;
183 /* The next free ring entry */
184 struct bufdesc *cur_rx, *cur_tx;
185 /* The ring entries to be free()ed */
186 struct bufdesc *dirty_tx;
189 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
191 /* hold while accessing the mii_list_t() elements */
198 phy_info_t const *phy;
199 struct work_struct phy_task;
202 uint mii_phy_task_queued;
213 static void fec_enet_mii(struct net_device *dev);
214 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
215 static void fec_enet_tx(struct net_device *dev);
216 static void fec_enet_rx(struct net_device *dev);
217 static int fec_enet_close(struct net_device *dev);
218 static void fec_restart(struct net_device *dev, int duplex);
219 static void fec_stop(struct net_device *dev);
222 /* MII processing. We keep this as simple as possible. Requests are
223 * placed on the list (if there is room). When the request is finished
224 * by the MII, an optional function may be called.
226 typedef struct mii_list {
228 void (*mii_func)(uint val, struct net_device *dev);
229 struct mii_list *mii_next;
233 static mii_list_t mii_cmds[NMII];
234 static mii_list_t *mii_free;
235 static mii_list_t *mii_head;
236 static mii_list_t *mii_tail;
238 static int mii_queue(struct net_device *dev, int request,
239 void (*func)(uint, struct net_device *));
241 /* Make MII read/write commands for the FEC */
242 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
243 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
247 /* Transmitter timeout */
248 #define TX_TIMEOUT (2 * HZ)
250 /* Register definitions for the PHY */
252 #define MII_REG_CR 0 /* Control Register */
253 #define MII_REG_SR 1 /* Status Register */
254 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
255 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
256 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
257 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
258 #define MII_REG_ANER 6 /* A-N Expansion Register */
259 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
260 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
262 /* values for phy_status */
264 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
265 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
266 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
267 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
268 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
269 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
270 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
272 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
273 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
274 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
275 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
276 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
277 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
278 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
279 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
283 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
285 struct fec_enet_private *fep = netdev_priv(dev);
287 unsigned short status;
291 /* Link is down or autonegotiation is in progress. */
295 spin_lock_irqsave(&fep->hw_lock, flags);
296 /* Fill in a Tx ring entry */
299 status = bdp->cbd_sc;
301 if (status & BD_ENET_TX_READY) {
302 /* Ooops. All transmit buffers are full. Bail out.
303 * This should not happen, since dev->tbusy should be set.
305 printk("%s: tx queue full!.\n", dev->name);
306 spin_unlock_irqrestore(&fep->hw_lock, flags);
310 /* Clear all of the status flags */
311 status &= ~BD_ENET_TX_STATS;
313 /* Set buffer length and buffer pointer */
314 bdp->cbd_bufaddr = __pa(skb->data);
315 bdp->cbd_datlen = skb->len;
318 * On some FEC implementations data must be aligned on
319 * 4-byte boundaries. Use bounce buffers to copy data
320 * and get it aligned. Ugh.
322 if (bdp->cbd_bufaddr & FEC_ALIGNMENT) {
324 index = bdp - fep->tx_bd_base;
325 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
326 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
329 /* Save skb pointer */
330 fep->tx_skbuff[fep->skb_cur] = skb;
332 dev->stats.tx_bytes += skb->len;
333 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
335 /* Push the data cache so the CPM does not get stale memory
338 dma_sync_single(NULL, bdp->cbd_bufaddr,
339 bdp->cbd_datlen, DMA_TO_DEVICE);
341 /* Send it on its way. Tell FEC it's ready, interrupt when done,
342 * it's the last BD of the frame, and to put the CRC on the end.
344 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
345 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
346 bdp->cbd_sc = status;
348 dev->trans_start = jiffies;
350 /* Trigger transmission start */
351 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
353 /* If this was the last BD in the ring, start at the beginning again. */
354 if (status & BD_ENET_TX_WRAP)
355 bdp = fep->tx_bd_base;
359 if (bdp == fep->dirty_tx) {
361 netif_stop_queue(dev);
366 spin_unlock_irqrestore(&fep->hw_lock, flags);
372 fec_timeout(struct net_device *dev)
374 struct fec_enet_private *fep = netdev_priv(dev);
376 dev->stats.tx_errors++;
378 fec_restart(dev, fep->full_duplex);
379 netif_wake_queue(dev);
383 fec_enet_interrupt(int irq, void * dev_id)
385 struct net_device *dev = dev_id;
386 struct fec_enet_private *fep = netdev_priv(dev);
388 irqreturn_t ret = IRQ_NONE;
391 int_events = readl(fep->hwp + FEC_IEVENT);
392 writel(int_events, fep->hwp + FEC_IEVENT);
394 if (int_events & FEC_ENET_RXF) {
399 /* Transmit OK, or non-fatal error. Update the buffer
400 * descriptors. FEC handles all errors, we just discover
401 * them as part of the transmit process.
403 if (int_events & FEC_ENET_TXF) {
408 if (int_events & FEC_ENET_MII) {
413 } while (int_events);
420 fec_enet_tx(struct net_device *dev)
422 struct fec_enet_private *fep;
424 unsigned short status;
427 fep = netdev_priv(dev);
428 spin_lock_irq(&fep->hw_lock);
431 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
432 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
434 skb = fep->tx_skbuff[fep->skb_dirty];
435 /* Check for errors. */
436 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
437 BD_ENET_TX_RL | BD_ENET_TX_UN |
439 dev->stats.tx_errors++;
440 if (status & BD_ENET_TX_HB) /* No heartbeat */
441 dev->stats.tx_heartbeat_errors++;
442 if (status & BD_ENET_TX_LC) /* Late collision */
443 dev->stats.tx_window_errors++;
444 if (status & BD_ENET_TX_RL) /* Retrans limit */
445 dev->stats.tx_aborted_errors++;
446 if (status & BD_ENET_TX_UN) /* Underrun */
447 dev->stats.tx_fifo_errors++;
448 if (status & BD_ENET_TX_CSL) /* Carrier lost */
449 dev->stats.tx_carrier_errors++;
451 dev->stats.tx_packets++;
454 if (status & BD_ENET_TX_READY)
455 printk("HEY! Enet xmit interrupt and TX_READY.\n");
457 /* Deferred means some collisions occurred during transmit,
458 * but we eventually sent the packet OK.
460 if (status & BD_ENET_TX_DEF)
461 dev->stats.collisions++;
463 /* Free the sk buffer associated with this last transmit */
464 dev_kfree_skb_any(skb);
465 fep->tx_skbuff[fep->skb_dirty] = NULL;
466 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
468 /* Update pointer to next buffer descriptor to be transmitted */
469 if (status & BD_ENET_TX_WRAP)
470 bdp = fep->tx_bd_base;
474 /* Since we have freed up a buffer, the ring is no longer full
478 if (netif_queue_stopped(dev))
479 netif_wake_queue(dev);
483 spin_unlock_irq(&fep->hw_lock);
487 /* During a receive, the cur_rx points to the current incoming buffer.
488 * When we update through the ring, if the next incoming buffer has
489 * not been given to the system, we just set the empty indicator,
490 * effectively tossing the packet.
493 fec_enet_rx(struct net_device *dev)
495 struct fec_enet_private *fep = netdev_priv(dev);
497 unsigned short status;
506 spin_lock_irq(&fep->hw_lock);
508 /* First, grab all of the stats for the incoming packet.
509 * These get messed up if we get called due to a busy condition.
513 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
515 /* Since we have allocated space to hold a complete frame,
516 * the last indicator should be set.
518 if ((status & BD_ENET_RX_LAST) == 0)
519 printk("FEC ENET: rcv is not +last\n");
522 goto rx_processing_done;
524 /* Check for errors. */
525 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
526 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
527 dev->stats.rx_errors++;
528 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
529 /* Frame too long or too short. */
530 dev->stats.rx_length_errors++;
532 if (status & BD_ENET_RX_NO) /* Frame alignment */
533 dev->stats.rx_frame_errors++;
534 if (status & BD_ENET_RX_CR) /* CRC Error */
535 dev->stats.rx_crc_errors++;
536 if (status & BD_ENET_RX_OV) /* FIFO overrun */
537 dev->stats.rx_fifo_errors++;
540 /* Report late collisions as a frame error.
541 * On this error, the BD is closed, but we don't know what we
542 * have in the buffer. So, just drop this frame on the floor.
544 if (status & BD_ENET_RX_CL) {
545 dev->stats.rx_errors++;
546 dev->stats.rx_frame_errors++;
547 goto rx_processing_done;
550 /* Process the incoming frame. */
551 dev->stats.rx_packets++;
552 pkt_len = bdp->cbd_datlen;
553 dev->stats.rx_bytes += pkt_len;
554 data = (__u8*)__va(bdp->cbd_bufaddr);
556 dma_sync_single(NULL, (unsigned long)__pa(data),
557 pkt_len - 4, DMA_FROM_DEVICE);
559 /* This does 16 byte alignment, exactly what we need.
560 * The packet length includes FCS, but we don't want to
561 * include that when passing upstream as it messes up
562 * bridging applications.
564 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
566 if (unlikely(!skb)) {
567 printk("%s: Memory squeeze, dropping packet.\n",
569 dev->stats.rx_dropped++;
571 skb_reserve(skb, NET_IP_ALIGN);
572 skb_put(skb, pkt_len - 4); /* Make room */
573 skb_copy_to_linear_data(skb, data, pkt_len - 4);
574 skb->protocol = eth_type_trans(skb, dev);
578 /* Clear the status flags for this buffer */
579 status &= ~BD_ENET_RX_STATS;
581 /* Mark the buffer empty */
582 status |= BD_ENET_RX_EMPTY;
583 bdp->cbd_sc = status;
585 /* Update BD pointer to next entry */
586 if (status & BD_ENET_RX_WRAP)
587 bdp = fep->rx_bd_base;
590 /* Doing this here will keep the FEC running while we process
591 * incoming frames. On a heavily loaded network, we should be
592 * able to keep up at the expense of system resources.
594 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
598 spin_unlock_irq(&fep->hw_lock);
601 /* called from interrupt context */
603 fec_enet_mii(struct net_device *dev)
605 struct fec_enet_private *fep;
608 fep = netdev_priv(dev);
609 spin_lock_irq(&fep->mii_lock);
611 if ((mip = mii_head) == NULL) {
612 printk("MII and no head!\n");
616 if (mip->mii_func != NULL)
617 (*(mip->mii_func))(readl(fep->hwp + FEC_MII_DATA), dev);
619 mii_head = mip->mii_next;
620 mip->mii_next = mii_free;
623 if ((mip = mii_head) != NULL)
624 writel(mip->mii_regval, fep->hwp + FEC_MII_DATA);
627 spin_unlock_irq(&fep->mii_lock);
631 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
633 struct fec_enet_private *fep;
638 /* Add PHY address to register command */
639 fep = netdev_priv(dev);
640 spin_lock_irqsave(&fep->mii_lock, flags);
642 regval |= fep->phy_addr << 23;
645 if ((mip = mii_free) != NULL) {
646 mii_free = mip->mii_next;
647 mip->mii_regval = regval;
648 mip->mii_func = func;
649 mip->mii_next = NULL;
651 mii_tail->mii_next = mip;
654 mii_head = mii_tail = mip;
655 writel(regval, fep->hwp + FEC_MII_DATA);
661 spin_unlock_irqrestore(&fep->mii_lock, flags);
665 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
670 for (; c->mii_data != mk_mii_end; c++)
671 mii_queue(dev, c->mii_data, c->funct);
674 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
676 struct fec_enet_private *fep = netdev_priv(dev);
677 volatile uint *s = &(fep->phy_status);
680 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
682 if (mii_reg & 0x0004)
683 status |= PHY_STAT_LINK;
684 if (mii_reg & 0x0010)
685 status |= PHY_STAT_FAULT;
686 if (mii_reg & 0x0020)
687 status |= PHY_STAT_ANC;
691 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
693 struct fec_enet_private *fep = netdev_priv(dev);
694 volatile uint *s = &(fep->phy_status);
697 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
699 if (mii_reg & 0x1000)
700 status |= PHY_CONF_ANE;
701 if (mii_reg & 0x4000)
702 status |= PHY_CONF_LOOP;
706 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
708 struct fec_enet_private *fep = netdev_priv(dev);
709 volatile uint *s = &(fep->phy_status);
712 status = *s & ~(PHY_CONF_SPMASK);
714 if (mii_reg & 0x0020)
715 status |= PHY_CONF_10HDX;
716 if (mii_reg & 0x0040)
717 status |= PHY_CONF_10FDX;
718 if (mii_reg & 0x0080)
719 status |= PHY_CONF_100HDX;
720 if (mii_reg & 0x00100)
721 status |= PHY_CONF_100FDX;
725 /* ------------------------------------------------------------------------- */
726 /* The Level one LXT970 is used by many boards */
728 #define MII_LXT970_MIRROR 16 /* Mirror register */
729 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
730 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
731 #define MII_LXT970_CONFIG 19 /* Configuration Register */
732 #define MII_LXT970_CSR 20 /* Chip Status Register */
734 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
736 struct fec_enet_private *fep = netdev_priv(dev);
737 volatile uint *s = &(fep->phy_status);
740 status = *s & ~(PHY_STAT_SPMASK);
741 if (mii_reg & 0x0800) {
742 if (mii_reg & 0x1000)
743 status |= PHY_STAT_100FDX;
745 status |= PHY_STAT_100HDX;
747 if (mii_reg & 0x1000)
748 status |= PHY_STAT_10FDX;
750 status |= PHY_STAT_10HDX;
755 static phy_cmd_t const phy_cmd_lxt970_config[] = {
756 { mk_mii_read(MII_REG_CR), mii_parse_cr },
757 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
760 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
761 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
762 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
765 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
766 /* read SR and ISR to acknowledge */
767 { mk_mii_read(MII_REG_SR), mii_parse_sr },
768 { mk_mii_read(MII_LXT970_ISR), NULL },
770 /* find out the current status */
771 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
774 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
775 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
778 static phy_info_t const phy_info_lxt970 = {
781 .config = phy_cmd_lxt970_config,
782 .startup = phy_cmd_lxt970_startup,
783 .ack_int = phy_cmd_lxt970_ack_int,
784 .shutdown = phy_cmd_lxt970_shutdown
787 /* ------------------------------------------------------------------------- */
788 /* The Level one LXT971 is used on some of my custom boards */
790 /* register definitions for the 971 */
792 #define MII_LXT971_PCR 16 /* Port Control Register */
793 #define MII_LXT971_SR2 17 /* Status Register 2 */
794 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
795 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
796 #define MII_LXT971_LCR 20 /* LED Control Register */
797 #define MII_LXT971_TCR 30 /* Transmit Control Register */
800 * I had some nice ideas of running the MDIO faster...
801 * The 971 should support 8MHz and I tried it, but things acted really
802 * weird, so 2.5 MHz ought to be enough for anyone...
805 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
807 struct fec_enet_private *fep = netdev_priv(dev);
808 volatile uint *s = &(fep->phy_status);
811 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
813 if (mii_reg & 0x0400) {
815 status |= PHY_STAT_LINK;
819 if (mii_reg & 0x0080)
820 status |= PHY_STAT_ANC;
821 if (mii_reg & 0x4000) {
822 if (mii_reg & 0x0200)
823 status |= PHY_STAT_100FDX;
825 status |= PHY_STAT_100HDX;
827 if (mii_reg & 0x0200)
828 status |= PHY_STAT_10FDX;
830 status |= PHY_STAT_10HDX;
832 if (mii_reg & 0x0008)
833 status |= PHY_STAT_FAULT;
838 static phy_cmd_t const phy_cmd_lxt971_config[] = {
839 /* limit to 10MBit because my prototype board
840 * doesn't work with 100. */
841 { mk_mii_read(MII_REG_CR), mii_parse_cr },
842 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
843 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
846 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
847 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
848 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
849 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
850 /* Somehow does the 971 tell me that the link is down
851 * the first read after power-up.
852 * read here to get a valid value in ack_int */
853 { mk_mii_read(MII_REG_SR), mii_parse_sr },
856 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
857 /* acknowledge the int before reading status ! */
858 { mk_mii_read(MII_LXT971_ISR), NULL },
859 /* find out the current status */
860 { mk_mii_read(MII_REG_SR), mii_parse_sr },
861 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
864 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
865 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
868 static phy_info_t const phy_info_lxt971 = {
871 .config = phy_cmd_lxt971_config,
872 .startup = phy_cmd_lxt971_startup,
873 .ack_int = phy_cmd_lxt971_ack_int,
874 .shutdown = phy_cmd_lxt971_shutdown
877 /* ------------------------------------------------------------------------- */
878 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
880 /* register definitions */
882 #define MII_QS6612_MCR 17 /* Mode Control Register */
883 #define MII_QS6612_FTR 27 /* Factory Test Register */
884 #define MII_QS6612_MCO 28 /* Misc. Control Register */
885 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
886 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
887 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
889 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
891 struct fec_enet_private *fep = netdev_priv(dev);
892 volatile uint *s = &(fep->phy_status);
895 status = *s & ~(PHY_STAT_SPMASK);
897 switch((mii_reg >> 2) & 7) {
898 case 1: status |= PHY_STAT_10HDX; break;
899 case 2: status |= PHY_STAT_100HDX; break;
900 case 5: status |= PHY_STAT_10FDX; break;
901 case 6: status |= PHY_STAT_100FDX; break;
907 static phy_cmd_t const phy_cmd_qs6612_config[] = {
908 /* The PHY powers up isolated on the RPX,
909 * so send a command to allow operation.
911 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
913 /* parse cr and anar to get some info */
914 { mk_mii_read(MII_REG_CR), mii_parse_cr },
915 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
918 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
919 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
920 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
923 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
924 /* we need to read ISR, SR and ANER to acknowledge */
925 { mk_mii_read(MII_QS6612_ISR), NULL },
926 { mk_mii_read(MII_REG_SR), mii_parse_sr },
927 { mk_mii_read(MII_REG_ANER), NULL },
929 /* read pcr to get info */
930 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
933 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
934 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
937 static phy_info_t const phy_info_qs6612 = {
940 .config = phy_cmd_qs6612_config,
941 .startup = phy_cmd_qs6612_startup,
942 .ack_int = phy_cmd_qs6612_ack_int,
943 .shutdown = phy_cmd_qs6612_shutdown
946 /* ------------------------------------------------------------------------- */
947 /* AMD AM79C874 phy */
949 /* register definitions for the 874 */
951 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
952 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
953 #define MII_AM79C874_DR 18 /* Diagnostic Register */
954 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
955 #define MII_AM79C874_MCR 21 /* ModeControl Register */
956 #define MII_AM79C874_DC 23 /* Disconnect Counter */
957 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
959 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
961 struct fec_enet_private *fep = netdev_priv(dev);
962 volatile uint *s = &(fep->phy_status);
965 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
967 if (mii_reg & 0x0080)
968 status |= PHY_STAT_ANC;
969 if (mii_reg & 0x0400)
970 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
972 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
977 static phy_cmd_t const phy_cmd_am79c874_config[] = {
978 { mk_mii_read(MII_REG_CR), mii_parse_cr },
979 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
980 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
983 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
984 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
985 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
986 { mk_mii_read(MII_REG_SR), mii_parse_sr },
989 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
990 /* find out the current status */
991 { mk_mii_read(MII_REG_SR), mii_parse_sr },
992 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
993 /* we only need to read ISR to acknowledge */
994 { mk_mii_read(MII_AM79C874_ICSR), NULL },
997 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
998 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1001 static phy_info_t const phy_info_am79c874 = {
1004 .config = phy_cmd_am79c874_config,
1005 .startup = phy_cmd_am79c874_startup,
1006 .ack_int = phy_cmd_am79c874_ack_int,
1007 .shutdown = phy_cmd_am79c874_shutdown
1011 /* ------------------------------------------------------------------------- */
1012 /* Kendin KS8721BL phy */
1014 /* register definitions for the 8721 */
1016 #define MII_KS8721BL_RXERCR 21
1017 #define MII_KS8721BL_ICSR 27
1018 #define MII_KS8721BL_PHYCR 31
1020 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1021 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1022 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1025 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1026 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1027 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1028 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1031 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1032 /* find out the current status */
1033 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1034 /* we only need to read ISR to acknowledge */
1035 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1038 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1039 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1042 static phy_info_t const phy_info_ks8721bl = {
1045 .config = phy_cmd_ks8721bl_config,
1046 .startup = phy_cmd_ks8721bl_startup,
1047 .ack_int = phy_cmd_ks8721bl_ack_int,
1048 .shutdown = phy_cmd_ks8721bl_shutdown
1051 /* ------------------------------------------------------------------------- */
1052 /* register definitions for the DP83848 */
1054 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1056 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1058 struct fec_enet_private *fep = netdev_priv(dev);
1059 volatile uint *s = &(fep->phy_status);
1061 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1064 if (mii_reg & 0x0001) {
1066 *s |= PHY_STAT_LINK;
1069 /* Status of link */
1070 if (mii_reg & 0x0010) /* Autonegotioation complete */
1072 if (mii_reg & 0x0002) { /* 10MBps? */
1073 if (mii_reg & 0x0004) /* Full Duplex? */
1074 *s |= PHY_STAT_10FDX;
1076 *s |= PHY_STAT_10HDX;
1077 } else { /* 100 Mbps? */
1078 if (mii_reg & 0x0004) /* Full Duplex? */
1079 *s |= PHY_STAT_100FDX;
1081 *s |= PHY_STAT_100HDX;
1083 if (mii_reg & 0x0008)
1084 *s |= PHY_STAT_FAULT;
1087 static phy_info_t phy_info_dp83848= {
1091 (const phy_cmd_t []) { /* config */
1092 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1093 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1094 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1097 (const phy_cmd_t []) { /* startup - enable interrupts */
1098 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1099 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1102 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1105 (const phy_cmd_t []) { /* shutdown */
1110 /* ------------------------------------------------------------------------- */
1112 static phy_info_t const * const phy_info[] = {
1122 /* ------------------------------------------------------------------------- */
1123 #ifdef HAVE_mii_link_interrupt
1125 mii_link_interrupt(int irq, void * dev_id);
1128 * This is specific to the MII interrupt setup of the M5272EVB.
1130 static void __inline__ fec_request_mii_intr(struct net_device *dev)
1132 if (request_irq(66, mii_link_interrupt, IRQF_DISABLED, "fec(MII)", dev) != 0)
1133 printk("FEC: Could not allocate fec(MII) IRQ(66)!\n");
1136 static void __inline__ fec_disable_phy_intr(void)
1138 volatile unsigned long *icrp;
1139 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1143 static void __inline__ fec_phy_ack_intr(void)
1145 volatile unsigned long *icrp;
1146 /* Acknowledge the interrupt */
1147 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1152 static void __inline__ fec_get_mac(struct net_device *dev)
1154 struct fec_enet_private *fep = netdev_priv(dev);
1155 unsigned char *iap, tmpaddr[ETH_ALEN];
1159 * Get MAC address from FLASH.
1160 * If it is all 1's or 0's, use the default.
1162 iap = (unsigned char *)FEC_FLASHMAC;
1163 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1164 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1165 iap = fec_mac_default;
1166 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1167 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1168 iap = fec_mac_default;
1170 *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
1171 *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1175 memcpy(dev->dev_addr, iap, ETH_ALEN);
1177 /* Adjust MAC if using default MAC address */
1178 if (iap == fec_mac_default)
1179 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1183 /* ------------------------------------------------------------------------- */
1185 static void mii_display_status(struct net_device *dev)
1187 struct fec_enet_private *fep = netdev_priv(dev);
1188 volatile uint *s = &(fep->phy_status);
1190 if (!fep->link && !fep->old_link) {
1191 /* Link is still down - don't print anything */
1195 printk("%s: status: ", dev->name);
1198 printk("link down");
1202 switch(*s & PHY_STAT_SPMASK) {
1203 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1204 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1205 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1206 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1208 printk(", Unknown speed/duplex");
1211 if (*s & PHY_STAT_ANC)
1212 printk(", auto-negotiation complete");
1215 if (*s & PHY_STAT_FAULT)
1216 printk(", remote fault");
1221 static void mii_display_config(struct work_struct *work)
1223 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1224 struct net_device *dev = fep->netdev;
1225 uint status = fep->phy_status;
1228 ** When we get here, phy_task is already removed from
1229 ** the workqueue. It is thus safe to allow to reuse it.
1231 fep->mii_phy_task_queued = 0;
1232 printk("%s: config: auto-negotiation ", dev->name);
1234 if (status & PHY_CONF_ANE)
1239 if (status & PHY_CONF_100FDX)
1241 if (status & PHY_CONF_100HDX)
1243 if (status & PHY_CONF_10FDX)
1245 if (status & PHY_CONF_10HDX)
1247 if (!(status & PHY_CONF_SPMASK))
1248 printk(", No speed/duplex selected?");
1250 if (status & PHY_CONF_LOOP)
1251 printk(", loopback enabled");
1255 fep->sequence_done = 1;
1258 static void mii_relink(struct work_struct *work)
1260 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1261 struct net_device *dev = fep->netdev;
1265 ** When we get here, phy_task is already removed from
1266 ** the workqueue. It is thus safe to allow to reuse it.
1268 fep->mii_phy_task_queued = 0;
1269 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1270 mii_display_status(dev);
1271 fep->old_link = fep->link;
1276 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1278 fec_restart(dev, duplex);
1283 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1284 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1286 struct fec_enet_private *fep = netdev_priv(dev);
1289 * We cannot queue phy_task twice in the workqueue. It
1290 * would cause an endless loop in the workqueue.
1291 * Fortunately, if the last mii_relink entry has not yet been
1292 * executed now, it will do the job for the current interrupt,
1293 * which is just what we want.
1295 if (fep->mii_phy_task_queued)
1298 fep->mii_phy_task_queued = 1;
1299 INIT_WORK(&fep->phy_task, mii_relink);
1300 schedule_work(&fep->phy_task);
1303 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1304 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1306 struct fec_enet_private *fep = netdev_priv(dev);
1308 if (fep->mii_phy_task_queued)
1311 fep->mii_phy_task_queued = 1;
1312 INIT_WORK(&fep->phy_task, mii_display_config);
1313 schedule_work(&fep->phy_task);
1316 phy_cmd_t const phy_cmd_relink[] = {
1317 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1320 phy_cmd_t const phy_cmd_config[] = {
1321 { mk_mii_read(MII_REG_CR), mii_queue_config },
1325 /* Read remainder of PHY ID. */
1327 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1329 struct fec_enet_private *fep;
1332 fep = netdev_priv(dev);
1333 fep->phy_id |= (mii_reg & 0xffff);
1334 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1336 for(i = 0; phy_info[i]; i++) {
1337 if(phy_info[i]->id == (fep->phy_id >> 4))
1342 printk(" -- %s\n", phy_info[i]->name);
1344 printk(" -- unknown PHY!\n");
1346 fep->phy = phy_info[i];
1347 fep->phy_id_done = 1;
1350 /* Scan all of the MII PHY addresses looking for someone to respond
1351 * with a valid ID. This usually happens quickly.
1354 mii_discover_phy(uint mii_reg, struct net_device *dev)
1356 struct fec_enet_private *fep;
1359 fep = netdev_priv(dev);
1361 if (fep->phy_addr < 32) {
1362 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1364 /* Got first part of ID, now get remainder */
1365 fep->phy_id = phytype << 16;
1366 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1370 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1374 printk("FEC: No PHY device found.\n");
1375 /* Disable external MII interface */
1376 writel(0, fep->hwp + FEC_MII_SPEED);
1378 #ifdef HAVE_mii_link_interrupt
1379 fec_disable_phy_intr();
1384 /* This interrupt occurs when the PHY detects a link change */
1385 #ifdef HAVE_mii_link_interrupt
1387 mii_link_interrupt(int irq, void * dev_id)
1389 struct net_device *dev = dev_id;
1390 struct fec_enet_private *fep = netdev_priv(dev);
1394 mii_do_cmd(dev, fep->phy->ack_int);
1395 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1402 fec_enet_open(struct net_device *dev)
1404 struct fec_enet_private *fep = netdev_priv(dev);
1406 /* I should reset the ring buffers here, but I don't yet know
1407 * a simple way to do that.
1410 fep->sequence_done = 0;
1414 mii_do_cmd(dev, fep->phy->ack_int);
1415 mii_do_cmd(dev, fep->phy->config);
1416 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1418 /* Poll until the PHY tells us its configuration
1420 * Request is initiated by mii_do_cmd above, but answer
1421 * comes by interrupt.
1422 * This should take about 25 usec per register at 2.5 MHz,
1423 * and we read approximately 5 registers.
1425 while(!fep->sequence_done)
1428 mii_do_cmd(dev, fep->phy->startup);
1430 /* Set the initial link state to true. A lot of hardware
1431 * based on this device does not implement a PHY interrupt,
1432 * so we are never notified of link change.
1436 fep->link = 1; /* lets just try it and see */
1437 /* no phy, go full duplex, it's most likely a hub chip */
1438 fec_restart(dev, 1);
1441 netif_start_queue(dev);
1447 fec_enet_close(struct net_device *dev)
1449 struct fec_enet_private *fep = netdev_priv(dev);
1451 /* Don't know what to do yet. */
1453 netif_stop_queue(dev);
1459 /* Set or clear the multicast filter for this adaptor.
1460 * Skeleton taken from sunlance driver.
1461 * The CPM Ethernet implementation allows Multicast as well as individual
1462 * MAC address filtering. Some of the drivers check to make sure it is
1463 * a group multicast address, and discard those that are not. I guess I
1464 * will do the same for now, but just remove the test if you want
1465 * individual filtering as well (do the upper net layers want or support
1466 * this kind of feature?).
1469 #define HASH_BITS 6 /* #bits in hash */
1470 #define CRC32_POLY 0xEDB88320
1472 static void set_multicast_list(struct net_device *dev)
1474 struct fec_enet_private *fep = netdev_priv(dev);
1475 struct dev_mc_list *dmi;
1476 unsigned int i, j, bit, data, crc, tmp;
1479 if (dev->flags & IFF_PROMISC) {
1480 tmp = readl(fep->hwp + FEC_R_CNTRL);
1482 writel(tmp, fep->hwp + FEC_R_CNTRL);
1486 tmp = readl(fep->hwp + FEC_R_CNTRL);
1488 writel(tmp, fep->hwp + FEC_R_CNTRL);
1490 if (dev->flags & IFF_ALLMULTI) {
1491 /* Catch all multicast addresses, so set the
1494 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1495 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1500 /* Clear filter and add the addresses in hash register
1502 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1503 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1507 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) {
1508 /* Only support group multicast for now */
1509 if (!(dmi->dmi_addr[0] & 1))
1512 /* calculate crc32 value of mac address */
1515 for (i = 0; i < dmi->dmi_addrlen; i++) {
1516 data = dmi->dmi_addr[i];
1517 for (bit = 0; bit < 8; bit++, data >>= 1) {
1519 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1523 /* only upper 6 bits (HASH_BITS) are used
1524 * which point to specific bit in he hash registers
1526 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1529 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1530 tmp |= 1 << (hash - 32);
1531 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1533 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1535 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1540 /* Set a MAC change in hardware. */
1542 fec_set_mac_address(struct net_device *dev, void *p)
1544 struct fec_enet_private *fep = netdev_priv(dev);
1545 struct sockaddr *addr = p;
1547 if (!is_valid_ether_addr(addr->sa_data))
1548 return -EADDRNOTAVAIL;
1550 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1552 writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
1553 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
1554 fep->hwp + FEC_ADDR_LOW);
1555 writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
1556 fep + FEC_ADDR_HIGH);
1560 static const struct net_device_ops fec_netdev_ops = {
1561 .ndo_open = fec_enet_open,
1562 .ndo_stop = fec_enet_close,
1563 .ndo_start_xmit = fec_enet_start_xmit,
1564 .ndo_set_multicast_list = set_multicast_list,
1565 .ndo_validate_addr = eth_validate_addr,
1566 .ndo_tx_timeout = fec_timeout,
1567 .ndo_set_mac_address = fec_set_mac_address,
1571 * XXX: We need to clean up on failure exits here.
1573 * index is only used in legacy code
1575 int __init fec_enet_init(struct net_device *dev, int index)
1577 struct fec_enet_private *fep = netdev_priv(dev);
1578 unsigned long mem_addr;
1579 struct bufdesc *bdp, *cbd_base;
1582 /* Allocate memory for buffer descriptors. */
1583 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1586 printk("FEC: allocate descriptor memory failed?\n");
1590 spin_lock_init(&fep->hw_lock);
1591 spin_lock_init(&fep->mii_lock);
1594 fep->hwp = (void __iomem *)dev->base_addr;
1597 /* Set the Ethernet address */
1603 l = readl(fep->hwp + FEC_ADDR_LOW);
1604 dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
1605 dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
1606 dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
1607 dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
1608 l = readl(fep->hwp + FEC_ADDR_HIGH);
1609 dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
1610 dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
1614 /* Set receive and transmit descriptor base. */
1615 fep->rx_bd_base = cbd_base;
1616 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1618 /* Initialize the receive buffer descriptors. */
1619 bdp = fep->rx_bd_base;
1620 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1622 /* Allocate a page */
1623 mem_addr = __get_free_page(GFP_KERNEL);
1624 /* XXX: missing check for allocation failure */
1626 /* Initialize the BD for every fragment in the page */
1627 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1628 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1629 bdp->cbd_bufaddr = __pa(mem_addr);
1630 mem_addr += FEC_ENET_RX_FRSIZE;
1635 /* Set the last buffer to wrap */
1637 bdp->cbd_sc |= BD_SC_WRAP;
1639 /* ...and the same for transmit */
1640 bdp = fep->tx_bd_base;
1641 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
1642 if (j >= FEC_ENET_TX_FRPPG) {
1643 mem_addr = __get_free_page(GFP_KERNEL);
1646 mem_addr += FEC_ENET_TX_FRSIZE;
1649 fep->tx_bounce[i] = (unsigned char *) mem_addr;
1651 /* Initialize the BD for every fragment in the page */
1653 bdp->cbd_bufaddr = 0;
1657 /* Set the last buffer to wrap */
1659 bdp->cbd_sc |= BD_SC_WRAP;
1661 #ifdef HAVE_mii_link_interrupt
1662 fec_request_mii_intr(dev);
1664 /* The FEC Ethernet specific entries in the device structure */
1665 dev->watchdog_timeo = TX_TIMEOUT;
1666 dev->netdev_ops = &fec_netdev_ops;
1668 for (i=0; i<NMII-1; i++)
1669 mii_cmds[i].mii_next = &mii_cmds[i+1];
1670 mii_free = mii_cmds;
1672 /* Set MII speed to 2.5 MHz */
1673 fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999)
1674 / 2500000) / 2) & 0x3F) << 1;
1675 fec_restart(dev, 0);
1677 /* Queue up command to detect the PHY and initialize the
1678 * remainder of the interface.
1680 fep->phy_id_done = 0;
1682 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1687 /* This function is called to start or restart the FEC during a link
1688 * change. This only happens when switching between half and full
1692 fec_restart(struct net_device *dev, int duplex)
1694 struct fec_enet_private *fep = netdev_priv(dev);
1695 struct bufdesc *bdp;
1698 /* Whack a reset. We should wait for this. */
1699 writel(1, fep->hwp + FEC_ECNTRL);
1702 /* Clear any outstanding interrupt. */
1703 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1705 /* Reset all multicast. */
1706 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1707 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1708 #ifndef CONFIG_M5272
1709 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1710 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1713 /* Set maximum receive buffer size. */
1714 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1716 /* Set receive and transmit descriptor base. */
1717 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1718 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1719 fep->hwp + FEC_X_DES_START);
1721 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1722 fep->cur_rx = fep->rx_bd_base;
1724 /* Reset SKB transmit buffers. */
1725 fep->skb_cur = fep->skb_dirty = 0;
1726 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
1727 if (fep->tx_skbuff[i]) {
1728 dev_kfree_skb_any(fep->tx_skbuff[i]);
1729 fep->tx_skbuff[i] = NULL;
1733 /* Initialize the receive buffer descriptors. */
1734 bdp = fep->rx_bd_base;
1735 for (i = 0; i < RX_RING_SIZE; i++) {
1737 /* Initialize the BD for every fragment in the page. */
1738 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1742 /* Set the last buffer to wrap */
1744 bdp->cbd_sc |= BD_SC_WRAP;
1746 /* ...and the same for transmit */
1747 bdp = fep->tx_bd_base;
1748 for (i = 0; i < TX_RING_SIZE; i++) {
1750 /* Initialize the BD for every fragment in the page. */
1752 bdp->cbd_bufaddr = 0;
1756 /* Set the last buffer to wrap */
1758 bdp->cbd_sc |= BD_SC_WRAP;
1760 /* Enable MII mode */
1762 /* MII enable / FD enable */
1763 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1764 writel(0x04, fep->hwp + FEC_X_CNTRL);
1766 /* MII enable / No Rcv on Xmit */
1767 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
1768 writel(0x0, fep->hwp + FEC_X_CNTRL);
1770 fep->full_duplex = duplex;
1773 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1775 /* And last, enable the transmit and receive processing */
1776 writel(2, fep->hwp + FEC_ECNTRL);
1777 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1779 /* Enable interrupts we wish to service */
1780 writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII,
1781 fep->hwp + FEC_IMASK);
1785 fec_stop(struct net_device *dev)
1787 struct fec_enet_private *fep = netdev_priv(dev);
1789 /* We cannot expect a graceful transmit stop without link !!! */
1791 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1793 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1794 printk("fec_stop : Graceful transmit stop did not complete !\n");
1797 /* Whack a reset. We should wait for this. */
1798 writel(1, fep->hwp + FEC_ECNTRL);
1801 /* Clear outstanding MII command interrupts. */
1802 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
1804 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1805 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1808 static int __devinit
1809 fec_probe(struct platform_device *pdev)
1811 struct fec_enet_private *fep;
1812 struct net_device *ndev;
1813 int i, irq, ret = 0;
1816 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1820 r = request_mem_region(r->start, resource_size(r), pdev->name);
1824 /* Init network device */
1825 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1829 SET_NETDEV_DEV(ndev, &pdev->dev);
1831 /* setup board info structure */
1832 fep = netdev_priv(ndev);
1833 memset(fep, 0, sizeof(*fep));
1835 ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
1837 if (!ndev->base_addr) {
1839 goto failed_ioremap;
1842 platform_set_drvdata(pdev, ndev);
1844 /* This device has up to three irqs on some platforms */
1845 for (i = 0; i < 3; i++) {
1846 irq = platform_get_irq(pdev, i);
1849 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1852 irq = platform_get_irq(pdev, i);
1853 free_irq(irq, ndev);
1860 fep->clk = clk_get(&pdev->dev, "fec_clk");
1861 if (IS_ERR(fep->clk)) {
1862 ret = PTR_ERR(fep->clk);
1865 clk_enable(fep->clk);
1867 ret = fec_enet_init(ndev, 0);
1871 ret = register_netdev(ndev);
1873 goto failed_register;
1879 clk_disable(fep->clk);
1882 for (i = 0; i < 3; i++) {
1883 irq = platform_get_irq(pdev, i);
1885 free_irq(irq, ndev);
1888 iounmap((void __iomem *)ndev->base_addr);
1895 static int __devexit
1896 fec_drv_remove(struct platform_device *pdev)
1898 struct net_device *ndev = platform_get_drvdata(pdev);
1899 struct fec_enet_private *fep = netdev_priv(ndev);
1901 platform_set_drvdata(pdev, NULL);
1904 clk_disable(fep->clk);
1906 iounmap((void __iomem *)ndev->base_addr);
1907 unregister_netdev(ndev);
1913 fec_suspend(struct platform_device *dev, pm_message_t state)
1915 struct net_device *ndev = platform_get_drvdata(dev);
1916 struct fec_enet_private *fep;
1919 fep = netdev_priv(ndev);
1920 if (netif_running(ndev)) {
1921 netif_device_detach(ndev);
1929 fec_resume(struct platform_device *dev)
1931 struct net_device *ndev = platform_get_drvdata(dev);
1934 if (netif_running(ndev)) {
1935 fec_enet_init(ndev, 0);
1936 netif_device_attach(ndev);
1942 static struct platform_driver fec_driver = {
1945 .owner = THIS_MODULE,
1948 .remove = __devexit_p(fec_drv_remove),
1949 .suspend = fec_suspend,
1950 .resume = fec_resume,
1954 fec_enet_module_init(void)
1956 printk(KERN_INFO "FEC Ethernet Driver\n");
1958 return platform_driver_register(&fec_driver);
1962 fec_enet_cleanup(void)
1964 platform_driver_unregister(&fec_driver);
1967 module_exit(fec_enet_cleanup);
1968 module_init(fec_enet_module_init);
1970 MODULE_LICENSE("GPL");