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   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include "e1000.h"
  35
  36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  40
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  44
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  48
  49 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  50 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  51
  52 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  53 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  54
  55 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  56 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  57 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  58 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  59 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  60 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  61
  62 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  63 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  64                                                 /* 1=Reverse Auto-Negotiation */
  65
  66 /* MAC Specific Control Register (Page 2, Register 21) */
  67 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  68 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  69 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  70 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  71 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  72
  73 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  74
  75 /* DSP Distance Register (Page 5, Register 26) */
  76 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  77                                                            1 = 50-80M
  78                                                            2 = 80-110M
  79                                                            3 = 110-140M
  80                                                            4 = >140M */
  81
  82 /* Kumeran Mode Control Register (Page 193, Register 16) */
  83 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  84
  85 /* Max number of times Kumeran read/write should be validated */
  86 #define GG82563_MAX_KMRN_RETRY  0x5
  87
  88 /* Power Management Control Register (Page 193, Register 20) */
  89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  90                                            /* 1=Enable SERDES Electrical Idle */
  91
  92 /* In-Band Control Register (Page 194, Register 18) */
  93 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  94
  95 /*
  96  * A table for the GG82563 cable length where the range is defined
  97  * with a lower bound at "index" and the upper bound at
  98  * "index + 5".
  99  */
 100 static const u16 e1000_gg82563_cable_length_table[] =
 101          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 102
 103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 104 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 110 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 111 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 112                                             u16 *data);
 113 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 114                                              u16 data);
 115
 116 /**
 117  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 118  *  @hw: pointer to the HW structure
 119  **/
 120 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 121 {
 122         struct e1000_phy_info *phy = &hw->phy;
 123         s32 ret_val;
 124
 125         if (hw->phy.media_type != e1000_media_type_copper) {
 126                 phy->type       = e1000_phy_none;
 127                 return 0;
 128         }
 129
 130         phy->addr               = 1;
 131         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 132         phy->reset_delay_us      = 100;
 133         phy->type               = e1000_phy_gg82563;
 134
 135         /* This can only be done after all function pointers are setup. */
 136         ret_val = e1000e_get_phy_id(hw);
 137
 138         /* Verify phy id */
 139         if (phy->id != GG82563_E_PHY_ID)
 140                 return -E1000_ERR_PHY;
 141
 142         return ret_val;
 143 }
 144
 145 /**
 146  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 147  *  @hw: pointer to the HW structure
 148  **/
 149 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 150 {
 151         struct e1000_nvm_info *nvm = &hw->nvm;
 152         u32 eecd = er32(EECD);
 153         u16 size;
 154
 155         nvm->opcode_bits        = 8;
 156         nvm->delay_usec  = 1;
 157         switch (nvm->override) {
 158         case e1000_nvm_override_spi_large:
 159                 nvm->page_size    = 32;
 160                 nvm->address_bits = 16;
 161                 break;
 162         case e1000_nvm_override_spi_small:
 163                 nvm->page_size    = 8;
 164                 nvm->address_bits = 8;
 165                 break;
 166         default:
 167                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 168                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 169                 break;
 170         }
 171
 172         nvm->type = e1000_nvm_eeprom_spi;
 173
 174         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 175                           E1000_EECD_SIZE_EX_SHIFT);
 176
 177         /*
 178          * Added to a constant, "size" becomes the left-shift value
 179          * for setting word_size.
 180          */
 181         size += NVM_WORD_SIZE_BASE_SHIFT;
 182
 183         /* EEPROM access above 16k is unsupported */
 184         if (size > 14)
 185                 size = 14;
 186         nvm->word_size  = 1 << size;
 187
 188         return 0;
 189 }
 190
 191 /**
 192  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 193  *  @hw: pointer to the HW structure
 194  **/
 195 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
 196 {
 197         struct e1000_hw *hw = &adapter->hw;
 198         struct e1000_mac_info *mac = &hw->mac;
 199         struct e1000_mac_operations *func = &mac->ops;
 200
 201         /* Set media type */
 202         switch (adapter->pdev->device) {
 203         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 204                 hw->phy.media_type = e1000_media_type_internal_serdes;
 205                 break;
 206         default:
 207                 hw->phy.media_type = e1000_media_type_copper;
 208                 break;
 209         }
 210
 211         /* Set mta register count */
 212         mac->mta_reg_count = 128;
 213         /* Set rar entry count */
 214         mac->rar_entry_count = E1000_RAR_ENTRIES;
 215         /* Set if manageability features are enabled. */
 216         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
 217                         ? true : false;
 218
 219         /* check for link */
 220         switch (hw->phy.media_type) {
 221         case e1000_media_type_copper:
 222                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
 223                 func->check_for_link = e1000e_check_for_copper_link;
 224                 break;
 225         case e1000_media_type_fiber:
 226                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 227                 func->check_for_link = e1000e_check_for_fiber_link;
 228                 break;
 229         case e1000_media_type_internal_serdes:
 230                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 231                 func->check_for_link = e1000e_check_for_serdes_link;
 232                 break;
 233         default:
 234                 return -E1000_ERR_CONFIG;
 235                 break;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 242 {
 243         struct e1000_hw *hw = &adapter->hw;
 244         s32 rc;
 245
 246         rc = e1000_init_mac_params_80003es2lan(adapter);
 247         if (rc)
 248                 return rc;
 249
 250         rc = e1000_init_nvm_params_80003es2lan(hw);
 251         if (rc)
 252                 return rc;
 253
 254         rc = e1000_init_phy_params_80003es2lan(hw);
 255         if (rc)
 256                 return rc;
 257
 258         return 0;
 259 }
 260
 261 /**
 262  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 263  *  @hw: pointer to the HW structure
 264  *
 265  *  A wrapper to acquire access rights to the correct PHY.
 266  **/
 267 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 268 {
 269         u16 mask;
 270
 271         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 272         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 273 }
 274
 275 /**
 276  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 277  *  @hw: pointer to the HW structure
 278  *
 279  *  A wrapper to release access rights to the correct PHY.
 280  **/
 281 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 282 {
 283         u16 mask;
 284
 285         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 286         e1000_release_swfw_sync_80003es2lan(hw, mask);
 287 }
 288
 289 /**
 290  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 291  *  @hw: pointer to the HW structure
 292  *
 293  *  Acquire the semaphore to access the Kumeran interface.
 294  *
 295  **/
 296 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 297 {
 298         u16 mask;
 299
 300         mask = E1000_SWFW_CSR_SM;
 301
 302         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 303 }
 304
 305 /**
 306  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 307  *  @hw: pointer to the HW structure
 308  *
 309  *  Release the semaphore used to access the Kumeran interface
 310  **/
 311 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 312 {
 313         u16 mask;
 314
 315         mask = E1000_SWFW_CSR_SM;
 316
 317         e1000_release_swfw_sync_80003es2lan(hw, mask);
 318 }
 319
 320 /**
 321  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 322  *  @hw: pointer to the HW structure
 323  *
 324  *  Acquire the semaphore to access the EEPROM.
 325  **/
 326 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 327 {
 328         s32 ret_val;
 329
 330         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 331         if (ret_val)
 332                 return ret_val;
 333
 334         ret_val = e1000e_acquire_nvm(hw);
 335
 336         if (ret_val)
 337                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 338
 339         return ret_val;
 340 }
 341
 342 /**
 343  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 344  *  @hw: pointer to the HW structure
 345  *
 346  *  Release the semaphore used to access the EEPROM.
 347  **/
 348 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 349 {
 350         e1000e_release_nvm(hw);
 351         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 352 }
 353
 354 /**
 355  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 356  *  @hw: pointer to the HW structure
 357  *  @mask: specifies which semaphore to acquire
 358  *
 359  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 360  *  will also specify which port we're acquiring the lock for.
 361  **/
 362 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 363 {
 364         u32 swfw_sync;
 365         u32 swmask = mask;
 366         u32 fwmask = mask << 16;
 367         s32 i = 0;
 368         s32 timeout = 50;
 369
 370         while (i < timeout) {
 371                 if (e1000e_get_hw_semaphore(hw))
 372                         return -E1000_ERR_SWFW_SYNC;
 373
 374                 swfw_sync = er32(SW_FW_SYNC);
 375                 if (!(swfw_sync & (fwmask | swmask)))
 376                         break;
 377
 378                 /*
 379                  * Firmware currently using resource (fwmask)
 380                  * or other software thread using resource (swmask)
 381                  */
 382                 e1000e_put_hw_semaphore(hw);
 383                 mdelay(5);
 384                 i++;
 385         }
 386
 387         if (i == timeout) {
 388                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 389                 return -E1000_ERR_SWFW_SYNC;
 390         }
 391
 392         swfw_sync |= swmask;
 393         ew32(SW_FW_SYNC, swfw_sync);
 394
 395         e1000e_put_hw_semaphore(hw);
 396
 397         return 0;
 398 }
 399
 400 /**
 401  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 402  *  @hw: pointer to the HW structure
 403  *  @mask: specifies which semaphore to acquire
 404  *
 405  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 406  *  will also specify which port we're releasing the lock for.
 407  **/
 408 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 409 {
 410         u32 swfw_sync;
 411
 412         while (e1000e_get_hw_semaphore(hw) != 0);
 413         /* Empty */
 414
 415         swfw_sync = er32(SW_FW_SYNC);
 416         swfw_sync &= ~mask;
 417         ew32(SW_FW_SYNC, swfw_sync);
 418
 419         e1000e_put_hw_semaphore(hw);
 420 }
 421
 422 /**
 423  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 424  *  @hw: pointer to the HW structure
 425  *  @offset: offset of the register to read
 426  *  @data: pointer to the data returned from the operation
 427  *
 428  *  Read the GG82563 PHY register.
 429  **/
 430 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 431                                                   u32 offset, u16 *data)
 432 {
 433         s32 ret_val;
 434         u32 page_select;
 435         u16 temp;
 436
 437         ret_val = e1000_acquire_phy_80003es2lan(hw);
 438         if (ret_val)
 439                 return ret_val;
 440
 441         /* Select Configuration Page */
 442         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 443                 page_select = GG82563_PHY_PAGE_SELECT;
 444         } else {
 445                 /*
 446                  * Use Alternative Page Select register to access
 447                  * registers 30 and 31
 448                  */
 449                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 450         }
 451
 452         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 453         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 454         if (ret_val) {
 455                 e1000_release_phy_80003es2lan(hw);
 456                 return ret_val;
 457         }
 458
 459         /*
 460          * The "ready" bit in the MDIC register may be incorrectly set
 461          * before the device has completed the "Page Select" MDI
 462          * transaction.  So we wait 200us after each MDI command...
 463          */
 464         udelay(200);
 465
 466         /* ...and verify the command was successful. */
 467         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 468
 469         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 470                 ret_val = -E1000_ERR_PHY;
 471                 e1000_release_phy_80003es2lan(hw);
 472                 return ret_val;
 473         }
 474
 475         udelay(200);
 476
 477         ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 478                                            data);
 479
 480         udelay(200);
 481         e1000_release_phy_80003es2lan(hw);
 482
 483         return ret_val;
 484 }
 485
 486 /**
 487  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 488  *  @hw: pointer to the HW structure
 489  *  @offset: offset of the register to read
 490  *  @data: value to write to the register
 491  *
 492  *  Write to the GG82563 PHY register.
 493  **/
 494 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 495                                                    u32 offset, u16 data)
 496 {
 497         s32 ret_val;
 498         u32 page_select;
 499         u16 temp;
 500
 501         ret_val = e1000_acquire_phy_80003es2lan(hw);
 502         if (ret_val)
 503                 return ret_val;
 504
 505         /* Select Configuration Page */
 506         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 507                 page_select = GG82563_PHY_PAGE_SELECT;
 508         } else {
 509                 /*
 510                  * Use Alternative Page Select register to access
 511                  * registers 30 and 31
 512                  */
 513                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 514         }
 515
 516         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 517         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 518         if (ret_val) {
 519                 e1000_release_phy_80003es2lan(hw);
 520                 return ret_val;
 521         }
 522
 523
 524         /*
 525          * The "ready" bit in the MDIC register may be incorrectly set
 526          * before the device has completed the "Page Select" MDI
 527          * transaction.  So we wait 200us after each MDI command...
 528          */
 529         udelay(200);
 530
 531         /* ...and verify the command was successful. */
 532         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 533
 534         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 535                 e1000_release_phy_80003es2lan(hw);
 536                 return -E1000_ERR_PHY;
 537         }
 538
 539         udelay(200);
 540
 541         ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 542                                             data);
 543
 544         udelay(200);
 545         e1000_release_phy_80003es2lan(hw);
 546
 547         return ret_val;
 548 }
 549
 550 /**
 551  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 552  *  @hw: pointer to the HW structure
 553  *  @offset: offset of the register to read
 554  *  @words: number of words to write
 555  *  @data: buffer of data to write to the NVM
 556  *
 557  *  Write "words" of data to the ESB2 NVM.
 558  **/
 559 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 560                                        u16 words, u16 *data)
 561 {
 562         return e1000e_write_nvm_spi(hw, offset, words, data);
 563 }
 564
 565 /**
 566  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 567  *  @hw: pointer to the HW structure
 568  *
 569  *  Wait a specific amount of time for manageability processes to complete.
 570  *  This is a function pointer entry point called by the phy module.
 571  **/
 572 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 573 {
 574         s32 timeout = PHY_CFG_TIMEOUT;
 575         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 576
 577         if (hw->bus.func == 1)
 578                 mask = E1000_NVM_CFG_DONE_PORT_1;
 579
 580         while (timeout) {
 581                 if (er32(EEMNGCTL) & mask)
 582                         break;
 583                 msleep(1);
 584                 timeout--;
 585         }
 586         if (!timeout) {
 587                 e_dbg("MNG configuration cycle has not completed.\n");
 588                 return -E1000_ERR_RESET;
 589         }
 590
 591         return 0;
 592 }
 593
 594 /**
 595  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 596  *  @hw: pointer to the HW structure
 597  *
 598  *  Force the speed and duplex settings onto the PHY.  This is a
 599  *  function pointer entry point called by the phy module.
 600  **/
 601 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 602 {
 603         s32 ret_val;
 604         u16 phy_data;
 605         bool link;
 606
 607         /*
 608          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 609          * forced whenever speed and duplex are forced.
 610          */
 611         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 612         if (ret_val)
 613                 return ret_val;
 614
 615         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 616         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 617         if (ret_val)
 618                 return ret_val;
 619
 620         e_dbg("GG82563 PSCR: %X\n", phy_data);
 621
 622         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 623         if (ret_val)
 624                 return ret_val;
 625
 626         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 627
 628         /* Reset the phy to commit changes. */
 629         phy_data |= MII_CR_RESET;
 630
 631         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 632         if (ret_val)
 633                 return ret_val;
 634
 635         udelay(1);
 636
 637         if (hw->phy.autoneg_wait_to_complete) {
 638                 e_dbg("Waiting for forced speed/duplex link "
 639                          "on GG82563 phy.\n");
 640
 641                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 642                                                      100000, &link);
 643                 if (ret_val)
 644                         return ret_val;
 645
 646                 if (!link) {
 647                         /*
 648                          * We didn't get link.
 649                          * Reset the DSP and cross our fingers.
 650                          */
 651                         ret_val = e1000e_phy_reset_dsp(hw);
 652                         if (ret_val)
 653                                 return ret_val;
 654                 }
 655
 656                 /* Try once more */
 657                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 658                                                      100000, &link);
 659                 if (ret_val)
 660                         return ret_val;
 661         }
 662
 663         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 664         if (ret_val)
 665                 return ret_val;
 666
 667         /*
 668          * Resetting the phy means we need to verify the TX_CLK corresponds
 669          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 670          */
 671         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 672         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 673                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 674         else
 675                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 676
 677         /*
 678          * In addition, we must re-enable CRS on Tx for both half and full
 679          * duplex.
 680          */
 681         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 682         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 683
 684         return ret_val;
 685 }
 686
 687 /**
 688  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 689  *  @hw: pointer to the HW structure
 690  *
 691  *  Find the approximate cable length as measured by the GG82563 PHY.
 692  *  This is a function pointer entry point called by the phy module.
 693  **/
 694 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 695 {
 696         struct e1000_phy_info *phy = &hw->phy;
 697         s32 ret_val;
 698         u16 phy_data;
 699         u16 index;
 700
 701         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 702         if (ret_val)
 703                 return ret_val;
 704
 705         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 706         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 707         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
 708
 709         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 710
 711         return 0;
 712 }
 713
 714 /**
 715  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 716  *  @hw: pointer to the HW structure
 717  *  @speed: pointer to speed buffer
 718  *  @duplex: pointer to duplex buffer
 719  *
 720  *  Retrieve the current speed and duplex configuration.
 721  **/
 722 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 723                                               u16 *duplex)
 724 {
 725         s32 ret_val;
 726
 727         if (hw->phy.media_type == e1000_media_type_copper) {
 728                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 729                                                                     speed,
 730                                                                     duplex);
 731                 hw->phy.ops.cfg_on_link_up(hw);
 732         } else {
 733                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 734                                                                   speed,
 735                                                                   duplex);
 736         }
 737
 738         return ret_val;
 739 }
 740
 741 /**
 742  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 743  *  @hw: pointer to the HW structure
 744  *
 745  *  Perform a global reset to the ESB2 controller.
 746  **/
 747 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 748 {
 749         u32 ctrl;
 750         u32 icr;
 751         s32 ret_val;
 752
 753         /*
 754          * Prevent the PCI-E bus from sticking if there is no TLP connection
 755          * on the last TLP read/write transaction when MAC is reset.
 756          */
 757         ret_val = e1000e_disable_pcie_master(hw);
 758         if (ret_val)
 759                 e_dbg("PCI-E Master disable polling has failed.\n");
 760
 761         e_dbg("Masking off all interrupts\n");
 762         ew32(IMC, 0xffffffff);
 763
 764         ew32(RCTL, 0);
 765         ew32(TCTL, E1000_TCTL_PSP);
 766         e1e_flush();
 767
 768         msleep(10);
 769
 770         ctrl = er32(CTRL);
 771
 772         ret_val = e1000_acquire_phy_80003es2lan(hw);
 773         e_dbg("Issuing a global reset to MAC\n");
 774         ew32(CTRL, ctrl | E1000_CTRL_RST);
 775         e1000_release_phy_80003es2lan(hw);
 776
 777         ret_val = e1000e_get_auto_rd_done(hw);
 778         if (ret_val)
 779                 /* We don't want to continue accessing MAC registers. */
 780                 return ret_val;
 781
 782         /* Clear any pending interrupt events. */
 783         ew32(IMC, 0xffffffff);
 784         icr = er32(ICR);
 785
 786         return 0;
 787 }
 788
 789 /**
 790  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 791  *  @hw: pointer to the HW structure
 792  *
 793  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 794  **/
 795 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 796 {
 797         struct e1000_mac_info *mac = &hw->mac;
 798         u32 reg_data;
 799         s32 ret_val;
 800         u16 i;
 801
 802         e1000_initialize_hw_bits_80003es2lan(hw);
 803
 804         /* Initialize identification LED */
 805         ret_val = e1000e_id_led_init(hw);
 806         if (ret_val) {
 807                 e_dbg("Error initializing identification LED\n");
 808                 return ret_val;
 809         }
 810
 811         /* Disabling VLAN filtering */
 812         e_dbg("Initializing the IEEE VLAN\n");
 813         e1000e_clear_vfta(hw);
 814
 815         /* Setup the receive address. */
 816         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 817
 818         /* Zero out the Multicast HASH table */
 819         e_dbg("Zeroing the MTA\n");
 820         for (i = 0; i < mac->mta_reg_count; i++)
 821                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 822
 823         /* Setup link and flow control */
 824         ret_val = e1000e_setup_link(hw);
 825
 826         /* Set the transmit descriptor write-back policy */
 827         reg_data = er32(TXDCTL(0));
 828         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 829                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 830         ew32(TXDCTL(0), reg_data);
 831
 832         /* ...for both queues. */
 833         reg_data = er32(TXDCTL(1));
 834         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 835                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 836         ew32(TXDCTL(1), reg_data);
 837
 838         /* Enable retransmit on late collisions */
 839         reg_data = er32(TCTL);
 840         reg_data |= E1000_TCTL_RTLC;
 841         ew32(TCTL, reg_data);
 842
 843         /* Configure Gigabit Carry Extend Padding */
 844         reg_data = er32(TCTL_EXT);
 845         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 846         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 847         ew32(TCTL_EXT, reg_data);
 848
 849         /* Configure Transmit Inter-Packet Gap */
 850         reg_data = er32(TIPG);
 851         reg_data &= ~E1000_TIPG_IPGT_MASK;
 852         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 853         ew32(TIPG, reg_data);
 854
 855         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 856         reg_data &= ~0x00100000;
 857         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 858
 859         /*
 860          * Clear all of the statistics registers (clear on read).  It is
 861          * important that we do this after we have tried to establish link
 862          * because the symbol error count will increment wildly if there
 863          * is no link.
 864          */
 865         e1000_clear_hw_cntrs_80003es2lan(hw);
 866
 867         return ret_val;
 868 }
 869
 870 /**
 871  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 872  *  @hw: pointer to the HW structure
 873  *
 874  *  Initializes required hardware-dependent bits needed for normal operation.
 875  **/
 876 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 877 {
 878         u32 reg;
 879
 880         /* Transmit Descriptor Control 0 */
 881         reg = er32(TXDCTL(0));
 882         reg |= (1 << 22);
 883         ew32(TXDCTL(0), reg);
 884
 885         /* Transmit Descriptor Control 1 */
 886         reg = er32(TXDCTL(1));
 887         reg |= (1 << 22);
 888         ew32(TXDCTL(1), reg);
 889
 890         /* Transmit Arbitration Control 0 */
 891         reg = er32(TARC(0));
 892         reg &= ~(0xF << 27); /* 30:27 */
 893         if (hw->phy.media_type != e1000_media_type_copper)
 894                 reg &= ~(1 << 20);
 895         ew32(TARC(0), reg);
 896
 897         /* Transmit Arbitration Control 1 */
 898         reg = er32(TARC(1));
 899         if (er32(TCTL) & E1000_TCTL_MULR)
 900                 reg &= ~(1 << 28);
 901         else
 902                 reg |= (1 << 28);
 903         ew32(TARC(1), reg);
 904 }
 905
 906 /**
 907  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 908  *  @hw: pointer to the HW structure
 909  *
 910  *  Setup some GG82563 PHY registers for obtaining link
 911  **/
 912 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 913 {
 914         struct e1000_phy_info *phy = &hw->phy;
 915         s32 ret_val;
 916         u32 ctrl_ext;
 917         u16 data;
 918
 919         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 920         if (ret_val)
 921                 return ret_val;
 922
 923         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 924         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 925         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 926
 927         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 928         if (ret_val)
 929                 return ret_val;
 930
 931         /*
 932          * Options:
 933          *   MDI/MDI-X = 0 (default)
 934          *   0 - Auto for all speeds
 935          *   1 - MDI mode
 936          *   2 - MDI-X mode
 937          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 938          */
 939         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 940         if (ret_val)
 941                 return ret_val;
 942
 943         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 944
 945         switch (phy->mdix) {
 946         case 1:
 947                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 948                 break;
 949         case 2:
 950                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 951                 break;
 952         case 0:
 953         default:
 954                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 955                 break;
 956         }
 957
 958         /*
 959          * Options:
 960          *   disable_polarity_correction = 0 (default)
 961          *       Automatic Correction for Reversed Cable Polarity
 962          *   0 - Disabled
 963          *   1 - Enabled
 964          */
 965         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 966         if (phy->disable_polarity_correction)
 967                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 968
 969         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 970         if (ret_val)
 971                 return ret_val;
 972
 973         /* SW Reset the PHY so all changes take effect */
 974         ret_val = e1000e_commit_phy(hw);
 975         if (ret_val) {
 976                 e_dbg("Error Resetting the PHY\n");
 977                 return ret_val;
 978         }
 979
 980         /* Bypass Rx and Tx FIFO's */
 981         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
 982                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
 983                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 984                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 985         if (ret_val)
 986                 return ret_val;
 987
 988         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
 989                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
 990                                        &data);
 991         if (ret_val)
 992                 return ret_val;
 993         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 994         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
 995                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
 996                                         data);
 997         if (ret_val)
 998                 return ret_val;
 999
1000         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1001         if (ret_val)
1002                 return ret_val;
1003
1004         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1005         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1006         if (ret_val)
1007                 return ret_val;
1008
1009         ctrl_ext = er32(CTRL_EXT);
1010         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1011         ew32(CTRL_EXT, ctrl_ext);
1012
1013         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1014         if (ret_val)
1015                 return ret_val;
1016
1017         /*
1018          * Do not init these registers when the HW is in IAMT mode, since the
1019          * firmware will have already initialized them.  We only initialize
1020          * them if the HW is not in IAMT mode.
1021          */
1022         if (!e1000e_check_mng_mode(hw)) {
1023                 /* Enable Electrical Idle on the PHY */
1024                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1025                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1026                 if (ret_val)
1027                         return ret_val;
1028
1029                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1030                 if (ret_val)
1031                         return ret_val;
1032
1033                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1034                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1035                 if (ret_val)
1036                         return ret_val;
1037         }
1038
1039         /*
1040          * Workaround: Disable padding in Kumeran interface in the MAC
1041          * and in the PHY to avoid CRC errors.
1042          */
1043         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1044         if (ret_val)
1045                 return ret_val;
1046
1047         data |= GG82563_ICR_DIS_PADDING;
1048         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1049         if (ret_val)
1050                 return ret_val;
1051
1052         return 0;
1053 }
1054
1055 /**
1056  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1057  *  @hw: pointer to the HW structure
1058  *
1059  *  Essentially a wrapper for setting up all things "copper" related.
1060  *  This is a function pointer entry point called by the mac module.
1061  **/
1062 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1063 {
1064         u32 ctrl;
1065         s32 ret_val;
1066         u16 reg_data;
1067
1068         ctrl = er32(CTRL);
1069         ctrl |= E1000_CTRL_SLU;
1070         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1071         ew32(CTRL, ctrl);
1072
1073         /*
1074          * Set the mac to wait the maximum time between each
1075          * iteration and increase the max iterations when
1076          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1077          */
1078         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1079                                                    0xFFFF);
1080         if (ret_val)
1081                 return ret_val;
1082         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1083                                                   &reg_data);
1084         if (ret_val)
1085                 return ret_val;
1086         reg_data |= 0x3F;
1087         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1088                                                    reg_data);
1089         if (ret_val)
1090                 return ret_val;
1091         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1092                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1093                                       &reg_data);
1094         if (ret_val)
1095                 return ret_val;
1096         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1097         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1098                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1099                                         reg_data);
1100         if (ret_val)
1101                 return ret_val;
1102
1103         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1104         if (ret_val)
1105                 return ret_val;
1106
1107         ret_val = e1000e_setup_copper_link(hw);
1108
1109         return 0;
1110 }
1111
1112 /**
1113  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1114  *  @hw: pointer to the HW structure
1115  *  @duplex: current duplex setting
1116  *
1117  *  Configure the KMRN interface by applying last minute quirks for
1118  *  10/100 operation.
1119  **/
1120 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1121 {
1122         s32 ret_val = 0;
1123         u16 speed;
1124         u16 duplex;
1125
1126         if (hw->phy.media_type == e1000_media_type_copper) {
1127                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1128                                                              &duplex);
1129                 if (ret_val)
1130                         return ret_val;
1131
1132                 if (speed == SPEED_1000)
1133                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1134                 else
1135                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1136         }
1137
1138         return ret_val;
1139 }
1140
1141 /**
1142  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1143  *  @hw: pointer to the HW structure
1144  *  @duplex: current duplex setting
1145  *
1146  *  Configure the KMRN interface by applying last minute quirks for
1147  *  10/100 operation.
1148  **/
1149 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1150 {
1151         s32 ret_val;
1152         u32 tipg;
1153         u32 i = 0;
1154         u16 reg_data, reg_data2;
1155
1156         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1157         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1158                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1159                                        reg_data);
1160         if (ret_val)
1161                 return ret_val;
1162
1163         /* Configure Transmit Inter-Packet Gap */
1164         tipg = er32(TIPG);
1165         tipg &= ~E1000_TIPG_IPGT_MASK;
1166         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1167         ew32(TIPG, tipg);
1168
1169         do {
1170                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1171                 if (ret_val)
1172                         return ret_val;
1173
1174                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1175                 if (ret_val)
1176                         return ret_val;
1177                 i++;
1178         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1179
1180         if (duplex == HALF_DUPLEX)
1181                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1182         else
1183                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1184
1185         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1186
1187         return 0;
1188 }
1189
1190 /**
1191  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1192  *  @hw: pointer to the HW structure
1193  *
1194  *  Configure the KMRN interface by applying last minute quirks for
1195  *  gigabit operation.
1196  **/
1197 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1198 {
1199         s32 ret_val;
1200         u16 reg_data, reg_data2;
1201         u32 tipg;
1202         u32 i = 0;
1203
1204         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1205         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1206                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1207                                        reg_data);
1208         if (ret_val)
1209                 return ret_val;
1210
1211         /* Configure Transmit Inter-Packet Gap */
1212         tipg = er32(TIPG);
1213         tipg &= ~E1000_TIPG_IPGT_MASK;
1214         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1215         ew32(TIPG, tipg);
1216
1217         do {
1218                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1219                 if (ret_val)
1220                         return ret_val;
1221
1222                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1223                 if (ret_val)
1224                         return ret_val;
1225                 i++;
1226         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1227
1228         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1229         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1230
1231         return ret_val;
1232 }
1233
1234 /**
1235  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1236  *  @hw: pointer to the HW structure
1237  *  @offset: register offset to be read
1238  *  @data: pointer to the read data
1239  *
1240  *  Acquire semaphore, then read the PHY register at offset
1241  *  using the kumeran interface.  The information retrieved is stored in data.
1242  *  Release the semaphore before exiting.
1243  **/
1244 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1245                                            u16 *data)
1246 {
1247         u32 kmrnctrlsta;
1248         s32 ret_val = 0;
1249
1250         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1251         if (ret_val)
1252                 return ret_val;
1253
1254         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1255                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1256         ew32(KMRNCTRLSTA, kmrnctrlsta);
1257
1258         udelay(2);
1259
1260         kmrnctrlsta = er32(KMRNCTRLSTA);
1261         *data = (u16)kmrnctrlsta;
1262
1263         e1000_release_mac_csr_80003es2lan(hw);
1264
1265         return ret_val;
1266 }
1267
1268 /**
1269  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1270  *  @hw: pointer to the HW structure
1271  *  @offset: register offset to write to
1272  *  @data: data to write at register offset
1273  *
1274  *  Acquire semaphore, then write the data to PHY register
1275  *  at the offset using the kumeran interface.  Release semaphore
1276  *  before exiting.
1277  **/
1278 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1279                                             u16 data)
1280 {
1281         u32 kmrnctrlsta;
1282         s32 ret_val = 0;
1283
1284         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1285         if (ret_val)
1286                 return ret_val;
1287
1288         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1289                        E1000_KMRNCTRLSTA_OFFSET) | data;
1290         ew32(KMRNCTRLSTA, kmrnctrlsta);
1291
1292         udelay(2);
1293
1294         e1000_release_mac_csr_80003es2lan(hw);
1295
1296         return ret_val;
1297 }
1298
1299 /**
1300  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1301  *  @hw: pointer to the HW structure
1302  *
1303  *  Clears the hardware counters by reading the counter registers.
1304  **/
1305 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1306 {
1307         u32 temp;
1308
1309         e1000e_clear_hw_cntrs_base(hw);
1310
1311         temp = er32(PRC64);
1312         temp = er32(PRC127);
1313         temp = er32(PRC255);
1314         temp = er32(PRC511);
1315         temp = er32(PRC1023);
1316         temp = er32(PRC1522);
1317         temp = er32(PTC64);
1318         temp = er32(PTC127);
1319         temp = er32(PTC255);
1320         temp = er32(PTC511);
1321         temp = er32(PTC1023);
1322         temp = er32(PTC1522);
1323
1324         temp = er32(ALGNERRC);
1325         temp = er32(RXERRC);
1326         temp = er32(TNCRS);
1327         temp = er32(CEXTERR);
1328         temp = er32(TSCTC);
1329         temp = er32(TSCTFC);
1330
1331         temp = er32(MGTPRC);
1332         temp = er32(MGTPDC);
1333         temp = er32(MGTPTC);
1334
1335         temp = er32(IAC);
1336         temp = er32(ICRXOC);
1337
1338         temp = er32(ICRXPTC);
1339         temp = er32(ICRXATC);
1340         temp = er32(ICTXPTC);
1341         temp = er32(ICTXATC);
1342         temp = er32(ICTXQEC);
1343         temp = er32(ICTXQMTC);
1344         temp = er32(ICRXDMTC);
1345 }
1346
1347 static struct e1000_mac_operations es2_mac_ops = {
1348         .id_led_init            = e1000e_id_led_init,
1349         .check_mng_mode         = e1000e_check_mng_mode_generic,
1350         /* check_for_link dependent on media type */
1351         .cleanup_led            = e1000e_cleanup_led_generic,
1352         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1353         .get_bus_info           = e1000e_get_bus_info_pcie,
1354         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1355         .led_on                 = e1000e_led_on_generic,
1356         .led_off                = e1000e_led_off_generic,
1357         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1358         .reset_hw               = e1000_reset_hw_80003es2lan,
1359         .init_hw                = e1000_init_hw_80003es2lan,
1360         .setup_link             = e1000e_setup_link,
1361         /* setup_physical_interface dependent on media type */
1362         .setup_led              = e1000e_setup_led_generic,
1363 };
1364
1365 static struct e1000_phy_operations es2_phy_ops = {
1366         .acquire                = e1000_acquire_phy_80003es2lan,
1367         .check_reset_block      = e1000e_check_reset_block_generic,
1368         .commit                 = e1000e_phy_sw_reset,
1369         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1370         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1371         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1372         .get_info               = e1000e_get_phy_info_m88,
1373         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1374         .release                = e1000_release_phy_80003es2lan,
1375         .reset                  = e1000e_phy_hw_reset_generic,
1376         .set_d0_lplu_state      = NULL,
1377         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1378         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1379         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1380 };
1381
1382 static struct e1000_nvm_operations es2_nvm_ops = {
1383         .acquire                = e1000_acquire_nvm_80003es2lan,
1384         .read                   = e1000e_read_nvm_eerd,
1385         .release                = e1000_release_nvm_80003es2lan,
1386         .update                 = e1000e_update_nvm_checksum_generic,
1387         .valid_led_default      = e1000e_valid_led_default,
1388         .validate               = e1000e_validate_nvm_checksum_generic,
1389         .write                  = e1000_write_nvm_80003es2lan,
1390 };
1391
1392 struct e1000_info e1000_es2_info = {
1393         .mac                    = e1000_80003es2lan,
1394         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1395                                   | FLAG_HAS_JUMBO_FRAMES
1396                                   | FLAG_HAS_WOL
1397                                   | FLAG_APME_IN_CTRL3
1398                                   | FLAG_RX_CSUM_ENABLED
1399                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1400                                   | FLAG_RX_NEEDS_RESTART /* errata */
1401                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1402                                   | FLAG_APME_CHECK_PORT_B
1403                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1404                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1405         .pba                    = 38,
1406         .max_hw_frame_size      = DEFAULT_JUMBO,
1407         .get_variants           = e1000_get_variants_80003es2lan,
1408         .mac_ops                = &es2_mac_ops,
1409         .phy_ops                = &es2_phy_ops,
1410         .nvm_ops                = &es2_nvm_ops,
1411 };
1412