1 /*******************************************************************************
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * e100.c: Intel(R) PRO/100 ethernet driver
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
55 * II. Driver Operation
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
150 #include <linux/module.h>
151 #include <linux/moduleparam.h>
152 #include <linux/kernel.h>
153 #include <linux/types.h>
154 #include <linux/slab.h>
155 #include <linux/delay.h>
156 #include <linux/init.h>
157 #include <linux/pci.h>
158 #include <linux/dma-mapping.h>
159 #include <linux/netdevice.h>
160 #include <linux/etherdevice.h>
161 #include <linux/mii.h>
162 #include <linux/if_vlan.h>
163 #include <linux/skbuff.h>
164 #include <linux/ethtool.h>
165 #include <linux/string.h>
166 #include <linux/firmware.h>
167 #include <asm/unaligned.h>
170 #define DRV_NAME "e100"
171 #define DRV_EXT "-NAPI"
172 #define DRV_VERSION "3.5.24-k2"DRV_EXT
173 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
174 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
175 #define PFX DRV_NAME ": "
177 #define E100_WATCHDOG_PERIOD (2 * HZ)
178 #define E100_NAPI_WEIGHT 16
180 #define FIRMWARE_D101M "e100/d101m_ucode.bin"
181 #define FIRMWARE_D101S "e100/d101s_ucode.bin"
182 #define FIRMWARE_D102E "e100/d102e_ucode.bin"
184 MODULE_DESCRIPTION(DRV_DESCRIPTION);
185 MODULE_AUTHOR(DRV_COPYRIGHT);
186 MODULE_LICENSE("GPL");
187 MODULE_VERSION(DRV_VERSION);
188 MODULE_FIRMWARE(FIRMWARE_D101M);
189 MODULE_FIRMWARE(FIRMWARE_D101S);
190 MODULE_FIRMWARE(FIRMWARE_D102E);
192 static int debug = 3;
193 static int eeprom_bad_csum_allow = 0;
194 static int use_io = 0;
195 module_param(debug, int, 0);
196 module_param(eeprom_bad_csum_allow, int, 0);
197 module_param(use_io, int, 0);
198 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
199 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
200 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
201 #define DPRINTK(nlevel, klevel, fmt, args...) \
202 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
203 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
206 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
207 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
208 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
209 static struct pci_device_id e100_id_table[] = {
210 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
211 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
213 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
218 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
224 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
232 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
233 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
241 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
247 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
248 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
249 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
250 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
254 MODULE_DEVICE_TABLE(pci, e100_id_table);
257 mac_82557_D100_A = 0,
258 mac_82557_D100_B = 1,
259 mac_82557_D100_C = 2,
260 mac_82558_D101_A4 = 4,
261 mac_82558_D101_B0 = 5,
265 mac_82550_D102_C = 13,
273 phy_100a = 0x000003E0,
274 phy_100c = 0x035002A8,
275 phy_82555_tx = 0x015002A8,
276 phy_nsc_tx = 0x5C002000,
277 phy_82562_et = 0x033002A8,
278 phy_82562_em = 0x032002A8,
279 phy_82562_ek = 0x031002A8,
280 phy_82562_eh = 0x017002A8,
281 phy_82552_v = 0xd061004d,
282 phy_unknown = 0xFFFFFFFF,
285 /* CSR (Control/Status Registers) */
311 RU_UNINITIALIZED = -1,
315 stat_ack_not_ours = 0x00,
316 stat_ack_sw_gen = 0x04,
318 stat_ack_cu_idle = 0x20,
319 stat_ack_frame_rx = 0x40,
320 stat_ack_cu_cmd_done = 0x80,
321 stat_ack_not_present = 0xFF,
322 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
323 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
327 irq_mask_none = 0x00,
335 ruc_load_base = 0x06,
338 cuc_dump_addr = 0x40,
339 cuc_dump_stats = 0x50,
340 cuc_load_base = 0x60,
341 cuc_dump_reset = 0x70,
345 cuc_dump_complete = 0x0000A005,
346 cuc_dump_reset_complete = 0x0000A007,
350 software_reset = 0x0000,
352 selective_reset = 0x0002,
355 enum eeprom_ctrl_lo {
363 mdi_write = 0x04000000,
364 mdi_read = 0x08000000,
365 mdi_ready = 0x10000000,
375 enum eeprom_offsets {
376 eeprom_cnfg_mdix = 0x03,
377 eeprom_phy_iface = 0x06,
379 eeprom_config_asf = 0x0D,
380 eeprom_smbus_addr = 0x90,
383 enum eeprom_cnfg_mdix {
384 eeprom_mdix_enabled = 0x0080,
387 enum eeprom_phy_iface {
400 eeprom_id_wol = 0x0020,
403 enum eeprom_config_asf {
409 cb_complete = 0x8000,
438 struct rx *next, *prev;
443 #if defined(__BIG_ENDIAN_BITFIELD)
449 /*0*/ u8 X(byte_count:6, pad0:2);
450 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
451 /*2*/ u8 adaptive_ifs;
452 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
453 term_write_cache_line:1), pad3:4);
454 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
455 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
456 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
457 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
458 rx_discard_overruns:1), rx_save_bad_frames:1);
459 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
460 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
462 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
463 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
464 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
465 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
467 /*11*/ u8 X(linear_priority:3, pad11:5);
468 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
469 /*13*/ u8 ip_addr_lo;
470 /*14*/ u8 ip_addr_hi;
471 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
472 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
473 pad15_2:1), crs_or_cdt:1);
474 /*16*/ u8 fc_delay_lo;
475 /*17*/ u8 fc_delay_hi;
476 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
477 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
478 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
479 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
480 full_duplex_force:1), full_duplex_pin:1);
481 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
482 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
483 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
487 #define E100_MAX_MULTICAST_ADDRS 64
490 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
493 /* Important: keep total struct u32-aligned */
494 #define UCODE_SIZE 134
501 __le32 ucode[UCODE_SIZE];
502 struct config config;
515 __le32 dump_buffer_addr;
517 struct cb *next, *prev;
523 lb_none = 0, lb_mac = 1, lb_phy = 3,
527 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
528 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
529 tx_multiple_collisions, tx_total_collisions;
530 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
531 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
532 rx_short_frame_errors;
533 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
534 __le16 xmt_tco_frames, rcv_tco_frames;
554 struct param_range rfds;
555 struct param_range cbs;
559 /* Begin: frequently used values: keep adjacent for cache effect */
560 u32 msg_enable ____cacheline_aligned;
561 struct net_device *netdev;
562 struct pci_dev *pdev;
563 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
565 struct rx *rxs ____cacheline_aligned;
566 struct rx *rx_to_use;
567 struct rx *rx_to_clean;
568 struct rfd blank_rfd;
569 enum ru_state ru_running;
571 spinlock_t cb_lock ____cacheline_aligned;
573 struct csr __iomem *csr;
574 enum scb_cmd_lo cuc_cmd;
575 unsigned int cbs_avail;
576 struct napi_struct napi;
578 struct cb *cb_to_use;
579 struct cb *cb_to_send;
580 struct cb *cb_to_clean;
582 /* End: frequently used values: keep adjacent for cache effect */
586 promiscuous = (1 << 1),
587 multicast_all = (1 << 2),
588 wol_magic = (1 << 3),
589 ich_10h_workaround = (1 << 4),
590 } flags ____cacheline_aligned;
594 struct params params;
595 struct timer_list watchdog;
596 struct timer_list blink_timer;
597 struct mii_if_info mii;
598 struct work_struct tx_timeout_task;
599 enum loopback loopback;
604 dma_addr_t cbs_dma_addr;
610 u32 tx_single_collisions;
611 u32 tx_multiple_collisions;
616 u32 rx_fc_unsupported;
618 u32 rx_over_length_errors;
623 spinlock_t mdio_lock;
626 static inline void e100_write_flush(struct nic *nic)
628 /* Flush previous PCI writes through intermediate bridges
629 * by doing a benign read */
630 (void)ioread8(&nic->csr->scb.status);
633 static void e100_enable_irq(struct nic *nic)
637 spin_lock_irqsave(&nic->cmd_lock, flags);
638 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
639 e100_write_flush(nic);
640 spin_unlock_irqrestore(&nic->cmd_lock, flags);
643 static void e100_disable_irq(struct nic *nic)
647 spin_lock_irqsave(&nic->cmd_lock, flags);
648 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
649 e100_write_flush(nic);
650 spin_unlock_irqrestore(&nic->cmd_lock, flags);
653 static void e100_hw_reset(struct nic *nic)
655 /* Put CU and RU into idle with a selective reset to get
656 * device off of PCI bus */
657 iowrite32(selective_reset, &nic->csr->port);
658 e100_write_flush(nic); udelay(20);
660 /* Now fully reset device */
661 iowrite32(software_reset, &nic->csr->port);
662 e100_write_flush(nic); udelay(20);
664 /* Mask off our interrupt line - it's unmasked after reset */
665 e100_disable_irq(nic);
668 static int e100_self_test(struct nic *nic)
670 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
672 /* Passing the self-test is a pretty good indication
673 * that the device can DMA to/from host memory */
675 nic->mem->selftest.signature = 0;
676 nic->mem->selftest.result = 0xFFFFFFFF;
678 iowrite32(selftest | dma_addr, &nic->csr->port);
679 e100_write_flush(nic);
680 /* Wait 10 msec for self-test to complete */
683 /* Interrupts are enabled after self-test */
684 e100_disable_irq(nic);
686 /* Check results of self-test */
687 if (nic->mem->selftest.result != 0) {
688 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
689 nic->mem->selftest.result);
692 if (nic->mem->selftest.signature == 0) {
693 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
700 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
702 u32 cmd_addr_data[3];
706 /* Three cmds: write/erase enable, write data, write/erase disable */
707 cmd_addr_data[0] = op_ewen << (addr_len - 2);
708 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
710 cmd_addr_data[2] = op_ewds << (addr_len - 2);
712 /* Bit-bang cmds to write word to eeprom */
713 for (j = 0; j < 3; j++) {
716 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
717 e100_write_flush(nic); udelay(4);
719 for (i = 31; i >= 0; i--) {
720 ctrl = (cmd_addr_data[j] & (1 << i)) ?
722 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
723 e100_write_flush(nic); udelay(4);
725 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
726 e100_write_flush(nic); udelay(4);
728 /* Wait 10 msec for cmd to complete */
732 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
733 e100_write_flush(nic); udelay(4);
737 /* General technique stolen from the eepro100 driver - very clever */
738 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
745 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
748 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
749 e100_write_flush(nic); udelay(4);
751 /* Bit-bang to read word from eeprom */
752 for (i = 31; i >= 0; i--) {
753 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
754 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
755 e100_write_flush(nic); udelay(4);
757 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
758 e100_write_flush(nic); udelay(4);
760 /* Eeprom drives a dummy zero to EEDO after receiving
761 * complete address. Use this to adjust addr_len. */
762 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
763 if (!(ctrl & eedo) && i > 16) {
764 *addr_len -= (i - 16);
768 data = (data << 1) | (ctrl & eedo ? 1 : 0);
772 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
773 e100_write_flush(nic); udelay(4);
775 return cpu_to_le16(data);
778 /* Load entire EEPROM image into driver cache and validate checksum */
779 static int e100_eeprom_load(struct nic *nic)
781 u16 addr, addr_len = 8, checksum = 0;
783 /* Try reading with an 8-bit addr len to discover actual addr len */
784 e100_eeprom_read(nic, &addr_len, 0);
785 nic->eeprom_wc = 1 << addr_len;
787 for (addr = 0; addr < nic->eeprom_wc; addr++) {
788 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
789 if (addr < nic->eeprom_wc - 1)
790 checksum += le16_to_cpu(nic->eeprom[addr]);
793 /* The checksum, stored in the last word, is calculated such that
794 * the sum of words should be 0xBABA */
795 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
796 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
797 if (!eeprom_bad_csum_allow)
804 /* Save (portion of) driver EEPROM cache to device and update checksum */
805 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
807 u16 addr, addr_len = 8, checksum = 0;
809 /* Try reading with an 8-bit addr len to discover actual addr len */
810 e100_eeprom_read(nic, &addr_len, 0);
811 nic->eeprom_wc = 1 << addr_len;
813 if (start + count >= nic->eeprom_wc)
816 for (addr = start; addr < start + count; addr++)
817 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
819 /* The checksum, stored in the last word, is calculated such that
820 * the sum of words should be 0xBABA */
821 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
822 checksum += le16_to_cpu(nic->eeprom[addr]);
823 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
824 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
825 nic->eeprom[nic->eeprom_wc - 1]);
830 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
831 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
832 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
838 spin_lock_irqsave(&nic->cmd_lock, flags);
840 /* Previous command is accepted when SCB clears */
841 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
842 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
845 if (unlikely(i > E100_WAIT_SCB_FAST))
848 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
853 if (unlikely(cmd != cuc_resume))
854 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
855 iowrite8(cmd, &nic->csr->scb.cmd_lo);
858 spin_unlock_irqrestore(&nic->cmd_lock, flags);
863 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
864 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
870 spin_lock_irqsave(&nic->cb_lock, flags);
872 if (unlikely(!nic->cbs_avail)) {
878 nic->cb_to_use = cb->next;
882 if (unlikely(!nic->cbs_avail))
885 cb_prepare(nic, cb, skb);
887 /* Order is important otherwise we'll be in a race with h/w:
888 * set S-bit in current first, then clear S-bit in previous. */
889 cb->command |= cpu_to_le16(cb_s);
891 cb->prev->command &= cpu_to_le16(~cb_s);
893 while (nic->cb_to_send != nic->cb_to_use) {
894 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
895 nic->cb_to_send->dma_addr))) {
896 /* Ok, here's where things get sticky. It's
897 * possible that we can't schedule the command
898 * because the controller is too busy, so
899 * let's just queue the command and try again
900 * when another command is scheduled. */
901 if (err == -ENOSPC) {
903 schedule_work(&nic->tx_timeout_task);
907 nic->cuc_cmd = cuc_resume;
908 nic->cb_to_send = nic->cb_to_send->next;
913 spin_unlock_irqrestore(&nic->cb_lock, flags);
918 static int mdio_read(struct net_device *netdev, int addr, int reg)
920 struct nic *nic = netdev_priv(netdev);
921 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
924 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
926 struct nic *nic = netdev_priv(netdev);
928 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
931 /* the standard mdio_ctrl() function for usual MII-compliant hardware */
932 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
940 * Stratus87247: we shouldn't be writing the MDI control
941 * register until the Ready bit shows True. Also, since
942 * manipulation of the MDI control registers is a multi-step
943 * procedure it should be done under lock.
945 spin_lock_irqsave(&nic->mdio_lock, flags);
946 for (i = 100; i; --i) {
947 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
952 printk("e100.mdio_ctrl(%s) won't go Ready\n",
954 spin_unlock_irqrestore(&nic->mdio_lock, flags);
955 return 0; /* No way to indicate timeout error */
957 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
959 for (i = 0; i < 100; i++) {
961 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
964 spin_unlock_irqrestore(&nic->mdio_lock, flags);
966 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
967 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
968 return (u16)data_out;
971 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
972 static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
978 if ((reg == MII_BMCR) && (dir == mdi_write)) {
979 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
980 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
984 * Workaround Si issue where sometimes the part will not
985 * autoneg to 100Mbps even when advertised.
987 if (advert & ADVERTISE_100FULL)
988 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
989 else if (advert & ADVERTISE_100HALF)
990 data |= BMCR_SPEED100;
993 return mdio_ctrl_hw(nic, addr, dir, reg, data);
996 /* Fully software-emulated mdio_ctrl() function for cards without
997 * MII-compliant PHYs.
998 * For now, this is mainly geared towards 80c24 support; in case of further
999 * requirements for other types (i82503, ...?) either extend this mechanism
1000 * or split it, whichever is cleaner.
1002 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1008 /* might need to allocate a netdev_priv'ed register array eventually
1009 * to be able to record state changes, but for now
1010 * some fully hardcoded register handling ought to be ok I guess. */
1012 if (dir == mdi_read) {
1015 /* Auto-negotiation, right? */
1016 return BMCR_ANENABLE |
1019 return BMSR_LSTATUS /* for mii_link_ok() */ |
1023 /* 80c24 is a "combo card" PHY, right? */
1024 return ADVERTISE_10HALF |
1028 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1029 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1036 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1037 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1042 static inline int e100_phy_supports_mii(struct nic *nic)
1044 /* for now, just check it by comparing whether we
1045 are using MII software emulation.
1047 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1050 static void e100_get_defaults(struct nic *nic)
1052 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1053 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1055 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1056 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1057 if (nic->mac == mac_unknown)
1058 nic->mac = mac_82557_D100_A;
1060 nic->params.rfds = rfds;
1061 nic->params.cbs = cbs;
1063 /* Quadwords to DMA into FIFO before starting frame transmit */
1064 nic->tx_threshold = 0xE0;
1066 /* no interrupt for every tx completion, delay = 256us if not 557 */
1067 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1068 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1070 /* Template for a freshly allocated RFD */
1071 nic->blank_rfd.command = 0;
1072 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1073 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1076 nic->mii.phy_id_mask = 0x1F;
1077 nic->mii.reg_num_mask = 0x1F;
1078 nic->mii.dev = nic->netdev;
1079 nic->mii.mdio_read = mdio_read;
1080 nic->mii.mdio_write = mdio_write;
1083 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1085 struct config *config = &cb->u.config;
1086 u8 *c = (u8 *)config;
1088 cb->command = cpu_to_le16(cb_config);
1090 memset(config, 0, sizeof(struct config));
1092 config->byte_count = 0x16; /* bytes in this struct */
1093 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1094 config->direct_rx_dma = 0x1; /* reserved */
1095 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1096 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1097 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1098 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1099 if (e100_phy_supports_mii(nic))
1100 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1101 config->pad10 = 0x6;
1102 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1103 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1104 config->ifs = 0x6; /* x16 = inter frame spacing */
1105 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1106 config->pad15_1 = 0x1;
1107 config->pad15_2 = 0x1;
1108 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1109 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1110 config->tx_padding = 0x1; /* 1=pad short frames */
1111 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1112 config->pad18 = 0x1;
1113 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1114 config->pad20_1 = 0x1F;
1115 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1116 config->pad21_1 = 0x5;
1118 config->adaptive_ifs = nic->adaptive_ifs;
1119 config->loopback = nic->loopback;
1121 if (nic->mii.force_media && nic->mii.full_duplex)
1122 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1124 if (nic->flags & promiscuous || nic->loopback) {
1125 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1126 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1127 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1130 if (nic->flags & multicast_all)
1131 config->multicast_all = 0x1; /* 1=accept, 0=no */
1133 /* disable WoL when up */
1134 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1135 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1137 if (nic->mac >= mac_82558_D101_A4) {
1138 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1139 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1140 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1141 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1142 if (nic->mac >= mac_82559_D101M) {
1143 config->tno_intr = 0x1; /* TCO stats enable */
1144 /* Enable TCO in extended config */
1145 if (nic->mac >= mac_82551_10) {
1146 config->byte_count = 0x20; /* extended bytes */
1147 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1150 config->standard_stat_counter = 0x0;
1154 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1155 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1156 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1157 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1158 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1159 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1162 /*************************************************************************
1163 * CPUSaver parameters
1165 * All CPUSaver parameters are 16-bit literals that are part of a
1166 * "move immediate value" instruction. By changing the value of
1167 * the literal in the instruction before the code is loaded, the
1168 * driver can change the algorithm.
1170 * INTDELAY - This loads the dead-man timer with its initial value.
1171 * When this timer expires the interrupt is asserted, and the
1172 * timer is reset each time a new packet is received. (see
1173 * BUNDLEMAX below to set the limit on number of chained packets)
1174 * The current default is 0x600 or 1536. Experiments show that
1175 * the value should probably stay within the 0x200 - 0x1000.
1178 * This sets the maximum number of frames that will be bundled. In
1179 * some situations, such as the TCP windowing algorithm, it may be
1180 * better to limit the growth of the bundle size than let it go as
1181 * high as it can, because that could cause too much added latency.
1182 * The default is six, because this is the number of packets in the
1183 * default TCP window size. A value of 1 would make CPUSaver indicate
1184 * an interrupt for every frame received. If you do not want to put
1185 * a limit on the bundle size, set this value to xFFFF.
1188 * This contains a bit-mask describing the minimum size frame that
1189 * will be bundled. The default masks the lower 7 bits, which means
1190 * that any frame less than 128 bytes in length will not be bundled,
1191 * but will instead immediately generate an interrupt. This does
1192 * not affect the current bundle in any way. Any frame that is 128
1193 * bytes or large will be bundled normally. This feature is meant
1194 * to provide immediate indication of ACK frames in a TCP environment.
1195 * Customers were seeing poor performance when a machine with CPUSaver
1196 * enabled was sending but not receiving. The delay introduced when
1197 * the ACKs were received was enough to reduce total throughput, because
1198 * the sender would sit idle until the ACK was finally seen.
1200 * The current default is 0xFF80, which masks out the lower 7 bits.
1201 * This means that any frame which is x7F (127) bytes or smaller
1202 * will cause an immediate interrupt. Because this value must be a
1203 * bit mask, there are only a few valid values that can be used. To
1204 * turn this feature off, the driver can write the value xFFFF to the
1205 * lower word of this instruction (in the same way that the other
1206 * parameters are used). Likewise, a value of 0xF800 (2047) would
1207 * cause an interrupt to be generated for every frame, because all
1208 * standard Ethernet frames are <= 2047 bytes in length.
1209 *************************************************************************/
1211 /* if you wish to disable the ucode functionality, while maintaining the
1212 * workarounds it provides, set the following defines to:
1217 #define BUNDLESMALL 1
1218 #define BUNDLEMAX (u16)6
1219 #define INTDELAY (u16)1536 /* 0x600 */
1221 /* Initialize firmware */
1222 static const struct firmware *e100_request_firmware(struct nic *nic)
1224 const char *fw_name;
1225 const struct firmware *fw;
1226 u8 timer, bundle, min_size;
1229 /* do not load u-code for ICH devices */
1230 if (nic->flags & ich)
1233 /* Search for ucode match against h/w revision */
1234 if (nic->mac == mac_82559_D101M)
1235 fw_name = FIRMWARE_D101M;
1236 else if (nic->mac == mac_82559_D101S)
1237 fw_name = FIRMWARE_D101S;
1238 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1239 fw_name = FIRMWARE_D102E;
1240 else /* No ucode on other devices */
1243 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1245 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1247 return ERR_PTR(err);
1249 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1250 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1251 if (fw->size != UCODE_SIZE * 4 + 3) {
1252 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1254 release_firmware(fw);
1255 return ERR_PTR(-EINVAL);
1258 /* Read timer, bundle and min_size from end of firmware blob */
1259 timer = fw->data[UCODE_SIZE * 4];
1260 bundle = fw->data[UCODE_SIZE * 4 + 1];
1261 min_size = fw->data[UCODE_SIZE * 4 + 2];
1263 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1264 min_size >= UCODE_SIZE) {
1266 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1267 fw_name, timer, bundle, min_size);
1268 release_firmware(fw);
1269 return ERR_PTR(-EINVAL);
1271 /* OK, firmware is validated and ready to use... */
1275 static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1276 struct sk_buff *skb)
1278 const struct firmware *fw = (void *)skb;
1279 u8 timer, bundle, min_size;
1281 /* It's not a real skb; we just abused the fact that e100_exec_cb
1282 will pass it through to here... */
1285 /* firmware is stored as little endian already */
1286 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1288 /* Read timer, bundle and min_size from end of firmware blob */
1289 timer = fw->data[UCODE_SIZE * 4];
1290 bundle = fw->data[UCODE_SIZE * 4 + 1];
1291 min_size = fw->data[UCODE_SIZE * 4 + 2];
1293 /* Insert user-tunable settings in cb->u.ucode */
1294 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1295 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1296 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1297 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1298 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1299 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1301 cb->command = cpu_to_le16(cb_ucode | cb_el);
1304 static inline int e100_load_ucode_wait(struct nic *nic)
1306 const struct firmware *fw;
1307 int err = 0, counter = 50;
1308 struct cb *cb = nic->cb_to_clean;
1310 fw = e100_request_firmware(nic);
1311 /* If it's NULL, then no ucode is required */
1312 if (!fw || IS_ERR(fw))
1315 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1316 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1318 /* must restart cuc */
1319 nic->cuc_cmd = cuc_start;
1321 /* wait for completion */
1322 e100_write_flush(nic);
1325 /* wait for possibly (ouch) 500ms */
1326 while (!(cb->status & cpu_to_le16(cb_complete))) {
1328 if (!--counter) break;
1331 /* ack any interrupts, something could have been set */
1332 iowrite8(~0, &nic->csr->scb.stat_ack);
1334 /* if the command failed, or is not OK, notify and return */
1335 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1336 DPRINTK(PROBE,ERR, "ucode load failed\n");
1343 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1344 struct sk_buff *skb)
1346 cb->command = cpu_to_le16(cb_iaaddr);
1347 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1350 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1352 cb->command = cpu_to_le16(cb_dump);
1353 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1354 offsetof(struct mem, dump_buf));
1357 static int e100_phy_check_without_mii(struct nic *nic)
1362 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1365 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1366 case I82503: /* Non-MII PHY; UNTESTED! */
1367 case S80C24: /* Non-MII PHY; tested and working */
1368 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1369 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1370 * doesn't have a programming interface of any sort. The
1371 * media is sensed automatically based on how the link partner
1372 * is configured. This is, in essence, manual configuration.
1374 DPRINTK(PROBE, INFO,
1375 "found MII-less i82503 or 80c24 or other PHY\n");
1377 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1378 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1380 /* these might be needed for certain MII-less cards...
1381 * nic->flags |= ich;
1382 * nic->flags |= ich_10h_workaround; */
1393 #define NCONFIG_AUTO_SWITCH 0x0080
1394 #define MII_NSC_CONG MII_RESV1
1395 #define NSC_CONG_ENABLE 0x0100
1396 #define NSC_CONG_TXREADY 0x0400
1397 #define ADVERTISE_FC_SUPPORTED 0x0400
1398 static int e100_phy_init(struct nic *nic)
1400 struct net_device *netdev = nic->netdev;
1402 u16 bmcr, stat, id_lo, id_hi, cong;
1404 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1405 for (addr = 0; addr < 32; addr++) {
1406 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1407 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1408 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1409 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1410 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1414 /* uhoh, no PHY detected: check whether we seem to be some
1415 * weird, rare variant which is *known* to not have any MII.
1416 * But do this AFTER MII checking only, since this does
1417 * lookup of EEPROM values which may easily be unreliable. */
1418 if (e100_phy_check_without_mii(nic))
1419 return 0; /* simply return and hope for the best */
1421 /* for unknown cases log a fatal error */
1423 "Failed to locate any known PHY, aborting.\n");
1427 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1430 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1431 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1432 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1433 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1435 /* Select the phy and isolate the rest */
1436 for (addr = 0; addr < 32; addr++) {
1437 if (addr != nic->mii.phy_id) {
1438 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1439 } else if (nic->phy != phy_82552_v) {
1440 bmcr = mdio_read(netdev, addr, MII_BMCR);
1441 mdio_write(netdev, addr, MII_BMCR,
1442 bmcr & ~BMCR_ISOLATE);
1446 * Workaround for 82552:
1447 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1448 * other phy_id's) using bmcr value from addr discovery loop above.
1450 if (nic->phy == phy_82552_v)
1451 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1452 bmcr & ~BMCR_ISOLATE);
1454 /* Handle National tx phys */
1455 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1456 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1457 /* Disable congestion control */
1458 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1459 cong |= NSC_CONG_TXREADY;
1460 cong &= ~NSC_CONG_ENABLE;
1461 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1464 if (nic->phy == phy_82552_v) {
1465 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1467 /* assign special tweaked mdio_ctrl() function */
1468 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1470 /* Workaround Si not advertising flow-control during autoneg */
1471 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1472 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1474 /* Reset for the above changes to take effect */
1475 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1477 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1478 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1479 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1480 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1481 /* enable/disable MDI/MDI-X auto-switching. */
1482 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1483 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1489 static int e100_hw_init(struct nic *nic)
1495 DPRINTK(HW, ERR, "e100_hw_init\n");
1496 if (!in_interrupt() && (err = e100_self_test(nic)))
1499 if ((err = e100_phy_init(nic)))
1501 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1503 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1505 if ((err = e100_load_ucode_wait(nic)))
1507 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1509 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1511 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1512 nic->dma_addr + offsetof(struct mem, stats))))
1514 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1517 e100_disable_irq(nic);
1522 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1524 struct net_device *netdev = nic->netdev;
1525 struct dev_mc_list *list = netdev->mc_list;
1526 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1528 cb->command = cpu_to_le16(cb_multi);
1529 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1530 for (i = 0; list && i < count; i++, list = list->next)
1531 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1535 static void e100_set_multicast_list(struct net_device *netdev)
1537 struct nic *nic = netdev_priv(netdev);
1539 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1540 netdev->mc_count, netdev->flags);
1542 if (netdev->flags & IFF_PROMISC)
1543 nic->flags |= promiscuous;
1545 nic->flags &= ~promiscuous;
1547 if (netdev->flags & IFF_ALLMULTI ||
1548 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1549 nic->flags |= multicast_all;
1551 nic->flags &= ~multicast_all;
1553 e100_exec_cb(nic, NULL, e100_configure);
1554 e100_exec_cb(nic, NULL, e100_multi);
1557 static void e100_update_stats(struct nic *nic)
1559 struct net_device *dev = nic->netdev;
1560 struct net_device_stats *ns = &dev->stats;
1561 struct stats *s = &nic->mem->stats;
1562 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1563 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1566 /* Device's stats reporting may take several microseconds to
1567 * complete, so we're always waiting for results of the
1568 * previous command. */
1570 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1572 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1573 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1574 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1575 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1576 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1577 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1578 ns->collisions += nic->tx_collisions;
1579 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1580 le32_to_cpu(s->tx_lost_crs);
1581 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1582 nic->rx_over_length_errors;
1583 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1584 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1585 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1586 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1587 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1588 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1589 le32_to_cpu(s->rx_alignment_errors) +
1590 le32_to_cpu(s->rx_short_frame_errors) +
1591 le32_to_cpu(s->rx_cdt_errors);
1592 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1593 nic->tx_single_collisions +=
1594 le32_to_cpu(s->tx_single_collisions);
1595 nic->tx_multiple_collisions +=
1596 le32_to_cpu(s->tx_multiple_collisions);
1597 if (nic->mac >= mac_82558_D101_A4) {
1598 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1599 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1600 nic->rx_fc_unsupported +=
1601 le32_to_cpu(s->fc_rcv_unsupported);
1602 if (nic->mac >= mac_82559_D101M) {
1603 nic->tx_tco_frames +=
1604 le16_to_cpu(s->xmt_tco_frames);
1605 nic->rx_tco_frames +=
1606 le16_to_cpu(s->rcv_tco_frames);
1612 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1613 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1616 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1618 /* Adjust inter-frame-spacing (IFS) between two transmits if
1619 * we're getting collisions on a half-duplex connection. */
1621 if (duplex == DUPLEX_HALF) {
1622 u32 prev = nic->adaptive_ifs;
1623 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1625 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1626 (nic->tx_frames > min_frames)) {
1627 if (nic->adaptive_ifs < 60)
1628 nic->adaptive_ifs += 5;
1629 } else if (nic->tx_frames < min_frames) {
1630 if (nic->adaptive_ifs >= 5)
1631 nic->adaptive_ifs -= 5;
1633 if (nic->adaptive_ifs != prev)
1634 e100_exec_cb(nic, NULL, e100_configure);
1638 static void e100_watchdog(unsigned long data)
1640 struct nic *nic = (struct nic *)data;
1641 struct ethtool_cmd cmd;
1643 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1645 /* mii library handles link maintenance tasks */
1647 mii_ethtool_gset(&nic->mii, &cmd);
1649 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1650 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1652 cmd.speed == SPEED_100 ? "100" : "10",
1653 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1654 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1655 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1659 mii_check_link(&nic->mii);
1661 /* Software generated interrupt to recover from (rare) Rx
1662 * allocation failure.
1663 * Unfortunately have to use a spinlock to not re-enable interrupts
1664 * accidentally, due to hardware that shares a register between the
1665 * interrupt mask bit and the SW Interrupt generation bit */
1666 spin_lock_irq(&nic->cmd_lock);
1667 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1668 e100_write_flush(nic);
1669 spin_unlock_irq(&nic->cmd_lock);
1671 e100_update_stats(nic);
1672 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1674 if (nic->mac <= mac_82557_D100_C)
1675 /* Issue a multicast command to workaround a 557 lock up */
1676 e100_set_multicast_list(nic->netdev);
1678 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1679 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1680 nic->flags |= ich_10h_workaround;
1682 nic->flags &= ~ich_10h_workaround;
1684 mod_timer(&nic->watchdog,
1685 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1688 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1689 struct sk_buff *skb)
1691 cb->command = nic->tx_command;
1692 /* interrupt every 16 packets regardless of delay */
1693 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1694 cb->command |= cpu_to_le16(cb_i);
1695 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1696 cb->u.tcb.tcb_byte_count = 0;
1697 cb->u.tcb.threshold = nic->tx_threshold;
1698 cb->u.tcb.tbd_count = 1;
1699 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1700 skb->data, skb->len, PCI_DMA_TODEVICE));
1701 /* check for mapping failure? */
1702 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1705 static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1706 struct net_device *netdev)
1708 struct nic *nic = netdev_priv(netdev);
1711 if (nic->flags & ich_10h_workaround) {
1712 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1713 Issue a NOP command followed by a 1us delay before
1714 issuing the Tx command. */
1715 if (e100_exec_cmd(nic, cuc_nop, 0))
1716 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1720 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1724 /* We queued the skb, but now we're out of space. */
1725 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1726 netif_stop_queue(netdev);
1729 /* This is a hard error - log it. */
1730 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1731 netif_stop_queue(netdev);
1732 return NETDEV_TX_BUSY;
1735 netdev->trans_start = jiffies;
1736 return NETDEV_TX_OK;
1739 static int e100_tx_clean(struct nic *nic)
1741 struct net_device *dev = nic->netdev;
1745 spin_lock(&nic->cb_lock);
1747 /* Clean CBs marked complete */
1748 for (cb = nic->cb_to_clean;
1749 cb->status & cpu_to_le16(cb_complete);
1750 cb = nic->cb_to_clean = cb->next) {
1751 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1752 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1755 if (likely(cb->skb != NULL)) {
1756 dev->stats.tx_packets++;
1757 dev->stats.tx_bytes += cb->skb->len;
1759 pci_unmap_single(nic->pdev,
1760 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1761 le16_to_cpu(cb->u.tcb.tbd.size),
1763 dev_kfree_skb_any(cb->skb);
1771 spin_unlock(&nic->cb_lock);
1773 /* Recover from running out of Tx resources in xmit_frame */
1774 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1775 netif_wake_queue(nic->netdev);
1780 static void e100_clean_cbs(struct nic *nic)
1783 while (nic->cbs_avail != nic->params.cbs.count) {
1784 struct cb *cb = nic->cb_to_clean;
1786 pci_unmap_single(nic->pdev,
1787 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1788 le16_to_cpu(cb->u.tcb.tbd.size),
1790 dev_kfree_skb(cb->skb);
1792 nic->cb_to_clean = nic->cb_to_clean->next;
1795 pci_free_consistent(nic->pdev,
1796 sizeof(struct cb) * nic->params.cbs.count,
1797 nic->cbs, nic->cbs_dma_addr);
1801 nic->cuc_cmd = cuc_start;
1802 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1806 static int e100_alloc_cbs(struct nic *nic)
1809 unsigned int i, count = nic->params.cbs.count;
1811 nic->cuc_cmd = cuc_start;
1812 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1815 nic->cbs = pci_alloc_consistent(nic->pdev,
1816 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1820 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1821 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1822 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1824 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1825 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1826 ((i+1) % count) * sizeof(struct cb));
1830 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1831 nic->cbs_avail = count;
1836 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1838 if (!nic->rxs) return;
1839 if (RU_SUSPENDED != nic->ru_running) return;
1841 /* handle init time starts */
1842 if (!rx) rx = nic->rxs;
1844 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1846 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1847 nic->ru_running = RU_RUNNING;
1851 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1852 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1854 if (!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1857 /* Align, init, and map the RFD. */
1858 skb_reserve(rx->skb, NET_IP_ALIGN);
1859 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1860 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1861 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1863 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1864 dev_kfree_skb_any(rx->skb);
1870 /* Link the RFD to end of RFA by linking previous RFD to
1871 * this one. We are safe to touch the previous RFD because
1872 * it is protected by the before last buffer's el bit being set */
1873 if (rx->prev->skb) {
1874 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1875 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1876 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1877 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1883 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1884 unsigned int *work_done, unsigned int work_to_do)
1886 struct net_device *dev = nic->netdev;
1887 struct sk_buff *skb = rx->skb;
1888 struct rfd *rfd = (struct rfd *)skb->data;
1889 u16 rfd_status, actual_size;
1891 if (unlikely(work_done && *work_done >= work_to_do))
1894 /* Need to sync before taking a peek at cb_complete bit */
1895 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1896 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1897 rfd_status = le16_to_cpu(rfd->status);
1899 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1901 /* If data isn't ready, nothing to indicate */
1902 if (unlikely(!(rfd_status & cb_complete))) {
1903 /* If the next buffer has the el bit, but we think the receiver
1904 * is still running, check to see if it really stopped while
1905 * we had interrupts off.
1906 * This allows for a fast restart without re-enabling
1908 if ((le16_to_cpu(rfd->command) & cb_el) &&
1909 (RU_RUNNING == nic->ru_running))
1911 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1912 nic->ru_running = RU_SUSPENDED;
1913 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1915 PCI_DMA_FROMDEVICE);
1919 /* Get actual data size */
1920 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1921 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1922 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1925 pci_unmap_single(nic->pdev, rx->dma_addr,
1926 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1928 /* If this buffer has the el bit, but we think the receiver
1929 * is still running, check to see if it really stopped while
1930 * we had interrupts off.
1931 * This allows for a fast restart without re-enabling interrupts.
1932 * This can happen when the RU sees the size change but also sees
1933 * the el bit set. */
1934 if ((le16_to_cpu(rfd->command) & cb_el) &&
1935 (RU_RUNNING == nic->ru_running)) {
1937 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1938 nic->ru_running = RU_SUSPENDED;
1941 /* Pull off the RFD and put the actual data (minus eth hdr) */
1942 skb_reserve(skb, sizeof(struct rfd));
1943 skb_put(skb, actual_size);
1944 skb->protocol = eth_type_trans(skb, nic->netdev);
1946 if (unlikely(!(rfd_status & cb_ok))) {
1947 /* Don't indicate if hardware indicates errors */
1948 dev_kfree_skb_any(skb);
1949 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1950 /* Don't indicate oversized frames */
1951 nic->rx_over_length_errors++;
1952 dev_kfree_skb_any(skb);
1954 dev->stats.rx_packets++;
1955 dev->stats.rx_bytes += actual_size;
1956 netif_receive_skb(skb);
1966 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1967 unsigned int work_to_do)
1970 int restart_required = 0, err = 0;
1971 struct rx *old_before_last_rx, *new_before_last_rx;
1972 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1974 /* Indicate newly arrived packets */
1975 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1976 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1977 /* Hit quota or no more to clean */
1978 if (-EAGAIN == err || -ENODATA == err)
1983 /* On EAGAIN, hit quota so have more work to do, restart once
1984 * cleanup is complete.
1985 * Else, are we already rnr? then pay attention!!! this ensures that
1986 * the state machine progression never allows a start with a
1987 * partially cleaned list, avoiding a race between hardware
1988 * and rx_to_clean when in NAPI mode */
1989 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
1990 restart_required = 1;
1992 old_before_last_rx = nic->rx_to_use->prev->prev;
1993 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
1995 /* Alloc new skbs to refill list */
1996 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1997 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1998 break; /* Better luck next time (see watchdog) */
2001 new_before_last_rx = nic->rx_to_use->prev->prev;
2002 if (new_before_last_rx != old_before_last_rx) {
2003 /* Set the el-bit on the buffer that is before the last buffer.
2004 * This lets us update the next pointer on the last buffer
2005 * without worrying about hardware touching it.
2006 * We set the size to 0 to prevent hardware from touching this
2008 * When the hardware hits the before last buffer with el-bit
2009 * and size of 0, it will RNR interrupt, the RUS will go into
2010 * the No Resources state. It will not complete nor write to
2012 new_before_last_rfd =
2013 (struct rfd *)new_before_last_rx->skb->data;
2014 new_before_last_rfd->size = 0;
2015 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2016 pci_dma_sync_single_for_device(nic->pdev,
2017 new_before_last_rx->dma_addr, sizeof(struct rfd),
2018 PCI_DMA_BIDIRECTIONAL);
2020 /* Now that we have a new stopping point, we can clear the old
2021 * stopping point. We must sync twice to get the proper
2022 * ordering on the hardware side of things. */
2023 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2024 pci_dma_sync_single_for_device(nic->pdev,
2025 old_before_last_rx->dma_addr, sizeof(struct rfd),
2026 PCI_DMA_BIDIRECTIONAL);
2027 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2028 pci_dma_sync_single_for_device(nic->pdev,
2029 old_before_last_rx->dma_addr, sizeof(struct rfd),
2030 PCI_DMA_BIDIRECTIONAL);
2033 if (restart_required) {
2035 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2036 e100_start_receiver(nic, nic->rx_to_clean);
2042 static void e100_rx_clean_list(struct nic *nic)
2045 unsigned int i, count = nic->params.rfds.count;
2047 nic->ru_running = RU_UNINITIALIZED;
2050 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2052 pci_unmap_single(nic->pdev, rx->dma_addr,
2053 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2054 dev_kfree_skb(rx->skb);
2061 nic->rx_to_use = nic->rx_to_clean = NULL;
2064 static int e100_rx_alloc_list(struct nic *nic)
2067 unsigned int i, count = nic->params.rfds.count;
2068 struct rfd *before_last;
2070 nic->rx_to_use = nic->rx_to_clean = NULL;
2071 nic->ru_running = RU_UNINITIALIZED;
2073 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2076 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2077 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2078 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2079 if (e100_rx_alloc_skb(nic, rx)) {
2080 e100_rx_clean_list(nic);
2084 /* Set the el-bit on the buffer that is before the last buffer.
2085 * This lets us update the next pointer on the last buffer without
2086 * worrying about hardware touching it.
2087 * We set the size to 0 to prevent hardware from touching this buffer.
2088 * When the hardware hits the before last buffer with el-bit and size
2089 * of 0, it will RNR interrupt, the RU will go into the No Resources
2090 * state. It will not complete nor write to this buffer. */
2091 rx = nic->rxs->prev->prev;
2092 before_last = (struct rfd *)rx->skb->data;
2093 before_last->command |= cpu_to_le16(cb_el);
2094 before_last->size = 0;
2095 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2096 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2098 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2099 nic->ru_running = RU_SUSPENDED;
2104 static irqreturn_t e100_intr(int irq, void *dev_id)
2106 struct net_device *netdev = dev_id;
2107 struct nic *nic = netdev_priv(netdev);
2108 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2110 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2112 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2113 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2116 /* Ack interrupt(s) */
2117 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2119 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2120 if (stat_ack & stat_ack_rnr)
2121 nic->ru_running = RU_SUSPENDED;
2123 if (likely(napi_schedule_prep(&nic->napi))) {
2124 e100_disable_irq(nic);
2125 __napi_schedule(&nic->napi);
2131 static int e100_poll(struct napi_struct *napi, int budget)
2133 struct nic *nic = container_of(napi, struct nic, napi);
2134 unsigned int work_done = 0;
2136 e100_rx_clean(nic, &work_done, budget);
2139 /* If budget not fully consumed, exit the polling mode */
2140 if (work_done < budget) {
2141 napi_complete(napi);
2142 e100_enable_irq(nic);
2148 #ifdef CONFIG_NET_POLL_CONTROLLER
2149 static void e100_netpoll(struct net_device *netdev)
2151 struct nic *nic = netdev_priv(netdev);
2153 e100_disable_irq(nic);
2154 e100_intr(nic->pdev->irq, netdev);
2156 e100_enable_irq(nic);
2160 static int e100_set_mac_address(struct net_device *netdev, void *p)
2162 struct nic *nic = netdev_priv(netdev);
2163 struct sockaddr *addr = p;
2165 if (!is_valid_ether_addr(addr->sa_data))
2166 return -EADDRNOTAVAIL;
2168 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2169 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2174 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2176 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2178 netdev->mtu = new_mtu;
2182 static int e100_asf(struct nic *nic)
2184 /* ASF can be enabled from eeprom */
2185 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2186 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2187 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2188 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2191 static int e100_up(struct nic *nic)
2195 if ((err = e100_rx_alloc_list(nic)))
2197 if ((err = e100_alloc_cbs(nic)))
2198 goto err_rx_clean_list;
2199 if ((err = e100_hw_init(nic)))
2201 e100_set_multicast_list(nic->netdev);
2202 e100_start_receiver(nic, NULL);
2203 mod_timer(&nic->watchdog, jiffies);
2204 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2205 nic->netdev->name, nic->netdev)))
2207 netif_wake_queue(nic->netdev);
2208 napi_enable(&nic->napi);
2209 /* enable ints _after_ enabling poll, preventing a race between
2210 * disable ints+schedule */
2211 e100_enable_irq(nic);
2215 del_timer_sync(&nic->watchdog);
2217 e100_clean_cbs(nic);
2219 e100_rx_clean_list(nic);
2223 static void e100_down(struct nic *nic)
2225 /* wait here for poll to complete */
2226 napi_disable(&nic->napi);
2227 netif_stop_queue(nic->netdev);
2229 free_irq(nic->pdev->irq, nic->netdev);
2230 del_timer_sync(&nic->watchdog);
2231 netif_carrier_off(nic->netdev);
2232 e100_clean_cbs(nic);
2233 e100_rx_clean_list(nic);
2236 static void e100_tx_timeout(struct net_device *netdev)
2238 struct nic *nic = netdev_priv(netdev);
2240 /* Reset outside of interrupt context, to avoid request_irq
2241 * in interrupt context */
2242 schedule_work(&nic->tx_timeout_task);
2245 static void e100_tx_timeout_task(struct work_struct *work)
2247 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2248 struct net_device *netdev = nic->netdev;
2250 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2251 ioread8(&nic->csr->scb.status));
2252 e100_down(netdev_priv(netdev));
2253 e100_up(netdev_priv(netdev));
2256 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2259 struct sk_buff *skb;
2261 /* Use driver resources to perform internal MAC or PHY
2262 * loopback test. A single packet is prepared and transmitted
2263 * in loopback mode, and the test passes if the received
2264 * packet compares byte-for-byte to the transmitted packet. */
2266 if ((err = e100_rx_alloc_list(nic)))
2268 if ((err = e100_alloc_cbs(nic)))
2271 /* ICH PHY loopback is broken so do MAC loopback instead */
2272 if (nic->flags & ich && loopback_mode == lb_phy)
2273 loopback_mode = lb_mac;
2275 nic->loopback = loopback_mode;
2276 if ((err = e100_hw_init(nic)))
2277 goto err_loopback_none;
2279 if (loopback_mode == lb_phy)
2280 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2283 e100_start_receiver(nic, NULL);
2285 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2287 goto err_loopback_none;
2289 skb_put(skb, ETH_DATA_LEN);
2290 memset(skb->data, 0xFF, ETH_DATA_LEN);
2291 e100_xmit_frame(skb, nic->netdev);
2295 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2296 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2298 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2299 skb->data, ETH_DATA_LEN))
2303 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2304 nic->loopback = lb_none;
2305 e100_clean_cbs(nic);
2308 e100_rx_clean_list(nic);
2312 #define MII_LED_CONTROL 0x1B
2313 #define E100_82552_LED_OVERRIDE 0x19
2314 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2315 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2316 static void e100_blink_led(unsigned long data)
2318 struct nic *nic = (struct nic *)data;
2325 u16 led_reg = MII_LED_CONTROL;
2327 if (nic->phy == phy_82552_v) {
2328 led_reg = E100_82552_LED_OVERRIDE;
2330 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2331 E100_82552_LED_OFF : E100_82552_LED_ON;
2333 nic->leds = (nic->leds & led_on) ? led_off :
2334 (nic->mac < mac_82559_D101M) ? led_on_557 :
2337 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2338 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2341 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2343 struct nic *nic = netdev_priv(netdev);
2344 return mii_ethtool_gset(&nic->mii, cmd);
2347 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2349 struct nic *nic = netdev_priv(netdev);
2352 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2353 err = mii_ethtool_sset(&nic->mii, cmd);
2354 e100_exec_cb(nic, NULL, e100_configure);
2359 static void e100_get_drvinfo(struct net_device *netdev,
2360 struct ethtool_drvinfo *info)
2362 struct nic *nic = netdev_priv(netdev);
2363 strcpy(info->driver, DRV_NAME);
2364 strcpy(info->version, DRV_VERSION);
2365 strcpy(info->fw_version, "N/A");
2366 strcpy(info->bus_info, pci_name(nic->pdev));
2369 #define E100_PHY_REGS 0x1C
2370 static int e100_get_regs_len(struct net_device *netdev)
2372 struct nic *nic = netdev_priv(netdev);
2373 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2376 static void e100_get_regs(struct net_device *netdev,
2377 struct ethtool_regs *regs, void *p)
2379 struct nic *nic = netdev_priv(netdev);
2383 regs->version = (1 << 24) | nic->pdev->revision;
2384 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2385 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2386 ioread16(&nic->csr->scb.status);
2387 for (i = E100_PHY_REGS; i >= 0; i--)
2388 buff[1 + E100_PHY_REGS - i] =
2389 mdio_read(netdev, nic->mii.phy_id, i);
2390 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2391 e100_exec_cb(nic, NULL, e100_dump);
2393 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2394 sizeof(nic->mem->dump_buf));
2397 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2399 struct nic *nic = netdev_priv(netdev);
2400 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2401 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2404 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2406 struct nic *nic = netdev_priv(netdev);
2408 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2409 !device_can_wakeup(&nic->pdev->dev))
2413 nic->flags |= wol_magic;
2415 nic->flags &= ~wol_magic;
2417 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2419 e100_exec_cb(nic, NULL, e100_configure);
2424 static u32 e100_get_msglevel(struct net_device *netdev)
2426 struct nic *nic = netdev_priv(netdev);
2427 return nic->msg_enable;
2430 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2432 struct nic *nic = netdev_priv(netdev);
2433 nic->msg_enable = value;
2436 static int e100_nway_reset(struct net_device *netdev)
2438 struct nic *nic = netdev_priv(netdev);
2439 return mii_nway_restart(&nic->mii);
2442 static u32 e100_get_link(struct net_device *netdev)
2444 struct nic *nic = netdev_priv(netdev);
2445 return mii_link_ok(&nic->mii);
2448 static int e100_get_eeprom_len(struct net_device *netdev)
2450 struct nic *nic = netdev_priv(netdev);
2451 return nic->eeprom_wc << 1;
2454 #define E100_EEPROM_MAGIC 0x1234
2455 static int e100_get_eeprom(struct net_device *netdev,
2456 struct ethtool_eeprom *eeprom, u8 *bytes)
2458 struct nic *nic = netdev_priv(netdev);
2460 eeprom->magic = E100_EEPROM_MAGIC;
2461 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2466 static int e100_set_eeprom(struct net_device *netdev,
2467 struct ethtool_eeprom *eeprom, u8 *bytes)
2469 struct nic *nic = netdev_priv(netdev);
2471 if (eeprom->magic != E100_EEPROM_MAGIC)
2474 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2476 return e100_eeprom_save(nic, eeprom->offset >> 1,
2477 (eeprom->len >> 1) + 1);
2480 static void e100_get_ringparam(struct net_device *netdev,
2481 struct ethtool_ringparam *ring)
2483 struct nic *nic = netdev_priv(netdev);
2484 struct param_range *rfds = &nic->params.rfds;
2485 struct param_range *cbs = &nic->params.cbs;
2487 ring->rx_max_pending = rfds->max;
2488 ring->tx_max_pending = cbs->max;
2489 ring->rx_mini_max_pending = 0;
2490 ring->rx_jumbo_max_pending = 0;
2491 ring->rx_pending = rfds->count;
2492 ring->tx_pending = cbs->count;
2493 ring->rx_mini_pending = 0;
2494 ring->rx_jumbo_pending = 0;
2497 static int e100_set_ringparam(struct net_device *netdev,
2498 struct ethtool_ringparam *ring)
2500 struct nic *nic = netdev_priv(netdev);
2501 struct param_range *rfds = &nic->params.rfds;
2502 struct param_range *cbs = &nic->params.cbs;
2504 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2507 if (netif_running(netdev))
2509 rfds->count = max(ring->rx_pending, rfds->min);
2510 rfds->count = min(rfds->count, rfds->max);
2511 cbs->count = max(ring->tx_pending, cbs->min);
2512 cbs->count = min(cbs->count, cbs->max);
2513 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2514 rfds->count, cbs->count);
2515 if (netif_running(netdev))
2521 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2522 "Link test (on/offline)",
2523 "Eeprom test (on/offline)",
2524 "Self test (offline)",
2525 "Mac loopback (offline)",
2526 "Phy loopback (offline)",
2528 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2530 static void e100_diag_test(struct net_device *netdev,
2531 struct ethtool_test *test, u64 *data)
2533 struct ethtool_cmd cmd;
2534 struct nic *nic = netdev_priv(netdev);
2537 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2538 data[0] = !mii_link_ok(&nic->mii);
2539 data[1] = e100_eeprom_load(nic);
2540 if (test->flags & ETH_TEST_FL_OFFLINE) {
2542 /* save speed, duplex & autoneg settings */
2543 err = mii_ethtool_gset(&nic->mii, &cmd);
2545 if (netif_running(netdev))
2547 data[2] = e100_self_test(nic);
2548 data[3] = e100_loopback_test(nic, lb_mac);
2549 data[4] = e100_loopback_test(nic, lb_phy);
2551 /* restore speed, duplex & autoneg settings */
2552 err = mii_ethtool_sset(&nic->mii, &cmd);
2554 if (netif_running(netdev))
2557 for (i = 0; i < E100_TEST_LEN; i++)
2558 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2560 msleep_interruptible(4 * 1000);
2563 static int e100_phys_id(struct net_device *netdev, u32 data)
2565 struct nic *nic = netdev_priv(netdev);
2566 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2569 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2570 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2571 mod_timer(&nic->blink_timer, jiffies);
2572 msleep_interruptible(data * 1000);
2573 del_timer_sync(&nic->blink_timer);
2574 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2579 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2580 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2581 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2582 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2583 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2584 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2585 "tx_heartbeat_errors", "tx_window_errors",
2586 /* device-specific stats */
2587 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2588 "tx_flow_control_pause", "rx_flow_control_pause",
2589 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2591 #define E100_NET_STATS_LEN 21
2592 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2594 static int e100_get_sset_count(struct net_device *netdev, int sset)
2598 return E100_TEST_LEN;
2600 return E100_STATS_LEN;
2606 static void e100_get_ethtool_stats(struct net_device *netdev,
2607 struct ethtool_stats *stats, u64 *data)
2609 struct nic *nic = netdev_priv(netdev);
2612 for (i = 0; i < E100_NET_STATS_LEN; i++)
2613 data[i] = ((unsigned long *)&netdev->stats)[i];
2615 data[i++] = nic->tx_deferred;
2616 data[i++] = nic->tx_single_collisions;
2617 data[i++] = nic->tx_multiple_collisions;
2618 data[i++] = nic->tx_fc_pause;
2619 data[i++] = nic->rx_fc_pause;
2620 data[i++] = nic->rx_fc_unsupported;
2621 data[i++] = nic->tx_tco_frames;
2622 data[i++] = nic->rx_tco_frames;
2625 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2627 switch (stringset) {
2629 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2632 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2637 static const struct ethtool_ops e100_ethtool_ops = {
2638 .get_settings = e100_get_settings,
2639 .set_settings = e100_set_settings,
2640 .get_drvinfo = e100_get_drvinfo,
2641 .get_regs_len = e100_get_regs_len,
2642 .get_regs = e100_get_regs,
2643 .get_wol = e100_get_wol,
2644 .set_wol = e100_set_wol,
2645 .get_msglevel = e100_get_msglevel,
2646 .set_msglevel = e100_set_msglevel,
2647 .nway_reset = e100_nway_reset,
2648 .get_link = e100_get_link,
2649 .get_eeprom_len = e100_get_eeprom_len,
2650 .get_eeprom = e100_get_eeprom,
2651 .set_eeprom = e100_set_eeprom,
2652 .get_ringparam = e100_get_ringparam,
2653 .set_ringparam = e100_set_ringparam,
2654 .self_test = e100_diag_test,
2655 .get_strings = e100_get_strings,
2656 .phys_id = e100_phys_id,
2657 .get_ethtool_stats = e100_get_ethtool_stats,
2658 .get_sset_count = e100_get_sset_count,
2661 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2663 struct nic *nic = netdev_priv(netdev);
2665 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2668 static int e100_alloc(struct nic *nic)
2670 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2672 return nic->mem ? 0 : -ENOMEM;
2675 static void e100_free(struct nic *nic)
2678 pci_free_consistent(nic->pdev, sizeof(struct mem),
2679 nic->mem, nic->dma_addr);
2684 static int e100_open(struct net_device *netdev)
2686 struct nic *nic = netdev_priv(netdev);
2689 netif_carrier_off(netdev);
2690 if ((err = e100_up(nic)))
2691 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2695 static int e100_close(struct net_device *netdev)
2697 e100_down(netdev_priv(netdev));
2701 static const struct net_device_ops e100_netdev_ops = {
2702 .ndo_open = e100_open,
2703 .ndo_stop = e100_close,
2704 .ndo_start_xmit = e100_xmit_frame,
2705 .ndo_validate_addr = eth_validate_addr,
2706 .ndo_set_multicast_list = e100_set_multicast_list,
2707 .ndo_set_mac_address = e100_set_mac_address,
2708 .ndo_change_mtu = e100_change_mtu,
2709 .ndo_do_ioctl = e100_do_ioctl,
2710 .ndo_tx_timeout = e100_tx_timeout,
2711 #ifdef CONFIG_NET_POLL_CONTROLLER
2712 .ndo_poll_controller = e100_netpoll,
2716 static int __devinit e100_probe(struct pci_dev *pdev,
2717 const struct pci_device_id *ent)
2719 struct net_device *netdev;
2723 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2724 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2725 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2729 netdev->netdev_ops = &e100_netdev_ops;
2730 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2731 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2732 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2734 nic = netdev_priv(netdev);
2735 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2736 nic->netdev = netdev;
2738 nic->msg_enable = (1 << debug) - 1;
2739 nic->mdio_ctrl = mdio_ctrl_hw;
2740 pci_set_drvdata(pdev, netdev);
2742 if ((err = pci_enable_device(pdev))) {
2743 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2744 goto err_out_free_dev;
2747 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2748 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2749 "base address, aborting.\n");
2751 goto err_out_disable_pdev;
2754 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2755 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2756 goto err_out_disable_pdev;
2759 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2760 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2761 goto err_out_free_res;
2764 SET_NETDEV_DEV(netdev, &pdev->dev);
2767 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2769 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2771 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2773 goto err_out_free_res;
2776 if (ent->driver_data)
2781 e100_get_defaults(nic);
2783 /* locks must be initialized before calling hw_reset */
2784 spin_lock_init(&nic->cb_lock);
2785 spin_lock_init(&nic->cmd_lock);
2786 spin_lock_init(&nic->mdio_lock);
2788 /* Reset the device before pci_set_master() in case device is in some
2789 * funky state and has an interrupt pending - hint: we don't have the
2790 * interrupt handler registered yet. */
2793 pci_set_master(pdev);
2795 init_timer(&nic->watchdog);
2796 nic->watchdog.function = e100_watchdog;
2797 nic->watchdog.data = (unsigned long)nic;
2798 init_timer(&nic->blink_timer);
2799 nic->blink_timer.function = e100_blink_led;
2800 nic->blink_timer.data = (unsigned long)nic;
2802 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2804 if ((err = e100_alloc(nic))) {
2805 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2806 goto err_out_iounmap;
2809 if ((err = e100_eeprom_load(nic)))
2814 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2815 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2816 if (!is_valid_ether_addr(netdev->perm_addr)) {
2817 if (!eeprom_bad_csum_allow) {
2818 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2819 "EEPROM, aborting.\n");
2823 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2824 "you MUST configure one.\n");
2828 /* Wol magic packet can be enabled from eeprom */
2829 if ((nic->mac >= mac_82558_D101_A4) &&
2830 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2831 nic->flags |= wol_magic;
2832 device_set_wakeup_enable(&pdev->dev, true);
2835 /* ack any pending wake events, disable PME */
2836 pci_pme_active(pdev, false);
2838 strcpy(netdev->name, "eth%d");
2839 if ((err = register_netdev(netdev))) {
2840 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2844 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
2845 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2846 pdev->irq, netdev->dev_addr);
2853 pci_iounmap(pdev, nic->csr);
2855 pci_release_regions(pdev);
2856 err_out_disable_pdev:
2857 pci_disable_device(pdev);
2859 pci_set_drvdata(pdev, NULL);
2860 free_netdev(netdev);
2864 static void __devexit e100_remove(struct pci_dev *pdev)
2866 struct net_device *netdev = pci_get_drvdata(pdev);
2869 struct nic *nic = netdev_priv(netdev);
2870 unregister_netdev(netdev);
2872 pci_iounmap(pdev, nic->csr);
2873 free_netdev(netdev);
2874 pci_release_regions(pdev);
2875 pci_disable_device(pdev);
2876 pci_set_drvdata(pdev, NULL);
2880 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2881 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2882 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2883 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2885 struct net_device *netdev = pci_get_drvdata(pdev);
2886 struct nic *nic = netdev_priv(netdev);
2888 if (netif_running(netdev))
2890 netif_device_detach(netdev);
2892 pci_save_state(pdev);
2894 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2895 /* enable reverse auto-negotiation */
2896 if (nic->phy == phy_82552_v) {
2897 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2898 E100_82552_SMARTSPEED);
2900 mdio_write(netdev, nic->mii.phy_id,
2901 E100_82552_SMARTSPEED, smartspeed |
2902 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2904 *enable_wake = true;
2906 *enable_wake = false;
2909 pci_disable_device(pdev);
2912 static int __e100_power_off(struct pci_dev *pdev, bool wake)
2915 return pci_prepare_to_sleep(pdev);
2917 pci_wake_from_d3(pdev, false);
2918 pci_set_power_state(pdev, PCI_D3hot);
2924 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2927 __e100_shutdown(pdev, &wake);
2928 return __e100_power_off(pdev, wake);
2931 static int e100_resume(struct pci_dev *pdev)
2933 struct net_device *netdev = pci_get_drvdata(pdev);
2934 struct nic *nic = netdev_priv(netdev);
2936 pci_set_power_state(pdev, PCI_D0);
2937 pci_restore_state(pdev);
2938 /* ack any pending wake events, disable PME */
2939 pci_enable_wake(pdev, 0, 0);
2941 /* disable reverse auto-negotiation */
2942 if (nic->phy == phy_82552_v) {
2943 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2944 E100_82552_SMARTSPEED);
2946 mdio_write(netdev, nic->mii.phy_id,
2947 E100_82552_SMARTSPEED,
2948 smartspeed & ~(E100_82552_REV_ANEG));
2951 netif_device_attach(netdev);
2952 if (netif_running(netdev))
2957 #endif /* CONFIG_PM */
2959 static void e100_shutdown(struct pci_dev *pdev)
2962 __e100_shutdown(pdev, &wake);
2963 if (system_state == SYSTEM_POWER_OFF)
2964 __e100_power_off(pdev, wake);
2967 /* ------------------ PCI Error Recovery infrastructure -------------- */
2969 * e100_io_error_detected - called when PCI error is detected.
2970 * @pdev: Pointer to PCI device
2971 * @state: The current pci connection state
2973 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2975 struct net_device *netdev = pci_get_drvdata(pdev);
2976 struct nic *nic = netdev_priv(netdev);
2978 netif_device_detach(netdev);
2980 if (state == pci_channel_io_perm_failure)
2981 return PCI_ERS_RESULT_DISCONNECT;
2983 if (netif_running(netdev))
2985 pci_disable_device(pdev);
2987 /* Request a slot reset. */
2988 return PCI_ERS_RESULT_NEED_RESET;
2992 * e100_io_slot_reset - called after the pci bus has been reset.
2993 * @pdev: Pointer to PCI device
2995 * Restart the card from scratch.
2997 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2999 struct net_device *netdev = pci_get_drvdata(pdev);
3000 struct nic *nic = netdev_priv(netdev);
3002 if (pci_enable_device(pdev)) {
3003 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
3004 return PCI_ERS_RESULT_DISCONNECT;
3006 pci_set_master(pdev);
3008 /* Only one device per card can do a reset */
3009 if (0 != PCI_FUNC(pdev->devfn))
3010 return PCI_ERS_RESULT_RECOVERED;
3014 return PCI_ERS_RESULT_RECOVERED;
3018 * e100_io_resume - resume normal operations
3019 * @pdev: Pointer to PCI device
3021 * Resume normal operations after an error recovery
3022 * sequence has been completed.
3024 static void e100_io_resume(struct pci_dev *pdev)
3026 struct net_device *netdev = pci_get_drvdata(pdev);
3027 struct nic *nic = netdev_priv(netdev);
3029 /* ack any pending wake events, disable PME */
3030 pci_enable_wake(pdev, 0, 0);
3032 netif_device_attach(netdev);
3033 if (netif_running(netdev)) {
3035 mod_timer(&nic->watchdog, jiffies);
3039 static struct pci_error_handlers e100_err_handler = {
3040 .error_detected = e100_io_error_detected,
3041 .slot_reset = e100_io_slot_reset,
3042 .resume = e100_io_resume,
3045 static struct pci_driver e100_driver = {
3047 .id_table = e100_id_table,
3048 .probe = e100_probe,
3049 .remove = __devexit_p(e100_remove),
3051 /* Power Management hooks */
3052 .suspend = e100_suspend,
3053 .resume = e100_resume,
3055 .shutdown = e100_shutdown,
3056 .err_handler = &e100_err_handler,
3059 static int __init e100_init_module(void)
3061 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3062 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3063 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
3065 return pci_register_driver(&e100_driver);
3068 static void __exit e100_cleanup_module(void)
3070 pci_unregister_driver(&e100_driver);
3073 module_init(e100_init_module);
3074 module_exit(e100_cleanup_module);