2 * Definitions of the CPL 5 commands and status codes.
4 * Copyright (C) 2004-2006 Chelsio Communications. All rights reserved.
6 * Written by Dimitris Michailidis (dm@chelsio.com)
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
11 * release for licensing terms and conditions.
17 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
18 # include <asm/byteorder.h>
22 CPL_PASS_OPEN_REQ = 0x1,
23 CPL_PASS_ACCEPT_RPL = 0x2,
24 CPL_ACT_OPEN_REQ = 0x3,
26 CPL_SET_TCB_FIELD = 0x5,
29 CPL_CLOSE_CON_REQ = 0x8,
30 CPL_CLOSE_LISTSRV_REQ = 0x9,
34 CPL_RX_DATA_ACK = 0xD,
36 CPL_RTE_DELETE_REQ = 0xF,
37 CPL_RTE_WRITE_REQ = 0x10,
38 CPL_RTE_READ_REQ = 0x11,
39 CPL_L2T_WRITE_REQ = 0x12,
40 CPL_L2T_READ_REQ = 0x13,
41 CPL_SMT_WRITE_REQ = 0x14,
42 CPL_SMT_READ_REQ = 0x15,
43 CPL_TX_PKT_LSO = 0x16,
46 CPL_TID_RELEASE = 0x1A,
48 CPL_CLOSE_LISTSRV_RPL = 0x20,
50 CPL_GET_TCB_RPL = 0x22,
51 CPL_L2T_WRITE_RPL = 0x23,
52 CPL_PCMD_READ_RPL = 0x24,
54 CPL_PEER_CLOSE = 0x26,
55 CPL_RTE_DELETE_RPL = 0x27,
56 CPL_RTE_WRITE_RPL = 0x28,
57 CPL_RX_DDP_COMPLETE = 0x29,
58 CPL_RX_PHYS_ADDR = 0x2A,
60 CPL_RX_URG_NOTIFY = 0x2C,
61 CPL_SET_TCB_RPL = 0x2D,
62 CPL_SMT_WRITE_RPL = 0x2E,
63 CPL_TX_DATA_ACK = 0x2F,
65 CPL_ABORT_REQ_RSS = 0x30,
66 CPL_ABORT_RPL_RSS = 0x31,
67 CPL_CLOSE_CON_RPL = 0x32,
69 CPL_L2T_READ_RPL = 0x34,
71 CPL_RDMA_CQE_READ_RSP = 0x36,
72 CPL_RDMA_CQE_ERR = 0x37,
73 CPL_RTE_READ_RPL = 0x38,
76 CPL_ACT_OPEN_RPL = 0x40,
77 CPL_PASS_OPEN_RPL = 0x41,
78 CPL_RX_DATA_DDP = 0x42,
79 CPL_SMT_READ_RPL = 0x43,
81 CPL_ACT_ESTABLISH = 0x50,
82 CPL_PASS_ESTABLISH = 0x51,
84 CPL_PASS_ACCEPT_REQ = 0x70,
86 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
88 CPL_TX_DMA_ACK = 0xA0,
89 CPL_RDMA_READ_REQ = 0xA1,
90 CPL_RDMA_TERMINATE = 0xA2,
92 CPL_RDMA_EC_STATUS = 0xA5,
94 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
99 CPL_ERR_TCAM_PARITY = 1,
100 CPL_ERR_TCAM_FULL = 3,
101 CPL_ERR_CONN_RESET = 20,
102 CPL_ERR_CONN_EXIST = 22,
103 CPL_ERR_ARP_MISS = 23,
104 CPL_ERR_BAD_SYN = 24,
105 CPL_ERR_CONN_TIMEDOUT = 30,
106 CPL_ERR_XMIT_TIMEDOUT = 31,
107 CPL_ERR_PERSIST_TIMEDOUT = 32,
108 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
109 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
110 CPL_ERR_RTX_NEG_ADVICE = 35,
111 CPL_ERR_PERSIST_NEG_ADVICE = 36,
112 CPL_ERR_ABORT_FAILED = 42,
117 CPL_CONN_POLICY_AUTO = 0,
118 CPL_CONN_POLICY_ASK = 1,
119 CPL_CONN_POLICY_DENY = 3
130 ULP_CRC_HEADER = 1 << 0,
131 ULP_CRC_DATA = 1 << 1
135 CPL_PASS_OPEN_ACCEPT,
140 CPL_ABORT_SEND_RST = 0,
142 CPL_ABORT_POST_CLOSE_REQ = 2
145 enum { /* TX_PKT_LSO ethernet types */
152 enum { /* TCP congestion control algorithms */
165 #define V_OPCODE(x) ((x) << S_OPCODE)
166 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
167 #define G_TID(x) ((x) & 0xFFFFFF)
169 /* tid is assumed to be 24-bits */
170 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
172 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
174 /* extract the TID from a CPL command */
175 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
180 #if defined(__LITTLE_ENDIAN_BITFIELD)
195 #if defined(__LITTLE_ENDIAN_BITFIELD)
207 struct work_request_hdr {
213 #define S_WR_SGE_CREDITS 0
214 #define M_WR_SGE_CREDITS 0xFF
215 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
216 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
218 #define S_WR_SGLSFLT 8
219 #define M_WR_SGLSFLT 0xFF
220 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
221 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
223 #define S_WR_BCNTLFLT 16
224 #define M_WR_BCNTLFLT 0xF
225 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
226 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
228 #define S_WR_DATATYPE 20
229 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
230 #define F_WR_DATATYPE V_WR_DATATYPE(1U)
232 #define S_WR_COMPL 21
233 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
234 #define F_WR_COMPL V_WR_COMPL(1U)
237 #define V_WR_EOP(x) ((x) << S_WR_EOP)
238 #define F_WR_EOP V_WR_EOP(1U)
241 #define V_WR_SOP(x) ((x) << S_WR_SOP)
242 #define F_WR_SOP V_WR_SOP(1U)
246 #define V_WR_OP(x) ((x) << S_WR_OP)
247 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
251 #define M_WR_LEN 0xFF
252 #define V_WR_LEN(x) ((x) << S_WR_LEN)
253 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
256 #define M_WR_TID 0xFFFFF
257 #define V_WR_TID(x) ((x) << S_WR_TID)
258 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
260 #define S_WR_CR_FLUSH 30
261 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
262 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U)
265 #define V_WR_GEN(x) ((x) << S_WR_GEN)
266 #define F_WR_GEN V_WR_GEN(1U)
268 # define WR_HDR struct work_request_hdr wr
272 # define RSS_HDR struct rss_header rss_hdr;
275 /* option 0 lower-half fields */
276 #define S_CPL_STATUS 0
277 #define M_CPL_STATUS 0xFF
278 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
279 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
281 #define S_INJECT_TIMER 6
282 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
283 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
285 #define S_NO_OFFLOAD 7
286 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
287 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U)
290 #define M_ULP_MODE 0xF
291 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
292 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
294 #define S_RCV_BUFSIZ 12
295 #define M_RCV_BUFSIZ 0x3FFF
296 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
297 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
301 #define V_TOS(x) ((x) << S_TOS)
302 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
304 /* option 0 upper-half fields */
306 #define V_DELACK(x) ((x) << S_DELACK)
307 #define F_DELACK V_DELACK(1U)
310 #define V_NO_CONG(x) ((x) << S_NO_CONG)
311 #define F_NO_CONG V_NO_CONG(1U)
313 #define S_SRC_MAC_SEL 2
314 #define M_SRC_MAC_SEL 0x3
315 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
316 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
319 #define M_L2T_IDX 0x7FF
320 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
321 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
323 #define S_TX_CHANNEL 15
324 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
325 #define F_TX_CHANNEL V_TX_CHANNEL(1U)
327 #define S_TCAM_BYPASS 16
328 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
329 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U)
332 #define V_NAGLE(x) ((x) << S_NAGLE)
333 #define F_NAGLE V_NAGLE(1U)
335 #define S_WND_SCALE 18
336 #define M_WND_SCALE 0xF
337 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
338 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
340 #define S_KEEP_ALIVE 22
341 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
342 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U)
344 #define S_MAX_RETRANS 23
345 #define M_MAX_RETRANS 0xF
346 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
347 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
349 #define S_MAX_RETRANS_OVERRIDE 27
350 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
351 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U)
354 #define M_MSS_IDX 0xF
355 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
356 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
358 /* option 1 fields */
359 #define S_RSS_ENABLE 0
360 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
361 #define F_RSS_ENABLE V_RSS_ENABLE(1U)
363 #define S_RSS_MASK_LEN 1
364 #define M_RSS_MASK_LEN 0x7
365 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
366 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
369 #define M_CPU_IDX 0x3F
370 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
371 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
373 #define S_MAC_MATCH_VALID 18
374 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
375 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
377 #define S_CONN_POLICY 19
378 #define M_CONN_POLICY 0x3
379 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
380 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
382 #define S_SYN_DEFENSE 21
383 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
384 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
386 #define S_VLAN_PRI 22
387 #define M_VLAN_PRI 0x3
388 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
389 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
391 #define S_VLAN_PRI_VALID 24
392 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
393 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U)
395 #define S_PKT_TYPE 25
396 #define M_PKT_TYPE 0x3
397 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
398 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
400 #define S_MAC_MATCH 27
401 #define M_MAC_MATCH 0x1F
402 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
403 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
405 /* option 2 fields */
406 #define S_CPU_INDEX 0
407 #define M_CPU_INDEX 0x7F
408 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
409 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
411 #define S_CPU_INDEX_VALID 7
412 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
413 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U)
415 #define S_RX_COALESCE 8
416 #define M_RX_COALESCE 0x3
417 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
418 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
420 #define S_RX_COALESCE_VALID 10
421 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
422 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
424 #define S_CONG_CONTROL_FLAVOR 11
425 #define M_CONG_CONTROL_FLAVOR 0x3
426 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
427 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
429 #define S_PACING_FLAVOR 13
430 #define M_PACING_FLAVOR 0x3
431 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
432 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
434 #define S_FLAVORS_VALID 15
435 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
436 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U)
438 #define S_RX_FC_DISABLE 16
439 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
440 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
442 #define S_RX_FC_VALID 17
443 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
444 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
446 struct cpl_pass_open_req {
459 struct cpl_pass_open_rpl {
460 RSS_HDR union opcode_tid ot;
469 struct cpl_pass_establish {
470 RSS_HDR union opcode_tid ot;
482 /* cpl_pass_establish.tos_tid fields */
483 #define S_PASS_OPEN_TID 0
484 #define M_PASS_OPEN_TID 0xFFFFFF
485 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
486 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
488 #define S_PASS_OPEN_TOS 24
489 #define M_PASS_OPEN_TOS 0xFF
490 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
491 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
493 /* cpl_pass_establish.l2t_idx fields */
494 #define S_L2T_IDX16 5
495 #define M_L2T_IDX16 0x7FF
496 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
497 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
499 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
500 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
501 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
502 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
503 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
504 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
506 struct cpl_pass_accept_req {
507 RSS_HDR union opcode_tid ot;
513 struct tcp_options tcp_options;
517 #if defined(__LITTLE_ENDIAN_BITFIELD)
533 struct cpl_pass_accept_rpl {
543 struct cpl_act_open_req {
556 /* cpl_act_open_req.params fields */
557 #define S_AOPEN_VLAN_PRI 9
558 #define M_AOPEN_VLAN_PRI 0x3
559 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
560 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
562 #define S_AOPEN_VLAN_PRI_VALID 11
563 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
564 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
566 #define S_AOPEN_PKT_TYPE 12
567 #define M_AOPEN_PKT_TYPE 0x3
568 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
569 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
571 #define S_AOPEN_MAC_MATCH 14
572 #define M_AOPEN_MAC_MATCH 0x1F
573 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
574 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
576 #define S_AOPEN_MAC_MATCH_VALID 19
577 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
578 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
580 #define S_AOPEN_IFF_VLAN 20
581 #define M_AOPEN_IFF_VLAN 0xFFF
582 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
583 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
585 struct cpl_act_open_rpl {
586 RSS_HDR union opcode_tid ot;
596 struct cpl_act_establish {
597 RSS_HDR union opcode_tid ot;
616 struct cpl_get_tcb_rpl {
617 RSS_HDR union opcode_tid ot;
631 /* cpl_set_tcb.reply fields */
633 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
634 #define F_NO_REPLY V_NO_REPLY(1U)
636 struct cpl_set_tcb_field {
646 struct cpl_set_tcb_rpl {
647 RSS_HDR union opcode_tid ot;
656 #if defined(__LITTLE_ENDIAN_BITFIELD)
670 struct cpl_pcmd_reply {
671 RSS_HDR union opcode_tid ot;
677 struct cpl_close_con_req {
683 struct cpl_close_con_rpl {
684 RSS_HDR union opcode_tid ot;
691 struct cpl_close_listserv_req {
699 struct cpl_close_listserv_rpl {
700 RSS_HDR union opcode_tid ot;
705 struct cpl_abort_req_rss {
706 RSS_HDR union opcode_tid ot;
713 struct cpl_abort_req {
722 struct cpl_abort_rpl_rss {
723 RSS_HDR union opcode_tid ot;
730 struct cpl_abort_rpl {
739 struct cpl_peer_close {
740 RSS_HDR union opcode_tid ot;
753 /* tx_data_wr.param fields */
755 #define M_TX_PORT 0x7
756 #define V_TX_PORT(x) ((x) << S_TX_PORT)
757 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
761 #define V_TX_MSS(x) ((x) << S_TX_MSS)
762 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
765 #define M_TX_QOS 0xFF
766 #define V_TX_QOS(x) ((x) << S_TX_QOS)
767 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
769 #define S_TX_SNDBUF 16
770 #define M_TX_SNDBUF 0xFFFF
771 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
772 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
782 /* cpl_tx_data.flags fields */
783 #define S_TX_ULP_SUBMODE 6
784 #define M_TX_ULP_SUBMODE 0xF
785 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
786 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
788 #define S_TX_ULP_MODE 10
789 #define M_TX_ULP_MODE 0xF
790 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
791 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
793 #define S_TX_SHOVE 14
794 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
795 #define F_TX_SHOVE V_TX_SHOVE(1U)
798 #define V_TX_MORE(x) ((x) << S_TX_MORE)
799 #define F_TX_MORE V_TX_MORE(1U)
801 /* additional tx_data_wr.flags fields */
802 #define S_TX_CPU_IDX 0
803 #define M_TX_CPU_IDX 0x3F
804 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
805 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
808 #define V_TX_URG(x) ((x) << S_TX_URG)
809 #define F_TX_URG V_TX_URG(1U)
811 #define S_TX_CLOSE 17
812 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
813 #define F_TX_CLOSE V_TX_CLOSE(1U)
816 #define V_TX_INIT(x) ((x) << S_TX_INIT)
817 #define F_TX_INIT V_TX_INIT(1U)
819 #define S_TX_IMM_ACK 19
820 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
821 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
823 #define S_TX_IMM_DMA 20
824 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
825 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
827 struct cpl_tx_data_ack {
828 RSS_HDR union opcode_tid ot;
833 RSS_HDR union opcode_tid ot;
840 struct cpl_rdma_ec_status {
841 RSS_HDR union opcode_tid ot;
846 struct mngt_pktsched_wr {
859 struct cpl_iscsi_hdr {
860 RSS_HDR union opcode_tid ot;
869 /* cpl_iscsi_hdr.pdu_len_ddp fields */
870 #define S_ISCSI_PDU_LEN 0
871 #define M_ISCSI_PDU_LEN 0x7FFF
872 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
873 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
875 #define S_ISCSI_DDP 15
876 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
877 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
880 RSS_HDR union opcode_tid ot;
885 #if defined(__LITTLE_ENDIAN_BITFIELD)
899 struct cpl_rx_data_ack {
905 /* cpl_rx_data_ack.ack_seq fields */
906 #define S_RX_CREDITS 0
907 #define M_RX_CREDITS 0x7FFFFFF
908 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
909 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
911 #define S_RX_MODULATE 27
912 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
913 #define F_RX_MODULATE V_RX_MODULATE(1U)
915 #define S_RX_FORCE_ACK 28
916 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
917 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
919 #define S_RX_DACK_MODE 29
920 #define M_RX_DACK_MODE 0x3
921 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
922 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
924 #define S_RX_DACK_CHANGE 31
925 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
926 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
928 struct cpl_rx_urg_notify {
929 RSS_HDR union opcode_tid ot;
933 struct cpl_rx_ddp_complete {
934 RSS_HDR union opcode_tid ot;
938 struct cpl_rx_data_ddp {
939 RSS_HDR union opcode_tid ot;
948 __be32 ddpvld_status;
951 /* cpl_rx_data_ddp.ddpvld_status fields */
952 #define S_DDP_STATUS 0
953 #define M_DDP_STATUS 0xFF
954 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
955 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
957 #define S_DDP_VALID 15
958 #define M_DDP_VALID 0x1FFFF
959 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
960 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
962 #define S_DDP_PPOD_MISMATCH 15
963 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
964 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
967 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
968 #define F_DDP_PDU V_DDP_PDU(1U)
970 #define S_DDP_LLIMIT_ERR 17
971 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
972 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
974 #define S_DDP_PPOD_PARITY_ERR 18
975 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
976 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
978 #define S_DDP_PADDING_ERR 19
979 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
980 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
982 #define S_DDP_HDRCRC_ERR 20
983 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
984 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
986 #define S_DDP_DATACRC_ERR 21
987 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
988 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
990 #define S_DDP_INVALID_TAG 22
991 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
992 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
994 #define S_DDP_ULIMIT_ERR 23
995 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
996 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
998 #define S_DDP_OFFSET_ERR 24
999 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1000 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1002 #define S_DDP_COLOR_ERR 25
1003 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1004 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1006 #define S_DDP_TID_MISMATCH 26
1007 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1008 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1010 #define S_DDP_INVALID_PPOD 27
1011 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1012 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1014 #define S_DDP_ULP_MODE 28
1015 #define M_DDP_ULP_MODE 0xF
1016 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1017 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1019 /* cpl_rx_data_ddp.ddp_report fields */
1020 #define S_DDP_OFFSET 0
1021 #define M_DDP_OFFSET 0x3FFFFF
1022 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1023 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1025 #define S_DDP_URG 24
1026 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1027 #define F_DDP_URG V_DDP_URG(1U)
1029 #define S_DDP_PSH 25
1030 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1031 #define F_DDP_PSH V_DDP_PSH(1U)
1033 #define S_DDP_BUF_COMPLETE 26
1034 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1035 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1037 #define S_DDP_BUF_TIMED_OUT 27
1038 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1039 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1041 #define S_DDP_BUF_IDX 28
1042 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1043 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1051 struct cpl_tx_pkt_lso {
1060 /* cpl_tx_pkt*.cntrl fields */
1061 #define S_TXPKT_VLAN 0
1062 #define M_TXPKT_VLAN 0xFFFF
1063 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1064 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1066 #define S_TXPKT_INTF 16
1067 #define M_TXPKT_INTF 0xF
1068 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1069 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1071 #define S_TXPKT_IPCSUM_DIS 20
1072 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1073 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U)
1075 #define S_TXPKT_L4CSUM_DIS 21
1076 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1077 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U)
1079 #define S_TXPKT_VLAN_VLD 22
1080 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1081 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U)
1083 #define S_TXPKT_LOOPBACK 23
1084 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1085 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1087 #define S_TXPKT_OPCODE 24
1088 #define M_TXPKT_OPCODE 0xFF
1089 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1090 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1092 /* cpl_tx_pkt_lso.lso_info fields */
1094 #define M_LSO_MSS 0x3FFF
1095 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1096 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1098 #define S_LSO_ETH_TYPE 14
1099 #define M_LSO_ETH_TYPE 0x3
1100 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1101 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1103 #define S_LSO_TCPHDR_WORDS 16
1104 #define M_LSO_TCPHDR_WORDS 0xF
1105 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1106 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1108 #define S_LSO_IPHDR_WORDS 20
1109 #define M_LSO_IPHDR_WORDS 0xF
1110 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1111 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1113 #define S_LSO_IPV6 24
1114 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1115 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1117 struct cpl_trace_pkt {
1120 #if defined(__LITTLE_ENDIAN_BITFIELD)
1128 #if defined(__LITTLE_ENDIAN_BITFIELD)
1136 #endif /* CHELSIO_FW */
1139 #if defined(__LITTLE_ENDIAN_BITFIELD)
1151 RSS_HDR __u8 opcode;
1152 #if defined(__LITTLE_ENDIAN_BITFIELD)
1170 struct cpl_l2t_write_req {
1172 union opcode_tid ot;
1178 /* cpl_l2t_write_req.params fields */
1179 #define S_L2T_W_IDX 0
1180 #define M_L2T_W_IDX 0x7FF
1181 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1182 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1184 #define S_L2T_W_VLAN 11
1185 #define M_L2T_W_VLAN 0xFFF
1186 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1187 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1189 #define S_L2T_W_IFF 23
1190 #define M_L2T_W_IFF 0xF
1191 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1192 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1194 #define S_L2T_W_PRIO 27
1195 #define M_L2T_W_PRIO 0x7
1196 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1197 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1199 struct cpl_l2t_write_rpl {
1200 RSS_HDR union opcode_tid ot;
1205 struct cpl_l2t_read_req {
1207 union opcode_tid ot;
1212 struct cpl_l2t_read_rpl {
1213 RSS_HDR union opcode_tid ot;
1219 /* cpl_l2t_read_rpl.params fields */
1220 #define S_L2T_R_PRIO 0
1221 #define M_L2T_R_PRIO 0x7
1222 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1223 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1225 #define S_L2T_R_VLAN 8
1226 #define M_L2T_R_VLAN 0xFFF
1227 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1228 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1230 #define S_L2T_R_IFF 20
1231 #define M_L2T_R_IFF 0xF
1232 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1233 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1235 #define S_L2T_STATUS 24
1236 #define M_L2T_STATUS 0xFF
1237 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1238 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1240 struct cpl_smt_write_req {
1242 union opcode_tid ot;
1244 #if defined(__LITTLE_ENDIAN_BITFIELD)
1258 struct cpl_smt_write_rpl {
1259 RSS_HDR union opcode_tid ot;
1264 struct cpl_smt_read_req {
1266 union opcode_tid ot;
1268 #if defined(__LITTLE_ENDIAN_BITFIELD)
1278 struct cpl_smt_read_rpl {
1279 RSS_HDR union opcode_tid ot;
1281 #if defined(__LITTLE_ENDIAN_BITFIELD)
1295 struct cpl_rte_delete_req {
1297 union opcode_tid ot;
1301 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1302 #define S_RTE_REQ_LUT_IX 8
1303 #define M_RTE_REQ_LUT_IX 0x7FF
1304 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1305 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1307 #define S_RTE_REQ_LUT_BASE 19
1308 #define M_RTE_REQ_LUT_BASE 0x7FF
1309 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1310 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1312 #define S_RTE_READ_REQ_SELECT 31
1313 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1314 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1316 struct cpl_rte_delete_rpl {
1317 RSS_HDR union opcode_tid ot;
1322 struct cpl_rte_write_req {
1324 union opcode_tid ot;
1325 #if defined(__LITTLE_ENDIAN_BITFIELD)
1328 __u8 write_l2t_lut:1;
1330 __u8 write_l2t_lut:1;
1342 /* cpl_rte_write_req.lut_params fields */
1343 #define S_RTE_WRITE_REQ_LUT_IX 10
1344 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF
1345 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1346 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1348 #define S_RTE_WRITE_REQ_LUT_BASE 21
1349 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF
1350 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1351 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1353 struct cpl_rte_write_rpl {
1354 RSS_HDR union opcode_tid ot;
1359 struct cpl_rte_read_req {
1361 union opcode_tid ot;
1365 struct cpl_rte_read_rpl {
1366 RSS_HDR union opcode_tid ot;
1370 #if defined(__LITTLE_ENDIAN_BITFIELD)
1381 struct cpl_tid_release {
1383 union opcode_tid ot;
1387 struct cpl_barrier {
1393 struct cpl_rdma_read_req {
1398 struct cpl_rdma_terminate {
1402 #if defined(__LITTLE_ENDIAN_BITFIELD)
1416 /* cpl_rdma_terminate.tid_len fields */
1417 #define S_FLIT_CNT 0
1418 #define M_FLIT_CNT 0xFF
1419 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1420 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1422 #define S_TERM_TID 8
1423 #define M_TERM_TID 0xFFFFF
1424 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1425 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1426 #endif /* T3_CPL_H */