2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/if_vlan.h>
40 #include <linux/mdio.h>
41 #include <linux/sockios.h>
42 #include <linux/workqueue.h>
43 #include <linux/proc_fs.h>
44 #include <linux/rtnetlink.h>
45 #include <linux/firmware.h>
46 #include <linux/log2.h>
47 #include <linux/stringify.h>
48 #include <linux/sched.h>
49 #include <asm/uaccess.h>
52 #include "cxgb3_ioctl.h"
54 #include "cxgb3_offload.h"
57 #include "cxgb3_ctl_defs.h"
59 #include "firmware_exports.h"
62 MAX_TXQ_ENTRIES = 16384,
63 MAX_CTRL_TXQ_ENTRIES = 1024,
64 MAX_RSPQ_ENTRIES = 16384,
65 MAX_RX_BUFFERS = 16384,
66 MAX_RX_JUMBO_BUFFERS = 16384,
68 MIN_CTRL_TXQ_ENTRIES = 4,
69 MIN_RSPQ_ENTRIES = 32,
73 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
75 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
76 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
77 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
79 #define EEPROM_MAGIC 0x38E2F10C
81 #define CH_DEVICE(devid, idx) \
82 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
84 static const struct pci_device_id cxgb3_pci_tbl[] = {
85 CH_DEVICE(0x20, 0), /* PE9000 */
86 CH_DEVICE(0x21, 1), /* T302E */
87 CH_DEVICE(0x22, 2), /* T310E */
88 CH_DEVICE(0x23, 3), /* T320X */
89 CH_DEVICE(0x24, 1), /* T302X */
90 CH_DEVICE(0x25, 3), /* T320E */
91 CH_DEVICE(0x26, 2), /* T310X */
92 CH_DEVICE(0x30, 2), /* T3B10 */
93 CH_DEVICE(0x31, 3), /* T3B20 */
94 CH_DEVICE(0x32, 1), /* T3B02 */
95 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
96 CH_DEVICE(0x36, 3), /* S320E-CR */
97 CH_DEVICE(0x37, 7), /* N320E-G2 */
101 MODULE_DESCRIPTION(DRV_DESC);
102 MODULE_AUTHOR("Chelsio Communications");
103 MODULE_LICENSE("Dual BSD/GPL");
104 MODULE_VERSION(DRV_VERSION);
105 MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
107 static int dflt_msg_enable = DFLT_MSG_ENABLE;
109 module_param(dflt_msg_enable, int, 0644);
110 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
113 * The driver uses the best interrupt scheme available on a platform in the
114 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
115 * of these schemes the driver may consider as follows:
117 * msi = 2: choose from among all three options
118 * msi = 1: only consider MSI and pin interrupts
119 * msi = 0: force pin interrupts
123 module_param(msi, int, 0644);
124 MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
127 * The driver enables offload as a default.
128 * To disable it, use ofld_disable = 1.
131 static int ofld_disable = 0;
133 module_param(ofld_disable, int, 0644);
134 MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
137 * We have work elements that we need to cancel when an interface is taken
138 * down. Normally the work elements would be executed by keventd but that
139 * can deadlock because of linkwatch. If our close method takes the rtnl
140 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
141 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
142 * for our work to complete. Get our own work queue to solve this.
144 struct workqueue_struct *cxgb3_wq;
147 * link_report - show link status and link speed/duplex
148 * @p: the port whose settings are to be reported
150 * Shows the link status, speed, and duplex of a port.
152 static void link_report(struct net_device *dev)
154 if (!netif_carrier_ok(dev))
155 printk(KERN_INFO "%s: link down\n", dev->name);
157 const char *s = "10Mbps";
158 const struct port_info *p = netdev_priv(dev);
160 switch (p->link_config.speed) {
172 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
173 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
177 static void enable_tx_fifo_drain(struct adapter *adapter,
178 struct port_info *pi)
180 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0,
182 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0);
183 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN);
184 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN);
187 static void disable_tx_fifo_drain(struct adapter *adapter,
188 struct port_info *pi)
190 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset,
194 void t3_os_link_fault(struct adapter *adap, int port_id, int state)
196 struct net_device *dev = adap->port[port_id];
197 struct port_info *pi = netdev_priv(dev);
199 if (state == netif_carrier_ok(dev))
203 struct cmac *mac = &pi->mac;
205 netif_carrier_on(dev);
207 disable_tx_fifo_drain(adap, pi);
209 /* Clear local faults */
210 t3_xgm_intr_disable(adap, pi->port_id);
211 t3_read_reg(adap, A_XGM_INT_STATUS +
214 A_XGM_INT_CAUSE + pi->mac.offset,
217 t3_set_reg_field(adap,
220 F_XGM_INT, F_XGM_INT);
221 t3_xgm_intr_enable(adap, pi->port_id);
223 t3_mac_enable(mac, MAC_DIRECTION_TX);
225 netif_carrier_off(dev);
228 enable_tx_fifo_drain(adap, pi);
234 * t3_os_link_changed - handle link status changes
235 * @adapter: the adapter associated with the link change
236 * @port_id: the port index whose limk status has changed
237 * @link_stat: the new status of the link
238 * @speed: the new speed setting
239 * @duplex: the new duplex setting
240 * @pause: the new flow-control setting
242 * This is the OS-dependent handler for link status changes. The OS
243 * neutral handler takes care of most of the processing for these events,
244 * then calls this handler for any OS-specific processing.
246 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
247 int speed, int duplex, int pause)
249 struct net_device *dev = adapter->port[port_id];
250 struct port_info *pi = netdev_priv(dev);
251 struct cmac *mac = &pi->mac;
253 /* Skip changes from disabled ports. */
254 if (!netif_running(dev))
257 if (link_stat != netif_carrier_ok(dev)) {
259 disable_tx_fifo_drain(adapter, pi);
261 t3_mac_enable(mac, MAC_DIRECTION_RX);
263 /* Clear local faults */
264 t3_xgm_intr_disable(adapter, pi->port_id);
265 t3_read_reg(adapter, A_XGM_INT_STATUS +
267 t3_write_reg(adapter,
268 A_XGM_INT_CAUSE + pi->mac.offset,
271 t3_set_reg_field(adapter,
272 A_XGM_INT_ENABLE + pi->mac.offset,
273 F_XGM_INT, F_XGM_INT);
274 t3_xgm_intr_enable(adapter, pi->port_id);
276 netif_carrier_on(dev);
278 netif_carrier_off(dev);
280 t3_xgm_intr_disable(adapter, pi->port_id);
281 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
282 t3_set_reg_field(adapter,
283 A_XGM_INT_ENABLE + pi->mac.offset,
287 pi->phy.ops->power_down(&pi->phy, 1);
289 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
290 t3_mac_disable(mac, MAC_DIRECTION_RX);
291 t3_link_start(&pi->phy, mac, &pi->link_config);
294 enable_tx_fifo_drain(adapter, pi);
302 * t3_os_phymod_changed - handle PHY module changes
303 * @phy: the PHY reporting the module change
304 * @mod_type: new module type
306 * This is the OS-dependent handler for PHY module changes. It is
307 * invoked when a PHY module is removed or inserted for any OS-specific
310 void t3_os_phymod_changed(struct adapter *adap, int port_id)
312 static const char *mod_str[] = {
313 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
316 const struct net_device *dev = adap->port[port_id];
317 const struct port_info *pi = netdev_priv(dev);
319 if (pi->phy.modtype == phy_modtype_none)
320 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
322 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
323 mod_str[pi->phy.modtype]);
326 static void cxgb_set_rxmode(struct net_device *dev)
328 struct t3_rx_mode rm;
329 struct port_info *pi = netdev_priv(dev);
331 init_rx_mode(&rm, dev, dev->mc_list);
332 t3_mac_set_rx_mode(&pi->mac, &rm);
336 * link_start - enable a port
337 * @dev: the device to enable
339 * Performs the MAC and PHY actions needed to enable a port.
341 static void link_start(struct net_device *dev)
343 struct t3_rx_mode rm;
344 struct port_info *pi = netdev_priv(dev);
345 struct cmac *mac = &pi->mac;
347 init_rx_mode(&rm, dev, dev->mc_list);
349 t3_mac_set_num_ucast(mac, MAX_MAC_IDX);
350 t3_mac_set_mtu(mac, dev->mtu);
351 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
352 t3_mac_set_address(mac, SAN_MAC_IDX, pi->iscsic.mac_addr);
353 t3_mac_set_rx_mode(mac, &rm);
354 t3_link_start(&pi->phy, mac, &pi->link_config);
355 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
358 static inline void cxgb_disable_msi(struct adapter *adapter)
360 if (adapter->flags & USING_MSIX) {
361 pci_disable_msix(adapter->pdev);
362 adapter->flags &= ~USING_MSIX;
363 } else if (adapter->flags & USING_MSI) {
364 pci_disable_msi(adapter->pdev);
365 adapter->flags &= ~USING_MSI;
370 * Interrupt handler for asynchronous events used with MSI-X.
372 static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
374 t3_slow_intr_handler(cookie);
379 * Name the MSI-X interrupts.
381 static void name_msix_vecs(struct adapter *adap)
383 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
385 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
386 adap->msix_info[0].desc[n] = 0;
388 for_each_port(adap, j) {
389 struct net_device *d = adap->port[j];
390 const struct port_info *pi = netdev_priv(d);
392 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
393 snprintf(adap->msix_info[msi_idx].desc, n,
394 "%s-%d", d->name, pi->first_qset + i);
395 adap->msix_info[msi_idx].desc[n] = 0;
400 static int request_msix_data_irqs(struct adapter *adap)
402 int i, j, err, qidx = 0;
404 for_each_port(adap, i) {
405 int nqsets = adap2pinfo(adap, i)->nqsets;
407 for (j = 0; j < nqsets; ++j) {
408 err = request_irq(adap->msix_info[qidx + 1].vec,
409 t3_intr_handler(adap,
412 adap->msix_info[qidx + 1].desc,
413 &adap->sge.qs[qidx]);
416 free_irq(adap->msix_info[qidx + 1].vec,
417 &adap->sge.qs[qidx]);
426 static void free_irq_resources(struct adapter *adapter)
428 if (adapter->flags & USING_MSIX) {
431 free_irq(adapter->msix_info[0].vec, adapter);
432 for_each_port(adapter, i)
433 n += adap2pinfo(adapter, i)->nqsets;
435 for (i = 0; i < n; ++i)
436 free_irq(adapter->msix_info[i + 1].vec,
437 &adapter->sge.qs[i]);
439 free_irq(adapter->pdev->irq, adapter);
442 static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
447 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
455 static int init_tp_parity(struct adapter *adap)
459 struct cpl_set_tcb_field *greq;
460 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
462 t3_tp_set_offload_mode(adap, 1);
464 for (i = 0; i < 16; i++) {
465 struct cpl_smt_write_req *req;
467 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
469 skb = adap->nofail_skb;
473 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
474 memset(req, 0, sizeof(*req));
475 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
476 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
477 req->mtu_idx = NMTUS - 1;
479 t3_mgmt_tx(adap, skb);
480 if (skb == adap->nofail_skb) {
481 await_mgmt_replies(adap, cnt, i + 1);
482 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
483 if (!adap->nofail_skb)
488 for (i = 0; i < 2048; i++) {
489 struct cpl_l2t_write_req *req;
491 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
493 skb = adap->nofail_skb;
497 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
498 memset(req, 0, sizeof(*req));
499 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
500 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
501 req->params = htonl(V_L2T_W_IDX(i));
502 t3_mgmt_tx(adap, skb);
503 if (skb == adap->nofail_skb) {
504 await_mgmt_replies(adap, cnt, 16 + i + 1);
505 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
506 if (!adap->nofail_skb)
511 for (i = 0; i < 2048; i++) {
512 struct cpl_rte_write_req *req;
514 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
516 skb = adap->nofail_skb;
520 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
521 memset(req, 0, sizeof(*req));
522 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
523 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
524 req->l2t_idx = htonl(V_L2T_W_IDX(i));
525 t3_mgmt_tx(adap, skb);
526 if (skb == adap->nofail_skb) {
527 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
528 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
529 if (!adap->nofail_skb)
534 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
536 skb = adap->nofail_skb;
540 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
541 memset(greq, 0, sizeof(*greq));
542 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
543 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
544 greq->mask = cpu_to_be64(1);
545 t3_mgmt_tx(adap, skb);
547 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
548 if (skb == adap->nofail_skb) {
549 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
550 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
553 t3_tp_set_offload_mode(adap, 0);
557 t3_tp_set_offload_mode(adap, 0);
562 * setup_rss - configure RSS
565 * Sets up RSS to distribute packets to multiple receive queues. We
566 * configure the RSS CPU lookup table to distribute to the number of HW
567 * receive queues, and the response queue lookup table to narrow that
568 * down to the response queues actually configured for each port.
569 * We always configure the RSS mapping for two ports since the mapping
570 * table has plenty of entries.
572 static void setup_rss(struct adapter *adap)
575 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
576 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
577 u8 cpus[SGE_QSETS + 1];
578 u16 rspq_map[RSS_TABLE_SIZE];
580 for (i = 0; i < SGE_QSETS; ++i)
582 cpus[SGE_QSETS] = 0xff; /* terminator */
584 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
585 rspq_map[i] = i % nq0;
586 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
589 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
590 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
591 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
594 static void ring_dbs(struct adapter *adap)
598 for (i = 0; i < SGE_QSETS; i++) {
599 struct sge_qset *qs = &adap->sge.qs[i];
602 for (j = 0; j < SGE_TXQ_PER_SET; j++)
603 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(qs->txq[j].cntxt_id));
607 static void init_napi(struct adapter *adap)
611 for (i = 0; i < SGE_QSETS; i++) {
612 struct sge_qset *qs = &adap->sge.qs[i];
615 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
620 * netif_napi_add() can be called only once per napi_struct because it
621 * adds each new napi_struct to a list. Be careful not to call it a
622 * second time, e.g., during EEH recovery, by making a note of it.
624 adap->flags |= NAPI_INIT;
628 * Wait until all NAPI handlers are descheduled. This includes the handlers of
629 * both netdevices representing interfaces and the dummy ones for the extra
632 static void quiesce_rx(struct adapter *adap)
636 for (i = 0; i < SGE_QSETS; i++)
637 if (adap->sge.qs[i].adap)
638 napi_disable(&adap->sge.qs[i].napi);
641 static void enable_all_napi(struct adapter *adap)
644 for (i = 0; i < SGE_QSETS; i++)
645 if (adap->sge.qs[i].adap)
646 napi_enable(&adap->sge.qs[i].napi);
650 * set_qset_lro - Turn a queue set's LRO capability on and off
651 * @dev: the device the qset is attached to
652 * @qset_idx: the queue set index
653 * @val: the LRO switch
655 * Sets LRO on or off for a particular queue set.
656 * the device's features flag is updated to reflect the LRO
657 * capability when all queues belonging to the device are
660 static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
662 struct port_info *pi = netdev_priv(dev);
663 struct adapter *adapter = pi->adapter;
665 adapter->params.sge.qset[qset_idx].lro = !!val;
666 adapter->sge.qs[qset_idx].lro_enabled = !!val;
670 * setup_sge_qsets - configure SGE Tx/Rx/response queues
673 * Determines how many sets of SGE queues to use and initializes them.
674 * We support multiple queue sets per port if we have MSI-X, otherwise
675 * just one queue set per port.
677 static int setup_sge_qsets(struct adapter *adap)
679 int i, j, err, irq_idx = 0, qset_idx = 0;
680 unsigned int ntxq = SGE_TXQ_PER_SET;
682 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
685 for_each_port(adap, i) {
686 struct net_device *dev = adap->port[i];
687 struct port_info *pi = netdev_priv(dev);
689 pi->qs = &adap->sge.qs[pi->first_qset];
690 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) {
691 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
692 err = t3_sge_alloc_qset(adap, qset_idx, 1,
693 (adap->flags & USING_MSIX) ? qset_idx + 1 :
695 &adap->params.sge.qset[qset_idx], ntxq, dev,
696 netdev_get_tx_queue(dev, j));
698 t3_free_sge_resources(adap);
707 static ssize_t attr_show(struct device *d, char *buf,
708 ssize_t(*format) (struct net_device *, char *))
712 /* Synchronize with ioctls that may shut down the device */
714 len = (*format) (to_net_dev(d), buf);
719 static ssize_t attr_store(struct device *d,
720 const char *buf, size_t len,
721 ssize_t(*set) (struct net_device *, unsigned int),
722 unsigned int min_val, unsigned int max_val)
728 if (!capable(CAP_NET_ADMIN))
731 val = simple_strtoul(buf, &endp, 0);
732 if (endp == buf || val < min_val || val > max_val)
736 ret = (*set) (to_net_dev(d), val);
743 #define CXGB3_SHOW(name, val_expr) \
744 static ssize_t format_##name(struct net_device *dev, char *buf) \
746 struct port_info *pi = netdev_priv(dev); \
747 struct adapter *adap = pi->adapter; \
748 return sprintf(buf, "%u\n", val_expr); \
750 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
753 return attr_show(d, buf, format_##name); \
756 static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
758 struct port_info *pi = netdev_priv(dev);
759 struct adapter *adap = pi->adapter;
760 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
762 if (adap->flags & FULL_INIT_DONE)
764 if (val && adap->params.rev == 0)
766 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
769 adap->params.mc5.nfilters = val;
773 static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
774 const char *buf, size_t len)
776 return attr_store(d, buf, len, set_nfilters, 0, ~0);
779 static ssize_t set_nservers(struct net_device *dev, unsigned int val)
781 struct port_info *pi = netdev_priv(dev);
782 struct adapter *adap = pi->adapter;
784 if (adap->flags & FULL_INIT_DONE)
786 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
789 adap->params.mc5.nservers = val;
793 static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
794 const char *buf, size_t len)
796 return attr_store(d, buf, len, set_nservers, 0, ~0);
799 #define CXGB3_ATTR_R(name, val_expr) \
800 CXGB3_SHOW(name, val_expr) \
801 static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
803 #define CXGB3_ATTR_RW(name, val_expr, store_method) \
804 CXGB3_SHOW(name, val_expr) \
805 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
807 CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
808 CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
809 CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
811 static struct attribute *cxgb3_attrs[] = {
812 &dev_attr_cam_size.attr,
813 &dev_attr_nfilters.attr,
814 &dev_attr_nservers.attr,
818 static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
820 static ssize_t tm_attr_show(struct device *d,
821 char *buf, int sched)
823 struct port_info *pi = netdev_priv(to_net_dev(d));
824 struct adapter *adap = pi->adapter;
825 unsigned int v, addr, bpt, cpt;
828 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
830 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
831 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
834 bpt = (v >> 8) & 0xff;
837 len = sprintf(buf, "disabled\n");
839 v = (adap->params.vpd.cclk * 1000) / cpt;
840 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
846 static ssize_t tm_attr_store(struct device *d,
847 const char *buf, size_t len, int sched)
849 struct port_info *pi = netdev_priv(to_net_dev(d));
850 struct adapter *adap = pi->adapter;
855 if (!capable(CAP_NET_ADMIN))
858 val = simple_strtoul(buf, &endp, 0);
859 if (endp == buf || val > 10000000)
863 ret = t3_config_sched(adap, val, sched);
870 #define TM_ATTR(name, sched) \
871 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
874 return tm_attr_show(d, buf, sched); \
876 static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
877 const char *buf, size_t len) \
879 return tm_attr_store(d, buf, len, sched); \
881 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
892 static struct attribute *offload_attrs[] = {
893 &dev_attr_sched0.attr,
894 &dev_attr_sched1.attr,
895 &dev_attr_sched2.attr,
896 &dev_attr_sched3.attr,
897 &dev_attr_sched4.attr,
898 &dev_attr_sched5.attr,
899 &dev_attr_sched6.attr,
900 &dev_attr_sched7.attr,
904 static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
907 * Sends an sk_buff to an offload queue driver
908 * after dealing with any active network taps.
910 static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
915 ret = t3_offload_tx(tdev, skb);
920 static int write_smt_entry(struct adapter *adapter, int idx)
922 struct cpl_smt_write_req *req;
923 struct port_info *pi = netdev_priv(adapter->port[idx]);
924 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
929 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
930 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
931 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
932 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
934 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
935 memcpy(req->src_mac1, pi->iscsic.mac_addr, ETH_ALEN);
937 offload_tx(&adapter->tdev, skb);
941 static int init_smt(struct adapter *adapter)
945 for_each_port(adapter, i)
946 write_smt_entry(adapter, i);
950 static void init_port_mtus(struct adapter *adapter)
952 unsigned int mtus = adapter->port[0]->mtu;
954 if (adapter->port[1])
955 mtus |= adapter->port[1]->mtu << 16;
956 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
959 static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
963 struct mngt_pktsched_wr *req;
966 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
968 skb = adap->nofail_skb;
972 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
973 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
974 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
980 ret = t3_mgmt_tx(adap, skb);
981 if (skb == adap->nofail_skb) {
982 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
984 if (!adap->nofail_skb)
991 static int bind_qsets(struct adapter *adap)
995 for_each_port(adap, i) {
996 const struct port_info *pi = adap2pinfo(adap, i);
998 for (j = 0; j < pi->nqsets; ++j) {
999 int ret = send_pktsched_cmd(adap, 1,
1000 pi->first_qset + j, -1,
1010 #define FW_VERSION __stringify(FW_VERSION_MAJOR) "." \
1011 __stringify(FW_VERSION_MINOR) "." __stringify(FW_VERSION_MICRO)
1012 #define FW_FNAME "cxgb3/t3fw-" FW_VERSION ".bin"
1013 #define TPSRAM_VERSION __stringify(TP_VERSION_MAJOR) "." \
1014 __stringify(TP_VERSION_MINOR) "." __stringify(TP_VERSION_MICRO)
1015 #define TPSRAM_NAME "cxgb3/t3%c_psram-" TPSRAM_VERSION ".bin"
1016 #define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
1017 #define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
1018 #define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
1019 MODULE_FIRMWARE(FW_FNAME);
1020 MODULE_FIRMWARE("cxgb3/t3b_psram-" TPSRAM_VERSION ".bin");
1021 MODULE_FIRMWARE("cxgb3/t3c_psram-" TPSRAM_VERSION ".bin");
1022 MODULE_FIRMWARE(AEL2005_OPT_EDC_NAME);
1023 MODULE_FIRMWARE(AEL2005_TWX_EDC_NAME);
1024 MODULE_FIRMWARE(AEL2020_TWX_EDC_NAME);
1026 static inline const char *get_edc_fw_name(int edc_idx)
1028 const char *fw_name = NULL;
1031 case EDC_OPT_AEL2005:
1032 fw_name = AEL2005_OPT_EDC_NAME;
1034 case EDC_TWX_AEL2005:
1035 fw_name = AEL2005_TWX_EDC_NAME;
1037 case EDC_TWX_AEL2020:
1038 fw_name = AEL2020_TWX_EDC_NAME;
1044 int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
1046 struct adapter *adapter = phy->adapter;
1047 const struct firmware *fw;
1051 u16 *cache = phy->phy_cache;
1054 snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));
1056 ret = request_firmware(&fw, buf, &adapter->pdev->dev);
1058 dev_err(&adapter->pdev->dev,
1059 "could not upgrade firmware: unable to load %s\n",
1064 /* check size, take checksum in account */
1065 if (fw->size > size + 4) {
1066 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1067 (unsigned int)fw->size, size + 4);
1071 /* compute checksum */
1072 p = (const __be32 *)fw->data;
1073 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1074 csum += ntohl(p[i]);
1076 if (csum != 0xffffffff) {
1077 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1082 for (i = 0; i < size / 4 ; i++) {
1083 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1084 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1087 release_firmware(fw);
1092 static int upgrade_fw(struct adapter *adap)
1095 const struct firmware *fw;
1096 struct device *dev = &adap->pdev->dev;
1098 ret = request_firmware(&fw, FW_FNAME, dev);
1100 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
1104 ret = t3_load_fw(adap, fw->data, fw->size);
1105 release_firmware(fw);
1108 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1109 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1111 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1112 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1117 static inline char t3rev2char(struct adapter *adapter)
1121 switch(adapter->params.rev) {
1133 static int update_tpsram(struct adapter *adap)
1135 const struct firmware *tpsram;
1137 struct device *dev = &adap->pdev->dev;
1141 rev = t3rev2char(adap);
1145 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev);
1147 ret = request_firmware(&tpsram, buf, dev);
1149 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1154 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1156 goto release_tpsram;
1158 ret = t3_set_proto_sram(adap, tpsram->data);
1161 "successful update of protocol engine "
1163 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1165 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1166 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1168 dev_err(dev, "loading protocol SRAM failed\n");
1171 release_firmware(tpsram);
1177 * cxgb_up - enable the adapter
1178 * @adapter: adapter being enabled
1180 * Called when the first port is enabled, this function performs the
1181 * actions necessary to make an adapter operational, such as completing
1182 * the initialization of HW modules, and enabling interrupts.
1184 * Must be called with the rtnl lock held.
1186 static int cxgb_up(struct adapter *adap)
1190 if (!(adap->flags & FULL_INIT_DONE)) {
1191 err = t3_check_fw_version(adap);
1192 if (err == -EINVAL) {
1193 err = upgrade_fw(adap);
1194 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1195 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1196 FW_VERSION_MICRO, err ? "failed" : "succeeded");
1199 err = t3_check_tpsram_version(adap);
1200 if (err == -EINVAL) {
1201 err = update_tpsram(adap);
1202 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1203 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1204 TP_VERSION_MICRO, err ? "failed" : "succeeded");
1208 * Clear interrupts now to catch errors if t3_init_hw fails.
1209 * We clear them again later as initialization may trigger
1210 * conditions that can interrupt.
1212 t3_intr_clear(adap);
1214 err = t3_init_hw(adap, 0);
1218 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
1219 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1221 err = setup_sge_qsets(adap);
1226 if (!(adap->flags & NAPI_INIT))
1229 t3_start_sge_timers(adap);
1230 adap->flags |= FULL_INIT_DONE;
1233 t3_intr_clear(adap);
1235 if (adap->flags & USING_MSIX) {
1236 name_msix_vecs(adap);
1237 err = request_irq(adap->msix_info[0].vec,
1238 t3_async_intr_handler, 0,
1239 adap->msix_info[0].desc, adap);
1243 err = request_msix_data_irqs(adap);
1245 free_irq(adap->msix_info[0].vec, adap);
1248 } else if ((err = request_irq(adap->pdev->irq,
1249 t3_intr_handler(adap,
1250 adap->sge.qs[0].rspq.
1252 (adap->flags & USING_MSI) ?
1257 enable_all_napi(adap);
1259 t3_intr_enable(adap);
1261 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1262 is_offload(adap) && init_tp_parity(adap) == 0)
1263 adap->flags |= TP_PARITY_INIT;
1265 if (adap->flags & TP_PARITY_INIT) {
1266 t3_write_reg(adap, A_TP_INT_CAUSE,
1267 F_CMCACHEPERR | F_ARPLUTPERR);
1268 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1271 if (!(adap->flags & QUEUES_BOUND)) {
1272 err = bind_qsets(adap);
1274 CH_ERR(adap, "failed to bind qsets, err %d\n", err);
1275 t3_intr_disable(adap);
1276 free_irq_resources(adap);
1279 adap->flags |= QUEUES_BOUND;
1285 CH_ERR(adap, "request_irq failed, err %d\n", err);
1290 * Release resources when all the ports and offloading have been stopped.
1292 static void cxgb_down(struct adapter *adapter)
1294 t3_sge_stop(adapter);
1295 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1296 t3_intr_disable(adapter);
1297 spin_unlock_irq(&adapter->work_lock);
1299 free_irq_resources(adapter);
1300 quiesce_rx(adapter);
1301 flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */
1304 static void schedule_chk_task(struct adapter *adap)
1308 timeo = adap->params.linkpoll_period ?
1309 (HZ * adap->params.linkpoll_period) / 10 :
1310 adap->params.stats_update_period * HZ;
1312 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1315 static int offload_open(struct net_device *dev)
1317 struct port_info *pi = netdev_priv(dev);
1318 struct adapter *adapter = pi->adapter;
1319 struct t3cdev *tdev = dev2t3cdev(dev);
1320 int adap_up = adapter->open_device_map & PORT_MASK;
1323 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1326 if (!adap_up && (err = cxgb_up(adapter)) < 0)
1329 t3_tp_set_offload_mode(adapter, 1);
1330 tdev->lldev = adapter->port[0];
1331 err = cxgb3_offload_activate(adapter);
1335 init_port_mtus(adapter);
1336 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1337 adapter->params.b_wnd,
1338 adapter->params.rev == 0 ?
1339 adapter->port[0]->mtu : 0xffff);
1342 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1343 dev_dbg(&dev->dev, "cannot create sysfs group\n");
1345 /* Call back all registered clients */
1346 cxgb3_add_clients(tdev);
1349 /* restore them in case the offload module has changed them */
1351 t3_tp_set_offload_mode(adapter, 0);
1352 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1353 cxgb3_set_dummy_ops(tdev);
1358 static int offload_close(struct t3cdev *tdev)
1360 struct adapter *adapter = tdev2adap(tdev);
1362 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1365 /* Call back all registered clients */
1366 cxgb3_remove_clients(tdev);
1368 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
1370 /* Flush work scheduled while releasing TIDs */
1371 flush_scheduled_work();
1374 cxgb3_set_dummy_ops(tdev);
1375 t3_tp_set_offload_mode(adapter, 0);
1376 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1378 if (!adapter->open_device_map)
1381 cxgb3_offload_deactivate(adapter);
1385 static int cxgb_open(struct net_device *dev)
1387 struct port_info *pi = netdev_priv(dev);
1388 struct adapter *adapter = pi->adapter;
1389 int other_ports = adapter->open_device_map & PORT_MASK;
1392 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
1395 set_bit(pi->port_id, &adapter->open_device_map);
1396 if (is_offload(adapter) && !ofld_disable) {
1397 err = offload_open(dev);
1400 "Could not initialize offload capabilities\n");
1403 dev->real_num_tx_queues = pi->nqsets;
1405 t3_port_intr_enable(adapter, pi->port_id);
1406 netif_tx_start_all_queues(dev);
1408 schedule_chk_task(adapter);
1410 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_UP, pi->port_id);
1414 static int cxgb_close(struct net_device *dev)
1416 struct port_info *pi = netdev_priv(dev);
1417 struct adapter *adapter = pi->adapter;
1420 if (!adapter->open_device_map)
1423 /* Stop link fault interrupts */
1424 t3_xgm_intr_disable(adapter, pi->port_id);
1425 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1427 t3_port_intr_disable(adapter, pi->port_id);
1428 netif_tx_stop_all_queues(dev);
1429 pi->phy.ops->power_down(&pi->phy, 1);
1430 netif_carrier_off(dev);
1431 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
1433 spin_lock_irq(&adapter->work_lock); /* sync with update task */
1434 clear_bit(pi->port_id, &adapter->open_device_map);
1435 spin_unlock_irq(&adapter->work_lock);
1437 if (!(adapter->open_device_map & PORT_MASK))
1438 cancel_delayed_work_sync(&adapter->adap_check_task);
1440 if (!adapter->open_device_map)
1443 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_DOWN, pi->port_id);
1447 static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1449 struct port_info *pi = netdev_priv(dev);
1450 struct adapter *adapter = pi->adapter;
1451 struct net_device_stats *ns = &pi->netstats;
1452 const struct mac_stats *pstats;
1454 spin_lock(&adapter->stats_lock);
1455 pstats = t3_mac_update_stats(&pi->mac);
1456 spin_unlock(&adapter->stats_lock);
1458 ns->tx_bytes = pstats->tx_octets;
1459 ns->tx_packets = pstats->tx_frames;
1460 ns->rx_bytes = pstats->rx_octets;
1461 ns->rx_packets = pstats->rx_frames;
1462 ns->multicast = pstats->rx_mcast_frames;
1464 ns->tx_errors = pstats->tx_underrun;
1465 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1466 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1467 pstats->rx_fifo_ovfl;
1469 /* detailed rx_errors */
1470 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1471 ns->rx_over_errors = 0;
1472 ns->rx_crc_errors = pstats->rx_fcs_errs;
1473 ns->rx_frame_errors = pstats->rx_symbol_errs;
1474 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1475 ns->rx_missed_errors = pstats->rx_cong_drops;
1477 /* detailed tx_errors */
1478 ns->tx_aborted_errors = 0;
1479 ns->tx_carrier_errors = 0;
1480 ns->tx_fifo_errors = pstats->tx_underrun;
1481 ns->tx_heartbeat_errors = 0;
1482 ns->tx_window_errors = 0;
1486 static u32 get_msglevel(struct net_device *dev)
1488 struct port_info *pi = netdev_priv(dev);
1489 struct adapter *adapter = pi->adapter;
1491 return adapter->msg_enable;
1494 static void set_msglevel(struct net_device *dev, u32 val)
1496 struct port_info *pi = netdev_priv(dev);
1497 struct adapter *adapter = pi->adapter;
1499 adapter->msg_enable = val;
1502 static char stats_strings[][ETH_GSTRING_LEN] = {
1505 "TxMulticastFramesOK",
1506 "TxBroadcastFramesOK",
1513 "TxFrames128To255 ",
1514 "TxFrames256To511 ",
1515 "TxFrames512To1023 ",
1516 "TxFrames1024To1518 ",
1517 "TxFrames1519ToMax ",
1521 "RxMulticastFramesOK",
1522 "RxBroadcastFramesOK",
1533 "RxFrames128To255 ",
1534 "RxFrames256To511 ",
1535 "RxFrames512To1023 ",
1536 "RxFrames1024To1518 ",
1537 "RxFrames1519ToMax ",
1550 "CheckTXEnToggled ",
1556 static int get_sset_count(struct net_device *dev, int sset)
1560 return ARRAY_SIZE(stats_strings);
1566 #define T3_REGMAP_SIZE (3 * 1024)
1568 static int get_regs_len(struct net_device *dev)
1570 return T3_REGMAP_SIZE;
1573 static int get_eeprom_len(struct net_device *dev)
1578 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1580 struct port_info *pi = netdev_priv(dev);
1581 struct adapter *adapter = pi->adapter;
1585 spin_lock(&adapter->stats_lock);
1586 t3_get_fw_version(adapter, &fw_vers);
1587 t3_get_tp_version(adapter, &tp_vers);
1588 spin_unlock(&adapter->stats_lock);
1590 strcpy(info->driver, DRV_NAME);
1591 strcpy(info->version, DRV_VERSION);
1592 strcpy(info->bus_info, pci_name(adapter->pdev));
1594 strcpy(info->fw_version, "N/A");
1596 snprintf(info->fw_version, sizeof(info->fw_version),
1597 "%s %u.%u.%u TP %u.%u.%u",
1598 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1599 G_FW_VERSION_MAJOR(fw_vers),
1600 G_FW_VERSION_MINOR(fw_vers),
1601 G_FW_VERSION_MICRO(fw_vers),
1602 G_TP_VERSION_MAJOR(tp_vers),
1603 G_TP_VERSION_MINOR(tp_vers),
1604 G_TP_VERSION_MICRO(tp_vers));
1608 static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1610 if (stringset == ETH_SS_STATS)
1611 memcpy(data, stats_strings, sizeof(stats_strings));
1614 static unsigned long collect_sge_port_stats(struct adapter *adapter,
1615 struct port_info *p, int idx)
1618 unsigned long tot = 0;
1620 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1621 tot += adapter->sge.qs[i].port_stats[idx];
1625 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1628 struct port_info *pi = netdev_priv(dev);
1629 struct adapter *adapter = pi->adapter;
1630 const struct mac_stats *s;
1632 spin_lock(&adapter->stats_lock);
1633 s = t3_mac_update_stats(&pi->mac);
1634 spin_unlock(&adapter->stats_lock);
1636 *data++ = s->tx_octets;
1637 *data++ = s->tx_frames;
1638 *data++ = s->tx_mcast_frames;
1639 *data++ = s->tx_bcast_frames;
1640 *data++ = s->tx_pause;
1641 *data++ = s->tx_underrun;
1642 *data++ = s->tx_fifo_urun;
1644 *data++ = s->tx_frames_64;
1645 *data++ = s->tx_frames_65_127;
1646 *data++ = s->tx_frames_128_255;
1647 *data++ = s->tx_frames_256_511;
1648 *data++ = s->tx_frames_512_1023;
1649 *data++ = s->tx_frames_1024_1518;
1650 *data++ = s->tx_frames_1519_max;
1652 *data++ = s->rx_octets;
1653 *data++ = s->rx_frames;
1654 *data++ = s->rx_mcast_frames;
1655 *data++ = s->rx_bcast_frames;
1656 *data++ = s->rx_pause;
1657 *data++ = s->rx_fcs_errs;
1658 *data++ = s->rx_symbol_errs;
1659 *data++ = s->rx_short;
1660 *data++ = s->rx_jabber;
1661 *data++ = s->rx_too_long;
1662 *data++ = s->rx_fifo_ovfl;
1664 *data++ = s->rx_frames_64;
1665 *data++ = s->rx_frames_65_127;
1666 *data++ = s->rx_frames_128_255;
1667 *data++ = s->rx_frames_256_511;
1668 *data++ = s->rx_frames_512_1023;
1669 *data++ = s->rx_frames_1024_1518;
1670 *data++ = s->rx_frames_1519_max;
1672 *data++ = pi->phy.fifo_errors;
1674 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1675 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1676 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1677 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1678 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
1682 *data++ = s->rx_cong_drops;
1684 *data++ = s->num_toggled;
1685 *data++ = s->num_resets;
1687 *data++ = s->link_faults;
1690 static inline void reg_block_dump(struct adapter *ap, void *buf,
1691 unsigned int start, unsigned int end)
1693 u32 *p = buf + start;
1695 for (; start <= end; start += sizeof(u32))
1696 *p++ = t3_read_reg(ap, start);
1699 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1702 struct port_info *pi = netdev_priv(dev);
1703 struct adapter *ap = pi->adapter;
1707 * bits 0..9: chip version
1708 * bits 10..15: chip revision
1709 * bit 31: set for PCIe cards
1711 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1714 * We skip the MAC statistics registers because they are clear-on-read.
1715 * Also reading multi-register stats would need to synchronize with the
1716 * periodic mac stats accumulation. Hard to justify the complexity.
1718 memset(buf, 0, T3_REGMAP_SIZE);
1719 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1720 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1721 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1722 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1723 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1724 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1725 XGM_REG(A_XGM_SERDES_STAT3, 1));
1726 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1727 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1730 static int restart_autoneg(struct net_device *dev)
1732 struct port_info *p = netdev_priv(dev);
1734 if (!netif_running(dev))
1736 if (p->link_config.autoneg != AUTONEG_ENABLE)
1738 p->phy.ops->autoneg_restart(&p->phy);
1742 static int cxgb3_phys_id(struct net_device *dev, u32 data)
1744 struct port_info *pi = netdev_priv(dev);
1745 struct adapter *adapter = pi->adapter;
1751 for (i = 0; i < data * 2; i++) {
1752 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1753 (i & 1) ? F_GPIO0_OUT_VAL : 0);
1754 if (msleep_interruptible(500))
1757 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1762 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1764 struct port_info *p = netdev_priv(dev);
1766 cmd->supported = p->link_config.supported;
1767 cmd->advertising = p->link_config.advertising;
1769 if (netif_carrier_ok(dev)) {
1770 cmd->speed = p->link_config.speed;
1771 cmd->duplex = p->link_config.duplex;
1777 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
1778 cmd->phy_address = p->phy.mdio.prtad;
1779 cmd->transceiver = XCVR_EXTERNAL;
1780 cmd->autoneg = p->link_config.autoneg;
1786 static int speed_duplex_to_caps(int speed, int duplex)
1792 if (duplex == DUPLEX_FULL)
1793 cap = SUPPORTED_10baseT_Full;
1795 cap = SUPPORTED_10baseT_Half;
1798 if (duplex == DUPLEX_FULL)
1799 cap = SUPPORTED_100baseT_Full;
1801 cap = SUPPORTED_100baseT_Half;
1804 if (duplex == DUPLEX_FULL)
1805 cap = SUPPORTED_1000baseT_Full;
1807 cap = SUPPORTED_1000baseT_Half;
1810 if (duplex == DUPLEX_FULL)
1811 cap = SUPPORTED_10000baseT_Full;
1816 #define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1817 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1818 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1819 ADVERTISED_10000baseT_Full)
1821 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1823 struct port_info *p = netdev_priv(dev);
1824 struct link_config *lc = &p->link_config;
1826 if (!(lc->supported & SUPPORTED_Autoneg)) {
1828 * PHY offers a single speed/duplex. See if that's what's
1831 if (cmd->autoneg == AUTONEG_DISABLE) {
1832 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1833 if (lc->supported & cap)
1839 if (cmd->autoneg == AUTONEG_DISABLE) {
1840 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1842 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1844 lc->requested_speed = cmd->speed;
1845 lc->requested_duplex = cmd->duplex;
1846 lc->advertising = 0;
1848 cmd->advertising &= ADVERTISED_MASK;
1849 cmd->advertising &= lc->supported;
1850 if (!cmd->advertising)
1852 lc->requested_speed = SPEED_INVALID;
1853 lc->requested_duplex = DUPLEX_INVALID;
1854 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1856 lc->autoneg = cmd->autoneg;
1857 if (netif_running(dev))
1858 t3_link_start(&p->phy, &p->mac, lc);
1862 static void get_pauseparam(struct net_device *dev,
1863 struct ethtool_pauseparam *epause)
1865 struct port_info *p = netdev_priv(dev);
1867 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1868 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1869 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1872 static int set_pauseparam(struct net_device *dev,
1873 struct ethtool_pauseparam *epause)
1875 struct port_info *p = netdev_priv(dev);
1876 struct link_config *lc = &p->link_config;
1878 if (epause->autoneg == AUTONEG_DISABLE)
1879 lc->requested_fc = 0;
1880 else if (lc->supported & SUPPORTED_Autoneg)
1881 lc->requested_fc = PAUSE_AUTONEG;
1885 if (epause->rx_pause)
1886 lc->requested_fc |= PAUSE_RX;
1887 if (epause->tx_pause)
1888 lc->requested_fc |= PAUSE_TX;
1889 if (lc->autoneg == AUTONEG_ENABLE) {
1890 if (netif_running(dev))
1891 t3_link_start(&p->phy, &p->mac, lc);
1893 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1894 if (netif_running(dev))
1895 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1900 static u32 get_rx_csum(struct net_device *dev)
1902 struct port_info *p = netdev_priv(dev);
1904 return p->rx_offload & T3_RX_CSUM;
1907 static int set_rx_csum(struct net_device *dev, u32 data)
1909 struct port_info *p = netdev_priv(dev);
1912 p->rx_offload |= T3_RX_CSUM;
1916 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
1917 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1918 set_qset_lro(dev, i, 0);
1923 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1925 struct port_info *pi = netdev_priv(dev);
1926 struct adapter *adapter = pi->adapter;
1927 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
1929 e->rx_max_pending = MAX_RX_BUFFERS;
1930 e->rx_mini_max_pending = 0;
1931 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1932 e->tx_max_pending = MAX_TXQ_ENTRIES;
1934 e->rx_pending = q->fl_size;
1935 e->rx_mini_pending = q->rspq_size;
1936 e->rx_jumbo_pending = q->jumbo_size;
1937 e->tx_pending = q->txq_size[0];
1940 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1942 struct port_info *pi = netdev_priv(dev);
1943 struct adapter *adapter = pi->adapter;
1944 struct qset_params *q;
1947 if (e->rx_pending > MAX_RX_BUFFERS ||
1948 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1949 e->tx_pending > MAX_TXQ_ENTRIES ||
1950 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1951 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1952 e->rx_pending < MIN_FL_ENTRIES ||
1953 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1954 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1957 if (adapter->flags & FULL_INIT_DONE)
1960 q = &adapter->params.sge.qset[pi->first_qset];
1961 for (i = 0; i < pi->nqsets; ++i, ++q) {
1962 q->rspq_size = e->rx_mini_pending;
1963 q->fl_size = e->rx_pending;
1964 q->jumbo_size = e->rx_jumbo_pending;
1965 q->txq_size[0] = e->tx_pending;
1966 q->txq_size[1] = e->tx_pending;
1967 q->txq_size[2] = e->tx_pending;
1972 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1974 struct port_info *pi = netdev_priv(dev);
1975 struct adapter *adapter = pi->adapter;
1976 struct qset_params *qsp = &adapter->params.sge.qset[0];
1977 struct sge_qset *qs = &adapter->sge.qs[0];
1979 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1982 qsp->coalesce_usecs = c->rx_coalesce_usecs;
1983 t3_update_qset_coalesce(qs, qsp);
1987 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1989 struct port_info *pi = netdev_priv(dev);
1990 struct adapter *adapter = pi->adapter;
1991 struct qset_params *q = adapter->params.sge.qset;
1993 c->rx_coalesce_usecs = q->coalesce_usecs;
1997 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2000 struct port_info *pi = netdev_priv(dev);
2001 struct adapter *adapter = pi->adapter;
2004 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2008 e->magic = EEPROM_MAGIC;
2009 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2010 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
2013 memcpy(data, buf + e->offset, e->len);
2018 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2021 struct port_info *pi = netdev_priv(dev);
2022 struct adapter *adapter = pi->adapter;
2023 u32 aligned_offset, aligned_len;
2028 if (eeprom->magic != EEPROM_MAGIC)
2031 aligned_offset = eeprom->offset & ~3;
2032 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2034 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2035 buf = kmalloc(aligned_len, GFP_KERNEL);
2038 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
2039 if (!err && aligned_len > 4)
2040 err = t3_seeprom_read(adapter,
2041 aligned_offset + aligned_len - 4,
2042 (__le32 *) & buf[aligned_len - 4]);
2045 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2049 err = t3_seeprom_wp(adapter, 0);
2053 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
2054 err = t3_seeprom_write(adapter, aligned_offset, *p);
2055 aligned_offset += 4;
2059 err = t3_seeprom_wp(adapter, 1);
2066 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2070 memset(&wol->sopass, 0, sizeof(wol->sopass));
2073 static const struct ethtool_ops cxgb_ethtool_ops = {
2074 .get_settings = get_settings,
2075 .set_settings = set_settings,
2076 .get_drvinfo = get_drvinfo,
2077 .get_msglevel = get_msglevel,
2078 .set_msglevel = set_msglevel,
2079 .get_ringparam = get_sge_param,
2080 .set_ringparam = set_sge_param,
2081 .get_coalesce = get_coalesce,
2082 .set_coalesce = set_coalesce,
2083 .get_eeprom_len = get_eeprom_len,
2084 .get_eeprom = get_eeprom,
2085 .set_eeprom = set_eeprom,
2086 .get_pauseparam = get_pauseparam,
2087 .set_pauseparam = set_pauseparam,
2088 .get_rx_csum = get_rx_csum,
2089 .set_rx_csum = set_rx_csum,
2090 .set_tx_csum = ethtool_op_set_tx_csum,
2091 .set_sg = ethtool_op_set_sg,
2092 .get_link = ethtool_op_get_link,
2093 .get_strings = get_strings,
2094 .phys_id = cxgb3_phys_id,
2095 .nway_reset = restart_autoneg,
2096 .get_sset_count = get_sset_count,
2097 .get_ethtool_stats = get_stats,
2098 .get_regs_len = get_regs_len,
2099 .get_regs = get_regs,
2101 .set_tso = ethtool_op_set_tso,
2104 static int in_range(int val, int lo, int hi)
2106 return val < 0 || (val <= hi && val >= lo);
2109 static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2111 struct port_info *pi = netdev_priv(dev);
2112 struct adapter *adapter = pi->adapter;
2116 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2120 case CHELSIO_SET_QSET_PARAMS:{
2122 struct qset_params *q;
2123 struct ch_qset_params t;
2124 int q1 = pi->first_qset;
2125 int nqsets = pi->nqsets;
2127 if (!capable(CAP_NET_ADMIN))
2129 if (copy_from_user(&t, useraddr, sizeof(t)))
2131 if (t.qset_idx >= SGE_QSETS)
2133 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
2134 !in_range(t.cong_thres, 0, 255) ||
2135 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2137 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2139 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2140 MAX_CTRL_TXQ_ENTRIES) ||
2141 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2143 !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2144 MAX_RX_JUMBO_BUFFERS) ||
2145 !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2149 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
2150 for_each_port(adapter, i) {
2151 pi = adap2pinfo(adapter, i);
2152 if (t.qset_idx >= pi->first_qset &&
2153 t.qset_idx < pi->first_qset + pi->nqsets &&
2154 !(pi->rx_offload & T3_RX_CSUM))
2158 if ((adapter->flags & FULL_INIT_DONE) &&
2159 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2160 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2161 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2162 t.polling >= 0 || t.cong_thres >= 0))
2165 /* Allow setting of any available qset when offload enabled */
2166 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2168 for_each_port(adapter, i) {
2169 pi = adap2pinfo(adapter, i);
2170 nqsets += pi->first_qset + pi->nqsets;
2174 if (t.qset_idx < q1)
2176 if (t.qset_idx > q1 + nqsets - 1)
2179 q = &adapter->params.sge.qset[t.qset_idx];
2181 if (t.rspq_size >= 0)
2182 q->rspq_size = t.rspq_size;
2183 if (t.fl_size[0] >= 0)
2184 q->fl_size = t.fl_size[0];
2185 if (t.fl_size[1] >= 0)
2186 q->jumbo_size = t.fl_size[1];
2187 if (t.txq_size[0] >= 0)
2188 q->txq_size[0] = t.txq_size[0];
2189 if (t.txq_size[1] >= 0)
2190 q->txq_size[1] = t.txq_size[1];
2191 if (t.txq_size[2] >= 0)
2192 q->txq_size[2] = t.txq_size[2];
2193 if (t.cong_thres >= 0)
2194 q->cong_thres = t.cong_thres;
2195 if (t.intr_lat >= 0) {
2196 struct sge_qset *qs =
2197 &adapter->sge.qs[t.qset_idx];
2199 q->coalesce_usecs = t.intr_lat;
2200 t3_update_qset_coalesce(qs, q);
2202 if (t.polling >= 0) {
2203 if (adapter->flags & USING_MSIX)
2204 q->polling = t.polling;
2206 /* No polling with INTx for T3A */
2207 if (adapter->params.rev == 0 &&
2208 !(adapter->flags & USING_MSI))
2211 for (i = 0; i < SGE_QSETS; i++) {
2212 q = &adapter->params.sge.
2214 q->polling = t.polling;
2219 set_qset_lro(dev, t.qset_idx, t.lro);
2223 case CHELSIO_GET_QSET_PARAMS:{
2224 struct qset_params *q;
2225 struct ch_qset_params t;
2226 int q1 = pi->first_qset;
2227 int nqsets = pi->nqsets;
2230 if (copy_from_user(&t, useraddr, sizeof(t)))
2233 /* Display qsets for all ports when offload enabled */
2234 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2236 for_each_port(adapter, i) {
2237 pi = adap2pinfo(adapter, i);
2238 nqsets = pi->first_qset + pi->nqsets;
2242 if (t.qset_idx >= nqsets)
2245 q = &adapter->params.sge.qset[q1 + t.qset_idx];
2246 t.rspq_size = q->rspq_size;
2247 t.txq_size[0] = q->txq_size[0];
2248 t.txq_size[1] = q->txq_size[1];
2249 t.txq_size[2] = q->txq_size[2];
2250 t.fl_size[0] = q->fl_size;
2251 t.fl_size[1] = q->jumbo_size;
2252 t.polling = q->polling;
2254 t.intr_lat = q->coalesce_usecs;
2255 t.cong_thres = q->cong_thres;
2258 if (adapter->flags & USING_MSIX)
2259 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2261 t.vector = adapter->pdev->irq;
2263 if (copy_to_user(useraddr, &t, sizeof(t)))
2267 case CHELSIO_SET_QSET_NUM:{
2268 struct ch_reg edata;
2269 unsigned int i, first_qset = 0, other_qsets = 0;
2271 if (!capable(CAP_NET_ADMIN))
2273 if (adapter->flags & FULL_INIT_DONE)
2275 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2277 if (edata.val < 1 ||
2278 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2281 for_each_port(adapter, i)
2282 if (adapter->port[i] && adapter->port[i] != dev)
2283 other_qsets += adap2pinfo(adapter, i)->nqsets;
2285 if (edata.val + other_qsets > SGE_QSETS)
2288 pi->nqsets = edata.val;
2290 for_each_port(adapter, i)
2291 if (adapter->port[i]) {
2292 pi = adap2pinfo(adapter, i);
2293 pi->first_qset = first_qset;
2294 first_qset += pi->nqsets;
2298 case CHELSIO_GET_QSET_NUM:{
2299 struct ch_reg edata;
2301 edata.cmd = CHELSIO_GET_QSET_NUM;
2302 edata.val = pi->nqsets;
2303 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2307 case CHELSIO_LOAD_FW:{
2309 struct ch_mem_range t;
2311 if (!capable(CAP_SYS_RAWIO))
2313 if (copy_from_user(&t, useraddr, sizeof(t)))
2315 /* Check t.len sanity ? */
2316 fw_data = kmalloc(t.len, GFP_KERNEL);
2321 (fw_data, useraddr + sizeof(t), t.len)) {
2326 ret = t3_load_fw(adapter, fw_data, t.len);
2332 case CHELSIO_SETMTUTAB:{
2336 if (!is_offload(adapter))
2338 if (!capable(CAP_NET_ADMIN))
2340 if (offload_running(adapter))
2342 if (copy_from_user(&m, useraddr, sizeof(m)))
2344 if (m.nmtus != NMTUS)
2346 if (m.mtus[0] < 81) /* accommodate SACK */
2349 /* MTUs must be in ascending order */
2350 for (i = 1; i < NMTUS; ++i)
2351 if (m.mtus[i] < m.mtus[i - 1])
2354 memcpy(adapter->params.mtus, m.mtus,
2355 sizeof(adapter->params.mtus));
2358 case CHELSIO_GET_PM:{
2359 struct tp_params *p = &adapter->params.tp;
2360 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2362 if (!is_offload(adapter))
2364 m.tx_pg_sz = p->tx_pg_size;
2365 m.tx_num_pg = p->tx_num_pgs;
2366 m.rx_pg_sz = p->rx_pg_size;
2367 m.rx_num_pg = p->rx_num_pgs;
2368 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2369 if (copy_to_user(useraddr, &m, sizeof(m)))
2373 case CHELSIO_SET_PM:{
2375 struct tp_params *p = &adapter->params.tp;
2377 if (!is_offload(adapter))
2379 if (!capable(CAP_NET_ADMIN))
2381 if (adapter->flags & FULL_INIT_DONE)
2383 if (copy_from_user(&m, useraddr, sizeof(m)))
2385 if (!is_power_of_2(m.rx_pg_sz) ||
2386 !is_power_of_2(m.tx_pg_sz))
2387 return -EINVAL; /* not power of 2 */
2388 if (!(m.rx_pg_sz & 0x14000))
2389 return -EINVAL; /* not 16KB or 64KB */
2390 if (!(m.tx_pg_sz & 0x1554000))
2392 if (m.tx_num_pg == -1)
2393 m.tx_num_pg = p->tx_num_pgs;
2394 if (m.rx_num_pg == -1)
2395 m.rx_num_pg = p->rx_num_pgs;
2396 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2398 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2399 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2401 p->rx_pg_size = m.rx_pg_sz;
2402 p->tx_pg_size = m.tx_pg_sz;
2403 p->rx_num_pgs = m.rx_num_pg;
2404 p->tx_num_pgs = m.tx_num_pg;
2407 case CHELSIO_GET_MEM:{
2408 struct ch_mem_range t;
2412 if (!is_offload(adapter))
2414 if (!(adapter->flags & FULL_INIT_DONE))
2415 return -EIO; /* need the memory controllers */
2416 if (copy_from_user(&t, useraddr, sizeof(t)))
2418 if ((t.addr & 7) || (t.len & 7))
2420 if (t.mem_id == MEM_CM)
2422 else if (t.mem_id == MEM_PMRX)
2423 mem = &adapter->pmrx;
2424 else if (t.mem_id == MEM_PMTX)
2425 mem = &adapter->pmtx;
2431 * bits 0..9: chip version
2432 * bits 10..15: chip revision
2434 t.version = 3 | (adapter->params.rev << 10);
2435 if (copy_to_user(useraddr, &t, sizeof(t)))
2439 * Read 256 bytes at a time as len can be large and we don't
2440 * want to use huge intermediate buffers.
2442 useraddr += sizeof(t); /* advance to start of buffer */
2444 unsigned int chunk =
2445 min_t(unsigned int, t.len, sizeof(buf));
2448 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2452 if (copy_to_user(useraddr, buf, chunk))
2460 case CHELSIO_SET_TRACE_FILTER:{
2462 const struct trace_params *tp;
2464 if (!capable(CAP_NET_ADMIN))
2466 if (!offload_running(adapter))
2468 if (copy_from_user(&t, useraddr, sizeof(t)))
2471 tp = (const struct trace_params *)&t.sip;
2473 t3_config_trace_filter(adapter, tp, 0,
2477 t3_config_trace_filter(adapter, tp, 1,
2488 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2490 struct mii_ioctl_data *data = if_mii(req);
2491 struct port_info *pi = netdev_priv(dev);
2492 struct adapter *adapter = pi->adapter;
2497 /* Convert phy_id from older PRTAD/DEVAD format */
2498 if (is_10G(adapter) &&
2499 !mdio_phy_id_is_c45(data->phy_id) &&
2500 (data->phy_id & 0x1f00) &&
2501 !(data->phy_id & 0xe0e0))
2502 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2503 data->phy_id & 0x1f);
2506 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
2508 return cxgb_extension_ioctl(dev, req->ifr_data);
2514 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2516 struct port_info *pi = netdev_priv(dev);
2517 struct adapter *adapter = pi->adapter;
2520 if (new_mtu < 81) /* accommodate SACK */
2522 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2525 init_port_mtus(adapter);
2526 if (adapter->params.rev == 0 && offload_running(adapter))
2527 t3_load_mtus(adapter, adapter->params.mtus,
2528 adapter->params.a_wnd, adapter->params.b_wnd,
2529 adapter->port[0]->mtu);
2533 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2535 struct port_info *pi = netdev_priv(dev);
2536 struct adapter *adapter = pi->adapter;
2537 struct sockaddr *addr = p;
2539 if (!is_valid_ether_addr(addr->sa_data))
2542 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2543 t3_mac_set_address(&pi->mac, LAN_MAC_IDX, dev->dev_addr);
2544 if (offload_running(adapter))
2545 write_smt_entry(adapter, pi->port_id);
2550 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2551 * @adap: the adapter
2554 * Ensures that current Rx processing on any of the queues associated with
2555 * the given port completes before returning. We do this by acquiring and
2556 * releasing the locks of the response queues associated with the port.
2558 static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2562 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2563 struct sge_rspq *q = &adap->sge.qs[i].rspq;
2565 spin_lock_irq(&q->lock);
2566 spin_unlock_irq(&q->lock);
2570 static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2572 struct port_info *pi = netdev_priv(dev);
2573 struct adapter *adapter = pi->adapter;
2576 if (adapter->params.rev > 0)
2577 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2579 /* single control for all ports */
2580 unsigned int i, have_vlans = 0;
2581 for_each_port(adapter, i)
2582 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2584 t3_set_vlan_accel(adapter, 1, have_vlans);
2586 t3_synchronize_rx(adapter, pi);
2589 #ifdef CONFIG_NET_POLL_CONTROLLER
2590 static void cxgb_netpoll(struct net_device *dev)
2592 struct port_info *pi = netdev_priv(dev);
2593 struct adapter *adapter = pi->adapter;
2596 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2597 struct sge_qset *qs = &adapter->sge.qs[qidx];
2600 if (adapter->flags & USING_MSIX)
2605 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2611 * Periodic accumulation of MAC statistics.
2613 static void mac_stats_update(struct adapter *adapter)
2617 for_each_port(adapter, i) {
2618 struct net_device *dev = adapter->port[i];
2619 struct port_info *p = netdev_priv(dev);
2621 if (netif_running(dev)) {
2622 spin_lock(&adapter->stats_lock);
2623 t3_mac_update_stats(&p->mac);
2624 spin_unlock(&adapter->stats_lock);
2629 static void check_link_status(struct adapter *adapter)
2633 for_each_port(adapter, i) {
2634 struct net_device *dev = adapter->port[i];
2635 struct port_info *p = netdev_priv(dev);
2638 spin_lock_irq(&adapter->work_lock);
2639 link_fault = p->link_fault;
2640 spin_unlock_irq(&adapter->work_lock);
2643 t3_link_fault(adapter, i);
2647 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2648 t3_xgm_intr_disable(adapter, i);
2649 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2651 t3_link_changed(adapter, i);
2652 t3_xgm_intr_enable(adapter, i);
2657 static void check_t3b2_mac(struct adapter *adapter)
2661 if (!rtnl_trylock()) /* synchronize with ifdown */
2664 for_each_port(adapter, i) {
2665 struct net_device *dev = adapter->port[i];
2666 struct port_info *p = netdev_priv(dev);
2669 if (!netif_running(dev))
2673 if (netif_running(dev) && netif_carrier_ok(dev))
2674 status = t3b2_mac_watchdog_task(&p->mac);
2676 p->mac.stats.num_toggled++;
2677 else if (status == 2) {
2678 struct cmac *mac = &p->mac;
2680 t3_mac_set_mtu(mac, dev->mtu);
2681 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
2682 cxgb_set_rxmode(dev);
2683 t3_link_start(&p->phy, mac, &p->link_config);
2684 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2685 t3_port_intr_enable(adapter, p->port_id);
2686 p->mac.stats.num_resets++;
2693 static void t3_adap_check_task(struct work_struct *work)
2695 struct adapter *adapter = container_of(work, struct adapter,
2696 adap_check_task.work);
2697 const struct adapter_params *p = &adapter->params;
2699 unsigned int v, status, reset;
2701 adapter->check_task_cnt++;
2703 check_link_status(adapter);
2705 /* Accumulate MAC stats if needed */
2706 if (!p->linkpoll_period ||
2707 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2708 p->stats_update_period) {
2709 mac_stats_update(adapter);
2710 adapter->check_task_cnt = 0;
2713 if (p->rev == T3_REV_B2)
2714 check_t3b2_mac(adapter);
2717 * Scan the XGMAC's to check for various conditions which we want to
2718 * monitor in a periodic polling manner rather than via an interrupt
2719 * condition. This is used for conditions which would otherwise flood
2720 * the system with interrupts and we only really need to know that the
2721 * conditions are "happening" ... For each condition we count the
2722 * detection of the condition and reset it for the next polling loop.
2724 for_each_port(adapter, port) {
2725 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2728 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2730 if (cause & F_RXFIFO_OVERFLOW) {
2731 mac->stats.rx_fifo_ovfl++;
2732 reset |= F_RXFIFO_OVERFLOW;
2735 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2739 * We do the same as above for FL_EMPTY interrupts.
2741 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2744 if (status & F_FLEMPTY) {
2745 struct sge_qset *qs = &adapter->sge.qs[0];
2750 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2754 qs->fl[i].empty += (v & 1);
2762 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2764 /* Schedule the next check update if any port is active. */
2765 spin_lock_irq(&adapter->work_lock);
2766 if (adapter->open_device_map & PORT_MASK)
2767 schedule_chk_task(adapter);
2768 spin_unlock_irq(&adapter->work_lock);
2771 static void db_full_task(struct work_struct *work)
2773 struct adapter *adapter = container_of(work, struct adapter,
2776 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_FULL, 0);
2779 static void db_empty_task(struct work_struct *work)
2781 struct adapter *adapter = container_of(work, struct adapter,
2784 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_EMPTY, 0);
2787 static void db_drop_task(struct work_struct *work)
2789 struct adapter *adapter = container_of(work, struct adapter,
2791 unsigned long delay = 1000;
2794 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_DROP, 0);
2797 * Sleep a while before ringing the driver qset dbs.
2798 * The delay is between 1000-2023 usecs.
2800 get_random_bytes(&r, 2);
2802 set_current_state(TASK_UNINTERRUPTIBLE);
2803 schedule_timeout(usecs_to_jiffies(delay));
2808 * Processes external (PHY) interrupts in process context.
2810 static void ext_intr_task(struct work_struct *work)
2812 struct adapter *adapter = container_of(work, struct adapter,
2813 ext_intr_handler_task);
2816 /* Disable link fault interrupts */
2817 for_each_port(adapter, i) {
2818 struct net_device *dev = adapter->port[i];
2819 struct port_info *p = netdev_priv(dev);
2821 t3_xgm_intr_disable(adapter, i);
2822 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2825 /* Re-enable link fault interrupts */
2826 t3_phy_intr_handler(adapter);
2828 for_each_port(adapter, i)
2829 t3_xgm_intr_enable(adapter, i);
2831 /* Now reenable external interrupts */
2832 spin_lock_irq(&adapter->work_lock);
2833 if (adapter->slow_intr_mask) {
2834 adapter->slow_intr_mask |= F_T3DBG;
2835 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2836 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2837 adapter->slow_intr_mask);
2839 spin_unlock_irq(&adapter->work_lock);
2843 * Interrupt-context handler for external (PHY) interrupts.
2845 void t3_os_ext_intr_handler(struct adapter *adapter)
2848 * Schedule a task to handle external interrupts as they may be slow
2849 * and we use a mutex to protect MDIO registers. We disable PHY
2850 * interrupts in the meantime and let the task reenable them when
2853 spin_lock(&adapter->work_lock);
2854 if (adapter->slow_intr_mask) {
2855 adapter->slow_intr_mask &= ~F_T3DBG;
2856 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2857 adapter->slow_intr_mask);
2858 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2860 spin_unlock(&adapter->work_lock);
2863 void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2865 struct net_device *netdev = adapter->port[port_id];
2866 struct port_info *pi = netdev_priv(netdev);
2868 spin_lock(&adapter->work_lock);
2870 spin_unlock(&adapter->work_lock);
2873 static int t3_adapter_error(struct adapter *adapter, int reset)
2877 if (is_offload(adapter) &&
2878 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2879 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
2880 offload_close(&adapter->tdev);
2883 /* Stop all ports */
2884 for_each_port(adapter, i) {
2885 struct net_device *netdev = adapter->port[i];
2887 if (netif_running(netdev))
2891 /* Stop SGE timers */
2892 t3_stop_sge_timers(adapter);
2894 adapter->flags &= ~FULL_INIT_DONE;
2897 ret = t3_reset_adapter(adapter);
2899 pci_disable_device(adapter->pdev);
2904 static int t3_reenable_adapter(struct adapter *adapter)
2906 if (pci_enable_device(adapter->pdev)) {
2907 dev_err(&adapter->pdev->dev,
2908 "Cannot re-enable PCI device after reset.\n");
2911 pci_set_master(adapter->pdev);
2912 pci_restore_state(adapter->pdev);
2913 pci_save_state(adapter->pdev);
2915 /* Free sge resources */
2916 t3_free_sge_resources(adapter);
2918 if (t3_replay_prep_adapter(adapter))
2926 static void t3_resume_ports(struct adapter *adapter)
2930 /* Restart the ports */
2931 for_each_port(adapter, i) {
2932 struct net_device *netdev = adapter->port[i];
2934 if (netif_running(netdev)) {
2935 if (cxgb_open(netdev)) {
2936 dev_err(&adapter->pdev->dev,
2937 "can't bring device back up"
2944 if (is_offload(adapter) && !ofld_disable)
2945 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
2949 * processes a fatal error.
2950 * Bring the ports down, reset the chip, bring the ports back up.
2952 static void fatal_error_task(struct work_struct *work)
2954 struct adapter *adapter = container_of(work, struct adapter,
2955 fatal_error_handler_task);
2959 err = t3_adapter_error(adapter, 1);
2961 err = t3_reenable_adapter(adapter);
2963 t3_resume_ports(adapter);
2965 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2969 void t3_fatal_err(struct adapter *adapter)
2971 unsigned int fw_status[4];
2973 if (adapter->flags & FULL_INIT_DONE) {
2974 t3_sge_stop(adapter);
2975 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2976 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2977 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2978 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
2980 spin_lock(&adapter->work_lock);
2981 t3_intr_disable(adapter);
2982 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2983 spin_unlock(&adapter->work_lock);
2985 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2986 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2987 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2988 fw_status[0], fw_status[1],
2989 fw_status[2], fw_status[3]);
2993 * t3_io_error_detected - called when PCI error is detected
2994 * @pdev: Pointer to PCI device
2995 * @state: The current pci connection state
2997 * This function is called after a PCI bus error affecting
2998 * this device has been detected.
3000 static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
3001 pci_channel_state_t state)
3003 struct adapter *adapter = pci_get_drvdata(pdev);
3006 if (state == pci_channel_io_perm_failure)
3007 return PCI_ERS_RESULT_DISCONNECT;
3009 ret = t3_adapter_error(adapter, 0);
3011 /* Request a slot reset. */
3012 return PCI_ERS_RESULT_NEED_RESET;
3016 * t3_io_slot_reset - called after the pci bus has been reset.
3017 * @pdev: Pointer to PCI device
3019 * Restart the card from scratch, as if from a cold-boot.
3021 static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
3023 struct adapter *adapter = pci_get_drvdata(pdev);
3025 if (!t3_reenable_adapter(adapter))
3026 return PCI_ERS_RESULT_RECOVERED;
3028 return PCI_ERS_RESULT_DISCONNECT;
3032 * t3_io_resume - called when traffic can start flowing again.
3033 * @pdev: Pointer to PCI device
3035 * This callback is called when the error recovery driver tells us that
3036 * its OK to resume normal operation.
3038 static void t3_io_resume(struct pci_dev *pdev)
3040 struct adapter *adapter = pci_get_drvdata(pdev);
3042 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
3043 t3_read_reg(adapter, A_PCIE_PEX_ERR));
3045 t3_resume_ports(adapter);
3048 static struct pci_error_handlers t3_err_handler = {
3049 .error_detected = t3_io_error_detected,
3050 .slot_reset = t3_io_slot_reset,
3051 .resume = t3_io_resume,
3055 * Set the number of qsets based on the number of CPUs and the number of ports,
3056 * not to exceed the number of available qsets, assuming there are enough qsets
3059 static void set_nqsets(struct adapter *adap)
3062 int num_cpus = num_online_cpus();
3063 int hwports = adap->params.nports;
3064 int nqsets = adap->msix_nvectors - 1;
3066 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
3068 (hwports * nqsets > SGE_QSETS ||
3069 num_cpus >= nqsets / hwports))
3071 if (nqsets > num_cpus)
3073 if (nqsets < 1 || hwports == 4)
3078 for_each_port(adap, i) {
3079 struct port_info *pi = adap2pinfo(adap, i);
3082 pi->nqsets = nqsets;
3083 j = pi->first_qset + nqsets;
3085 dev_info(&adap->pdev->dev,
3086 "Port %d using %d queue sets.\n", i, nqsets);
3090 static int __devinit cxgb_enable_msix(struct adapter *adap)
3092 struct msix_entry entries[SGE_QSETS + 1];
3096 vectors = ARRAY_SIZE(entries);
3097 for (i = 0; i < vectors; ++i)
3098 entries[i].entry = i;
3100 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
3104 pci_disable_msix(adap->pdev);
3106 if (!err && vectors < (adap->params.nports + 1)) {
3107 pci_disable_msix(adap->pdev);
3112 for (i = 0; i < vectors; ++i)
3113 adap->msix_info[i].vec = entries[i].vector;
3114 adap->msix_nvectors = vectors;
3120 static void __devinit print_port_info(struct adapter *adap,
3121 const struct adapter_info *ai)
3123 static const char *pci_variant[] = {
3124 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3131 snprintf(buf, sizeof(buf), "%s x%d",
3132 pci_variant[adap->params.pci.variant],
3133 adap->params.pci.width);
3135 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3136 pci_variant[adap->params.pci.variant],
3137 adap->params.pci.speed, adap->params.pci.width);
3139 for_each_port(adap, i) {
3140 struct net_device *dev = adap->port[i];
3141 const struct port_info *pi = netdev_priv(dev);
3143 if (!test_bit(i, &adap->registered_device_map))
3145 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
3146 dev->name, ai->desc, pi->phy.desc,
3147 is_offload(adap) ? "R" : "", adap->params.rev, buf,
3148 (adap->flags & USING_MSIX) ? " MSI-X" :
3149 (adap->flags & USING_MSI) ? " MSI" : "");
3150 if (adap->name == dev->name && adap->params.vpd.mclk)
3152 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
3153 adap->name, t3_mc7_size(&adap->cm) >> 20,
3154 t3_mc7_size(&adap->pmtx) >> 20,
3155 t3_mc7_size(&adap->pmrx) >> 20,
3156 adap->params.vpd.sn);
3160 static const struct net_device_ops cxgb_netdev_ops = {
3161 .ndo_open = cxgb_open,
3162 .ndo_stop = cxgb_close,
3163 .ndo_start_xmit = t3_eth_xmit,
3164 .ndo_get_stats = cxgb_get_stats,
3165 .ndo_validate_addr = eth_validate_addr,
3166 .ndo_set_multicast_list = cxgb_set_rxmode,
3167 .ndo_do_ioctl = cxgb_ioctl,
3168 .ndo_change_mtu = cxgb_change_mtu,
3169 .ndo_set_mac_address = cxgb_set_mac_addr,
3170 .ndo_vlan_rx_register = vlan_rx_register,
3171 #ifdef CONFIG_NET_POLL_CONTROLLER
3172 .ndo_poll_controller = cxgb_netpoll,
3176 static void __devinit cxgb3_init_iscsi_mac(struct net_device *dev)
3178 struct port_info *pi = netdev_priv(dev);
3180 memcpy(pi->iscsic.mac_addr, dev->dev_addr, ETH_ALEN);
3181 pi->iscsic.mac_addr[3] |= 0x80;
3184 static int __devinit init_one(struct pci_dev *pdev,
3185 const struct pci_device_id *ent)
3187 static int version_printed;
3189 int i, err, pci_using_dac = 0;
3190 resource_size_t mmio_start, mmio_len;
3191 const struct adapter_info *ai;
3192 struct adapter *adapter = NULL;
3193 struct port_info *pi;
3195 if (!version_printed) {
3196 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3201 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3203 printk(KERN_ERR DRV_NAME
3204 ": cannot initialize work queue\n");
3209 err = pci_request_regions(pdev, DRV_NAME);
3211 /* Just info, some other driver may have claimed the device. */
3212 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3216 err = pci_enable_device(pdev);
3218 dev_err(&pdev->dev, "cannot enable PCI device\n");
3219 goto out_release_regions;
3222 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3224 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3226 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3227 "coherent allocations\n");
3228 goto out_disable_device;
3230 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3231 dev_err(&pdev->dev, "no usable DMA configuration\n");
3232 goto out_disable_device;
3235 pci_set_master(pdev);
3236 pci_save_state(pdev);
3238 mmio_start = pci_resource_start(pdev, 0);
3239 mmio_len = pci_resource_len(pdev, 0);
3240 ai = t3_get_adapter_info(ent->driver_data);
3242 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3245 goto out_disable_device;
3248 adapter->nofail_skb =
3249 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3250 if (!adapter->nofail_skb) {
3251 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3253 goto out_free_adapter;
3256 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3257 if (!adapter->regs) {
3258 dev_err(&pdev->dev, "cannot map device registers\n");
3260 goto out_free_adapter;
3263 adapter->pdev = pdev;
3264 adapter->name = pci_name(pdev);
3265 adapter->msg_enable = dflt_msg_enable;
3266 adapter->mmio_len = mmio_len;
3268 mutex_init(&adapter->mdio_lock);
3269 spin_lock_init(&adapter->work_lock);
3270 spin_lock_init(&adapter->stats_lock);
3272 INIT_LIST_HEAD(&adapter->adapter_list);
3273 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
3274 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
3276 INIT_WORK(&adapter->db_full_task, db_full_task);
3277 INIT_WORK(&adapter->db_empty_task, db_empty_task);
3278 INIT_WORK(&adapter->db_drop_task, db_drop_task);
3280 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3282 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
3283 struct net_device *netdev;
3285 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
3291 SET_NETDEV_DEV(netdev, &pdev->dev);
3293 adapter->port[i] = netdev;
3294 pi = netdev_priv(netdev);
3295 pi->adapter = adapter;
3296 pi->rx_offload = T3_RX_CSUM | T3_LRO;
3298 netif_carrier_off(netdev);
3299 netif_tx_stop_all_queues(netdev);
3300 netdev->irq = pdev->irq;
3301 netdev->mem_start = mmio_start;
3302 netdev->mem_end = mmio_start + mmio_len - 1;
3303 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3304 netdev->features |= NETIF_F_GRO;
3306 netdev->features |= NETIF_F_HIGHDMA;
3308 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3309 netdev->netdev_ops = &cxgb_netdev_ops;
3310 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3313 pci_set_drvdata(pdev, adapter);
3314 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3320 * The card is now ready to go. If any errors occur during device
3321 * registration we do not fail the whole card but rather proceed only
3322 * with the ports we manage to register successfully. However we must
3323 * register at least one net device.
3325 for_each_port(adapter, i) {
3326 err = register_netdev(adapter->port[i]);
3328 dev_warn(&pdev->dev,
3329 "cannot register net device %s, skipping\n",
3330 adapter->port[i]->name);
3333 * Change the name we use for messages to the name of
3334 * the first successfully registered interface.
3336 if (!adapter->registered_device_map)
3337 adapter->name = adapter->port[i]->name;
3339 __set_bit(i, &adapter->registered_device_map);
3342 if (!adapter->registered_device_map) {
3343 dev_err(&pdev->dev, "could not register any net devices\n");
3347 for_each_port(adapter, i)
3348 cxgb3_init_iscsi_mac(adapter->port[i]);
3350 /* Driver's ready. Reflect it on LEDs */
3351 t3_led_ready(adapter);
3353 if (is_offload(adapter)) {
3354 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3355 cxgb3_adapter_ofld(adapter);
3358 /* See what interrupts we'll be using */
3359 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3360 adapter->flags |= USING_MSIX;
3361 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3362 adapter->flags |= USING_MSI;
3364 set_nqsets(adapter);
3366 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
3369 print_port_info(adapter, ai);
3373 iounmap(adapter->regs);
3374 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
3375 if (adapter->port[i])
3376 free_netdev(adapter->port[i]);
3382 pci_disable_device(pdev);
3383 out_release_regions:
3384 pci_release_regions(pdev);
3385 pci_set_drvdata(pdev, NULL);
3389 static void __devexit remove_one(struct pci_dev *pdev)
3391 struct adapter *adapter = pci_get_drvdata(pdev);
3396 t3_sge_stop(adapter);
3397 sysfs_remove_group(&adapter->port[0]->dev.kobj,
3400 if (is_offload(adapter)) {
3401 cxgb3_adapter_unofld(adapter);
3402 if (test_bit(OFFLOAD_DEVMAP_BIT,
3403 &adapter->open_device_map))
3404 offload_close(&adapter->tdev);
3407 for_each_port(adapter, i)
3408 if (test_bit(i, &adapter->registered_device_map))
3409 unregister_netdev(adapter->port[i]);
3411 t3_stop_sge_timers(adapter);
3412 t3_free_sge_resources(adapter);
3413 cxgb_disable_msi(adapter);
3415 for_each_port(adapter, i)
3416 if (adapter->port[i])
3417 free_netdev(adapter->port[i]);
3419 iounmap(adapter->regs);
3420 if (adapter->nofail_skb)
3421 kfree_skb(adapter->nofail_skb);
3423 pci_release_regions(pdev);
3424 pci_disable_device(pdev);
3425 pci_set_drvdata(pdev, NULL);
3429 static struct pci_driver driver = {
3431 .id_table = cxgb3_pci_tbl,
3433 .remove = __devexit_p(remove_one),
3434 .err_handler = &t3_err_handler,
3437 static int __init cxgb3_init_module(void)
3441 cxgb3_offload_init();
3443 ret = pci_register_driver(&driver);
3447 static void __exit cxgb3_cleanup_module(void)
3449 pci_unregister_driver(&driver);
3451 destroy_workqueue(cxgb3_wq);
3454 module_init(cxgb3_init_module);
3455 module_exit(cxgb3_cleanup_module);