2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 AEL100X_TX_CONFIG1 = 0xc002,
37 AEL1002_PWR_DOWN_HI = 0xc011,
38 AEL1002_PWR_DOWN_LO = 0xc012,
39 AEL1002_XFI_EQL = 0xc015,
40 AEL1002_LB_EN = 0xc017,
41 AEL_OPT_SETTINGS = 0xc017,
42 AEL_I2C_CTRL = 0xc30a,
43 AEL_I2C_DATA = 0xc30b,
44 AEL_I2C_STAT = 0xc30c,
45 AEL2005_GPIO_CTRL = 0xc214,
46 AEL2005_GPIO_STAT = 0xc215,
48 AEL2020_GPIO_INTR = 0xc103, /* Latch High (LH) */
49 AEL2020_GPIO_CTRL = 0xc108, /* Store Clear (SC) */
50 AEL2020_GPIO_STAT = 0xc10c, /* Read Only (RO) */
51 AEL2020_GPIO_CFG = 0xc110, /* Read Write (RW) */
53 AEL2020_GPIO_SDA = 0, /* IN: i2c serial data */
54 AEL2020_GPIO_MODDET = 1, /* IN: Module Detect */
55 AEL2020_GPIO_0 = 3, /* IN: unassigned */
56 AEL2020_GPIO_1 = 2, /* OUT: unassigned */
57 AEL2020_GPIO_LSTAT = AEL2020_GPIO_1, /* wired to link status LED */
60 enum { edc_none, edc_sr, edc_twinax };
62 /* PHY module I2C device address */
64 MODULE_DEV_ADDR = 0xa0,
68 /* PHY transceiver type */
70 phy_transtype_unknown = 0,
71 phy_transtype_sfp = 3,
72 phy_transtype_xfp = 6,
75 #define AEL2005_MODDET_IRQ 4
78 unsigned short mmd_addr;
79 unsigned short reg_addr;
80 unsigned short clear_bits;
81 unsigned short set_bits;
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
88 for (err = 0; rv->mmd_addr && !err; rv++) {
89 if (rv->clear_bits == 0xffff)
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr,
93 err = t3_mdio_change_bits(phy, rv->mmd_addr,
94 rv->reg_addr, rv->clear_bits,
100 static void ael100x_txon(struct cphy *phy)
103 phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
106 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
111 * Read an 8-bit word from a device attached to the PHY's i2c bus.
113 static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
116 unsigned int stat, data;
118 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
119 (dev_addr << 8) | (1 << 8) | word_addr);
123 for (i = 0; i < 200; i++) {
125 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
128 if ((stat & 3) == 1) {
129 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
136 CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %#x.%#x timed out\n",
137 phy->mdio.prtad, dev_addr, word_addr);
141 static int ael1002_power_down(struct cphy *phy, int enable)
145 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
147 err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
148 MDIO_MMD_PMAPMD, MDIO_CTRL1,
149 MDIO_CTRL1_LPOWER, enable);
153 static int ael1002_reset(struct cphy *phy, int wait)
157 if ((err = ael1002_power_down(phy, 0)) ||
158 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
159 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
160 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
161 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
162 (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
168 static int ael1002_intr_noop(struct cphy *phy)
174 * Get link status for a 10GBASE-R device.
176 static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed,
177 int *duplex, int *fc)
180 unsigned int stat0, stat1, stat2;
181 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
182 MDIO_PMA_RXDET, &stat0);
185 err = t3_mdio_read(phy, MDIO_MMD_PCS,
186 MDIO_PCS_10GBRT_STAT1, &stat1);
188 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
189 MDIO_PHYXS_LNSTAT, &stat2);
192 *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1;
195 *speed = SPEED_10000;
197 *duplex = DUPLEX_FULL;
201 static struct cphy_ops ael1002_ops = {
202 .reset = ael1002_reset,
203 .intr_enable = ael1002_intr_noop,
204 .intr_disable = ael1002_intr_noop,
205 .intr_clear = ael1002_intr_noop,
206 .intr_handler = ael1002_intr_noop,
207 .get_link_status = get_link_status_r,
208 .power_down = ael1002_power_down,
209 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
212 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
213 int phy_addr, const struct mdio_ops *mdio_ops)
215 cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops,
216 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
222 static int ael1006_reset(struct cphy *phy, int wait)
224 return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait);
227 static struct cphy_ops ael1006_ops = {
228 .reset = ael1006_reset,
229 .intr_enable = t3_phy_lasi_intr_enable,
230 .intr_disable = t3_phy_lasi_intr_disable,
231 .intr_clear = t3_phy_lasi_intr_clear,
232 .intr_handler = t3_phy_lasi_intr_handler,
233 .get_link_status = get_link_status_r,
234 .power_down = ael1002_power_down,
235 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
238 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
239 int phy_addr, const struct mdio_ops *mdio_ops)
241 cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops,
242 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
249 * Decode our module type.
251 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms)
258 /* see SFF-8472 for below */
259 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);
264 return phy_modtype_sr;
266 return phy_modtype_lr;
268 return phy_modtype_lrm;
270 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);
276 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);
281 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
284 return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax;
287 return phy_modtype_unknown;
291 * Code to support the Aeluros/NetLogic 2005 10Gb PHY.
293 static int ael2005_setup_sr_edc(struct cphy *phy)
295 static struct reg_val regs[] = {
296 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
297 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
298 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
301 static u16 sr_edc[] = {
576 err = set_phy_regs(phy, regs);
582 for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2)
583 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, sr_edc[i],
590 static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
592 static struct reg_val regs[] = {
593 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
596 static struct reg_val preemphasis[] = {
597 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
598 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
601 static u16 twinax_edc[] = {
971 err = set_phy_regs(phy, regs);
972 if (!err && modtype == phy_modtype_twinax_long)
973 err = set_phy_regs(phy, preemphasis);
979 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2)
980 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i],
983 phy->priv = edc_twinax;
987 static int ael2005_get_module_type(struct cphy *phy, int delay_ms)
992 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
996 if (stat & (1 << 8)) /* module absent */
997 return phy_modtype_none;
999 return ael2xxx_get_module_type(phy, delay_ms);
1002 static int ael2005_intr_enable(struct cphy *phy)
1004 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
1005 return err ? err : t3_phy_lasi_intr_enable(phy);
1008 static int ael2005_intr_disable(struct cphy *phy)
1010 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
1011 return err ? err : t3_phy_lasi_intr_disable(phy);
1014 static int ael2005_intr_clear(struct cphy *phy)
1016 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
1017 return err ? err : t3_phy_lasi_intr_clear(phy);
1020 static int ael2005_reset(struct cphy *phy, int wait)
1022 static struct reg_val regs0[] = {
1023 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
1024 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
1025 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
1026 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
1027 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 },
1028 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
1029 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
1032 static struct reg_val regs1[] = {
1033 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
1034 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
1039 unsigned int lasi_ctrl;
1041 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
1046 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
1051 phy->priv = edc_none;
1052 err = set_phy_regs(phy, regs0);
1058 err = ael2005_get_module_type(phy, 0);
1063 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
1064 err = ael2005_setup_twinax_edc(phy, err);
1066 err = ael2005_setup_sr_edc(phy);
1070 err = set_phy_regs(phy, regs1);
1074 /* reset wipes out interrupts, reenable them if they were on */
1076 err = ael2005_intr_enable(phy);
1080 static int ael2005_intr_handler(struct cphy *phy)
1083 int ret, edc_needed, cause = 0;
1085 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat);
1089 if (stat & AEL2005_MODDET_IRQ) {
1090 ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL,
1095 /* modules have max 300 ms init time after hot plug */
1096 ret = ael2005_get_module_type(phy, 300);
1101 if (ret == phy_modtype_none)
1102 edc_needed = phy->priv; /* on unplug retain EDC */
1103 else if (ret == phy_modtype_twinax ||
1104 ret == phy_modtype_twinax_long)
1105 edc_needed = edc_twinax;
1107 edc_needed = edc_sr;
1109 if (edc_needed != phy->priv) {
1110 ret = ael2005_reset(phy, 0);
1111 return ret ? ret : cphy_cause_module_change;
1113 cause = cphy_cause_module_change;
1116 ret = t3_phy_lasi_intr_handler(phy);
1121 return ret ? ret : cphy_cause_link_change;
1124 static struct cphy_ops ael2005_ops = {
1125 .reset = ael2005_reset,
1126 .intr_enable = ael2005_intr_enable,
1127 .intr_disable = ael2005_intr_disable,
1128 .intr_clear = ael2005_intr_clear,
1129 .intr_handler = ael2005_intr_handler,
1130 .get_link_status = get_link_status_r,
1131 .power_down = ael1002_power_down,
1132 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1135 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
1136 int phy_addr, const struct mdio_ops *mdio_ops)
1138 cphy_init(phy, adapter, phy_addr, &ael2005_ops, mdio_ops,
1139 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
1140 SUPPORTED_IRQ, "10GBASE-R");
1142 return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,
1147 * Setup EDC and other parameters for operation with an optical module.
1149 static int ael2020_setup_sr_edc(struct cphy *phy)
1151 static struct reg_val regs[] = {
1152 /* set CDR offset to 10 */
1153 { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
1155 /* adjust 10G RX bias current */
1156 { MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 },
1157 { MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 },
1158 { MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 },
1165 err = set_phy_regs(phy, regs);
1175 * Setup EDC and other parameters for operation with an TWINAX module.
1177 static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
1179 /* set uC to 40MHz */
1180 static struct reg_val uCclock40MHz[] = {
1181 { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
1182 { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
1186 /* activate uC clock */
1187 static struct reg_val uCclockActivate[] = {
1188 { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
1192 /* set PC to start of SRAM and activate uC */
1193 static struct reg_val uCactivate[] = {
1194 { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
1195 { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
1199 /* TWINAX EDC firmware */
1200 static u16 twinax_edc[] = {
1599 /* set uC clock and activate it */
1600 err = set_phy_regs(phy, uCclock40MHz);
1604 err = set_phy_regs(phy, uCclockActivate);
1609 /* write TWINAX EDC firmware into PHY */
1610 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2)
1611 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i],
1614 err = set_phy_regs(phy, uCactivate);
1616 phy->priv = edc_twinax;
1621 * Return Module Type.
1623 static int ael2020_get_module_type(struct cphy *phy, int delay_ms)
1628 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat);
1632 if (stat & (0x1 << (AEL2020_GPIO_MODDET*4))) {
1634 return phy_modtype_none;
1637 return ael2xxx_get_module_type(phy, delay_ms);
1641 * Enable PHY interrupts. We enable "Module Detection" interrupts (on any
1642 * state transition) and then generic Link Alarm Status Interrupt (LASI).
1644 static int ael2020_intr_enable(struct cphy *phy)
1646 struct reg_val regs[] = {
1647 /* output Module's Loss Of Signal (LOS) to LED */
1648 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
1650 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1651 0xffff, 0x8 << (AEL2020_GPIO_LSTAT*4) },
1653 /* enable module detect status change interrupts */
1654 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1655 0xffff, 0x2 << (AEL2020_GPIO_MODDET*4) },
1660 int err, link_ok = 0;
1662 /* set up "link status" LED and enable module change interrupts */
1663 err = set_phy_regs(phy, regs);
1667 err = get_link_status_r(phy, &link_ok, NULL, NULL, NULL);
1671 t3_link_changed(phy->adapter,
1674 err = t3_phy_lasi_intr_enable(phy);
1682 * Disable PHY interrupts. The mirror of the above ...
1684 static int ael2020_intr_disable(struct cphy *phy)
1686 struct reg_val regs[] = {
1687 /* reset "link status" LED to "off" */
1688 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1689 0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) },
1691 /* disable module detect status change interrupts */
1692 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1693 0xffff, 0x1 << (AEL2020_GPIO_MODDET*4) },
1700 /* turn off "link status" LED and disable module change interrupts */
1701 err = set_phy_regs(phy, regs);
1705 return t3_phy_lasi_intr_disable(phy);
1709 * Clear PHY interrupt state.
1711 static int ael2020_intr_clear(struct cphy *phy)
1714 * The GPIO Interrupt register on the AEL2020 is a "Latching High"
1715 * (LH) register which is cleared to the current state when it's read.
1716 * Thus, we simply read the register and discard the result.
1719 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
1720 return err ? err : t3_phy_lasi_intr_clear(phy);
1723 static struct reg_val ael2020_reset_regs[] = {
1724 /* Erratum #2: CDRLOL asserted, causing PMA link down status */
1725 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
1727 /* force XAUI to send LF when RX_LOS is asserted */
1728 { MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 },
1730 /* allow writes to transceiver module EEPROM on i2c bus */
1731 { MDIO_MMD_PMAPMD, 0xff02, 0xffff, 0x0023 },
1732 { MDIO_MMD_PMAPMD, 0xff03, 0xffff, 0x0000 },
1733 { MDIO_MMD_PMAPMD, 0xff04, 0xffff, 0x0000 },
1739 * Reset the PHY and put it into a canonical operating state.
1741 static int ael2020_reset(struct cphy *phy, int wait)
1744 unsigned int lasi_ctrl;
1746 /* grab current interrupt state */
1747 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
1752 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125);
1757 /* basic initialization for all module types */
1758 phy->priv = edc_none;
1759 err = set_phy_regs(phy, ael2020_reset_regs);
1763 /* determine module type and perform appropriate initialization */
1764 err = ael2020_get_module_type(phy, 0);
1767 phy->modtype = (u8)err;
1768 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
1769 err = ael2020_setup_twinax_edc(phy, err);
1771 err = ael2020_setup_sr_edc(phy);
1775 /* reset wipes out interrupts, reenable them if they were on */
1777 err = ael2005_intr_enable(phy);
1782 * Handle a PHY interrupt.
1784 static int ael2020_intr_handler(struct cphy *phy)
1787 int ret, edc_needed, cause = 0;
1789 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
1793 if (stat & (0x1 << AEL2020_GPIO_MODDET)) {
1794 /* modules have max 300 ms init time after hot plug */
1795 ret = ael2020_get_module_type(phy, 300);
1799 phy->modtype = (u8)ret;
1800 if (ret == phy_modtype_none)
1801 edc_needed = phy->priv; /* on unplug retain EDC */
1802 else if (ret == phy_modtype_twinax ||
1803 ret == phy_modtype_twinax_long)
1804 edc_needed = edc_twinax;
1806 edc_needed = edc_sr;
1808 if (edc_needed != phy->priv) {
1809 ret = ael2020_reset(phy, 0);
1810 return ret ? ret : cphy_cause_module_change;
1812 cause = cphy_cause_module_change;
1815 ret = t3_phy_lasi_intr_handler(phy);
1820 return ret ? ret : cphy_cause_link_change;
1823 static struct cphy_ops ael2020_ops = {
1824 .reset = ael2020_reset,
1825 .intr_enable = ael2020_intr_enable,
1826 .intr_disable = ael2020_intr_disable,
1827 .intr_clear = ael2020_intr_clear,
1828 .intr_handler = ael2020_intr_handler,
1829 .get_link_status = get_link_status_r,
1830 .power_down = ael1002_power_down,
1831 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1834 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
1835 const struct mdio_ops *mdio_ops)
1839 cphy_init(phy, adapter, phy_addr, &ael2020_ops, mdio_ops,
1840 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
1841 SUPPORTED_IRQ, "10GBASE-R");
1844 err = set_phy_regs(phy, ael2020_reset_regs);
1851 * Get link status for a 10GBASE-X device.
1853 static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed,
1854 int *duplex, int *fc)
1857 unsigned int stat0, stat1, stat2;
1858 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
1859 MDIO_PMA_RXDET, &stat0);
1862 err = t3_mdio_read(phy, MDIO_MMD_PCS,
1863 MDIO_PCS_10GBX_STAT1, &stat1);
1865 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
1866 MDIO_PHYXS_LNSTAT, &stat2);
1869 *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1;
1872 *speed = SPEED_10000;
1874 *duplex = DUPLEX_FULL;
1878 static struct cphy_ops qt2045_ops = {
1879 .reset = ael1006_reset,
1880 .intr_enable = t3_phy_lasi_intr_enable,
1881 .intr_disable = t3_phy_lasi_intr_disable,
1882 .intr_clear = t3_phy_lasi_intr_clear,
1883 .intr_handler = t3_phy_lasi_intr_handler,
1884 .get_link_status = get_link_status_x,
1885 .power_down = ael1002_power_down,
1886 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1889 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
1890 int phy_addr, const struct mdio_ops *mdio_ops)
1894 cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops,
1895 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
1899 * Some cards where the PHY is supposed to be at address 0 actually
1903 !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) &&
1905 phy->mdio.prtad = 1;
1909 static int xaui_direct_reset(struct cphy *phy, int wait)
1914 static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
1915 int *speed, int *duplex, int *fc)
1918 unsigned int status;
1919 int prtad = phy->mdio.prtad;
1921 status = t3_read_reg(phy->adapter,
1922 XGM_REG(A_XGM_SERDES_STAT0, prtad)) |
1923 t3_read_reg(phy->adapter,
1924 XGM_REG(A_XGM_SERDES_STAT1, prtad)) |
1925 t3_read_reg(phy->adapter,
1926 XGM_REG(A_XGM_SERDES_STAT2, prtad)) |
1927 t3_read_reg(phy->adapter,
1928 XGM_REG(A_XGM_SERDES_STAT3, prtad));
1929 *link_ok = !(status & F_LOWSIG0);
1932 *speed = SPEED_10000;
1934 *duplex = DUPLEX_FULL;
1938 static int xaui_direct_power_down(struct cphy *phy, int enable)
1943 static struct cphy_ops xaui_direct_ops = {
1944 .reset = xaui_direct_reset,
1945 .intr_enable = ael1002_intr_noop,
1946 .intr_disable = ael1002_intr_noop,
1947 .intr_clear = ael1002_intr_noop,
1948 .intr_handler = ael1002_intr_noop,
1949 .get_link_status = xaui_direct_get_link_status,
1950 .power_down = xaui_direct_power_down,
1953 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
1954 int phy_addr, const struct mdio_ops *mdio_ops)
1956 cphy_init(phy, adapter, MDIO_PRTAD_NONE, &xaui_direct_ops, mdio_ops,
1957 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,