1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the regsister Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
23 /* [R 19] Interrupt register #0 read */
24 #define BRB1_REG_BRB1_INT_STS 0x6011c
25 /* [RW 4] Parity mask register #0 read/write */
26 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
27 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
28 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
29 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
30 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
31 /* [RW 23] LL RAM data. */
32 #define BRB1_REG_LL_RAM 0x61000
33 /* [R 24] The number of full blocks. */
34 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
35 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
37 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
38 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
39 #define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
40 #define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
41 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
42 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
44 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
45 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
46 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
47 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
48 /* [RW 10] Write client 0: De-assert pause threshold. */
49 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
50 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
51 /* [RW 10] Write client 0: Assert pause threshold. */
52 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
53 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
54 /* [RW 1] Reset the design by software. */
55 #define BRB1_REG_SOFT_RESET 0x600dc
56 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
57 #define CCM_REG_CAM_OCCUP 0xd0188
58 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
59 acknowledge output is deasserted; all other signals are treated as usual;
60 if 1 - normal activity. */
61 #define CCM_REG_CCM_CFC_IFEN 0xd003c
62 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
63 disregarded; valid is deasserted; all other signals are treated as usual;
64 if 1 - normal activity. */
65 #define CCM_REG_CCM_CQM_IFEN 0xd000c
66 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
67 Otherwise 0 is inserted. */
68 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
69 /* [RW 11] Interrupt mask register #0 read/write */
70 #define CCM_REG_CCM_INT_MASK 0xd01e4
71 /* [R 11] Interrupt register #0 read */
72 #define CCM_REG_CCM_INT_STS 0xd01d8
73 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
74 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
75 Is used to determine the number of the AG context REG-pairs written back;
76 when the input message Reg1WbFlg isn't set. */
77 #define CCM_REG_CCM_REG0_SZ 0xd00c4
78 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
79 disregarded; valid is deasserted; all other signals are treated as usual;
80 if 1 - normal activity. */
81 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
82 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
83 disregarded; valid is deasserted; all other signals are treated as usual;
84 if 1 - normal activity. */
85 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
86 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
87 disregarded; valid output is deasserted; all other signals are treated as
88 usual; if 1 - normal activity. */
89 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
90 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
91 are disregarded; all other signals are treated as usual; if 1 - normal
93 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
94 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
95 disregarded; valid output is deasserted; all other signals are treated as
96 usual; if 1 - normal activity. */
97 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
98 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
99 input is disregarded; all other signals are treated as usual; if 1 -
101 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
102 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
103 the initial credit value; read returns the current value of the credit
104 counter. Must be initialized to 1 at start-up. */
105 #define CCM_REG_CFC_INIT_CRD 0xd0204
106 /* [RW 2] Auxillary counter flag Q number 1. */
107 #define CCM_REG_CNT_AUX1_Q 0xd00c8
108 /* [RW 2] Auxillary counter flag Q number 2. */
109 #define CCM_REG_CNT_AUX2_Q 0xd00cc
110 /* [RW 28] The CM header value for QM request (primary). */
111 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
112 /* [RW 28] The CM header value for QM request (secondary). */
113 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
114 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
115 acknowledge output is deasserted; all other signals are treated as usual;
116 if 1 - normal activity. */
117 #define CCM_REG_CQM_CCM_IFEN 0xd0014
118 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
119 the initial credit value; read returns the current value of the credit
120 counter. Must be initialized to 32 at start-up. */
121 #define CCM_REG_CQM_INIT_CRD 0xd020c
122 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
123 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
124 prioritised); 2 stands for weight 2; tc. */
125 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
126 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
127 acknowledge output is deasserted; all other signals are treated as usual;
128 if 1 - normal activity. */
129 #define CCM_REG_CSDM_IFEN 0xd0018
130 /* [RC 1] Set when the message length mismatch (relative to last indication)
131 at the SDM interface is detected. */
132 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
133 /* [RW 28] The CM header for QM formatting in case of an error in the QM
135 #define CCM_REG_ERR_CCM_HDR 0xd0094
136 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
137 #define CCM_REG_ERR_EVNT_ID 0xd0098
138 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
139 writes the initial credit value; read returns the current value of the
140 credit counter. Must be initialized to 64 at start-up. */
141 #define CCM_REG_FIC0_INIT_CRD 0xd0210
142 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
143 writes the initial credit value; read returns the current value of the
144 credit counter. Must be initialized to 64 at start-up. */
145 #define CCM_REG_FIC1_INIT_CRD 0xd0214
146 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
147 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
148 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
149 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
150 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
151 #define CCM_REG_GR_ARB_TYPE 0xd015c
152 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
153 highest priority is 3. It is supposed; that the Store channel priority is
154 the compliment to 4 of the rest priorities - Aggregation channel; Load
155 (FIC0) channel and Load (FIC1). */
156 #define CCM_REG_GR_LD0_PR 0xd0164
157 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
158 highest priority is 3. It is supposed; that the Store channel priority is
159 the compliment to 4 of the rest priorities - Aggregation channel; Load
160 (FIC0) channel and Load (FIC1). */
161 #define CCM_REG_GR_LD1_PR 0xd0168
162 /* [RW 2] General flags index. */
163 #define CCM_REG_INV_DONE_Q 0xd0108
164 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
165 context and sent to STORM; for a specific connection type. The double
166 REG-pairs are used in order to align to STORM context row size of 128
167 bits. The offset of these data in the STORM context is always 0. Index
168 _(0..15) stands for the connection type (one of 16). */
169 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
170 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
171 #define CCM_REG_N_SM_CTX_LD_10 0xd0074
172 #define CCM_REG_N_SM_CTX_LD_11 0xd0078
173 #define CCM_REG_N_SM_CTX_LD_12 0xd007c
174 #define CCM_REG_N_SM_CTX_LD_13 0xd0080
175 #define CCM_REG_N_SM_CTX_LD_14 0xd0084
176 #define CCM_REG_N_SM_CTX_LD_15 0xd0088
177 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
178 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
179 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
180 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
181 acknowledge output is deasserted; all other signals are treated as usual;
182 if 1 - normal activity. */
183 #define CCM_REG_PBF_IFEN 0xd0028
184 /* [RC 1] Set when the message length mismatch (relative to last indication)
185 at the pbf interface is detected. */
186 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
187 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
188 weight 8 (the most prioritised); 1 stands for weight 1(least
189 prioritised); 2 stands for weight 2; tc. */
190 #define CCM_REG_PBF_WEIGHT 0xd00ac
191 /* [RW 6] The physical queue number of queue number 1 per port index. */
192 #define CCM_REG_PHYS_QNUM1_0 0xd0134
193 #define CCM_REG_PHYS_QNUM1_1 0xd0138
194 /* [RW 6] The physical queue number of queue number 2 per port index. */
195 #define CCM_REG_PHYS_QNUM2_0 0xd013c
196 #define CCM_REG_PHYS_QNUM2_1 0xd0140
197 /* [RW 6] The physical queue number of queue number 3 per port index. */
198 #define CCM_REG_PHYS_QNUM3_0 0xd0144
199 /* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port
201 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
202 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
203 /* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port
205 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
206 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
207 /* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port
209 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
210 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
211 disregarded; acknowledge output is deasserted; all other signals are
212 treated as usual; if 1 - normal activity. */
213 #define CCM_REG_STORM_CCM_IFEN 0xd0010
214 /* [RC 1] Set when the message length mismatch (relative to last indication)
215 at the STORM interface is detected. */
216 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
217 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
218 disregarded; acknowledge output is deasserted; all other signals are
219 treated as usual; if 1 - normal activity. */
220 #define CCM_REG_TSEM_IFEN 0xd001c
221 /* [RC 1] Set when the message length mismatch (relative to last indication)
222 at the tsem interface is detected. */
223 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
224 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
225 weight 8 (the most prioritised); 1 stands for weight 1(least
226 prioritised); 2 stands for weight 2; tc. */
227 #define CCM_REG_TSEM_WEIGHT 0xd00a0
228 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
229 disregarded; acknowledge output is deasserted; all other signals are
230 treated as usual; if 1 - normal activity. */
231 #define CCM_REG_USEM_IFEN 0xd0024
232 /* [RC 1] Set when message length mismatch (relative to last indication) at
233 the usem interface is detected. */
234 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
235 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
236 weight 8 (the most prioritised); 1 stands for weight 1(least
237 prioritised); 2 stands for weight 2; tc. */
238 #define CCM_REG_USEM_WEIGHT 0xd00a8
239 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
240 disregarded; acknowledge output is deasserted; all other signals are
241 treated as usual; if 1 - normal activity. */
242 #define CCM_REG_XSEM_IFEN 0xd0020
243 /* [RC 1] Set when the message length mismatch (relative to last indication)
244 at the xsem interface is detected. */
245 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
246 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
247 weight 8 (the most prioritised); 1 stands for weight 1(least
248 prioritised); 2 stands for weight 2; tc. */
249 #define CCM_REG_XSEM_WEIGHT 0xd00a4
250 /* [RW 19] Indirect access to the descriptor table of the XX protection
251 mechanism. The fields are: [5:0] - message length; [12:6] - message
252 pointer; 18:13] - next pointer. */
253 #define CCM_REG_XX_DESCR_TABLE 0xd0300
254 /* [R 7] Used to read the value of XX protection Free counter. */
255 #define CCM_REG_XX_FREE 0xd0184
256 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
257 of the Input Stage XX protection buffer by the XX protection pending
258 messages. Max credit available - 127. Write writes the initial credit
259 value; read returns the current value of the credit counter. Must be
260 initialized to maximum XX protected message size - 2 at start-up. */
261 #define CCM_REG_XX_INIT_CRD 0xd0220
262 /* [RW 7] The maximum number of pending messages; which may be stored in XX
263 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
264 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
266 #define CCM_REG_XX_MSG_NUM 0xd0224
267 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
268 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
269 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
270 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
272 #define CCM_REG_XX_TABLE 0xd0280
273 #define CDU_REG_CDU_CHK_MASK0 0x101000
274 #define CDU_REG_CDU_CHK_MASK1 0x101004
275 #define CDU_REG_CDU_CONTROL0 0x101008
276 #define CDU_REG_CDU_DEBUG 0x101010
277 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
278 /* [RW 7] Interrupt mask register #0 read/write */
279 #define CDU_REG_CDU_INT_MASK 0x10103c
280 /* [R 7] Interrupt register #0 read */
281 #define CDU_REG_CDU_INT_STS 0x101030
282 /* [RW 5] Parity mask register #0 read/write */
283 #define CDU_REG_CDU_PRTY_MASK 0x10104c
284 /* [RC 32] logging of error data in case of a CDU load error:
285 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
286 ype_error; ctual_active; ctual_compressed_context}; */
287 #define CDU_REG_ERROR_DATA 0x101014
288 /* [WB 216] L1TT ram access. each entry has the following format :
289 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
290 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
291 #define CDU_REG_L1TT 0x101800
292 /* [WB 24] MATT ram access. each entry has the following
293 format:{RegionLength[11:0]; egionOffset[11:0]} */
294 #define CDU_REG_MATT 0x101100
295 /* [R 1] indication the initializing the activity counter by the hardware
297 #define CFC_REG_AC_INIT_DONE 0x104078
298 /* [RW 13] activity counter ram access */
299 #define CFC_REG_ACTIVITY_COUNTER 0x104400
300 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
301 /* [R 1] indication the initializing the cams by the hardware was done. */
302 #define CFC_REG_CAM_INIT_DONE 0x10407c
303 /* [RW 2] Interrupt mask register #0 read/write */
304 #define CFC_REG_CFC_INT_MASK 0x104108
305 /* [R 2] Interrupt register #0 read */
306 #define CFC_REG_CFC_INT_STS 0x1040fc
307 /* [RC 2] Interrupt register #0 read clear */
308 #define CFC_REG_CFC_INT_STS_CLR 0x104100
309 /* [RW 4] Parity mask register #0 read/write */
310 #define CFC_REG_CFC_PRTY_MASK 0x104118
311 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
312 #define CFC_REG_CID_CAM 0x104800
313 #define CFC_REG_CONTROL0 0x104028
314 #define CFC_REG_DEBUG0 0x104050
315 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
316 vector) whether the cfc should be disabled upon it */
317 #define CFC_REG_DISABLE_ON_ERROR 0x104044
318 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
319 set one of these bits. the bit description can be found in CFC
321 #define CFC_REG_ERROR_VECTOR 0x10403c
322 #define CFC_REG_INIT_REG 0x10404c
323 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
324 field allows changing the priorities of the weighted-round-robin arbiter
325 which selects which CFC load client should be served next */
326 #define CFC_REG_LCREQ_WEIGHTS 0x104084
327 /* [R 1] indication the initializing the link list by the hardware was done. */
328 #define CFC_REG_LL_INIT_DONE 0x104074
329 /* [R 9] Number of allocated LCIDs which are at empty state */
330 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
331 /* [R 9] Number of Arriving LCIDs in Link List Block */
332 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
333 /* [R 9] Number of Inside LCIDs in Link List Block */
334 #define CFC_REG_NUM_LCIDS_INSIDE 0x104008
335 /* [R 9] Number of Leaving LCIDs in Link List Block */
336 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
337 /* [RW 8] The event id for aggregated interrupt 0 */
338 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
339 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
340 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
341 /* [RW 16] The maximum value of the competion counter #0 */
342 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
343 /* [RW 16] The maximum value of the competion counter #1 */
344 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
345 /* [RW 16] The maximum value of the competion counter #2 */
346 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
347 /* [RW 16] The maximum value of the competion counter #3 */
348 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
349 /* [RW 13] The start address in the internal RAM for the completion
351 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
352 /* [RW 32] Interrupt mask register #0 read/write */
353 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
354 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
355 /* [RW 11] Parity mask register #0 read/write */
356 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
357 #define CSDM_REG_ENABLE_IN1 0xc2238
358 #define CSDM_REG_ENABLE_IN2 0xc223c
359 #define CSDM_REG_ENABLE_OUT1 0xc2240
360 #define CSDM_REG_ENABLE_OUT2 0xc2244
361 /* [RW 4] The initial number of messages that can be sent to the pxp control
362 interface without receiving any ACK. */
363 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
364 /* [ST 32] The number of ACK after placement messages received */
365 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
366 /* [ST 32] The number of packet end messages received from the parser */
367 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
368 /* [ST 32] The number of requests received from the pxp async if */
369 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
370 /* [ST 32] The number of commands received in queue 0 */
371 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
372 /* [ST 32] The number of commands received in queue 10 */
373 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
374 /* [ST 32] The number of commands received in queue 11 */
375 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
376 /* [ST 32] The number of commands received in queue 1 */
377 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
378 /* [ST 32] The number of commands received in queue 3 */
379 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
380 /* [ST 32] The number of commands received in queue 4 */
381 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
382 /* [ST 32] The number of commands received in queue 5 */
383 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
384 /* [ST 32] The number of commands received in queue 6 */
385 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
386 /* [ST 32] The number of commands received in queue 7 */
387 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
388 /* [ST 32] The number of commands received in queue 8 */
389 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
390 /* [ST 32] The number of commands received in queue 9 */
391 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
392 /* [RW 13] The start address in the internal RAM for queue counters */
393 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
394 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
395 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
396 /* [R 1] parser fifo empty in sdm_sync block */
397 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
398 /* [R 1] parser serial fifo empty in sdm_sync block */
399 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
400 /* [RW 32] Tick for timer counter. Applicable only when
401 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
402 #define CSDM_REG_TIMER_TICK 0xc2000
403 /* [RW 5] The number of time_slots in the arbitration cycle */
404 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
405 /* [RW 3] The source that is associated with arbitration element 0. Source
406 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
407 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
408 #define CSEM_REG_ARB_ELEMENT0 0x200020
409 /* [RW 3] The source that is associated with arbitration element 1. Source
410 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
411 sleeping thread with priority 1; 4- sleeping thread with priority 2.
412 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
413 #define CSEM_REG_ARB_ELEMENT1 0x200024
414 /* [RW 3] The source that is associated with arbitration element 2. Source
415 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
416 sleeping thread with priority 1; 4- sleeping thread with priority 2.
417 Could not be equal to register ~csem_registers_arb_element0.arb_element0
418 and ~csem_registers_arb_element1.arb_element1 */
419 #define CSEM_REG_ARB_ELEMENT2 0x200028
420 /* [RW 3] The source that is associated with arbitration element 3. Source
421 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
422 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
423 not be equal to register ~csem_registers_arb_element0.arb_element0 and
424 ~csem_registers_arb_element1.arb_element1 and
425 ~csem_registers_arb_element2.arb_element2 */
426 #define CSEM_REG_ARB_ELEMENT3 0x20002c
427 /* [RW 3] The source that is associated with arbitration element 4. Source
428 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
429 sleeping thread with priority 1; 4- sleeping thread with priority 2.
430 Could not be equal to register ~csem_registers_arb_element0.arb_element0
431 and ~csem_registers_arb_element1.arb_element1 and
432 ~csem_registers_arb_element2.arb_element2 and
433 ~csem_registers_arb_element3.arb_element3 */
434 #define CSEM_REG_ARB_ELEMENT4 0x200030
435 /* [RW 32] Interrupt mask register #0 read/write */
436 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
437 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
438 /* [RW 32] Parity mask register #0 read/write */
439 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
440 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
441 #define CSEM_REG_ENABLE_IN 0x2000a4
442 #define CSEM_REG_ENABLE_OUT 0x2000a8
443 /* [RW 32] This address space contains all registers and memories that are
444 placed in SEM_FAST block. The SEM_FAST registers are described in
445 appendix B. In order to access the SEM_FAST registers the base address
446 CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each
447 SEM_FAST register offset. */
448 #define CSEM_REG_FAST_MEMORY 0x220000
449 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
451 #define CSEM_REG_FIC0_DISABLE 0x200224
452 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
454 #define CSEM_REG_FIC1_DISABLE 0x200234
455 /* [RW 15] Interrupt table Read and write access to it is not possible in
456 the middle of the work */
457 #define CSEM_REG_INT_TABLE 0x200400
458 /* [ST 24] Statistics register. The number of messages that entered through
460 #define CSEM_REG_MSG_NUM_FIC0 0x200000
461 /* [ST 24] Statistics register. The number of messages that entered through
463 #define CSEM_REG_MSG_NUM_FIC1 0x200004
464 /* [ST 24] Statistics register. The number of messages that were sent to
466 #define CSEM_REG_MSG_NUM_FOC0 0x200008
467 /* [ST 24] Statistics register. The number of messages that were sent to
469 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
470 /* [ST 24] Statistics register. The number of messages that were sent to
472 #define CSEM_REG_MSG_NUM_FOC2 0x200010
473 /* [ST 24] Statistics register. The number of messages that were sent to
475 #define CSEM_REG_MSG_NUM_FOC3 0x200014
476 /* [RW 1] Disables input messages from the passive buffer May be updated
477 during run_time by the microcode */
478 #define CSEM_REG_PAS_DISABLE 0x20024c
479 /* [WB 128] Debug only. Passive buffer memory */
480 #define CSEM_REG_PASSIVE_BUFFER 0x202000
481 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
482 #define CSEM_REG_PRAM 0x240000
483 /* [R 16] Valid sleeping threads indication have bit per thread */
484 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
485 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
486 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
487 /* [RW 16] List of free threads . There is a bit per thread. */
488 #define CSEM_REG_THREADS_LIST 0x2002e4
489 /* [RW 3] The arbitration scheme of time_slot 0 */
490 #define CSEM_REG_TS_0_AS 0x200038
491 /* [RW 3] The arbitration scheme of time_slot 10 */
492 #define CSEM_REG_TS_10_AS 0x200060
493 /* [RW 3] The arbitration scheme of time_slot 11 */
494 #define CSEM_REG_TS_11_AS 0x200064
495 /* [RW 3] The arbitration scheme of time_slot 12 */
496 #define CSEM_REG_TS_12_AS 0x200068
497 /* [RW 3] The arbitration scheme of time_slot 13 */
498 #define CSEM_REG_TS_13_AS 0x20006c
499 /* [RW 3] The arbitration scheme of time_slot 14 */
500 #define CSEM_REG_TS_14_AS 0x200070
501 /* [RW 3] The arbitration scheme of time_slot 15 */
502 #define CSEM_REG_TS_15_AS 0x200074
503 /* [RW 3] The arbitration scheme of time_slot 16 */
504 #define CSEM_REG_TS_16_AS 0x200078
505 /* [RW 3] The arbitration scheme of time_slot 17 */
506 #define CSEM_REG_TS_17_AS 0x20007c
507 /* [RW 3] The arbitration scheme of time_slot 18 */
508 #define CSEM_REG_TS_18_AS 0x200080
509 /* [RW 3] The arbitration scheme of time_slot 1 */
510 #define CSEM_REG_TS_1_AS 0x20003c
511 /* [RW 3] The arbitration scheme of time_slot 2 */
512 #define CSEM_REG_TS_2_AS 0x200040
513 /* [RW 3] The arbitration scheme of time_slot 3 */
514 #define CSEM_REG_TS_3_AS 0x200044
515 /* [RW 3] The arbitration scheme of time_slot 4 */
516 #define CSEM_REG_TS_4_AS 0x200048
517 /* [RW 3] The arbitration scheme of time_slot 5 */
518 #define CSEM_REG_TS_5_AS 0x20004c
519 /* [RW 3] The arbitration scheme of time_slot 6 */
520 #define CSEM_REG_TS_6_AS 0x200050
521 /* [RW 3] The arbitration scheme of time_slot 7 */
522 #define CSEM_REG_TS_7_AS 0x200054
523 /* [RW 3] The arbitration scheme of time_slot 8 */
524 #define CSEM_REG_TS_8_AS 0x200058
525 /* [RW 3] The arbitration scheme of time_slot 9 */
526 #define CSEM_REG_TS_9_AS 0x20005c
527 /* [RW 1] Parity mask register #0 read/write */
528 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
529 /* [RW 2] debug only: These bits indicate the credit for PCI request type 4
530 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
532 #define DBG_REG_PCI_REQ_CREDIT 0xc120
533 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
535 #define DMAE_REG_CMD_MEM 0x102400
536 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
537 initial value is all ones. */
538 #define DMAE_REG_CRC16C_INIT 0x10201c
539 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
540 CRC-16 T10 initial value is all ones. */
541 #define DMAE_REG_CRC16T10_INIT 0x102020
542 /* [RW 2] Interrupt mask register #0 read/write */
543 #define DMAE_REG_DMAE_INT_MASK 0x102054
544 /* [RW 4] Parity mask register #0 read/write */
545 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
546 /* [RW 1] Command 0 go. */
547 #define DMAE_REG_GO_C0 0x102080
548 /* [RW 1] Command 1 go. */
549 #define DMAE_REG_GO_C1 0x102084
550 /* [RW 1] Command 10 go. */
551 #define DMAE_REG_GO_C10 0x102088
552 #define DMAE_REG_GO_C10_SIZE 1
553 /* [RW 1] Command 11 go. */
554 #define DMAE_REG_GO_C11 0x10208c
555 #define DMAE_REG_GO_C11_SIZE 1
556 /* [RW 1] Command 12 go. */
557 #define DMAE_REG_GO_C12 0x102090
558 #define DMAE_REG_GO_C12_SIZE 1
559 /* [RW 1] Command 13 go. */
560 #define DMAE_REG_GO_C13 0x102094
561 #define DMAE_REG_GO_C13_SIZE 1
562 /* [RW 1] Command 14 go. */
563 #define DMAE_REG_GO_C14 0x102098
564 #define DMAE_REG_GO_C14_SIZE 1
565 /* [RW 1] Command 15 go. */
566 #define DMAE_REG_GO_C15 0x10209c
567 #define DMAE_REG_GO_C15_SIZE 1
568 /* [RW 1] Command 10 go. */
569 #define DMAE_REG_GO_C10 0x102088
570 /* [RW 1] Command 11 go. */
571 #define DMAE_REG_GO_C11 0x10208c
572 /* [RW 1] Command 12 go. */
573 #define DMAE_REG_GO_C12 0x102090
574 /* [RW 1] Command 13 go. */
575 #define DMAE_REG_GO_C13 0x102094
576 /* [RW 1] Command 14 go. */
577 #define DMAE_REG_GO_C14 0x102098
578 /* [RW 1] Command 15 go. */
579 #define DMAE_REG_GO_C15 0x10209c
580 /* [RW 1] Command 2 go. */
581 #define DMAE_REG_GO_C2 0x1020a0
582 /* [RW 1] Command 3 go. */
583 #define DMAE_REG_GO_C3 0x1020a4
584 /* [RW 1] Command 4 go. */
585 #define DMAE_REG_GO_C4 0x1020a8
586 /* [RW 1] Command 5 go. */
587 #define DMAE_REG_GO_C5 0x1020ac
588 /* [RW 1] Command 6 go. */
589 #define DMAE_REG_GO_C6 0x1020b0
590 /* [RW 1] Command 7 go. */
591 #define DMAE_REG_GO_C7 0x1020b4
592 /* [RW 1] Command 8 go. */
593 #define DMAE_REG_GO_C8 0x1020b8
594 /* [RW 1] Command 9 go. */
595 #define DMAE_REG_GO_C9 0x1020bc
596 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
597 input is disregarded; valid is deasserted; all other signals are treated
598 as usual; if 1 - normal activity. */
599 #define DMAE_REG_GRC_IFEN 0x102008
600 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
601 acknowledge input is disregarded; valid is deasserted; full is asserted;
602 all other signals are treated as usual; if 1 - normal activity. */
603 #define DMAE_REG_PCI_IFEN 0x102004
604 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
605 initial value to the credit counter; related to the address. Read returns
606 the current value of the counter. */
607 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
608 /* [RW 8] Aggregation command. */
609 #define DORQ_REG_AGG_CMD0 0x170060
610 /* [RW 8] Aggregation command. */
611 #define DORQ_REG_AGG_CMD1 0x170064
612 /* [RW 8] Aggregation command. */
613 #define DORQ_REG_AGG_CMD2 0x170068
614 /* [RW 8] Aggregation command. */
615 #define DORQ_REG_AGG_CMD3 0x17006c
616 /* [RW 28] UCM Header. */
617 #define DORQ_REG_CMHEAD_RX 0x170050
618 /* [RW 5] Interrupt mask register #0 read/write */
619 #define DORQ_REG_DORQ_INT_MASK 0x170180
620 /* [R 5] Interrupt register #0 read */
621 #define DORQ_REG_DORQ_INT_STS 0x170174
622 /* [RC 5] Interrupt register #0 read clear */
623 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
624 /* [RW 2] Parity mask register #0 read/write */
625 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
626 /* [RW 8] The address to write the DPM CID to STORM. */
627 #define DORQ_REG_DPM_CID_ADDR 0x170044
628 /* [RW 5] The DPM mode CID extraction offset. */
629 #define DORQ_REG_DPM_CID_OFST 0x170030
630 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
631 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
632 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
633 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
634 /* [R 13] Current value of the DQ FIFO fill level according to following
635 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
637 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
638 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
639 equal to full threshold; reset on full clear. */
640 #define DORQ_REG_DQ_FULL_ST 0x1700c0
641 /* [RW 28] The value sent to CM header in the case of CFC load error. */
642 #define DORQ_REG_ERR_CMHEAD 0x170058
643 #define DORQ_REG_IF_EN 0x170004
644 #define DORQ_REG_MODE_ACT 0x170008
645 /* [RW 5] The normal mode CID extraction offset. */
646 #define DORQ_REG_NORM_CID_OFST 0x17002c
647 /* [RW 28] TCM Header when only TCP context is loaded. */
648 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
649 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
651 #define DORQ_REG_OUTST_REQ 0x17003c
652 #define DORQ_REG_REGN 0x170038
653 /* [R 4] Current value of response A counter credit. Initial credit is
654 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
656 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
657 /* [R 4] Current value of response B counter credit. Initial credit is
658 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
660 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
661 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
662 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
663 read reads this written value. */
664 #define DORQ_REG_RSP_INIT_CRD 0x170048
665 /* [RW 4] Initial activity counter value on the load request; when the
667 #define DORQ_REG_SHRT_ACT_CNT 0x170070
668 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
669 #define DORQ_REG_SHRT_CMHEAD 0x170054
670 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
671 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
672 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
673 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
674 #define HC_REG_AGG_INT_0 0x108050
675 #define HC_REG_AGG_INT_1 0x108054
676 /* [RW 16] attention bit and attention acknowledge bits status for port 0
677 and 1 according to the following address map: addr 0 - attn_bit_0; addr 1
678 - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1; */
679 #define HC_REG_ATTN_BIT 0x108120
680 /* [RW 16] attn bits status index for attn bit msg; addr 0 - function 0;
681 addr 1 - functin 1 */
682 #define HC_REG_ATTN_IDX 0x108100
683 /* [RW 32] port 0 lower 32 bits address field for attn messag. */
684 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
685 /* [RW 32] port 1 lower 32 bits address field for attn messag. */
686 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
687 /* [RW 8] status block number for attn bit msg - function 0; */
688 #define HC_REG_ATTN_NUM_P0 0x108038
689 /* [RW 8] status block number for attn bit msg - function 1 */
690 #define HC_REG_ATTN_NUM_P1 0x10803c
691 #define HC_REG_CONFIG_0 0x108000
692 #define HC_REG_CONFIG_1 0x108004
693 /* [RW 3] Parity mask register #0 read/write */
694 #define HC_REG_HC_PRTY_MASK 0x1080a0
695 /* [RW 17] status block interrupt mask; one in each bit means unmask; zerow
696 in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1...
697 bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */
698 #define HC_REG_INT_MASK 0x108108
699 /* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
700 lock a change fron 0 to 1 in the corresponding attention signals that
701 comes from the AEU */
702 #define HC_REG_LEADING_EDGE_0 0x108040
703 #define HC_REG_LEADING_EDGE_1 0x108048
704 /* [RW 16] all producer and consumer of port 0 according to the following
705 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
706 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
707 U/C/X/T/Attn-69/70/71/72/73 */
708 #define HC_REG_P0_PROD_CONS 0x108200
709 /* [RW 16] all producer and consumer of port 1according to the following
710 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
711 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
712 U/C/X/T/Attn-69/70/71/72/73 */
713 #define HC_REG_P1_PROD_CONS 0x108400
714 /* [W 1] This register is write only and has 4 addresses as follow: 0 =
715 clear all PBA bits port 0; 1 = clear all pending interrupts request
716 port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts
717 request port1; here is no meaning for the data in this register */
718 #define HC_REG_PBA_COMMAND 0x108140
719 #define HC_REG_PCI_CONFIG_0 0x108010
720 #define HC_REG_PCI_CONFIG_1 0x108014
721 /* [RW 24] all counters acording to the following address: LSB: 0=read; 1=
722 read_clear; 0-71 = HW counters (the inside order is the same as the
723 interrupt table in the spec); 72-219 = SW counters 1 (stops after first
724 consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135
725 C_non_defaul_p0; 36-145 U/C/X/T/Attn_default_p0; 146-177
726 U_non_default_p1; 178-209 C_non_defaul_p1; 10-219 U/C/X/T/Attn_default_p1
727 ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is:
728 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0; 84-293
729 U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357
730 C_non_defaul_p1; 58-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox
731 counters; (the inside order of the mailbox counter is 368-431 U and C
732 non_default_p0; 432-441 U/C/X/T/Attn_default_p0; 442-505 U and C
733 non_default_p1; 506-515 U/C/X/T/Attn_default_p1) */
734 #define HC_REG_STATISTIC_COUNTERS 0x109000
735 /* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
736 lock a change fron 1 to 0 in the corresponding attention signals that
737 comes from the AEU */
738 #define HC_REG_TRAILING_EDGE_0 0x108044
739 #define HC_REG_TRAILING_EDGE_1 0x10804c
740 #define HC_REG_UC_RAM_ADDR_0 0x108028
741 #define HC_REG_UC_RAM_ADDR_1 0x108030
742 /* [RW 16] ustorm address for coalesc now message */
743 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
744 #define HC_REG_VQID_0 0x108008
745 #define HC_REG_VQID_1 0x10800c
746 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
747 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
748 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
749 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
750 #define MCP_REG_MCPR_NVM_READ 0x86410
751 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
752 #define MCP_REG_MCPR_NVM_WRITE 0x86408
753 #define MCP_REG_MCPR_NVM_WRITE1 0x86428
754 #define MCP_REG_MCPR_SCRATCH 0xa0000
755 /* [R 32] read first 32 bit after inversion of function 0. mapped as
756 follows: [0] NIG attention for function0; [1] NIG attention for
757 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
758 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
759 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
760 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
761 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
762 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
763 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
764 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
765 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
766 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
767 Parity error; [31] PBF Hw interrupt; */
768 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
769 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
770 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
771 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
772 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
773 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
774 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
775 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
776 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
777 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
778 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
779 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
780 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
781 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
783 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
784 /* [R 32] read second 32 bit after inversion of function 0. mapped as
785 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
786 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
787 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
788 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
789 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
790 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
791 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
792 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
793 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
794 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
795 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
797 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
798 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
799 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
800 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
801 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
802 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
803 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
804 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
805 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
806 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
807 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
808 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
809 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
810 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
811 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
812 /* [R 32] read third 32 bit after inversion of function 0. mapped as
813 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
814 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
815 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
816 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
817 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
818 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
819 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
820 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
821 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
822 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
823 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
825 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
826 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
827 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
828 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
829 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
830 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
831 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
832 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
833 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
834 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
835 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
836 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
837 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
838 timers attn_4 func1; [30] General attn0; [31] General attn1; */
839 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
840 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
841 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
842 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
843 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
844 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
845 [14] General attn16; [15] General attn17; [16] General attn18; [17]
846 General attn19; [18] General attn20; [19] General attn21; [20] Main power
847 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
848 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
849 Latched timeout attention; [27] GRC Latched reserved access attention;
850 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
851 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
852 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
853 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
854 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
855 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
856 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
857 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
858 General attn13; [12] General attn14; [13] General attn15; [14] General
859 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
860 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
861 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
862 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
863 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
864 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
865 ump_tx_parity; [31] MCP Latched scpad_parity; */
866 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
867 /* [W 11] write to this register results with the clear of the latched
868 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
869 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
870 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
871 GRC Latched reserved access attention; one in d7 clears Latched
872 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
873 Latched ump_tx_parity; one in d10 clears Latched scpad_parity; read from
874 this register return zero */
875 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
876 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
877 as follows: [0] NIG attention for function0; [1] NIG attention for
878 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
879 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
880 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
881 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
882 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
883 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
884 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
885 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
886 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
887 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
888 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
889 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
890 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
891 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
892 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
893 as follows: [0] NIG attention for function0; [1] NIG attention for
894 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
895 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
896 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
897 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
898 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
899 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
900 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
901 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
902 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
903 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
904 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
905 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
906 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
907 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
908 /* [RW 32] first 32b for enabling the output for close the gate nig 0.
909 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
910 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
911 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
912 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
913 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
914 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
915 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
916 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
917 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
918 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
919 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
920 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
921 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
922 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
923 /* [RW 32] first 32b for enabling the output for close the gate pxp 0.
924 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
925 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
926 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
927 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
928 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
929 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
930 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
931 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
932 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
933 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
934 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
935 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
936 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
937 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
938 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
939 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
940 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
941 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
942 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
943 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
944 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
945 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
946 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
947 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
948 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
949 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
951 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
952 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
953 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
954 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
955 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
956 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
957 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
958 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
959 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
960 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
961 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
962 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
963 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
964 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
966 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
967 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
968 /* [RW 32] second 32b for enabling the output for close the gate nig 0.
969 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
970 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
971 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
972 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
973 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
974 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
975 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
976 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
977 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
978 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
979 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
980 Parity error; [31] CCM Hw interrupt; */
981 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
982 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
983 /* [RW 32] second 32b for enabling the output for close the gate pxp 0.
984 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
985 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
986 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
987 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
988 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
989 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
990 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
991 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
992 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
993 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
994 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
995 Parity error; [31] CCM Hw interrupt; */
996 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
997 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
998 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
999 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1000 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1001 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1002 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1003 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1004 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1005 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1006 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1007 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1008 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1009 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1011 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1012 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1013 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1014 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1015 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1016 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1017 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1018 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1019 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1020 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1021 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1022 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1023 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1024 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1026 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1027 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1028 /* [RW 32] third 32b for enabling the output for close the gate nig 0.
1029 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1030 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1031 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1032 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1033 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1034 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1035 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1036 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1037 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1038 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1039 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1041 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1042 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1043 /* [RW 32] third 32b for enabling the output for close the gate pxp 0.
1044 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1045 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1046 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1047 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1048 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1049 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1050 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1051 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1052 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1053 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1054 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1056 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1057 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1058 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1059 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1060 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1061 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1062 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1063 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1064 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1065 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1066 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1067 Latched timeout attention; [27] GRC Latched reserved access attention;
1068 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1069 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1070 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1071 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1072 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1073 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1074 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1075 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1076 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1077 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1078 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1079 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1080 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1081 Latched timeout attention; [27] GRC Latched reserved access attention;
1082 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1083 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1084 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1085 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1086 /* [RW 32] fourth 32b for enabling the output for close the gate nig
1087 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1088 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1089 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1090 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1091 General attn15; [14] General attn16; [15] General attn17; [16] General
1092 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1093 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1094 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1095 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1096 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1097 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1099 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1100 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1101 /* [RW 32] fourth 32b for enabling the output for close the gate pxp
1102 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1103 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1104 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1105 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1106 General attn15; [14] General attn16; [15] General attn17; [16] General
1107 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1108 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1109 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1110 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1111 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1112 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1114 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1115 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1116 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1118 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1119 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1120 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1121 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1122 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1123 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1124 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1125 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1126 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1127 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1128 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1129 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1130 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1131 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1132 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1133 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1134 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1135 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1136 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1137 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1138 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1139 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1140 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1141 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1142 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1143 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1144 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1145 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1146 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1147 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1148 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1149 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1150 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1151 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1152 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1153 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1154 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1155 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1156 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1157 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1158 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1159 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1160 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1161 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1162 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1163 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1164 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1165 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1166 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1167 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1168 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1169 [9:8] = mask close the gates signals of function 0 toward PXP [8] and NIG
1170 [9]. Zero = mask; one = unmask */
1171 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1172 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1173 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1175 #define MISC_REG_BOND_ID 0xa400
1176 /* [R 8] These bits indicate the metal revision of the chip. This value
1177 starts at 0x00 for each all-layer tape-out and increments by one for each
1179 #define MISC_REG_CHIP_METAL 0xa404
1180 /* [R 16] These bits indicate the part number for the chip. */
1181 #define MISC_REG_CHIP_NUM 0xa408
1182 /* [R 4] These bits indicate the base revision of the chip. This value
1183 starts at 0x0 for the A0 tape-out and increments by one for each
1184 all-layer tape-out. */
1185 #define MISC_REG_CHIP_REV 0xa40c
1186 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1187 access that does not finish within
1188 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1189 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1190 assert it attention output. */
1191 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1192 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1193 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1194 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1195 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1196 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1197 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1198 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1199 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1200 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1201 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1202 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1203 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1204 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1205 connected to RESET input directly. [15] capRetry_en (reset value 0)
1206 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1207 value 0) bit to continuously monitor vco freq (inverted). [17]
1208 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1209 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1210 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1211 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1212 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1213 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1214 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1215 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1216 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1217 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1218 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1220 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1221 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1222 /* [RW 4] Interrupt mask register #0 read/write */
1223 #define MISC_REG_MISC_INT_MASK 0xa388
1224 /* [RW 1] Parity mask register #0 read/write */
1225 #define MISC_REG_MISC_PRTY_MASK 0xa398
1226 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1227 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1228 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1229 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1230 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1231 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1232 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1233 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1234 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1235 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1236 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1237 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1238 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1239 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1240 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1241 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1242 testa_en (reset value 0); */
1243 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1244 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1245 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1246 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1247 /* [RW 32] reset reg#1; rite/read one = the specific block is out of reset;
1248 write/read zero = the specific block is in reset; addr 0-wr- the write
1249 value will be written to the register; addr 1-set - one will be written
1250 to all the bits that have the value of one in the data written (bits that
1251 have the value of zero will not be change) ; addr 2-clear - zero will be
1252 written to all the bits that have the value of one in the data written
1253 (bits that have the value of zero will not be change); addr 3-ignore;
1254 read ignore from all addr except addr 00; inside order of the bits is:
1255 [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5]
1256 rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10]
1257 rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15]
1258 rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20]
1259 rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25]
1260 rst_cfc; [26] rst_pxp; [27] rst_pxpv; [28] rst_rbcp; [29] rst_hc; [30]
1261 rst_dmae; [31] rst_semi_rtc; */
1262 #define MISC_REG_RESET_REG_1 0xa580
1263 #define MISC_REG_RESET_REG_2 0xa590
1264 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1265 shared with the driver resides */
1266 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1267 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1268 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1269 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1270 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1271 /* [RW 1] Input enable for RX_BMAC0 IF */
1272 #define NIG_REG_BMAC0_IN_EN 0x100ac
1273 /* [RW 1] output enable for TX_BMAC0 IF */
1274 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1275 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1276 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1277 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1278 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1279 /* [RW 1] output enable for RX BRB1 port0 IF */
1280 #define NIG_REG_BRB0_OUT_EN 0x100f8
1281 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1282 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1283 /* [RW 1] output enable for RX BRB1 port1 IF */
1284 #define NIG_REG_BRB1_OUT_EN 0x100fc
1285 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1286 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1287 /* [RW 1] output enable for RX BRB1 LP IF */
1288 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1289 /* [WB_W 72] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1290 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush */
1291 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1292 /* [RW 1] Input enable for TX Debug packet */
1293 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1294 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1295 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1296 First packet may be deleted from the middle. And last packet will be
1297 always deleted till the end. */
1298 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1299 /* [RW 1] Output enable to EMAC0 */
1300 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1301 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1302 to emac for port0; other way to bmac for port0 */
1303 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1304 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1305 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1306 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1307 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1308 /* [RW 1] Input enable for RX_EMAC0 IF */
1309 #define NIG_REG_EMAC0_IN_EN 0x100a4
1310 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1311 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1312 /* [R 1] status from emac0. This bit is set when MDINT from either the
1313 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1314 be cleared in the attached PHY device that is driving the MINT pin. */
1315 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1316 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1317 are described in appendix A. In order to access the BMAC0 registers; the
1318 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1319 added to each BMAC register offset */
1320 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1321 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1322 are described in appendix A. In order to access the BMAC0 registers; the
1323 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1324 added to each BMAC register offset */
1325 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1326 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1327 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1328 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1329 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1330 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1331 /* [RW 1] led 10g for port 0 */
1332 #define NIG_REG_LED_10G_P0 0x10320
1333 /* [RW 1] Port0: This bit is set to enable the use of the
1334 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1335 defined below. If this bit is cleared; then the blink rate will be about
1337 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1338 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1339 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1340 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1341 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1342 /* [RW 1] Port0: If set along with the
1343 nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1344 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1345 bit; the Traffic LED will blink with the blink rate specified in
1346 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1347 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1349 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1350 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1351 Traffic LED will then be controlled via bit ~nig_registers_
1352 led_control_traffic_p0.led_control_traffic_p0 and bit
1353 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1354 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1355 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1356 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1357 set; the LED will blink with blink rate specified in
1358 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1359 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1361 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1362 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1363 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1364 #define NIG_REG_LED_MODE_P0 0x102f0
1365 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1366 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1367 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1368 /* [RW 32] cm header for llh0 */
1369 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1370 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1371 /* [RW 8] event id for llh0 */
1372 #define NIG_REG_LLH0_EVENT_ID 0x10084
1373 /* [RW 8] init credit counter for port0 in LLH */
1374 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1375 #define NIG_REG_LLH0_XCM_MASK 0x10130
1376 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1377 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1378 /* [RW 32] cm header for llh1 */
1379 #define NIG_REG_LLH1_CM_HEADER 0x10080
1380 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1381 /* [RW 8] event id for llh1 */
1382 #define NIG_REG_LLH1_EVENT_ID 0x10088
1383 /* [RW 8] init credit counter for port1 in LLH */
1384 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1385 #define NIG_REG_LLH1_XCM_MASK 0x10134
1386 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1387 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1388 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1389 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1390 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1391 EMAC0 to strip the CRC from the ingress packets. */
1392 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1393 /* [RW 1] Input enable for RX PBF LP IF */
1394 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1395 /* [RW 1] output enable for RX parser descriptor IF */
1396 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1397 /* [RW 1] Input enable for RX parser request IF */
1398 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1399 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1400 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1401 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1402 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1403 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1405 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1406 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1408 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1409 /* [WB_R 64] Rx statistics : User octets received for LP */
1410 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1411 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1412 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1413 /* [RW 1] output enable for RX_XCM0 IF */
1414 #define NIG_REG_XCM0_OUT_EN 0x100f0
1415 /* [RW 1] output enable for RX_XCM1 IF */
1416 #define NIG_REG_XCM1_OUT_EN 0x100f4
1417 /* [RW 5] control to xgxs - CL45 DEVAD */
1418 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1419 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1420 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1421 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1422 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1423 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1424 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1425 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1426 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1427 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1428 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1429 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1430 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1431 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1432 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1433 /* [RW 1] Disable processing further tasks from port 0 (after ending the
1434 current task in process). */
1435 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1436 /* [RW 1] Disable processing further tasks from port 1 (after ending the
1437 current task in process). */
1438 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1439 /* [RW 1] Disable processing further tasks from port 4 (after ending the
1440 current task in process). */
1441 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1442 #define PBF_REG_IF_ENABLE_REG 0x140044
1443 /* [RW 1] Init bit. When set the initial credits are copied to the credit
1444 registers (except the port credits). Should be set and then reset after
1445 the configuration of the block has ended. */
1446 #define PBF_REG_INIT 0x140000
1447 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1448 copied to the credit register. Should be set and then reset after the
1449 configuration of the port has ended. */
1450 #define PBF_REG_INIT_P0 0x140004
1451 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1452 copied to the credit register. Should be set and then reset after the
1453 configuration of the port has ended. */
1454 #define PBF_REG_INIT_P1 0x140008
1455 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1456 copied to the credit register. Should be set and then reset after the
1457 configuration of the port has ended. */
1458 #define PBF_REG_INIT_P4 0x14000c
1459 /* [RW 1] Enable for mac interface 0. */
1460 #define PBF_REG_MAC_IF0_ENABLE 0x140030
1461 /* [RW 1] Enable for mac interface 1. */
1462 #define PBF_REG_MAC_IF1_ENABLE 0x140034
1463 /* [RW 1] Enable for the loopback interface. */
1464 #define PBF_REG_MAC_LB_ENABLE 0x140040
1465 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1467 #define PBF_REG_P0_ARB_THRSH 0x1400e4
1468 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1469 #define PBF_REG_P0_CREDIT 0x140200
1470 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1472 #define PBF_REG_P0_INIT_CRD 0x1400d0
1473 /* [RW 1] Indication that pause is enabled for port 0. */
1474 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
1475 /* [R 8] Number of tasks in port 0 task queue. */
1476 #define PBF_REG_P0_TASK_CNT 0x140204
1477 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1478 #define PBF_REG_P1_CREDIT 0x140208
1479 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1481 #define PBF_REG_P1_INIT_CRD 0x1400d4
1482 /* [R 8] Number of tasks in port 1 task queue. */
1483 #define PBF_REG_P1_TASK_CNT 0x14020c
1484 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1485 #define PBF_REG_P4_CREDIT 0x140210
1486 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1488 #define PBF_REG_P4_INIT_CRD 0x1400e0
1489 /* [R 8] Number of tasks in port 4 task queue. */
1490 #define PBF_REG_P4_TASK_CNT 0x140214
1491 /* [RW 5] Interrupt mask register #0 read/write */
1492 #define PBF_REG_PBF_INT_MASK 0x1401d4
1493 /* [R 5] Interrupt register #0 read */
1494 #define PBF_REG_PBF_INT_STS 0x1401c8
1495 #define PB_REG_CONTROL 0
1496 /* [RW 2] Interrupt mask register #0 read/write */
1497 #define PB_REG_PB_INT_MASK 0x28
1498 /* [R 2] Interrupt register #0 read */
1499 #define PB_REG_PB_INT_STS 0x1c
1500 /* [RW 4] Parity mask register #0 read/write */
1501 #define PB_REG_PB_PRTY_MASK 0x38
1502 #define PRS_REG_A_PRSU_20 0x40134
1503 /* [R 8] debug only: CFC load request current credit. Transaction based. */
1504 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1505 /* [R 8] debug only: CFC search request current credit. Transaction based. */
1506 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1507 /* [RW 6] The initial credit for the search message to the CFC interface.
1508 Credit is transaction based. */
1509 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1510 /* [RW 24] CID for port 0 if no match */
1511 #define PRS_REG_CID_PORT_0 0x400fc
1512 #define PRS_REG_CID_PORT_1 0x40100
1513 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1514 load response is reset and packet type is 0. Used in packet start message
1516 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1517 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1518 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1519 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1520 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1521 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1522 load response is set and packet type is 0. Used in packet start message
1524 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1525 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1526 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1527 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1528 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1529 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
1530 Used in packet start message to TCM. */
1531 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1532 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1533 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1534 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1535 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
1537 #define PRS_REG_CM_HDR_TYPE_0 0x40078
1538 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
1539 #define PRS_REG_CM_HDR_TYPE_2 0x40080
1540 #define PRS_REG_CM_HDR_TYPE_3 0x40084
1541 #define PRS_REG_CM_HDR_TYPE_4 0x40088
1542 /* [RW 32] The CM header in case there was not a match on the connection */
1543 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1544 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1545 start message to TCM. */
1546 #define PRS_REG_EVENT_ID_1 0x40054
1547 #define PRS_REG_EVENT_ID_2 0x40058
1548 #define PRS_REG_EVENT_ID_3 0x4005c
1549 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1550 load request message. */
1551 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1552 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1553 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1554 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1555 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1556 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1557 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1558 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1559 /* [RW 4] The increment value to send in the CFC load request message */
1560 #define PRS_REG_INC_VALUE 0x40048
1561 /* [RW 1] If set indicates not to send messages to CFC on received packets */
1562 #define PRS_REG_NIC_MODE 0x40138
1563 /* [RW 8] The 8-bit event ID for cases where there is no match on the
1564 connection. Used in packet start message to TCM. */
1565 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1566 /* [ST 24] The number of input CFC flush packets */
1567 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1568 /* [ST 32] The number of cycles the Parser halted its operation since it
1569 could not allocate the next serial number */
1570 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1571 /* [ST 24] The number of input packets */
1572 #define PRS_REG_NUM_OF_PACKETS 0x40124
1573 /* [ST 24] The number of input transparent flush packets */
1574 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
1575 /* [RW 8] Context region for received Ethernet packet with a match and
1576 packet type 0. Used in CFC load request message */
1577 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
1578 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
1579 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
1580 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
1581 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
1582 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
1583 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
1584 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
1585 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
1586 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
1587 /* [R 2] debug only: Number of pending requests for header parsing. */
1588 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
1589 /* [R 1] Interrupt register #0 read */
1590 #define PRS_REG_PRS_INT_STS 0x40188
1591 /* [RW 8] Parity mask register #0 read/write */
1592 #define PRS_REG_PRS_PRTY_MASK 0x401a4
1593 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
1595 #define PRS_REG_PURE_REGIONS 0x40024
1596 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
1597 serail number was released by SDM but cannot be used because a previous
1598 serial number was not released. */
1599 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
1600 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
1601 serail number was released by SDM but cannot be used because a previous
1602 serial number was not released. */
1603 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
1604 /* [R 4] debug only: SRC current credit. Transaction based. */
1605 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
1606 /* [R 8] debug only: TCM current credit. Cycle based. */
1607 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
1608 /* [R 8] debug only: TSDM current credit. Transaction based. */
1609 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
1610 /* [R 6] Debug only: Number of used entries in the data FIFO */
1611 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1612 /* [R 7] Debug only: Number of used entries in the header FIFO */
1613 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1614 #define PXP2_REG_PGL_CONTROL0 0x120490
1615 #define PXP2_REG_PGL_CONTROL1 0x120514
1616 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1617 its[15:0]-address */
1618 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
1619 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
1620 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
1621 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
1622 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
1623 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
1624 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
1625 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
1626 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
1627 its[15:0]-address */
1628 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
1629 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
1630 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
1631 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
1632 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
1633 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
1634 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
1635 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
1636 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
1637 its[15:0]-address */
1638 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
1639 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
1640 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
1641 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
1642 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
1643 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
1644 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
1645 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
1646 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
1647 its[15:0]-address */
1648 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
1649 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
1650 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
1651 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
1652 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
1653 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
1654 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
1655 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
1656 /* [R 1] this bit indicates that a read request was blocked because of
1657 bus_master_en was deasserted */
1658 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
1659 /* [R 6] debug only */
1660 #define PXP2_REG_PGL_TXR_CDTS 0x120528
1661 /* [R 18] debug only */
1662 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
1663 /* [R 1] this bit indicates that a write request was blocked because of
1664 bus_master_en was deasserted */
1665 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
1666 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
1667 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1668 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1669 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1670 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1671 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
1672 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1673 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1674 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
1675 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
1676 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
1677 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
1678 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
1679 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
1680 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
1681 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1682 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1683 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1684 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1685 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
1686 #define PXP2_REG_PSWRQ_BW_L28 0x120318
1687 #define PXP2_REG_PSWRQ_BW_L28 0x120318
1688 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
1689 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
1690 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
1691 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
1692 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
1693 #define PXP2_REG_PSWRQ_BW_RD 0x120324
1694 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
1695 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1696 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
1697 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1698 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
1699 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
1700 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1701 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1702 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
1703 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
1704 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
1705 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
1706 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
1707 #define PXP2_REG_PSWRQ_BW_WR 0x120328
1708 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
1709 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
1710 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
1711 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
1712 /* [RW 25] Interrupt mask register #0 read/write */
1713 #define PXP2_REG_PXP2_INT_MASK 0x120578
1714 /* [R 25] Interrupt register #0 read */
1715 #define PXP2_REG_PXP2_INT_STS 0x12056c
1716 /* [RC 25] Interrupt register #0 read clear */
1717 #define PXP2_REG_PXP2_INT_STS_CLR 0x120570
1718 /* [RW 32] Parity mask register #0 read/write */
1719 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
1720 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
1721 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
1722 indication about backpressure) */
1723 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
1724 /* [R 8] Debug only: The blocks counter - number of unused block ids */
1725 #define PXP2_REG_RD_BLK_CNT 0x120418
1726 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
1727 Must be bigger than 6. Normally should not be changed. */
1728 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
1729 /* [RW 2] CDU byte swapping mode configuration for master read requests */
1730 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
1731 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
1732 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
1733 /* [R 1] PSWRD internal memories initialization is done */
1734 #define PXP2_REG_RD_INIT_DONE 0x120370
1735 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1736 allocated for vq10 */
1737 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
1738 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1739 allocated for vq11 */
1740 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
1741 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1742 allocated for vq17 */
1743 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
1744 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1745 allocated for vq18 */
1746 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
1747 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1748 allocated for vq19 */
1749 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
1750 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1751 allocated for vq22 */
1752 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
1753 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1754 allocated for vq6 */
1755 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
1756 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1757 allocated for vq9 */
1758 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
1759 /* [RW 2] PBF byte swapping mode configuration for master read requests */
1760 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
1761 /* [R 1] Debug only: Indication if delivery ports are idle */
1762 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
1763 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
1764 /* [RW 2] QM byte swapping mode configuration for master read requests */
1765 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
1766 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
1767 #define PXP2_REG_RD_SR_CNT 0x120414
1768 /* [RW 2] SRC byte swapping mode configuration for master read requests */
1769 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
1770 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
1771 be bigger than 1. Normally should not be changed. */
1772 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
1773 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
1774 #define PXP2_REG_RD_START_INIT 0x12036c
1775 /* [RW 2] TM byte swapping mode configuration for master read requests */
1776 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
1777 /* [RW 10] Bandwidth addition to VQ0 write requests */
1778 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
1779 /* [RW 10] Bandwidth addition to VQ12 read requests */
1780 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
1781 /* [RW 10] Bandwidth addition to VQ13 read requests */
1782 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
1783 /* [RW 10] Bandwidth addition to VQ14 read requests */
1784 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
1785 /* [RW 10] Bandwidth addition to VQ15 read requests */
1786 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
1787 /* [RW 10] Bandwidth addition to VQ16 read requests */
1788 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
1789 /* [RW 10] Bandwidth addition to VQ17 read requests */
1790 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
1791 /* [RW 10] Bandwidth addition to VQ18 read requests */
1792 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
1793 /* [RW 10] Bandwidth addition to VQ19 read requests */
1794 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
1795 /* [RW 10] Bandwidth addition to VQ20 read requests */
1796 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
1797 /* [RW 10] Bandwidth addition to VQ22 read requests */
1798 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
1799 /* [RW 10] Bandwidth addition to VQ23 read requests */
1800 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
1801 /* [RW 10] Bandwidth addition to VQ24 read requests */
1802 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
1803 /* [RW 10] Bandwidth addition to VQ25 read requests */
1804 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
1805 /* [RW 10] Bandwidth addition to VQ26 read requests */
1806 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
1807 /* [RW 10] Bandwidth addition to VQ27 read requests */
1808 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
1809 /* [RW 10] Bandwidth addition to VQ4 read requests */
1810 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
1811 /* [RW 10] Bandwidth addition to VQ5 read requests */
1812 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
1813 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
1814 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
1815 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
1816 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
1817 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
1818 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
1819 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
1820 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
1821 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
1822 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
1823 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
1824 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
1825 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
1826 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
1827 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
1828 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
1829 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
1830 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
1831 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
1832 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
1833 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
1834 #define PXP2_REG_RQ_BW_RD_L22 0x120300
1835 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
1836 #define PXP2_REG_RQ_BW_RD_L23 0x120304
1837 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
1838 #define PXP2_REG_RQ_BW_RD_L24 0x120308
1839 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
1840 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
1841 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
1842 #define PXP2_REG_RQ_BW_RD_L26 0x120310
1843 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
1844 #define PXP2_REG_RQ_BW_RD_L27 0x120314
1845 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
1846 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
1847 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
1848 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
1849 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
1850 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
1851 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
1852 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
1853 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
1854 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
1855 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
1856 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
1857 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
1858 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
1859 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
1860 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
1861 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
1862 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
1863 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
1864 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
1865 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
1866 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
1867 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
1868 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
1869 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
1870 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
1871 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
1872 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
1873 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
1874 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
1875 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
1876 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
1877 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
1878 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
1879 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
1880 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
1881 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
1882 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
1883 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
1884 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
1885 /* [RW 10] Bandwidth addition to VQ29 write requests */
1886 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
1887 /* [RW 10] Bandwidth addition to VQ30 write requests */
1888 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
1889 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
1890 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
1891 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
1892 #define PXP2_REG_RQ_BW_WR_L30 0x120320
1893 /* [RW 7] Bandwidth upper bound for VQ29 */
1894 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
1895 /* [RW 7] Bandwidth upper bound for VQ30 */
1896 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
1897 /* [RW 2] Endian mode for cdu */
1898 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
1899 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
1901 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
1902 /* [R 1] 1' indicates that the requester has finished its internal
1904 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
1905 /* [RW 2] Endian mode for debug */
1906 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
1907 /* [RW 1] When '1'; requests will enter input buffers but wont get out
1909 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
1910 /* [RW 2] Endian mode for hc */
1911 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
1912 /* [WB 53] Onchip address table */
1913 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
1914 /* [RW 2] Endian mode for qm */
1915 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
1916 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
1918 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
1919 /* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */
1920 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
1921 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
1922 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
1923 #define PXP2_REG_RQ_RD_MBS0 0x120160
1924 /* [RW 2] Endian mode for src */
1925 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
1926 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
1928 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
1929 /* [RW 2] Endian mode for tm */
1930 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
1931 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
1933 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
1934 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
1935 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
1936 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
1937 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
1938 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
1939 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
1940 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
1941 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
1942 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
1943 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
1944 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
1945 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
1946 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
1947 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
1948 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
1949 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
1950 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
1951 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
1952 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
1953 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
1954 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
1955 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
1956 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
1957 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
1958 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
1959 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
1960 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
1961 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
1962 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
1963 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
1964 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
1965 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
1966 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
1967 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
1968 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
1969 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
1970 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
1971 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
1972 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
1973 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
1974 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
1975 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
1976 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
1977 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
1978 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
1979 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
1980 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
1981 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
1982 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
1983 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
1984 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
1985 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
1986 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
1987 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
1988 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
1989 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
1990 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
1991 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
1992 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
1993 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
1994 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
1995 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
1996 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
1997 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
1998 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
1999 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2000 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2001 001:256B; 010: 512B; */
2002 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2003 /* [RW 10] if Number of entries in dmae fifo will be higer than this
2004 threshold then has_payload indication will be asserted; the default value
2005 should be equal to > write MBS size! */
2006 #define PXP2_REG_WR_DMAE_TH 0x120368
2007 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2008 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2009 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2010 this client is waiting for the arbiter. */
2011 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2012 /* [WB 160] Used for initialization of the inbound interrupts memory */
2013 #define PXP_REG_HST_INBOUND_INT 0x103800
2014 /* [RW 32] Interrupt mask register #0 read/write */
2015 #define PXP_REG_PXP_INT_MASK_0 0x103074
2016 #define PXP_REG_PXP_INT_MASK_1 0x103084
2017 /* [R 32] Interrupt register #0 read */
2018 #define PXP_REG_PXP_INT_STS_0 0x103068
2019 #define PXP_REG_PXP_INT_STS_1 0x103078
2020 /* [RC 32] Interrupt register #0 read clear */
2021 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2022 /* [RW 26] Parity mask register #0 read/write */
2023 #define PXP_REG_PXP_PRTY_MASK 0x103094
2024 /* [RW 4] The activity counter initial increment value sent in the load
2026 #define QM_REG_ACTCTRINITVAL_0 0x168040
2027 #define QM_REG_ACTCTRINITVAL_1 0x168044
2028 #define QM_REG_ACTCTRINITVAL_2 0x168048
2029 #define QM_REG_ACTCTRINITVAL_3 0x16804c
2030 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2031 index I represents the physical queue number. The 12 lsbs are ignore and
2032 considered zero so practically there are only 20 bits in this register. */
2033 #define QM_REG_BASEADDR 0x168900
2034 /* [RW 16] The byte credit cost for each task. This value is for both ports */
2035 #define QM_REG_BYTECRDCOST 0x168234
2036 /* [RW 16] The initial byte credit value for both ports. */
2037 #define QM_REG_BYTECRDINITVAL 0x168238
2038 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2039 queue uses port 0 else it uses port 1. */
2040 #define QM_REG_BYTECRDPORT_LSB 0x168228
2041 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2042 queue uses port 0 else it uses port 1. */
2043 #define QM_REG_BYTECRDPORT_MSB 0x168224
2044 /* [RW 16] The byte credit value that if above the QM is considered almost
2046 #define QM_REG_BYTECREDITAFULLTHR 0x168094
2047 /* [RW 4] The initial credit for interface */
2048 #define QM_REG_CMINITCRD_0 0x1680cc
2049 #define QM_REG_CMINITCRD_1 0x1680d0
2050 #define QM_REG_CMINITCRD_2 0x1680d4
2051 #define QM_REG_CMINITCRD_3 0x1680d8
2052 #define QM_REG_CMINITCRD_4 0x1680dc
2053 #define QM_REG_CMINITCRD_5 0x1680e0
2054 #define QM_REG_CMINITCRD_6 0x1680e4
2055 #define QM_REG_CMINITCRD_7 0x1680e8
2056 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2058 #define QM_REG_CMINTEN 0x1680ec
2059 /* [RW 12] A bit vector which indicates which one of the queues are tied to
2061 #define QM_REG_CMINTVOQMASK_0 0x1681f4
2062 #define QM_REG_CMINTVOQMASK_1 0x1681f8
2063 #define QM_REG_CMINTVOQMASK_2 0x1681fc
2064 #define QM_REG_CMINTVOQMASK_3 0x168200
2065 #define QM_REG_CMINTVOQMASK_4 0x168204
2066 #define QM_REG_CMINTVOQMASK_5 0x168208
2067 #define QM_REG_CMINTVOQMASK_6 0x16820c
2068 #define QM_REG_CMINTVOQMASK_7 0x168210
2069 /* [RW 20] The number of connections divided by 16 which dictates the size
2070 of each queue per port 0 */
2071 #define QM_REG_CONNNUM_0 0x168020
2072 /* [R 6] Keep the fill level of the fifo from write client 4 */
2073 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
2074 /* [RW 8] The context regions sent in the CFC load request */
2075 #define QM_REG_CTXREG_0 0x168030
2076 #define QM_REG_CTXREG_1 0x168034
2077 #define QM_REG_CTXREG_2 0x168038
2078 #define QM_REG_CTXREG_3 0x16803c
2079 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2081 #define QM_REG_ENBYPVOQMASK 0x16823c
2082 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2083 physical queue uses the byte credit */
2084 #define QM_REG_ENBYTECRD_LSB 0x168220
2085 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2086 physical queue uses the byte credit */
2087 #define QM_REG_ENBYTECRD_MSB 0x16821c
2088 /* [RW 4] If cleared then the secondary interface will not be served by the
2090 #define QM_REG_ENSEC 0x1680f0
2091 /* [RW 32] A bit vector per each physical queue which selects which function
2092 number to use on PCI access for that queue. */
2093 #define QM_REG_FUNCNUMSEL_LSB 0x168230
2094 /* [RW 32] A bit vector per each physical queue which selects which function
2095 number to use on PCI access for that queue. */
2096 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
2097 /* [RW 32] A mask register to mask the Almost empty signals which will not
2098 be use for the almost empty indication to the HW block */
2099 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
2100 /* [RW 32] A mask register to mask the Almost empty signals which will not
2101 be use for the almost empty indication to the HW block */
2102 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
2103 /* [RW 4] The number of outstanding request to CFC */
2104 #define QM_REG_OUTLDREQ 0x168804
2105 /* [RC 1] A flag to indicate that overflow error occurred in one of the
2107 #define QM_REG_OVFERROR 0x16805c
2108 /* [RC 6] the Q were the qverflow occurs */
2109 #define QM_REG_OVFQNUM 0x168058
2110 /* [R 32] Pause state for physical queues 31-0 */
2111 #define QM_REG_PAUSESTATE0 0x168410
2112 /* [R 32] Pause state for physical queues 64-32 */
2113 #define QM_REG_PAUSESTATE1 0x168414
2114 /* [RW 2] The PCI attributes field used in the PCI request. */
2115 #define QM_REG_PCIREQAT 0x168054
2116 /* [R 16] The byte credit of port 0 */
2117 #define QM_REG_PORT0BYTECRD 0x168300
2118 /* [R 16] The byte credit of port 1 */
2119 #define QM_REG_PORT1BYTECRD 0x168304
2120 /* [WB 54] Pointer Table Memory; The mapping is as follow: ptrtbl[53:30]
2121 read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0;
2122 ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2123 #define QM_REG_PTRTBL 0x168a00
2124 /* [RW 2] Interrupt mask register #0 read/write */
2125 #define QM_REG_QM_INT_MASK 0x168444
2126 /* [R 2] Interrupt register #0 read */
2127 #define QM_REG_QM_INT_STS 0x168438
2128 /* [RW 9] Parity mask register #0 read/write */
2129 #define QM_REG_QM_PRTY_MASK 0x168454
2130 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2131 #define QM_REG_QSTATUS_HIGH 0x16802c
2132 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2133 #define QM_REG_QSTATUS_LOW 0x168028
2134 /* [R 24] The number of tasks queued for each queue */
2135 #define QM_REG_QTASKCTR_0 0x168308
2136 /* [RW 4] Queue tied to VOQ */
2137 #define QM_REG_QVOQIDX_0 0x1680f4
2138 #define QM_REG_QVOQIDX_10 0x16811c
2139 #define QM_REG_QVOQIDX_11 0x168120
2140 #define QM_REG_QVOQIDX_12 0x168124
2141 #define QM_REG_QVOQIDX_13 0x168128
2142 #define QM_REG_QVOQIDX_14 0x16812c
2143 #define QM_REG_QVOQIDX_15 0x168130
2144 #define QM_REG_QVOQIDX_16 0x168134
2145 #define QM_REG_QVOQIDX_17 0x168138
2146 #define QM_REG_QVOQIDX_21 0x168148
2147 #define QM_REG_QVOQIDX_25 0x168158
2148 #define QM_REG_QVOQIDX_29 0x168168
2149 #define QM_REG_QVOQIDX_32 0x168174
2150 #define QM_REG_QVOQIDX_33 0x168178
2151 #define QM_REG_QVOQIDX_34 0x16817c
2152 #define QM_REG_QVOQIDX_35 0x168180
2153 #define QM_REG_QVOQIDX_36 0x168184
2154 #define QM_REG_QVOQIDX_37 0x168188
2155 #define QM_REG_QVOQIDX_38 0x16818c
2156 #define QM_REG_QVOQIDX_39 0x168190
2157 #define QM_REG_QVOQIDX_40 0x168194
2158 #define QM_REG_QVOQIDX_41 0x168198
2159 #define QM_REG_QVOQIDX_42 0x16819c
2160 #define QM_REG_QVOQIDX_43 0x1681a0
2161 #define QM_REG_QVOQIDX_44 0x1681a4
2162 #define QM_REG_QVOQIDX_45 0x1681a8
2163 #define QM_REG_QVOQIDX_46 0x1681ac
2164 #define QM_REG_QVOQIDX_47 0x1681b0
2165 #define QM_REG_QVOQIDX_48 0x1681b4
2166 #define QM_REG_QVOQIDX_49 0x1681b8
2167 #define QM_REG_QVOQIDX_5 0x168108
2168 #define QM_REG_QVOQIDX_50 0x1681bc
2169 #define QM_REG_QVOQIDX_51 0x1681c0
2170 #define QM_REG_QVOQIDX_52 0x1681c4
2171 #define QM_REG_QVOQIDX_53 0x1681c8
2172 #define QM_REG_QVOQIDX_54 0x1681cc
2173 #define QM_REG_QVOQIDX_55 0x1681d0
2174 #define QM_REG_QVOQIDX_56 0x1681d4
2175 #define QM_REG_QVOQIDX_57 0x1681d8
2176 #define QM_REG_QVOQIDX_58 0x1681dc
2177 #define QM_REG_QVOQIDX_59 0x1681e0
2178 #define QM_REG_QVOQIDX_50 0x1681bc
2179 #define QM_REG_QVOQIDX_51 0x1681c0
2180 #define QM_REG_QVOQIDX_52 0x1681c4
2181 #define QM_REG_QVOQIDX_53 0x1681c8
2182 #define QM_REG_QVOQIDX_54 0x1681cc
2183 #define QM_REG_QVOQIDX_55 0x1681d0
2184 #define QM_REG_QVOQIDX_56 0x1681d4
2185 #define QM_REG_QVOQIDX_57 0x1681d8
2186 #define QM_REG_QVOQIDX_58 0x1681dc
2187 #define QM_REG_QVOQIDX_59 0x1681e0
2188 #define QM_REG_QVOQIDX_6 0x16810c
2189 #define QM_REG_QVOQIDX_60 0x1681e4
2190 #define QM_REG_QVOQIDX_61 0x1681e8
2191 #define QM_REG_QVOQIDX_62 0x1681ec
2192 #define QM_REG_QVOQIDX_63 0x1681f0
2193 #define QM_REG_QVOQIDX_60 0x1681e4
2194 #define QM_REG_QVOQIDX_61 0x1681e8
2195 #define QM_REG_QVOQIDX_62 0x1681ec
2196 #define QM_REG_QVOQIDX_63 0x1681f0
2197 #define QM_REG_QVOQIDX_7 0x168110
2198 #define QM_REG_QVOQIDX_8 0x168114
2199 #define QM_REG_QVOQIDX_9 0x168118
2200 /* [R 24] Remaining pause timeout for port 0 */
2201 #define QM_REG_REMAINPAUSETM0 0x168418
2202 /* [R 24] Remaining pause timeout for port 1 */
2203 #define QM_REG_REMAINPAUSETM1 0x16841c
2204 /* [RW 1] Initialization bit command */
2205 #define QM_REG_SOFT_RESET 0x168428
2206 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2207 #define QM_REG_TASKCRDCOST_0 0x16809c
2208 #define QM_REG_TASKCRDCOST_1 0x1680a0
2209 #define QM_REG_TASKCRDCOST_10 0x1680c4
2210 #define QM_REG_TASKCRDCOST_11 0x1680c8
2211 #define QM_REG_TASKCRDCOST_2 0x1680a4
2212 #define QM_REG_TASKCRDCOST_4 0x1680ac
2213 #define QM_REG_TASKCRDCOST_5 0x1680b0
2214 /* [R 6] Keep the fill level of the fifo from write client 3 */
2215 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
2216 /* [R 6] Keep the fill level of the fifo from write client 2 */
2217 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
2218 /* [RC 32] Credit update error register */
2219 #define QM_REG_VOQCRDERRREG 0x168408
2220 /* [R 16] The credit value for each VOQ */
2221 #define QM_REG_VOQCREDIT_0 0x1682d0
2222 #define QM_REG_VOQCREDIT_1 0x1682d4
2223 #define QM_REG_VOQCREDIT_10 0x1682f8
2224 #define QM_REG_VOQCREDIT_11 0x1682fc
2225 #define QM_REG_VOQCREDIT_4 0x1682e0
2226 /* [RW 16] The credit value that if above the QM is considered almost full */
2227 #define QM_REG_VOQCREDITAFULLTHR 0x168090
2228 /* [RW 16] The init and maximum credit for each VoQ */
2229 #define QM_REG_VOQINITCREDIT_0 0x168060
2230 #define QM_REG_VOQINITCREDIT_1 0x168064
2231 #define QM_REG_VOQINITCREDIT_10 0x168088
2232 #define QM_REG_VOQINITCREDIT_11 0x16808c
2233 #define QM_REG_VOQINITCREDIT_2 0x168068
2234 #define QM_REG_VOQINITCREDIT_4 0x168070
2235 #define QM_REG_VOQINITCREDIT_5 0x168074
2236 /* [RW 1] The port of which VOQ belongs */
2237 #define QM_REG_VOQPORT_1 0x1682a4
2238 #define QM_REG_VOQPORT_10 0x1682c8
2239 #define QM_REG_VOQPORT_11 0x1682cc
2240 #define QM_REG_VOQPORT_2 0x1682a8
2241 /* [RW 32] The physical queue number associated with each VOQ */
2242 #define QM_REG_VOQQMASK_0_LSB 0x168240
2243 /* [RW 32] The physical queue number associated with each VOQ */
2244 #define QM_REG_VOQQMASK_0_MSB 0x168244
2245 /* [RW 32] The physical queue number associated with each VOQ */
2246 #define QM_REG_VOQQMASK_1_MSB 0x16824c
2247 /* [RW 32] The physical queue number associated with each VOQ */
2248 #define QM_REG_VOQQMASK_2_LSB 0x168250
2249 /* [RW 32] The physical queue number associated with each VOQ */
2250 #define QM_REG_VOQQMASK_2_MSB 0x168254
2251 /* [RW 32] The physical queue number associated with each VOQ */
2252 #define QM_REG_VOQQMASK_3_LSB 0x168258
2253 /* [RW 32] The physical queue number associated with each VOQ */
2254 #define QM_REG_VOQQMASK_4_LSB 0x168260
2255 /* [RW 32] The physical queue number associated with each VOQ */
2256 #define QM_REG_VOQQMASK_4_MSB 0x168264
2257 /* [RW 32] The physical queue number associated with each VOQ */
2258 #define QM_REG_VOQQMASK_5_LSB 0x168268
2259 /* [RW 32] The physical queue number associated with each VOQ */
2260 #define QM_REG_VOQQMASK_5_MSB 0x16826c
2261 /* [RW 32] The physical queue number associated with each VOQ */
2262 #define QM_REG_VOQQMASK_6_LSB 0x168270
2263 /* [RW 32] The physical queue number associated with each VOQ */
2264 #define QM_REG_VOQQMASK_6_MSB 0x168274
2265 /* [RW 32] The physical queue number associated with each VOQ */
2266 #define QM_REG_VOQQMASK_7_LSB 0x168278
2267 /* [RW 32] The physical queue number associated with each VOQ */
2268 #define QM_REG_VOQQMASK_7_MSB 0x16827c
2269 /* [RW 32] The physical queue number associated with each VOQ */
2270 #define QM_REG_VOQQMASK_8_LSB 0x168280
2271 /* [RW 32] The physical queue number associated with each VOQ */
2272 #define QM_REG_VOQQMASK_8_MSB 0x168284
2273 /* [RW 32] The physical queue number associated with each VOQ */
2274 #define QM_REG_VOQQMASK_9_LSB 0x168288
2275 /* [RW 32] Wrr weights */
2276 #define QM_REG_WRRWEIGHTS_0 0x16880c
2277 #define QM_REG_WRRWEIGHTS_1 0x168810
2278 #define QM_REG_WRRWEIGHTS_10 0x168814
2279 #define QM_REG_WRRWEIGHTS_10_SIZE 1
2280 /* [RW 32] Wrr weights */
2281 #define QM_REG_WRRWEIGHTS_11 0x168818
2282 #define QM_REG_WRRWEIGHTS_11_SIZE 1
2283 /* [RW 32] Wrr weights */
2284 #define QM_REG_WRRWEIGHTS_12 0x16881c
2285 #define QM_REG_WRRWEIGHTS_12_SIZE 1
2286 /* [RW 32] Wrr weights */
2287 #define QM_REG_WRRWEIGHTS_13 0x168820
2288 #define QM_REG_WRRWEIGHTS_13_SIZE 1
2289 /* [RW 32] Wrr weights */
2290 #define QM_REG_WRRWEIGHTS_14 0x168824
2291 #define QM_REG_WRRWEIGHTS_14_SIZE 1
2292 /* [RW 32] Wrr weights */
2293 #define QM_REG_WRRWEIGHTS_15 0x168828
2294 #define QM_REG_WRRWEIGHTS_15_SIZE 1
2295 /* [RW 32] Wrr weights */
2296 #define QM_REG_WRRWEIGHTS_10 0x168814
2297 #define QM_REG_WRRWEIGHTS_11 0x168818
2298 #define QM_REG_WRRWEIGHTS_12 0x16881c
2299 #define QM_REG_WRRWEIGHTS_13 0x168820
2300 #define QM_REG_WRRWEIGHTS_14 0x168824
2301 #define QM_REG_WRRWEIGHTS_15 0x168828
2302 #define QM_REG_WRRWEIGHTS_2 0x16882c
2303 #define QM_REG_WRRWEIGHTS_3 0x168830
2304 #define QM_REG_WRRWEIGHTS_4 0x168834
2305 #define QM_REG_WRRWEIGHTS_5 0x168838
2306 #define QM_REG_WRRWEIGHTS_6 0x16883c
2307 #define QM_REG_WRRWEIGHTS_7 0x168840
2308 #define QM_REG_WRRWEIGHTS_8 0x168844
2309 #define QM_REG_WRRWEIGHTS_9 0x168848
2310 /* [R 6] Keep the fill level of the fifo from write client 1 */
2311 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
2312 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2313 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2314 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2315 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2316 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2317 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2318 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2319 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2320 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
2321 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
2322 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
2323 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
2324 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
2325 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
2326 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2327 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
2328 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2329 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2330 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2331 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2332 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2333 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2334 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2335 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2336 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
2337 #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
2338 /* [R 1] debug only: This bit indicates wheter indicates that external
2339 buffer was wrapped (oldest data was thrown); Relevant only when
2340 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
2341 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
2342 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
2343 /* [R 1] debug only: This bit indicates wheter the internal buffer was
2344 wrapped (oldest data was thrown) Relevant only when
2345 ~dbg_registers_debug_target=0 (internal buffer) */
2346 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
2347 #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
2348 /* [RW 32] Wrr weights */
2349 #define QM_REG_WRRWEIGHTS_0 0x16880c
2350 #define QM_REG_WRRWEIGHTS_0_SIZE 1
2351 /* [RW 32] Wrr weights */
2352 #define QM_REG_WRRWEIGHTS_1 0x168810
2353 #define QM_REG_WRRWEIGHTS_1_SIZE 1
2354 /* [RW 32] Wrr weights */
2355 #define QM_REG_WRRWEIGHTS_10 0x168814
2356 #define QM_REG_WRRWEIGHTS_10_SIZE 1
2357 /* [RW 32] Wrr weights */
2358 #define QM_REG_WRRWEIGHTS_11 0x168818
2359 #define QM_REG_WRRWEIGHTS_11_SIZE 1
2360 /* [RW 32] Wrr weights */
2361 #define QM_REG_WRRWEIGHTS_12 0x16881c
2362 #define QM_REG_WRRWEIGHTS_12_SIZE 1
2363 /* [RW 32] Wrr weights */
2364 #define QM_REG_WRRWEIGHTS_13 0x168820
2365 #define QM_REG_WRRWEIGHTS_13_SIZE 1
2366 /* [RW 32] Wrr weights */
2367 #define QM_REG_WRRWEIGHTS_14 0x168824
2368 #define QM_REG_WRRWEIGHTS_14_SIZE 1
2369 /* [RW 32] Wrr weights */
2370 #define QM_REG_WRRWEIGHTS_15 0x168828
2371 #define QM_REG_WRRWEIGHTS_15_SIZE 1
2372 /* [RW 32] Wrr weights */
2373 #define QM_REG_WRRWEIGHTS_2 0x16882c
2374 #define QM_REG_WRRWEIGHTS_2_SIZE 1
2375 /* [RW 32] Wrr weights */
2376 #define QM_REG_WRRWEIGHTS_3 0x168830
2377 #define QM_REG_WRRWEIGHTS_3_SIZE 1
2378 /* [RW 32] Wrr weights */
2379 #define QM_REG_WRRWEIGHTS_4 0x168834
2380 #define QM_REG_WRRWEIGHTS_4_SIZE 1
2381 /* [RW 32] Wrr weights */
2382 #define QM_REG_WRRWEIGHTS_5 0x168838
2383 #define QM_REG_WRRWEIGHTS_5_SIZE 1
2384 /* [RW 32] Wrr weights */
2385 #define QM_REG_WRRWEIGHTS_6 0x16883c
2386 #define QM_REG_WRRWEIGHTS_6_SIZE 1
2387 /* [RW 32] Wrr weights */
2388 #define QM_REG_WRRWEIGHTS_7 0x168840
2389 #define QM_REG_WRRWEIGHTS_7_SIZE 1
2390 /* [RW 32] Wrr weights */
2391 #define QM_REG_WRRWEIGHTS_8 0x168844
2392 #define QM_REG_WRRWEIGHTS_8_SIZE 1
2393 /* [RW 32] Wrr weights */
2394 #define QM_REG_WRRWEIGHTS_9 0x168848
2395 #define QM_REG_WRRWEIGHTS_9_SIZE 1
2396 /* [RW 22] Number of free element in the free list of T2 entries - port 0. */
2397 #define SRC_REG_COUNTFREE0 0x40500
2398 /* [WB 64] First free element in the free list of T2 entries - port 0. */
2399 #define SRC_REG_FIRSTFREE0 0x40510
2400 #define SRC_REG_KEYRSS0_0 0x40408
2401 #define SRC_REG_KEYRSS1_9 0x40454
2402 /* [WB 64] Last free element in the free list of T2 entries - port 0. */
2403 #define SRC_REG_LASTFREE0 0x40530
2404 /* [RW 5] The number of hash bits used for the search (h); Values can be 8
2406 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
2407 /* [RW 1] Reset internal state machines. */
2408 #define SRC_REG_SOFT_RST 0x4049c
2409 /* [R 1] Interrupt register #0 read */
2410 #define SRC_REG_SRC_INT_STS 0x404ac
2411 /* [RW 3] Parity mask register #0 read/write */
2412 #define SRC_REG_SRC_PRTY_MASK 0x404c8
2413 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
2414 #define TCM_REG_CAM_OCCUP 0x5017c
2415 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
2416 disregarded; valid output is deasserted; all other signals are treated as
2417 usual; if 1 - normal activity. */
2418 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
2419 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
2420 are disregarded; all other signals are treated as usual; if 1 - normal
2422 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
2423 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
2424 disregarded; valid output is deasserted; all other signals are treated as
2425 usual; if 1 - normal activity. */
2426 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
2427 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
2428 input is disregarded; all other signals are treated as usual; if 1 -
2430 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
2431 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
2432 the initial credit value; read returns the current value of the credit
2433 counter. Must be initialized to 1 at start-up. */
2434 #define TCM_REG_CFC_INIT_CRD 0x50204
2435 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
2436 weight 8 (the most prioritised); 1 stands for weight 1(least
2437 prioritised); 2 stands for weight 2; tc. */
2438 #define TCM_REG_CP_WEIGHT 0x500c0
2439 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
2440 disregarded; acknowledge output is deasserted; all other signals are
2441 treated as usual; if 1 - normal activity. */
2442 #define TCM_REG_CSEM_IFEN 0x5002c
2443 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
2445 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
2446 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
2447 #define TCM_REG_ERR_EVNT_ID 0x500a0
2448 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
2449 #define TCM_REG_ERR_TCM_HDR 0x5009c
2450 /* [RW 8] The Event ID for Timers expiration. */
2451 #define TCM_REG_EXPR_EVNT_ID 0x500a4
2452 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
2453 writes the initial credit value; read returns the current value of the
2454 credit counter. Must be initialized to 64 at start-up. */
2455 #define TCM_REG_FIC0_INIT_CRD 0x5020c
2456 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
2457 writes the initial credit value; read returns the current value of the
2458 credit counter. Must be initialized to 64 at start-up. */
2459 #define TCM_REG_FIC1_INIT_CRD 0x50210
2460 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
2461 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
2462 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
2463 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
2464 #define TCM_REG_GR_ARB_TYPE 0x50114
2465 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
2466 highest priority is 3. It is supposed that the Store channel is the
2467 compliment of the other 3 groups. */
2468 #define TCM_REG_GR_LD0_PR 0x5011c
2469 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
2470 highest priority is 3. It is supposed that the Store channel is the
2471 compliment of the other 3 groups. */
2472 #define TCM_REG_GR_LD1_PR 0x50120
2473 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
2474 sent to STORM; for a specific connection type. The double REG-pairs are
2475 used to align to STORM context row size of 128 bits. The offset of these
2476 data in the STORM context is always 0. Index _i stands for the connection
2477 type (one of 16). */
2478 #define TCM_REG_N_SM_CTX_LD_0 0x50050
2479 #define TCM_REG_N_SM_CTX_LD_1 0x50054
2480 #define TCM_REG_N_SM_CTX_LD_10 0x50078
2481 #define TCM_REG_N_SM_CTX_LD_11 0x5007c
2482 #define TCM_REG_N_SM_CTX_LD_12 0x50080
2483 #define TCM_REG_N_SM_CTX_LD_13 0x50084
2484 #define TCM_REG_N_SM_CTX_LD_14 0x50088
2485 #define TCM_REG_N_SM_CTX_LD_15 0x5008c
2486 #define TCM_REG_N_SM_CTX_LD_2 0x50058
2487 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
2488 #define TCM_REG_N_SM_CTX_LD_4 0x50060
2489 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
2490 acknowledge output is deasserted; all other signals are treated as usual;
2491 if 1 - normal activity. */
2492 #define TCM_REG_PBF_IFEN 0x50024
2493 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
2495 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
2496 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
2497 weight 8 (the most prioritised); 1 stands for weight 1(least
2498 prioritised); 2 stands for weight 2; tc. */
2499 #define TCM_REG_PBF_WEIGHT 0x500b4
2500 /* [RW 6] The physical queue number 0 per port index. */
2501 #define TCM_REG_PHYS_QNUM0_0 0x500e0
2502 #define TCM_REG_PHYS_QNUM0_1 0x500e4
2503 /* [RW 6] The physical queue number 1 per port index. */
2504 #define TCM_REG_PHYS_QNUM1_0 0x500e8
2505 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
2506 acknowledge output is deasserted; all other signals are treated as usual;
2507 if 1 - normal activity. */
2508 #define TCM_REG_PRS_IFEN 0x50020
2509 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
2511 #define TCM_REG_PRS_LENGTH_MIS 0x50168
2512 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
2513 weight 8 (the most prioritised); 1 stands for weight 1(least
2514 prioritised); 2 stands for weight 2; tc. */
2515 #define TCM_REG_PRS_WEIGHT 0x500b0
2516 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
2517 #define TCM_REG_STOP_EVNT_ID 0x500a8
2518 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
2520 #define TCM_REG_STORM_LENGTH_MIS 0x50160
2521 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
2522 disregarded; acknowledge output is deasserted; all other signals are
2523 treated as usual; if 1 - normal activity. */
2524 #define TCM_REG_STORM_TCM_IFEN 0x50010
2525 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
2526 acknowledge output is deasserted; all other signals are treated as usual;
2527 if 1 - normal activity. */
2528 #define TCM_REG_TCM_CFC_IFEN 0x50040
2529 /* [RW 11] Interrupt mask register #0 read/write */
2530 #define TCM_REG_TCM_INT_MASK 0x501dc
2531 /* [R 11] Interrupt register #0 read */
2532 #define TCM_REG_TCM_INT_STS 0x501d0
2533 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
2534 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2535 Is used to determine the number of the AG context REG-pairs written back;
2536 when the input message Reg1WbFlg isn't set. */
2537 #define TCM_REG_TCM_REG0_SZ 0x500d8
2538 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
2539 disregarded; valid is deasserted; all other signals are treated as usual;
2540 if 1 - normal activity. */
2541 #define TCM_REG_TCM_STORM0_IFEN 0x50004
2542 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
2543 disregarded; valid is deasserted; all other signals are treated as usual;
2544 if 1 - normal activity. */
2545 #define TCM_REG_TCM_STORM1_IFEN 0x50008
2546 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
2547 disregarded; valid is deasserted; all other signals are treated as usual;
2548 if 1 - normal activity. */
2549 #define TCM_REG_TCM_TQM_IFEN 0x5000c
2550 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
2551 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
2552 /* [RW 28] The CM header for Timers expiration command. */
2553 #define TCM_REG_TM_TCM_HDR 0x50098
2554 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
2555 disregarded; acknowledge output is deasserted; all other signals are
2556 treated as usual; if 1 - normal activity. */
2557 #define TCM_REG_TM_TCM_IFEN 0x5001c
2558 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
2559 the initial credit value; read returns the current value of the credit
2560 counter. Must be initialized to 32 at start-up. */
2561 #define TCM_REG_TQM_INIT_CRD 0x5021c
2562 /* [RW 28] The CM header value for QM request (primary). */
2563 #define TCM_REG_TQM_TCM_HDR_P 0x50090
2564 /* [RW 28] The CM header value for QM request (secondary). */
2565 #define TCM_REG_TQM_TCM_HDR_S 0x50094
2566 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
2567 acknowledge output is deasserted; all other signals are treated as usual;
2568 if 1 - normal activity. */
2569 #define TCM_REG_TQM_TCM_IFEN 0x50014
2570 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
2571 acknowledge output is deasserted; all other signals are treated as usual;
2572 if 1 - normal activity. */
2573 #define TCM_REG_TSDM_IFEN 0x50018
2574 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
2576 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
2577 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
2578 weight 8 (the most prioritised); 1 stands for weight 1(least
2579 prioritised); 2 stands for weight 2; tc. */
2580 #define TCM_REG_TSDM_WEIGHT 0x500c4
2581 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
2582 disregarded; acknowledge output is deasserted; all other signals are
2583 treated as usual; if 1 - normal activity. */
2584 #define TCM_REG_USEM_IFEN 0x50028
2585 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
2587 #define TCM_REG_USEM_LENGTH_MIS 0x50170
2588 /* [RW 21] Indirect access to the descriptor table of the XX protection
2589 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
2590 pointer; 20:16] - next pointer. */
2591 #define TCM_REG_XX_DESCR_TABLE 0x50280
2592 /* [R 6] Use to read the value of XX protection Free counter. */
2593 #define TCM_REG_XX_FREE 0x50178
2594 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
2595 of the Input Stage XX protection buffer by the XX protection pending
2596 messages. Max credit available - 127.Write writes the initial credit
2597 value; read returns the current value of the credit counter. Must be
2598 initialized to 19 at start-up. */
2599 #define TCM_REG_XX_INIT_CRD 0x50220
2600 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
2602 #define TCM_REG_XX_MAX_LL_SZ 0x50044
2603 /* [RW 6] The maximum number of pending messages; which may be stored in XX
2604 protection. ~tcm_registers_xx_free.xx_free is read on read. */
2605 #define TCM_REG_XX_MSG_NUM 0x50224
2606 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
2607 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
2608 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
2609 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
2611 #define TCM_REG_XX_TABLE 0x50240
2612 /* [RW 4] Load value for for cfc ac credit cnt. */
2613 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
2614 /* [RW 4] Load value for cfc cld credit cnt. */
2615 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
2616 /* [RW 8] Client0 context region. */
2617 #define TM_REG_CL0_CONT_REGION 0x164030
2618 /* [RW 8] Client1 context region. */
2619 #define TM_REG_CL1_CONT_REGION 0x164034
2620 /* [RW 8] Client2 context region. */
2621 #define TM_REG_CL2_CONT_REGION 0x164038
2622 /* [RW 2] Client in High priority client number. */
2623 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
2624 /* [RW 4] Load value for clout0 cred cnt. */
2625 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
2626 /* [RW 4] Load value for clout1 cred cnt. */
2627 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
2628 /* [RW 4] Load value for clout2 cred cnt. */
2629 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
2630 /* [RW 1] Enable client0 input. */
2631 #define TM_REG_EN_CL0_INPUT 0x164008
2632 /* [RW 1] Enable client1 input. */
2633 #define TM_REG_EN_CL1_INPUT 0x16400c
2634 /* [RW 1] Enable client2 input. */
2635 #define TM_REG_EN_CL2_INPUT 0x164010
2636 /* [RW 1] Enable real time counter. */
2637 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
2638 /* [RW 1] Enable for Timers state machines. */
2639 #define TM_REG_EN_TIMERS 0x164000
2640 /* [RW 4] Load value for expiration credit cnt. CFC max number of
2641 outstanding load requests for timers (expiration) context loading. */
2642 #define TM_REG_EXP_CRDCNT_VAL 0x164238
2643 /* [RW 18] Linear0 Max active cid. */
2644 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
2645 /* [WB 64] Linear0 phy address. */
2646 #define TM_REG_LIN0_PHY_ADDR 0x164270
2647 /* [RW 24] Linear0 array scan timeout. */
2648 #define TM_REG_LIN0_SCAN_TIME 0x16403c
2649 /* [WB 64] Linear1 phy address. */
2650 #define TM_REG_LIN1_PHY_ADDR 0x164280
2651 /* [RW 6] Linear timer set_clear fifo threshold. */
2652 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
2653 /* [RW 2] Load value for pci arbiter credit cnt. */
2654 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
2655 /* [RW 1] Timer software reset - active high. */
2656 #define TM_REG_TIMER_SOFT_RST 0x164004
2657 /* [RW 20] The amount of hardware cycles for each timer tick. */
2658 #define TM_REG_TIMER_TICK_SIZE 0x16401c
2659 /* [RW 8] Timers Context region. */
2660 #define TM_REG_TM_CONTEXT_REGION 0x164044
2661 /* [RW 1] Interrupt mask register #0 read/write */
2662 #define TM_REG_TM_INT_MASK 0x1640fc
2663 /* [R 1] Interrupt register #0 read */
2664 #define TM_REG_TM_INT_STS 0x1640f0
2665 /* [RW 8] The event id for aggregated interrupt 0 */
2666 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
2667 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
2668 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
2669 /* [RW 16] The maximum value of the competion counter #0 */
2670 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
2671 /* [RW 16] The maximum value of the competion counter #1 */
2672 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
2673 /* [RW 16] The maximum value of the competion counter #2 */
2674 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
2675 /* [RW 16] The maximum value of the competion counter #3 */
2676 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
2677 /* [RW 13] The start address in the internal RAM for the completion
2679 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
2680 #define TSDM_REG_ENABLE_IN1 0x42238
2681 #define TSDM_REG_ENABLE_IN2 0x4223c
2682 #define TSDM_REG_ENABLE_OUT1 0x42240
2683 #define TSDM_REG_ENABLE_OUT2 0x42244
2684 /* [RW 4] The initial number of messages that can be sent to the pxp control
2685 interface without receiving any ACK. */
2686 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
2687 /* [ST 32] The number of ACK after placement messages received */
2688 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
2689 /* [ST 32] The number of packet end messages received from the parser */
2690 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
2691 /* [ST 32] The number of requests received from the pxp async if */
2692 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
2693 /* [ST 32] The number of commands received in queue 0 */
2694 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
2695 /* [ST 32] The number of commands received in queue 10 */
2696 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
2697 /* [ST 32] The number of commands received in queue 11 */
2698 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
2699 /* [ST 32] The number of commands received in queue 1 */
2700 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
2701 /* [ST 32] The number of commands received in queue 3 */
2702 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
2703 /* [ST 32] The number of commands received in queue 4 */
2704 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
2705 /* [ST 32] The number of commands received in queue 5 */
2706 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
2707 /* [ST 32] The number of commands received in queue 6 */
2708 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
2709 /* [ST 32] The number of commands received in queue 7 */
2710 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
2711 /* [ST 32] The number of commands received in queue 8 */
2712 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
2713 /* [ST 32] The number of commands received in queue 9 */
2714 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
2715 /* [RW 13] The start address in the internal RAM for the packet end message */
2716 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
2717 /* [RW 13] The start address in the internal RAM for queue counters */
2718 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
2719 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
2720 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
2721 /* [R 1] parser fifo empty in sdm_sync block */
2722 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
2723 /* [R 1] parser serial fifo empty in sdm_sync block */
2724 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
2725 /* [RW 32] Tick for timer counter. Applicable only when
2726 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
2727 #define TSDM_REG_TIMER_TICK 0x42000
2728 /* [RW 32] Interrupt mask register #0 read/write */
2729 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
2730 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
2731 /* [RW 11] Parity mask register #0 read/write */
2732 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
2733 /* [RW 5] The number of time_slots in the arbitration cycle */
2734 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
2735 /* [RW 3] The source that is associated with arbitration element 0. Source
2736 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2737 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
2738 #define TSEM_REG_ARB_ELEMENT0 0x180020
2739 /* [RW 3] The source that is associated with arbitration element 1. Source
2740 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2741 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2742 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
2743 #define TSEM_REG_ARB_ELEMENT1 0x180024
2744 /* [RW 3] The source that is associated with arbitration element 2. Source
2745 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2746 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2747 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2748 and ~tsem_registers_arb_element1.arb_element1 */
2749 #define TSEM_REG_ARB_ELEMENT2 0x180028
2750 /* [RW 3] The source that is associated with arbitration element 3. Source
2751 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2752 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
2753 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
2754 ~tsem_registers_arb_element1.arb_element1 and
2755 ~tsem_registers_arb_element2.arb_element2 */
2756 #define TSEM_REG_ARB_ELEMENT3 0x18002c
2757 /* [RW 3] The source that is associated with arbitration element 4. Source
2758 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2759 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2760 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2761 and ~tsem_registers_arb_element1.arb_element1 and
2762 ~tsem_registers_arb_element2.arb_element2 and
2763 ~tsem_registers_arb_element3.arb_element3 */
2764 #define TSEM_REG_ARB_ELEMENT4 0x180030
2765 #define TSEM_REG_ENABLE_IN 0x1800a4
2766 #define TSEM_REG_ENABLE_OUT 0x1800a8
2767 /* [RW 32] This address space contains all registers and memories that are
2768 placed in SEM_FAST block. The SEM_FAST registers are described in
2769 appendix B. In order to access the SEM_FAST registers the base address
2770 TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each
2771 SEM_FAST register offset. */
2772 #define TSEM_REG_FAST_MEMORY 0x1a0000
2773 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
2775 #define TSEM_REG_FIC0_DISABLE 0x180224
2776 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
2778 #define TSEM_REG_FIC1_DISABLE 0x180234
2779 /* [RW 15] Interrupt table Read and write access to it is not possible in
2780 the middle of the work */
2781 #define TSEM_REG_INT_TABLE 0x180400
2782 /* [ST 24] Statistics register. The number of messages that entered through
2784 #define TSEM_REG_MSG_NUM_FIC0 0x180000
2785 /* [ST 24] Statistics register. The number of messages that entered through
2787 #define TSEM_REG_MSG_NUM_FIC1 0x180004
2788 /* [ST 24] Statistics register. The number of messages that were sent to
2790 #define TSEM_REG_MSG_NUM_FOC0 0x180008
2791 /* [ST 24] Statistics register. The number of messages that were sent to
2793 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
2794 /* [ST 24] Statistics register. The number of messages that were sent to
2796 #define TSEM_REG_MSG_NUM_FOC2 0x180010
2797 /* [ST 24] Statistics register. The number of messages that were sent to
2799 #define TSEM_REG_MSG_NUM_FOC3 0x180014
2800 /* [RW 1] Disables input messages from the passive buffer May be updated
2801 during run_time by the microcode */
2802 #define TSEM_REG_PAS_DISABLE 0x18024c
2803 /* [WB 128] Debug only. Passive buffer memory */
2804 #define TSEM_REG_PASSIVE_BUFFER 0x181000
2805 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
2806 #define TSEM_REG_PRAM 0x1c0000
2807 /* [R 8] Valid sleeping threads indication have bit per thread */
2808 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
2809 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
2810 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
2811 /* [RW 8] List of free threads . There is a bit per thread. */
2812 #define TSEM_REG_THREADS_LIST 0x1802e4
2813 /* [RW 3] The arbitration scheme of time_slot 0 */
2814 #define TSEM_REG_TS_0_AS 0x180038
2815 /* [RW 3] The arbitration scheme of time_slot 10 */
2816 #define TSEM_REG_TS_10_AS 0x180060
2817 /* [RW 3] The arbitration scheme of time_slot 11 */
2818 #define TSEM_REG_TS_11_AS 0x180064
2819 /* [RW 3] The arbitration scheme of time_slot 12 */
2820 #define TSEM_REG_TS_12_AS 0x180068
2821 /* [RW 3] The arbitration scheme of time_slot 13 */
2822 #define TSEM_REG_TS_13_AS 0x18006c
2823 /* [RW 3] The arbitration scheme of time_slot 14 */
2824 #define TSEM_REG_TS_14_AS 0x180070
2825 /* [RW 3] The arbitration scheme of time_slot 15 */
2826 #define TSEM_REG_TS_15_AS 0x180074
2827 /* [RW 3] The arbitration scheme of time_slot 16 */
2828 #define TSEM_REG_TS_16_AS 0x180078
2829 /* [RW 3] The arbitration scheme of time_slot 17 */
2830 #define TSEM_REG_TS_17_AS 0x18007c
2831 /* [RW 3] The arbitration scheme of time_slot 18 */
2832 #define TSEM_REG_TS_18_AS 0x180080
2833 /* [RW 3] The arbitration scheme of time_slot 1 */
2834 #define TSEM_REG_TS_1_AS 0x18003c
2835 /* [RW 3] The arbitration scheme of time_slot 2 */
2836 #define TSEM_REG_TS_2_AS 0x180040
2837 /* [RW 3] The arbitration scheme of time_slot 3 */
2838 #define TSEM_REG_TS_3_AS 0x180044
2839 /* [RW 3] The arbitration scheme of time_slot 4 */
2840 #define TSEM_REG_TS_4_AS 0x180048
2841 /* [RW 3] The arbitration scheme of time_slot 5 */
2842 #define TSEM_REG_TS_5_AS 0x18004c
2843 /* [RW 3] The arbitration scheme of time_slot 6 */
2844 #define TSEM_REG_TS_6_AS 0x180050
2845 /* [RW 3] The arbitration scheme of time_slot 7 */
2846 #define TSEM_REG_TS_7_AS 0x180054
2847 /* [RW 3] The arbitration scheme of time_slot 8 */
2848 #define TSEM_REG_TS_8_AS 0x180058
2849 /* [RW 3] The arbitration scheme of time_slot 9 */
2850 #define TSEM_REG_TS_9_AS 0x18005c
2851 /* [RW 32] Interrupt mask register #0 read/write */
2852 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
2853 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
2854 /* [RW 32] Parity mask register #0 read/write */
2855 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
2856 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
2857 /* [R 5] Used to read the XX protection CAM occupancy counter. */
2858 #define UCM_REG_CAM_OCCUP 0xe0170
2859 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
2860 disregarded; valid output is deasserted; all other signals are treated as
2861 usual; if 1 - normal activity. */
2862 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
2863 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
2864 are disregarded; all other signals are treated as usual; if 1 - normal
2866 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
2867 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
2868 disregarded; valid output is deasserted; all other signals are treated as
2869 usual; if 1 - normal activity. */
2870 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
2871 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
2872 input is disregarded; all other signals are treated as usual; if 1 -
2874 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
2875 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
2876 the initial credit value; read returns the current value of the credit
2877 counter. Must be initialized to 1 at start-up. */
2878 #define UCM_REG_CFC_INIT_CRD 0xe0204
2879 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
2880 weight 8 (the most prioritised); 1 stands for weight 1(least
2881 prioritised); 2 stands for weight 2; tc. */
2882 #define UCM_REG_CP_WEIGHT 0xe00c4
2883 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
2884 disregarded; acknowledge output is deasserted; all other signals are
2885 treated as usual; if 1 - normal activity. */
2886 #define UCM_REG_CSEM_IFEN 0xe0028
2887 /* [RC 1] Set when the message length mismatch (relative to last indication)
2888 at the csem interface is detected. */
2889 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
2890 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
2891 weight 8 (the most prioritised); 1 stands for weight 1(least
2892 prioritised); 2 stands for weight 2; tc. */
2893 #define UCM_REG_CSEM_WEIGHT 0xe00b8
2894 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
2895 disregarded; acknowledge output is deasserted; all other signals are
2896 treated as usual; if 1 - normal activity. */
2897 #define UCM_REG_DORQ_IFEN 0xe0030
2898 /* [RC 1] Set when the message length mismatch (relative to last indication)
2899 at the dorq interface is detected. */
2900 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
2901 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
2902 #define UCM_REG_ERR_EVNT_ID 0xe00a4
2903 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
2904 #define UCM_REG_ERR_UCM_HDR 0xe00a0
2905 /* [RW 8] The Event ID for Timers expiration. */
2906 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
2907 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
2908 writes the initial credit value; read returns the current value of the
2909 credit counter. Must be initialized to 64 at start-up. */
2910 #define UCM_REG_FIC0_INIT_CRD 0xe020c
2911 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
2912 writes the initial credit value; read returns the current value of the
2913 credit counter. Must be initialized to 64 at start-up. */
2914 #define UCM_REG_FIC1_INIT_CRD 0xe0210
2915 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
2916 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
2917 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
2918 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
2919 #define UCM_REG_GR_ARB_TYPE 0xe0144
2920 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
2921 highest priority is 3. It is supposed that the Store channel group is
2922 compliment to the others. */
2923 #define UCM_REG_GR_LD0_PR 0xe014c
2924 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
2925 highest priority is 3. It is supposed that the Store channel group is
2926 compliment to the others. */
2927 #define UCM_REG_GR_LD1_PR 0xe0150
2928 /* [RW 2] The queue index for invalidate counter flag decision. */
2929 #define UCM_REG_INV_CFLG_Q 0xe00e4
2930 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
2931 sent to STORM; for a specific connection type. the double REG-pairs are
2932 used in order to align to STORM context row size of 128 bits. The offset
2933 of these data in the STORM context is always 0. Index _i stands for the
2934 connection type (one of 16). */
2935 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
2936 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
2937 #define UCM_REG_N_SM_CTX_LD_10 0xe007c
2938 #define UCM_REG_N_SM_CTX_LD_11 0xe0080
2939 #define UCM_REG_N_SM_CTX_LD_12 0xe0084
2940 #define UCM_REG_N_SM_CTX_LD_13 0xe0088
2941 #define UCM_REG_N_SM_CTX_LD_14 0xe008c
2942 #define UCM_REG_N_SM_CTX_LD_15 0xe0090
2943 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
2944 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
2945 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
2946 /* [RW 6] The physical queue number 0 per port index (CID[23]) */
2947 #define UCM_REG_PHYS_QNUM0_0 0xe0110
2948 #define UCM_REG_PHYS_QNUM0_1 0xe0114
2949 /* [RW 6] The physical queue number 1 per port index (CID[23]) */
2950 #define UCM_REG_PHYS_QNUM1_0 0xe0118
2951 #define UCM_REG_PHYS_QNUM1_1 0xe011c
2952 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
2953 #define UCM_REG_STOP_EVNT_ID 0xe00ac
2954 /* [RC 1] Set when the message length mismatch (relative to last indication)
2955 at the STORM interface is detected. */
2956 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
2957 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
2958 disregarded; acknowledge output is deasserted; all other signals are
2959 treated as usual; if 1 - normal activity. */
2960 #define UCM_REG_STORM_UCM_IFEN 0xe0010
2961 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
2962 writes the initial credit value; read returns the current value of the
2963 credit counter. Must be initialized to 4 at start-up. */
2964 #define UCM_REG_TM_INIT_CRD 0xe021c
2965 /* [RW 28] The CM header for Timers expiration command. */
2966 #define UCM_REG_TM_UCM_HDR 0xe009c
2967 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
2968 disregarded; acknowledge output is deasserted; all other signals are
2969 treated as usual; if 1 - normal activity. */
2970 #define UCM_REG_TM_UCM_IFEN 0xe001c
2971 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
2972 disregarded; acknowledge output is deasserted; all other signals are
2973 treated as usual; if 1 - normal activity. */
2974 #define UCM_REG_TSEM_IFEN 0xe0024
2975 /* [RC 1] Set when the message length mismatch (relative to last indication)
2976 at the tsem interface is detected. */
2977 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
2978 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
2979 weight 8 (the most prioritised); 1 stands for weight 1(least
2980 prioritised); 2 stands for weight 2; tc. */
2981 #define UCM_REG_TSEM_WEIGHT 0xe00b4
2982 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
2983 acknowledge output is deasserted; all other signals are treated as usual;
2984 if 1 - normal activity. */
2985 #define UCM_REG_UCM_CFC_IFEN 0xe0044
2986 /* [RW 11] Interrupt mask register #0 read/write */
2987 #define UCM_REG_UCM_INT_MASK 0xe01d4
2988 /* [R 11] Interrupt register #0 read */
2989 #define UCM_REG_UCM_INT_STS 0xe01c8
2990 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
2991 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2992 Is used to determine the number of the AG context REG-pairs written back;
2993 when the Reg1WbFlg isn't set. */
2994 #define UCM_REG_UCM_REG0_SZ 0xe00dc
2995 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
2996 disregarded; valid is deasserted; all other signals are treated as usual;
2997 if 1 - normal activity. */
2998 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
2999 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3000 disregarded; valid is deasserted; all other signals are treated as usual;
3001 if 1 - normal activity. */
3002 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
3003 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3004 disregarded; acknowledge output is deasserted; all other signals are
3005 treated as usual; if 1 - normal activity. */
3006 #define UCM_REG_UCM_TM_IFEN 0xe0020
3007 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3008 disregarded; valid is deasserted; all other signals are treated as usual;
3009 if 1 - normal activity. */
3010 #define UCM_REG_UCM_UQM_IFEN 0xe000c
3011 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3012 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
3013 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3014 the initial credit value; read returns the current value of the credit
3015 counter. Must be initialized to 32 at start-up. */
3016 #define UCM_REG_UQM_INIT_CRD 0xe0220
3017 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3018 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3019 prioritised); 2 stands for weight 2; tc. */
3020 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
3021 /* [RW 28] The CM header value for QM request (primary). */
3022 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
3023 /* [RW 28] The CM header value for QM request (secondary). */
3024 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
3025 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3026 acknowledge output is deasserted; all other signals are treated as usual;
3027 if 1 - normal activity. */
3028 #define UCM_REG_UQM_UCM_IFEN 0xe0014
3029 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3030 acknowledge output is deasserted; all other signals are treated as usual;
3031 if 1 - normal activity. */
3032 #define UCM_REG_USDM_IFEN 0xe0018
3033 /* [RC 1] Set when the message length mismatch (relative to last indication)
3034 at the SDM interface is detected. */
3035 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
3036 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
3037 disregarded; acknowledge output is deasserted; all other signals are
3038 treated as usual; if 1 - normal activity. */
3039 #define UCM_REG_XSEM_IFEN 0xe002c
3040 /* [RC 1] Set when the message length mismatch (relative to last indication)
3041 at the xsem interface isdetected. */
3042 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
3043 /* [RW 20] Indirect access to the descriptor table of the XX protection
3044 mechanism. The fields are:[5:0] - message length; 14:6] - message
3045 pointer; 19:15] - next pointer. */
3046 #define UCM_REG_XX_DESCR_TABLE 0xe0280
3047 /* [R 6] Use to read the XX protection Free counter. */
3048 #define UCM_REG_XX_FREE 0xe016c
3049 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3050 of the Input Stage XX protection buffer by the XX protection pending
3051 messages. Write writes the initial credit value; read returns the current
3052 value of the credit counter. Must be initialized to 12 at start-up. */
3053 #define UCM_REG_XX_INIT_CRD 0xe0224
3054 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3055 protection. ~ucm_registers_xx_free.xx_free read on read. */
3056 #define UCM_REG_XX_MSG_NUM 0xe0228
3057 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3058 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
3059 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3060 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
3062 #define UCM_REG_XX_TABLE 0xe0300
3063 /* [RW 8] The event id for aggregated interrupt 0 */
3064 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
3065 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
3066 #define USDM_REG_AGG_INT_EVENT_10 0xc4060
3067 #define USDM_REG_AGG_INT_EVENT_11 0xc4064
3068 #define USDM_REG_AGG_INT_EVENT_12 0xc4068
3069 #define USDM_REG_AGG_INT_EVENT_13 0xc406c
3070 #define USDM_REG_AGG_INT_EVENT_14 0xc4070
3071 #define USDM_REG_AGG_INT_EVENT_15 0xc4074
3072 #define USDM_REG_AGG_INT_EVENT_16 0xc4078
3073 #define USDM_REG_AGG_INT_EVENT_17 0xc407c
3074 #define USDM_REG_AGG_INT_EVENT_18 0xc4080
3075 #define USDM_REG_AGG_INT_EVENT_19 0xc4084
3076 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3077 or auto-mask-mode (1) */
3078 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
3079 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
3080 #define USDM_REG_AGG_INT_MODE_10 0xc41e0
3081 #define USDM_REG_AGG_INT_MODE_11 0xc41e4
3082 #define USDM_REG_AGG_INT_MODE_12 0xc41e8
3083 #define USDM_REG_AGG_INT_MODE_13 0xc41ec
3084 #define USDM_REG_AGG_INT_MODE_14 0xc41f0
3085 #define USDM_REG_AGG_INT_MODE_15 0xc41f4
3086 #define USDM_REG_AGG_INT_MODE_16 0xc41f8
3087 #define USDM_REG_AGG_INT_MODE_17 0xc41fc
3088 #define USDM_REG_AGG_INT_MODE_18 0xc4200
3089 #define USDM_REG_AGG_INT_MODE_19 0xc4204
3090 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3091 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
3092 /* [RW 16] The maximum value of the competion counter #0 */
3093 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
3094 /* [RW 16] The maximum value of the competion counter #1 */
3095 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
3096 /* [RW 16] The maximum value of the competion counter #2 */
3097 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
3098 /* [RW 16] The maximum value of the competion counter #3 */
3099 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
3100 /* [RW 13] The start address in the internal RAM for the completion
3102 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
3103 #define USDM_REG_ENABLE_IN1 0xc4238
3104 #define USDM_REG_ENABLE_IN2 0xc423c
3105 #define USDM_REG_ENABLE_OUT1 0xc4240
3106 #define USDM_REG_ENABLE_OUT2 0xc4244
3107 /* [RW 4] The initial number of messages that can be sent to the pxp control
3108 interface without receiving any ACK. */
3109 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
3110 /* [ST 32] The number of ACK after placement messages received */
3111 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
3112 /* [ST 32] The number of packet end messages received from the parser */
3113 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
3114 /* [ST 32] The number of requests received from the pxp async if */
3115 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
3116 /* [ST 32] The number of commands received in queue 0 */
3117 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
3118 /* [ST 32] The number of commands received in queue 10 */
3119 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
3120 /* [ST 32] The number of commands received in queue 11 */
3121 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
3122 /* [ST 32] The number of commands received in queue 1 */
3123 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
3124 /* [ST 32] The number of commands received in queue 2 */
3125 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
3126 /* [ST 32] The number of commands received in queue 3 */
3127 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
3128 /* [ST 32] The number of commands received in queue 4 */
3129 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
3130 /* [ST 32] The number of commands received in queue 5 */
3131 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
3132 /* [ST 32] The number of commands received in queue 6 */
3133 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
3134 /* [ST 32] The number of commands received in queue 7 */
3135 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
3136 /* [ST 32] The number of commands received in queue 8 */
3137 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
3138 /* [ST 32] The number of commands received in queue 9 */
3139 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
3140 /* [RW 13] The start address in the internal RAM for the packet end message */
3141 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
3142 /* [RW 13] The start address in the internal RAM for queue counters */
3143 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
3144 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3145 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
3146 /* [R 1] parser fifo empty in sdm_sync block */
3147 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
3148 /* [R 1] parser serial fifo empty in sdm_sync block */
3149 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
3150 /* [RW 32] Tick for timer counter. Applicable only when
3151 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
3152 #define USDM_REG_TIMER_TICK 0xc4000
3153 /* [RW 32] Interrupt mask register #0 read/write */
3154 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
3155 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
3156 /* [RW 11] Parity mask register #0 read/write */
3157 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
3158 /* [RW 5] The number of time_slots in the arbitration cycle */
3159 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
3160 /* [RW 3] The source that is associated with arbitration element 0. Source
3161 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3162 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3163 #define USEM_REG_ARB_ELEMENT0 0x300020
3164 /* [RW 3] The source that is associated with arbitration element 1. Source
3165 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3166 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3167 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
3168 #define USEM_REG_ARB_ELEMENT1 0x300024
3169 /* [RW 3] The source that is associated with arbitration element 2. Source
3170 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3171 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3172 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3173 and ~usem_registers_arb_element1.arb_element1 */
3174 #define USEM_REG_ARB_ELEMENT2 0x300028
3175 /* [RW 3] The source that is associated with arbitration element 3. Source
3176 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3177 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3178 not be equal to register ~usem_registers_arb_element0.arb_element0 and
3179 ~usem_registers_arb_element1.arb_element1 and
3180 ~usem_registers_arb_element2.arb_element2 */
3181 #define USEM_REG_ARB_ELEMENT3 0x30002c
3182 /* [RW 3] The source that is associated with arbitration element 4. Source
3183 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3184 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3185 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3186 and ~usem_registers_arb_element1.arb_element1 and
3187 ~usem_registers_arb_element2.arb_element2 and
3188 ~usem_registers_arb_element3.arb_element3 */
3189 #define USEM_REG_ARB_ELEMENT4 0x300030
3190 #define USEM_REG_ENABLE_IN 0x3000a4
3191 #define USEM_REG_ENABLE_OUT 0x3000a8
3192 /* [RW 32] This address space contains all registers and memories that are
3193 placed in SEM_FAST block. The SEM_FAST registers are described in
3194 appendix B. In order to access the SEM_FAST registers... the base address
3195 USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each
3196 SEM_FAST register offset. */
3197 #define USEM_REG_FAST_MEMORY 0x320000
3198 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3200 #define USEM_REG_FIC0_DISABLE 0x300224
3201 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3203 #define USEM_REG_FIC1_DISABLE 0x300234
3204 /* [RW 15] Interrupt table Read and write access to it is not possible in
3205 the middle of the work */
3206 #define USEM_REG_INT_TABLE 0x300400
3207 /* [ST 24] Statistics register. The number of messages that entered through
3209 #define USEM_REG_MSG_NUM_FIC0 0x300000
3210 /* [ST 24] Statistics register. The number of messages that entered through
3212 #define USEM_REG_MSG_NUM_FIC1 0x300004
3213 /* [ST 24] Statistics register. The number of messages that were sent to
3215 #define USEM_REG_MSG_NUM_FOC0 0x300008
3216 /* [ST 24] Statistics register. The number of messages that were sent to
3218 #define USEM_REG_MSG_NUM_FOC1 0x30000c
3219 /* [ST 24] Statistics register. The number of messages that were sent to
3221 #define USEM_REG_MSG_NUM_FOC2 0x300010
3222 /* [ST 24] Statistics register. The number of messages that were sent to
3224 #define USEM_REG_MSG_NUM_FOC3 0x300014
3225 /* [RW 1] Disables input messages from the passive buffer May be updated
3226 during run_time by the microcode */
3227 #define USEM_REG_PAS_DISABLE 0x30024c
3228 /* [WB 128] Debug only. Passive buffer memory */
3229 #define USEM_REG_PASSIVE_BUFFER 0x302000
3230 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3231 #define USEM_REG_PRAM 0x340000
3232 /* [R 16] Valid sleeping threads indication have bit per thread */
3233 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
3234 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3235 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
3236 /* [RW 16] List of free threads . There is a bit per thread. */
3237 #define USEM_REG_THREADS_LIST 0x3002e4
3238 /* [RW 3] The arbitration scheme of time_slot 0 */
3239 #define USEM_REG_TS_0_AS 0x300038
3240 /* [RW 3] The arbitration scheme of time_slot 10 */
3241 #define USEM_REG_TS_10_AS 0x300060
3242 /* [RW 3] The arbitration scheme of time_slot 11 */
3243 #define USEM_REG_TS_11_AS 0x300064
3244 /* [RW 3] The arbitration scheme of time_slot 12 */
3245 #define USEM_REG_TS_12_AS 0x300068
3246 /* [RW 3] The arbitration scheme of time_slot 13 */
3247 #define USEM_REG_TS_13_AS 0x30006c
3248 /* [RW 3] The arbitration scheme of time_slot 14 */
3249 #define USEM_REG_TS_14_AS 0x300070
3250 /* [RW 3] The arbitration scheme of time_slot 15 */
3251 #define USEM_REG_TS_15_AS 0x300074
3252 /* [RW 3] The arbitration scheme of time_slot 16 */
3253 #define USEM_REG_TS_16_AS 0x300078
3254 /* [RW 3] The arbitration scheme of time_slot 17 */
3255 #define USEM_REG_TS_17_AS 0x30007c
3256 /* [RW 3] The arbitration scheme of time_slot 18 */
3257 #define USEM_REG_TS_18_AS 0x300080
3258 /* [RW 3] The arbitration scheme of time_slot 1 */
3259 #define USEM_REG_TS_1_AS 0x30003c
3260 /* [RW 3] The arbitration scheme of time_slot 2 */
3261 #define USEM_REG_TS_2_AS 0x300040
3262 /* [RW 3] The arbitration scheme of time_slot 3 */
3263 #define USEM_REG_TS_3_AS 0x300044
3264 /* [RW 3] The arbitration scheme of time_slot 4 */
3265 #define USEM_REG_TS_4_AS 0x300048
3266 /* [RW 3] The arbitration scheme of time_slot 5 */
3267 #define USEM_REG_TS_5_AS 0x30004c
3268 /* [RW 3] The arbitration scheme of time_slot 6 */
3269 #define USEM_REG_TS_6_AS 0x300050
3270 /* [RW 3] The arbitration scheme of time_slot 7 */
3271 #define USEM_REG_TS_7_AS 0x300054
3272 /* [RW 3] The arbitration scheme of time_slot 8 */
3273 #define USEM_REG_TS_8_AS 0x300058
3274 /* [RW 3] The arbitration scheme of time_slot 9 */
3275 #define USEM_REG_TS_9_AS 0x30005c
3276 /* [RW 32] Interrupt mask register #0 read/write */
3277 #define USEM_REG_USEM_INT_MASK_0 0x300110
3278 #define USEM_REG_USEM_INT_MASK_1 0x300120
3279 /* [RW 32] Parity mask register #0 read/write */
3280 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
3281 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
3282 /* [RW 2] The queue index for registration on Aux1 counter flag. */
3283 #define XCM_REG_AUX1_Q 0x20134
3284 /* [RW 2] Per each decision rule the queue index to register to. */
3285 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
3286 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3287 #define XCM_REG_CAM_OCCUP 0x20244
3288 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3289 disregarded; valid output is deasserted; all other signals are treated as
3290 usual; if 1 - normal activity. */
3291 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
3292 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3293 are disregarded; all other signals are treated as usual; if 1 - normal
3295 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
3296 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3297 disregarded; valid output is deasserted; all other signals are treated as
3298 usual; if 1 - normal activity. */
3299 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
3300 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3301 input is disregarded; all other signals are treated as usual; if 1 -
3303 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
3304 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3305 the initial credit value; read returns the current value of the credit
3306 counter. Must be initialized to 1 at start-up. */
3307 #define XCM_REG_CFC_INIT_CRD 0x20404
3308 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3309 weight 8 (the most prioritised); 1 stands for weight 1(least
3310 prioritised); 2 stands for weight 2; tc. */
3311 #define XCM_REG_CP_WEIGHT 0x200dc
3312 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3313 disregarded; acknowledge output is deasserted; all other signals are
3314 treated as usual; if 1 - normal activity. */
3315 #define XCM_REG_CSEM_IFEN 0x20028
3316 /* [RC 1] Set at message length mismatch (relative to last indication) at
3317 the csem interface. */
3318 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
3319 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3320 weight 8 (the most prioritised); 1 stands for weight 1(least
3321 prioritised); 2 stands for weight 2; tc. */
3322 #define XCM_REG_CSEM_WEIGHT 0x200c4
3323 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3324 disregarded; acknowledge output is deasserted; all other signals are
3325 treated as usual; if 1 - normal activity. */
3326 #define XCM_REG_DORQ_IFEN 0x20030
3327 /* [RC 1] Set at message length mismatch (relative to last indication) at
3328 the dorq interface. */
3329 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
3330 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
3331 #define XCM_REG_ERR_EVNT_ID 0x200b0
3332 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3333 #define XCM_REG_ERR_XCM_HDR 0x200ac
3334 /* [RW 8] The Event ID for Timers expiration. */
3335 #define XCM_REG_EXPR_EVNT_ID 0x200b4
3336 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3337 writes the initial credit value; read returns the current value of the
3338 credit counter. Must be initialized to 64 at start-up. */
3339 #define XCM_REG_FIC0_INIT_CRD 0x2040c
3340 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3341 writes the initial credit value; read returns the current value of the
3342 credit counter. Must be initialized to 64 at start-up. */
3343 #define XCM_REG_FIC1_INIT_CRD 0x20410
3344 /* [RW 8] The maximum delayed ACK counter value.Must be at least 2. Per port
3346 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
3347 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
3348 /* [RW 28] The delayed ACK timeout in ticks. Per port value. */
3349 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
3350 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
3351 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
3352 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
3353 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
3354 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
3355 #define XCM_REG_GR_ARB_TYPE 0x2020c
3356 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3357 highest priority is 3. It is supposed that the Channel group is the
3358 compliment of the other 3 groups. */
3359 #define XCM_REG_GR_LD0_PR 0x20214
3360 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3361 highest priority is 3. It is supposed that the Channel group is the
3362 compliment of the other 3 groups. */
3363 #define XCM_REG_GR_LD1_PR 0x20218
3364 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
3365 disregarded; acknowledge output is deasserted; all other signals are
3366 treated as usual; if 1 - normal activity. */
3367 #define XCM_REG_NIG0_IFEN 0x20038
3368 /* [RC 1] Set at message length mismatch (relative to last indication) at
3369 the nig0 interface. */
3370 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
3371 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
3372 disregarded; acknowledge output is deasserted; all other signals are
3373 treated as usual; if 1 - normal activity. */
3374 #define XCM_REG_NIG1_IFEN 0x2003c
3375 /* [RC 1] Set at message length mismatch (relative to last indication) at
3376 the nig1 interface. */
3377 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
3378 /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
3379 weight 8 (the most prioritised); 1 stands for weight 1(least
3380 prioritised); 2 stands for weight 2; tc. */
3381 #define XCM_REG_NIG1_WEIGHT 0x200d8
3382 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3383 sent to STORM; for a specific connection type. The double REG-pairs are
3384 used in order to align to STORM context row size of 128 bits. The offset
3385 of these data in the STORM context is always 0. Index _i stands for the
3386 connection type (one of 16). */
3387 #define XCM_REG_N_SM_CTX_LD_0 0x20060
3388 #define XCM_REG_N_SM_CTX_LD_1 0x20064
3389 #define XCM_REG_N_SM_CTX_LD_10 0x20088
3390 #define XCM_REG_N_SM_CTX_LD_11 0x2008c
3391 #define XCM_REG_N_SM_CTX_LD_12 0x20090
3392 #define XCM_REG_N_SM_CTX_LD_13 0x20094
3393 #define XCM_REG_N_SM_CTX_LD_14 0x20098
3394 #define XCM_REG_N_SM_CTX_LD_15 0x2009c
3395 #define XCM_REG_N_SM_CTX_LD_2 0x20068
3396 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
3397 #define XCM_REG_N_SM_CTX_LD_4 0x20070
3398 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3399 acknowledge output is deasserted; all other signals are treated as usual;
3400 if 1 - normal activity. */
3401 #define XCM_REG_PBF_IFEN 0x20034
3402 /* [RC 1] Set at message length mismatch (relative to last indication) at
3403 the pbf interface. */
3404 #define XCM_REG_PBF_LENGTH_MIS 0x20234
3405 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3406 weight 8 (the most prioritised); 1 stands for weight 1(least
3407 prioritised); 2 stands for weight 2; tc. */
3408 #define XCM_REG_PBF_WEIGHT 0x200d0
3409 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3410 #define XCM_REG_STOP_EVNT_ID 0x200b8
3411 /* [RC 1] Set at message length mismatch (relative to last indication) at
3412 the STORM interface. */
3413 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
3414 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3415 weight 8 (the most prioritised); 1 stands for weight 1(least
3416 prioritised); 2 stands for weight 2; tc. */
3417 #define XCM_REG_STORM_WEIGHT 0x200bc
3418 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3419 disregarded; acknowledge output is deasserted; all other signals are
3420 treated as usual; if 1 - normal activity. */
3421 #define XCM_REG_STORM_XCM_IFEN 0x20010
3422 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
3423 writes the initial credit value; read returns the current value of the
3424 credit counter. Must be initialized to 4 at start-up. */
3425 #define XCM_REG_TM_INIT_CRD 0x2041c
3426 /* [RW 28] The CM header for Timers expiration command. */
3427 #define XCM_REG_TM_XCM_HDR 0x200a8
3428 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3429 disregarded; acknowledge output is deasserted; all other signals are
3430 treated as usual; if 1 - normal activity. */
3431 #define XCM_REG_TM_XCM_IFEN 0x2001c
3432 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
3433 disregarded; acknowledge output is deasserted; all other signals are
3434 treated as usual; if 1 - normal activity. */
3435 #define XCM_REG_TSEM_IFEN 0x20024
3436 /* [RC 1] Set at message length mismatch (relative to last indication) at
3437 the tsem interface. */
3438 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
3439 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
3440 weight 8 (the most prioritised); 1 stands for weight 1(least
3441 prioritised); 2 stands for weight 2; tc. */
3442 #define XCM_REG_TSEM_WEIGHT 0x200c0
3443 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
3444 #define XCM_REG_UNA_GT_NXT_Q 0x20120
3445 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3446 disregarded; acknowledge output is deasserted; all other signals are
3447 treated as usual; if 1 - normal activity. */
3448 #define XCM_REG_USEM_IFEN 0x2002c
3449 /* [RC 1] Message length mismatch (relative to last indication) at the usem
3451 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
3452 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3453 weight 8 (the most prioritised); 1 stands for weight 1(least
3454 prioritised); 2 stands for weight 2; tc. */
3455 #define XCM_REG_USEM_WEIGHT 0x200c8
3456 /* [RW 2] DA counter command; used in case of window update doorbell.The
3457 first index stands for the value DaEnable of that connection. The second
3458 index stands for port number. */
3459 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
3460 /* [RW 2] DA counter command; used in case of window update doorbell.The
3461 first index stands for the value DaEnable of that connection. The second
3462 index stands for port number. */
3463 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
3464 /* [RW 2] DA counter command; used in case of window update doorbell.The
3465 first index stands for the value DaEnable of that connection. The second
3466 index stands for port number. */
3467 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
3468 /* [RW 2] DA counter command; used in case of window update doorbell.The
3469 first index stands for the value DaEnable of that connection. The second
3470 index stands for port number. */
3471 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
3472 /* [RW 8] DA counter update value used in case of window update doorbell.The
3473 first index stands for the value DaEnable of that connection. The second
3474 index stands for port number. */
3475 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
3476 /* [RW 8] DA counter update value; used in case of window update
3477 doorbell.The first index stands for the value DaEnable of that
3478 connection. The second index stands for port number. */
3479 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
3480 /* [RW 8] DA counter update value; used in case of window update
3481 doorbell.The first index stands for the value DaEnable of that
3482 connection. The second index stands for port number. */
3483 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
3484 /* [RW 8] DA counter update value; used in case of window update
3485 doorbell.The first index stands for the value DaEnable of that
3486 connection. The second index stands for port number. */
3487 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
3488 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3489 index stands for the value DaEnable of that connection. The second index
3490 stands for port number. */
3491 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
3492 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3493 index stands for the value DaEnable of that connection. The second index
3494 stands for port number. */
3495 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
3496 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3497 index stands for the value DaEnable of that connection. The second index
3498 stands for port number. */
3499 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
3500 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3501 index stands for the value DaEnable of that connection. The second index
3502 stands for port number. */
3503 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
3504 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3505 acknowledge output is deasserted; all other signals are treated as usual;
3506 if 1 - normal activity. */
3507 #define XCM_REG_XCM_CFC_IFEN 0x20050
3508 /* [RW 14] Interrupt mask register #0 read/write */
3509 #define XCM_REG_XCM_INT_MASK 0x202b4
3510 /* [R 14] Interrupt register #0 read */
3511 #define XCM_REG_XCM_INT_STS 0x202a8
3512 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
3513 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3514 Is used to determine the number of the AG context REG-pairs written back;
3515 when the Reg1WbFlg isn't set. */
3516 #define XCM_REG_XCM_REG0_SZ 0x200f4
3517 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3518 disregarded; valid is deasserted; all other signals are treated as usual;
3519 if 1 - normal activity. */
3520 #define XCM_REG_XCM_STORM0_IFEN 0x20004
3521 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3522 disregarded; valid is deasserted; all other signals are treated as usual;
3523 if 1 - normal activity. */
3524 #define XCM_REG_XCM_STORM1_IFEN 0x20008
3525 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3526 disregarded; acknowledge output is deasserted; all other signals are
3527 treated as usual; if 1 - normal activity. */
3528 #define XCM_REG_XCM_TM_IFEN 0x20020
3529 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3530 disregarded; valid is deasserted; all other signals are treated as usual;
3531 if 1 - normal activity. */
3532 #define XCM_REG_XCM_XQM_IFEN 0x2000c
3533 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3534 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
3535 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
3536 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
3537 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3538 the initial credit value; read returns the current value of the credit
3539 counter. Must be initialized to 32 at start-up. */
3540 #define XCM_REG_XQM_INIT_CRD 0x20420
3541 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3542 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3543 prioritised); 2 stands for weight 2; tc. */
3544 #define XCM_REG_XQM_P_WEIGHT 0x200e4
3545 /* [RW 28] The CM header value for QM request (primary). */
3546 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
3547 /* [RW 28] The CM header value for QM request (secondary). */
3548 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
3549 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3550 acknowledge output is deasserted; all other signals are treated as usual;
3551 if 1 - normal activity. */
3552 #define XCM_REG_XQM_XCM_IFEN 0x20014
3553 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3554 acknowledge output is deasserted; all other signals are treated as usual;
3555 if 1 - normal activity. */
3556 #define XCM_REG_XSDM_IFEN 0x20018
3557 /* [RC 1] Set at message length mismatch (relative to last indication) at
3558 the SDM interface. */
3559 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
3560 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3561 weight 8 (the most prioritised); 1 stands for weight 1(least
3562 prioritised); 2 stands for weight 2; tc. */
3563 #define XCM_REG_XSDM_WEIGHT 0x200e0
3564 /* [RW 17] Indirect access to the descriptor table of the XX protection
3565 mechanism. The fields are: [5:0] - message length; 11:6] - message
3566 pointer; 16:12] - next pointer. */
3567 #define XCM_REG_XX_DESCR_TABLE 0x20480
3568 /* [R 6] Used to read the XX protection Free counter. */
3569 #define XCM_REG_XX_FREE 0x20240
3570 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3571 of the Input Stage XX protection buffer by the XX protection pending
3572 messages. Max credit available - 3.Write writes the initial credit value;
3573 read returns the current value of the credit counter. Must be initialized
3574 to 2 at start-up. */
3575 #define XCM_REG_XX_INIT_CRD 0x20424
3576 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3577 protection. ~xcm_registers_xx_free.xx_free read on read. */
3578 #define XCM_REG_XX_MSG_NUM 0x20428
3579 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3580 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
3581 /* [RW 15] Indirect access to the XX table of the XX protection mechanism.
3582 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
3584 #define XCM_REG_XX_TABLE 0x20500
3585 /* [RW 8] The event id for aggregated interrupt 0 */
3586 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
3587 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
3588 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
3589 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
3590 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
3591 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
3592 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
3593 #define XSDM_REG_AGG_INT_EVENT_15 0x166074
3594 #define XSDM_REG_AGG_INT_EVENT_16 0x166078
3595 #define XSDM_REG_AGG_INT_EVENT_17 0x16607c
3596 #define XSDM_REG_AGG_INT_EVENT_18 0x166080
3597 #define XSDM_REG_AGG_INT_EVENT_19 0x166084
3598 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
3599 #define XSDM_REG_AGG_INT_EVENT_20 0x166088
3600 #define XSDM_REG_AGG_INT_EVENT_21 0x16608c
3601 #define XSDM_REG_AGG_INT_EVENT_22 0x166090
3602 #define XSDM_REG_AGG_INT_EVENT_23 0x166094
3603 #define XSDM_REG_AGG_INT_EVENT_24 0x166098
3604 #define XSDM_REG_AGG_INT_EVENT_25 0x16609c
3605 #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
3606 #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
3607 #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
3608 #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
3609 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3610 or auto-mask-mode (1) */
3611 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
3612 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
3613 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0
3614 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4
3615 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8
3616 #define XSDM_REG_AGG_INT_MODE_13 0x1661ec
3617 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0
3618 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4
3619 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8
3620 #define XSDM_REG_AGG_INT_MODE_17 0x1661fc
3621 #define XSDM_REG_AGG_INT_MODE_18 0x166200
3622 #define XSDM_REG_AGG_INT_MODE_19 0x166204
3623 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3624 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
3625 /* [RW 16] The maximum value of the competion counter #0 */
3626 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
3627 /* [RW 16] The maximum value of the competion counter #1 */
3628 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
3629 /* [RW 16] The maximum value of the competion counter #2 */
3630 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
3631 /* [RW 16] The maximum value of the competion counter #3 */
3632 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
3633 /* [RW 13] The start address in the internal RAM for the completion
3635 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
3636 #define XSDM_REG_ENABLE_IN1 0x166238
3637 #define XSDM_REG_ENABLE_IN2 0x16623c
3638 #define XSDM_REG_ENABLE_OUT1 0x166240
3639 #define XSDM_REG_ENABLE_OUT2 0x166244
3640 /* [RW 4] The initial number of messages that can be sent to the pxp control
3641 interface without receiving any ACK. */
3642 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
3643 /* [ST 32] The number of ACK after placement messages received */
3644 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
3645 /* [ST 32] The number of packet end messages received from the parser */
3646 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
3647 /* [ST 32] The number of requests received from the pxp async if */
3648 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
3649 /* [ST 32] The number of commands received in queue 0 */
3650 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
3651 /* [ST 32] The number of commands received in queue 10 */
3652 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
3653 /* [ST 32] The number of commands received in queue 11 */
3654 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
3655 /* [ST 32] The number of commands received in queue 1 */
3656 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
3657 /* [ST 32] The number of commands received in queue 3 */
3658 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
3659 /* [ST 32] The number of commands received in queue 4 */
3660 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
3661 /* [ST 32] The number of commands received in queue 5 */
3662 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
3663 /* [ST 32] The number of commands received in queue 6 */
3664 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
3665 /* [ST 32] The number of commands received in queue 7 */
3666 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
3667 /* [ST 32] The number of commands received in queue 8 */
3668 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
3669 /* [ST 32] The number of commands received in queue 9 */
3670 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
3671 /* [RW 13] The start address in the internal RAM for queue counters */
3672 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
3673 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3674 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
3675 /* [R 1] parser fifo empty in sdm_sync block */
3676 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
3677 /* [R 1] parser serial fifo empty in sdm_sync block */
3678 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
3679 /* [RW 32] Tick for timer counter. Applicable only when
3680 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3681 #define XSDM_REG_TIMER_TICK 0x166000
3682 /* [RW 32] Interrupt mask register #0 read/write */
3683 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
3684 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
3685 /* [RW 11] Parity mask register #0 read/write */
3686 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
3687 /* [RW 5] The number of time_slots in the arbitration cycle */
3688 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
3689 /* [RW 3] The source that is associated with arbitration element 0. Source
3690 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3691 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3692 #define XSEM_REG_ARB_ELEMENT0 0x280020
3693 /* [RW 3] The source that is associated with arbitration element 1. Source
3694 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3695 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3696 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
3697 #define XSEM_REG_ARB_ELEMENT1 0x280024
3698 /* [RW 3] The source that is associated with arbitration element 2. Source
3699 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3700 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3701 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3702 and ~xsem_registers_arb_element1.arb_element1 */
3703 #define XSEM_REG_ARB_ELEMENT2 0x280028
3704 /* [RW 3] The source that is associated with arbitration element 3. Source
3705 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3706 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3707 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
3708 ~xsem_registers_arb_element1.arb_element1 and
3709 ~xsem_registers_arb_element2.arb_element2 */
3710 #define XSEM_REG_ARB_ELEMENT3 0x28002c
3711 /* [RW 3] The source that is associated with arbitration element 4. Source
3712 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3713 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3714 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3715 and ~xsem_registers_arb_element1.arb_element1 and
3716 ~xsem_registers_arb_element2.arb_element2 and
3717 ~xsem_registers_arb_element3.arb_element3 */
3718 #define XSEM_REG_ARB_ELEMENT4 0x280030
3719 #define XSEM_REG_ENABLE_IN 0x2800a4
3720 #define XSEM_REG_ENABLE_OUT 0x2800a8
3721 /* [RW 32] This address space contains all registers and memories that are
3722 placed in SEM_FAST block. The SEM_FAST registers are described in
3723 appendix B. In order to access the SEM_FAST registers the base address
3724 XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each
3725 SEM_FAST register offset. */
3726 #define XSEM_REG_FAST_MEMORY 0x2a0000
3727 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3729 #define XSEM_REG_FIC0_DISABLE 0x280224
3730 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3732 #define XSEM_REG_FIC1_DISABLE 0x280234
3733 /* [RW 15] Interrupt table Read and write access to it is not possible in
3734 the middle of the work */
3735 #define XSEM_REG_INT_TABLE 0x280400
3736 /* [ST 24] Statistics register. The number of messages that entered through
3738 #define XSEM_REG_MSG_NUM_FIC0 0x280000
3739 /* [ST 24] Statistics register. The number of messages that entered through
3741 #define XSEM_REG_MSG_NUM_FIC1 0x280004
3742 /* [ST 24] Statistics register. The number of messages that were sent to
3744 #define XSEM_REG_MSG_NUM_FOC0 0x280008
3745 /* [ST 24] Statistics register. The number of messages that were sent to
3747 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
3748 /* [ST 24] Statistics register. The number of messages that were sent to
3750 #define XSEM_REG_MSG_NUM_FOC2 0x280010
3751 /* [ST 24] Statistics register. The number of messages that were sent to
3753 #define XSEM_REG_MSG_NUM_FOC3 0x280014
3754 /* [RW 1] Disables input messages from the passive buffer May be updated
3755 during run_time by the microcode */
3756 #define XSEM_REG_PAS_DISABLE 0x28024c
3757 /* [WB 128] Debug only. Passive buffer memory */
3758 #define XSEM_REG_PASSIVE_BUFFER 0x282000
3759 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3760 #define XSEM_REG_PRAM 0x2c0000
3761 /* [R 16] Valid sleeping threads indication have bit per thread */
3762 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
3763 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3764 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
3765 /* [RW 16] List of free threads . There is a bit per thread. */
3766 #define XSEM_REG_THREADS_LIST 0x2802e4
3767 /* [RW 3] The arbitration scheme of time_slot 0 */
3768 #define XSEM_REG_TS_0_AS 0x280038
3769 /* [RW 3] The arbitration scheme of time_slot 10 */
3770 #define XSEM_REG_TS_10_AS 0x280060
3771 /* [RW 3] The arbitration scheme of time_slot 11 */
3772 #define XSEM_REG_TS_11_AS 0x280064
3773 /* [RW 3] The arbitration scheme of time_slot 12 */
3774 #define XSEM_REG_TS_12_AS 0x280068
3775 /* [RW 3] The arbitration scheme of time_slot 13 */
3776 #define XSEM_REG_TS_13_AS 0x28006c
3777 /* [RW 3] The arbitration scheme of time_slot 14 */
3778 #define XSEM_REG_TS_14_AS 0x280070
3779 /* [RW 3] The arbitration scheme of time_slot 15 */
3780 #define XSEM_REG_TS_15_AS 0x280074
3781 /* [RW 3] The arbitration scheme of time_slot 16 */
3782 #define XSEM_REG_TS_16_AS 0x280078
3783 /* [RW 3] The arbitration scheme of time_slot 17 */
3784 #define XSEM_REG_TS_17_AS 0x28007c
3785 /* [RW 3] The arbitration scheme of time_slot 18 */
3786 #define XSEM_REG_TS_18_AS 0x280080
3787 /* [RW 3] The arbitration scheme of time_slot 1 */
3788 #define XSEM_REG_TS_1_AS 0x28003c
3789 /* [RW 3] The arbitration scheme of time_slot 2 */
3790 #define XSEM_REG_TS_2_AS 0x280040
3791 /* [RW 3] The arbitration scheme of time_slot 3 */
3792 #define XSEM_REG_TS_3_AS 0x280044
3793 /* [RW 3] The arbitration scheme of time_slot 4 */
3794 #define XSEM_REG_TS_4_AS 0x280048
3795 /* [RW 3] The arbitration scheme of time_slot 5 */
3796 #define XSEM_REG_TS_5_AS 0x28004c
3797 /* [RW 3] The arbitration scheme of time_slot 6 */
3798 #define XSEM_REG_TS_6_AS 0x280050
3799 /* [RW 3] The arbitration scheme of time_slot 7 */
3800 #define XSEM_REG_TS_7_AS 0x280054
3801 /* [RW 3] The arbitration scheme of time_slot 8 */
3802 #define XSEM_REG_TS_8_AS 0x280058
3803 /* [RW 3] The arbitration scheme of time_slot 9 */
3804 #define XSEM_REG_TS_9_AS 0x28005c
3805 /* [RW 32] Interrupt mask register #0 read/write */
3806 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
3807 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
3808 /* [RW 32] Parity mask register #0 read/write */
3809 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
3810 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
3811 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
3812 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
3813 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
3814 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
3815 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
3816 #define MCPR_NVM_COMMAND_DONE (1L<<3)
3817 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
3818 #define MCPR_NVM_COMMAND_LAST (1L<<8)
3819 #define MCPR_NVM_COMMAND_WR (1L<<5)
3820 #define MCPR_NVM_COMMAND_WREN (1L<<16)
3821 #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
3822 #define MCPR_NVM_COMMAND_WRDI (1L<<17)
3823 #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
3824 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
3825 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
3826 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
3827 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
3828 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
3829 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
3830 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
3831 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
3832 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
3833 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
3834 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
3835 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
3836 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
3837 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
3838 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
3839 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
3840 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
3841 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
3842 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
3843 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
3844 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
3845 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
3846 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
3847 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
3848 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
3849 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
3850 #define EMAC_MODE_25G_MODE (1L<<5)
3851 #define EMAC_MODE_ACPI_RCVD (1L<<20)
3852 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
3853 #define EMAC_MODE_MPKT (1L<<18)
3854 #define EMAC_MODE_MPKT_RCVD (1L<<19)
3855 #define EMAC_MODE_PORT_GMII (2L<<2)
3856 #define EMAC_MODE_PORT_MII (1L<<2)
3857 #define EMAC_MODE_PORT_MII_10M (3L<<2)
3858 #define EMAC_MODE_RESET (1L<<0)
3859 #define EMAC_REG_EMAC_MAC_MATCH 0x10
3860 #define EMAC_REG_EMAC_MDIO_COMM 0xac
3861 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
3862 #define EMAC_REG_EMAC_MODE 0x0
3863 #define EMAC_REG_EMAC_RX_MODE 0xc8
3864 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
3865 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
3866 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
3867 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
3868 #define EMAC_REG_EMAC_TX_MODE 0xbc
3869 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
3870 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
3871 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
3872 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
3873 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
3874 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
3875 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
3876 #define EMAC_TX_MODE_RESET (1L<<0)
3877 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
3878 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
3879 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
3880 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
3881 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
3882 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
3883 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
3884 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
3885 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
3886 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
3887 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
3888 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
3889 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
3890 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
3891 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
3892 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
3893 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
3894 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
3895 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
3896 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
3897 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
3898 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
3899 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
3900 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
3901 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
3902 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
3903 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
3904 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
3905 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
3906 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
3907 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
3908 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
3909 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
3910 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
3911 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
3912 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
3913 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
3914 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
3915 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
3916 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
3917 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
3918 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
3919 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
3920 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
3921 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
3922 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
3923 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
3924 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
3925 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
3926 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
3927 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
3928 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
3929 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
3930 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
3931 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
3932 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
3933 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
3934 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
3935 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
3936 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
3937 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
3938 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
3939 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
3940 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
3942 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0
3943 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
3945 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
3946 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
3947 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
3948 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
3949 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
3950 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
3951 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
3952 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
3953 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
3954 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
3955 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
3956 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
3957 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
3958 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
3959 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
3960 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
3962 /* storm asserts attention bits */
3963 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
3964 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
3965 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
3966 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
3968 /* mcp error attention bit */
3969 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
3971 #define LATCHED_ATTN_RBCR 23
3972 #define LATCHED_ATTN_RBCT 24
3973 #define LATCHED_ATTN_RBCN 25
3974 #define LATCHED_ATTN_RBCU 26
3975 #define LATCHED_ATTN_RBCP 27
3976 #define LATCHED_ATTN_TIMEOUT_GRC 28
3977 #define LATCHED_ATTN_RSVD_GRC 29
3978 #define LATCHED_ATTN_ROM_PARITY_MCP 30
3979 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
3980 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
3981 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
3983 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
3984 #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
3986 * This file defines GRC base address for every block.
3987 * This file is included by chipsim, asm microcode and cpp microcode.
3988 * These values are used in Design.xml on regBase attribute
3989 * Use the base with the generated offsets of specific registers.
3992 #define GRCBASE_PXPCS 0x000000
3993 #define GRCBASE_PCICONFIG 0x002000
3994 #define GRCBASE_PCIREG 0x002400
3995 #define GRCBASE_EMAC0 0x008000
3996 #define GRCBASE_EMAC1 0x008400
3997 #define GRCBASE_DBU 0x008800
3998 #define GRCBASE_MISC 0x00A000
3999 #define GRCBASE_DBG 0x00C000
4000 #define GRCBASE_NIG 0x010000
4001 #define GRCBASE_XCM 0x020000
4002 #define GRCBASE_PRS 0x040000
4003 #define GRCBASE_SRCH 0x040400
4004 #define GRCBASE_TSDM 0x042000
4005 #define GRCBASE_TCM 0x050000
4006 #define GRCBASE_BRB1 0x060000
4007 #define GRCBASE_MCP 0x080000
4008 #define GRCBASE_UPB 0x0C1000
4009 #define GRCBASE_CSDM 0x0C2000
4010 #define GRCBASE_USDM 0x0C4000
4011 #define GRCBASE_CCM 0x0D0000
4012 #define GRCBASE_UCM 0x0E0000
4013 #define GRCBASE_CDU 0x101000
4014 #define GRCBASE_DMAE 0x102000
4015 #define GRCBASE_PXP 0x103000
4016 #define GRCBASE_CFC 0x104000
4017 #define GRCBASE_HC 0x108000
4018 #define GRCBASE_PXP2 0x120000
4019 #define GRCBASE_PBF 0x140000
4020 #define GRCBASE_XPB 0x161000
4021 #define GRCBASE_TIMERS 0x164000
4022 #define GRCBASE_XSDM 0x166000
4023 #define GRCBASE_QM 0x168000
4024 #define GRCBASE_DQ 0x170000
4025 #define GRCBASE_TSEM 0x180000
4026 #define GRCBASE_CSEM 0x200000
4027 #define GRCBASE_XSEM 0x280000
4028 #define GRCBASE_USEM 0x300000
4029 #define GRCBASE_MISC_AEU GRCBASE_MISC
4032 /*the offset of the configuration space in the pci core register*/
4033 #define PCICFG_OFFSET 0x2000
4034 #define PCICFG_VENDOR_ID_OFFSET 0x00
4035 #define PCICFG_DEVICE_ID_OFFSET 0x02
4036 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
4037 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
4038 #define PCICFG_INT_LINE 0x3c
4039 #define PCICFG_INT_PIN 0x3d
4040 #define PCICFG_CACHE_LINE_SIZE 0x0c
4041 #define PCICFG_LATENCY_TIMER 0x0d
4042 #define PCICFG_REVESION_ID 0x08
4043 #define PCICFG_BAR_1_LOW 0x10
4044 #define PCICFG_BAR_1_HIGH 0x14
4045 #define PCICFG_BAR_2_LOW 0x18
4046 #define PCICFG_BAR_2_HIGH 0x1c
4047 #define PCICFG_GRC_ADDRESS 0x78
4048 #define PCICFG_GRC_DATA 0x80
4049 #define PCICFG_DEVICE_CONTROL 0xb4
4050 #define PCICFG_LINK_CONTROL 0xbc
4052 #define BAR_USTRORM_INTMEM 0x400000
4053 #define BAR_CSTRORM_INTMEM 0x410000
4054 #define BAR_XSTRORM_INTMEM 0x420000
4055 #define BAR_TSTRORM_INTMEM 0x430000
4057 #define BAR_IGU_INTMEM 0x440000
4059 #define BAR_DOORBELL_OFFSET 0x800000
4061 #define BAR_ME_REGISTER 0x450000
4064 #define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */
4065 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
4066 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
4067 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
4068 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
4069 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
4070 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
4071 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
4072 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
4073 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
4074 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
4075 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
4076 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
4077 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
4078 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
4079 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
4080 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
4081 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
4082 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
4083 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
4084 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
4085 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
4086 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
4087 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
4088 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
4089 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
4090 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
4091 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
4092 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
4093 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
4094 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
4095 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
4096 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
4097 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
4098 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
4099 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
4100 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
4101 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
4102 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
4103 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
4104 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
4106 /* config_3 offset */
4107 #define GRC_CONFIG_3_SIZE_REG (0x40c)
4108 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
4109 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
4110 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
4111 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
4112 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
4113 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
4114 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
4116 /* config_2 offset */
4117 #define GRC_CONFIG_2_SIZE_REG 0x408
4119 #define GRC_BAR2_CONFIG 0x4e0
4120 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
4121 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
4122 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
4123 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
4124 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
4125 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
4126 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
4127 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
4128 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
4129 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
4130 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
4131 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
4132 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
4133 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
4134 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
4135 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
4136 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
4137 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
4139 #define PCI_PM_DATA_A (0x410)
4140 #define PCI_PM_DATA_B (0x414)
4141 #define PCI_ID_VAL1 (0x434)
4142 #define PCI_ID_VAL2 (0x438)
4144 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
4145 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
4146 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
4147 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
4148 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
4150 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
4151 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
4152 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
4153 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
4154 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
4155 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
4157 #define MDIO_REG_BANK_RX0 0x80b0
4158 #define MDIO_RX0_RX_EQ_BOOST 0x1c
4159 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4160 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
4162 #define MDIO_REG_BANK_RX1 0x80c0
4163 #define MDIO_RX1_RX_EQ_BOOST 0x1c
4164 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4165 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
4167 #define MDIO_REG_BANK_RX2 0x80d0
4168 #define MDIO_RX2_RX_EQ_BOOST 0x1c
4169 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4170 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
4172 #define MDIO_REG_BANK_RX3 0x80e0
4173 #define MDIO_RX3_RX_EQ_BOOST 0x1c
4174 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4175 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
4177 #define MDIO_REG_BANK_RX_ALL 0x80f0
4178 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
4179 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4180 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
4182 #define MDIO_REG_BANK_TX0 0x8060
4183 #define MDIO_TX0_TX_DRIVER 0x17
4184 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4185 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4186 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4187 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4188 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4189 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4190 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4191 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4192 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4194 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
4195 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
4197 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
4198 #define MDIO_BLOCK1_LANE_CTRL0 0x15
4199 #define MDIO_BLOCK1_LANE_CTRL1 0x16
4200 #define MDIO_BLOCK1_LANE_CTRL2 0x17
4201 #define MDIO_BLOCK1_LANE_PRBS 0x19
4203 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
4204 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
4205 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
4206 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
4207 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
4208 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
4209 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
4211 #define MDIO_REG_BANK_GP_STATUS 0x8120
4212 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
4213 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
4214 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
4215 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
4216 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
4217 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
4218 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
4220 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
4221 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
4222 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
4223 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
4224 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
4225 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
4226 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
4227 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
4228 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
4229 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
4230 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
4231 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
4232 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
4233 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
4234 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
4235 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
4236 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
4237 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4240 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
4241 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
4242 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
4243 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
4244 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
4246 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
4247 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
4248 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
4249 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
4250 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
4251 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
4252 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
4253 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
4254 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
4255 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
4256 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
4257 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
4258 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
4259 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
4260 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
4261 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
4262 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
4263 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
4264 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
4265 #define MDIO_SERDES_DIGITAL_MISC1 0x18
4266 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
4267 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
4268 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
4269 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
4270 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
4271 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
4272 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
4273 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
4274 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
4275 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
4276 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
4277 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
4278 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
4279 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
4280 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
4281 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
4282 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
4283 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
4285 #define MDIO_REG_BANK_OVER_1G 0x8320
4286 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
4287 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
4288 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
4289 #define MDIO_OVER_1G_UP1 0x19
4290 #define MDIO_OVER_1G_UP1_2_5G 0x0001
4291 #define MDIO_OVER_1G_UP1_5G 0x0002
4292 #define MDIO_OVER_1G_UP1_6G 0x0004
4293 #define MDIO_OVER_1G_UP1_10G 0x0010
4294 #define MDIO_OVER_1G_UP1_10GH 0x0008
4295 #define MDIO_OVER_1G_UP1_12G 0x0020
4296 #define MDIO_OVER_1G_UP1_12_5G 0x0040
4297 #define MDIO_OVER_1G_UP1_13G 0x0080
4298 #define MDIO_OVER_1G_UP1_15G 0x0100
4299 #define MDIO_OVER_1G_UP1_16G 0x0200
4300 #define MDIO_OVER_1G_UP2 0x1A
4301 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
4302 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
4303 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
4304 #define MDIO_OVER_1G_UP3 0x1B
4305 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
4306 #define MDIO_OVER_1G_LP_UP1 0x1C
4307 #define MDIO_OVER_1G_LP_UP2 0x1D
4308 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
4309 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
4310 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
4311 #define MDIO_OVER_1G_LP_UP3 0x1E
4313 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
4314 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
4315 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
4316 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
4318 #define MDIO_REG_BANK_CL73_USERB0 0x8370
4319 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
4320 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
4321 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
4322 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
4323 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
4324 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
4326 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
4327 #define MDIO_AER_BLOCK_AER_REG 0x1E
4329 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
4330 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
4331 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
4332 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
4333 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
4334 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
4335 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
4336 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
4337 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
4338 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
4339 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
4340 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
4341 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
4342 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
4343 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
4344 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
4345 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
4346 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
4347 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
4348 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
4349 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
4350 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
4351 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
4352 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
4353 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
4354 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
4355 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
4356 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
4358 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
4360 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
4361 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
4362 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
4365 #define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
4366 #define EXT_PHY_OPT_WIS_DEVAD 0x2
4367 #define EXT_PHY_OPT_PCS_DEVAD 0x3
4368 #define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
4369 #define EXT_PHY_OPT_CNTL 0x0
4370 #define EXT_PHY_OPT_PMD_RX_SD 0xa
4371 #define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
4372 #define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
4373 #define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
4374 #define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
4375 #define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
4376 #define EXT_PHY_OPT_LASI_CNTL 0x9002
4377 #define EXT_PHY_OPT_RX_ALARM 0x9003
4378 #define EXT_PHY_OPT_LASI_STATUS 0x9005
4379 #define EXT_PHY_OPT_PCS_STATUS 0x0020
4380 #define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
4382 #define EXT_PHY_KR_PMA_PMD_DEVAD 0x1
4383 #define EXT_PHY_KR_PCS_DEVAD 0x3
4384 #define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7
4385 #define EXT_PHY_KR_CTRL 0x0000
4386 #define EXT_PHY_KR_CTRL2 0x0007
4387 #define EXT_PHY_KR_PCS_STATUS 0x0020
4388 #define EXT_PHY_KR_PMD_CTRL 0x0096
4389 #define EXT_PHY_KR_LASI_CNTL 0x9002
4390 #define EXT_PHY_KR_LASI_STATUS 0x9005
4391 #define EXT_PHY_KR_MISC_CTRL1 0xca85
4392 #define EXT_PHY_KR_GEN_CTRL 0xca10
4393 #define EXT_PHY_KR_ROM_CODE 0xca19
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