1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
23 /* [R 19] Interrupt register #0 read */
24 #define BRB1_REG_BRB1_INT_STS 0x6011c
25 /* [RW 4] Parity mask register #0 read/write */
26 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
27 /* [R 4] Parity register #0 read */
28 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
29 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
32 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
33 /* [RW 10] The number of free blocks above which the High_llfc signal to
34 interface #n is de-asserted. */
35 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
36 /* [RW 10] The number of free blocks below which the High_llfc signal to
37 interface #n is asserted. */
38 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
39 /* [RW 23] LL RAM data. */
40 #define BRB1_REG_LL_RAM 0x61000
41 /* [RW 10] The number of free blocks above which the Low_llfc signal to
42 interface #n is de-asserted. */
43 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
44 /* [RW 10] The number of free blocks below which the Low_llfc signal to
45 interface #n is asserted. */
46 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
47 /* [R 24] The number of full blocks. */
48 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
49 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
51 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
52 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
53 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
54 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
56 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
57 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
58 /* [RW 10] Write client 0: De-assert pause threshold. */
59 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
60 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
61 /* [RW 10] Write client 0: Assert pause threshold. */
62 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
63 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
64 /* [R 24] The number of full blocks occupied by port. */
65 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
66 /* [RW 1] Reset the design by software. */
67 #define BRB1_REG_SOFT_RESET 0x600dc
68 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
69 #define CCM_REG_CAM_OCCUP 0xd0188
70 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
71 acknowledge output is deasserted; all other signals are treated as usual;
72 if 1 - normal activity. */
73 #define CCM_REG_CCM_CFC_IFEN 0xd003c
74 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
75 disregarded; valid is deasserted; all other signals are treated as usual;
76 if 1 - normal activity. */
77 #define CCM_REG_CCM_CQM_IFEN 0xd000c
78 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
79 Otherwise 0 is inserted. */
80 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
81 /* [RW 11] Interrupt mask register #0 read/write */
82 #define CCM_REG_CCM_INT_MASK 0xd01e4
83 /* [R 11] Interrupt register #0 read */
84 #define CCM_REG_CCM_INT_STS 0xd01d8
85 /* [R 27] Parity register #0 read */
86 #define CCM_REG_CCM_PRTY_STS 0xd01e8
87 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
88 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
89 Is used to determine the number of the AG context REG-pairs written back;
90 when the input message Reg1WbFlg isn't set. */
91 #define CCM_REG_CCM_REG0_SZ 0xd00c4
92 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
93 disregarded; valid is deasserted; all other signals are treated as usual;
94 if 1 - normal activity. */
95 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
96 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
97 disregarded; valid is deasserted; all other signals are treated as usual;
98 if 1 - normal activity. */
99 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
100 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
101 disregarded; valid output is deasserted; all other signals are treated as
102 usual; if 1 - normal activity. */
103 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
104 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
105 are disregarded; all other signals are treated as usual; if 1 - normal
107 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
108 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
109 disregarded; valid output is deasserted; all other signals are treated as
110 usual; if 1 - normal activity. */
111 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
112 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
113 input is disregarded; all other signals are treated as usual; if 1 -
115 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
116 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
117 the initial credit value; read returns the current value of the credit
118 counter. Must be initialized to 1 at start-up. */
119 #define CCM_REG_CFC_INIT_CRD 0xd0204
120 /* [RW 2] Auxillary counter flag Q number 1. */
121 #define CCM_REG_CNT_AUX1_Q 0xd00c8
122 /* [RW 2] Auxillary counter flag Q number 2. */
123 #define CCM_REG_CNT_AUX2_Q 0xd00cc
124 /* [RW 28] The CM header value for QM request (primary). */
125 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
126 /* [RW 28] The CM header value for QM request (secondary). */
127 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
128 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
129 acknowledge output is deasserted; all other signals are treated as usual;
130 if 1 - normal activity. */
131 #define CCM_REG_CQM_CCM_IFEN 0xd0014
132 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
133 the initial credit value; read returns the current value of the credit
134 counter. Must be initialized to 32 at start-up. */
135 #define CCM_REG_CQM_INIT_CRD 0xd020c
136 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
137 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
138 prioritised); 2 stands for weight 2; tc. */
139 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
140 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
141 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
142 prioritised); 2 stands for weight 2; tc. */
143 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
144 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
145 acknowledge output is deasserted; all other signals are treated as usual;
146 if 1 - normal activity. */
147 #define CCM_REG_CSDM_IFEN 0xd0018
148 /* [RC 1] Set when the message length mismatch (relative to last indication)
149 at the SDM interface is detected. */
150 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
151 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
152 weight 8 (the most prioritised); 1 stands for weight 1(least
153 prioritised); 2 stands for weight 2; tc. */
154 #define CCM_REG_CSDM_WEIGHT 0xd00b4
155 /* [RW 28] The CM header for QM formatting in case of an error in the QM
157 #define CCM_REG_ERR_CCM_HDR 0xd0094
158 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
159 #define CCM_REG_ERR_EVNT_ID 0xd0098
160 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
161 writes the initial credit value; read returns the current value of the
162 credit counter. Must be initialized to 64 at start-up. */
163 #define CCM_REG_FIC0_INIT_CRD 0xd0210
164 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
165 writes the initial credit value; read returns the current value of the
166 credit counter. Must be initialized to 64 at start-up. */
167 #define CCM_REG_FIC1_INIT_CRD 0xd0214
168 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
169 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
170 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
171 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
172 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
173 #define CCM_REG_GR_ARB_TYPE 0xd015c
174 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
175 highest priority is 3. It is supposed; that the Store channel priority is
176 the compliment to 4 of the rest priorities - Aggregation channel; Load
177 (FIC0) channel and Load (FIC1). */
178 #define CCM_REG_GR_LD0_PR 0xd0164
179 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
180 highest priority is 3. It is supposed; that the Store channel priority is
181 the compliment to 4 of the rest priorities - Aggregation channel; Load
182 (FIC0) channel and Load (FIC1). */
183 #define CCM_REG_GR_LD1_PR 0xd0168
184 /* [RW 2] General flags index. */
185 #define CCM_REG_INV_DONE_Q 0xd0108
186 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
187 context and sent to STORM; for a specific connection type. The double
188 REG-pairs are used in order to align to STORM context row size of 128
189 bits. The offset of these data in the STORM context is always 0. Index
190 _(0..15) stands for the connection type (one of 16). */
191 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
192 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
193 #define CCM_REG_N_SM_CTX_LD_10 0xd0074
194 #define CCM_REG_N_SM_CTX_LD_11 0xd0078
195 #define CCM_REG_N_SM_CTX_LD_12 0xd007c
196 #define CCM_REG_N_SM_CTX_LD_13 0xd0080
197 #define CCM_REG_N_SM_CTX_LD_14 0xd0084
198 #define CCM_REG_N_SM_CTX_LD_15 0xd0088
199 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
200 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
201 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
202 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
203 acknowledge output is deasserted; all other signals are treated as usual;
204 if 1 - normal activity. */
205 #define CCM_REG_PBF_IFEN 0xd0028
206 /* [RC 1] Set when the message length mismatch (relative to last indication)
207 at the pbf interface is detected. */
208 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
209 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
210 weight 8 (the most prioritised); 1 stands for weight 1(least
211 prioritised); 2 stands for weight 2; tc. */
212 #define CCM_REG_PBF_WEIGHT 0xd00ac
213 #define CCM_REG_PHYS_QNUM1_0 0xd0134
214 #define CCM_REG_PHYS_QNUM1_1 0xd0138
215 #define CCM_REG_PHYS_QNUM2_0 0xd013c
216 #define CCM_REG_PHYS_QNUM2_1 0xd0140
217 #define CCM_REG_PHYS_QNUM3_0 0xd0144
218 #define CCM_REG_PHYS_QNUM3_1 0xd0148
219 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
220 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
221 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
222 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
223 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
224 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
225 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
226 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
227 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
228 disregarded; acknowledge output is deasserted; all other signals are
229 treated as usual; if 1 - normal activity. */
230 #define CCM_REG_STORM_CCM_IFEN 0xd0010
231 /* [RC 1] Set when the message length mismatch (relative to last indication)
232 at the STORM interface is detected. */
233 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
234 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
235 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
236 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
238 #define CCM_REG_STORM_WEIGHT 0xd009c
239 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
240 disregarded; acknowledge output is deasserted; all other signals are
241 treated as usual; if 1 - normal activity. */
242 #define CCM_REG_TSEM_IFEN 0xd001c
243 /* [RC 1] Set when the message length mismatch (relative to last indication)
244 at the tsem interface is detected. */
245 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
246 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
247 weight 8 (the most prioritised); 1 stands for weight 1(least
248 prioritised); 2 stands for weight 2; tc. */
249 #define CCM_REG_TSEM_WEIGHT 0xd00a0
250 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
251 disregarded; acknowledge output is deasserted; all other signals are
252 treated as usual; if 1 - normal activity. */
253 #define CCM_REG_USEM_IFEN 0xd0024
254 /* [RC 1] Set when message length mismatch (relative to last indication) at
255 the usem interface is detected. */
256 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
257 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
258 weight 8 (the most prioritised); 1 stands for weight 1(least
259 prioritised); 2 stands for weight 2; tc. */
260 #define CCM_REG_USEM_WEIGHT 0xd00a8
261 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
262 disregarded; acknowledge output is deasserted; all other signals are
263 treated as usual; if 1 - normal activity. */
264 #define CCM_REG_XSEM_IFEN 0xd0020
265 /* [RC 1] Set when the message length mismatch (relative to last indication)
266 at the xsem interface is detected. */
267 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
268 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
269 weight 8 (the most prioritised); 1 stands for weight 1(least
270 prioritised); 2 stands for weight 2; tc. */
271 #define CCM_REG_XSEM_WEIGHT 0xd00a4
272 /* [RW 19] Indirect access to the descriptor table of the XX protection
273 mechanism. The fields are: [5:0] - message length; [12:6] - message
274 pointer; 18:13] - next pointer. */
275 #define CCM_REG_XX_DESCR_TABLE 0xd0300
276 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
277 /* [R 7] Used to read the value of XX protection Free counter. */
278 #define CCM_REG_XX_FREE 0xd0184
279 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
280 of the Input Stage XX protection buffer by the XX protection pending
281 messages. Max credit available - 127. Write writes the initial credit
282 value; read returns the current value of the credit counter. Must be
283 initialized to maximum XX protected message size - 2 at start-up. */
284 #define CCM_REG_XX_INIT_CRD 0xd0220
285 /* [RW 7] The maximum number of pending messages; which may be stored in XX
286 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
287 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
289 #define CCM_REG_XX_MSG_NUM 0xd0224
290 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
291 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
292 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
293 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
295 #define CCM_REG_XX_TABLE 0xd0280
296 #define CDU_REG_CDU_CHK_MASK0 0x101000
297 #define CDU_REG_CDU_CHK_MASK1 0x101004
298 #define CDU_REG_CDU_CONTROL0 0x101008
299 #define CDU_REG_CDU_DEBUG 0x101010
300 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
301 /* [RW 7] Interrupt mask register #0 read/write */
302 #define CDU_REG_CDU_INT_MASK 0x10103c
303 /* [R 7] Interrupt register #0 read */
304 #define CDU_REG_CDU_INT_STS 0x101030
305 /* [RW 5] Parity mask register #0 read/write */
306 #define CDU_REG_CDU_PRTY_MASK 0x10104c
307 /* [R 5] Parity register #0 read */
308 #define CDU_REG_CDU_PRTY_STS 0x101040
309 /* [RC 32] logging of error data in case of a CDU load error:
310 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
311 ype_error; ctual_active; ctual_compressed_context}; */
312 #define CDU_REG_ERROR_DATA 0x101014
313 /* [WB 216] L1TT ram access. each entry has the following format :
314 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
315 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
316 #define CDU_REG_L1TT 0x101800
317 /* [WB 24] MATT ram access. each entry has the following
318 format:{RegionLength[11:0]; egionOffset[11:0]} */
319 #define CDU_REG_MATT 0x101100
320 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
321 #define CDU_REG_MF_MODE 0x101050
322 /* [R 1] indication the initializing the activity counter by the hardware
324 #define CFC_REG_AC_INIT_DONE 0x104078
325 /* [RW 13] activity counter ram access */
326 #define CFC_REG_ACTIVITY_COUNTER 0x104400
327 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
328 /* [R 1] indication the initializing the cams by the hardware was done. */
329 #define CFC_REG_CAM_INIT_DONE 0x10407c
330 /* [RW 2] Interrupt mask register #0 read/write */
331 #define CFC_REG_CFC_INT_MASK 0x104108
332 /* [R 2] Interrupt register #0 read */
333 #define CFC_REG_CFC_INT_STS 0x1040fc
334 /* [RC 2] Interrupt register #0 read clear */
335 #define CFC_REG_CFC_INT_STS_CLR 0x104100
336 /* [RW 4] Parity mask register #0 read/write */
337 #define CFC_REG_CFC_PRTY_MASK 0x104118
338 /* [R 4] Parity register #0 read */
339 #define CFC_REG_CFC_PRTY_STS 0x10410c
340 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
341 #define CFC_REG_CID_CAM 0x104800
342 #define CFC_REG_CONTROL0 0x104028
343 #define CFC_REG_DEBUG0 0x104050
344 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
345 vector) whether the cfc should be disabled upon it */
346 #define CFC_REG_DISABLE_ON_ERROR 0x104044
347 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
348 set one of these bits. the bit description can be found in CFC
350 #define CFC_REG_ERROR_VECTOR 0x10403c
351 /* [WB 93] LCID info ram access */
352 #define CFC_REG_INFO_RAM 0x105000
353 #define CFC_REG_INFO_RAM_SIZE 1024
354 #define CFC_REG_INIT_REG 0x10404c
355 #define CFC_REG_INTERFACES 0x104058
356 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
357 field allows changing the priorities of the weighted-round-robin arbiter
358 which selects which CFC load client should be served next */
359 #define CFC_REG_LCREQ_WEIGHTS 0x104084
360 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
361 #define CFC_REG_LINK_LIST 0x104c00
362 #define CFC_REG_LINK_LIST_SIZE 256
363 /* [R 1] indication the initializing the link list by the hardware was done. */
364 #define CFC_REG_LL_INIT_DONE 0x104074
365 /* [R 9] Number of allocated LCIDs which are at empty state */
366 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
367 /* [R 9] Number of Arriving LCIDs in Link List Block */
368 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
369 /* [R 9] Number of Leaving LCIDs in Link List Block */
370 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
371 /* [RW 8] The event id for aggregated interrupt 0 */
372 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
373 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
374 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
375 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
376 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
377 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
378 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
379 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
380 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
381 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
382 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
383 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
384 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
385 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
386 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
387 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
388 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
389 or auto-mask-mode (1) */
390 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
391 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
392 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
393 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
394 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
395 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
396 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
397 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
398 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
399 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
400 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
401 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
402 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
403 /* [RW 16] The maximum value of the competion counter #0 */
404 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
405 /* [RW 16] The maximum value of the competion counter #1 */
406 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
407 /* [RW 16] The maximum value of the competion counter #2 */
408 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
409 /* [RW 16] The maximum value of the competion counter #3 */
410 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
411 /* [RW 13] The start address in the internal RAM for the completion
413 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
414 /* [RW 32] Interrupt mask register #0 read/write */
415 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
416 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
417 /* [R 32] Interrupt register #0 read */
418 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
419 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
420 /* [RW 11] Parity mask register #0 read/write */
421 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
422 /* [R 11] Parity register #0 read */
423 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
424 #define CSDM_REG_ENABLE_IN1 0xc2238
425 #define CSDM_REG_ENABLE_IN2 0xc223c
426 #define CSDM_REG_ENABLE_OUT1 0xc2240
427 #define CSDM_REG_ENABLE_OUT2 0xc2244
428 /* [RW 4] The initial number of messages that can be sent to the pxp control
429 interface without receiving any ACK. */
430 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
431 /* [ST 32] The number of ACK after placement messages received */
432 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
433 /* [ST 32] The number of packet end messages received from the parser */
434 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
435 /* [ST 32] The number of requests received from the pxp async if */
436 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
437 /* [ST 32] The number of commands received in queue 0 */
438 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
439 /* [ST 32] The number of commands received in queue 10 */
440 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
441 /* [ST 32] The number of commands received in queue 11 */
442 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
443 /* [ST 32] The number of commands received in queue 1 */
444 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
445 /* [ST 32] The number of commands received in queue 3 */
446 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
447 /* [ST 32] The number of commands received in queue 4 */
448 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
449 /* [ST 32] The number of commands received in queue 5 */
450 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
451 /* [ST 32] The number of commands received in queue 6 */
452 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
453 /* [ST 32] The number of commands received in queue 7 */
454 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
455 /* [ST 32] The number of commands received in queue 8 */
456 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
457 /* [ST 32] The number of commands received in queue 9 */
458 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
459 /* [RW 13] The start address in the internal RAM for queue counters */
460 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
461 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
462 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
463 /* [R 1] parser fifo empty in sdm_sync block */
464 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
465 /* [R 1] parser serial fifo empty in sdm_sync block */
466 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
467 /* [RW 32] Tick for timer counter. Applicable only when
468 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
469 #define CSDM_REG_TIMER_TICK 0xc2000
470 /* [RW 5] The number of time_slots in the arbitration cycle */
471 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
472 /* [RW 3] The source that is associated with arbitration element 0. Source
473 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
474 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
475 #define CSEM_REG_ARB_ELEMENT0 0x200020
476 /* [RW 3] The source that is associated with arbitration element 1. Source
477 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
478 sleeping thread with priority 1; 4- sleeping thread with priority 2.
479 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
480 #define CSEM_REG_ARB_ELEMENT1 0x200024
481 /* [RW 3] The source that is associated with arbitration element 2. Source
482 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
483 sleeping thread with priority 1; 4- sleeping thread with priority 2.
484 Could not be equal to register ~csem_registers_arb_element0.arb_element0
485 and ~csem_registers_arb_element1.arb_element1 */
486 #define CSEM_REG_ARB_ELEMENT2 0x200028
487 /* [RW 3] The source that is associated with arbitration element 3. Source
488 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
489 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
490 not be equal to register ~csem_registers_arb_element0.arb_element0 and
491 ~csem_registers_arb_element1.arb_element1 and
492 ~csem_registers_arb_element2.arb_element2 */
493 #define CSEM_REG_ARB_ELEMENT3 0x20002c
494 /* [RW 3] The source that is associated with arbitration element 4. Source
495 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
496 sleeping thread with priority 1; 4- sleeping thread with priority 2.
497 Could not be equal to register ~csem_registers_arb_element0.arb_element0
498 and ~csem_registers_arb_element1.arb_element1 and
499 ~csem_registers_arb_element2.arb_element2 and
500 ~csem_registers_arb_element3.arb_element3 */
501 #define CSEM_REG_ARB_ELEMENT4 0x200030
502 /* [RW 32] Interrupt mask register #0 read/write */
503 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
504 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
505 /* [R 32] Interrupt register #0 read */
506 #define CSEM_REG_CSEM_INT_STS_0 0x200104
507 #define CSEM_REG_CSEM_INT_STS_1 0x200114
508 /* [RW 32] Parity mask register #0 read/write */
509 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
510 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
511 /* [R 32] Parity register #0 read */
512 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
513 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
514 #define CSEM_REG_ENABLE_IN 0x2000a4
515 #define CSEM_REG_ENABLE_OUT 0x2000a8
516 /* [RW 32] This address space contains all registers and memories that are
517 placed in SEM_FAST block. The SEM_FAST registers are described in
518 appendix B. In order to access the sem_fast registers the base address
519 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
520 #define CSEM_REG_FAST_MEMORY 0x220000
521 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
523 #define CSEM_REG_FIC0_DISABLE 0x200224
524 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
526 #define CSEM_REG_FIC1_DISABLE 0x200234
527 /* [RW 15] Interrupt table Read and write access to it is not possible in
528 the middle of the work */
529 #define CSEM_REG_INT_TABLE 0x200400
530 /* [ST 24] Statistics register. The number of messages that entered through
532 #define CSEM_REG_MSG_NUM_FIC0 0x200000
533 /* [ST 24] Statistics register. The number of messages that entered through
535 #define CSEM_REG_MSG_NUM_FIC1 0x200004
536 /* [ST 24] Statistics register. The number of messages that were sent to
538 #define CSEM_REG_MSG_NUM_FOC0 0x200008
539 /* [ST 24] Statistics register. The number of messages that were sent to
541 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
542 /* [ST 24] Statistics register. The number of messages that were sent to
544 #define CSEM_REG_MSG_NUM_FOC2 0x200010
545 /* [ST 24] Statistics register. The number of messages that were sent to
547 #define CSEM_REG_MSG_NUM_FOC3 0x200014
548 /* [RW 1] Disables input messages from the passive buffer May be updated
549 during run_time by the microcode */
550 #define CSEM_REG_PAS_DISABLE 0x20024c
551 /* [WB 128] Debug only. Passive buffer memory */
552 #define CSEM_REG_PASSIVE_BUFFER 0x202000
553 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
554 #define CSEM_REG_PRAM 0x240000
555 /* [R 16] Valid sleeping threads indication have bit per thread */
556 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
557 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
558 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
559 /* [RW 16] List of free threads . There is a bit per thread. */
560 #define CSEM_REG_THREADS_LIST 0x2002e4
561 /* [RW 3] The arbitration scheme of time_slot 0 */
562 #define CSEM_REG_TS_0_AS 0x200038
563 /* [RW 3] The arbitration scheme of time_slot 10 */
564 #define CSEM_REG_TS_10_AS 0x200060
565 /* [RW 3] The arbitration scheme of time_slot 11 */
566 #define CSEM_REG_TS_11_AS 0x200064
567 /* [RW 3] The arbitration scheme of time_slot 12 */
568 #define CSEM_REG_TS_12_AS 0x200068
569 /* [RW 3] The arbitration scheme of time_slot 13 */
570 #define CSEM_REG_TS_13_AS 0x20006c
571 /* [RW 3] The arbitration scheme of time_slot 14 */
572 #define CSEM_REG_TS_14_AS 0x200070
573 /* [RW 3] The arbitration scheme of time_slot 15 */
574 #define CSEM_REG_TS_15_AS 0x200074
575 /* [RW 3] The arbitration scheme of time_slot 16 */
576 #define CSEM_REG_TS_16_AS 0x200078
577 /* [RW 3] The arbitration scheme of time_slot 17 */
578 #define CSEM_REG_TS_17_AS 0x20007c
579 /* [RW 3] The arbitration scheme of time_slot 18 */
580 #define CSEM_REG_TS_18_AS 0x200080
581 /* [RW 3] The arbitration scheme of time_slot 1 */
582 #define CSEM_REG_TS_1_AS 0x20003c
583 /* [RW 3] The arbitration scheme of time_slot 2 */
584 #define CSEM_REG_TS_2_AS 0x200040
585 /* [RW 3] The arbitration scheme of time_slot 3 */
586 #define CSEM_REG_TS_3_AS 0x200044
587 /* [RW 3] The arbitration scheme of time_slot 4 */
588 #define CSEM_REG_TS_4_AS 0x200048
589 /* [RW 3] The arbitration scheme of time_slot 5 */
590 #define CSEM_REG_TS_5_AS 0x20004c
591 /* [RW 3] The arbitration scheme of time_slot 6 */
592 #define CSEM_REG_TS_6_AS 0x200050
593 /* [RW 3] The arbitration scheme of time_slot 7 */
594 #define CSEM_REG_TS_7_AS 0x200054
595 /* [RW 3] The arbitration scheme of time_slot 8 */
596 #define CSEM_REG_TS_8_AS 0x200058
597 /* [RW 3] The arbitration scheme of time_slot 9 */
598 #define CSEM_REG_TS_9_AS 0x20005c
599 /* [RW 1] Parity mask register #0 read/write */
600 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
601 /* [R 1] Parity register #0 read */
602 #define DBG_REG_DBG_PRTY_STS 0xc09c
603 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
605 #define DMAE_REG_CMD_MEM 0x102400
606 #define DMAE_REG_CMD_MEM_SIZE 224
607 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
608 initial value is all ones. */
609 #define DMAE_REG_CRC16C_INIT 0x10201c
610 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
611 CRC-16 T10 initial value is all ones. */
612 #define DMAE_REG_CRC16T10_INIT 0x102020
613 /* [RW 2] Interrupt mask register #0 read/write */
614 #define DMAE_REG_DMAE_INT_MASK 0x102054
615 /* [RW 4] Parity mask register #0 read/write */
616 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
617 /* [R 4] Parity register #0 read */
618 #define DMAE_REG_DMAE_PRTY_STS 0x102058
619 /* [RW 1] Command 0 go. */
620 #define DMAE_REG_GO_C0 0x102080
621 /* [RW 1] Command 1 go. */
622 #define DMAE_REG_GO_C1 0x102084
623 /* [RW 1] Command 10 go. */
624 #define DMAE_REG_GO_C10 0x102088
625 #define DMAE_REG_GO_C10_SIZE 1
626 /* [RW 1] Command 11 go. */
627 #define DMAE_REG_GO_C11 0x10208c
628 #define DMAE_REG_GO_C11_SIZE 1
629 /* [RW 1] Command 12 go. */
630 #define DMAE_REG_GO_C12 0x102090
631 #define DMAE_REG_GO_C12_SIZE 1
632 /* [RW 1] Command 13 go. */
633 #define DMAE_REG_GO_C13 0x102094
634 #define DMAE_REG_GO_C13_SIZE 1
635 /* [RW 1] Command 14 go. */
636 #define DMAE_REG_GO_C14 0x102098
637 #define DMAE_REG_GO_C14_SIZE 1
638 /* [RW 1] Command 15 go. */
639 #define DMAE_REG_GO_C15 0x10209c
640 #define DMAE_REG_GO_C15_SIZE 1
641 /* [RW 1] Command 10 go. */
642 #define DMAE_REG_GO_C10 0x102088
643 /* [RW 1] Command 11 go. */
644 #define DMAE_REG_GO_C11 0x10208c
645 /* [RW 1] Command 12 go. */
646 #define DMAE_REG_GO_C12 0x102090
647 /* [RW 1] Command 13 go. */
648 #define DMAE_REG_GO_C13 0x102094
649 /* [RW 1] Command 14 go. */
650 #define DMAE_REG_GO_C14 0x102098
651 /* [RW 1] Command 15 go. */
652 #define DMAE_REG_GO_C15 0x10209c
653 /* [RW 1] Command 2 go. */
654 #define DMAE_REG_GO_C2 0x1020a0
655 /* [RW 1] Command 3 go. */
656 #define DMAE_REG_GO_C3 0x1020a4
657 /* [RW 1] Command 4 go. */
658 #define DMAE_REG_GO_C4 0x1020a8
659 /* [RW 1] Command 5 go. */
660 #define DMAE_REG_GO_C5 0x1020ac
661 /* [RW 1] Command 6 go. */
662 #define DMAE_REG_GO_C6 0x1020b0
663 /* [RW 1] Command 7 go. */
664 #define DMAE_REG_GO_C7 0x1020b4
665 /* [RW 1] Command 8 go. */
666 #define DMAE_REG_GO_C8 0x1020b8
667 /* [RW 1] Command 9 go. */
668 #define DMAE_REG_GO_C9 0x1020bc
669 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
670 input is disregarded; valid is deasserted; all other signals are treated
671 as usual; if 1 - normal activity. */
672 #define DMAE_REG_GRC_IFEN 0x102008
673 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
674 acknowledge input is disregarded; valid is deasserted; full is asserted;
675 all other signals are treated as usual; if 1 - normal activity. */
676 #define DMAE_REG_PCI_IFEN 0x102004
677 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
678 initial value to the credit counter; related to the address. Read returns
679 the current value of the counter. */
680 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
681 /* [RW 8] Aggregation command. */
682 #define DORQ_REG_AGG_CMD0 0x170060
683 /* [RW 8] Aggregation command. */
684 #define DORQ_REG_AGG_CMD1 0x170064
685 /* [RW 8] Aggregation command. */
686 #define DORQ_REG_AGG_CMD2 0x170068
687 /* [RW 8] Aggregation command. */
688 #define DORQ_REG_AGG_CMD3 0x17006c
689 /* [RW 28] UCM Header. */
690 #define DORQ_REG_CMHEAD_RX 0x170050
691 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
692 #define DORQ_REG_DB_ADDR0 0x17008c
693 /* [RW 5] Interrupt mask register #0 read/write */
694 #define DORQ_REG_DORQ_INT_MASK 0x170180
695 /* [R 5] Interrupt register #0 read */
696 #define DORQ_REG_DORQ_INT_STS 0x170174
697 /* [RC 5] Interrupt register #0 read clear */
698 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
699 /* [RW 2] Parity mask register #0 read/write */
700 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
701 /* [R 2] Parity register #0 read */
702 #define DORQ_REG_DORQ_PRTY_STS 0x170184
703 /* [RW 8] The address to write the DPM CID to STORM. */
704 #define DORQ_REG_DPM_CID_ADDR 0x170044
705 /* [RW 5] The DPM mode CID extraction offset. */
706 #define DORQ_REG_DPM_CID_OFST 0x170030
707 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
708 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
709 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
710 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
711 /* [R 13] Current value of the DQ FIFO fill level according to following
712 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
714 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
715 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
716 equal to full threshold; reset on full clear. */
717 #define DORQ_REG_DQ_FULL_ST 0x1700c0
718 /* [RW 28] The value sent to CM header in the case of CFC load error. */
719 #define DORQ_REG_ERR_CMHEAD 0x170058
720 #define DORQ_REG_IF_EN 0x170004
721 #define DORQ_REG_MODE_ACT 0x170008
722 /* [RW 5] The normal mode CID extraction offset. */
723 #define DORQ_REG_NORM_CID_OFST 0x17002c
724 /* [RW 28] TCM Header when only TCP context is loaded. */
725 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
726 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
728 #define DORQ_REG_OUTST_REQ 0x17003c
729 #define DORQ_REG_REGN 0x170038
730 /* [R 4] Current value of response A counter credit. Initial credit is
731 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
733 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
734 /* [R 4] Current value of response B counter credit. Initial credit is
735 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
737 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
738 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
739 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
740 read reads this written value. */
741 #define DORQ_REG_RSP_INIT_CRD 0x170048
742 /* [RW 4] Initial activity counter value on the load request; when the
744 #define DORQ_REG_SHRT_ACT_CNT 0x170070
745 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
746 #define DORQ_REG_SHRT_CMHEAD 0x170054
747 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
748 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
749 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
750 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
751 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
752 #define HC_REG_AGG_INT_0 0x108050
753 #define HC_REG_AGG_INT_1 0x108054
754 #define HC_REG_ATTN_BIT 0x108120
755 #define HC_REG_ATTN_IDX 0x108100
756 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
757 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
758 #define HC_REG_ATTN_NUM_P0 0x108038
759 #define HC_REG_ATTN_NUM_P1 0x10803c
760 #define HC_REG_COMMAND_REG 0x108180
761 #define HC_REG_CONFIG_0 0x108000
762 #define HC_REG_CONFIG_1 0x108004
763 #define HC_REG_FUNC_NUM_P0 0x1080ac
764 #define HC_REG_FUNC_NUM_P1 0x1080b0
765 /* [RW 3] Parity mask register #0 read/write */
766 #define HC_REG_HC_PRTY_MASK 0x1080a0
767 /* [R 3] Parity register #0 read */
768 #define HC_REG_HC_PRTY_STS 0x108094
769 #define HC_REG_INT_MASK 0x108108
770 #define HC_REG_LEADING_EDGE_0 0x108040
771 #define HC_REG_LEADING_EDGE_1 0x108048
772 #define HC_REG_P0_PROD_CONS 0x108200
773 #define HC_REG_P1_PROD_CONS 0x108400
774 #define HC_REG_PBA_COMMAND 0x108140
775 #define HC_REG_PCI_CONFIG_0 0x108010
776 #define HC_REG_PCI_CONFIG_1 0x108014
777 #define HC_REG_STATISTIC_COUNTERS 0x109000
778 #define HC_REG_TRAILING_EDGE_0 0x108044
779 #define HC_REG_TRAILING_EDGE_1 0x10804c
780 #define HC_REG_UC_RAM_ADDR_0 0x108028
781 #define HC_REG_UC_RAM_ADDR_1 0x108030
782 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
783 #define HC_REG_VQID_0 0x108008
784 #define HC_REG_VQID_1 0x10800c
785 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
786 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
787 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
788 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
789 #define MCP_REG_MCPR_NVM_READ 0x86410
790 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
791 #define MCP_REG_MCPR_NVM_WRITE 0x86408
792 #define MCP_REG_MCPR_NVM_WRITE1 0x86428
793 #define MCP_REG_MCPR_SCRATCH 0xa0000
794 /* [R 32] read first 32 bit after inversion of function 0. mapped as
795 follows: [0] NIG attention for function0; [1] NIG attention for
796 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
797 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
798 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
799 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
800 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
801 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
802 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
803 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
804 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
805 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
806 Parity error; [31] PBF Hw interrupt; */
807 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
808 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
809 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
810 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
811 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
812 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
813 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
814 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
815 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
816 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
817 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
818 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
819 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
820 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
822 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
823 /* [R 32] read second 32 bit after inversion of function 0. mapped as
824 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
825 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
826 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
827 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
828 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
829 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
830 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
831 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
832 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
833 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
834 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
836 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
837 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
838 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
839 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
840 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
841 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
842 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
843 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
844 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
845 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
846 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
847 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
848 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
849 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
850 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
851 /* [R 32] read third 32 bit after inversion of function 0. mapped as
852 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
853 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
854 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
855 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
856 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
857 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
858 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
859 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
860 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
861 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
862 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
864 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
865 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
866 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
867 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
868 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
869 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
870 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
871 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
872 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
873 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
874 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
875 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
876 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
877 timers attn_4 func1; [30] General attn0; [31] General attn1; */
878 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
879 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
880 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
881 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
882 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
883 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
884 [14] General attn16; [15] General attn17; [16] General attn18; [17]
885 General attn19; [18] General attn20; [19] General attn21; [20] Main power
886 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
887 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
888 Latched timeout attention; [27] GRC Latched reserved access attention;
889 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
890 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
891 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
892 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
893 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
894 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
895 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
896 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
897 General attn13; [12] General attn14; [13] General attn15; [14] General
898 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
899 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
900 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
901 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
902 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
903 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
904 ump_tx_parity; [31] MCP Latched scpad_parity; */
905 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
906 /* [W 14] write to this register results with the clear of the latched
907 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
908 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
909 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
910 GRC Latched reserved access attention; one in d7 clears Latched
911 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
912 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
913 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
914 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
915 from this register return zero */
916 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
917 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
918 as follows: [0] NIG attention for function0; [1] NIG attention for
919 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
920 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
921 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
922 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
923 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
924 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
925 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
926 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
927 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
928 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
929 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
930 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
931 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
932 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
933 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
934 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
935 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
936 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
937 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
938 as follows: [0] NIG attention for function0; [1] NIG attention for
939 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
940 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
941 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
942 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
943 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
944 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
945 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
946 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
947 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
948 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
949 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
950 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
951 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
952 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
953 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
954 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
955 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
956 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
957 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
958 as follows: [0] NIG attention for function0; [1] NIG attention for
959 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
960 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
961 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
962 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
963 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
964 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
965 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
966 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
967 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
968 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
969 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
970 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
971 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
972 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
973 as follows: [0] NIG attention for function0; [1] NIG attention for
974 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
975 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
976 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
977 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
978 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
979 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
980 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
981 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
982 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
983 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
984 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
985 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
986 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
987 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
988 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
989 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
990 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
991 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
992 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
993 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
994 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
995 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
996 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
997 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
998 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1000 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1001 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1002 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1003 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1004 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1005 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1006 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1007 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1008 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1009 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1010 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1011 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1012 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1013 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1015 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1016 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1017 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1018 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1019 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1020 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1021 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1022 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1023 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1024 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1025 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1026 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1027 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1028 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1030 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1031 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1032 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1033 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1034 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1035 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1036 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1037 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1038 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1039 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1040 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1041 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1042 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1043 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1045 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1046 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1047 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1048 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1049 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1050 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1051 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1052 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1053 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1054 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1055 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1056 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1057 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1058 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1060 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1061 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1062 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1063 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1064 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1065 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1066 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1067 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1068 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1069 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1070 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1071 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1072 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1073 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1075 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1076 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1077 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1078 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1079 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1080 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1081 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1082 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1083 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1084 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1085 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1086 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1087 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1088 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1090 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1091 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1092 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1093 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1094 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1095 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1096 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1097 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1098 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1099 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1100 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1101 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1102 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1103 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1105 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1106 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1107 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1108 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1109 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1110 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1111 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1112 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1113 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1114 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1115 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1116 Latched timeout attention; [27] GRC Latched reserved access attention;
1117 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1118 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1119 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1120 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1121 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1122 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1123 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1124 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1125 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1126 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1127 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1128 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1129 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1130 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1131 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1132 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1133 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1134 Latched timeout attention; [27] GRC Latched reserved access attention;
1135 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1136 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1137 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1138 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1139 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1140 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1141 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1142 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1143 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1144 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1145 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1146 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1147 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1148 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1149 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1150 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1151 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1152 Latched timeout attention; [27] GRC Latched reserved access attention;
1153 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1154 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1155 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1156 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1157 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1158 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1159 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1160 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1161 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1162 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1163 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1164 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1165 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1166 Latched timeout attention; [27] GRC Latched reserved access attention;
1167 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1168 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1169 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1170 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1171 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1173 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1174 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1175 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1176 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1177 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1178 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1179 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1180 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1181 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1182 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1183 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1184 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1185 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1186 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1187 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1188 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1189 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1190 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1191 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1192 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1193 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1194 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1195 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1196 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1197 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1198 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1199 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1200 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1201 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1202 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1203 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1204 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1205 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1206 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1207 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1208 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1209 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1210 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1211 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1212 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1213 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1214 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1215 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1216 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1217 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1218 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1219 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1220 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1221 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1222 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1223 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1224 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1225 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1226 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1227 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1228 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1229 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1230 [9:8] = raserved. Zero = mask; one = unmask */
1231 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1232 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1233 /* [RW 1] If set a system kill occurred */
1234 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1235 /* [RW 32] Represent the status of the input vector to the AEU when a system
1236 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1237 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1238 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1239 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1240 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1241 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1242 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1243 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1244 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1245 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1246 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1247 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1249 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1250 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1251 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1252 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1253 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1255 #define MISC_REG_BOND_ID 0xa400
1256 /* [R 8] These bits indicate the metal revision of the chip. This value
1257 starts at 0x00 for each all-layer tape-out and increments by one for each
1259 #define MISC_REG_CHIP_METAL 0xa404
1260 /* [R 16] These bits indicate the part number for the chip. */
1261 #define MISC_REG_CHIP_NUM 0xa408
1262 /* [R 4] These bits indicate the base revision of the chip. This value
1263 starts at 0x0 for the A0 tape-out and increments by one for each
1264 all-layer tape-out. */
1265 #define MISC_REG_CHIP_REV 0xa40c
1266 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1267 32 clients. Each client can be controlled by one driver only. One in each
1268 bit represent that this driver control the appropriate client (Ex: bit 5
1269 is set means this driver control client number 5). addr1 = set; addr0 =
1270 clear; read from both addresses will give the same result = status. write
1271 to address 1 will set a request to control all the clients that their
1272 appropriate bit (in the write command) is set. if the client is free (the
1273 appropriate bit in all the other drivers is clear) one will be written to
1274 that driver register; if the client isn't free the bit will remain zero.
1275 if the appropriate bit is set (the driver request to gain control on a
1276 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1277 interrupt will be asserted). write to address 0 will set a request to
1278 free all the clients that their appropriate bit (in the write command) is
1279 set. if the appropriate bit is clear (the driver request to free a client
1280 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1282 #define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1283 #define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1284 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1285 32 clients. Each client can be controlled by one driver only. One in each
1286 bit represent that this driver control the appropriate client (Ex: bit 5
1287 is set means this driver control client number 5). addr1 = set; addr0 =
1288 clear; read from both addresses will give the same result = status. write
1289 to address 1 will set a request to control all the clients that their
1290 appropriate bit (in the write command) is set. if the client is free (the
1291 appropriate bit in all the other drivers is clear) one will be written to
1292 that driver register; if the client isn't free the bit will remain zero.
1293 if the appropriate bit is set (the driver request to gain control on a
1294 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1295 interrupt will be asserted). write to address 0 will set a request to
1296 free all the clients that their appropriate bit (in the write command) is
1297 set. if the appropriate bit is clear (the driver request to free a client
1298 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1300 #define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1301 #define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1302 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1303 32 clients. Each client can be controlled by one driver only. One in each
1304 bit represent that this driver control the appropriate client (Ex: bit 5
1305 is set means this driver control client number 5). addr1 = set; addr0 =
1306 clear; read from both addresses will give the same result = status. write
1307 to address 1 will set a request to control all the clients that their
1308 appropriate bit (in the write command) is set. if the client is free (the
1309 appropriate bit in all the other drivers is clear) one will be written to
1310 that driver register; if the client isn't free the bit will remain zero.
1311 if the appropriate bit is set (the driver request to gain control on a
1312 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1313 interrupt will be asserted). write to address 0 will set a request to
1314 free all the clients that their appropriate bit (in the write command) is
1315 set. if the appropriate bit is clear (the driver request to free a client
1316 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1318 #define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1319 #define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1320 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1321 32 clients. Each client can be controlled by one driver only. One in each
1322 bit represent that this driver control the appropriate client (Ex: bit 5
1323 is set means this driver control client number 5). addr1 = set; addr0 =
1324 clear; read from both addresses will give the same result = status. write
1325 to address 1 will set a request to control all the clients that their
1326 appropriate bit (in the write command) is set. if the client is free (the
1327 appropriate bit in all the other drivers is clear) one will be written to
1328 that driver register; if the client isn't free the bit will remain zero.
1329 if the appropriate bit is set (the driver request to gain control on a
1330 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1331 interrupt will be asserted). write to address 0 will set a request to
1332 free all the clients that their appropriate bit (in the write command) is
1333 set. if the appropriate bit is clear (the driver request to free a client
1334 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1336 #define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1337 #define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1338 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1339 32 clients. Each client can be controlled by one driver only. One in each
1340 bit represent that this driver control the appropriate client (Ex: bit 5
1341 is set means this driver control client number 5). addr1 = set; addr0 =
1342 clear; read from both addresses will give the same result = status. write
1343 to address 1 will set a request to control all the clients that their
1344 appropriate bit (in the write command) is set. if the client is free (the
1345 appropriate bit in all the other drivers is clear) one will be written to
1346 that driver register; if the client isn't free the bit will remain zero.
1347 if the appropriate bit is set (the driver request to gain control on a
1348 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1349 interrupt will be asserted). write to address 0 will set a request to
1350 free all the clients that their appropriate bit (in the write command) is
1351 set. if the appropriate bit is clear (the driver request to free a client
1352 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1354 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1355 #define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1356 #define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1357 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1358 32 clients. Each client can be controlled by one driver only. One in each
1359 bit represent that this driver control the appropriate client (Ex: bit 5
1360 is set means this driver control client number 5). addr1 = set; addr0 =
1361 clear; read from both addresses will give the same result = status. write
1362 to address 1 will set a request to control all the clients that their
1363 appropriate bit (in the write command) is set. if the client is free (the
1364 appropriate bit in all the other drivers is clear) one will be written to
1365 that driver register; if the client isn't free the bit will remain zero.
1366 if the appropriate bit is set (the driver request to gain control on a
1367 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1368 interrupt will be asserted). write to address 0 will set a request to
1369 free all the clients that their appropriate bit (in the write command) is
1370 set. if the appropriate bit is clear (the driver request to free a client
1371 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1373 #define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1374 #define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1375 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1376 32 clients. Each client can be controlled by one driver only. One in each
1377 bit represent that this driver control the appropriate client (Ex: bit 5
1378 is set means this driver control client number 5). addr1 = set; addr0 =
1379 clear; read from both addresses will give the same result = status. write
1380 to address 1 will set a request to control all the clients that their
1381 appropriate bit (in the write command) is set. if the client is free (the
1382 appropriate bit in all the other drivers is clear) one will be written to
1383 that driver register; if the client isn't free the bit will remain zero.
1384 if the appropriate bit is set (the driver request to gain control on a
1385 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1386 interrupt will be asserted). write to address 0 will set a request to
1387 free all the clients that their appropriate bit (in the write command) is
1388 set. if the appropriate bit is clear (the driver request to free a client
1389 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1391 #define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1392 #define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1393 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1394 32 clients. Each client can be controlled by one driver only. One in each
1395 bit represent that this driver control the appropriate client (Ex: bit 5
1396 is set means this driver control client number 5). addr1 = set; addr0 =
1397 clear; read from both addresses will give the same result = status. write
1398 to address 1 will set a request to control all the clients that their
1399 appropriate bit (in the write command) is set. if the client is free (the
1400 appropriate bit in all the other drivers is clear) one will be written to
1401 that driver register; if the client isn't free the bit will remain zero.
1402 if the appropriate bit is set (the driver request to gain control on a
1403 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1404 interrupt will be asserted). write to address 0 will set a request to
1405 free all the clients that their appropriate bit (in the write command) is
1406 set. if the appropriate bit is clear (the driver request to free a client
1407 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1409 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1410 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1412 #define MISC_REG_E1HMF_MODE 0xa5f8
1413 /* [RW 32] Debug only: spare RW register reset by core reset */
1414 #define MISC_REG_GENERIC_CR_0 0xa460
1415 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1416 these bits is written as a '1'; the corresponding SPIO bit will turn off
1417 it's drivers and become an input. This is the reset state of all GPIO
1418 pins. The read value of these bits will be a '1' if that last command
1419 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1420 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1421 as a '1'; the corresponding GPIO bit will drive low. The read value of
1422 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1423 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1424 SET When any of these bits is written as a '1'; the corresponding GPIO
1425 bit will drive high (if it has that capability). The read value of these
1426 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1427 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1428 RO; These bits indicate the read value of each of the eight GPIO pins.
1429 This is the result value of the pin; not the drive value. Writing these
1430 bits will have not effect. */
1431 #define MISC_REG_GPIO 0xa490
1432 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1433 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1434 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1436 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1437 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1438 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1439 This will acknowledge an interrupt on the falling edge of corresponding
1440 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1441 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1442 register. This will acknowledge an interrupt on the rising edge of
1443 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1444 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1445 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1446 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1447 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1448 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1449 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1450 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1451 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1452 set when the GPIO input does not match the current value in #OLD_VALUE
1454 #define MISC_REG_GPIO_INT 0xa494
1455 /* [R 28] this field hold the last information that caused reserved
1456 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1457 [27:24] the master that caused the attention - according to the following
1458 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1460 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1461 /* [R 28] this field hold the last information that caused timeout
1462 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1463 [27:24] the master that caused the attention - according to the following
1464 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1466 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1467 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1468 access that does not finish within
1469 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1470 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1471 assert it attention output. */
1472 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1473 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1474 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1475 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1476 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1477 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1478 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1479 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1480 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1481 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1482 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1483 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1484 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1485 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1486 connected to RESET input directly. [15] capRetry_en (reset value 0)
1487 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1488 value 0) bit to continuously monitor vco freq (inverted). [17]
1489 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1490 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1491 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1492 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1493 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1494 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1495 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1496 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1497 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1498 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1499 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1501 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1502 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1503 /* [RW 4] Interrupt mask register #0 read/write */
1504 #define MISC_REG_MISC_INT_MASK 0xa388
1505 /* [RW 1] Parity mask register #0 read/write */
1506 #define MISC_REG_MISC_PRTY_MASK 0xa398
1507 /* [R 1] Parity register #0 read */
1508 #define MISC_REG_MISC_PRTY_STS 0xa38c
1509 #define MISC_REG_NIG_WOL_P0 0xa270
1510 #define MISC_REG_NIG_WOL_P1 0xa274
1511 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1513 #define MISC_REG_PCIE_HOT_RESET 0xa618
1514 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1515 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1516 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1517 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1518 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1519 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1520 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1521 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1522 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1523 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1524 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1525 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1526 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1527 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1528 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1529 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1530 testa_en (reset value 0); */
1531 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1532 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1533 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1534 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1535 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1536 write/read zero = the specific block is in reset; addr 0-wr- the write
1537 value will be written to the register; addr 1-set - one will be written
1538 to all the bits that have the value of one in the data written (bits that
1539 have the value of zero will not be change) ; addr 2-clear - zero will be
1540 written to all the bits that have the value of one in the data written
1541 (bits that have the value of zero will not be change); addr 3-ignore;
1542 read ignore from all addr except addr 00; inside order of the bits is:
1543 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1544 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1545 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1546 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1547 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1548 rst_pxp_rq_rd_wr; 31:17] reserved */
1549 #define MISC_REG_RESET_REG_2 0xa590
1550 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1551 shared with the driver resides */
1552 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1553 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1554 the corresponding SPIO bit will turn off it's drivers and become an
1555 input. This is the reset state of all SPIO pins. The read value of these
1556 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1557 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1558 is written as a '1'; the corresponding SPIO bit will drive low. The read
1559 value of these bits will be a '1' if that last command (#SET; #CLR; or
1560 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1561 these bits is written as a '1'; the corresponding SPIO bit will drive
1562 high (if it has that capability). The read value of these bits will be a
1563 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1564 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1565 each of the eight SPIO pins. This is the result value of the pin; not the
1566 drive value. Writing these bits will have not effect. Each 8 bits field
1567 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1568 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1569 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1570 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1571 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1572 select VAUX supply. (This is an output pin only; it is not controlled by
1573 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1574 field is not applicable for this pin; only the VALUE fields is relevant -
1575 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1576 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1577 device ID select; read by UMP firmware. */
1578 #define MISC_REG_SPIO 0xa4fc
1579 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1580 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1582 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1583 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1584 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1585 interrupt on the falling edge of corresponding SPIO input (reset value
1586 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1587 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1588 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1589 RO; These bits indicate the old value of the SPIO input value. When the
1590 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1591 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1592 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1593 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1594 RO; These bits indicate the current SPIO interrupt state for each SPIO
1595 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1596 command bit is written. This bit is set when the SPIO input does not
1597 match the current value in #OLD_VALUE (reset value 0). */
1598 #define MISC_REG_SPIO_INT 0xa500
1599 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1600 the counter reached zero and the reload bit
1601 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1602 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1603 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1604 in this register. addres 0 - timer 1; address - timer 2�address 7 -
1606 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1607 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1608 loaded; 0-prepare; -unprepare */
1609 #define MISC_REG_UNPREPARED 0xa424
1610 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1611 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1612 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1613 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1614 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1615 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1616 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1617 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1618 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1619 /* [RW 1] Input enable for RX_BMAC0 IF */
1620 #define NIG_REG_BMAC0_IN_EN 0x100ac
1621 /* [RW 1] output enable for TX_BMAC0 IF */
1622 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1623 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1624 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1625 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1626 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1627 /* [RW 1] output enable for RX BRB1 port0 IF */
1628 #define NIG_REG_BRB0_OUT_EN 0x100f8
1629 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1630 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1631 /* [RW 1] output enable for RX BRB1 port1 IF */
1632 #define NIG_REG_BRB1_OUT_EN 0x100fc
1633 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1634 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1635 /* [RW 1] output enable for RX BRB1 LP IF */
1636 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1637 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1638 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1639 72:73]-vnic_num; 81:74]-sideband_info */
1640 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1641 /* [RW 1] Input enable for TX Debug packet */
1642 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1643 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1644 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1645 First packet may be deleted from the middle. And last packet will be
1646 always deleted till the end. */
1647 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1648 /* [RW 1] Output enable to EMAC0 */
1649 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1650 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1651 to emac for port0; other way to bmac for port0 */
1652 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1653 /* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1654 #define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
1655 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1656 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1657 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1658 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1659 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1660 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1661 /* [RW 1] Input enable for RX_EMAC0 IF */
1662 #define NIG_REG_EMAC0_IN_EN 0x100a4
1663 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1664 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1665 /* [R 1] status from emac0. This bit is set when MDINT from either the
1666 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1667 be cleared in the attached PHY device that is driving the MINT pin. */
1668 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1669 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1670 are described in appendix A. In order to access the BMAC0 registers; the
1671 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1672 added to each BMAC register offset */
1673 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1674 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1675 are described in appendix A. In order to access the BMAC0 registers; the
1676 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1677 added to each BMAC register offset */
1678 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1679 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1680 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1681 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1682 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1683 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1684 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1685 logic for interrupts must be used. Enable per bit of interrupt of
1686 ~latch_status.latch_status */
1687 #define NIG_REG_LATCH_BC_0 0x16210
1688 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1689 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1690 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1691 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1692 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1693 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1694 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1695 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1696 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1697 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1698 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1699 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1700 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1701 #define NIG_REG_LATCH_STATUS_0 0x18000
1702 /* [RW 1] led 10g for port 0 */
1703 #define NIG_REG_LED_10G_P0 0x10320
1704 /* [RW 1] led 10g for port 1 */
1705 #define NIG_REG_LED_10G_P1 0x10324
1706 /* [RW 1] Port0: This bit is set to enable the use of the
1707 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1708 defined below. If this bit is cleared; then the blink rate will be about
1710 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1711 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1712 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1713 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1714 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1715 /* [RW 1] Port0: If set along with the
1716 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1717 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1718 bit; the Traffic LED will blink with the blink rate specified in
1719 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1720 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1722 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1723 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1724 Traffic LED will then be controlled via bit ~nig_registers_
1725 led_control_traffic_p0.led_control_traffic_p0 and bit
1726 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1727 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1728 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1729 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1730 set; the LED will blink with blink rate specified in
1731 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1732 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1734 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1735 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1736 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1737 #define NIG_REG_LED_MODE_P0 0x102f0
1738 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1739 tsdm enable; b2- usdm enable */
1740 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1741 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
1742 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1743 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1745 #define NIG_REG_LLFC_ENABLE_0 0x16208
1746 /* [RW 16] classes are high-priority for port0 */
1747 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1748 /* [RW 16] classes are low-priority for port0 */
1749 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1750 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1751 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
1752 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1753 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1754 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1755 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1756 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1757 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1758 /* [RW 2] Determine the classification participants. 0: no classification.1:
1759 classification upon VLAN id. 2: classification upon MAC address. 3:
1760 classification upon both VLAN id & MAC addr. */
1761 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1762 /* [RW 32] cm header for llh0 */
1763 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1764 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1765 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1766 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1767 all incoming packets. */
1768 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1769 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1770 all incoming packets. */
1771 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1772 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1773 /* [RW 8] event id for llh0 */
1774 #define NIG_REG_LLH0_EVENT_ID 0x10084
1775 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1776 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1777 /* [RW 1] Determine the IP version to look for in
1778 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1779 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1780 /* [RW 1] t bit for llh0 */
1781 #define NIG_REG_LLH0_T_BIT 0x10074
1782 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1783 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1784 /* [RW 8] init credit counter for port0 in LLH */
1785 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1786 #define NIG_REG_LLH0_XCM_MASK 0x10130
1787 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1788 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1789 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1790 /* [RW 2] Determine the classification participants. 0: no classification.1:
1791 classification upon VLAN id. 2: classification upon MAC address. 3:
1792 classification upon both VLAN id & MAC addr. */
1793 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1794 /* [RW 32] cm header for llh1 */
1795 #define NIG_REG_LLH1_CM_HEADER 0x10080
1796 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1797 /* [RW 8] event id for llh1 */
1798 #define NIG_REG_LLH1_EVENT_ID 0x10088
1799 /* [RW 8] init credit counter for port1 in LLH */
1800 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1801 #define NIG_REG_LLH1_XCM_MASK 0x10134
1802 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1804 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1805 /* [RW 1] When this bit is set; the LLH will classify the packet before
1806 sending it to the BRB or calculating WoL on it. */
1807 #define NIG_REG_LLH_MF_MODE 0x16024
1808 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1809 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1810 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1811 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1812 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1813 #define NIG_REG_NIG_EMAC1_EN 0x10040
1814 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1815 EMAC0 to strip the CRC from the ingress packets. */
1816 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1817 /* [R 32] Interrupt register #0 read */
1818 #define NIG_REG_NIG_INT_STS_0 0x103b0
1819 #define NIG_REG_NIG_INT_STS_1 0x103c0
1820 /* [R 32] Parity register #0 read */
1821 #define NIG_REG_NIG_PRTY_STS 0x103d0
1822 /* [RW 1] Pause enable for port0. This register may get 1 only when
1823 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1825 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
1826 /* [RW 1] Input enable for RX PBF LP IF */
1827 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1828 /* [RW 1] Value of this register will be transmitted to port swap when
1829 ~nig_registers_strap_override.strap_override =1 */
1830 #define NIG_REG_PORT_SWAP 0x10394
1831 /* [RW 1] output enable for RX parser descriptor IF */
1832 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1833 /* [RW 1] Input enable for RX parser request IF */
1834 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1835 /* [RW 5] control to serdes - CL45 DEVAD */
1836 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
1837 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
1838 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
1839 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1840 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1841 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1842 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1843 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1845 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1846 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1848 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1849 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1850 between 1024 and 1522 bytes for port0 */
1851 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1852 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1853 between 1523 bytes and above for port0 */
1854 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1855 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1857 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1858 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1859 between 1024 and 1522 bytes for port1 */
1860 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1861 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1862 between 1523 bytes and above for port1 */
1863 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1864 /* [WB_R 64] Rx statistics : User octets received for LP */
1865 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1866 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1867 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1868 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1869 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1870 ort swap is equal to ~nig_registers_port_swap.port_swap */
1871 #define NIG_REG_STRAP_OVERRIDE 0x10398
1872 /* [RW 1] output enable for RX_XCM0 IF */
1873 #define NIG_REG_XCM0_OUT_EN 0x100f0
1874 /* [RW 1] output enable for RX_XCM1 IF */
1875 #define NIG_REG_XCM1_OUT_EN 0x100f4
1876 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
1877 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
1878 /* [RW 5] control to xgxs - CL45 DEVAD */
1879 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1880 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1881 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
1882 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1883 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1884 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1885 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1886 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1887 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1888 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1889 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1890 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1891 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1892 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
1893 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1894 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1895 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1896 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1897 /* [RW 1] Disable processing further tasks from port 0 (after ending the
1898 current task in process). */
1899 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1900 /* [RW 1] Disable processing further tasks from port 1 (after ending the
1901 current task in process). */
1902 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1903 /* [RW 1] Disable processing further tasks from port 4 (after ending the
1904 current task in process). */
1905 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1906 #define PBF_REG_IF_ENABLE_REG 0x140044
1907 /* [RW 1] Init bit. When set the initial credits are copied to the credit
1908 registers (except the port credits). Should be set and then reset after
1909 the configuration of the block has ended. */
1910 #define PBF_REG_INIT 0x140000
1911 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1912 copied to the credit register. Should be set and then reset after the
1913 configuration of the port has ended. */
1914 #define PBF_REG_INIT_P0 0x140004
1915 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1916 copied to the credit register. Should be set and then reset after the
1917 configuration of the port has ended. */
1918 #define PBF_REG_INIT_P1 0x140008
1919 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1920 copied to the credit register. Should be set and then reset after the
1921 configuration of the port has ended. */
1922 #define PBF_REG_INIT_P4 0x14000c
1923 /* [RW 1] Enable for mac interface 0. */
1924 #define PBF_REG_MAC_IF0_ENABLE 0x140030
1925 /* [RW 1] Enable for mac interface 1. */
1926 #define PBF_REG_MAC_IF1_ENABLE 0x140034
1927 /* [RW 1] Enable for the loopback interface. */
1928 #define PBF_REG_MAC_LB_ENABLE 0x140040
1929 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1931 #define PBF_REG_P0_ARB_THRSH 0x1400e4
1932 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1933 #define PBF_REG_P0_CREDIT 0x140200
1934 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1936 #define PBF_REG_P0_INIT_CRD 0x1400d0
1937 /* [RW 1] Indication that pause is enabled for port 0. */
1938 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
1939 /* [R 8] Number of tasks in port 0 task queue. */
1940 #define PBF_REG_P0_TASK_CNT 0x140204
1941 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1942 #define PBF_REG_P1_CREDIT 0x140208
1943 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1945 #define PBF_REG_P1_INIT_CRD 0x1400d4
1946 /* [R 8] Number of tasks in port 1 task queue. */
1947 #define PBF_REG_P1_TASK_CNT 0x14020c
1948 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1949 #define PBF_REG_P4_CREDIT 0x140210
1950 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1952 #define PBF_REG_P4_INIT_CRD 0x1400e0
1953 /* [R 8] Number of tasks in port 4 task queue. */
1954 #define PBF_REG_P4_TASK_CNT 0x140214
1955 /* [RW 5] Interrupt mask register #0 read/write */
1956 #define PBF_REG_PBF_INT_MASK 0x1401d4
1957 /* [R 5] Interrupt register #0 read */
1958 #define PBF_REG_PBF_INT_STS 0x1401c8
1959 #define PB_REG_CONTROL 0
1960 /* [RW 2] Interrupt mask register #0 read/write */
1961 #define PB_REG_PB_INT_MASK 0x28
1962 /* [R 2] Interrupt register #0 read */
1963 #define PB_REG_PB_INT_STS 0x1c
1964 /* [RW 4] Parity mask register #0 read/write */
1965 #define PB_REG_PB_PRTY_MASK 0x38
1966 /* [R 4] Parity register #0 read */
1967 #define PB_REG_PB_PRTY_STS 0x2c
1968 #define PRS_REG_A_PRSU_20 0x40134
1969 /* [R 8] debug only: CFC load request current credit. Transaction based. */
1970 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1971 /* [R 8] debug only: CFC search request current credit. Transaction based. */
1972 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1973 /* [RW 6] The initial credit for the search message to the CFC interface.
1974 Credit is transaction based. */
1975 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1976 /* [RW 24] CID for port 0 if no match */
1977 #define PRS_REG_CID_PORT_0 0x400fc
1978 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1979 load response is reset and packet type is 0. Used in packet start message
1981 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1982 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1983 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1984 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1985 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1986 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
1987 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1988 load response is set and packet type is 0. Used in packet start message
1990 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1991 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1992 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1993 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1994 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1995 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
1996 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
1997 Used in packet start message to TCM. */
1998 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1999 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2000 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2001 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2002 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
2004 #define PRS_REG_CM_HDR_TYPE_0 0x40078
2005 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
2006 #define PRS_REG_CM_HDR_TYPE_2 0x40080
2007 #define PRS_REG_CM_HDR_TYPE_3 0x40084
2008 #define PRS_REG_CM_HDR_TYPE_4 0x40088
2009 /* [RW 32] The CM header in case there was not a match on the connection */
2010 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
2011 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2012 #define PRS_REG_E1HOV_MODE 0x401c8
2013 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2014 start message to TCM. */
2015 #define PRS_REG_EVENT_ID_1 0x40054
2016 #define PRS_REG_EVENT_ID_2 0x40058
2017 #define PRS_REG_EVENT_ID_3 0x4005c
2018 /* [RW 16] The Ethernet type value for FCoE */
2019 #define PRS_REG_FCOE_TYPE 0x401d0
2020 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2021 load request message. */
2022 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2023 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2024 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2025 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2026 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2027 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2028 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2029 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
2030 /* [RW 4] The increment value to send in the CFC load request message */
2031 #define PRS_REG_INC_VALUE 0x40048
2032 /* [RW 1] If set indicates not to send messages to CFC on received packets */
2033 #define PRS_REG_NIC_MODE 0x40138
2034 /* [RW 8] The 8-bit event ID for cases where there is no match on the
2035 connection. Used in packet start message to TCM. */
2036 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2037 /* [ST 24] The number of input CFC flush packets */
2038 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2039 /* [ST 32] The number of cycles the Parser halted its operation since it
2040 could not allocate the next serial number */
2041 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2042 /* [ST 24] The number of input packets */
2043 #define PRS_REG_NUM_OF_PACKETS 0x40124
2044 /* [ST 24] The number of input transparent flush packets */
2045 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2046 /* [RW 8] Context region for received Ethernet packet with a match and
2047 packet type 0. Used in CFC load request message */
2048 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2049 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2050 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2051 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2052 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2053 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2054 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2055 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2056 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
2057 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2058 /* [R 2] debug only: Number of pending requests for header parsing. */
2059 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2060 /* [R 1] Interrupt register #0 read */
2061 #define PRS_REG_PRS_INT_STS 0x40188
2062 /* [RW 8] Parity mask register #0 read/write */
2063 #define PRS_REG_PRS_PRTY_MASK 0x401a4
2064 /* [R 8] Parity register #0 read */
2065 #define PRS_REG_PRS_PRTY_STS 0x40198
2066 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2068 #define PRS_REG_PURE_REGIONS 0x40024
2069 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2070 serail number was released by SDM but cannot be used because a previous
2071 serial number was not released. */
2072 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2073 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2074 serail number was released by SDM but cannot be used because a previous
2075 serial number was not released. */
2076 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2077 /* [R 4] debug only: SRC current credit. Transaction based. */
2078 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2079 /* [R 8] debug only: TCM current credit. Cycle based. */
2080 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2081 /* [R 8] debug only: TSDM current credit. Transaction based. */
2082 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2083 /* [R 6] Debug only: Number of used entries in the data FIFO */
2084 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2085 /* [R 7] Debug only: Number of used entries in the header FIFO */
2086 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
2087 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
2088 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2089 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2090 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
2091 #define PXP2_REG_PGL_CONTROL0 0x120490
2092 #define PXP2_REG_PGL_CONTROL1 0x120514
2093 #define PXP2_REG_PGL_DEBUG 0x120520
2094 /* [RW 32] third dword data of expansion rom request. this register is
2095 special. reading from it provides a vector outstanding read requests. if
2096 a bit is zero it means that a read request on the corresponding tag did
2097 not finish yet (not all completions have arrived for it) */
2098 #define PXP2_REG_PGL_EXP_ROM2 0x120808
2099 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2100 its[15:0]-address */
2101 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2102 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2103 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2104 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
2105 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
2106 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
2107 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2108 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
2109 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2110 its[15:0]-address */
2111 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
2112 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
2113 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2114 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2115 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2116 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2117 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2118 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2119 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2120 its[15:0]-address */
2121 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2122 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2123 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2124 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2125 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2126 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2127 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2128 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2129 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2130 its[15:0]-address */
2131 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2132 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2133 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2134 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2135 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2136 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2137 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2138 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2139 /* [RW 3] this field allows one function to pretend being another function
2140 when accessing any BAR mapped resource within the device. the value of
2141 the field is the number of the function that will be accessed
2142 effectively. after software write to this bit it must read it in order to
2143 know that the new value is updated */
2144 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
2145 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
2146 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
2147 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
2148 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
2149 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
2150 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
2151 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
2152 /* [R 1] this bit indicates that a read request was blocked because of
2153 bus_master_en was deasserted */
2154 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
2155 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
2156 /* [R 18] debug only */
2157 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
2158 /* [R 1] this bit indicates that a write request was blocked because of
2159 bus_master_en was deasserted */
2160 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2161 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2162 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2163 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2164 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2165 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2166 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2167 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2168 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2169 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2170 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2171 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2172 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2173 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2174 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2175 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2176 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2177 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2178 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2179 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2180 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2181 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2182 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2183 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2184 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2185 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2186 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2187 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2188 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2189 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2190 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2191 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2192 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2193 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2194 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2195 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2196 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2197 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2198 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2199 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2200 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2201 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2202 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2203 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2204 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2205 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2206 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2207 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2208 /* [RW 32] Interrupt mask register #0 read/write */
2209 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2210 /* [R 32] Interrupt register #0 read */
2211 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2212 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2213 /* [RC 32] Interrupt register #0 read clear */
2214 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2215 /* [RW 32] Parity mask register #0 read/write */
2216 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2217 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2218 /* [R 32] Parity register #0 read */
2219 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2220 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2221 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2222 indication about backpressure) */
2223 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2224 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2225 #define PXP2_REG_RD_BLK_CNT 0x120418
2226 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2227 Must be bigger than 6. Normally should not be changed. */
2228 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2229 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2230 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2231 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2232 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2233 /* [R 1] PSWRD internal memories initialization is done */
2234 #define PXP2_REG_RD_INIT_DONE 0x120370
2235 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2236 allocated for vq10 */
2237 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2238 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2239 allocated for vq11 */
2240 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2241 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2242 allocated for vq17 */
2243 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2244 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2245 allocated for vq18 */
2246 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2247 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2248 allocated for vq19 */
2249 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2250 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2251 allocated for vq22 */
2252 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2253 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2254 allocated for vq25 */
2255 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
2256 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2257 allocated for vq6 */
2258 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2259 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2260 allocated for vq9 */
2261 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2262 /* [RW 2] PBF byte swapping mode configuration for master read requests */
2263 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2264 /* [R 1] Debug only: Indication if delivery ports are idle */
2265 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2266 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2267 /* [RW 2] QM byte swapping mode configuration for master read requests */
2268 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2269 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
2270 #define PXP2_REG_RD_SR_CNT 0x120414
2271 /* [RW 2] SRC byte swapping mode configuration for master read requests */
2272 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2273 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2274 be bigger than 1. Normally should not be changed. */
2275 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
2276 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
2277 #define PXP2_REG_RD_START_INIT 0x12036c
2278 /* [RW 2] TM byte swapping mode configuration for master read requests */
2279 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2280 /* [RW 10] Bandwidth addition to VQ0 write requests */
2281 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2282 /* [RW 10] Bandwidth addition to VQ12 read requests */
2283 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2284 /* [RW 10] Bandwidth addition to VQ13 read requests */
2285 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2286 /* [RW 10] Bandwidth addition to VQ14 read requests */
2287 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2288 /* [RW 10] Bandwidth addition to VQ15 read requests */
2289 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2290 /* [RW 10] Bandwidth addition to VQ16 read requests */
2291 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2292 /* [RW 10] Bandwidth addition to VQ17 read requests */
2293 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2294 /* [RW 10] Bandwidth addition to VQ18 read requests */
2295 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2296 /* [RW 10] Bandwidth addition to VQ19 read requests */
2297 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2298 /* [RW 10] Bandwidth addition to VQ20 read requests */
2299 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2300 /* [RW 10] Bandwidth addition to VQ22 read requests */
2301 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2302 /* [RW 10] Bandwidth addition to VQ23 read requests */
2303 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2304 /* [RW 10] Bandwidth addition to VQ24 read requests */
2305 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2306 /* [RW 10] Bandwidth addition to VQ25 read requests */
2307 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2308 /* [RW 10] Bandwidth addition to VQ26 read requests */
2309 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2310 /* [RW 10] Bandwidth addition to VQ27 read requests */
2311 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2312 /* [RW 10] Bandwidth addition to VQ4 read requests */
2313 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2314 /* [RW 10] Bandwidth addition to VQ5 read requests */
2315 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2316 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2317 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2318 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2319 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2320 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2321 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2322 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2323 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2324 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2325 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2326 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2327 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2328 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2329 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2330 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2331 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2332 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2333 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2334 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2335 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2336 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2337 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2338 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2339 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2340 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2341 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2342 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2343 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2344 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2345 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2346 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2347 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2348 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2349 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2350 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2351 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2352 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2353 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2354 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2355 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2356 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2357 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2358 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2359 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2360 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2361 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2362 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2363 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2364 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2365 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2366 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2367 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2368 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2369 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2370 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2371 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2372 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2373 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2374 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2375 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2376 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2377 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2378 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2379 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2380 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2381 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2382 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2383 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2384 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2385 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2386 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2387 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2388 /* [RW 10] Bandwidth addition to VQ29 write requests */
2389 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2390 /* [RW 10] Bandwidth addition to VQ30 write requests */
2391 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2392 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2393 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2394 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2395 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2396 /* [RW 7] Bandwidth upper bound for VQ29 */
2397 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2398 /* [RW 7] Bandwidth upper bound for VQ30 */
2399 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2400 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2401 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2402 /* [RW 2] Endian mode for cdu */
2403 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2404 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2405 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2406 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2408 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2409 /* [R 1] 1' indicates that the requester has finished its internal
2411 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2412 /* [RW 2] Endian mode for debug */
2413 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2414 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2416 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2417 /* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2418 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2419 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2421 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2422 /* [RW 2] Endian mode for hc */
2423 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2424 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2425 compatibility needs; Note that different registers are used per mode */
2426 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
2427 /* [WB 53] Onchip address table */
2428 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2429 /* [WB 53] Onchip address table - B0 */
2430 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2431 /* [RW 13] Pending read limiter threshold; in Dwords */
2432 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2433 /* [RW 2] Endian mode for qm */
2434 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2435 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2436 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2437 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2439 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2440 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2441 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2442 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2443 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2444 #define PXP2_REG_RQ_RD_MBS0 0x120160
2445 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2446 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2447 #define PXP2_REG_RQ_RD_MBS1 0x120168
2448 /* [RW 2] Endian mode for src */
2449 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2450 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2451 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2452 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2454 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2455 /* [RW 2] Endian mode for tm */
2456 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2457 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2458 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2459 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2461 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2462 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2463 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2464 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2465 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2466 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2467 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2468 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2469 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2470 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2471 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2472 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2473 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2474 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2475 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2476 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2477 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2478 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2479 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2480 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2481 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2482 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2483 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2484 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2485 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2486 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2487 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2488 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2489 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2490 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2491 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2492 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2493 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2494 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2495 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2496 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2497 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2498 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2499 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2500 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2501 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2502 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2503 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2504 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2505 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2506 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2507 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2508 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2509 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2510 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2511 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2512 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2513 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2514 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2515 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2516 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2517 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2518 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2519 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2520 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2521 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2522 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2523 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2524 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2525 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2526 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2527 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2528 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2529 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2530 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2531 001:256B; 010: 512B; */
2532 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2533 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2534 001:256B; 010: 512B; */
2535 #define PXP2_REG_RQ_WR_MBS1 0x120164
2536 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2537 buffer reaches this number has_payload will be asserted */
2538 #define PXP2_REG_WR_CDU_MPS 0x1205f0
2539 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2540 buffer reaches this number has_payload will be asserted */
2541 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
2542 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2543 buffer reaches this number has_payload will be asserted */
2544 #define PXP2_REG_WR_DBG_MPS 0x1205e8
2545 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2546 buffer reaches this number has_payload will be asserted */
2547 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
2548 /* [RW 10] if Number of entries in dmae fifo will be higher than this
2549 threshold then has_payload indication will be asserted; the default value
2550 should be equal to > write MBS size! */
2551 #define PXP2_REG_WR_DMAE_TH 0x120368
2552 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2553 buffer reaches this number has_payload will be asserted */
2554 #define PXP2_REG_WR_HC_MPS 0x1205c8
2555 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2556 buffer reaches this number has_payload will be asserted */
2557 #define PXP2_REG_WR_QM_MPS 0x1205dc
2558 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2559 #define PXP2_REG_WR_REV_MODE 0x120670
2560 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2561 buffer reaches this number has_payload will be asserted */
2562 #define PXP2_REG_WR_SRC_MPS 0x1205e4
2563 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2564 buffer reaches this number has_payload will be asserted */
2565 #define PXP2_REG_WR_TM_MPS 0x1205e0
2566 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2567 buffer reaches this number has_payload will be asserted */
2568 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
2569 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
2570 threshold then has_payload indication will be asserted; the default value
2571 should be equal to > write MBS size! */
2572 #define PXP2_REG_WR_USDMDP_TH 0x120348
2573 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2574 buffer reaches this number has_payload will be asserted */
2575 #define PXP2_REG_WR_USDM_MPS 0x1205cc
2576 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2577 buffer reaches this number has_payload will be asserted */
2578 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
2579 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2580 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2581 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2582 this client is waiting for the arbiter. */
2583 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2584 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2585 should update accoring to 'hst_discard_doorbells' register when the state
2587 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2588 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2589 means this PSWHST is discarding inputs from this client. Each bit should
2590 update accoring to 'hst_discard_internal_writes' register when the state
2592 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
2593 /* [WB 160] Used for initialization of the inbound interrupts memory */
2594 #define PXP_REG_HST_INBOUND_INT 0x103800
2595 /* [RW 32] Interrupt mask register #0 read/write */
2596 #define PXP_REG_PXP_INT_MASK_0 0x103074
2597 #define PXP_REG_PXP_INT_MASK_1 0x103084
2598 /* [R 32] Interrupt register #0 read */
2599 #define PXP_REG_PXP_INT_STS_0 0x103068
2600 #define PXP_REG_PXP_INT_STS_1 0x103078
2601 /* [RC 32] Interrupt register #0 read clear */
2602 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2603 /* [RW 26] Parity mask register #0 read/write */
2604 #define PXP_REG_PXP_PRTY_MASK 0x103094
2605 /* [R 26] Parity register #0 read */
2606 #define PXP_REG_PXP_PRTY_STS 0x103088
2607 /* [RW 4] The activity counter initial increment value sent in the load
2609 #define QM_REG_ACTCTRINITVAL_0 0x168040
2610 #define QM_REG_ACTCTRINITVAL_1 0x168044
2611 #define QM_REG_ACTCTRINITVAL_2 0x168048
2612 #define QM_REG_ACTCTRINITVAL_3 0x16804c
2613 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2614 index I represents the physical queue number. The 12 lsbs are ignore and
2615 considered zero so practically there are only 20 bits in this register;
2617 #define QM_REG_BASEADDR 0x168900
2618 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2619 index I represents the physical queue number. The 12 lsbs are ignore and
2620 considered zero so practically there are only 20 bits in this register;
2622 #define QM_REG_BASEADDR_EXT_A 0x16e100
2623 /* [RW 16] The byte credit cost for each task. This value is for both ports */
2624 #define QM_REG_BYTECRDCOST 0x168234
2625 /* [RW 16] The initial byte credit value for both ports. */
2626 #define QM_REG_BYTECRDINITVAL 0x168238
2627 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2628 queue uses port 0 else it uses port 1; queues 31-0 */
2629 #define QM_REG_BYTECRDPORT_LSB 0x168228
2630 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2631 queue uses port 0 else it uses port 1; queues 95-64 */
2632 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2633 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2634 queue uses port 0 else it uses port 1; queues 63-32 */
2635 #define QM_REG_BYTECRDPORT_MSB 0x168224
2636 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2637 queue uses port 0 else it uses port 1; queues 127-96 */
2638 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
2639 /* [RW 16] The byte credit value that if above the QM is considered almost
2641 #define QM_REG_BYTECREDITAFULLTHR 0x168094
2642 /* [RW 4] The initial credit for interface */
2643 #define QM_REG_CMINITCRD_0 0x1680cc
2644 #define QM_REG_CMINITCRD_1 0x1680d0
2645 #define QM_REG_CMINITCRD_2 0x1680d4
2646 #define QM_REG_CMINITCRD_3 0x1680d8
2647 #define QM_REG_CMINITCRD_4 0x1680dc
2648 #define QM_REG_CMINITCRD_5 0x1680e0
2649 #define QM_REG_CMINITCRD_6 0x1680e4
2650 #define QM_REG_CMINITCRD_7 0x1680e8
2651 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2653 #define QM_REG_CMINTEN 0x1680ec
2654 /* [RW 12] A bit vector which indicates which one of the queues are tied to
2656 #define QM_REG_CMINTVOQMASK_0 0x1681f4
2657 #define QM_REG_CMINTVOQMASK_1 0x1681f8
2658 #define QM_REG_CMINTVOQMASK_2 0x1681fc
2659 #define QM_REG_CMINTVOQMASK_3 0x168200
2660 #define QM_REG_CMINTVOQMASK_4 0x168204
2661 #define QM_REG_CMINTVOQMASK_5 0x168208
2662 #define QM_REG_CMINTVOQMASK_6 0x16820c
2663 #define QM_REG_CMINTVOQMASK_7 0x168210
2664 /* [RW 20] The number of connections divided by 16 which dictates the size
2665 of each queue which belongs to even function number. */
2666 #define QM_REG_CONNNUM_0 0x168020
2667 /* [R 6] Keep the fill level of the fifo from write client 4 */
2668 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
2669 /* [RW 8] The context regions sent in the CFC load request */
2670 #define QM_REG_CTXREG_0 0x168030
2671 #define QM_REG_CTXREG_1 0x168034
2672 #define QM_REG_CTXREG_2 0x168038
2673 #define QM_REG_CTXREG_3 0x16803c
2674 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2676 #define QM_REG_ENBYPVOQMASK 0x16823c
2677 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2678 physical queue uses the byte credit; queues 31-0 */
2679 #define QM_REG_ENBYTECRD_LSB 0x168220
2680 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2681 physical queue uses the byte credit; queues 95-64 */
2682 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2683 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2684 physical queue uses the byte credit; queues 63-32 */
2685 #define QM_REG_ENBYTECRD_MSB 0x16821c
2686 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2687 physical queue uses the byte credit; queues 127-96 */
2688 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
2689 /* [RW 4] If cleared then the secondary interface will not be served by the
2691 #define QM_REG_ENSEC 0x1680f0
2693 #define QM_REG_FUNCNUMSEL_LSB 0x168230
2695 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
2696 /* [RW 32] A mask register to mask the Almost empty signals which will not
2697 be use for the almost empty indication to the HW block; queues 31:0 */
2698 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
2699 /* [RW 32] A mask register to mask the Almost empty signals which will not
2700 be use for the almost empty indication to the HW block; queues 95-64 */
2701 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2702 /* [RW 32] A mask register to mask the Almost empty signals which will not
2703 be use for the almost empty indication to the HW block; queues 63:32 */
2704 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
2705 /* [RW 32] A mask register to mask the Almost empty signals which will not
2706 be use for the almost empty indication to the HW block; queues 127-96 */
2707 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
2708 /* [RW 4] The number of outstanding request to CFC */
2709 #define QM_REG_OUTLDREQ 0x168804
2710 /* [RC 1] A flag to indicate that overflow error occurred in one of the
2712 #define QM_REG_OVFERROR 0x16805c
2713 /* [RC 7] the Q were the qverflow occurs */
2714 #define QM_REG_OVFQNUM 0x168058
2715 /* [R 16] Pause state for physical queues 15-0 */
2716 #define QM_REG_PAUSESTATE0 0x168410
2717 /* [R 16] Pause state for physical queues 31-16 */
2718 #define QM_REG_PAUSESTATE1 0x168414
2719 /* [R 16] Pause state for physical queues 47-32 */
2720 #define QM_REG_PAUSESTATE2 0x16e684
2721 /* [R 16] Pause state for physical queues 63-48 */
2722 #define QM_REG_PAUSESTATE3 0x16e688
2723 /* [R 16] Pause state for physical queues 79-64 */
2724 #define QM_REG_PAUSESTATE4 0x16e68c
2725 /* [R 16] Pause state for physical queues 95-80 */
2726 #define QM_REG_PAUSESTATE5 0x16e690
2727 /* [R 16] Pause state for physical queues 111-96 */
2728 #define QM_REG_PAUSESTATE6 0x16e694
2729 /* [R 16] Pause state for physical queues 127-112 */
2730 #define QM_REG_PAUSESTATE7 0x16e698
2731 /* [RW 2] The PCI attributes field used in the PCI request. */
2732 #define QM_REG_PCIREQAT 0x168054
2733 /* [R 16] The byte credit of port 0 */
2734 #define QM_REG_PORT0BYTECRD 0x168300
2735 /* [R 16] The byte credit of port 1 */
2736 #define QM_REG_PORT1BYTECRD 0x168304
2737 /* [RW 3] pci function number of queues 15-0 */
2738 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2739 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2740 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2741 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2742 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2743 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2744 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2745 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2746 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2747 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2748 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2749 #define QM_REG_PTRTBL 0x168a00
2750 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2751 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2752 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2753 #define QM_REG_PTRTBL_EXT_A 0x16e200
2754 /* [RW 2] Interrupt mask register #0 read/write */
2755 #define QM_REG_QM_INT_MASK 0x168444
2756 /* [R 2] Interrupt register #0 read */
2757 #define QM_REG_QM_INT_STS 0x168438
2758 /* [RW 12] Parity mask register #0 read/write */
2759 #define QM_REG_QM_PRTY_MASK 0x168454
2760 /* [R 12] Parity register #0 read */
2761 #define QM_REG_QM_PRTY_STS 0x168448
2762 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2763 #define QM_REG_QSTATUS_HIGH 0x16802c
2764 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2765 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
2766 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2767 #define QM_REG_QSTATUS_LOW 0x168028
2768 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2769 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2770 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
2771 #define QM_REG_QTASKCTR_0 0x168308
2772 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
2773 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
2774 /* [RW 4] Queue tied to VOQ */
2775 #define QM_REG_QVOQIDX_0 0x1680f4
2776 #define QM_REG_QVOQIDX_10 0x16811c
2777 #define QM_REG_QVOQIDX_100 0x16e49c
2778 #define QM_REG_QVOQIDX_101 0x16e4a0
2779 #define QM_REG_QVOQIDX_102 0x16e4a4
2780 #define QM_REG_QVOQIDX_103 0x16e4a8
2781 #define QM_REG_QVOQIDX_104 0x16e4ac
2782 #define QM_REG_QVOQIDX_105 0x16e4b0
2783 #define QM_REG_QVOQIDX_106 0x16e4b4
2784 #define QM_REG_QVOQIDX_107 0x16e4b8
2785 #define QM_REG_QVOQIDX_108 0x16e4bc
2786 #define QM_REG_QVOQIDX_109 0x16e4c0
2787 #define QM_REG_QVOQIDX_100 0x16e49c
2788 #define QM_REG_QVOQIDX_101 0x16e4a0
2789 #define QM_REG_QVOQIDX_102 0x16e4a4
2790 #define QM_REG_QVOQIDX_103 0x16e4a8
2791 #define QM_REG_QVOQIDX_104 0x16e4ac
2792 #define QM_REG_QVOQIDX_105 0x16e4b0
2793 #define QM_REG_QVOQIDX_106 0x16e4b4
2794 #define QM_REG_QVOQIDX_107 0x16e4b8
2795 #define QM_REG_QVOQIDX_108 0x16e4bc
2796 #define QM_REG_QVOQIDX_109 0x16e4c0
2797 #define QM_REG_QVOQIDX_11 0x168120
2798 #define QM_REG_QVOQIDX_110 0x16e4c4
2799 #define QM_REG_QVOQIDX_111 0x16e4c8
2800 #define QM_REG_QVOQIDX_112 0x16e4cc
2801 #define QM_REG_QVOQIDX_113 0x16e4d0
2802 #define QM_REG_QVOQIDX_114 0x16e4d4
2803 #define QM_REG_QVOQIDX_115 0x16e4d8
2804 #define QM_REG_QVOQIDX_116 0x16e4dc
2805 #define QM_REG_QVOQIDX_117 0x16e4e0
2806 #define QM_REG_QVOQIDX_118 0x16e4e4
2807 #define QM_REG_QVOQIDX_119 0x16e4e8
2808 #define QM_REG_QVOQIDX_110 0x16e4c4
2809 #define QM_REG_QVOQIDX_111 0x16e4c8
2810 #define QM_REG_QVOQIDX_112 0x16e4cc
2811 #define QM_REG_QVOQIDX_113 0x16e4d0
2812 #define QM_REG_QVOQIDX_114 0x16e4d4
2813 #define QM_REG_QVOQIDX_115 0x16e4d8
2814 #define QM_REG_QVOQIDX_116 0x16e4dc
2815 #define QM_REG_QVOQIDX_117 0x16e4e0
2816 #define QM_REG_QVOQIDX_118 0x16e4e4
2817 #define QM_REG_QVOQIDX_119 0x16e4e8
2818 #define QM_REG_QVOQIDX_12 0x168124
2819 #define QM_REG_QVOQIDX_120 0x16e4ec
2820 #define QM_REG_QVOQIDX_121 0x16e4f0
2821 #define QM_REG_QVOQIDX_122 0x16e4f4
2822 #define QM_REG_QVOQIDX_123 0x16e4f8
2823 #define QM_REG_QVOQIDX_124 0x16e4fc
2824 #define QM_REG_QVOQIDX_125 0x16e500
2825 #define QM_REG_QVOQIDX_126 0x16e504
2826 #define QM_REG_QVOQIDX_127 0x16e508
2827 #define QM_REG_QVOQIDX_120 0x16e4ec
2828 #define QM_REG_QVOQIDX_121 0x16e4f0
2829 #define QM_REG_QVOQIDX_122 0x16e4f4
2830 #define QM_REG_QVOQIDX_123 0x16e4f8
2831 #define QM_REG_QVOQIDX_124 0x16e4fc
2832 #define QM_REG_QVOQIDX_125 0x16e500
2833 #define QM_REG_QVOQIDX_126 0x16e504
2834 #define QM_REG_QVOQIDX_127 0x16e508
2835 #define QM_REG_QVOQIDX_13 0x168128
2836 #define QM_REG_QVOQIDX_14 0x16812c
2837 #define QM_REG_QVOQIDX_15 0x168130
2838 #define QM_REG_QVOQIDX_16 0x168134
2839 #define QM_REG_QVOQIDX_17 0x168138
2840 #define QM_REG_QVOQIDX_21 0x168148
2841 #define QM_REG_QVOQIDX_22 0x16814c
2842 #define QM_REG_QVOQIDX_23 0x168150
2843 #define QM_REG_QVOQIDX_24 0x168154
2844 #define QM_REG_QVOQIDX_25 0x168158
2845 #define QM_REG_QVOQIDX_26 0x16815c
2846 #define QM_REG_QVOQIDX_27 0x168160
2847 #define QM_REG_QVOQIDX_28 0x168164
2848 #define QM_REG_QVOQIDX_29 0x168168
2849 #define QM_REG_QVOQIDX_30 0x16816c
2850 #define QM_REG_QVOQIDX_31 0x168170
2851 #define QM_REG_QVOQIDX_32 0x168174
2852 #define QM_REG_QVOQIDX_33 0x168178
2853 #define QM_REG_QVOQIDX_34 0x16817c
2854 #define QM_REG_QVOQIDX_35 0x168180
2855 #define QM_REG_QVOQIDX_36 0x168184
2856 #define QM_REG_QVOQIDX_37 0x168188
2857 #define QM_REG_QVOQIDX_38 0x16818c
2858 #define QM_REG_QVOQIDX_39 0x168190
2859 #define QM_REG_QVOQIDX_40 0x168194
2860 #define QM_REG_QVOQIDX_41 0x168198
2861 #define QM_REG_QVOQIDX_42 0x16819c
2862 #define QM_REG_QVOQIDX_43 0x1681a0
2863 #define QM_REG_QVOQIDX_44 0x1681a4
2864 #define QM_REG_QVOQIDX_45 0x1681a8
2865 #define QM_REG_QVOQIDX_46 0x1681ac
2866 #define QM_REG_QVOQIDX_47 0x1681b0
2867 #define QM_REG_QVOQIDX_48 0x1681b4
2868 #define QM_REG_QVOQIDX_49 0x1681b8
2869 #define QM_REG_QVOQIDX_5 0x168108
2870 #define QM_REG_QVOQIDX_50 0x1681bc
2871 #define QM_REG_QVOQIDX_51 0x1681c0
2872 #define QM_REG_QVOQIDX_52 0x1681c4
2873 #define QM_REG_QVOQIDX_53 0x1681c8
2874 #define QM_REG_QVOQIDX_54 0x1681cc
2875 #define QM_REG_QVOQIDX_55 0x1681d0
2876 #define QM_REG_QVOQIDX_56 0x1681d4
2877 #define QM_REG_QVOQIDX_57 0x1681d8
2878 #define QM_REG_QVOQIDX_58 0x1681dc
2879 #define QM_REG_QVOQIDX_59 0x1681e0
2880 #define QM_REG_QVOQIDX_50 0x1681bc
2881 #define QM_REG_QVOQIDX_51 0x1681c0
2882 #define QM_REG_QVOQIDX_52 0x1681c4
2883 #define QM_REG_QVOQIDX_53 0x1681c8
2884 #define QM_REG_QVOQIDX_54 0x1681cc
2885 #define QM_REG_QVOQIDX_55 0x1681d0
2886 #define QM_REG_QVOQIDX_56 0x1681d4
2887 #define QM_REG_QVOQIDX_57 0x1681d8
2888 #define QM_REG_QVOQIDX_58 0x1681dc
2889 #define QM_REG_QVOQIDX_59 0x1681e0
2890 #define QM_REG_QVOQIDX_6 0x16810c
2891 #define QM_REG_QVOQIDX_60 0x1681e4
2892 #define QM_REG_QVOQIDX_61 0x1681e8
2893 #define QM_REG_QVOQIDX_62 0x1681ec
2894 #define QM_REG_QVOQIDX_63 0x1681f0
2895 #define QM_REG_QVOQIDX_64 0x16e40c
2896 #define QM_REG_QVOQIDX_65 0x16e410
2897 #define QM_REG_QVOQIDX_66 0x16e414
2898 #define QM_REG_QVOQIDX_67 0x16e418
2899 #define QM_REG_QVOQIDX_68 0x16e41c
2900 #define QM_REG_QVOQIDX_69 0x16e420
2901 #define QM_REG_QVOQIDX_60 0x1681e4
2902 #define QM_REG_QVOQIDX_61 0x1681e8
2903 #define QM_REG_QVOQIDX_62 0x1681ec
2904 #define QM_REG_QVOQIDX_63 0x1681f0
2905 #define QM_REG_QVOQIDX_64 0x16e40c
2906 #define QM_REG_QVOQIDX_65 0x16e410
2907 #define QM_REG_QVOQIDX_69 0x16e420
2908 #define QM_REG_QVOQIDX_7 0x168110
2909 #define QM_REG_QVOQIDX_70 0x16e424
2910 #define QM_REG_QVOQIDX_71 0x16e428
2911 #define QM_REG_QVOQIDX_72 0x16e42c
2912 #define QM_REG_QVOQIDX_73 0x16e430
2913 #define QM_REG_QVOQIDX_74 0x16e434
2914 #define QM_REG_QVOQIDX_75 0x16e438
2915 #define QM_REG_QVOQIDX_76 0x16e43c
2916 #define QM_REG_QVOQIDX_77 0x16e440
2917 #define QM_REG_QVOQIDX_78 0x16e444
2918 #define QM_REG_QVOQIDX_79 0x16e448
2919 #define QM_REG_QVOQIDX_70 0x16e424
2920 #define QM_REG_QVOQIDX_71 0x16e428
2921 #define QM_REG_QVOQIDX_72 0x16e42c
2922 #define QM_REG_QVOQIDX_73 0x16e430
2923 #define QM_REG_QVOQIDX_74 0x16e434
2924 #define QM_REG_QVOQIDX_75 0x16e438
2925 #define QM_REG_QVOQIDX_76 0x16e43c
2926 #define QM_REG_QVOQIDX_77 0x16e440
2927 #define QM_REG_QVOQIDX_78 0x16e444
2928 #define QM_REG_QVOQIDX_79 0x16e448
2929 #define QM_REG_QVOQIDX_8 0x168114
2930 #define QM_REG_QVOQIDX_80 0x16e44c
2931 #define QM_REG_QVOQIDX_81 0x16e450
2932 #define QM_REG_QVOQIDX_82 0x16e454
2933 #define QM_REG_QVOQIDX_83 0x16e458
2934 #define QM_REG_QVOQIDX_84 0x16e45c
2935 #define QM_REG_QVOQIDX_85 0x16e460
2936 #define QM_REG_QVOQIDX_86 0x16e464
2937 #define QM_REG_QVOQIDX_87 0x16e468
2938 #define QM_REG_QVOQIDX_88 0x16e46c
2939 #define QM_REG_QVOQIDX_89 0x16e470
2940 #define QM_REG_QVOQIDX_80 0x16e44c
2941 #define QM_REG_QVOQIDX_81 0x16e450
2942 #define QM_REG_QVOQIDX_85 0x16e460
2943 #define QM_REG_QVOQIDX_86 0x16e464
2944 #define QM_REG_QVOQIDX_87 0x16e468
2945 #define QM_REG_QVOQIDX_88 0x16e46c
2946 #define QM_REG_QVOQIDX_89 0x16e470
2947 #define QM_REG_QVOQIDX_9 0x168118
2948 #define QM_REG_QVOQIDX_90 0x16e474
2949 #define QM_REG_QVOQIDX_91 0x16e478
2950 #define QM_REG_QVOQIDX_92 0x16e47c
2951 #define QM_REG_QVOQIDX_93 0x16e480
2952 #define QM_REG_QVOQIDX_94 0x16e484
2953 #define QM_REG_QVOQIDX_95 0x16e488
2954 #define QM_REG_QVOQIDX_96 0x16e48c
2955 #define QM_REG_QVOQIDX_97 0x16e490
2956 #define QM_REG_QVOQIDX_98 0x16e494
2957 #define QM_REG_QVOQIDX_99 0x16e498
2958 #define QM_REG_QVOQIDX_90 0x16e474
2959 #define QM_REG_QVOQIDX_91 0x16e478
2960 #define QM_REG_QVOQIDX_92 0x16e47c
2961 #define QM_REG_QVOQIDX_93 0x16e480
2962 #define QM_REG_QVOQIDX_94 0x16e484
2963 #define QM_REG_QVOQIDX_95 0x16e488
2964 #define QM_REG_QVOQIDX_96 0x16e48c
2965 #define QM_REG_QVOQIDX_97 0x16e490
2966 #define QM_REG_QVOQIDX_98 0x16e494
2967 #define QM_REG_QVOQIDX_99 0x16e498
2968 /* [RW 1] Initialization bit command */
2969 #define QM_REG_SOFT_RESET 0x168428
2970 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2971 #define QM_REG_TASKCRDCOST_0 0x16809c
2972 #define QM_REG_TASKCRDCOST_1 0x1680a0
2973 #define QM_REG_TASKCRDCOST_10 0x1680c4
2974 #define QM_REG_TASKCRDCOST_11 0x1680c8
2975 #define QM_REG_TASKCRDCOST_2 0x1680a4
2976 #define QM_REG_TASKCRDCOST_4 0x1680ac
2977 #define QM_REG_TASKCRDCOST_5 0x1680b0
2978 /* [R 6] Keep the fill level of the fifo from write client 3 */
2979 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
2980 /* [R 6] Keep the fill level of the fifo from write client 2 */
2981 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
2982 /* [RC 32] Credit update error register */
2983 #define QM_REG_VOQCRDERRREG 0x168408
2984 /* [R 16] The credit value for each VOQ */
2985 #define QM_REG_VOQCREDIT_0 0x1682d0
2986 #define QM_REG_VOQCREDIT_1 0x1682d4
2987 #define QM_REG_VOQCREDIT_10 0x1682f8
2988 #define QM_REG_VOQCREDIT_11 0x1682fc
2989 #define QM_REG_VOQCREDIT_4 0x1682e0
2990 /* [RW 16] The credit value that if above the QM is considered almost full */
2991 #define QM_REG_VOQCREDITAFULLTHR 0x168090
2992 /* [RW 16] The init and maximum credit for each VoQ */
2993 #define QM_REG_VOQINITCREDIT_0 0x168060
2994 #define QM_REG_VOQINITCREDIT_1 0x168064
2995 #define QM_REG_VOQINITCREDIT_10 0x168088
2996 #define QM_REG_VOQINITCREDIT_11 0x16808c
2997 #define QM_REG_VOQINITCREDIT_2 0x168068
2998 #define QM_REG_VOQINITCREDIT_4 0x168070
2999 #define QM_REG_VOQINITCREDIT_5 0x168074
3000 /* [RW 1] The port of which VOQ belongs */
3001 #define QM_REG_VOQPORT_0 0x1682a0
3002 #define QM_REG_VOQPORT_1 0x1682a4
3003 #define QM_REG_VOQPORT_10 0x1682c8
3004 #define QM_REG_VOQPORT_11 0x1682cc
3005 #define QM_REG_VOQPORT_2 0x1682a8
3006 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3007 #define QM_REG_VOQQMASK_0_LSB 0x168240
3008 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3009 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3010 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3011 #define QM_REG_VOQQMASK_0_MSB 0x168244
3012 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3013 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3014 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3015 #define QM_REG_VOQQMASK_10_LSB 0x168290
3016 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3017 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3018 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3019 #define QM_REG_VOQQMASK_10_MSB 0x168294
3020 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3021 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3022 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3023 #define QM_REG_VOQQMASK_11_LSB 0x168298
3024 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3025 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3026 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3027 #define QM_REG_VOQQMASK_11_MSB 0x16829c
3028 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3029 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3030 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3031 #define QM_REG_VOQQMASK_1_LSB 0x168248
3032 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3033 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3034 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3035 #define QM_REG_VOQQMASK_1_MSB 0x16824c
3036 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3037 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3038 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3039 #define QM_REG_VOQQMASK_2_LSB 0x168250
3040 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3041 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3042 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3043 #define QM_REG_VOQQMASK_2_MSB 0x168254
3044 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3045 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3046 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3047 #define QM_REG_VOQQMASK_3_LSB 0x168258
3048 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3049 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3050 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3051 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3052 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3053 #define QM_REG_VOQQMASK_4_LSB 0x168260
3054 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3055 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3056 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3057 #define QM_REG_VOQQMASK_4_MSB 0x168264
3058 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3059 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3060 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3061 #define QM_REG_VOQQMASK_5_LSB 0x168268
3062 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3063 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3064 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3065 #define QM_REG_VOQQMASK_5_MSB 0x16826c
3066 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3067 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3068 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3069 #define QM_REG_VOQQMASK_6_LSB 0x168270
3070 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3071 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3072 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3073 #define QM_REG_VOQQMASK_6_MSB 0x168274
3074 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3075 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3076 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3077 #define QM_REG_VOQQMASK_7_LSB 0x168278
3078 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3079 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3080 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3081 #define QM_REG_VOQQMASK_7_MSB 0x16827c
3082 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3083 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3084 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3085 #define QM_REG_VOQQMASK_8_LSB 0x168280
3086 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3087 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3088 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3089 #define QM_REG_VOQQMASK_8_MSB 0x168284
3090 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3091 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3092 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3093 #define QM_REG_VOQQMASK_9_LSB 0x168288
3094 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3095 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3096 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3097 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3098 /* [RW 32] Wrr weights */
3099 #define QM_REG_WRRWEIGHTS_0 0x16880c
3100 #define QM_REG_WRRWEIGHTS_1 0x168810
3101 #define QM_REG_WRRWEIGHTS_10 0x168814
3102 #define QM_REG_WRRWEIGHTS_10_SIZE 1
3103 /* [RW 32] Wrr weights */
3104 #define QM_REG_WRRWEIGHTS_11 0x168818
3105 #define QM_REG_WRRWEIGHTS_11_SIZE 1
3106 /* [RW 32] Wrr weights */
3107 #define QM_REG_WRRWEIGHTS_12 0x16881c
3108 #define QM_REG_WRRWEIGHTS_12_SIZE 1
3109 /* [RW 32] Wrr weights */
3110 #define QM_REG_WRRWEIGHTS_13 0x168820
3111 #define QM_REG_WRRWEIGHTS_13_SIZE 1
3112 /* [RW 32] Wrr weights */
3113 #define QM_REG_WRRWEIGHTS_14 0x168824
3114 #define QM_REG_WRRWEIGHTS_14_SIZE 1
3115 /* [RW 32] Wrr weights */
3116 #define QM_REG_WRRWEIGHTS_15 0x168828
3117 #define QM_REG_WRRWEIGHTS_15_SIZE 1
3118 /* [RW 32] Wrr weights */
3119 #define QM_REG_WRRWEIGHTS_16 0x16e000
3120 #define QM_REG_WRRWEIGHTS_16_SIZE 1
3121 /* [RW 32] Wrr weights */
3122 #define QM_REG_WRRWEIGHTS_17 0x16e004
3123 #define QM_REG_WRRWEIGHTS_17_SIZE 1
3124 /* [RW 32] Wrr weights */
3125 #define QM_REG_WRRWEIGHTS_18 0x16e008
3126 #define QM_REG_WRRWEIGHTS_18_SIZE 1
3127 /* [RW 32] Wrr weights */
3128 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3129 #define QM_REG_WRRWEIGHTS_19_SIZE 1
3130 /* [RW 32] Wrr weights */
3131 #define QM_REG_WRRWEIGHTS_10 0x168814
3132 #define QM_REG_WRRWEIGHTS_11 0x168818
3133 #define QM_REG_WRRWEIGHTS_12 0x16881c
3134 #define QM_REG_WRRWEIGHTS_13 0x168820
3135 #define QM_REG_WRRWEIGHTS_14 0x168824
3136 #define QM_REG_WRRWEIGHTS_15 0x168828
3137 #define QM_REG_WRRWEIGHTS_16 0x16e000
3138 #define QM_REG_WRRWEIGHTS_17 0x16e004
3139 #define QM_REG_WRRWEIGHTS_18 0x16e008
3140 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3141 #define QM_REG_WRRWEIGHTS_2 0x16882c
3142 #define QM_REG_WRRWEIGHTS_20 0x16e010
3143 #define QM_REG_WRRWEIGHTS_20_SIZE 1
3144 /* [RW 32] Wrr weights */
3145 #define QM_REG_WRRWEIGHTS_21 0x16e014
3146 #define QM_REG_WRRWEIGHTS_21_SIZE 1
3147 /* [RW 32] Wrr weights */
3148 #define QM_REG_WRRWEIGHTS_22 0x16e018
3149 #define QM_REG_WRRWEIGHTS_22_SIZE 1
3150 /* [RW 32] Wrr weights */
3151 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3152 #define QM_REG_WRRWEIGHTS_23_SIZE 1
3153 /* [RW 32] Wrr weights */
3154 #define QM_REG_WRRWEIGHTS_24 0x16e020
3155 #define QM_REG_WRRWEIGHTS_24_SIZE 1
3156 /* [RW 32] Wrr weights */
3157 #define QM_REG_WRRWEIGHTS_25 0x16e024
3158 #define QM_REG_WRRWEIGHTS_25_SIZE 1
3159 /* [RW 32] Wrr weights */
3160 #define QM_REG_WRRWEIGHTS_26 0x16e028
3161 #define QM_REG_WRRWEIGHTS_26_SIZE 1
3162 /* [RW 32] Wrr weights */
3163 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3164 #define QM_REG_WRRWEIGHTS_27_SIZE 1
3165 /* [RW 32] Wrr weights */
3166 #define QM_REG_WRRWEIGHTS_28 0x16e030
3167 #define QM_REG_WRRWEIGHTS_28_SIZE 1
3168 /* [RW 32] Wrr weights */
3169 #define QM_REG_WRRWEIGHTS_29 0x16e034
3170 #define QM_REG_WRRWEIGHTS_29_SIZE 1
3171 /* [RW 32] Wrr weights */
3172 #define QM_REG_WRRWEIGHTS_20 0x16e010
3173 #define QM_REG_WRRWEIGHTS_21 0x16e014
3174 #define QM_REG_WRRWEIGHTS_22 0x16e018
3175 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3176 #define QM_REG_WRRWEIGHTS_24 0x16e020
3177 #define QM_REG_WRRWEIGHTS_25 0x16e024
3178 #define QM_REG_WRRWEIGHTS_26 0x16e028
3179 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3180 #define QM_REG_WRRWEIGHTS_28 0x16e030
3181 #define QM_REG_WRRWEIGHTS_29 0x16e034
3182 #define QM_REG_WRRWEIGHTS_3 0x168830
3183 #define QM_REG_WRRWEIGHTS_30 0x16e038
3184 #define QM_REG_WRRWEIGHTS_30_SIZE 1
3185 /* [RW 32] Wrr weights */
3186 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3187 #define QM_REG_WRRWEIGHTS_31_SIZE 1
3188 /* [RW 32] Wrr weights */
3189 #define QM_REG_WRRWEIGHTS_30 0x16e038
3190 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3191 #define QM_REG_WRRWEIGHTS_4 0x168834
3192 #define QM_REG_WRRWEIGHTS_5 0x168838
3193 #define QM_REG_WRRWEIGHTS_6 0x16883c
3194 #define QM_REG_WRRWEIGHTS_7 0x168840
3195 #define QM_REG_WRRWEIGHTS_8 0x168844
3196 #define QM_REG_WRRWEIGHTS_9 0x168848
3197 /* [R 6] Keep the fill level of the fifo from write client 1 */
3198 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
3199 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3200 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3201 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3202 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3203 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3204 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3205 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3206 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3207 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3208 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3209 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3210 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3211 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3212 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3213 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3214 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3215 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3216 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3217 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3218 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3219 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3220 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3221 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3222 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3223 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3224 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3225 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3226 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3227 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3228 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3229 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3230 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3231 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3232 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3233 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3234 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3235 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3236 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3237 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3238 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3239 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3240 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3241 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3242 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3243 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3244 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3245 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3246 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3247 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3248 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3249 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3250 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3251 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3252 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3253 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3254 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3255 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3256 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3257 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3258 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3259 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3260 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3261 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3262 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3263 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3264 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3265 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3266 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3267 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3268 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3269 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3270 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3271 #define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3272 #define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3273 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3274 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3275 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3276 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3277 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3278 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3279 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3280 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3281 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3282 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3283 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3284 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3285 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3286 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3287 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3288 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3289 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3290 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3291 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3292 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3293 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3294 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3295 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3296 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3297 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3298 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3299 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3300 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3301 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3302 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3303 #define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3304 #define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3305 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3306 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3307 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3308 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3309 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3310 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3311 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3312 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3313 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3314 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3315 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3316 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3317 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3318 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3319 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3320 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3321 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3322 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3323 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3324 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3325 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3326 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3327 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3328 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3329 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3330 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3331 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3332 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3333 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3334 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3335 #define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3336 #define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3337 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3338 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3339 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3340 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3341 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3342 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3343 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3344 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3345 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3346 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3347 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3348 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3349 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3350 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3351 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3352 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3353 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3354 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3355 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3356 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3357 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3358 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3359 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3360 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3361 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3362 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3363 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3364 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3365 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3366 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3367 #define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3368 #define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3369 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3370 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3371 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3372 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3373 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3374 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3375 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3376 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3377 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3378 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3379 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3380 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3381 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3382 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3383 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3384 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3385 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3386 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3387 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3388 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3389 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3390 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3391 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3392 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3393 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3394 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3395 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3396 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3397 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3398 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3399 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3400 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3401 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3402 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3403 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3404 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3405 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3406 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3407 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3408 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3409 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3410 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3411 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3412 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3413 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3414 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3415 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3416 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3417 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3418 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3419 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3420 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3421 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3422 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3423 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3424 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3425 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3426 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3427 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3428 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3429 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3430 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3431 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3432 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3433 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3434 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3435 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3436 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3437 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3438 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3439 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3440 #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
3441 /* [R 1] debug only: This bit indicates whether indicates that external
3442 buffer was wrapped (oldest data was thrown); Relevant only when
3443 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3444 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3445 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
3446 /* [R 1] debug only: This bit indicates whether the internal buffer was
3447 wrapped (oldest data was thrown) Relevant only when
3448 ~dbg_registers_debug_target=0 (internal buffer) */
3449 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
3450 #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
3451 #define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3452 #define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3453 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3454 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3455 #define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3456 #define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3457 #define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3458 #define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
3459 /* [RW 32] Wrr weights */
3460 #define QM_REG_WRRWEIGHTS_0 0x16880c
3461 #define QM_REG_WRRWEIGHTS_0_SIZE 1
3462 /* [RW 32] Wrr weights */
3463 #define QM_REG_WRRWEIGHTS_1 0x168810
3464 #define QM_REG_WRRWEIGHTS_1_SIZE 1
3465 /* [RW 32] Wrr weights */
3466 #define QM_REG_WRRWEIGHTS_10 0x168814
3467 #define QM_REG_WRRWEIGHTS_10_SIZE 1
3468 /* [RW 32] Wrr weights */
3469 #define QM_REG_WRRWEIGHTS_11 0x168818
3470 #define QM_REG_WRRWEIGHTS_11_SIZE 1
3471 /* [RW 32] Wrr weights */
3472 #define QM_REG_WRRWEIGHTS_12 0x16881c
3473 #define QM_REG_WRRWEIGHTS_12_SIZE 1
3474 /* [RW 32] Wrr weights */
3475 #define QM_REG_WRRWEIGHTS_13 0x168820
3476 #define QM_REG_WRRWEIGHTS_13_SIZE 1
3477 /* [RW 32] Wrr weights */
3478 #define QM_REG_WRRWEIGHTS_14 0x168824
3479 #define QM_REG_WRRWEIGHTS_14_SIZE 1
3480 /* [RW 32] Wrr weights */
3481 #define QM_REG_WRRWEIGHTS_15 0x168828
3482 #define QM_REG_WRRWEIGHTS_15_SIZE 1
3483 /* [RW 32] Wrr weights */
3484 #define QM_REG_WRRWEIGHTS_2 0x16882c
3485 #define QM_REG_WRRWEIGHTS_2_SIZE 1
3486 /* [RW 32] Wrr weights */
3487 #define QM_REG_WRRWEIGHTS_3 0x168830
3488 #define QM_REG_WRRWEIGHTS_3_SIZE 1
3489 /* [RW 32] Wrr weights */
3490 #define QM_REG_WRRWEIGHTS_4 0x168834
3491 #define QM_REG_WRRWEIGHTS_4_SIZE 1
3492 /* [RW 32] Wrr weights */
3493 #define QM_REG_WRRWEIGHTS_5 0x168838
3494 #define QM_REG_WRRWEIGHTS_5_SIZE 1
3495 /* [RW 32] Wrr weights */
3496 #define QM_REG_WRRWEIGHTS_6 0x16883c
3497 #define QM_REG_WRRWEIGHTS_6_SIZE 1
3498 /* [RW 32] Wrr weights */
3499 #define QM_REG_WRRWEIGHTS_7 0x168840
3500 #define QM_REG_WRRWEIGHTS_7_SIZE 1
3501 /* [RW 32] Wrr weights */
3502 #define QM_REG_WRRWEIGHTS_8 0x168844
3503 #define QM_REG_WRRWEIGHTS_8_SIZE 1
3504 /* [RW 32] Wrr weights */
3505 #define QM_REG_WRRWEIGHTS_9 0x168848
3506 #define QM_REG_WRRWEIGHTS_9_SIZE 1
3507 /* [RW 32] Wrr weights */
3508 #define QM_REG_WRRWEIGHTS_16 0x16e000
3509 #define QM_REG_WRRWEIGHTS_16_SIZE 1
3510 /* [RW 32] Wrr weights */
3511 #define QM_REG_WRRWEIGHTS_17 0x16e004
3512 #define QM_REG_WRRWEIGHTS_17_SIZE 1
3513 /* [RW 32] Wrr weights */
3514 #define QM_REG_WRRWEIGHTS_18 0x16e008
3515 #define QM_REG_WRRWEIGHTS_18_SIZE 1
3516 /* [RW 32] Wrr weights */
3517 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3518 #define QM_REG_WRRWEIGHTS_19_SIZE 1
3519 /* [RW 32] Wrr weights */
3520 #define QM_REG_WRRWEIGHTS_20 0x16e010
3521 #define QM_REG_WRRWEIGHTS_20_SIZE 1
3522 /* [RW 32] Wrr weights */
3523 #define QM_REG_WRRWEIGHTS_21 0x16e014
3524 #define QM_REG_WRRWEIGHTS_21_SIZE 1
3525 /* [RW 32] Wrr weights */
3526 #define QM_REG_WRRWEIGHTS_22 0x16e018
3527 #define QM_REG_WRRWEIGHTS_22_SIZE 1
3528 /* [RW 32] Wrr weights */
3529 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3530 #define QM_REG_WRRWEIGHTS_23_SIZE 1
3531 /* [RW 32] Wrr weights */
3532 #define QM_REG_WRRWEIGHTS_24 0x16e020
3533 #define QM_REG_WRRWEIGHTS_24_SIZE 1
3534 /* [RW 32] Wrr weights */
3535 #define QM_REG_WRRWEIGHTS_25 0x16e024
3536 #define QM_REG_WRRWEIGHTS_25_SIZE 1
3537 /* [RW 32] Wrr weights */
3538 #define QM_REG_WRRWEIGHTS_26 0x16e028
3539 #define QM_REG_WRRWEIGHTS_26_SIZE 1
3540 /* [RW 32] Wrr weights */
3541 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3542 #define QM_REG_WRRWEIGHTS_27_SIZE 1
3543 /* [RW 32] Wrr weights */
3544 #define QM_REG_WRRWEIGHTS_28 0x16e030
3545 #define QM_REG_WRRWEIGHTS_28_SIZE 1
3546 /* [RW 32] Wrr weights */
3547 #define QM_REG_WRRWEIGHTS_29 0x16e034
3548 #define QM_REG_WRRWEIGHTS_29_SIZE 1
3549 /* [RW 32] Wrr weights */
3550 #define QM_REG_WRRWEIGHTS_30 0x16e038
3551 #define QM_REG_WRRWEIGHTS_30_SIZE 1
3552 /* [RW 32] Wrr weights */
3553 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3554 #define QM_REG_WRRWEIGHTS_31_SIZE 1
3555 #define SRC_REG_COUNTFREE0 0x40500
3556 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3557 ports. If set the searcher support 8 functions. */
3558 #define SRC_REG_E1HMF_ENABLE 0x404cc
3559 #define SRC_REG_FIRSTFREE0 0x40510
3560 #define SRC_REG_KEYRSS0_0 0x40408
3561 #define SRC_REG_KEYRSS0_7 0x40424
3562 #define SRC_REG_KEYRSS1_9 0x40454
3563 #define SRC_REG_KEYSEARCH_0 0x40458
3564 #define SRC_REG_KEYSEARCH_1 0x4045c
3565 #define SRC_REG_KEYSEARCH_2 0x40460
3566 #define SRC_REG_KEYSEARCH_3 0x40464
3567 #define SRC_REG_KEYSEARCH_4 0x40468
3568 #define SRC_REG_KEYSEARCH_5 0x4046c
3569 #define SRC_REG_KEYSEARCH_6 0x40470
3570 #define SRC_REG_KEYSEARCH_7 0x40474
3571 #define SRC_REG_KEYSEARCH_8 0x40478
3572 #define SRC_REG_KEYSEARCH_9 0x4047c
3573 #define SRC_REG_LASTFREE0 0x40530
3574 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
3575 /* [RW 1] Reset internal state machines. */
3576 #define SRC_REG_SOFT_RST 0x4049c
3577 /* [R 3] Interrupt register #0 read */
3578 #define SRC_REG_SRC_INT_STS 0x404ac
3579 /* [RW 3] Parity mask register #0 read/write */
3580 #define SRC_REG_SRC_PRTY_MASK 0x404c8
3581 /* [R 3] Parity register #0 read */
3582 #define SRC_REG_SRC_PRTY_STS 0x404bc
3583 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3584 #define TCM_REG_CAM_OCCUP 0x5017c
3585 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3586 disregarded; valid output is deasserted; all other signals are treated as
3587 usual; if 1 - normal activity. */
3588 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
3589 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3590 are disregarded; all other signals are treated as usual; if 1 - normal
3592 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
3593 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3594 disregarded; valid output is deasserted; all other signals are treated as
3595 usual; if 1 - normal activity. */
3596 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3597 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3598 input is disregarded; all other signals are treated as usual; if 1 -
3600 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
3601 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3602 the initial credit value; read returns the current value of the credit
3603 counter. Must be initialized to 1 at start-up. */
3604 #define TCM_REG_CFC_INIT_CRD 0x50204
3605 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3606 weight 8 (the most prioritised); 1 stands for weight 1(least
3607 prioritised); 2 stands for weight 2; tc. */
3608 #define TCM_REG_CP_WEIGHT 0x500c0
3609 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3610 disregarded; acknowledge output is deasserted; all other signals are
3611 treated as usual; if 1 - normal activity. */
3612 #define TCM_REG_CSEM_IFEN 0x5002c
3613 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
3615 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
3616 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3617 weight 8 (the most prioritised); 1 stands for weight 1(least
3618 prioritised); 2 stands for weight 2; tc. */
3619 #define TCM_REG_CSEM_WEIGHT 0x500bc
3620 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3621 #define TCM_REG_ERR_EVNT_ID 0x500a0
3622 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3623 #define TCM_REG_ERR_TCM_HDR 0x5009c
3624 /* [RW 8] The Event ID for Timers expiration. */
3625 #define TCM_REG_EXPR_EVNT_ID 0x500a4
3626 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3627 writes the initial credit value; read returns the current value of the
3628 credit counter. Must be initialized to 64 at start-up. */
3629 #define TCM_REG_FIC0_INIT_CRD 0x5020c
3630 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3631 writes the initial credit value; read returns the current value of the
3632 credit counter. Must be initialized to 64 at start-up. */
3633 #define TCM_REG_FIC1_INIT_CRD 0x50210
3634 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3635 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3636 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3637 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3638 #define TCM_REG_GR_ARB_TYPE 0x50114
3639 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3640 highest priority is 3. It is supposed that the Store channel is the
3641 compliment of the other 3 groups. */
3642 #define TCM_REG_GR_LD0_PR 0x5011c
3643 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3644 highest priority is 3. It is supposed that the Store channel is the
3645 compliment of the other 3 groups. */
3646 #define TCM_REG_GR_LD1_PR 0x50120
3647 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3648 sent to STORM; for a specific connection type. The double REG-pairs are
3649 used to align to STORM context row size of 128 bits. The offset of these
3650 data in the STORM context is always 0. Index _i stands for the connection
3651 type (one of 16). */
3652 #define TCM_REG_N_SM_CTX_LD_0 0x50050
3653 #define TCM_REG_N_SM_CTX_LD_1 0x50054
3654 #define TCM_REG_N_SM_CTX_LD_10 0x50078
3655 #define TCM_REG_N_SM_CTX_LD_11 0x5007c
3656 #define TCM_REG_N_SM_CTX_LD_12 0x50080
3657 #define TCM_REG_N_SM_CTX_LD_13 0x50084
3658 #define TCM_REG_N_SM_CTX_LD_14 0x50088
3659 #define TCM_REG_N_SM_CTX_LD_15 0x5008c
3660 #define TCM_REG_N_SM_CTX_LD_2 0x50058
3661 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
3662 #define TCM_REG_N_SM_CTX_LD_4 0x50060
3663 #define TCM_REG_N_SM_CTX_LD_5 0x50064
3664 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3665 acknowledge output is deasserted; all other signals are treated as usual;
3666 if 1 - normal activity. */
3667 #define TCM_REG_PBF_IFEN 0x50024
3668 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
3670 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
3671 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3672 weight 8 (the most prioritised); 1 stands for weight 1(least
3673 prioritised); 2 stands for weight 2; tc. */
3674 #define TCM_REG_PBF_WEIGHT 0x500b4
3675 #define TCM_REG_PHYS_QNUM0_0 0x500e0
3676 #define TCM_REG_PHYS_QNUM0_1 0x500e4
3677 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3678 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3679 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3680 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3681 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3682 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3683 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3684 acknowledge output is deasserted; all other signals are treated as usual;
3685 if 1 - normal activity. */
3686 #define TCM_REG_PRS_IFEN 0x50020
3687 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3689 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3690 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3691 weight 8 (the most prioritised); 1 stands for weight 1(least
3692 prioritised); 2 stands for weight 2; tc. */
3693 #define TCM_REG_PRS_WEIGHT 0x500b0
3694 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3695 #define TCM_REG_STOP_EVNT_ID 0x500a8
3696 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3698 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3699 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3700 disregarded; acknowledge output is deasserted; all other signals are
3701 treated as usual; if 1 - normal activity. */
3702 #define TCM_REG_STORM_TCM_IFEN 0x50010
3703 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3704 weight 8 (the most prioritised); 1 stands for weight 1(least
3705 prioritised); 2 stands for weight 2; tc. */
3706 #define TCM_REG_STORM_WEIGHT 0x500ac
3707 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3708 acknowledge output is deasserted; all other signals are treated as usual;
3709 if 1 - normal activity. */
3710 #define TCM_REG_TCM_CFC_IFEN 0x50040
3711 /* [RW 11] Interrupt mask register #0 read/write */
3712 #define TCM_REG_TCM_INT_MASK 0x501dc
3713 /* [R 11] Interrupt register #0 read */
3714 #define TCM_REG_TCM_INT_STS 0x501d0
3715 /* [R 27] Parity register #0 read */
3716 #define TCM_REG_TCM_PRTY_STS 0x501e0
3717 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3718 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3719 Is used to determine the number of the AG context REG-pairs written back;
3720 when the input message Reg1WbFlg isn't set. */
3721 #define TCM_REG_TCM_REG0_SZ 0x500d8
3722 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3723 disregarded; valid is deasserted; all other signals are treated as usual;
3724 if 1 - normal activity. */
3725 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3726 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3727 disregarded; valid is deasserted; all other signals are treated as usual;
3728 if 1 - normal activity. */
3729 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3730 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3731 disregarded; valid is deasserted; all other signals are treated as usual;
3732 if 1 - normal activity. */
3733 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3734 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3735 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3736 /* [RW 28] The CM header for Timers expiration command. */
3737 #define TCM_REG_TM_TCM_HDR 0x50098
3738 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3739 disregarded; acknowledge output is deasserted; all other signals are
3740 treated as usual; if 1 - normal activity. */
3741 #define TCM_REG_TM_TCM_IFEN 0x5001c
3742 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3743 weight 8 (the most prioritised); 1 stands for weight 1(least
3744 prioritised); 2 stands for weight 2; tc. */
3745 #define TCM_REG_TM_WEIGHT 0x500d0
3746 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3747 the initial credit value; read returns the current value of the credit
3748 counter. Must be initialized to 32 at start-up. */
3749 #define TCM_REG_TQM_INIT_CRD 0x5021c
3750 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3751 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3752 prioritised); 2 stands for weight 2; tc. */
3753 #define TCM_REG_TQM_P_WEIGHT 0x500c8
3754 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3755 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3756 prioritised); 2 stands for weight 2; tc. */
3757 #define TCM_REG_TQM_S_WEIGHT 0x500cc
3758 /* [RW 28] The CM header value for QM request (primary). */
3759 #define TCM_REG_TQM_TCM_HDR_P 0x50090
3760 /* [RW 28] The CM header value for QM request (secondary). */
3761 #define TCM_REG_TQM_TCM_HDR_S 0x50094
3762 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3763 acknowledge output is deasserted; all other signals are treated as usual;
3764 if 1 - normal activity. */
3765 #define TCM_REG_TQM_TCM_IFEN 0x50014
3766 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3767 acknowledge output is deasserted; all other signals are treated as usual;
3768 if 1 - normal activity. */
3769 #define TCM_REG_TSDM_IFEN 0x50018
3770 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
3772 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
3773 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3774 weight 8 (the most prioritised); 1 stands for weight 1(least
3775 prioritised); 2 stands for weight 2; tc. */
3776 #define TCM_REG_TSDM_WEIGHT 0x500c4
3777 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3778 disregarded; acknowledge output is deasserted; all other signals are
3779 treated as usual; if 1 - normal activity. */
3780 #define TCM_REG_USEM_IFEN 0x50028
3781 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
3783 #define TCM_REG_USEM_LENGTH_MIS 0x50170
3784 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3785 weight 8 (the most prioritised); 1 stands for weight 1(least
3786 prioritised); 2 stands for weight 2; tc. */
3787 #define TCM_REG_USEM_WEIGHT 0x500b8
3788 /* [RW 21] Indirect access to the descriptor table of the XX protection
3789 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3790 pointer; 20:16] - next pointer. */
3791 #define TCM_REG_XX_DESCR_TABLE 0x50280
3792 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
3793 /* [R 6] Use to read the value of XX protection Free counter. */
3794 #define TCM_REG_XX_FREE 0x50178
3795 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3796 of the Input Stage XX protection buffer by the XX protection pending
3797 messages. Max credit available - 127.Write writes the initial credit
3798 value; read returns the current value of the credit counter. Must be
3799 initialized to 19 at start-up. */
3800 #define TCM_REG_XX_INIT_CRD 0x50220
3801 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
3803 #define TCM_REG_XX_MAX_LL_SZ 0x50044
3804 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3805 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3806 #define TCM_REG_XX_MSG_NUM 0x50224
3807 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3808 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3809 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3810 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3812 #define TCM_REG_XX_TABLE 0x50240
3813 /* [RW 4] Load value for for cfc ac credit cnt. */
3814 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3815 /* [RW 4] Load value for cfc cld credit cnt. */
3816 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3817 /* [RW 8] Client0 context region. */
3818 #define TM_REG_CL0_CONT_REGION 0x164030
3819 /* [RW 8] Client1 context region. */
3820 #define TM_REG_CL1_CONT_REGION 0x164034
3821 /* [RW 8] Client2 context region. */
3822 #define TM_REG_CL2_CONT_REGION 0x164038
3823 /* [RW 2] Client in High priority client number. */
3824 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3825 /* [RW 4] Load value for clout0 cred cnt. */
3826 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3827 /* [RW 4] Load value for clout1 cred cnt. */
3828 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3829 /* [RW 4] Load value for clout2 cred cnt. */
3830 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3831 /* [RW 1] Enable client0 input. */
3832 #define TM_REG_EN_CL0_INPUT 0x164008
3833 /* [RW 1] Enable client1 input. */
3834 #define TM_REG_EN_CL1_INPUT 0x16400c
3835 /* [RW 1] Enable client2 input. */
3836 #define TM_REG_EN_CL2_INPUT 0x164010
3837 #define TM_REG_EN_LINEAR0_TIMER 0x164014
3838 /* [RW 1] Enable real time counter. */
3839 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3840 /* [RW 1] Enable for Timers state machines. */
3841 #define TM_REG_EN_TIMERS 0x164000
3842 /* [RW 4] Load value for expiration credit cnt. CFC max number of
3843 outstanding load requests for timers (expiration) context loading. */
3844 #define TM_REG_EXP_CRDCNT_VAL 0x164238
3845 /* [RW 32] Linear0 logic address. */
3846 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
3847 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3848 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3849 /* [WB 64] Linear0 phy address. */
3850 #define TM_REG_LIN0_PHY_ADDR 0x164270
3851 /* [RW 1] Linear0 physical address valid. */
3852 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
3853 #define TM_REG_LIN0_SCAN_ON 0x1640d0
3854 /* [RW 24] Linear0 array scan timeout. */
3855 #define TM_REG_LIN0_SCAN_TIME 0x16403c
3856 /* [RW 32] Linear1 logic address. */
3857 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
3858 /* [WB 64] Linear1 phy address. */
3859 #define TM_REG_LIN1_PHY_ADDR 0x164280
3860 /* [RW 1] Linear1 physical address valid. */
3861 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
3862 /* [RW 6] Linear timer set_clear fifo threshold. */
3863 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3864 /* [RW 2] Load value for pci arbiter credit cnt. */
3865 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3866 /* [RW 1] Timer software reset - active high. */
3867 #define TM_REG_TIMER_SOFT_RST 0x164004
3868 /* [RW 20] The amount of hardware cycles for each timer tick. */
3869 #define TM_REG_TIMER_TICK_SIZE 0x16401c
3870 /* [RW 8] Timers Context region. */
3871 #define TM_REG_TM_CONTEXT_REGION 0x164044
3872 /* [RW 1] Interrupt mask register #0 read/write */
3873 #define TM_REG_TM_INT_MASK 0x1640fc
3874 /* [R 1] Interrupt register #0 read */
3875 #define TM_REG_TM_INT_STS 0x1640f0
3876 /* [RW 8] The event id for aggregated interrupt 0 */
3877 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
3878 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3879 #define TSDM_REG_AGG_INT_EVENT_10 0x42060
3880 #define TSDM_REG_AGG_INT_EVENT_11 0x42064
3881 #define TSDM_REG_AGG_INT_EVENT_12 0x42068
3882 #define TSDM_REG_AGG_INT_EVENT_13 0x4206c
3883 #define TSDM_REG_AGG_INT_EVENT_14 0x42070
3884 #define TSDM_REG_AGG_INT_EVENT_15 0x42074
3885 #define TSDM_REG_AGG_INT_EVENT_16 0x42078
3886 #define TSDM_REG_AGG_INT_EVENT_17 0x4207c
3887 #define TSDM_REG_AGG_INT_EVENT_18 0x42080
3888 #define TSDM_REG_AGG_INT_EVENT_19 0x42084
3889 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
3890 #define TSDM_REG_AGG_INT_EVENT_20 0x42088
3891 #define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3892 #define TSDM_REG_AGG_INT_EVENT_22 0x42090
3893 #define TSDM_REG_AGG_INT_EVENT_23 0x42094
3894 #define TSDM_REG_AGG_INT_EVENT_24 0x42098
3895 #define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3896 #define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3897 #define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3898 #define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3899 #define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3900 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
3901 #define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3902 #define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3903 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
3904 /* [RW 1] The T bit for aggregated interrupt 0 */
3905 #define TSDM_REG_AGG_INT_T_0 0x420b8
3906 #define TSDM_REG_AGG_INT_T_1 0x420bc
3907 #define TSDM_REG_AGG_INT_T_10 0x420e0
3908 #define TSDM_REG_AGG_INT_T_11 0x420e4
3909 #define TSDM_REG_AGG_INT_T_12 0x420e8
3910 #define TSDM_REG_AGG_INT_T_13 0x420ec
3911 #define TSDM_REG_AGG_INT_T_14 0x420f0
3912 #define TSDM_REG_AGG_INT_T_15 0x420f4
3913 #define TSDM_REG_AGG_INT_T_16 0x420f8
3914 #define TSDM_REG_AGG_INT_T_17 0x420fc
3915 #define TSDM_REG_AGG_INT_T_18 0x42100
3916 #define TSDM_REG_AGG_INT_T_19 0x42104
3917 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3918 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3919 /* [RW 16] The maximum value of the competion counter #0 */
3920 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3921 /* [RW 16] The maximum value of the competion counter #1 */
3922 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3923 /* [RW 16] The maximum value of the competion counter #2 */
3924 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3925 /* [RW 16] The maximum value of the competion counter #3 */
3926 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3927 /* [RW 13] The start address in the internal RAM for the completion
3929 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3930 #define TSDM_REG_ENABLE_IN1 0x42238
3931 #define TSDM_REG_ENABLE_IN2 0x4223c
3932 #define TSDM_REG_ENABLE_OUT1 0x42240
3933 #define TSDM_REG_ENABLE_OUT2 0x42244
3934 /* [RW 4] The initial number of messages that can be sent to the pxp control
3935 interface without receiving any ACK. */
3936 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3937 /* [ST 32] The number of ACK after placement messages received */
3938 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3939 /* [ST 32] The number of packet end messages received from the parser */
3940 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3941 /* [ST 32] The number of requests received from the pxp async if */
3942 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3943 /* [ST 32] The number of commands received in queue 0 */
3944 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3945 /* [ST 32] The number of commands received in queue 10 */
3946 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3947 /* [ST 32] The number of commands received in queue 11 */
3948 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3949 /* [ST 32] The number of commands received in queue 1 */
3950 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3951 /* [ST 32] The number of commands received in queue 3 */
3952 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3953 /* [ST 32] The number of commands received in queue 4 */
3954 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3955 /* [ST 32] The number of commands received in queue 5 */
3956 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3957 /* [ST 32] The number of commands received in queue 6 */
3958 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3959 /* [ST 32] The number of commands received in queue 7 */
3960 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3961 /* [ST 32] The number of commands received in queue 8 */
3962 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3963 /* [ST 32] The number of commands received in queue 9 */
3964 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3965 /* [RW 13] The start address in the internal RAM for the packet end message */
3966 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3967 /* [RW 13] The start address in the internal RAM for queue counters */
3968 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3969 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3970 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3971 /* [R 1] parser fifo empty in sdm_sync block */
3972 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3973 /* [R 1] parser serial fifo empty in sdm_sync block */
3974 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3975 /* [RW 32] Tick for timer counter. Applicable only when
3976 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3977 #define TSDM_REG_TIMER_TICK 0x42000
3978 /* [RW 32] Interrupt mask register #0 read/write */
3979 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3980 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3981 /* [R 32] Interrupt register #0 read */
3982 #define TSDM_REG_TSDM_INT_STS_0 0x42290
3983 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
3984 /* [RW 11] Parity mask register #0 read/write */
3985 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
3986 /* [R 11] Parity register #0 read */
3987 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
3988 /* [RW 5] The number of time_slots in the arbitration cycle */
3989 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3990 /* [RW 3] The source that is associated with arbitration element 0. Source
3991 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3992 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3993 #define TSEM_REG_ARB_ELEMENT0 0x180020
3994 /* [RW 3] The source that is associated with arbitration element 1. Source
3995 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3996 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3997 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3998 #define TSEM_REG_ARB_ELEMENT1 0x180024
3999 /* [RW 3] The source that is associated with arbitration element 2. Source
4000 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4001 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4002 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4003 and ~tsem_registers_arb_element1.arb_element1 */
4004 #define TSEM_REG_ARB_ELEMENT2 0x180028
4005 /* [RW 3] The source that is associated with arbitration element 3. Source
4006 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4007 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4008 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4009 ~tsem_registers_arb_element1.arb_element1 and
4010 ~tsem_registers_arb_element2.arb_element2 */
4011 #define TSEM_REG_ARB_ELEMENT3 0x18002c
4012 /* [RW 3] The source that is associated with arbitration element 4. Source
4013 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4014 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4015 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4016 and ~tsem_registers_arb_element1.arb_element1 and
4017 ~tsem_registers_arb_element2.arb_element2 and
4018 ~tsem_registers_arb_element3.arb_element3 */
4019 #define TSEM_REG_ARB_ELEMENT4 0x180030
4020 #define TSEM_REG_ENABLE_IN 0x1800a4
4021 #define TSEM_REG_ENABLE_OUT 0x1800a8
4022 /* [RW 32] This address space contains all registers and memories that are
4023 placed in SEM_FAST block. The SEM_FAST registers are described in
4024 appendix B. In order to access the sem_fast registers the base address
4025 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4026 #define TSEM_REG_FAST_MEMORY 0x1a0000
4027 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4029 #define TSEM_REG_FIC0_DISABLE 0x180224
4030 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4032 #define TSEM_REG_FIC1_DISABLE 0x180234
4033 /* [RW 15] Interrupt table Read and write access to it is not possible in
4034 the middle of the work */
4035 #define TSEM_REG_INT_TABLE 0x180400
4036 /* [ST 24] Statistics register. The number of messages that entered through
4038 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4039 /* [ST 24] Statistics register. The number of messages that entered through
4041 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4042 /* [ST 24] Statistics register. The number of messages that were sent to
4044 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4045 /* [ST 24] Statistics register. The number of messages that were sent to
4047 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4048 /* [ST 24] Statistics register. The number of messages that were sent to
4050 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4051 /* [ST 24] Statistics register. The number of messages that were sent to
4053 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4054 /* [RW 1] Disables input messages from the passive buffer May be updated
4055 during run_time by the microcode */
4056 #define TSEM_REG_PAS_DISABLE 0x18024c
4057 /* [WB 128] Debug only. Passive buffer memory */
4058 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4059 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4060 #define TSEM_REG_PRAM 0x1c0000
4061 /* [R 8] Valid sleeping threads indication have bit per thread */
4062 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4063 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4064 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4065 /* [RW 8] List of free threads . There is a bit per thread. */
4066 #define TSEM_REG_THREADS_LIST 0x1802e4
4067 /* [RW 3] The arbitration scheme of time_slot 0 */
4068 #define TSEM_REG_TS_0_AS 0x180038
4069 /* [RW 3] The arbitration scheme of time_slot 10 */
4070 #define TSEM_REG_TS_10_AS 0x180060
4071 /* [RW 3] The arbitration scheme of time_slot 11 */
4072 #define TSEM_REG_TS_11_AS 0x180064
4073 /* [RW 3] The arbitration scheme of time_slot 12 */
4074 #define TSEM_REG_TS_12_AS 0x180068
4075 /* [RW 3] The arbitration scheme of time_slot 13 */
4076 #define TSEM_REG_TS_13_AS 0x18006c
4077 /* [RW 3] The arbitration scheme of time_slot 14 */
4078 #define TSEM_REG_TS_14_AS 0x180070
4079 /* [RW 3] The arbitration scheme of time_slot 15 */
4080 #define TSEM_REG_TS_15_AS 0x180074
4081 /* [RW 3] The arbitration scheme of time_slot 16 */
4082 #define TSEM_REG_TS_16_AS 0x180078
4083 /* [RW 3] The arbitration scheme of time_slot 17 */
4084 #define TSEM_REG_TS_17_AS 0x18007c
4085 /* [RW 3] The arbitration scheme of time_slot 18 */
4086 #define TSEM_REG_TS_18_AS 0x180080
4087 /* [RW 3] The arbitration scheme of time_slot 1 */
4088 #define TSEM_REG_TS_1_AS 0x18003c
4089 /* [RW 3] The arbitration scheme of time_slot 2 */
4090 #define TSEM_REG_TS_2_AS 0x180040
4091 /* [RW 3] The arbitration scheme of time_slot 3 */
4092 #define TSEM_REG_TS_3_AS 0x180044
4093 /* [RW 3] The arbitration scheme of time_slot 4 */
4094 #define TSEM_REG_TS_4_AS 0x180048
4095 /* [RW 3] The arbitration scheme of time_slot 5 */
4096 #define TSEM_REG_TS_5_AS 0x18004c
4097 /* [RW 3] The arbitration scheme of time_slot 6 */
4098 #define TSEM_REG_TS_6_AS 0x180050
4099 /* [RW 3] The arbitration scheme of time_slot 7 */
4100 #define TSEM_REG_TS_7_AS 0x180054
4101 /* [RW 3] The arbitration scheme of time_slot 8 */
4102 #define TSEM_REG_TS_8_AS 0x180058
4103 /* [RW 3] The arbitration scheme of time_slot 9 */
4104 #define TSEM_REG_TS_9_AS 0x18005c
4105 /* [RW 32] Interrupt mask register #0 read/write */
4106 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4107 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4108 /* [R 32] Interrupt register #0 read */
4109 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4110 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4111 /* [RW 32] Parity mask register #0 read/write */
4112 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4113 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4114 /* [R 32] Parity register #0 read */
4115 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4116 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4117 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4118 #define UCM_REG_CAM_OCCUP 0xe0170
4119 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4120 disregarded; valid output is deasserted; all other signals are treated as
4121 usual; if 1 - normal activity. */
4122 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4123 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4124 are disregarded; all other signals are treated as usual; if 1 - normal
4126 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4127 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4128 disregarded; valid output is deasserted; all other signals are treated as
4129 usual; if 1 - normal activity. */
4130 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4131 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4132 input is disregarded; all other signals are treated as usual; if 1 -
4134 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4135 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4136 the initial credit value; read returns the current value of the credit
4137 counter. Must be initialized to 1 at start-up. */
4138 #define UCM_REG_CFC_INIT_CRD 0xe0204
4139 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4140 weight 8 (the most prioritised); 1 stands for weight 1(least
4141 prioritised); 2 stands for weight 2; tc. */
4142 #define UCM_REG_CP_WEIGHT 0xe00c4
4143 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4144 disregarded; acknowledge output is deasserted; all other signals are
4145 treated as usual; if 1 - normal activity. */
4146 #define UCM_REG_CSEM_IFEN 0xe0028
4147 /* [RC 1] Set when the message length mismatch (relative to last indication)
4148 at the csem interface is detected. */
4149 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4150 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4151 weight 8 (the most prioritised); 1 stands for weight 1(least
4152 prioritised); 2 stands for weight 2; tc. */
4153 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4154 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4155 disregarded; acknowledge output is deasserted; all other signals are
4156 treated as usual; if 1 - normal activity. */
4157 #define UCM_REG_DORQ_IFEN 0xe0030
4158 /* [RC 1] Set when the message length mismatch (relative to last indication)
4159 at the dorq interface is detected. */
4160 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4161 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4162 weight 8 (the most prioritised); 1 stands for weight 1(least
4163 prioritised); 2 stands for weight 2; tc. */
4164 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4165 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4166 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4167 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4168 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4169 /* [RW 8] The Event ID for Timers expiration. */
4170 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4171 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4172 writes the initial credit value; read returns the current value of the
4173 credit counter. Must be initialized to 64 at start-up. */
4174 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4175 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4176 writes the initial credit value; read returns the current value of the
4177 credit counter. Must be initialized to 64 at start-up. */
4178 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4179 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4180 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4181 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4182 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4183 #define UCM_REG_GR_ARB_TYPE 0xe0144
4184 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4185 highest priority is 3. It is supposed that the Store channel group is
4186 compliment to the others. */
4187 #define UCM_REG_GR_LD0_PR 0xe014c
4188 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4189 highest priority is 3. It is supposed that the Store channel group is
4190 compliment to the others. */
4191 #define UCM_REG_GR_LD1_PR 0xe0150
4192 /* [RW 2] The queue index for invalidate counter flag decision. */
4193 #define UCM_REG_INV_CFLG_Q 0xe00e4
4194 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4195 sent to STORM; for a specific connection type. the double REG-pairs are
4196 used in order to align to STORM context row size of 128 bits. The offset
4197 of these data in the STORM context is always 0. Index _i stands for the
4198 connection type (one of 16). */
4199 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4200 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4201 #define UCM_REG_N_SM_CTX_LD_10 0xe007c
4202 #define UCM_REG_N_SM_CTX_LD_11 0xe0080
4203 #define UCM_REG_N_SM_CTX_LD_12 0xe0084
4204 #define UCM_REG_N_SM_CTX_LD_13 0xe0088
4205 #define UCM_REG_N_SM_CTX_LD_14 0xe008c
4206 #define UCM_REG_N_SM_CTX_LD_15 0xe0090
4207 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4208 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4209 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4210 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4211 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4212 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4213 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4214 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4215 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4216 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4217 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4218 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4219 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4220 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4221 /* [RC 1] Set when the message length mismatch (relative to last indication)
4222 at the STORM interface is detected. */
4223 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4224 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4225 disregarded; acknowledge output is deasserted; all other signals are
4226 treated as usual; if 1 - normal activity. */
4227 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4228 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4229 weight 8 (the most prioritised); 1 stands for weight 1(least
4230 prioritised); 2 stands for weight 2; tc. */
4231 #define UCM_REG_STORM_WEIGHT 0xe00b0
4232 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4233 writes the initial credit value; read returns the current value of the
4234 credit counter. Must be initialized to 4 at start-up. */
4235 #define UCM_REG_TM_INIT_CRD 0xe021c
4236 /* [RW 28] The CM header for Timers expiration command. */
4237 #define UCM_REG_TM_UCM_HDR 0xe009c
4238 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4239 disregarded; acknowledge output is deasserted; all other signals are
4240 treated as usual; if 1 - normal activity. */
4241 #define UCM_REG_TM_UCM_IFEN 0xe001c
4242 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4243 weight 8 (the most prioritised); 1 stands for weight 1(least
4244 prioritised); 2 stands for weight 2; tc. */
4245 #define UCM_REG_TM_WEIGHT 0xe00d4
4246 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4247 disregarded; acknowledge output is deasserted; all other signals are
4248 treated as usual; if 1 - normal activity. */
4249 #define UCM_REG_TSEM_IFEN 0xe0024
4250 /* [RC 1] Set when the message length mismatch (relative to last indication)
4251 at the tsem interface is detected. */
4252 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4253 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4254 weight 8 (the most prioritised); 1 stands for weight 1(least
4255 prioritised); 2 stands for weight 2; tc. */
4256 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4257 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4258 acknowledge output is deasserted; all other signals are treated as usual;
4259 if 1 - normal activity. */
4260 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4261 /* [RW 11] Interrupt mask register #0 read/write */
4262 #define UCM_REG_UCM_INT_MASK 0xe01d4
4263 /* [R 11] Interrupt register #0 read */
4264 #define UCM_REG_UCM_INT_STS 0xe01c8
4265 /* [R 27] Parity register #0 read */
4266 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4267 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4268 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4269 Is used to determine the number of the AG context REG-pairs written back;
4270 when the Reg1WbFlg isn't set. */
4271 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4272 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4273 disregarded; valid is deasserted; all other signals are treated as usual;
4274 if 1 - normal activity. */
4275 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4276 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4277 disregarded; valid is deasserted; all other signals are treated as usual;
4278 if 1 - normal activity. */
4279 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4280 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4281 disregarded; acknowledge output is deasserted; all other signals are
4282 treated as usual; if 1 - normal activity. */
4283 #define UCM_REG_UCM_TM_IFEN 0xe0020
4284 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4285 disregarded; valid is deasserted; all other signals are treated as usual;
4286 if 1 - normal activity. */
4287 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4288 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4289 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4290 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4291 the initial credit value; read returns the current value of the credit
4292 counter. Must be initialized to 32 at start-up. */
4293 #define UCM_REG_UQM_INIT_CRD 0xe0220
4294 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4295 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4296 prioritised); 2 stands for weight 2; tc. */
4297 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4298 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4299 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4300 prioritised); 2 stands for weight 2; tc. */
4301 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4302 /* [RW 28] The CM header value for QM request (primary). */
4303 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4304 /* [RW 28] The CM header value for QM request (secondary). */
4305 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4306 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4307 acknowledge output is deasserted; all other signals are treated as usual;
4308 if 1 - normal activity. */
4309 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4310 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4311 acknowledge output is deasserted; all other signals are treated as usual;
4312 if 1 - normal activity. */
4313 #define UCM_REG_USDM_IFEN 0xe0018
4314 /* [RC 1] Set when the message length mismatch (relative to last indication)
4315 at the SDM interface is detected. */
4316 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4317 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4318 weight 8 (the most prioritised); 1 stands for weight 1(least
4319 prioritised); 2 stands for weight 2; tc. */
4320 #define UCM_REG_USDM_WEIGHT 0xe00c8
4321 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4322 disregarded; acknowledge output is deasserted; all other signals are
4323 treated as usual; if 1 - normal activity. */
4324 #define UCM_REG_XSEM_IFEN 0xe002c
4325 /* [RC 1] Set when the message length mismatch (relative to last indication)
4326 at the xsem interface isdetected. */
4327 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4328 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4329 weight 8 (the most prioritised); 1 stands for weight 1(least
4330 prioritised); 2 stands for weight 2; tc. */
4331 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4332 /* [RW 20] Indirect access to the descriptor table of the XX protection
4333 mechanism. The fields are:[5:0] - message length; 14:6] - message
4334 pointer; 19:15] - next pointer. */
4335 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4336 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
4337 /* [R 6] Use to read the XX protection Free counter. */
4338 #define UCM_REG_XX_FREE 0xe016c
4339 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4340 of the Input Stage XX protection buffer by the XX protection pending
4341 messages. Write writes the initial credit value; read returns the current
4342 value of the credit counter. Must be initialized to 12 at start-up. */
4343 #define UCM_REG_XX_INIT_CRD 0xe0224
4344 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4345 protection. ~ucm_registers_xx_free.xx_free read on read. */
4346 #define UCM_REG_XX_MSG_NUM 0xe0228
4347 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4348 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4349 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4350 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4352 #define UCM_REG_XX_TABLE 0xe0300
4353 /* [RW 8] The event id for aggregated interrupt 0 */
4354 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
4355 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
4356 #define USDM_REG_AGG_INT_EVENT_10 0xc4060
4357 #define USDM_REG_AGG_INT_EVENT_11 0xc4064
4358 #define USDM_REG_AGG_INT_EVENT_12 0xc4068
4359 #define USDM_REG_AGG_INT_EVENT_13 0xc406c
4360 #define USDM_REG_AGG_INT_EVENT_14 0xc4070
4361 #define USDM_REG_AGG_INT_EVENT_15 0xc4074
4362 #define USDM_REG_AGG_INT_EVENT_16 0xc4078
4363 #define USDM_REG_AGG_INT_EVENT_17 0xc407c
4364 #define USDM_REG_AGG_INT_EVENT_18 0xc4080
4365 #define USDM_REG_AGG_INT_EVENT_19 0xc4084
4366 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
4367 #define USDM_REG_AGG_INT_EVENT_20 0xc4088
4368 #define USDM_REG_AGG_INT_EVENT_21 0xc408c
4369 #define USDM_REG_AGG_INT_EVENT_22 0xc4090
4370 #define USDM_REG_AGG_INT_EVENT_23 0xc4094
4371 #define USDM_REG_AGG_INT_EVENT_24 0xc4098
4372 #define USDM_REG_AGG_INT_EVENT_25 0xc409c
4373 #define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4374 #define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4375 #define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4376 #define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4377 #define USDM_REG_AGG_INT_EVENT_3 0xc4044
4378 #define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4379 #define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4380 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
4381 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
4382 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
4383 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4384 or auto-mask-mode (1) */
4385 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
4386 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
4387 #define USDM_REG_AGG_INT_MODE_10 0xc41e0
4388 #define USDM_REG_AGG_INT_MODE_11 0xc41e4
4389 #define USDM_REG_AGG_INT_MODE_12 0xc41e8
4390 #define USDM_REG_AGG_INT_MODE_13 0xc41ec
4391 #define USDM_REG_AGG_INT_MODE_14 0xc41f0
4392 #define USDM_REG_AGG_INT_MODE_15 0xc41f4
4393 #define USDM_REG_AGG_INT_MODE_16 0xc41f8
4394 #define USDM_REG_AGG_INT_MODE_17 0xc41fc
4395 #define USDM_REG_AGG_INT_MODE_18 0xc4200
4396 #define USDM_REG_AGG_INT_MODE_19 0xc4204
4397 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
4398 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
4399 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
4400 /* [RW 1] The T bit for aggregated interrupt 5 */
4401 #define USDM_REG_AGG_INT_T_5 0xc40cc
4402 #define USDM_REG_AGG_INT_T_6 0xc40d0
4403 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4404 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4405 /* [RW 16] The maximum value of the competion counter #0 */
4406 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4407 /* [RW 16] The maximum value of the competion counter #1 */
4408 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4409 /* [RW 16] The maximum value of the competion counter #2 */
4410 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4411 /* [RW 16] The maximum value of the competion counter #3 */
4412 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4413 /* [RW 13] The start address in the internal RAM for the completion
4415 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4416 #define USDM_REG_ENABLE_IN1 0xc4238
4417 #define USDM_REG_ENABLE_IN2 0xc423c
4418 #define USDM_REG_ENABLE_OUT1 0xc4240
4419 #define USDM_REG_ENABLE_OUT2 0xc4244
4420 /* [RW 4] The initial number of messages that can be sent to the pxp control
4421 interface without receiving any ACK. */
4422 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4423 /* [ST 32] The number of ACK after placement messages received */
4424 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4425 /* [ST 32] The number of packet end messages received from the parser */
4426 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4427 /* [ST 32] The number of requests received from the pxp async if */
4428 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4429 /* [ST 32] The number of commands received in queue 0 */
4430 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4431 /* [ST 32] The number of commands received in queue 10 */
4432 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4433 /* [ST 32] The number of commands received in queue 11 */
4434 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4435 /* [ST 32] The number of commands received in queue 1 */
4436 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4437 /* [ST 32] The number of commands received in queue 2 */
4438 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4439 /* [ST 32] The number of commands received in queue 3 */
4440 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4441 /* [ST 32] The number of commands received in queue 4 */
4442 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4443 /* [ST 32] The number of commands received in queue 5 */
4444 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4445 /* [ST 32] The number of commands received in queue 6 */
4446 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4447 /* [ST 32] The number of commands received in queue 7 */
4448 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4449 /* [ST 32] The number of commands received in queue 8 */
4450 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4451 /* [ST 32] The number of commands received in queue 9 */
4452 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4453 /* [RW 13] The start address in the internal RAM for the packet end message */
4454 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4455 /* [RW 13] The start address in the internal RAM for queue counters */
4456 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4457 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4458 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4459 /* [R 1] parser fifo empty in sdm_sync block */
4460 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4461 /* [R 1] parser serial fifo empty in sdm_sync block */
4462 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4463 /* [RW 32] Tick for timer counter. Applicable only when
4464 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4465 #define USDM_REG_TIMER_TICK 0xc4000
4466 /* [RW 32] Interrupt mask register #0 read/write */
4467 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
4468 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
4469 /* [R 32] Interrupt register #0 read */
4470 #define USDM_REG_USDM_INT_STS_0 0xc4294
4471 #define USDM_REG_USDM_INT_STS_1 0xc42a4
4472 /* [RW 11] Parity mask register #0 read/write */
4473 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
4474 /* [R 11] Parity register #0 read */
4475 #define USDM_REG_USDM_PRTY_STS 0xc42b4
4476 /* [RW 5] The number of time_slots in the arbitration cycle */
4477 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
4478 /* [RW 3] The source that is associated with arbitration element 0. Source
4479 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4480 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4481 #define USEM_REG_ARB_ELEMENT0 0x300020
4482 /* [RW 3] The source that is associated with arbitration element 1. Source
4483 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4484 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4485 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4486 #define USEM_REG_ARB_ELEMENT1 0x300024
4487 /* [RW 3] The source that is associated with arbitration element 2. Source
4488 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4489 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4490 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4491 and ~usem_registers_arb_element1.arb_element1 */
4492 #define USEM_REG_ARB_ELEMENT2 0x300028
4493 /* [RW 3] The source that is associated with arbitration element 3. Source
4494 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4495 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4496 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4497 ~usem_registers_arb_element1.arb_element1 and
4498 ~usem_registers_arb_element2.arb_element2 */
4499 #define USEM_REG_ARB_ELEMENT3 0x30002c
4500 /* [RW 3] The source that is associated with arbitration element 4. Source
4501 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4502 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4503 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4504 and ~usem_registers_arb_element1.arb_element1 and
4505 ~usem_registers_arb_element2.arb_element2 and
4506 ~usem_registers_arb_element3.arb_element3 */
4507 #define USEM_REG_ARB_ELEMENT4 0x300030
4508 #define USEM_REG_ENABLE_IN 0x3000a4
4509 #define USEM_REG_ENABLE_OUT 0x3000a8
4510 /* [RW 32] This address space contains all registers and memories that are
4511 placed in SEM_FAST block. The SEM_FAST registers are described in
4512 appendix B. In order to access the sem_fast registers the base address
4513 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4514 #define USEM_REG_FAST_MEMORY 0x320000
4515 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4517 #define USEM_REG_FIC0_DISABLE 0x300224
4518 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4520 #define USEM_REG_FIC1_DISABLE 0x300234
4521 /* [RW 15] Interrupt table Read and write access to it is not possible in
4522 the middle of the work */
4523 #define USEM_REG_INT_TABLE 0x300400
4524 /* [ST 24] Statistics register. The number of messages that entered through
4526 #define USEM_REG_MSG_NUM_FIC0 0x300000
4527 /* [ST 24] Statistics register. The number of messages that entered through
4529 #define USEM_REG_MSG_NUM_FIC1 0x300004
4530 /* [ST 24] Statistics register. The number of messages that were sent to
4532 #define USEM_REG_MSG_NUM_FOC0 0x300008
4533 /* [ST 24] Statistics register. The number of messages that were sent to
4535 #define USEM_REG_MSG_NUM_FOC1 0x30000c
4536 /* [ST 24] Statistics register. The number of messages that were sent to
4538 #define USEM_REG_MSG_NUM_FOC2 0x300010
4539 /* [ST 24] Statistics register. The number of messages that were sent to
4541 #define USEM_REG_MSG_NUM_FOC3 0x300014
4542 /* [RW 1] Disables input messages from the passive buffer May be updated
4543 during run_time by the microcode */
4544 #define USEM_REG_PAS_DISABLE 0x30024c
4545 /* [WB 128] Debug only. Passive buffer memory */
4546 #define USEM_REG_PASSIVE_BUFFER 0x302000
4547 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4548 #define USEM_REG_PRAM 0x340000
4549 /* [R 16] Valid sleeping threads indication have bit per thread */
4550 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4551 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4552 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4553 /* [RW 16] List of free threads . There is a bit per thread. */
4554 #define USEM_REG_THREADS_LIST 0x3002e4
4555 /* [RW 3] The arbitration scheme of time_slot 0 */
4556 #define USEM_REG_TS_0_AS 0x300038
4557 /* [RW 3] The arbitration scheme of time_slot 10 */
4558 #define USEM_REG_TS_10_AS 0x300060
4559 /* [RW 3] The arbitration scheme of time_slot 11 */
4560 #define USEM_REG_TS_11_AS 0x300064
4561 /* [RW 3] The arbitration scheme of time_slot 12 */
4562 #define USEM_REG_TS_12_AS 0x300068
4563 /* [RW 3] The arbitration scheme of time_slot 13 */
4564 #define USEM_REG_TS_13_AS 0x30006c
4565 /* [RW 3] The arbitration scheme of time_slot 14 */
4566 #define USEM_REG_TS_14_AS 0x300070
4567 /* [RW 3] The arbitration scheme of time_slot 15 */
4568 #define USEM_REG_TS_15_AS 0x300074
4569 /* [RW 3] The arbitration scheme of time_slot 16 */
4570 #define USEM_REG_TS_16_AS 0x300078
4571 /* [RW 3] The arbitration scheme of time_slot 17 */
4572 #define USEM_REG_TS_17_AS 0x30007c
4573 /* [RW 3] The arbitration scheme of time_slot 18 */
4574 #define USEM_REG_TS_18_AS 0x300080
4575 /* [RW 3] The arbitration scheme of time_slot 1 */
4576 #define USEM_REG_TS_1_AS 0x30003c
4577 /* [RW 3] The arbitration scheme of time_slot 2 */
4578 #define USEM_REG_TS_2_AS 0x300040
4579 /* [RW 3] The arbitration scheme of time_slot 3 */
4580 #define USEM_REG_TS_3_AS 0x300044
4581 /* [RW 3] The arbitration scheme of time_slot 4 */
4582 #define USEM_REG_TS_4_AS 0x300048
4583 /* [RW 3] The arbitration scheme of time_slot 5 */
4584 #define USEM_REG_TS_5_AS 0x30004c
4585 /* [RW 3] The arbitration scheme of time_slot 6 */
4586 #define USEM_REG_TS_6_AS 0x300050
4587 /* [RW 3] The arbitration scheme of time_slot 7 */
4588 #define USEM_REG_TS_7_AS 0x300054
4589 /* [RW 3] The arbitration scheme of time_slot 8 */
4590 #define USEM_REG_TS_8_AS 0x300058
4591 /* [RW 3] The arbitration scheme of time_slot 9 */
4592 #define USEM_REG_TS_9_AS 0x30005c
4593 /* [RW 32] Interrupt mask register #0 read/write */
4594 #define USEM_REG_USEM_INT_MASK_0 0x300110
4595 #define USEM_REG_USEM_INT_MASK_1 0x300120
4596 /* [R 32] Interrupt register #0 read */
4597 #define USEM_REG_USEM_INT_STS_0 0x300104
4598 #define USEM_REG_USEM_INT_STS_1 0x300114
4599 /* [RW 32] Parity mask register #0 read/write */
4600 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
4601 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
4602 /* [R 32] Parity register #0 read */
4603 #define USEM_REG_USEM_PRTY_STS_0 0x300124
4604 #define USEM_REG_USEM_PRTY_STS_1 0x300134
4605 /* [RW 2] The queue index for registration on Aux1 counter flag. */
4606 #define XCM_REG_AUX1_Q 0x20134
4607 /* [RW 2] Per each decision rule the queue index to register to. */
4608 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4609 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4610 #define XCM_REG_CAM_OCCUP 0x20244
4611 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4612 disregarded; valid output is deasserted; all other signals are treated as
4613 usual; if 1 - normal activity. */
4614 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
4615 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4616 are disregarded; all other signals are treated as usual; if 1 - normal
4618 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
4619 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4620 disregarded; valid output is deasserted; all other signals are treated as
4621 usual; if 1 - normal activity. */
4622 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4623 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4624 input is disregarded; all other signals are treated as usual; if 1 -
4626 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
4627 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4628 the initial credit value; read returns the current value of the credit
4629 counter. Must be initialized to 1 at start-up. */
4630 #define XCM_REG_CFC_INIT_CRD 0x20404
4631 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4632 weight 8 (the most prioritised); 1 stands for weight 1(least
4633 prioritised); 2 stands for weight 2; tc. */
4634 #define XCM_REG_CP_WEIGHT 0x200dc
4635 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4636 disregarded; acknowledge output is deasserted; all other signals are
4637 treated as usual; if 1 - normal activity. */
4638 #define XCM_REG_CSEM_IFEN 0x20028
4639 /* [RC 1] Set at message length mismatch (relative to last indication) at
4640 the csem interface. */
4641 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
4642 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4643 weight 8 (the most prioritised); 1 stands for weight 1(least
4644 prioritised); 2 stands for weight 2; tc. */
4645 #define XCM_REG_CSEM_WEIGHT 0x200c4
4646 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4647 disregarded; acknowledge output is deasserted; all other signals are
4648 treated as usual; if 1 - normal activity. */
4649 #define XCM_REG_DORQ_IFEN 0x20030
4650 /* [RC 1] Set at message length mismatch (relative to last indication) at
4651 the dorq interface. */
4652 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
4653 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4654 weight 8 (the most prioritised); 1 stands for weight 1(least
4655 prioritised); 2 stands for weight 2; tc. */
4656 #define XCM_REG_DORQ_WEIGHT 0x200cc
4657 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4658 #define XCM_REG_ERR_EVNT_ID 0x200b0
4659 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4660 #define XCM_REG_ERR_XCM_HDR 0x200ac
4661 /* [RW 8] The Event ID for Timers expiration. */
4662 #define XCM_REG_EXPR_EVNT_ID 0x200b4
4663 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4664 writes the initial credit value; read returns the current value of the
4665 credit counter. Must be initialized to 64 at start-up. */
4666 #define XCM_REG_FIC0_INIT_CRD 0x2040c
4667 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4668 writes the initial credit value; read returns the current value of the
4669 credit counter. Must be initialized to 64 at start-up. */
4670 #define XCM_REG_FIC1_INIT_CRD 0x20410
4671 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4672 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
4673 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4674 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4675 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4676 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4677 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4678 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4679 #define XCM_REG_GR_ARB_TYPE 0x2020c
4680 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4681 highest priority is 3. It is supposed that the Channel group is the
4682 compliment of the other 3 groups. */
4683 #define XCM_REG_GR_LD0_PR 0x20214
4684 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4685 highest priority is 3. It is supposed that the Channel group is the
4686 compliment of the other 3 groups. */
4687 #define XCM_REG_GR_LD1_PR 0x20218
4688 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4689 disregarded; acknowledge output is deasserted; all other signals are
4690 treated as usual; if 1 - normal activity. */
4691 #define XCM_REG_NIG0_IFEN 0x20038
4692 /* [RC 1] Set at message length mismatch (relative to last indication) at
4693 the nig0 interface. */
4694 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
4695 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4696 weight 8 (the most prioritised); 1 stands for weight 1(least
4697 prioritised); 2 stands for weight 2; tc. */
4698 #define XCM_REG_NIG0_WEIGHT 0x200d4
4699 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4700 disregarded; acknowledge output is deasserted; all other signals are
4701 treated as usual; if 1 - normal activity. */
4702 #define XCM_REG_NIG1_IFEN 0x2003c
4703 /* [RC 1] Set at message length mismatch (relative to last indication) at
4704 the nig1 interface. */
4705 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4706 /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
4707 weight 8 (the most prioritised); 1 stands for weight 1(least
4708 prioritised); 2 stands for weight 2; tc. */
4709 #define XCM_REG_NIG1_WEIGHT 0x200d8
4710 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4711 sent to STORM; for a specific connection type. The double REG-pairs are
4712 used in order to align to STORM context row size of 128 bits. The offset
4713 of these data in the STORM context is always 0. Index _i stands for the
4714 connection type (one of 16). */
4715 #define XCM_REG_N_SM_CTX_LD_0 0x20060
4716 #define XCM_REG_N_SM_CTX_LD_1 0x20064
4717 #define XCM_REG_N_SM_CTX_LD_10 0x20088
4718 #define XCM_REG_N_SM_CTX_LD_11 0x2008c
4719 #define XCM_REG_N_SM_CTX_LD_12 0x20090
4720 #define XCM_REG_N_SM_CTX_LD_13 0x20094
4721 #define XCM_REG_N_SM_CTX_LD_14 0x20098
4722 #define XCM_REG_N_SM_CTX_LD_15 0x2009c
4723 #define XCM_REG_N_SM_CTX_LD_2 0x20068
4724 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
4725 #define XCM_REG_N_SM_CTX_LD_4 0x20070
4726 #define XCM_REG_N_SM_CTX_LD_5 0x20074
4727 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4728 acknowledge output is deasserted; all other signals are treated as usual;
4729 if 1 - normal activity. */
4730 #define XCM_REG_PBF_IFEN 0x20034
4731 /* [RC 1] Set at message length mismatch (relative to last indication) at
4732 the pbf interface. */
4733 #define XCM_REG_PBF_LENGTH_MIS 0x20234
4734 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4735 weight 8 (the most prioritised); 1 stands for weight 1(least
4736 prioritised); 2 stands for weight 2; tc. */
4737 #define XCM_REG_PBF_WEIGHT 0x200d0
4738 #define XCM_REG_PHYS_QNUM3_0 0x20100
4739 #define XCM_REG_PHYS_QNUM3_1 0x20104
4740 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4741 #define XCM_REG_STOP_EVNT_ID 0x200b8
4742 /* [RC 1] Set at message length mismatch (relative to last indication) at
4743 the STORM interface. */
4744 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
4745 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4746 weight 8 (the most prioritised); 1 stands for weight 1(least
4747 prioritised); 2 stands for weight 2; tc. */
4748 #define XCM_REG_STORM_WEIGHT 0x200bc
4749 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4750 disregarded; acknowledge output is deasserted; all other signals are
4751 treated as usual; if 1 - normal activity. */
4752 #define XCM_REG_STORM_XCM_IFEN 0x20010
4753 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4754 writes the initial credit value; read returns the current value of the
4755 credit counter. Must be initialized to 4 at start-up. */
4756 #define XCM_REG_TM_INIT_CRD 0x2041c
4757 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4758 weight 8 (the most prioritised); 1 stands for weight 1(least
4759 prioritised); 2 stands for weight 2; tc. */
4760 #define XCM_REG_TM_WEIGHT 0x200ec
4761 /* [RW 28] The CM header for Timers expiration command. */
4762 #define XCM_REG_TM_XCM_HDR 0x200a8
4763 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4764 disregarded; acknowledge output is deasserted; all other signals are
4765 treated as usual; if 1 - normal activity. */
4766 #define XCM_REG_TM_XCM_IFEN 0x2001c
4767 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4768 disregarded; acknowledge output is deasserted; all other signals are
4769 treated as usual; if 1 - normal activity. */
4770 #define XCM_REG_TSEM_IFEN 0x20024
4771 /* [RC 1] Set at message length mismatch (relative to last indication) at
4772 the tsem interface. */
4773 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4774 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4775 weight 8 (the most prioritised); 1 stands for weight 1(least
4776 prioritised); 2 stands for weight 2; tc. */
4777 #define XCM_REG_TSEM_WEIGHT 0x200c0
4778 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4779 #define XCM_REG_UNA_GT_NXT_Q 0x20120
4780 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4781 disregarded; acknowledge output is deasserted; all other signals are
4782 treated as usual; if 1 - normal activity. */
4783 #define XCM_REG_USEM_IFEN 0x2002c
4784 /* [RC 1] Message length mismatch (relative to last indication) at the usem
4786 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
4787 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4788 weight 8 (the most prioritised); 1 stands for weight 1(least
4789 prioritised); 2 stands for weight 2; tc. */
4790 #define XCM_REG_USEM_WEIGHT 0x200c8
4791 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
4792 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
4793 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
4794 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
4795 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
4796 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
4797 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
4798 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
4799 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
4800 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
4801 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
4802 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4803 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4804 acknowledge output is deasserted; all other signals are treated as usual;
4805 if 1 - normal activity. */
4806 #define XCM_REG_XCM_CFC_IFEN 0x20050
4807 /* [RW 14] Interrupt mask register #0 read/write */
4808 #define XCM_REG_XCM_INT_MASK 0x202b4
4809 /* [R 14] Interrupt register #0 read */
4810 #define XCM_REG_XCM_INT_STS 0x202a8
4811 /* [R 30] Parity register #0 read */
4812 #define XCM_REG_XCM_PRTY_STS 0x202b8
4813 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4814 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4815 Is used to determine the number of the AG context REG-pairs written back;
4816 when the Reg1WbFlg isn't set. */
4817 #define XCM_REG_XCM_REG0_SZ 0x200f4
4818 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4819 disregarded; valid is deasserted; all other signals are treated as usual;
4820 if 1 - normal activity. */
4821 #define XCM_REG_XCM_STORM0_IFEN 0x20004
4822 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4823 disregarded; valid is deasserted; all other signals are treated as usual;
4824 if 1 - normal activity. */
4825 #define XCM_REG_XCM_STORM1_IFEN 0x20008
4826 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4827 disregarded; acknowledge output is deasserted; all other signals are
4828 treated as usual; if 1 - normal activity. */
4829 #define XCM_REG_XCM_TM_IFEN 0x20020
4830 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4831 disregarded; valid is deasserted; all other signals are treated as usual;
4832 if 1 - normal activity. */
4833 #define XCM_REG_XCM_XQM_IFEN 0x2000c
4834 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4835 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
4836 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4837 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4838 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4839 the initial credit value; read returns the current value of the credit
4840 counter. Must be initialized to 32 at start-up. */
4841 #define XCM_REG_XQM_INIT_CRD 0x20420
4842 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4843 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4844 prioritised); 2 stands for weight 2; tc. */
4845 #define XCM_REG_XQM_P_WEIGHT 0x200e4
4846 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4847 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4848 prioritised); 2 stands for weight 2; tc. */
4849 #define XCM_REG_XQM_S_WEIGHT 0x200e8
4850 /* [RW 28] The CM header value for QM request (primary). */
4851 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
4852 /* [RW 28] The CM header value for QM request (secondary). */
4853 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
4854 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4855 acknowledge output is deasserted; all other signals are treated as usual;
4856 if 1 - normal activity. */
4857 #define XCM_REG_XQM_XCM_IFEN 0x20014
4858 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4859 acknowledge output is deasserted; all other signals are treated as usual;
4860 if 1 - normal activity. */
4861 #define XCM_REG_XSDM_IFEN 0x20018
4862 /* [RC 1] Set at message length mismatch (relative to last indication) at
4863 the SDM interface. */
4864 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
4865 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4866 weight 8 (the most prioritised); 1 stands for weight 1(least
4867 prioritised); 2 stands for weight 2; tc. */
4868 #define XCM_REG_XSDM_WEIGHT 0x200e0
4869 /* [RW 17] Indirect access to the descriptor table of the XX protection
4870 mechanism. The fields are: [5:0] - message length; 11:6] - message
4871 pointer; 16:12] - next pointer. */
4872 #define XCM_REG_XX_DESCR_TABLE 0x20480
4873 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
4874 /* [R 6] Used to read the XX protection Free counter. */
4875 #define XCM_REG_XX_FREE 0x20240
4876 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4877 of the Input Stage XX protection buffer by the XX protection pending
4878 messages. Max credit available - 3.Write writes the initial credit value;
4879 read returns the current value of the credit counter. Must be initialized
4880 to 2 at start-up. */
4881 #define XCM_REG_XX_INIT_CRD 0x20424
4882 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4883 protection. ~xcm_registers_xx_free.xx_free read on read. */
4884 #define XCM_REG_XX_MSG_NUM 0x20428
4885 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4886 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
4887 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4888 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4890 #define XCM_REG_XX_TABLE 0x20500
4891 /* [RW 8] The event id for aggregated interrupt 0 */
4892 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
4893 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4894 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4895 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4896 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4897 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4898 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4899 #define XSDM_REG_AGG_INT_EVENT_15 0x166074
4900 #define XSDM_REG_AGG_INT_EVENT_16 0x166078
4901 #define XSDM_REG_AGG_INT_EVENT_17 0x16607c
4902 #define XSDM_REG_AGG_INT_EVENT_18 0x166080
4903 #define XSDM_REG_AGG_INT_EVENT_19 0x166084
4904 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4905 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4906 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4907 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4908 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4909 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
4910 #define XSDM_REG_AGG_INT_EVENT_20 0x166088
4911 #define XSDM_REG_AGG_INT_EVENT_21 0x16608c
4912 #define XSDM_REG_AGG_INT_EVENT_22 0x166090
4913 #define XSDM_REG_AGG_INT_EVENT_23 0x166094
4914 #define XSDM_REG_AGG_INT_EVENT_24 0x166098
4915 #define XSDM_REG_AGG_INT_EVENT_25 0x16609c
4916 #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
4917 #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
4918 #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
4919 #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
4920 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
4921 #define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4922 #define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4923 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
4924 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4925 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
4926 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
4927 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
4928 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
4929 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4930 or auto-mask-mode (1) */
4931 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4932 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4933 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0
4934 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4
4935 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8
4936 #define XSDM_REG_AGG_INT_MODE_13 0x1661ec
4937 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0
4938 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4
4939 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8
4940 #define XSDM_REG_AGG_INT_MODE_17 0x1661fc
4941 #define XSDM_REG_AGG_INT_MODE_18 0x166200
4942 #define XSDM_REG_AGG_INT_MODE_19 0x166204
4943 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4944 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4945 /* [RW 16] The maximum value of the competion counter #0 */
4946 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4947 /* [RW 16] The maximum value of the competion counter #1 */
4948 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4949 /* [RW 16] The maximum value of the competion counter #2 */
4950 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4951 /* [RW 16] The maximum value of the competion counter #3 */
4952 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4953 /* [RW 13] The start address in the internal RAM for the completion
4955 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4956 #define XSDM_REG_ENABLE_IN1 0x166238
4957 #define XSDM_REG_ENABLE_IN2 0x16623c
4958 #define XSDM_REG_ENABLE_OUT1 0x166240
4959 #define XSDM_REG_ENABLE_OUT2 0x166244
4960 /* [RW 4] The initial number of messages that can be sent to the pxp control
4961 interface without receiving any ACK. */
4962 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4963 /* [ST 32] The number of ACK after placement messages received */
4964 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4965 /* [ST 32] The number of packet end messages received from the parser */
4966 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4967 /* [ST 32] The number of requests received from the pxp async if */
4968 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4969 /* [ST 32] The number of commands received in queue 0 */
4970 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4971 /* [ST 32] The number of commands received in queue 10 */
4972 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4973 /* [ST 32] The number of commands received in queue 11 */
4974 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4975 /* [ST 32] The number of commands received in queue 1 */
4976 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4977 /* [ST 32] The number of commands received in queue 3 */
4978 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4979 /* [ST 32] The number of commands received in queue 4 */
4980 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4981 /* [ST 32] The number of commands received in queue 5 */
4982 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4983 /* [ST 32] The number of commands received in queue 6 */
4984 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4985 /* [ST 32] The number of commands received in queue 7 */
4986 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4987 /* [ST 32] The number of commands received in queue 8 */
4988 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4989 /* [ST 32] The number of commands received in queue 9 */
4990 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4991 /* [RW 13] The start address in the internal RAM for queue counters */
4992 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4993 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4994 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4995 /* [R 1] parser fifo empty in sdm_sync block */
4996 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4997 /* [R 1] parser serial fifo empty in sdm_sync block */
4998 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4999 /* [RW 32] Tick for timer counter. Applicable only when
5000 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5001 #define XSDM_REG_TIMER_TICK 0x166000
5002 /* [RW 32] Interrupt mask register #0 read/write */
5003 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5004 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
5005 /* [R 32] Interrupt register #0 read */
5006 #define XSDM_REG_XSDM_INT_STS_0 0x166290
5007 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
5008 /* [RW 11] Parity mask register #0 read/write */
5009 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
5010 /* [R 11] Parity register #0 read */
5011 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
5012 /* [RW 5] The number of time_slots in the arbitration cycle */
5013 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5014 /* [RW 3] The source that is associated with arbitration element 0. Source
5015 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5016 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5017 #define XSEM_REG_ARB_ELEMENT0 0x280020
5018 /* [RW 3] The source that is associated with arbitration element 1. Source
5019 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5020 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5021 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5022 #define XSEM_REG_ARB_ELEMENT1 0x280024
5023 /* [RW 3] The source that is associated with arbitration element 2. Source
5024 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5025 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5026 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5027 and ~xsem_registers_arb_element1.arb_element1 */
5028 #define XSEM_REG_ARB_ELEMENT2 0x280028
5029 /* [RW 3] The source that is associated with arbitration element 3. Source
5030 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5031 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5032 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5033 ~xsem_registers_arb_element1.arb_element1 and
5034 ~xsem_registers_arb_element2.arb_element2 */
5035 #define XSEM_REG_ARB_ELEMENT3 0x28002c
5036 /* [RW 3] The source that is associated with arbitration element 4. Source
5037 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5038 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5039 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5040 and ~xsem_registers_arb_element1.arb_element1 and
5041 ~xsem_registers_arb_element2.arb_element2 and
5042 ~xsem_registers_arb_element3.arb_element3 */
5043 #define XSEM_REG_ARB_ELEMENT4 0x280030
5044 #define XSEM_REG_ENABLE_IN 0x2800a4
5045 #define XSEM_REG_ENABLE_OUT 0x2800a8
5046 /* [RW 32] This address space contains all registers and memories that are
5047 placed in SEM_FAST block. The SEM_FAST registers are described in
5048 appendix B. In order to access the sem_fast registers the base address
5049 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5050 #define XSEM_REG_FAST_MEMORY 0x2a0000
5051 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5053 #define XSEM_REG_FIC0_DISABLE 0x280224
5054 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5056 #define XSEM_REG_FIC1_DISABLE 0x280234
5057 /* [RW 15] Interrupt table Read and write access to it is not possible in
5058 the middle of the work */
5059 #define XSEM_REG_INT_TABLE 0x280400
5060 /* [ST 24] Statistics register. The number of messages that entered through
5062 #define XSEM_REG_MSG_NUM_FIC0 0x280000
5063 /* [ST 24] Statistics register. The number of messages that entered through
5065 #define XSEM_REG_MSG_NUM_FIC1 0x280004
5066 /* [ST 24] Statistics register. The number of messages that were sent to
5068 #define XSEM_REG_MSG_NUM_FOC0 0x280008
5069 /* [ST 24] Statistics register. The number of messages that were sent to
5071 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
5072 /* [ST 24] Statistics register. The number of messages that were sent to
5074 #define XSEM_REG_MSG_NUM_FOC2 0x280010
5075 /* [ST 24] Statistics register. The number of messages that were sent to
5077 #define XSEM_REG_MSG_NUM_FOC3 0x280014
5078 /* [RW 1] Disables input messages from the passive buffer May be updated
5079 during run_time by the microcode */
5080 #define XSEM_REG_PAS_DISABLE 0x28024c
5081 /* [WB 128] Debug only. Passive buffer memory */
5082 #define XSEM_REG_PASSIVE_BUFFER 0x282000
5083 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5084 #define XSEM_REG_PRAM 0x2c0000
5085 /* [R 16] Valid sleeping threads indication have bit per thread */
5086 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5087 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5088 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5089 /* [RW 16] List of free threads . There is a bit per thread. */
5090 #define XSEM_REG_THREADS_LIST 0x2802e4
5091 /* [RW 3] The arbitration scheme of time_slot 0 */
5092 #define XSEM_REG_TS_0_AS 0x280038
5093 /* [RW 3] The arbitration scheme of time_slot 10 */
5094 #define XSEM_REG_TS_10_AS 0x280060
5095 /* [RW 3] The arbitration scheme of time_slot 11 */
5096 #define XSEM_REG_TS_11_AS 0x280064
5097 /* [RW 3] The arbitration scheme of time_slot 12 */
5098 #define XSEM_REG_TS_12_AS 0x280068
5099 /* [RW 3] The arbitration scheme of time_slot 13 */
5100 #define XSEM_REG_TS_13_AS 0x28006c
5101 /* [RW 3] The arbitration scheme of time_slot 14 */
5102 #define XSEM_REG_TS_14_AS 0x280070
5103 /* [RW 3] The arbitration scheme of time_slot 15 */
5104 #define XSEM_REG_TS_15_AS 0x280074
5105 /* [RW 3] The arbitration scheme of time_slot 16 */
5106 #define XSEM_REG_TS_16_AS 0x280078
5107 /* [RW 3] The arbitration scheme of time_slot 17 */
5108 #define XSEM_REG_TS_17_AS 0x28007c
5109 /* [RW 3] The arbitration scheme of time_slot 18 */
5110 #define XSEM_REG_TS_18_AS 0x280080
5111 /* [RW 3] The arbitration scheme of time_slot 1 */
5112 #define XSEM_REG_TS_1_AS 0x28003c
5113 /* [RW 3] The arbitration scheme of time_slot 2 */
5114 #define XSEM_REG_TS_2_AS 0x280040
5115 /* [RW 3] The arbitration scheme of time_slot 3 */
5116 #define XSEM_REG_TS_3_AS 0x280044
5117 /* [RW 3] The arbitration scheme of time_slot 4 */
5118 #define XSEM_REG_TS_4_AS 0x280048
5119 /* [RW 3] The arbitration scheme of time_slot 5 */
5120 #define XSEM_REG_TS_5_AS 0x28004c
5121 /* [RW 3] The arbitration scheme of time_slot 6 */
5122 #define XSEM_REG_TS_6_AS 0x280050
5123 /* [RW 3] The arbitration scheme of time_slot 7 */
5124 #define XSEM_REG_TS_7_AS 0x280054
5125 /* [RW 3] The arbitration scheme of time_slot 8 */
5126 #define XSEM_REG_TS_8_AS 0x280058
5127 /* [RW 3] The arbitration scheme of time_slot 9 */
5128 #define XSEM_REG_TS_9_AS 0x28005c
5129 /* [RW 32] Interrupt mask register #0 read/write */
5130 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5131 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5132 /* [R 32] Interrupt register #0 read */
5133 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5134 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5135 /* [RW 32] Parity mask register #0 read/write */
5136 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5137 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5138 /* [R 32] Parity register #0 read */
5139 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5140 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5141 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5142 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5143 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5144 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5145 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
5146 #define MCPR_NVM_COMMAND_DONE (1L<<3)
5147 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
5148 #define MCPR_NVM_COMMAND_LAST (1L<<8)
5149 #define MCPR_NVM_COMMAND_WR (1L<<5)
5150 #define MCPR_NVM_COMMAND_WREN (1L<<16)
5151 #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
5152 #define MCPR_NVM_COMMAND_WRDI (1L<<17)
5153 #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
5154 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5155 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5156 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5157 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5158 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5159 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5160 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5161 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5162 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5163 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5164 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5165 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5166 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5167 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5168 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5169 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5170 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5171 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5172 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
5173 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
5174 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5175 #define EMAC_LED_OVERRIDE (1L<<0)
5176 #define EMAC_LED_TRAFFIC (1L<<6)
5177 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5178 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5179 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5180 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5181 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5182 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5183 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5184 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5185 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5186 #define EMAC_MODE_25G_MODE (1L<<5)
5187 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
5188 #define EMAC_MODE_PORT_GMII (2L<<2)
5189 #define EMAC_MODE_PORT_MII (1L<<2)
5190 #define EMAC_MODE_PORT_MII_10M (3L<<2)
5191 #define EMAC_MODE_RESET (1L<<0)
5192 #define EMAC_REG_EMAC_LED 0xc
5193 #define EMAC_REG_EMAC_MAC_MATCH 0x10
5194 #define EMAC_REG_EMAC_MDIO_COMM 0xac
5195 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5196 #define EMAC_REG_EMAC_MODE 0x0
5197 #define EMAC_REG_EMAC_RX_MODE 0xc8
5198 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5199 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5200 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5201 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5202 #define EMAC_REG_EMAC_TX_MODE 0xbc
5203 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5204 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5205 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5206 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5207 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5208 #define EMAC_RX_MODE_RESET (1L<<0)
5209 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5210 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5211 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5212 #define EMAC_TX_MODE_RESET (1L<<0)
5213 #define MISC_REGISTERS_GPIO_0 0
5214 #define MISC_REGISTERS_GPIO_1 1
5215 #define MISC_REGISTERS_GPIO_2 2
5216 #define MISC_REGISTERS_GPIO_3 3
5217 #define MISC_REGISTERS_GPIO_CLR_POS 16
5218 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5219 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5220 #define MISC_REGISTERS_GPIO_HIGH 1
5221 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5222 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5223 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5224 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5225 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
5226 #define MISC_REGISTERS_GPIO_LOW 0
5227 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5228 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5229 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5230 #define MISC_REGISTERS_GPIO_SET_POS 8
5231 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5232 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5233 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5234 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5235 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5236 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5237 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5238 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5239 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5240 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5241 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5242 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5243 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5244 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5245 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5246 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5247 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5248 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5249 #define MISC_REGISTERS_SPIO_4 4
5250 #define MISC_REGISTERS_SPIO_5 5
5251 #define MISC_REGISTERS_SPIO_7 7
5252 #define MISC_REGISTERS_SPIO_CLR_POS 16
5253 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5254 #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
5255 #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
5256 #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
5257 #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
5258 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5259 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5260 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5261 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5262 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5263 #define MISC_REGISTERS_SPIO_SET_POS 8
5264 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5265 #define HW_LOCK_RESOURCE_GPIO 1
5266 #define HW_LOCK_RESOURCE_MDIO 0
5267 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5268 #define HW_LOCK_RESOURCE_SPIO 2
5269 #define HW_LOCK_RESOURCE_UNDI 5
5270 #define PRS_FLAG_OVERETH_IPV4 1
5271 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5272 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5273 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5274 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5275 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5276 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5277 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5278 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5279 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5280 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5281 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5282 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5283 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5284 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5285 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
5286 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
5287 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5288 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5289 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5290 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5291 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5292 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5293 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5294 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5295 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5296 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5297 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5298 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5299 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
5300 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
5301 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5302 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5303 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5304 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5305 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5306 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5307 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5308 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5309 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5310 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5311 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5312 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5313 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5314 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5315 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5316 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5317 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5318 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5319 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5320 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
5322 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
5323 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5325 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
5326 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
5327 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
5328 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
5329 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
5330 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
5331 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
5332 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
5333 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
5334 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
5335 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
5336 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
5337 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
5338 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
5339 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
5340 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
5342 /* storm asserts attention bits */
5343 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5344 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5345 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5346 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5348 /* mcp error attention bit */
5349 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5351 /*E1H NIG status sync attention mapped to group 4-7*/
5352 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5353 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5354 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5355 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5356 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5357 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5358 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5359 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5362 #define LATCHED_ATTN_RBCR 23
5363 #define LATCHED_ATTN_RBCT 24
5364 #define LATCHED_ATTN_RBCN 25
5365 #define LATCHED_ATTN_RBCU 26
5366 #define LATCHED_ATTN_RBCP 27
5367 #define LATCHED_ATTN_TIMEOUT_GRC 28
5368 #define LATCHED_ATTN_RSVD_GRC 29
5369 #define LATCHED_ATTN_ROM_PARITY_MCP 30
5370 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5371 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5372 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5374 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5375 #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
5377 * This file defines GRC base address for every block.
5378 * This file is included by chipsim, asm microcode and cpp microcode.
5379 * These values are used in Design.xml on regBase attribute
5380 * Use the base with the generated offsets of specific registers.
5383 #define GRCBASE_PXPCS 0x000000
5384 #define GRCBASE_PCICONFIG 0x002000
5385 #define GRCBASE_PCIREG 0x002400
5386 #define GRCBASE_EMAC0 0x008000
5387 #define GRCBASE_EMAC1 0x008400
5388 #define GRCBASE_DBU 0x008800
5389 #define GRCBASE_MISC 0x00A000
5390 #define GRCBASE_DBG 0x00C000
5391 #define GRCBASE_NIG 0x010000
5392 #define GRCBASE_XCM 0x020000
5393 #define GRCBASE_PRS 0x040000
5394 #define GRCBASE_SRCH 0x040400
5395 #define GRCBASE_TSDM 0x042000
5396 #define GRCBASE_TCM 0x050000
5397 #define GRCBASE_BRB1 0x060000
5398 #define GRCBASE_MCP 0x080000
5399 #define GRCBASE_UPB 0x0C1000
5400 #define GRCBASE_CSDM 0x0C2000
5401 #define GRCBASE_USDM 0x0C4000
5402 #define GRCBASE_CCM 0x0D0000
5403 #define GRCBASE_UCM 0x0E0000
5404 #define GRCBASE_CDU 0x101000
5405 #define GRCBASE_DMAE 0x102000
5406 #define GRCBASE_PXP 0x103000
5407 #define GRCBASE_CFC 0x104000
5408 #define GRCBASE_HC 0x108000
5409 #define GRCBASE_PXP2 0x120000
5410 #define GRCBASE_PBF 0x140000
5411 #define GRCBASE_XPB 0x161000
5412 #define GRCBASE_TIMERS 0x164000
5413 #define GRCBASE_XSDM 0x166000
5414 #define GRCBASE_QM 0x168000
5415 #define GRCBASE_DQ 0x170000
5416 #define GRCBASE_TSEM 0x180000
5417 #define GRCBASE_CSEM 0x200000
5418 #define GRCBASE_XSEM 0x280000
5419 #define GRCBASE_USEM 0x300000
5420 #define GRCBASE_MISC_AEU GRCBASE_MISC
5423 /* offset of configuration space in the pci core register */
5424 #define PCICFG_OFFSET 0x2000
5425 #define PCICFG_VENDOR_ID_OFFSET 0x00
5426 #define PCICFG_DEVICE_ID_OFFSET 0x02
5427 #define PCICFG_COMMAND_OFFSET 0x04
5428 #define PCICFG_COMMAND_IO_SPACE (1<<0)
5429 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
5430 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
5431 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5432 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5433 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5434 #define PCICFG_COMMAND_PERR_ENA (1<<6)
5435 #define PCICFG_COMMAND_STEPPING (1<<7)
5436 #define PCICFG_COMMAND_SERR_ENA (1<<8)
5437 #define PCICFG_COMMAND_FAST_B2B (1<<9)
5438 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
5439 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
5440 #define PCICFG_STATUS_OFFSET 0x06
5441 #define PCICFG_REVESION_ID_OFFSET 0x08
5442 #define PCICFG_CACHE_LINE_SIZE 0x0c
5443 #define PCICFG_LATENCY_TIMER 0x0d
5444 #define PCICFG_BAR_1_LOW 0x10
5445 #define PCICFG_BAR_1_HIGH 0x14
5446 #define PCICFG_BAR_2_LOW 0x18
5447 #define PCICFG_BAR_2_HIGH 0x1c
5448 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5449 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5450 #define PCICFG_INT_LINE 0x3c
5451 #define PCICFG_INT_PIN 0x3d
5452 #define PCICFG_PM_CAPABILITY 0x48
5453 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5454 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5455 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5456 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
5457 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5458 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5459 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5460 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5461 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5462 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5463 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5464 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5465 #define PCICFG_PM_CSR_OFFSET 0x4c
5466 #define PCICFG_PM_CSR_STATE (0x3<<0)
5467 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5468 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
5469 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
5470 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5471 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5472 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5473 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5474 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5475 #define PCICFG_GRC_ADDRESS 0x78
5476 #define PCICFG_GRC_DATA 0x80
5477 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
5478 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5479 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5480 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5481 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5483 #define PCICFG_DEVICE_CONTROL 0xb4
5484 #define PCICFG_DEVICE_STATUS 0xb6
5485 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5486 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5487 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5488 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5489 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5490 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
5491 #define PCICFG_LINK_CONTROL 0xbc
5494 #define BAR_USTRORM_INTMEM 0x400000
5495 #define BAR_CSTRORM_INTMEM 0x410000
5496 #define BAR_XSTRORM_INTMEM 0x420000
5497 #define BAR_TSTRORM_INTMEM 0x430000
5499 /* for accessing the IGU in case of status block ACK */
5500 #define BAR_IGU_INTMEM 0x440000
5502 #define BAR_DOORBELL_OFFSET 0x800000
5504 #define BAR_ME_REGISTER 0x450000
5506 /* config_2 offset */
5507 #define GRC_CONFIG_2_SIZE_REG 0x408
5508 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5509 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5510 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5511 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5512 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5513 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5514 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5515 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5516 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5517 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5518 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5519 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5520 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5521 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5522 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5523 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5524 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5525 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5526 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5527 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5528 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5529 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5530 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5531 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5532 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5533 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5534 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5535 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5536 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5537 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5538 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5539 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5540 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5541 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5542 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5543 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5544 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5545 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5546 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5547 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5549 /* config_3 offset */
5550 #define GRC_CONFIG_3_SIZE_REG 0x40c
5551 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5552 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
5553 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
5554 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5555 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5556 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5557 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
5559 #define GRC_BAR2_CONFIG 0x4e0
5560 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5561 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5562 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5563 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5564 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5565 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5566 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5567 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5568 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5569 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5570 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5571 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5572 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5573 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5574 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5575 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5576 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5577 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5579 #define PCI_PM_DATA_A 0x410
5580 #define PCI_PM_DATA_B 0x414
5581 #define PCI_ID_VAL1 0x434
5582 #define PCI_ID_VAL2 0x438
5585 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
5586 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5587 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5588 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5589 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5591 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
5592 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
5593 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5594 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5595 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5596 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5598 #define MDIO_REG_BANK_RX0 0x80b0
5599 #define MDIO_RX0_RX_EQ_BOOST 0x1c
5600 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5601 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5603 #define MDIO_REG_BANK_RX1 0x80c0
5604 #define MDIO_RX1_RX_EQ_BOOST 0x1c
5605 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5606 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5608 #define MDIO_REG_BANK_RX2 0x80d0
5609 #define MDIO_RX2_RX_EQ_BOOST 0x1c
5610 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5611 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5613 #define MDIO_REG_BANK_RX3 0x80e0
5614 #define MDIO_RX3_RX_EQ_BOOST 0x1c
5615 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5616 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5618 #define MDIO_REG_BANK_RX_ALL 0x80f0
5619 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5620 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5621 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
5623 #define MDIO_REG_BANK_TX0 0x8060
5624 #define MDIO_TX0_TX_DRIVER 0x17
5625 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5626 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5627 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5628 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5629 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5630 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5631 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5632 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5633 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5635 #define MDIO_REG_BANK_TX1 0x8070
5636 #define MDIO_TX1_TX_DRIVER 0x17
5637 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5638 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5639 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5640 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5641 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5642 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5643 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5644 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5645 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5647 #define MDIO_REG_BANK_TX2 0x8080
5648 #define MDIO_TX2_TX_DRIVER 0x17
5649 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5650 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5651 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5652 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5653 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5654 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5655 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5656 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5657 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5659 #define MDIO_REG_BANK_TX3 0x8090
5660 #define MDIO_TX3_TX_DRIVER 0x17
5661 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5662 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5663 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5664 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5665 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5666 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5667 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5668 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5669 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5671 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5672 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
5674 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5675 #define MDIO_BLOCK1_LANE_CTRL0 0x15
5676 #define MDIO_BLOCK1_LANE_CTRL1 0x16
5677 #define MDIO_BLOCK1_LANE_CTRL2 0x17
5678 #define MDIO_BLOCK1_LANE_PRBS 0x19
5680 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
5681 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
5682 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
5683 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
5684 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
5685 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
5686 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
5687 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
5688 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
5689 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
5691 #define MDIO_REG_BANK_GP_STATUS 0x8120
5692 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
5693 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
5694 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
5695 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
5696 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
5697 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
5698 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
5699 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
5700 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
5701 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
5702 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
5703 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
5704 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
5705 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
5706 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
5707 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
5708 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
5709 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
5710 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
5711 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
5712 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
5713 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
5714 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5715 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5716 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
5719 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
5720 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
5721 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
5722 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
5723 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
5725 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
5726 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
5727 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
5728 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
5729 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
5730 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
5731 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
5732 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
5733 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
5734 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
5735 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
5736 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
5737 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
5738 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
5739 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
5740 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
5741 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
5742 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
5743 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
5744 #define MDIO_SERDES_DIGITAL_MISC1 0x18
5745 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
5746 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
5747 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
5748 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
5749 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
5750 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
5751 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
5752 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
5753 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
5754 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
5755 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
5756 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
5757 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
5758 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
5759 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
5760 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
5761 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
5762 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
5764 #define MDIO_REG_BANK_OVER_1G 0x8320
5765 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
5766 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
5767 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5768 #define MDIO_OVER_1G_UP1 0x19
5769 #define MDIO_OVER_1G_UP1_2_5G 0x0001
5770 #define MDIO_OVER_1G_UP1_5G 0x0002
5771 #define MDIO_OVER_1G_UP1_6G 0x0004
5772 #define MDIO_OVER_1G_UP1_10G 0x0010
5773 #define MDIO_OVER_1G_UP1_10GH 0x0008
5774 #define MDIO_OVER_1G_UP1_12G 0x0020
5775 #define MDIO_OVER_1G_UP1_12_5G 0x0040
5776 #define MDIO_OVER_1G_UP1_13G 0x0080
5777 #define MDIO_OVER_1G_UP1_15G 0x0100
5778 #define MDIO_OVER_1G_UP1_16G 0x0200
5779 #define MDIO_OVER_1G_UP2 0x1A
5780 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5781 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5782 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5783 #define MDIO_OVER_1G_UP3 0x1B
5784 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5785 #define MDIO_OVER_1G_LP_UP1 0x1C
5786 #define MDIO_OVER_1G_LP_UP2 0x1D
5787 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5788 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5789 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5790 #define MDIO_OVER_1G_LP_UP3 0x1E
5792 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
5793 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5794 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5795 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5797 #define MDIO_REG_BANK_CL73_USERB0 0x8370
5798 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5799 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5800 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5801 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5802 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5803 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5805 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5806 #define MDIO_AER_BLOCK_AER_REG 0x1E
5808 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5809 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5810 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5811 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5812 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5813 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5814 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5815 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5816 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5817 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5818 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5819 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5820 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5821 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5822 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5823 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5824 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5825 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5826 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5827 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5828 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5829 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5830 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5831 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5832 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5833 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5834 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5835 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5836 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5837 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5838 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5839 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5840 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5841 Theotherbitsarereservedandshouldbezero*/
5842 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5845 #define MDIO_PMA_DEVAD 0x1
5847 #define MDIO_PMA_REG_CTRL 0x0
5848 #define MDIO_PMA_REG_STATUS 0x1
5849 #define MDIO_PMA_REG_10G_CTRL2 0x7
5850 #define MDIO_PMA_REG_RX_SD 0xa
5852 #define MDIO_PMA_REG_BCM_CTRL 0x0096
5853 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
5854 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5855 #define MDIO_PMA_REG_LASI_CTRL 0x9002
5856 #define MDIO_PMA_REG_RX_ALARM 0x9003
5857 #define MDIO_PMA_REG_TX_ALARM 0x9004
5858 #define MDIO_PMA_REG_LASI_STATUS 0x9005
5859 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5860 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5861 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5862 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5863 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5864 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
5865 #define MDIO_PMA_REG_GEN_CTRL 0xca10
5866 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5867 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5868 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5869 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
5870 #define MDIO_PMA_REG_ROM_VER1 0xca19
5871 #define MDIO_PMA_REG_ROM_VER2 0xca1a
5872 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5873 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5874 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
5875 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
5876 #define MDIO_PMA_REG_LRM_MODE 0xca3f
5877 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5878 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
5880 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
5881 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
5882 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
5883 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
5884 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
5885 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
5886 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
5887 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
5888 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
5889 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
5890 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
5891 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
5893 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
5894 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
5895 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
5896 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
5897 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
5898 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
5899 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
5900 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
5902 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
5903 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
5904 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
5906 #define MDIO_PMA_REG_7101_RESET 0xc000
5907 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5908 #define MDIO_PMA_REG_7101_VER1 0xc026
5909 #define MDIO_PMA_REG_7101_VER2 0xc027
5911 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
5912 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
5913 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
5914 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
5915 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
5916 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
5919 #define MDIO_WIS_DEVAD 0x2
5921 #define MDIO_WIS_REG_LASI_CNTL 0x9002
5922 #define MDIO_WIS_REG_LASI_STATUS 0x9005
5924 #define MDIO_PCS_DEVAD 0x3
5925 #define MDIO_PCS_REG_STATUS 0x0020
5926 #define MDIO_PCS_REG_LASI_STATUS 0x9005
5927 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5928 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5929 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5930 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5931 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5932 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5933 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5934 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5935 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5938 #define MDIO_XS_DEVAD 0x4
5939 #define MDIO_XS_PLL_SEQUENCER 0x8000
5940 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
5942 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
5943 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
5944 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
5945 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
5946 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
5948 #define MDIO_AN_DEVAD 0x7
5950 #define MDIO_AN_REG_CTRL 0x0000
5951 #define MDIO_AN_REG_STATUS 0x0001
5952 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5953 #define MDIO_AN_REG_ADV_PAUSE 0x0010
5954 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5955 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5956 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5957 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5958 #define MDIO_AN_REG_ADV 0x0011
5959 #define MDIO_AN_REG_ADV2 0x0012
5960 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5961 #define MDIO_AN_REG_MASTER_STATUS 0x0021
5963 #define MDIO_AN_REG_LINK_STATUS 0x8304
5964 #define MDIO_AN_REG_CL37_CL73 0x8370
5965 #define MDIO_AN_REG_CL37_AN 0xffe0
5966 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
5967 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
5969 #define MDIO_AN_REG_8073_2_5G 0x8329
5971 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
5972 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
5973 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
5974 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
5975 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
5976 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
5978 #define IGU_FUNC_BASE 0x0400
5980 #define IGU_ADDR_MSIX 0x0000
5981 #define IGU_ADDR_INT_ACK 0x0200
5982 #define IGU_ADDR_PROD_UPD 0x0201
5983 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
5984 #define IGU_ADDR_ATTN_BITS_SET 0x0203
5985 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
5986 #define IGU_ADDR_COALESCE_NOW 0x0205
5987 #define IGU_ADDR_SIMD_MASK 0x0206
5988 #define IGU_ADDR_SIMD_NOMASK 0x0207
5989 #define IGU_ADDR_MSI_CTL 0x0210
5990 #define IGU_ADDR_MSI_ADDR_LO 0x0211
5991 #define IGU_ADDR_MSI_ADDR_HI 0x0212
5992 #define IGU_ADDR_MSI_DATA 0x0213
5994 #define IGU_INT_ENABLE 0
5995 #define IGU_INT_DISABLE 1
5996 #define IGU_INT_NOP 2
5997 #define IGU_INT_NOP2 3
5999 #define COMMAND_REG_INT_ACK 0x0
6000 #define COMMAND_REG_PROD_UPD 0x4
6001 #define COMMAND_REG_ATTN_BITS_UPD 0x8
6002 #define COMMAND_REG_ATTN_BITS_SET 0xc
6003 #define COMMAND_REG_ATTN_BITS_CLR 0x10
6004 #define COMMAND_REG_COALESCE_NOW 0x14
6005 #define COMMAND_REG_SIMD_MASK 0x18
6006 #define COMMAND_REG_SIMD_NOMASK 0x1c
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