SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2009 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/kernel.h>
  21 #include <linux/device.h>  /* for dev_info() */
  22 #include <linux/timer.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/slab.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/pci.h>
  29 #include <linux/init.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/irq.h>
  36 #include <linux/delay.h>
  37 #include <asm/byteorder.h>
  38 #include <linux/time.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/mii.h>
  41 #include <linux/if_vlan.h>
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <net/ip6_checksum.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/crc32.h>
  48 #include <linux/crc32c.h>
  49 #include <linux/prefetch.h>
  50 #include <linux/zlib.h>
  51 #include <linux/io.h>
  52
  53
  54 #include "bnx2x.h"
  55 #include "bnx2x_init.h"
  56 #include "bnx2x_init_ops.h"
  57 #include "bnx2x_dump.h"
  58
  59 #define DRV_MODULE_VERSION      "1.48.105-1"
  60 #define DRV_MODULE_RELDATE      "2009/04/22"
  61 #define BNX2X_BC_VER            0x040200
  62
  63 #include <linux/firmware.h>
  64 #include "bnx2x_fw_file_hdr.h"
  65 /* FW files */
  66 #define FW_FILE_PREFIX_E1               "bnx2x-e1-"
  67 #define FW_FILE_PREFIX_E1H              "bnx2x-e1h-"
  68
  69 /* Time in jiffies before concluding the transmitter is hung */
  70 #define TX_TIMEOUT              (5*HZ)
  71
  72 static char version[] __devinitdata =
  73         "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
  74         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  75
  76 MODULE_AUTHOR("Eliezer Tamir");
  77 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
  78 MODULE_LICENSE("GPL");
  79 MODULE_VERSION(DRV_MODULE_VERSION);
  80
  81 static int multi_mode = 1;
  82 module_param(multi_mode, int, 0);
  83 MODULE_PARM_DESC(multi_mode, " Use per-CPU queues");
  84
  85 static int disable_tpa;
  86 module_param(disable_tpa, int, 0);
  87 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
  88
  89 static int int_mode;
  90 module_param(int_mode, int, 0);
  91 MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
  92
  93 static int poll;
  94 module_param(poll, int, 0);
  95 MODULE_PARM_DESC(poll, " Use polling (for debug)");
  96
  97 static int mrrs = -1;
  98 module_param(mrrs, int, 0);
  99 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 100
 101 static int debug;
 102 module_param(debug, int, 0);
 103 MODULE_PARM_DESC(debug, " Default debug msglevel");
 104
 105 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
 106
 107 static struct workqueue_struct *bnx2x_wq;
 108
 109 enum bnx2x_board_type {
 110         BCM57710 = 0,
 111         BCM57711 = 1,
 112         BCM57711E = 2,
 113 };
 114
 115 /* indexed by board_type, above */
 116 static struct {
 117         char *name;
 118 } board_info[] __devinitdata = {
 119         { "Broadcom NetXtreme II BCM57710 XGb" },
 120         { "Broadcom NetXtreme II BCM57711 XGb" },
 121         { "Broadcom NetXtreme II BCM57711E XGb" }
 122 };
 123
 124
 125 static const struct pci_device_id bnx2x_pci_tbl[] = {
 126         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
 127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
 128         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
 129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
 130         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
 131                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
 132         { 0 }
 133 };
 134
 135 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 136
 137 /****************************************************************************
 138 * General service functions
 139 ****************************************************************************/
 140
 141 /* used only at init
 142  * locking is done by mcp
 143  */
 144 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 145 {
 146         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 147         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 148         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 149                                PCICFG_VENDOR_ID_OFFSET);
 150 }
 151
 152 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 153 {
 154         u32 val;
 155
 156         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 157         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 158         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 159                                PCICFG_VENDOR_ID_OFFSET);
 160
 161         return val;
 162 }
 163
 164 static const u32 dmae_reg_go_c[] = {
 165         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
 166         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
 167         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
 168         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
 169 };
 170
 171 /* copy command into DMAE command memory and set DMAE command go */
 172 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
 173                             int idx)
 174 {
 175         u32 cmd_offset;
 176         int i;
 177
 178         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 179         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 180                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 181
 182                 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
 183                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
 184         }
 185         REG_WR(bp, dmae_reg_go_c[idx], 1);
 186 }
 187
 188 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 189                       u32 len32)
 190 {
 191         struct dmae_command *dmae = &bp->init_dmae;
 192         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 193         int cnt = 200;
 194
 195         if (!bp->dmae_ready) {
 196                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 197
 198                 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
 199                    "  using indirect\n", dst_addr, len32);
 200                 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 201                 return;
 202         }
 203
 204         mutex_lock(&bp->dmae_mutex);
 205
 206         memset(dmae, 0, sizeof(struct dmae_command));
 207
 208         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
 209                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
 210                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
 211 #ifdef __BIG_ENDIAN
 212                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
 213 #else
 214                         DMAE_CMD_ENDIANITY_DW_SWAP |
 215 #endif
 216                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
 217                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
 218         dmae->src_addr_lo = U64_LO(dma_addr);
 219         dmae->src_addr_hi = U64_HI(dma_addr);
 220         dmae->dst_addr_lo = dst_addr >> 2;
 221         dmae->dst_addr_hi = 0;
 222         dmae->len = len32;
 223         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 224         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 225         dmae->comp_val = DMAE_COMP_VAL;
 226
 227         DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
 228            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
 229                     "dst_addr [%x:%08x (%08x)]\n"
 230            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 231            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 232            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
 233            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
 234         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
 235            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
 236            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
 237
 238         *wb_comp = 0;
 239
 240         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 241
 242         udelay(5);
 243
 244         while (*wb_comp != DMAE_COMP_VAL) {
 245                 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
 246
 247                 if (!cnt) {
 248                         BNX2X_ERR("DMAE timeout!\n");
 249                         break;
 250                 }
 251                 cnt--;
 252                 /* adjust delay for emulation/FPGA */
 253                 if (CHIP_REV_IS_SLOW(bp))
 254                         msleep(100);
 255                 else
 256                         udelay(5);
 257         }
 258
 259         mutex_unlock(&bp->dmae_mutex);
 260 }
 261
 262 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 263 {
 264         struct dmae_command *dmae = &bp->init_dmae;
 265         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 266         int cnt = 200;
 267
 268         if (!bp->dmae_ready) {
 269                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 270                 int i;
 271
 272                 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
 273                    "  using indirect\n", src_addr, len32);
 274                 for (i = 0; i < len32; i++)
 275                         data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 276                 return;
 277         }
 278
 279         mutex_lock(&bp->dmae_mutex);
 280
 281         memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
 282         memset(dmae, 0, sizeof(struct dmae_command));
 283
 284         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
 285                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
 286                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
 287 #ifdef __BIG_ENDIAN
 288                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
 289 #else
 290                         DMAE_CMD_ENDIANITY_DW_SWAP |
 291 #endif
 292                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
 293                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
 294         dmae->src_addr_lo = src_addr >> 2;
 295         dmae->src_addr_hi = 0;
 296         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 297         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 298         dmae->len = len32;
 299         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 300         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 301         dmae->comp_val = DMAE_COMP_VAL;
 302
 303         DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
 304            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
 305                     "dst_addr [%x:%08x (%08x)]\n"
 306            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 307            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 308            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
 309            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
 310
 311         *wb_comp = 0;
 312
 313         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 314
 315         udelay(5);
 316
 317         while (*wb_comp != DMAE_COMP_VAL) {
 318
 319                 if (!cnt) {
 320                         BNX2X_ERR("DMAE timeout!\n");
 321                         break;
 322                 }
 323                 cnt--;
 324                 /* adjust delay for emulation/FPGA */
 325                 if (CHIP_REV_IS_SLOW(bp))
 326                         msleep(100);
 327                 else
 328                         udelay(5);
 329         }
 330         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
 331            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
 332            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
 333
 334         mutex_unlock(&bp->dmae_mutex);
 335 }
 336
 337 /* used only for slowpath so not inlined */
 338 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
 339 {
 340         u32 wb_write[2];
 341
 342         wb_write[0] = val_hi;
 343         wb_write[1] = val_lo;
 344         REG_WR_DMAE(bp, reg, wb_write, 2);
 345 }
 346
 347 #ifdef USE_WB_RD
 348 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
 349 {
 350         u32 wb_data[2];
 351
 352         REG_RD_DMAE(bp, reg, wb_data, 2);
 353
 354         return HILO_U64(wb_data[0], wb_data[1]);
 355 }
 356 #endif
 357
 358 static int bnx2x_mc_assert(struct bnx2x *bp)
 359 {
 360         char last_idx;
 361         int i, rc = 0;
 362         u32 row0, row1, row2, row3;
 363
 364         /* XSTORM */
 365         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 366                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 367         if (last_idx)
 368                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 369
 370         /* print the asserts */
 371         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 372
 373                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 374                               XSTORM_ASSERT_LIST_OFFSET(i));
 375                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 376                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 377                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 378                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 379                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 380                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 381
 382                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 383                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
 384                                   " 0x%08x 0x%08x 0x%08x\n",
 385                                   i, row3, row2, row1, row0);
 386                         rc++;
 387                 } else {
 388                         break;
 389                 }
 390         }
 391
 392         /* TSTORM */
 393         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 394                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 395         if (last_idx)
 396                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 397
 398         /* print the asserts */
 399         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 400
 401                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 402                               TSTORM_ASSERT_LIST_OFFSET(i));
 403                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 404                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 405                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 406                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 407                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 408                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 409
 410                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 411                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
 412                                   " 0x%08x 0x%08x 0x%08x\n",
 413                                   i, row3, row2, row1, row0);
 414                         rc++;
 415                 } else {
 416                         break;
 417                 }
 418         }
 419
 420         /* CSTORM */
 421         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 422                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 423         if (last_idx)
 424                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 425
 426         /* print the asserts */
 427         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 428
 429                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 430                               CSTORM_ASSERT_LIST_OFFSET(i));
 431                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 432                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 433                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 434                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 435                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 436                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 437
 438                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 439                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
 440                                   " 0x%08x 0x%08x 0x%08x\n",
 441                                   i, row3, row2, row1, row0);
 442                         rc++;
 443                 } else {
 444                         break;
 445                 }
 446         }
 447
 448         /* USTORM */
 449         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 450                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 451         if (last_idx)
 452                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 453
 454         /* print the asserts */
 455         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 456
 457                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 458                               USTORM_ASSERT_LIST_OFFSET(i));
 459                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 460                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 461                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 462                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 463                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 464                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 465
 466                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 467                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
 468                                   " 0x%08x 0x%08x 0x%08x\n",
 469                                   i, row3, row2, row1, row0);
 470                         rc++;
 471                 } else {
 472                         break;
 473                 }
 474         }
 475
 476         return rc;
 477 }
 478
 479 static void bnx2x_fw_dump(struct bnx2x *bp)
 480 {
 481         u32 mark, offset;
 482         __be32 data[9];
 483         int word;
 484
 485         mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
 486         mark = ((mark + 0x3) & ~0x3);
 487         printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
 488
 489         for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
 490                 for (word = 0; word < 8; word++)
 491                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
 492                                                   offset + 4*word));
 493                 data[8] = 0x0;
 494                 printk(KERN_CONT "%s", (char *)data);
 495         }
 496         for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
 497                 for (word = 0; word < 8; word++)
 498                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
 499                                                   offset + 4*word));
 500                 data[8] = 0x0;
 501                 printk(KERN_CONT "%s", (char *)data);
 502         }
 503         printk("\n" KERN_ERR PFX "end of fw dump\n");
 504 }
 505
 506 static void bnx2x_panic_dump(struct bnx2x *bp)
 507 {
 508         int i;
 509         u16 j, start, end;
 510
 511         bp->stats_state = STATS_STATE_DISABLED;
 512         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 513
 514         BNX2X_ERR("begin crash dump -----------------\n");
 515
 516         /* Indices */
 517         /* Common */
 518         BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
 519                   "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
 520                   "  spq_prod_idx(%u)\n",
 521                   bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
 522                   bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
 523
 524         /* Rx */
 525         for_each_rx_queue(bp, i) {
 526                 struct bnx2x_fastpath *fp = &bp->fp[i];
 527
 528                 BNX2X_ERR("fp%d: rx_bd_prod(%x)  rx_bd_cons(%x)"
 529                           "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
 530                           "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
 531                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 532                           le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
 533                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 534                 BNX2X_ERR("      rx_sge_prod(%x)  last_max_sge(%x)"
 535                           "  fp_u_idx(%x) *sb_u_idx(%x)\n",
 536                           fp->rx_sge_prod, fp->last_max_sge,
 537                           le16_to_cpu(fp->fp_u_idx),
 538                           fp->status_blk->u_status_block.status_block_index);
 539         }
 540
 541         /* Tx */
 542         for_each_tx_queue(bp, i) {
 543                 struct bnx2x_fastpath *fp = &bp->fp[i];
 544                 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
 545
 546                 BNX2X_ERR("fp%d: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
 547                           "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
 548                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
 549                           fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
 550                 BNX2X_ERR("      fp_c_idx(%x)  *sb_c_idx(%x)"
 551                           "  bd data(%x,%x)\n", le16_to_cpu(fp->fp_c_idx),
 552                           fp->status_blk->c_status_block.status_block_index,
 553                           hw_prods->packets_prod, hw_prods->bds_prod);
 554         }
 555
 556         /* Rings */
 557         /* Rx */
 558         for_each_rx_queue(bp, i) {
 559                 struct bnx2x_fastpath *fp = &bp->fp[i];
 560
 561                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
 562                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
 563                 for (j = start; j != end; j = RX_BD(j + 1)) {
 564                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
 565                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
 566
 567                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
 568                                   i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
 569                 }
 570
 571                 start = RX_SGE(fp->rx_sge_prod);
 572                 end = RX_SGE(fp->last_max_sge);
 573                 for (j = start; j != end; j = RX_SGE(j + 1)) {
 574                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
 575                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
 576
 577                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
 578                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
 579                 }
 580
 581                 start = RCQ_BD(fp->rx_comp_cons - 10);
 582                 end = RCQ_BD(fp->rx_comp_cons + 503);
 583                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
 584                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
 585
 586                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
 587                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
 588                 }
 589         }
 590
 591         /* Tx */
 592         for_each_tx_queue(bp, i) {
 593                 struct bnx2x_fastpath *fp = &bp->fp[i];
 594
 595                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
 596                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
 597                 for (j = start; j != end; j = TX_BD(j + 1)) {
 598                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
 599
 600                         BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
 601                                   i, j, sw_bd->skb, sw_bd->first_bd);
 602                 }
 603
 604                 start = TX_BD(fp->tx_bd_cons - 10);
 605                 end = TX_BD(fp->tx_bd_cons + 254);
 606                 for (j = start; j != end; j = TX_BD(j + 1)) {
 607                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
 608
 609                         BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
 610                                   i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
 611                 }
 612         }
 613
 614         bnx2x_fw_dump(bp);
 615         bnx2x_mc_assert(bp);
 616         BNX2X_ERR("end crash dump -----------------\n");
 617 }
 618
 619 static void bnx2x_int_enable(struct bnx2x *bp)
 620 {
 621         int port = BP_PORT(bp);
 622         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 623         u32 val = REG_RD(bp, addr);
 624         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
 625         int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
 626
 627         if (msix) {
 628                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 629                          HC_CONFIG_0_REG_INT_LINE_EN_0);
 630                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 631                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 632         } else if (msi) {
 633                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
 634                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 635                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 636                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 637         } else {
 638                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 639                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 640                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
 641                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 642
 643                 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
 644                    val, port, addr);
 645
 646                 REG_WR(bp, addr, val);
 647
 648                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
 649         }
 650
 651         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
 652            val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
 653
 654         REG_WR(bp, addr, val);
 655
 656         if (CHIP_IS_E1H(bp)) {
 657                 /* init leading/trailing edge */
 658                 if (IS_E1HMF(bp)) {
 659                         val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
 660                         if (bp->port.pmf)
 661                                 /* enable nig and gpio3 attention */
 662                                 val |= 0x1100;
 663                 } else
 664                         val = 0xffff;
 665
 666                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
 667                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
 668         }
 669 }
 670
 671 static void bnx2x_int_disable(struct bnx2x *bp)
 672 {
 673         int port = BP_PORT(bp);
 674         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 675         u32 val = REG_RD(bp, addr);
 676
 677         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 678                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 679                  HC_CONFIG_0_REG_INT_LINE_EN_0 |
 680                  HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 681
 682         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
 683            val, port, addr);
 684
 685         /* flush all outstanding writes */
 686         mmiowb();
 687
 688         REG_WR(bp, addr, val);
 689         if (REG_RD(bp, addr) != val)
 690                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 691
 692 }
 693
 694 static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
 695 {
 696         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
 697         int i, offset;
 698
 699         /* disable interrupt handling */
 700         atomic_inc(&bp->intr_sem);
 701         if (disable_hw)
 702                 /* prevent the HW from sending interrupts */
 703                 bnx2x_int_disable(bp);
 704
 705         /* make sure all ISRs are done */
 706         if (msix) {
 707                 synchronize_irq(bp->msix_table[0].vector);
 708                 offset = 1;
 709                 for_each_queue(bp, i)
 710                         synchronize_irq(bp->msix_table[i + offset].vector);
 711         } else
 712                 synchronize_irq(bp->pdev->irq);
 713
 714         /* make sure sp_task is not running */
 715         cancel_delayed_work(&bp->sp_task);
 716         flush_workqueue(bnx2x_wq);
 717 }
 718
 719 /* fast path */
 720
 721 /*
 722  * General service functions
 723  */
 724
 725 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
 726                                 u8 storm, u16 index, u8 op, u8 update)
 727 {
 728         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 729                        COMMAND_REG_INT_ACK);
 730         struct igu_ack_register igu_ack;
 731
 732         igu_ack.status_block_index = index;
 733         igu_ack.sb_id_and_flags =
 734                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
 735                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
 736                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
 737                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
 738
 739         DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
 740            (*(u32 *)&igu_ack), hc_addr);
 741         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
 742 }
 743
 744 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
 745 {
 746         struct host_status_block *fpsb = fp->status_blk;
 747         u16 rc = 0;
 748
 749         barrier(); /* status block is written to by the chip */
 750         if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
 751                 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
 752                 rc |= 1;
 753         }
 754         if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
 755                 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
 756                 rc |= 2;
 757         }
 758         return rc;
 759 }
 760
 761 static u16 bnx2x_ack_int(struct bnx2x *bp)
 762 {
 763         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 764                        COMMAND_REG_SIMD_MASK);
 765         u32 result = REG_RD(bp, hc_addr);
 766
 767         DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
 768            result, hc_addr);
 769
 770         return result;
 771 }
 772
 773
 774 /*
 775  * fast path service functions
 776  */
 777
 778 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
 779 {
 780         u16 tx_cons_sb;
 781
 782         /* Tell compiler that status block fields can change */
 783         barrier();
 784         tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb);
 785         return (fp->tx_pkt_cons != tx_cons_sb);
 786 }
 787
 788 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
 789 {
 790         /* Tell compiler that consumer and producer can change */
 791         barrier();
 792         return (fp->tx_pkt_prod != fp->tx_pkt_cons);
 793 }
 794
 795 /* free skb in the packet ring at pos idx
 796  * return idx of last bd freed
 797  */
 798 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
 799                              u16 idx)
 800 {
 801         struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
 802         struct eth_tx_bd *tx_bd;
 803         struct sk_buff *skb = tx_buf->skb;
 804         u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
 805         int nbd;
 806
 807         DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
 808            idx, tx_buf, skb);
 809
 810         /* unmap first bd */
 811         DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
 812         tx_bd = &fp->tx_desc_ring[bd_idx];
 813         pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
 814                          BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
 815
 816         nbd = le16_to_cpu(tx_bd->nbd) - 1;
 817         new_cons = nbd + tx_buf->first_bd;
 818 #ifdef BNX2X_STOP_ON_ERROR
 819         if (nbd > (MAX_SKB_FRAGS + 2)) {
 820                 BNX2X_ERR("BAD nbd!\n");
 821                 bnx2x_panic();
 822         }
 823 #endif
 824
 825         /* Skip a parse bd and the TSO split header bd
 826            since they have no mapping */
 827         if (nbd)
 828                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
 829
 830         if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
 831                                            ETH_TX_BD_FLAGS_TCP_CSUM |
 832                                            ETH_TX_BD_FLAGS_SW_LSO)) {
 833                 if (--nbd)
 834                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
 835                 tx_bd = &fp->tx_desc_ring[bd_idx];
 836                 /* is this a TSO split header bd? */
 837                 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
 838                         if (--nbd)
 839                                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
 840                 }
 841         }
 842
 843         /* now free frags */
 844         while (nbd > 0) {
 845
 846                 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
 847                 tx_bd = &fp->tx_desc_ring[bd_idx];
 848                 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
 849                                BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
 850                 if (--nbd)
 851                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
 852         }
 853
 854         /* release skb */
 855         WARN_ON(!skb);
 856         dev_kfree_skb(skb);
 857         tx_buf->first_bd = 0;
 858         tx_buf->skb = NULL;
 859
 860         return new_cons;
 861 }
 862
 863 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
 864 {
 865         s16 used;
 866         u16 prod;
 867         u16 cons;
 868
 869         barrier(); /* Tell compiler that prod and cons can change */
 870         prod = fp->tx_bd_prod;
 871         cons = fp->tx_bd_cons;
 872
 873         /* NUM_TX_RINGS = number of "next-page" entries
 874            It will be used as a threshold */
 875         used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
 876
 877 #ifdef BNX2X_STOP_ON_ERROR
 878         WARN_ON(used < 0);
 879         WARN_ON(used > fp->bp->tx_ring_size);
 880         WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
 881 #endif
 882
 883         return (s16)(fp->bp->tx_ring_size) - used;
 884 }
 885
 886 static void bnx2x_tx_int(struct bnx2x_fastpath *fp)
 887 {
 888         struct bnx2x *bp = fp->bp;
 889         struct netdev_queue *txq;
 890         u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
 891         int done = 0;
 892
 893 #ifdef BNX2X_STOP_ON_ERROR
 894         if (unlikely(bp->panic))
 895                 return;
 896 #endif
 897
 898         txq = netdev_get_tx_queue(bp->dev, fp->index);
 899         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
 900         sw_cons = fp->tx_pkt_cons;
 901
 902         while (sw_cons != hw_cons) {
 903                 u16 pkt_cons;
 904
 905                 pkt_cons = TX_BD(sw_cons);
 906
 907                 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
 908
 909                 DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
 910                    hw_cons, sw_cons, pkt_cons);
 911
 912 /*              if (NEXT_TX_IDX(sw_cons) != hw_cons) {
 913                         rmb();
 914                         prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
 915                 }
 916 */
 917                 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
 918                 sw_cons++;
 919                 done++;
 920         }
 921
 922         fp->tx_pkt_cons = sw_cons;
 923         fp->tx_bd_cons = bd_cons;
 924
 925         /* TBD need a thresh? */
 926         if (unlikely(netif_tx_queue_stopped(txq))) {
 927
 928                 __netif_tx_lock(txq, smp_processor_id());
 929
 930                 /* Need to make the tx_bd_cons update visible to start_xmit()
 931                  * before checking for netif_tx_queue_stopped().  Without the
 932                  * memory barrier, there is a small possibility that
 933                  * start_xmit() will miss it and cause the queue to be stopped
 934                  * forever.
 935                  */
 936                 smp_mb();
 937
 938                 if ((netif_tx_queue_stopped(txq)) &&
 939                     (bp->state == BNX2X_STATE_OPEN) &&
 940                     (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
 941                         netif_tx_wake_queue(txq);
 942
 943                 __netif_tx_unlock(txq);
 944         }
 945 }
 946
 947
 948 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
 949                            union eth_rx_cqe *rr_cqe)
 950 {
 951         struct bnx2x *bp = fp->bp;
 952         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
 953         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
 954
 955         DP(BNX2X_MSG_SP,
 956            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
 957            fp->index, cid, command, bp->state,
 958            rr_cqe->ramrod_cqe.ramrod_type);
 959
 960         bp->spq_left++;
 961
 962         if (fp->index) {
 963                 switch (command | fp->state) {
 964                 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
 965                                                 BNX2X_FP_STATE_OPENING):
 966                         DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
 967                            cid);
 968                         fp->state = BNX2X_FP_STATE_OPEN;
 969                         break;
 970
 971                 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
 972                         DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
 973                            cid);
 974                         fp->state = BNX2X_FP_STATE_HALTED;
 975                         break;
 976
 977                 default:
 978                         BNX2X_ERR("unexpected MC reply (%d)  "
 979                                   "fp->state is %x\n", command, fp->state);
 980                         break;
 981                 }
 982                 mb(); /* force bnx2x_wait_ramrod() to see the change */
 983                 return;
 984         }
 985
 986         switch (command | bp->state) {
 987         case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
 988                 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
 989                 bp->state = BNX2X_STATE_OPEN;
 990                 break;
 991
 992         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
 993                 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
 994                 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
 995                 fp->state = BNX2X_FP_STATE_HALTED;
 996                 break;
 997
 998         case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
 999                 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
1000                 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
1001                 break;
1002
1003
1004         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
1005         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
1006                 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
1007                 bp->set_mac_pending = 0;
1008                 break;
1009
1010         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
1011                 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
1012                 break;
1013
1014         default:
1015                 BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
1016                           command, bp->state);
1017                 break;
1018         }
1019         mb(); /* force bnx2x_wait_ramrod() to see the change */
1020 }
1021
1022 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
1023                                      struct bnx2x_fastpath *fp, u16 index)
1024 {
1025         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1026         struct page *page = sw_buf->page;
1027         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1028
1029         /* Skip "next page" elements */
1030         if (!page)
1031                 return;
1032
1033         pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
1034                        SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1035         __free_pages(page, PAGES_PER_SGE_SHIFT);
1036
1037         sw_buf->page = NULL;
1038         sge->addr_hi = 0;
1039         sge->addr_lo = 0;
1040 }
1041
1042 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1043                                            struct bnx2x_fastpath *fp, int last)
1044 {
1045         int i;
1046
1047         for (i = 0; i < last; i++)
1048                 bnx2x_free_rx_sge(bp, fp, i);
1049 }
1050
1051 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1052                                      struct bnx2x_fastpath *fp, u16 index)
1053 {
1054         struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1055         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1056         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1057         dma_addr_t mapping;
1058
1059         if (unlikely(page == NULL))
1060                 return -ENOMEM;
1061
1062         mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
1063                                PCI_DMA_FROMDEVICE);
1064         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1065                 __free_pages(page, PAGES_PER_SGE_SHIFT);
1066                 return -ENOMEM;
1067         }
1068
1069         sw_buf->page = page;
1070         pci_unmap_addr_set(sw_buf, mapping, mapping);
1071
1072         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1073         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1074
1075         return 0;
1076 }
1077
1078 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1079                                      struct bnx2x_fastpath *fp, u16 index)
1080 {
1081         struct sk_buff *skb;
1082         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1083         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1084         dma_addr_t mapping;
1085
1086         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1087         if (unlikely(skb == NULL))
1088                 return -ENOMEM;
1089
1090         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
1091                                  PCI_DMA_FROMDEVICE);
1092         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1093                 dev_kfree_skb(skb);
1094                 return -ENOMEM;
1095         }
1096
1097         rx_buf->skb = skb;
1098         pci_unmap_addr_set(rx_buf, mapping, mapping);
1099
1100         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1101         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1102
1103         return 0;
1104 }
1105
1106 /* note that we are not allocating a new skb,
1107  * we are just moving one from cons to prod
1108  * we are not creating a new mapping,
1109  * so there is no need to check for dma_mapping_error().
1110  */
1111 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1112                                struct sk_buff *skb, u16 cons, u16 prod)
1113 {
1114         struct bnx2x *bp = fp->bp;
1115         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1116         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1117         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1118         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1119
1120         pci_dma_sync_single_for_device(bp->pdev,
1121                                        pci_unmap_addr(cons_rx_buf, mapping),
1122                                        RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1123
1124         prod_rx_buf->skb = cons_rx_buf->skb;
1125         pci_unmap_addr_set(prod_rx_buf, mapping,
1126                            pci_unmap_addr(cons_rx_buf, mapping));
1127         *prod_bd = *cons_bd;
1128 }
1129
1130 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1131                                              u16 idx)
1132 {
1133         u16 last_max = fp->last_max_sge;
1134
1135         if (SUB_S16(idx, last_max) > 0)
1136                 fp->last_max_sge = idx;
1137 }
1138
1139 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1140 {
1141         int i, j;
1142
1143         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1144                 int idx = RX_SGE_CNT * i - 1;
1145
1146                 for (j = 0; j < 2; j++) {
1147                         SGE_MASK_CLEAR_BIT(fp, idx);
1148                         idx--;
1149                 }
1150         }
1151 }
1152
1153 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1154                                   struct eth_fast_path_rx_cqe *fp_cqe)
1155 {
1156         struct bnx2x *bp = fp->bp;
1157         u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1158                                      le16_to_cpu(fp_cqe->len_on_bd)) >>
1159                       SGE_PAGE_SHIFT;
1160         u16 last_max, last_elem, first_elem;
1161         u16 delta = 0;
1162         u16 i;
1163
1164         if (!sge_len)
1165                 return;
1166
1167         /* First mark all used pages */
1168         for (i = 0; i < sge_len; i++)
1169                 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1170
1171         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1172            sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1173
1174         /* Here we assume that the last SGE index is the biggest */
1175         prefetch((void *)(fp->sge_mask));
1176         bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1177
1178         last_max = RX_SGE(fp->last_max_sge);
1179         last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1180         first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1181
1182         /* If ring is not full */
1183         if (last_elem + 1 != first_elem)
1184                 last_elem++;
1185
1186         /* Now update the prod */
1187         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1188                 if (likely(fp->sge_mask[i]))
1189                         break;
1190
1191                 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1192                 delta += RX_SGE_MASK_ELEM_SZ;
1193         }
1194
1195         if (delta > 0) {
1196                 fp->rx_sge_prod += delta;
1197                 /* clear page-end entries */
1198                 bnx2x_clear_sge_mask_next_elems(fp);
1199         }
1200
1201         DP(NETIF_MSG_RX_STATUS,
1202            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
1203            fp->last_max_sge, fp->rx_sge_prod);
1204 }
1205
1206 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1207 {
1208         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1209         memset(fp->sge_mask, 0xff,
1210                (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1211
1212         /* Clear the two last indices in the page to 1:
1213            these are the indices that correspond to the "next" element,
1214            hence will never be indicated and should be removed from
1215            the calculations. */
1216         bnx2x_clear_sge_mask_next_elems(fp);
1217 }
1218
1219 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1220                             struct sk_buff *skb, u16 cons, u16 prod)
1221 {
1222         struct bnx2x *bp = fp->bp;
1223         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1224         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1225         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1226         dma_addr_t mapping;
1227
1228         /* move empty skb from pool to prod and map it */
1229         prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1230         mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1231                                  bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1232         pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1233
1234         /* move partial skb from cons to pool (don't unmap yet) */
1235         fp->tpa_pool[queue] = *cons_rx_buf;
1236
1237         /* mark bin state as start - print error if current state != stop */
1238         if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1239                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1240
1241         fp->tpa_state[queue] = BNX2X_TPA_START;
1242
1243         /* point prod_bd to new skb */
1244         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1245         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1246
1247 #ifdef BNX2X_STOP_ON_ERROR
1248         fp->tpa_queue_used |= (1 << queue);
1249 #ifdef __powerpc64__
1250         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1251 #else
1252         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1253 #endif
1254            fp->tpa_queue_used);
1255 #endif
1256 }
1257
1258 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1259                                struct sk_buff *skb,
1260                                struct eth_fast_path_rx_cqe *fp_cqe,
1261                                u16 cqe_idx)
1262 {
1263         struct sw_rx_page *rx_pg, old_rx_pg;
1264         u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1265         u32 i, frag_len, frag_size, pages;
1266         int err;
1267         int j;
1268
1269         frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1270         pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
1271
1272         /* This is needed in order to enable forwarding support */
1273         if (frag_size)
1274                 skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
1275                                                max(frag_size, (u32)len_on_bd));
1276
1277 #ifdef BNX2X_STOP_ON_ERROR
1278         if (pages >
1279             min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
1280                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1281                           pages, cqe_idx);
1282                 BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
1283                           fp_cqe->pkt_len, len_on_bd);
1284                 bnx2x_panic();
1285                 return -EINVAL;
1286         }
1287 #endif
1288
1289         /* Run through the SGL and compose the fragmented skb */
1290         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1291                 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1292
1293                 /* FW gives the indices of the SGE as if the ring is an array
1294                    (meaning that "next" element will consume 2 indices) */
1295                 frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
1296                 rx_pg = &fp->rx_page_ring[sge_idx];
1297                 old_rx_pg = *rx_pg;
1298
1299                 /* If we fail to allocate a substitute page, we simply stop
1300                    where we are and drop the whole packet */
1301                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1302                 if (unlikely(err)) {
1303                         fp->eth_q_stats.rx_skb_alloc_failed++;
1304                         return err;
1305                 }
1306
1307                 /* Unmap the page as we r going to pass it to the stack */
1308                 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1309                               SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1310
1311                 /* Add one frag and update the appropriate fields in the skb */
1312                 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1313
1314                 skb->data_len += frag_len;
1315                 skb->truesize += frag_len;
1316                 skb->len += frag_len;
1317
1318                 frag_size -= frag_len;
1319         }
1320
1321         return 0;
1322 }
1323
1324 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1325                            u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1326                            u16 cqe_idx)
1327 {
1328         struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1329         struct sk_buff *skb = rx_buf->skb;
1330         /* alloc new skb */
1331         struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1332
1333         /* Unmap skb in the pool anyway, as we are going to change
1334            pool entry status to BNX2X_TPA_STOP even if new skb allocation
1335            fails. */
1336         pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1337                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1338
1339         if (likely(new_skb)) {
1340                 /* fix ip xsum and give it to the stack */
1341                 /* (no need to map the new skb) */
1342 #ifdef BCM_VLAN
1343                 int is_vlan_cqe =
1344                         (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1345                          PARSING_FLAGS_VLAN);
1346                 int is_not_hwaccel_vlan_cqe =
1347                         (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
1348 #endif
1349
1350                 prefetch(skb);
1351                 prefetch(((char *)(skb)) + 128);
1352
1353 #ifdef BNX2X_STOP_ON_ERROR
1354                 if (pad + len > bp->rx_buf_size) {
1355                         BNX2X_ERR("skb_put is about to fail...  "
1356                                   "pad %d  len %d  rx_buf_size %d\n",
1357                                   pad, len, bp->rx_buf_size);
1358                         bnx2x_panic();
1359                         return;
1360                 }
1361 #endif
1362
1363                 skb_reserve(skb, pad);
1364                 skb_put(skb, len);
1365
1366                 skb->protocol = eth_type_trans(skb, bp->dev);
1367                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1368
1369                 {
1370                         struct iphdr *iph;
1371
1372                         iph = (struct iphdr *)skb->data;
1373 #ifdef BCM_VLAN
1374                         /* If there is no Rx VLAN offloading -
1375                            take VLAN tag into an account */
1376                         if (unlikely(is_not_hwaccel_vlan_cqe))
1377                                 iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
1378 #endif
1379                         iph->check = 0;
1380                         iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1381                 }
1382
1383                 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1384                                          &cqe->fast_path_cqe, cqe_idx)) {
1385 #ifdef BCM_VLAN
1386                         if ((bp->vlgrp != NULL) && is_vlan_cqe &&
1387                             (!is_not_hwaccel_vlan_cqe))
1388                                 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1389                                                 le16_to_cpu(cqe->fast_path_cqe.
1390                                                             vlan_tag));
1391                         else
1392 #endif
1393                                 netif_receive_skb(skb);
1394                 } else {
1395                         DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1396                            " - dropping packet!\n");
1397                         dev_kfree_skb(skb);
1398                 }
1399
1400
1401                 /* put new skb in bin */
1402                 fp->tpa_pool[queue].skb = new_skb;
1403
1404         } else {
1405                 /* else drop the packet and keep the buffer in the bin */
1406                 DP(NETIF_MSG_RX_STATUS,
1407                    "Failed to allocate new skb - dropping packet!\n");
1408                 fp->eth_q_stats.rx_skb_alloc_failed++;
1409         }
1410
1411         fp->tpa_state[queue] = BNX2X_TPA_STOP;
1412 }
1413
1414 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1415                                         struct bnx2x_fastpath *fp,
1416                                         u16 bd_prod, u16 rx_comp_prod,
1417                                         u16 rx_sge_prod)
1418 {
1419         struct ustorm_eth_rx_producers rx_prods = {0};
1420         int i;
1421
1422         /* Update producers */
1423         rx_prods.bd_prod = bd_prod;
1424         rx_prods.cqe_prod = rx_comp_prod;
1425         rx_prods.sge_prod = rx_sge_prod;
1426
1427         /*
1428          * Make sure that the BD and SGE data is updated before updating the
1429          * producers since FW might read the BD/SGE right after the producer
1430          * is updated.
1431          * This is only applicable for weak-ordered memory model archs such
1432          * as IA-64. The following barrier is also mandatory since FW will
1433          * assumes BDs must have buffers.
1434          */
1435         wmb();
1436
1437         for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
1438                 REG_WR(bp, BAR_USTRORM_INTMEM +
1439                        USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4,
1440                        ((u32 *)&rx_prods)[i]);
1441
1442         mmiowb(); /* keep prod updates ordered */
1443
1444         DP(NETIF_MSG_RX_STATUS,
1445            "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
1446            fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
1447 }
1448
1449 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1450 {
1451         struct bnx2x *bp = fp->bp;
1452         u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1453         u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1454         int rx_pkt = 0;
1455
1456 #ifdef BNX2X_STOP_ON_ERROR
1457         if (unlikely(bp->panic))
1458                 return 0;
1459 #endif
1460
1461         /* CQ "next element" is of the size of the regular element,
1462            that's why it's ok here */
1463         hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1464         if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1465                 hw_comp_cons++;
1466
1467         bd_cons = fp->rx_bd_cons;
1468         bd_prod = fp->rx_bd_prod;
1469         bd_prod_fw = bd_prod;
1470         sw_comp_cons = fp->rx_comp_cons;
1471         sw_comp_prod = fp->rx_comp_prod;
1472
1473         /* Memory barrier necessary as speculative reads of the rx
1474          * buffer can be ahead of the index in the status block
1475          */
1476         rmb();
1477
1478         DP(NETIF_MSG_RX_STATUS,
1479            "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
1480            fp->index, hw_comp_cons, sw_comp_cons);
1481
1482         while (sw_comp_cons != hw_comp_cons) {
1483                 struct sw_rx_bd *rx_buf = NULL;
1484                 struct sk_buff *skb;
1485                 union eth_rx_cqe *cqe;
1486                 u8 cqe_fp_flags;
1487                 u16 len, pad;
1488
1489                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1490                 bd_prod = RX_BD(bd_prod);
1491                 bd_cons = RX_BD(bd_cons);
1492
1493                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1494                 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1495
1496                 DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
1497                    "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
1498                    cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1499                    le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
1500                    le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1501                    le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1502
1503                 /* is this a slowpath msg? */
1504                 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1505                         bnx2x_sp_event(fp, cqe);
1506                         goto next_cqe;
1507
1508                 /* this is an rx packet */
1509                 } else {
1510                         rx_buf = &fp->rx_buf_ring[bd_cons];
1511                         skb = rx_buf->skb;
1512                         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1513                         pad = cqe->fast_path_cqe.placement_offset;
1514
1515                         /* If CQE is marked both TPA_START and TPA_END
1516                            it is a non-TPA CQE */
1517                         if ((!fp->disable_tpa) &&
1518                             (TPA_TYPE(cqe_fp_flags) !=
1519                                         (TPA_TYPE_START | TPA_TYPE_END))) {
1520                                 u16 queue = cqe->fast_path_cqe.queue_index;
1521
1522                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1523                                         DP(NETIF_MSG_RX_STATUS,
1524                                            "calling tpa_start on queue %d\n",
1525                                            queue);
1526
1527                                         bnx2x_tpa_start(fp, queue, skb,
1528                                                         bd_cons, bd_prod);
1529                                         goto next_rx;
1530                                 }
1531
1532                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1533                                         DP(NETIF_MSG_RX_STATUS,
1534                                            "calling tpa_stop on queue %d\n",
1535                                            queue);
1536
1537                                         if (!BNX2X_RX_SUM_FIX(cqe))
1538                                                 BNX2X_ERR("STOP on none TCP "
1539                                                           "data\n");
1540
1541                                         /* This is a size of the linear data
1542                                            on this skb */
1543                                         len = le16_to_cpu(cqe->fast_path_cqe.
1544                                                                 len_on_bd);
1545                                         bnx2x_tpa_stop(bp, fp, queue, pad,
1546                                                     len, cqe, comp_ring_cons);
1547 #ifdef BNX2X_STOP_ON_ERROR
1548                                         if (bp->panic)
1549                                                 return 0;
1550 #endif
1551
1552                                         bnx2x_update_sge_prod(fp,
1553                                                         &cqe->fast_path_cqe);
1554                                         goto next_cqe;
1555                                 }
1556                         }
1557
1558                         pci_dma_sync_single_for_device(bp->pdev,
1559                                         pci_unmap_addr(rx_buf, mapping),
1560                                                        pad + RX_COPY_THRESH,
1561                                                        PCI_DMA_FROMDEVICE);
1562                         prefetch(skb);
1563                         prefetch(((char *)(skb)) + 128);
1564
1565                         /* is this an error packet? */
1566                         if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1567                                 DP(NETIF_MSG_RX_ERR,
1568                                    "ERROR  flags %x  rx packet %u\n",
1569                                    cqe_fp_flags, sw_comp_cons);
1570                                 fp->eth_q_stats.rx_err_discard_pkt++;
1571                                 goto reuse_rx;
1572                         }
1573
1574                         /* Since we don't have a jumbo ring
1575                          * copy small packets if mtu > 1500
1576                          */
1577                         if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1578                             (len <= RX_COPY_THRESH)) {
1579                                 struct sk_buff *new_skb;
1580
1581                                 new_skb = netdev_alloc_skb(bp->dev,
1582                                                            len + pad);
1583                                 if (new_skb == NULL) {
1584                                         DP(NETIF_MSG_RX_ERR,
1585                                            "ERROR  packet dropped "
1586                                            "because of alloc failure\n");
1587                                         fp->eth_q_stats.rx_skb_alloc_failed++;
1588                                         goto reuse_rx;
1589                                 }
1590
1591                                 /* aligned copy */
1592                                 skb_copy_from_linear_data_offset(skb, pad,
1593                                                     new_skb->data + pad, len);
1594                                 skb_reserve(new_skb, pad);
1595                                 skb_put(new_skb, len);
1596
1597                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1598
1599                                 skb = new_skb;
1600
1601                         } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1602                                 pci_unmap_single(bp->pdev,
1603                                         pci_unmap_addr(rx_buf, mapping),
1604                                                  bp->rx_buf_size,
1605                                                  PCI_DMA_FROMDEVICE);
1606                                 skb_reserve(skb, pad);
1607                                 skb_put(skb, len);
1608
1609                         } else {
1610                                 DP(NETIF_MSG_RX_ERR,
1611                                    "ERROR  packet dropped because "
1612                                    "of alloc failure\n");
1613                                 fp->eth_q_stats.rx_skb_alloc_failed++;
1614 reuse_rx:
1615                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1616                                 goto next_rx;
1617                         }
1618
1619                         skb->protocol = eth_type_trans(skb, bp->dev);
1620
1621                         skb->ip_summed = CHECKSUM_NONE;
1622                         if (bp->rx_csum) {
1623                                 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1624                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1625                                 else
1626                                         fp->eth_q_stats.hw_csum_err++;
1627                         }
1628                 }
1629
1630                 skb_record_rx_queue(skb, fp->index);
1631 #ifdef BCM_VLAN
1632                 if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
1633                     (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1634                      PARSING_FLAGS_VLAN))
1635                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1636                                 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1637                 else
1638 #endif
1639                         netif_receive_skb(skb);
1640
1641
1642 next_rx:
1643                 rx_buf->skb = NULL;
1644
1645                 bd_cons = NEXT_RX_IDX(bd_cons);
1646                 bd_prod = NEXT_RX_IDX(bd_prod);
1647                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1648                 rx_pkt++;
1649 next_cqe:
1650                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1651                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1652
1653                 if (rx_pkt == budget)
1654                         break;
1655         } /* while */
1656
1657         fp->rx_bd_cons = bd_cons;
1658         fp->rx_bd_prod = bd_prod_fw;
1659         fp->rx_comp_cons = sw_comp_cons;
1660         fp->rx_comp_prod = sw_comp_prod;
1661
1662         /* Update producers */
1663         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1664                              fp->rx_sge_prod);
1665
1666         fp->rx_pkt += rx_pkt;
1667         fp->rx_calls++;
1668
1669         return rx_pkt;
1670 }
1671
1672 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1673 {
1674         struct bnx2x_fastpath *fp = fp_cookie;
1675         struct bnx2x *bp = fp->bp;
1676         int index = fp->index;
1677
1678         /* Return here if interrupt is disabled */
1679         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1680                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1681                 return IRQ_HANDLED;
1682         }
1683
1684         DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1685            index, fp->sb_id);
1686         bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1687
1688 #ifdef BNX2X_STOP_ON_ERROR
1689         if (unlikely(bp->panic))
1690                 return IRQ_HANDLED;
1691 #endif
1692
1693         prefetch(fp->rx_cons_sb);
1694         prefetch(fp->tx_cons_sb);
1695         prefetch(&fp->status_blk->c_status_block.status_block_index);
1696         prefetch(&fp->status_blk->u_status_block.status_block_index);
1697
1698         napi_schedule(&bnx2x_fp(bp, index, napi));
1699
1700         return IRQ_HANDLED;
1701 }
1702
1703 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1704 {
1705         struct bnx2x *bp = netdev_priv(dev_instance);
1706         u16 status = bnx2x_ack_int(bp);
1707         u16 mask;
1708
1709         /* Return here if interrupt is shared and it's not for us */
1710         if (unlikely(status == 0)) {
1711                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1712                 return IRQ_NONE;
1713         }
1714         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1715
1716         /* Return here if interrupt is disabled */
1717         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1718                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1719                 return IRQ_HANDLED;
1720         }
1721
1722 #ifdef BNX2X_STOP_ON_ERROR
1723         if (unlikely(bp->panic))
1724                 return IRQ_HANDLED;
1725 #endif
1726
1727         mask = 0x2 << bp->fp[0].sb_id;
1728         if (status & mask) {
1729                 struct bnx2x_fastpath *fp = &bp->fp[0];
1730
1731                 prefetch(fp->rx_cons_sb);
1732                 prefetch(fp->tx_cons_sb);
1733                 prefetch(&fp->status_blk->c_status_block.status_block_index);
1734                 prefetch(&fp->status_blk->u_status_block.status_block_index);
1735
1736                 napi_schedule(&bnx2x_fp(bp, 0, napi));
1737
1738                 status &= ~mask;
1739         }
1740
1741
1742         if (unlikely(status & 0x1)) {
1743                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1744
1745                 status &= ~0x1;
1746                 if (!status)
1747                         return IRQ_HANDLED;
1748         }
1749
1750         if (status)
1751                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1752                    status);
1753
1754         return IRQ_HANDLED;
1755 }
1756
1757 /* end of fast path */
1758
1759 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1760
1761 /* Link */
1762
1763 /*
1764  * General service functions
1765  */
1766
1767 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1768 {
1769         u32 lock_status;
1770         u32 resource_bit = (1 << resource);
1771         int func = BP_FUNC(bp);
1772         u32 hw_lock_control_reg;
1773         int cnt;
1774
1775         /* Validating that the resource is within range */
1776         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1777                 DP(NETIF_MSG_HW,
1778                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1779                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1780                 return -EINVAL;
1781         }
1782
1783         if (func <= 5) {
1784                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1785         } else {
1786                 hw_lock_control_reg =
1787                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1788         }
1789
1790         /* Validating that the resource is not already taken */
1791         lock_status = REG_RD(bp, hw_lock_control_reg);
1792         if (lock_status & resource_bit) {
1793                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1794                    lock_status, resource_bit);
1795                 return -EEXIST;
1796         }
1797
1798         /* Try for 5 second every 5ms */
1799         for (cnt = 0; cnt < 1000; cnt++) {
1800                 /* Try to acquire the lock */
1801                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1802                 lock_status = REG_RD(bp, hw_lock_control_reg);
1803                 if (lock_status & resource_bit)
1804                         return 0;
1805
1806                 msleep(5);
1807         }
1808         DP(NETIF_MSG_HW, "Timeout\n");
1809         return -EAGAIN;
1810 }
1811
1812 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1813 {
1814         u32 lock_status;
1815         u32 resource_bit = (1 << resource);
1816         int func = BP_FUNC(bp);
1817         u32 hw_lock_control_reg;
1818
1819         /* Validating that the resource is within range */
1820         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1821                 DP(NETIF_MSG_HW,
1822                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1823                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1824                 return -EINVAL;
1825         }
1826
1827         if (func <= 5) {
1828                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1829         } else {
1830                 hw_lock_control_reg =
1831                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1832         }
1833
1834         /* Validating that the resource is currently taken */
1835         lock_status = REG_RD(bp, hw_lock_control_reg);
1836         if (!(lock_status & resource_bit)) {
1837                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1838                    lock_status, resource_bit);
1839                 return -EFAULT;
1840         }
1841
1842         REG_WR(bp, hw_lock_control_reg, resource_bit);
1843         return 0;
1844 }
1845
1846 /* HW Lock for shared dual port PHYs */
1847 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1848 {
1849         mutex_lock(&bp->port.phy_mutex);
1850
1851         if (bp->port.need_hw_lock)
1852                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1853 }
1854
1855 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1856 {
1857         if (bp->port.need_hw_lock)
1858                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1859
1860         mutex_unlock(&bp->port.phy_mutex);
1861 }
1862
1863 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1864 {
1865         /* The GPIO should be swapped if swap register is set and active */
1866         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1867                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1868         int gpio_shift = gpio_num +
1869                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1870         u32 gpio_mask = (1 << gpio_shift);
1871         u32 gpio_reg;
1872         int value;
1873
1874         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1875                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1876                 return -EINVAL;
1877         }
1878
1879         /* read GPIO value */
1880         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1881
1882         /* get the requested pin value */
1883         if ((gpio_reg & gpio_mask) == gpio_mask)
1884                 value = 1;
1885         else
1886                 value = 0;
1887
1888         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
1889
1890         return value;
1891 }
1892
1893 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1894 {
1895         /* The GPIO should be swapped if swap register is set and active */
1896         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1897                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1898         int gpio_shift = gpio_num +
1899                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1900         u32 gpio_mask = (1 << gpio_shift);
1901         u32 gpio_reg;
1902
1903         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1904                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1905                 return -EINVAL;
1906         }
1907
1908         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1909         /* read GPIO and mask except the float bits */
1910         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1911
1912         switch (mode) {
1913         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1914                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1915                    gpio_num, gpio_shift);
1916                 /* clear FLOAT and set CLR */
1917                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1918                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1919                 break;
1920
1921         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1922                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1923                    gpio_num, gpio_shift);
1924                 /* clear FLOAT and set SET */
1925                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1926                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1927                 break;
1928
1929         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1930                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1931                    gpio_num, gpio_shift);
1932                 /* set FLOAT */
1933                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1934                 break;
1935
1936         default:
1937                 break;
1938         }
1939
1940         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1941         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1942
1943         return 0;
1944 }
1945
1946 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1947 {
1948         /* The GPIO should be swapped if swap register is set and active */
1949         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1950                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1951         int gpio_shift = gpio_num +
1952                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1953         u32 gpio_mask = (1 << gpio_shift);
1954         u32 gpio_reg;
1955
1956         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1957                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1958                 return -EINVAL;
1959         }
1960
1961         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1962         /* read GPIO int */
1963         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1964
1965         switch (mode) {
1966         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1967                 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1968                                    "output low\n", gpio_num, gpio_shift);
1969                 /* clear SET and set CLR */
1970                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1971                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1972                 break;
1973
1974         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1975                 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1976                                    "output high\n", gpio_num, gpio_shift);
1977                 /* clear CLR and set SET */
1978                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1979                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1980                 break;
1981
1982         default:
1983                 break;
1984         }
1985
1986         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1987         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1988
1989         return 0;
1990 }
1991
1992 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1993 {
1994         u32 spio_mask = (1 << spio_num);
1995         u32 spio_reg;
1996
1997         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1998             (spio_num > MISC_REGISTERS_SPIO_7)) {
1999                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2000                 return -EINVAL;
2001         }
2002
2003         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2004         /* read SPIO and mask except the float bits */
2005         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2006
2007         switch (mode) {
2008         case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2009                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2010                 /* clear FLOAT and set CLR */
2011                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2012                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2013                 break;
2014
2015         case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2016                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2017                 /* clear FLOAT and set SET */
2018                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2019                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2020                 break;
2021
2022         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2023                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2024                 /* set FLOAT */
2025                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2026                 break;
2027
2028         default:
2029                 break;
2030         }
2031
2032         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2033         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2034
2035         return 0;
2036 }
2037
2038 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
2039 {
2040         switch (bp->link_vars.ieee_fc &
2041                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2042         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2043                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
2044                                           ADVERTISED_Pause);
2045                 break;
2046
2047         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2048                 bp->port.advertising |= (ADVERTISED_Asym_Pause |
2049                                          ADVERTISED_Pause);
2050                 break;
2051
2052         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2053                 bp->port.advertising |= ADVERTISED_Asym_Pause;
2054                 break;
2055
2056         default:
2057                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
2058                                           ADVERTISED_Pause);
2059                 break;
2060         }
2061 }
2062
2063 static void bnx2x_link_report(struct bnx2x *bp)
2064 {
2065         if (bp->link_vars.link_up) {
2066                 if (bp->state == BNX2X_STATE_OPEN)
2067                         netif_carrier_on(bp->dev);
2068                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
2069
2070                 printk("%d Mbps ", bp->link_vars.line_speed);
2071
2072                 if (bp->link_vars.duplex == DUPLEX_FULL)
2073                         printk("full duplex");
2074                 else
2075                         printk("half duplex");
2076
2077                 if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
2078                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
2079                                 printk(", receive ");
2080                                 if (bp->link_vars.flow_ctrl &
2081                                     BNX2X_FLOW_CTRL_TX)
2082                                         printk("& transmit ");
2083                         } else {
2084                                 printk(", transmit ");
2085                         }
2086                         printk("flow control ON");
2087                 }
2088                 printk("\n");
2089
2090         } else { /* link_down */
2091                 netif_carrier_off(bp->dev);
2092                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
2093         }
2094 }
2095
2096 static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2097 {
2098         if (!BP_NOMCP(bp)) {
2099                 u8 rc;
2100
2101                 /* Initialize link parameters structure variables */
2102                 /* It is recommended to turn off RX FC for jumbo frames
2103                    for better performance */
2104                 if (IS_E1HMF(bp))
2105                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2106                 else if (bp->dev->mtu > 5000)
2107                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2108                 else
2109                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2110
2111                 bnx2x_acquire_phy_lock(bp);
2112
2113                 if (load_mode == LOAD_DIAG)
2114                         bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
2115
2116                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2117
2118                 bnx2x_release_phy_lock(bp);
2119
2120                 bnx2x_calc_fc_adv(bp);
2121
2122                 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2123                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2124                         bnx2x_link_report(bp);
2125                 }
2126
2127                 return rc;
2128         }
2129         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2130         return -EINVAL;
2131 }
2132
2133 static void bnx2x_link_set(struct bnx2x *bp)
2134 {
2135         if (!BP_NOMCP(bp)) {
2136                 bnx2x_acquire_phy_lock(bp);
2137                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2138                 bnx2x_release_phy_lock(bp);
2139
2140                 bnx2x_calc_fc_adv(bp);
2141         } else
2142                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2143 }
2144
2145 static void bnx2x__link_reset(struct bnx2x *bp)
2146 {
2147         if (!BP_NOMCP(bp)) {
2148                 bnx2x_acquire_phy_lock(bp);
2149                 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2150                 bnx2x_release_phy_lock(bp);
2151         } else
2152                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2153 }
2154
2155 static u8 bnx2x_link_test(struct bnx2x *bp)
2156 {
2157         u8 rc;
2158
2159         bnx2x_acquire_phy_lock(bp);
2160         rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2161         bnx2x_release_phy_lock(bp);
2162
2163         return rc;
2164 }
2165
2166 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2167 {
2168         u32 r_param = bp->link_vars.line_speed / 8;
2169         u32 fair_periodic_timeout_usec;
2170         u32 t_fair;
2171
2172         memset(&(bp->cmng.rs_vars), 0,
2173                sizeof(struct rate_shaping_vars_per_port));
2174         memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2175
2176         /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2177         bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2178
2179         /* this is the threshold below which no timer arming will occur
2180            1.25 coefficient is for the threshold to be a little bigger
2181            than the real time, to compensate for timer in-accuracy */
2182         bp->cmng.rs_vars.rs_threshold =
2183                                 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2184
2185         /* resolution of fairness timer */
2186         fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2187         /* for 10G it is 1000usec. for 1G it is 10000usec. */
2188         t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2189
2190         /* this is the threshold below which we won't arm the timer anymore */
2191         bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2192
2193         /* we multiply by 1e3/8 to get bytes/msec.
2194            We don't want the credits to pass a credit
2195            of the t_fair*FAIR_MEM (algorithm resolution) */
2196         bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2197         /* since each tick is 4 usec */
2198         bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2199 }
2200
2201 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
2202 {
2203         struct rate_shaping_vars_per_vn m_rs_vn;
2204         struct fairness_vars_per_vn m_fair_vn;
2205         u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2206         u16 vn_min_rate, vn_max_rate;
2207         int i;
2208
2209         /* If function is hidden - set min and max to zeroes */
2210         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2211                 vn_min_rate = 0;
2212                 vn_max_rate = 0;
2213
2214         } else {
2215                 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2216                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2217                 /* If fairness is enabled (not all min rates are zeroes) and
2218                    if current min rate is zero - set it to 1.
2219                    This is a requirement of the algorithm. */
2220                 if (bp->vn_weight_sum && (vn_min_rate == 0))
2221                         vn_min_rate = DEF_MIN_RATE;
2222                 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2223                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2224         }
2225
2226         DP(NETIF_MSG_IFUP,
2227            "func %d: vn_min_rate=%d  vn_max_rate=%d  vn_weight_sum=%d\n",
2228            func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2229
2230         memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2231         memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2232
2233         /* global vn counter - maximal Mbps for this vn */
2234         m_rs_vn.vn_counter.rate = vn_max_rate;
2235
2236         /* quota - number of bytes transmitted in this period */
2237         m_rs_vn.vn_counter.quota =
2238                                 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2239
2240         if (bp->vn_weight_sum) {
2241                 /* credit for each period of the fairness algorithm:
2242                    number of bytes in T_FAIR (the vn share the port rate).
2243                    vn_weight_sum should not be larger than 10000, thus
2244                    T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2245                    than zero */
2246                 m_fair_vn.vn_credit_delta =
2247                         max((u32)(vn_min_rate * (T_FAIR_COEF /
2248                                                  (8 * bp->vn_weight_sum))),
2249                             (u32)(bp->cmng.fair_vars.fair_threshold * 2));
2250                 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2251                    m_fair_vn.vn_credit_delta);
2252         }
2253
2254         /* Store it to internal memory */
2255         for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2256                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2257                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2258                        ((u32 *)(&m_rs_vn))[i]);
2259
2260         for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2261                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2262                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2263                        ((u32 *)(&m_fair_vn))[i]);
2264 }
2265
2266
2267 /* This function is called upon link interrupt */
2268 static void bnx2x_link_attn(struct bnx2x *bp)
2269 {
2270         /* Make sure that we are synced with the current statistics */
2271         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2272
2273         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2274
2275         if (bp->link_vars.link_up) {
2276
2277                 /* dropless flow control */
2278                 if (CHIP_IS_E1H(bp)) {
2279                         int port = BP_PORT(bp);
2280                         u32 pause_enabled = 0;
2281
2282                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2283                                 pause_enabled = 1;
2284
2285                         REG_WR(bp, BAR_USTRORM_INTMEM +
2286                                USTORM_PAUSE_ENABLED_OFFSET(port),
2287                                pause_enabled);
2288                 }
2289
2290                 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2291                         struct host_port_stats *pstats;
2292
2293                         pstats = bnx2x_sp(bp, port_stats);
2294                         /* reset old bmac stats */
2295                         memset(&(pstats->mac_stx[0]), 0,
2296                                sizeof(struct mac_stx));
2297                 }
2298                 if ((bp->state == BNX2X_STATE_OPEN) ||
2299                     (bp->state == BNX2X_STATE_DISABLED))
2300                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2301         }
2302
2303         /* indicate link status */
2304         bnx2x_link_report(bp);
2305
2306         if (IS_E1HMF(bp)) {
2307                 int port = BP_PORT(bp);
2308                 int func;
2309                 int vn;
2310
2311                 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2312                         if (vn == BP_E1HVN(bp))
2313                                 continue;
2314
2315                         func = ((vn << 1) | port);
2316
2317                         /* Set the attention towards other drivers
2318                            on the same port */
2319                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2320                                (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2321                 }
2322
2323                 if (bp->link_vars.link_up) {
2324                         int i;
2325
2326                         /* Init rate shaping and fairness contexts */
2327                         bnx2x_init_port_minmax(bp);
2328
2329                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
2330                                 bnx2x_init_vn_minmax(bp, 2*vn + port);
2331
2332                         /* Store it to internal memory */
2333                         for (i = 0;
2334                              i < sizeof(struct cmng_struct_per_port) / 4; i++)
2335                                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2336                                   XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
2337                                        ((u32 *)(&bp->cmng))[i]);
2338                 }
2339         }
2340 }
2341
2342 static void bnx2x__link_status_update(struct bnx2x *bp)
2343 {
2344         if (bp->state != BNX2X_STATE_OPEN)
2345                 return;
2346
2347         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2348
2349         if (bp->link_vars.link_up)
2350                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2351         else
2352                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2353
2354         /* indicate link status */
2355         bnx2x_link_report(bp);
2356 }
2357
2358 static void bnx2x_pmf_update(struct bnx2x *bp)
2359 {
2360         int port = BP_PORT(bp);
2361         u32 val;
2362
2363         bp->port.pmf = 1;
2364         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2365
2366         /* enable nig attention */
2367         val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2368         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2369         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2370
2371         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2372 }
2373
2374 /* end of Link */
2375
2376 /* slow path */
2377
2378 /*
2379  * General service functions
2380  */
2381
2382 /* the slow path queue is odd since completions arrive on the fastpath ring */
2383 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2384                          u32 data_hi, u32 data_lo, int common)
2385 {
2386         int func = BP_FUNC(bp);
2387
2388         DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2389            "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
2390            (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2391            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2392            HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2393
2394 #ifdef BNX2X_STOP_ON_ERROR
2395         if (unlikely(bp->panic))
2396                 return -EIO;
2397 #endif
2398
2399         spin_lock_bh(&bp->spq_lock);
2400
2401         if (!bp->spq_left) {
2402                 BNX2X_ERR("BUG! SPQ ring full!\n");
2403                 spin_unlock_bh(&bp->spq_lock);
2404                 bnx2x_panic();
2405                 return -EBUSY;
2406         }
2407
2408         /* CID needs port number to be encoded int it */
2409         bp->spq_prod_bd->hdr.conn_and_cmd_data =
2410                         cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2411                                      HW_CID(bp, cid)));
2412         bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2413         if (common)
2414                 bp->spq_prod_bd->hdr.type |=
2415                         cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2416
2417         bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2418         bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2419
2420         bp->spq_left--;
2421
2422         if (bp->spq_prod_bd == bp->spq_last_bd) {
2423                 bp->spq_prod_bd = bp->spq;
2424                 bp->spq_prod_idx = 0;
2425                 DP(NETIF_MSG_TIMER, "end of spq\n");
2426
2427         } else {
2428                 bp->spq_prod_bd++;
2429                 bp->spq_prod_idx++;
2430         }
2431
2432         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2433                bp->spq_prod_idx);
2434
2435         spin_unlock_bh(&bp->spq_lock);
2436         return 0;
2437 }
2438
2439 /* acquire split MCP access lock register */
2440 static int bnx2x_acquire_alr(struct bnx2x *bp)
2441 {
2442         u32 i, j, val;
2443         int rc = 0;
2444
2445         might_sleep();
2446         i = 100;
2447         for (j = 0; j < i*10; j++) {
2448                 val = (1UL << 31);
2449                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2450                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2451                 if (val & (1L << 31))
2452                         break;
2453
2454                 msleep(5);
2455         }
2456         if (!(val & (1L << 31))) {
2457                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2458                 rc = -EBUSY;
2459         }
2460
2461         return rc;
2462 }
2463
2464 /* release split MCP access lock register */
2465 static void bnx2x_release_alr(struct bnx2x *bp)
2466 {
2467         u32 val = 0;
2468
2469         REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2470 }
2471
2472 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2473 {
2474         struct host_def_status_block *def_sb = bp->def_status_blk;
2475         u16 rc = 0;
2476
2477         barrier(); /* status block is written to by the chip */
2478         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2479                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2480                 rc |= 1;
2481         }
2482         if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2483                 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2484                 rc |= 2;
2485         }
2486         if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2487                 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2488                 rc |= 4;
2489         }
2490         if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2491                 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2492                 rc |= 8;
2493         }
2494         if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2495                 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2496                 rc |= 16;
2497         }
2498         return rc;
2499 }
2500
2501 /*
2502  * slow path service functions
2503  */
2504
2505 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2506 {
2507         int port = BP_PORT(bp);
2508         u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2509                        COMMAND_REG_ATTN_BITS_SET);
2510         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2511                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
2512         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2513                                        NIG_REG_MASK_INTERRUPT_PORT0;
2514         u32 aeu_mask;
2515         u32 nig_mask = 0;
2516
2517         if (bp->attn_state & asserted)
2518                 BNX2X_ERR("IGU ERROR\n");
2519
2520         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2521         aeu_mask = REG_RD(bp, aeu_addr);
2522
2523         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
2524            aeu_mask, asserted);
2525         aeu_mask &= ~(asserted & 0xff);
2526         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2527
2528         REG_WR(bp, aeu_addr, aeu_mask);
2529         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2530
2531         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2532         bp->attn_state |= asserted;
2533         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2534
2535         if (asserted & ATTN_HARD_WIRED_MASK) {
2536                 if (asserted & ATTN_NIG_FOR_FUNC) {
2537
2538                         bnx2x_acquire_phy_lock(bp);
2539
2540                         /* save nig interrupt mask */
2541                         nig_mask = REG_RD(bp, nig_int_mask_addr);
2542                         REG_WR(bp, nig_int_mask_addr, 0);
2543
2544                         bnx2x_link_attn(bp);
2545
2546                         /* handle unicore attn? */
2547                 }
2548                 if (asserted & ATTN_SW_TIMER_4_FUNC)
2549                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2550
2551                 if (asserted & GPIO_2_FUNC)
2552                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2553
2554                 if (asserted & GPIO_3_FUNC)
2555                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2556
2557                 if (asserted & GPIO_4_FUNC)
2558                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2559
2560                 if (port == 0) {
2561                         if (asserted & ATTN_GENERAL_ATTN_1) {
2562                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2563                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2564                         }
2565                         if (asserted & ATTN_GENERAL_ATTN_2) {
2566                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2567                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2568                         }
2569                         if (asserted & ATTN_GENERAL_ATTN_3) {
2570                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2571                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2572                         }
2573                 } else {
2574                         if (asserted & ATTN_GENERAL_ATTN_4) {
2575                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2576                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2577                         }
2578                         if (asserted & ATTN_GENERAL_ATTN_5) {
2579                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2580                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2581                         }
2582                         if (asserted & ATTN_GENERAL_ATTN_6) {
2583                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2584                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2585                         }
2586                 }
2587
2588         } /* if hardwired */
2589
2590         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2591            asserted, hc_addr);
2592         REG_WR(bp, hc_addr, asserted);
2593
2594         /* now set back the mask */
2595         if (asserted & ATTN_NIG_FOR_FUNC) {
2596                 REG_WR(bp, nig_int_mask_addr, nig_mask);
2597                 bnx2x_release_phy_lock(bp);
2598         }
2599 }
2600
2601 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2602 {
2603         int port = BP_PORT(bp);
2604
2605         /* mark the failure */
2606         bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2607         bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2608         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2609                  bp->link_params.ext_phy_config);
2610
2611         /* log the failure */
2612         printk(KERN_ERR PFX "Fan Failure on Network Controller %s has caused"
2613                " the driver to shutdown the card to prevent permanent"
2614                " damage.  Please contact Dell Support for assistance\n",
2615                bp->dev->name);
2616 }
2617 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2618 {
2619         int port = BP_PORT(bp);
2620         int reg_offset;
2621         u32 val;
2622
2623         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2624                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2625
2626         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2627
2628                 val = REG_RD(bp, reg_offset);
2629                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2630                 REG_WR(bp, reg_offset, val);
2631
2632                 BNX2X_ERR("SPIO5 hw attention\n");
2633
2634                 /* Fan failure attention */
2635                 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
2636                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2637                         /* Low power mode is controlled by GPIO 2 */
2638                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2639                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2640                         /* The PHY reset is controlled by GPIO 1 */
2641                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2642                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2643                         break;
2644
2645                 default:
2646                         break;
2647                 }
2648                 bnx2x_fan_failure(bp);
2649         }
2650
2651         if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2652                     AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2653                 bnx2x_acquire_phy_lock(bp);
2654                 bnx2x_handle_module_detect_int(&bp->link_params);
2655                 bnx2x_release_phy_lock(bp);
2656         }
2657
2658         if (attn & HW_INTERRUT_ASSERT_SET_0) {
2659
2660                 val = REG_RD(bp, reg_offset);
2661                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2662                 REG_WR(bp, reg_offset, val);
2663
2664                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2665                           (attn & HW_INTERRUT_ASSERT_SET_0));
2666                 bnx2x_panic();
2667         }
2668 }
2669
2670 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2671 {
2672         u32 val;
2673
2674         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
2675
2676                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2677                 BNX2X_ERR("DB hw attention 0x%x\n", val);
2678                 /* DORQ discard attention */
2679                 if (val & 0x2)
2680                         BNX2X_ERR("FATAL error from DORQ\n");
2681         }
2682
2683         if (attn & HW_INTERRUT_ASSERT_SET_1) {
2684
2685                 int port = BP_PORT(bp);
2686                 int reg_offset;
2687
2688                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2689                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2690
2691                 val = REG_RD(bp, reg_offset);
2692                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2693                 REG_WR(bp, reg_offset, val);
2694
2695                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2696                           (attn & HW_INTERRUT_ASSERT_SET_1));
2697                 bnx2x_panic();
2698         }
2699 }
2700
2701 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2702 {
2703         u32 val;
2704
2705         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2706
2707                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2708                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2709                 /* CFC error attention */
2710                 if (val & 0x2)
2711                         BNX2X_ERR("FATAL error from CFC\n");
2712         }
2713
2714         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2715
2716                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2717                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2718                 /* RQ_USDMDP_FIFO_OVERFLOW */
2719                 if (val & 0x18000)
2720                         BNX2X_ERR("FATAL error from PXP\n");
2721         }
2722
2723         if (attn & HW_INTERRUT_ASSERT_SET_2) {
2724
2725                 int port = BP_PORT(bp);
2726                 int reg_offset;
2727
2728                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2729                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2730
2731                 val = REG_RD(bp, reg_offset);
2732                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2733                 REG_WR(bp, reg_offset, val);
2734
2735                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2736                           (attn & HW_INTERRUT_ASSERT_SET_2));
2737                 bnx2x_panic();
2738         }
2739 }
2740
2741 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2742 {
2743         u32 val;
2744
2745         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2746
2747                 if (attn & BNX2X_PMF_LINK_ASSERT) {
2748                         int func = BP_FUNC(bp);
2749
2750                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2751                         bnx2x__link_status_update(bp);
2752                         if (SHMEM_RD(bp, func_mb[func].drv_status) &
2753                                                         DRV_STATUS_PMF)
2754                                 bnx2x_pmf_update(bp);
2755
2756                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2757
2758                         BNX2X_ERR("MC assert!\n");
2759                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2760                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2761                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2762                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2763                         bnx2x_panic();
2764
2765                 } else if (attn & BNX2X_MCP_ASSERT) {
2766
2767                         BNX2X_ERR("MCP assert!\n");
2768                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2769                         bnx2x_fw_dump(bp);
2770
2771                 } else
2772                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2773         }
2774
2775         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2776                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2777                 if (attn & BNX2X_GRC_TIMEOUT) {
2778                         val = CHIP_IS_E1H(bp) ?
2779                                 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2780                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
2781                 }
2782                 if (attn & BNX2X_GRC_RSV) {
2783                         val = CHIP_IS_E1H(bp) ?
2784                                 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2785                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
2786                 }
2787                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2788         }
2789 }
2790
2791 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2792 {
2793         struct attn_route attn;
2794         struct attn_route group_mask;
2795         int port = BP_PORT(bp);
2796         int index;
2797         u32 reg_addr;
2798         u32 val;
2799         u32 aeu_mask;
2800
2801         /* need to take HW lock because MCP or other port might also
2802            try to handle this event */
2803         bnx2x_acquire_alr(bp);
2804
2805         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2806         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2807         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2808         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2809         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2810            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2811
2812         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2813                 if (deasserted & (1 << index)) {
2814                         group_mask = bp->attn_group[index];
2815
2816                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2817                            index, group_mask.sig[0], group_mask.sig[1],
2818                            group_mask.sig[2], group_mask.sig[3]);
2819
2820                         bnx2x_attn_int_deasserted3(bp,
2821                                         attn.sig[3] & group_mask.sig[3]);
2822                         bnx2x_attn_int_deasserted1(bp,
2823                                         attn.sig[1] & group_mask.sig[1]);
2824                         bnx2x_attn_int_deasserted2(bp,
2825                                         attn.sig[2] & group_mask.sig[2]);
2826                         bnx2x_attn_int_deasserted0(bp,
2827                                         attn.sig[0] & group_mask.sig[0]);
2828
2829                         if ((attn.sig[0] & group_mask.sig[0] &
2830                                                 HW_PRTY_ASSERT_SET_0) ||
2831                             (attn.sig[1] & group_mask.sig[1] &
2832                                                 HW_PRTY_ASSERT_SET_1) ||
2833                             (attn.sig[2] & group_mask.sig[2] &
2834                                                 HW_PRTY_ASSERT_SET_2))
2835                                 BNX2X_ERR("FATAL HW block parity attention\n");
2836                 }
2837         }
2838
2839         bnx2x_release_alr(bp);
2840
2841         reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2842
2843         val = ~deasserted;
2844         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2845            val, reg_addr);
2846         REG_WR(bp, reg_addr, val);
2847
2848         if (~bp->attn_state & deasserted)
2849                 BNX2X_ERR("IGU ERROR\n");
2850
2851         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2852                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
2853
2854         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2855         aeu_mask = REG_RD(bp, reg_addr);
2856
2857         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
2858            aeu_mask, deasserted);
2859         aeu_mask |= (deasserted & 0xff);
2860         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2861
2862         REG_WR(bp, reg_addr, aeu_mask);
2863         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2864
2865         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2866         bp->attn_state &= ~deasserted;
2867         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2868 }
2869
2870 static void bnx2x_attn_int(struct bnx2x *bp)
2871 {
2872         /* read local copy of bits */
2873         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
2874                                                                 attn_bits);
2875         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
2876                                                                 attn_bits_ack);
2877         u32 attn_state = bp->attn_state;
2878
2879         /* look for changed bits */
2880         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
2881         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
2882
2883         DP(NETIF_MSG_HW,
2884            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
2885            attn_bits, attn_ack, asserted, deasserted);
2886
2887         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2888                 BNX2X_ERR("BAD attention state\n");
2889
2890         /* handle bits that were raised */
2891         if (asserted)
2892                 bnx2x_attn_int_asserted(bp, asserted);
2893
2894         if (deasserted)
2895                 bnx2x_attn_int_deasserted(bp, deasserted);
2896 }
2897
2898 static void bnx2x_sp_task(struct work_struct *work)
2899 {
2900         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
2901         u16 status;
2902
2903
2904         /* Return here if interrupt is disabled */
2905         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2906                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2907                 return;
2908         }
2909
2910         status = bnx2x_update_dsb_idx(bp);
2911 /*      if (status == 0)                                     */
2912 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
2913
2914         DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2915
2916         /* HW attentions */
2917         if (status & 0x1)
2918                 bnx2x_attn_int(bp);
2919
2920         bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
2921                      IGU_INT_NOP, 1);
2922         bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2923                      IGU_INT_NOP, 1);
2924         bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2925                      IGU_INT_NOP, 1);
2926         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2927                      IGU_INT_NOP, 1);
2928         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2929                      IGU_INT_ENABLE, 1);
2930
2931 }
2932
2933 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2934 {
2935         struct net_device *dev = dev_instance;
2936         struct bnx2x *bp = netdev_priv(dev);
2937
2938         /* Return here if interrupt is disabled */
2939         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2940                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2941                 return IRQ_HANDLED;
2942         }
2943
2944         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
2945
2946 #ifdef BNX2X_STOP_ON_ERROR
2947         if (unlikely(bp->panic))
2948                 return IRQ_HANDLED;
2949 #endif
2950
2951         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
2952
2953         return IRQ_HANDLED;
2954 }
2955
2956 /* end of slow path */
2957
2958 /* Statistics */
2959
2960 /****************************************************************************
2961 * Macros
2962 ****************************************************************************/
2963
2964 /* sum[hi:lo] += add[hi:lo] */
2965 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2966         do { \
2967                 s_lo += a_lo; \
2968                 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
2969         } while (0)
2970
2971 /* difference = minuend - subtrahend */
2972 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2973         do { \
2974                 if (m_lo < s_lo) { \
2975                         /* underflow */ \
2976                         d_hi = m_hi - s_hi; \
2977                         if (d_hi > 0) { \
2978                                 /* we can 'loan' 1 */ \
2979                                 d_hi--; \
2980                                 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2981                         } else { \
2982                                 /* m_hi <= s_hi */ \
2983                                 d_hi = 0; \
2984                                 d_lo = 0; \
2985                         } \
2986                 } else { \
2987                         /* m_lo >= s_lo */ \
2988                         if (m_hi < s_hi) { \
2989                                 d_hi = 0; \
2990                                 d_lo = 0; \
2991                         } else { \
2992                                 /* m_hi >= s_hi */ \
2993                                 d_hi = m_hi - s_hi; \
2994                                 d_lo = m_lo - s_lo; \
2995                         } \
2996                 } \
2997         } while (0)
2998
2999 #define UPDATE_STAT64(s, t) \
3000         do { \
3001                 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
3002                         diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
3003                 pstats->mac_stx[0].t##_hi = new->s##_hi; \
3004                 pstats->mac_stx[0].t##_lo = new->s##_lo; \
3005                 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
3006                        pstats->mac_stx[1].t##_lo, diff.lo); \
3007         } while (0)
3008
3009 #define UPDATE_STAT64_NIG(s, t) \
3010         do { \
3011                 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
3012                         diff.lo, new->s##_lo, old->s##_lo); \
3013                 ADD_64(estats->t##_hi, diff.hi, \
3014                        estats->t##_lo, diff.lo); \
3015         } while (0)
3016
3017 /* sum[hi:lo] += add */
3018 #define ADD_EXTEND_64(s_hi, s_lo, a) \
3019         do { \
3020                 s_lo += a; \
3021                 s_hi += (s_lo < a) ? 1 : 0; \
3022         } while (0)
3023
3024 #define UPDATE_EXTEND_STAT(s) \
3025         do { \
3026                 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
3027                               pstats->mac_stx[1].s##_lo, \
3028                               new->s); \
3029         } while (0)
3030
3031 #define UPDATE_EXTEND_TSTAT(s, t) \
3032         do { \
3033                 diff = le32_to_cpu(tclient->s) - le32_to_cpu(old_tclient->s); \
3034                 old_tclient->s = tclient->s; \
3035                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3036         } while (0)
3037
3038 #define UPDATE_EXTEND_USTAT(s, t) \
3039         do { \
3040                 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
3041                 old_uclient->s = uclient->s; \
3042                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3043         } while (0)
3044
3045 #define UPDATE_EXTEND_XSTAT(s, t) \
3046         do { \
3047                 diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \
3048                 old_xclient->s = xclient->s; \
3049                 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3050         } while (0)
3051
3052 /* minuend -= subtrahend */
3053 #define SUB_64(m_hi, s_hi, m_lo, s_lo) \
3054         do { \
3055                 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
3056         } while (0)
3057
3058 /* minuend[hi:lo] -= subtrahend */
3059 #define SUB_EXTEND_64(m_hi, m_lo, s) \
3060         do { \
3061                 SUB_64(m_hi, 0, m_lo, s); \
3062         } while (0)
3063
3064 #define SUB_EXTEND_USTAT(s, t) \
3065         do { \
3066                 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
3067                 SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3068         } while (0)
3069
3070 /*
3071  * General service functions
3072  */
3073
3074 static inline long bnx2x_hilo(u32 *hiref)
3075 {
3076         u32 lo = *(hiref + 1);
3077 #if (BITS_PER_LONG == 64)
3078         u32 hi = *hiref;
3079
3080         return HILO_U64(hi, lo);
3081 #else
3082         return lo;
3083 #endif
3084 }
3085
3086 /*
3087  * Init service functions
3088  */
3089
3090 static void bnx2x_storm_stats_post(struct bnx2x *bp)
3091 {
3092         if (!bp->stats_pending) {
3093                 struct eth_query_ramrod_data ramrod_data = {0};
3094                 int i, rc;
3095
3096                 ramrod_data.drv_counter = bp->stats_counter++;
3097                 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
3098                 for_each_queue(bp, i)
3099                         ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
3100
3101                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3102                                    ((u32 *)&ramrod_data)[1],
3103                                    ((u32 *)&ramrod_data)[0], 0);
3104                 if (rc == 0) {
3105                         /* stats ramrod has it's own slot on the spq */
3106                         bp->spq_left++;
3107                         bp->stats_pending = 1;
3108                 }
3109         }
3110 }
3111
3112 static void bnx2x_stats_init(struct bnx2x *bp)
3113 {
3114         int port = BP_PORT(bp);
3115         int i;
3116
3117         bp->stats_pending = 0;
3118         bp->executer_idx = 0;
3119         bp->stats_counter = 0;
3120
3121         /* port stats */
3122         if (!BP_NOMCP(bp))
3123                 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3124         else
3125                 bp->port.port_stx = 0;
3126         DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3127
3128         memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3129         bp->port.old_nig_stats.brb_discard =
3130                         REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3131         bp->port.old_nig_stats.brb_truncate =
3132                         REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3133         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3134                     &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3135         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3136                     &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3137
3138         /* function stats */
3139         for_each_queue(bp, i) {
3140                 struct bnx2x_fastpath *fp = &bp->fp[i];
3141
3142                 memset(&fp->old_tclient, 0,
3143                        sizeof(struct tstorm_per_client_stats));
3144                 memset(&fp->old_uclient, 0,
3145                        sizeof(struct ustorm_per_client_stats));
3146                 memset(&fp->old_xclient, 0,
3147                        sizeof(struct xstorm_per_client_stats));
3148                 memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
3149         }
3150
3151         memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3152         memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3153
3154         bp->stats_state = STATS_STATE_DISABLED;
3155         if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3156                 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3157 }
3158
3159 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3160 {
3161         struct dmae_command *dmae = &bp->stats_dmae;
3162         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3163
3164         *stats_comp = DMAE_COMP_VAL;
3165         if (CHIP_REV_IS_SLOW(bp))
3166                 return;
3167
3168         /* loader */
3169         if (bp->executer_idx) {
3170                 int loader_idx = PMF_DMAE_C(bp);
3171
3172                 memset(dmae, 0, sizeof(struct dmae_command));
3173
3174                 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3175                                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3176                                 DMAE_CMD_DST_RESET |
3177 #ifdef __BIG_ENDIAN
3178                                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3179 #else
3180                                 DMAE_CMD_ENDIANITY_DW_SWAP |
3181 #endif
3182                                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3183                                                DMAE_CMD_PORT_0) |
3184                                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3185                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3186                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3187                 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3188                                      sizeof(struct dmae_command) *
3189                                      (loader_idx + 1)) >> 2;
3190                 dmae->dst_addr_hi = 0;
3191                 dmae->len = sizeof(struct dmae_command) >> 2;
3192                 if (CHIP_IS_E1(bp))
3193                         dmae->len--;
3194                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3195                 dmae->comp_addr_hi = 0;
3196                 dmae->comp_val = 1;
3197
3198                 *stats_comp = 0;
3199                 bnx2x_post_dmae(bp, dmae, loader_idx);
3200
3201         } else if (bp->func_stx) {
3202                 *stats_comp = 0;
3203                 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3204         }
3205 }
3206
3207 static int bnx2x_stats_comp(struct bnx2x *bp)
3208 {
3209         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3210         int cnt = 10;
3211
3212         might_sleep();
3213         while (*stats_comp != DMAE_COMP_VAL) {
3214                 if (!cnt) {
3215                         BNX2X_ERR("timeout waiting for stats finished\n");
3216                         break;
3217                 }
3218                 cnt--;
3219                 msleep(1);
3220         }
3221         return 1;
3222 }
3223
3224 /*
3225  * Statistics service functions
3226  */
3227
3228 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3229 {
3230         struct dmae_command *dmae;
3231         u32 opcode;
3232         int loader_idx = PMF_DMAE_C(bp);
3233         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3234
3235         /* sanity */
3236         if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3237                 BNX2X_ERR("BUG!\n");
3238                 return;
3239         }
3240
3241         bp->executer_idx = 0;
3242
3243         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3244                   DMAE_CMD_C_ENABLE |
3245                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3246 #ifdef __BIG_ENDIAN
3247                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3248 #else
3249                   DMAE_CMD_ENDIANITY_DW_SWAP |
3250 #endif
3251                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3252                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3253
3254         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3255         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3256         dmae->src_addr_lo = bp->port.port_stx >> 2;
3257         dmae->src_addr_hi = 0;
3258         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3259         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3260         dmae->len = DMAE_LEN32_RD_MAX;
3261         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3262         dmae->comp_addr_hi = 0;
3263         dmae->comp_val = 1;
3264
3265         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3266         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3267         dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3268         dmae->src_addr_hi = 0;
3269         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3270                                    DMAE_LEN32_RD_MAX * 4);
3271         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3272                                    DMAE_LEN32_RD_MAX * 4);
3273         dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3274         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3275         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3276         dmae->comp_val = DMAE_COMP_VAL;
3277
3278         *stats_comp = 0;
3279         bnx2x_hw_stats_post(bp);
3280         bnx2x_stats_comp(bp);
3281 }
3282
3283 static void bnx2x_port_stats_init(struct bnx2x *bp)
3284 {
3285         struct dmae_command *dmae;
3286         int port = BP_PORT(bp);
3287         int vn = BP_E1HVN(bp);
3288         u32 opcode;
3289         int loader_idx = PMF_DMAE_C(bp);
3290         u32 mac_addr;
3291         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3292
3293         /* sanity */
3294         if (!bp->link_vars.link_up || !bp->port.pmf) {
3295                 BNX2X_ERR("BUG!\n");
3296                 return;
3297         }
3298
3299         bp->executer_idx = 0;
3300
3301         /* MCP */
3302         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3303                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3304                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3305 #ifdef __BIG_ENDIAN
3306                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3307 #else
3308                   DMAE_CMD_ENDIANITY_DW_SWAP |
3309 #endif
3310                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3311                   (vn << DMAE_CMD_E1HVN_SHIFT));
3312
3313         if (bp->port.port_stx) {
3314
3315                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3316                 dmae->opcode = opcode;
3317                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3318                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3319                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3320                 dmae->dst_addr_hi = 0;
3321                 dmae->len = sizeof(struct host_port_stats) >> 2;
3322                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3323                 dmae->comp_addr_hi = 0;
3324                 dmae->comp_val = 1;
3325         }
3326
3327         if (bp->func_stx) {
3328
3329                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3330                 dmae->opcode = opcode;
3331                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3332                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3333                 dmae->dst_addr_lo = bp->func_stx >> 2;
3334                 dmae->dst_addr_hi = 0;
3335                 dmae->len = sizeof(struct host_func_stats) >> 2;
3336                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3337                 dmae->comp_addr_hi = 0;
3338                 dmae->comp_val = 1;
3339         }
3340
3341         /* MAC */
3342         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3343                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3344                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3345 #ifdef __BIG_ENDIAN
3346                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3347 #else
3348                   DMAE_CMD_ENDIANITY_DW_SWAP |
3349 #endif
3350                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3351                   (vn << DMAE_CMD_E1HVN_SHIFT));
3352
3353         if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3354
3355                 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3356                                    NIG_REG_INGRESS_BMAC0_MEM);
3357
3358                 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3359                    BIGMAC_REGISTER_TX_STAT_GTBYT */
3360                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3361                 dmae->opcode = opcode;
3362                 dmae->src_addr_lo = (mac_addr +
3363                                      BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3364                 dmae->src_addr_hi = 0;
3365                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3366                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3367                 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3368                              BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3369                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3370                 dmae->comp_addr_hi = 0;
3371                 dmae->comp_val = 1;
3372
3373                 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3374                    BIGMAC_REGISTER_RX_STAT_GRIPJ */
3375                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3376                 dmae->opcode = opcode;
3377                 dmae->src_addr_lo = (mac_addr +
3378                                      BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3379                 dmae->src_addr_hi = 0;
3380                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3381                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3382                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3383                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3384                 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3385                              BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3386                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3387                 dmae->comp_addr_hi = 0;
3388                 dmae->comp_val = 1;
3389
3390         } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3391
3392                 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3393
3394                 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3395                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3396                 dmae->opcode = opcode;
3397                 dmae->src_addr_lo = (mac_addr +
3398                                      EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3399                 dmae->src_addr_hi = 0;
3400                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3401                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3402                 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3403                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3404                 dmae->comp_addr_hi = 0;
3405                 dmae->comp_val = 1;
3406
3407                 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3408                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3409                 dmae->opcode = opcode;
3410                 dmae->src_addr_lo = (mac_addr +
3411                                      EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3412                 dmae->src_addr_hi = 0;
3413                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3414                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3415                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3416                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3417                 dmae->len = 1;
3418                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3419                 dmae->comp_addr_hi = 0;
3420                 dmae->comp_val = 1;
3421
3422                 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3423                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3424                 dmae->opcode = opcode;
3425                 dmae->src_addr_lo = (mac_addr +
3426                                      EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3427                 dmae->src_addr_hi = 0;
3428                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3429                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3430                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3431                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3432                 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3433                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3434                 dmae->comp_addr_hi = 0;
3435                 dmae->comp_val = 1;
3436         }
3437
3438         /* NIG */
3439         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3440         dmae->opcode = opcode;
3441         dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3442                                     NIG_REG_STAT0_BRB_DISCARD) >> 2;
3443         dmae->src_addr_hi = 0;
3444         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3445         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3446         dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3447         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3448         dmae->comp_addr_hi = 0;
3449         dmae->comp_val = 1;
3450
3451         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3452         dmae->opcode = opcode;
3453         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3454                                     NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3455         dmae->src_addr_hi = 0;
3456         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3457                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3458         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3459                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3460         dmae->len = (2*sizeof(u32)) >> 2;
3461         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3462         dmae->comp_addr_hi = 0;
3463         dmae->comp_val = 1;
3464
3465         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3466         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3467                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3468                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3469 #ifdef __BIG_ENDIAN
3470                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3471 #else
3472                         DMAE_CMD_ENDIANITY_DW_SWAP |
3473 #endif
3474                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3475                         (vn << DMAE_CMD_E1HVN_SHIFT));
3476         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3477                                     NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3478         dmae->src_addr_hi = 0;
3479         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3480                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3481         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3482                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3483         dmae->len = (2*sizeof(u32)) >> 2;
3484         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3485         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3486         dmae->comp_val = DMAE_COMP_VAL;
3487
3488         *stats_comp = 0;
3489 }
3490
3491 static void bnx2x_func_stats_init(struct bnx2x *bp)
3492 {
3493         struct dmae_command *dmae = &bp->stats_dmae;
3494         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3495
3496         /* sanity */
3497         if (!bp->func_stx) {
3498                 BNX2X_ERR("BUG!\n");
3499                 return;
3500         }
3501
3502         bp->executer_idx = 0;
3503         memset(dmae, 0, sizeof(struct dmae_command));
3504
3505         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3506                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3507                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3508 #ifdef __BIG_ENDIAN
3509                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3510 #else
3511                         DMAE_CMD_ENDIANITY_DW_SWAP |
3512 #endif
3513                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3514                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3515         dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3516         dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3517         dmae->dst_addr_lo = bp->func_stx >> 2;
3518         dmae->dst_addr_hi = 0;
3519         dmae->len = sizeof(struct host_func_stats) >> 2;
3520         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3521         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3522         dmae->comp_val = DMAE_COMP_VAL;
3523
3524         *stats_comp = 0;
3525 }
3526
3527 static void bnx2x_stats_start(struct bnx2x *bp)
3528 {
3529         if (bp->port.pmf)
3530                 bnx2x_port_stats_init(bp);
3531
3532         else if (bp->func_stx)
3533                 bnx2x_func_stats_init(bp);
3534
3535         bnx2x_hw_stats_post(bp);
3536         bnx2x_storm_stats_post(bp);
3537 }
3538
3539 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3540 {
3541         bnx2x_stats_comp(bp);
3542         bnx2x_stats_pmf_update(bp);
3543         bnx2x_stats_start(bp);
3544 }
3545
3546 static void bnx2x_stats_restart(struct bnx2x *bp)
3547 {
3548         bnx2x_stats_comp(bp);
3549         bnx2x_stats_start(bp);
3550 }
3551
3552 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3553 {
3554         struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3555         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3556         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3557         struct {
3558                 u32 lo;
3559                 u32 hi;
3560         } diff;
3561
3562         UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3563         UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3564         UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3565         UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3566         UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3567         UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3568         UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3569         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3570         UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
3571         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3572         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3573         UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3574         UPDATE_STAT64(tx_stat_gt127,
3575                                 tx_stat_etherstatspkts65octetsto127octets);
3576         UPDATE_STAT64(tx_stat_gt255,
3577                                 tx_stat_etherstatspkts128octetsto255octets);
3578         UPDATE_STAT64(tx_stat_gt511,
3579                                 tx_stat_etherstatspkts256octetsto511octets);
3580         UPDATE_STAT64(tx_stat_gt1023,
3581                                 tx_stat_etherstatspkts512octetsto1023octets);
3582         UPDATE_STAT64(tx_stat_gt1518,
3583                                 tx_stat_etherstatspkts1024octetsto1522octets);
3584         UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3585         UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3586         UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3587         UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3588         UPDATE_STAT64(tx_stat_gterr,
3589                                 tx_stat_dot3statsinternalmactransmiterrors);
3590         UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3591
3592         estats->pause_frames_received_hi =
3593                                 pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
3594         estats->pause_frames_received_lo =
3595                                 pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
3596
3597         estats->pause_frames_sent_hi =
3598                                 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
3599         estats->pause_frames_sent_lo =
3600                                 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
3601 }
3602
3603 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3604 {
3605         struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3606         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3607         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3608
3609         UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3610         UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3611         UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3612         UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3613         UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3614         UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3615         UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3616         UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3617         UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3618         UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3619         UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3620         UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3621         UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3622         UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3623         UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3624         UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3625         UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3626         UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3627         UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3628         UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3629         UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3630         UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3631         UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3632         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3633         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3634         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3635         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3636         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3637         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3638         UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3639         UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3640
3641         estats->pause_frames_received_hi =
3642                         pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
3643         estats->pause_frames_received_lo =
3644                         pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
3645         ADD_64(estats->pause_frames_received_hi,
3646                pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
3647                estats->pause_frames_received_lo,
3648                pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
3649
3650         estats->pause_frames_sent_hi =
3651                         pstats->mac_stx[1].tx_stat_outxonsent_hi;
3652         estats->pause_frames_sent_lo =
3653                         pstats->mac_stx[1].tx_stat_outxonsent_lo;
3654         ADD_64(estats->pause_frames_sent_hi,
3655                pstats->mac_stx[1].tx_stat_outxoffsent_hi,
3656                estats->pause_frames_sent_lo,
3657                pstats->mac_stx[1].tx_stat_outxoffsent_lo);
3658 }
3659
3660 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3661 {
3662         struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3663         struct nig_stats *old = &(bp->port.old_nig_stats);
3664         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3665         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3666         struct {
3667                 u32 lo;
3668                 u32 hi;
3669         } diff;
3670         u32 nig_timer_max;
3671
3672         if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3673                 bnx2x_bmac_stats_update(bp);
3674
3675         else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3676                 bnx2x_emac_stats_update(bp);
3677
3678         else { /* unreached */
3679                 BNX2X_ERR("stats updated by DMAE but no MAC active\n");
3680                 return -1;
3681         }
3682
3683         ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3684                       new->brb_discard - old->brb_discard);
3685         ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3686                       new->brb_truncate - old->brb_truncate);
3687
3688         UPDATE_STAT64_NIG(egress_mac_pkt0,
3689                                         etherstatspkts1024octetsto1522octets);
3690         UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3691
3692         memcpy(old, new, sizeof(struct nig_stats));
3693
3694         memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3695                sizeof(struct mac_stx));
3696         estats->brb_drop_hi = pstats->brb_drop_hi;
3697         estats->brb_drop_lo = pstats->brb_drop_lo;
3698
3699         pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3700
3701         nig_timer_max = SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
3702         if (nig_timer_max != estats->nig_timer_max) {
3703                 estats->nig_timer_max = nig_timer_max;
3704                 BNX2X_ERR("NIG timer max (%u)\n", estats->nig_timer_max);
3705         }
3706
3707         return 0;
3708 }
3709
3710 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3711 {
3712         struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3713         struct tstorm_per_port_stats *tport =
3714                                         &stats->tstorm_common.port_statistics;
3715         struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3716         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3717         int i;
3718
3719         memset(&(fstats->total_bytes_received_hi), 0,
3720                sizeof(struct host_func_stats) - 2*sizeof(u32));
3721         estats->error_bytes_received_hi = 0;
3722         estats->error_bytes_received_lo = 0;
3723         estats->etherstatsoverrsizepkts_hi = 0;
3724         estats->etherstatsoverrsizepkts_lo = 0;
3725         estats->no_buff_discard_hi = 0;
3726         estats->no_buff_discard_lo = 0;
3727
3728         for_each_queue(bp, i) {
3729                 struct bnx2x_fastpath *fp = &bp->fp[i];
3730                 int cl_id = fp->cl_id;
3731                 struct tstorm_per_client_stats *tclient =
3732                                 &stats->tstorm_common.client_statistics[cl_id];
3733                 struct tstorm_per_client_stats *old_tclient = &fp->old_tclient;
3734                 struct ustorm_per_client_stats *uclient =
3735                                 &stats->ustorm_common.client_statistics[cl_id];
3736                 struct ustorm_per_client_stats *old_uclient = &fp->old_uclient;
3737                 struct xstorm_per_client_stats *xclient =
3738                                 &stats->xstorm_common.client_statistics[cl_id];
3739                 struct xstorm_per_client_stats *old_xclient = &fp->old_xclient;
3740                 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
3741                 u32 diff;
3742
3743                 /* are storm stats valid? */
3744                 if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3745                                                         bp->stats_counter) {
3746                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
3747                            "  xstorm counter (%d) != stats_counter (%d)\n",
3748                            i, xclient->stats_counter, bp->stats_counter);
3749                         return -1;
3750                 }
3751                 if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3752                                                         bp->stats_counter) {
3753                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
3754                            "  tstorm counter (%d) != stats_counter (%d)\n",
3755                            i, tclient->stats_counter, bp->stats_counter);
3756                         return -2;
3757                 }
3758                 if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) !=
3759                                                         bp->stats_counter) {
3760                         DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
3761                            "  ustorm counter (%d) != stats_counter (%d)\n",
3762                            i, uclient->stats_counter, bp->stats_counter);
3763                         return -4;
3764                 }
3765
3766                 qstats->total_bytes_received_hi =
3767                 qstats->valid_bytes_received_hi =
3768                                 le32_to_cpu(tclient->total_rcv_bytes.hi);
3769                 qstats->total_bytes_received_lo =
3770                 qstats->valid_bytes_received_lo =
3771                                 le32_to_cpu(tclient->total_rcv_bytes.lo);
3772
3773                 qstats->error_bytes_received_hi =
3774                                 le32_to_cpu(tclient->rcv_error_bytes.hi);
3775                 qstats->error_bytes_received_lo =
3776                                 le32_to_cpu(tclient->rcv_error_bytes.lo);
3777
3778                 ADD_64(qstats->total_bytes_received_hi,
3779                        qstats->error_bytes_received_hi,
3780                        qstats->total_bytes_received_lo,
3781                        qstats->error_bytes_received_lo);
3782
3783                 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
3784                                         total_unicast_packets_received);
3785                 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3786                                         total_multicast_packets_received);
3787                 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3788                                         total_broadcast_packets_received);
3789                 UPDATE_EXTEND_TSTAT(packets_too_big_discard,
3790                                         etherstatsoverrsizepkts);
3791                 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
3792
3793                 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
3794                                         total_unicast_packets_received);
3795                 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
3796                                         total_multicast_packets_received);
3797                 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
3798                                         total_broadcast_packets_received);
3799                 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
3800                 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
3801                 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
3802
3803                 qstats->total_bytes_transmitted_hi =
3804                                 le32_to_cpu(xclient->total_sent_bytes.hi);
3805                 qstats->total_bytes_transmitted_lo =
3806                                 le32_to_cpu(xclient->total_sent_bytes.lo);
3807
3808                 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3809                                         total_unicast_packets_transmitted);
3810                 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3811                                         total_multicast_packets_transmitted);
3812                 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3813                                         total_broadcast_packets_transmitted);
3814
3815                 old_tclient->checksum_discard = tclient->checksum_discard;
3816                 old_tclient->ttl0_discard = tclient->ttl0_discard;
3817
3818                 ADD_64(fstats->total_bytes_received_hi,
3819                        qstats->total_bytes_received_hi,
3820                        fstats->total_bytes_received_lo,
3821                        qstats->total_bytes_received_lo);
3822                 ADD_64(fstats->total_bytes_transmitted_hi,
3823                        qstats->total_bytes_transmitted_hi,
3824                        fstats->total_bytes_transmitted_lo,
3825                        qstats->total_bytes_transmitted_lo);
3826                 ADD_64(fstats->total_unicast_packets_received_hi,
3827                        qstats->total_unicast_packets_received_hi,
3828                        fstats->total_unicast_packets_received_lo,
3829                        qstats->total_unicast_packets_received_lo);
3830                 ADD_64(fstats->total_multicast_packets_received_hi,
3831                        qstats->total_multicast_packets_received_hi,
3832                        fstats->total_multicast_packets_received_lo,
3833                        qstats->total_multicast_packets_received_lo);
3834                 ADD_64(fstats->total_broadcast_packets_received_hi,
3835                        qstats->total_broadcast_packets_received_hi,
3836                        fstats->total_broadcast_packets_received_lo,
3837                        qstats->total_broadcast_packets_received_lo);
3838                 ADD_64(fstats->total_unicast_packets_transmitted_hi,
3839                        qstats->total_unicast_packets_transmitted_hi,
3840                        fstats->total_unicast_packets_transmitted_lo,
3841                        qstats->total_unicast_packets_transmitted_lo);
3842                 ADD_64(fstats->total_multicast_packets_transmitted_hi,
3843                        qstats->total_multicast_packets_transmitted_hi,
3844                        fstats->total_multicast_packets_transmitted_lo,
3845                        qstats->total_multicast_packets_transmitted_lo);
3846                 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
3847                        qstats->total_broadcast_packets_transmitted_hi,
3848                        fstats->total_broadcast_packets_transmitted_lo,
3849                        qstats->total_broadcast_packets_transmitted_lo);
3850                 ADD_64(fstats->valid_bytes_received_hi,
3851                        qstats->valid_bytes_received_hi,
3852                        fstats->valid_bytes_received_lo,
3853                        qstats->valid_bytes_received_lo);
3854
3855                 ADD_64(estats->error_bytes_received_hi,
3856                        qstats->error_bytes_received_hi,
3857                        estats->error_bytes_received_lo,
3858                        qstats->error_bytes_received_lo);
3859                 ADD_64(estats->etherstatsoverrsizepkts_hi,
3860                        qstats->etherstatsoverrsizepkts_hi,
3861                        estats->etherstatsoverrsizepkts_lo,
3862                        qstats->etherstatsoverrsizepkts_lo);
3863                 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
3864                        estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
3865         }
3866
3867         ADD_64(fstats->total_bytes_received_hi,
3868                estats->rx_stat_ifhcinbadoctets_hi,
3869                fstats->total_bytes_received_lo,
3870                estats->rx_stat_ifhcinbadoctets_lo);
3871
3872         memcpy(estats, &(fstats->total_bytes_received_hi),
3873                sizeof(struct host_func_stats) - 2*sizeof(u32));
3874
3875         ADD_64(estats->etherstatsoverrsizepkts_hi,
3876                estats->rx_stat_dot3statsframestoolong_hi,
3877                estats->etherstatsoverrsizepkts_lo,
3878                estats->rx_stat_dot3statsframestoolong_lo);
3879         ADD_64(estats->error_bytes_received_hi,
3880                estats->rx_stat_ifhcinbadoctets_hi,
3881                estats->error_bytes_received_lo,
3882                estats->rx_stat_ifhcinbadoctets_lo);
3883
3884         if (bp->port.pmf) {
3885                 estats->mac_filter_discard =
3886                                 le32_to_cpu(tport->mac_filter_discard);
3887                 estats->xxoverflow_discard =
3888                                 le32_to_cpu(tport->xxoverflow_discard);
3889                 estats->brb_truncate_discard =
3890                                 le32_to_cpu(tport->brb_truncate_discard);
3891                 estats->mac_discard = le32_to_cpu(tport->mac_discard);
3892         }
3893
3894         fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3895
3896         bp->stats_pending = 0;
3897
3898         return 0;
3899 }
3900
3901 static void bnx2x_net_stats_update(struct bnx2x *bp)
3902 {
3903         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3904         struct net_device_stats *nstats = &bp->dev->stats;
3905         int i;
3906
3907         nstats->rx_packets =
3908                 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3909                 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3910                 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3911
3912         nstats->tx_packets =
3913                 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3914                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3915                 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3916
3917         nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
3918
3919         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3920
3921         nstats->rx_dropped = estats->mac_discard;
3922         for_each_queue(bp, i)
3923                 nstats->rx_dropped +=
3924                         le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
3925
3926         nstats->tx_dropped = 0;
3927
3928         nstats->multicast =
3929                 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
3930
3931         nstats->collisions =
3932                 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
3933
3934         nstats->rx_length_errors =
3935                 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
3936                 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
3937         nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
3938                                  bnx2x_hilo(&estats->brb_truncate_hi);
3939         nstats->rx_crc_errors =
3940                 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
3941         nstats->rx_frame_errors =
3942                 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
3943         nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
3944         nstats->rx_missed_errors = estats->xxoverflow_discard;
3945
3946         nstats->rx_errors = nstats->rx_length_errors +
3947                             nstats->rx_over_errors +
3948                             nstats->rx_crc_errors +
3949                             nstats->rx_frame_errors +
3950                             nstats->rx_fifo_errors +
3951                             nstats->rx_missed_errors;
3952
3953         nstats->tx_aborted_errors =
3954                 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
3955                 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
3956         nstats->tx_carrier_errors =
3957                 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
3958         nstats->tx_fifo_errors = 0;
3959         nstats->tx_heartbeat_errors = 0;
3960         nstats->tx_window_errors = 0;
3961
3962         nstats->tx_errors = nstats->tx_aborted_errors +
3963                             nstats->tx_carrier_errors +
3964             bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
3965 }
3966
3967 static void bnx2x_drv_stats_update(struct bnx2x *bp)
3968 {
3969         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3970         int i;
3971
3972         estats->driver_xoff = 0;
3973         estats->rx_err_discard_pkt = 0;
3974         estats->rx_skb_alloc_failed = 0;
3975         estats->hw_csum_err = 0;
3976         for_each_queue(bp, i) {
3977                 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
3978
3979                 estats->driver_xoff += qstats->driver_xoff;
3980                 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
3981                 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
3982                 estats->hw_csum_err += qstats->hw_csum_err;
3983         }
3984 }
3985
3986 static void bnx2x_stats_update(struct bnx2x *bp)
3987 {
3988         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3989
3990         if (*stats_comp != DMAE_COMP_VAL)
3991                 return;
3992
3993         if (bp->port.pmf)
3994                 bnx2x_hw_stats_update(bp);
3995
3996         if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
3997                 BNX2X_ERR("storm stats were not updated for 3 times\n");
3998                 bnx2x_panic();
3999                 return;
4000         }
4001
4002         bnx2x_net_stats_update(bp);
4003         bnx2x_drv_stats_update(bp);
4004
4005         if (bp->msglevel & NETIF_MSG_TIMER) {
4006                 struct tstorm_per_client_stats *old_tclient =
4007                                                         &bp->fp->old_tclient;
4008                 struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats;
4009                 struct bnx2x_eth_stats *estats = &bp->eth_stats;
4010                 struct net_device_stats *nstats = &bp->dev->stats;
4011                 int i;
4012
4013                 printk(KERN_DEBUG "%s:\n", bp->dev->name);
4014                 printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
4015                                   "  tx pkt (%lx)\n",
4016                        bnx2x_tx_avail(bp->fp),
4017                        le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
4018                 printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
4019                                   "  rx pkt (%lx)\n",
4020                        (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
4021                              bp->fp->rx_comp_cons),
4022                        le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
4023                 printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u  "
4024                                   "brb truncate %u\n",
4025                        (netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"),
4026                        qstats->driver_xoff,
4027                        estats->brb_drop_lo, estats->brb_truncate_lo);
4028                 printk(KERN_DEBUG "tstats: checksum_discard %u  "
4029                         "packets_too_big_discard %lu  no_buff_discard %lu  "
4030                         "mac_discard %u  mac_filter_discard %u  "
4031                         "xxovrflow_discard %u  brb_truncate_discard %u  "
4032                         "ttl0_discard %u\n",
4033                        le32_to_cpu(old_tclient->checksum_discard),
4034                        bnx2x_hilo(&qstats->etherstatsoverrsizepkts_hi),
4035                        bnx2x_hilo(&qstats->no_buff_discard_hi),
4036                        estats->mac_discard, estats->mac_filter_discard,
4037                        estats->xxoverflow_discard, estats->brb_truncate_discard,
4038                        le32_to_cpu(old_tclient->ttl0_discard));
4039
4040                 for_each_queue(bp, i) {
4041                         printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
4042                                bnx2x_fp(bp, i, tx_pkt),
4043                                bnx2x_fp(bp, i, rx_pkt),
4044                                bnx2x_fp(bp, i, rx_calls));
4045                 }
4046         }
4047
4048         bnx2x_hw_stats_post(bp);
4049         bnx2x_storm_stats_post(bp);
4050 }
4051
4052 static void bnx2x_port_stats_stop(struct bnx2x *bp)
4053 {
4054         struct dmae_command *dmae;
4055         u32 opcode;
4056         int loader_idx = PMF_DMAE_C(bp);
4057         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
4058
4059         bp->executer_idx = 0;
4060
4061         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4062                   DMAE_CMD_C_ENABLE |
4063                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4064 #ifdef __BIG_ENDIAN
4065                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
4066 #else
4067                   DMAE_CMD_ENDIANITY_DW_SWAP |
4068 #endif
4069                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4070                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
4071
4072         if (bp->port.port_stx) {
4073
4074                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4075                 if (bp->func_stx)
4076                         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
4077                 else
4078                         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
4079                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
4080                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
4081                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
4082                 dmae->dst_addr_hi = 0;
4083                 dmae->len = sizeof(struct host_port_stats) >> 2;
4084                 if (bp->func_stx) {
4085                         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4086                         dmae->comp_addr_hi = 0;
4087                         dmae->comp_val = 1;
4088                 } else {
4089                         dmae->comp_addr_lo =
4090                                 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4091                         dmae->comp_addr_hi =
4092                                 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4093                         dmae->comp_val = DMAE_COMP_VAL;
4094
4095                         *stats_comp = 0;
4096                 }
4097         }
4098
4099         if (bp->func_stx) {
4100
4101                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4102                 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
4103                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
4104                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
4105                 dmae->dst_addr_lo = bp->func_stx >> 2;
4106                 dmae->dst_addr_hi = 0;
4107                 dmae->len = sizeof(struct host_func_stats) >> 2;
4108                 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4109                 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4110                 dmae->comp_val = DMAE_COMP_VAL;
4111
4112                 *stats_comp = 0;
4113         }
4114 }
4115
4116 static void bnx2x_stats_stop(struct bnx2x *bp)
4117 {
4118         int update = 0;
4119
4120         bnx2x_stats_comp(bp);
4121
4122         if (bp->port.pmf)
4123                 update = (bnx2x_hw_stats_update(bp) == 0);
4124
4125         update |= (bnx2x_storm_stats_update(bp) == 0);
4126
4127         if (update) {
4128                 bnx2x_net_stats_update(bp);
4129
4130                 if (bp->port.pmf)
4131                         bnx2x_port_stats_stop(bp);
4132
4133                 bnx2x_hw_stats_post(bp);
4134                 bnx2x_stats_comp(bp);
4135         }
4136 }
4137
4138 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
4139 {
4140 }
4141
4142 static const struct {
4143         void (*action)(struct bnx2x *bp);
4144         enum bnx2x_stats_state next_state;
4145 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
4146 /* state        event   */
4147 {
4148 /* DISABLED     PMF     */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
4149 /*              LINK_UP */ {bnx2x_stats_start,      STATS_STATE_ENABLED},
4150 /*              UPDATE  */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
4151 /*              STOP    */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
4152 },
4153 {
4154 /* ENABLED      PMF     */ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
4155 /*              LINK_UP */ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
4156 /*              UPDATE  */ {bnx2x_stats_update,     STATS_STATE_ENABLED},
4157 /*              STOP    */ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
4158 }
4159 };
4160
4161 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
4162 {
4163         enum bnx2x_stats_state state = bp->stats_state;
4164
4165         bnx2x_stats_stm[state][event].action(bp);
4166         bp->stats_state = bnx2x_stats_stm[state][event].next_state;
4167
4168         if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
4169                 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
4170                    state, event, bp->stats_state);
4171 }
4172
4173 static void bnx2x_timer(unsigned long data)
4174 {
4175         struct bnx2x *bp = (struct bnx2x *) data;
4176
4177         if (!netif_running(bp->dev))
4178                 return;
4179
4180         if (atomic_read(&bp->intr_sem) != 0)
4181                 goto timer_restart;
4182
4183         if (poll) {
4184                 struct bnx2x_fastpath *fp = &bp->fp[0];
4185                 int rc;
4186
4187                 bnx2x_tx_int(fp);
4188                 rc = bnx2x_rx_int(fp, 1000);
4189         }
4190
4191         if (!BP_NOMCP(bp)) {
4192                 int func = BP_FUNC(bp);
4193                 u32 drv_pulse;
4194                 u32 mcp_pulse;
4195
4196                 ++bp->fw_drv_pulse_wr_seq;
4197                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4198                 /* TBD - add SYSTEM_TIME */
4199                 drv_pulse = bp->fw_drv_pulse_wr_seq;
4200                 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
4201
4202                 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
4203                              MCP_PULSE_SEQ_MASK);
4204                 /* The delta between driver pulse and mcp response
4205                  * should be 1 (before mcp response) or 0 (after mcp response)
4206                  */
4207                 if ((drv_pulse != mcp_pulse) &&
4208                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4209                         /* someone lost a heartbeat... */
4210                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4211                                   drv_pulse, mcp_pulse);
4212                 }
4213         }
4214
4215         if ((bp->state == BNX2X_STATE_OPEN) ||
4216             (bp->state == BNX2X_STATE_DISABLED))
4217                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4218
4219 timer_restart:
4220         mod_timer(&bp->timer, jiffies + bp->current_interval);
4221 }
4222
4223 /* end of Statistics */
4224
4225 /* nic init */
4226
4227 /*
4228  * nic init service functions
4229  */
4230
4231 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4232 {
4233         int port = BP_PORT(bp);
4234
4235         bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
4236                         USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4237                         sizeof(struct ustorm_status_block)/4);
4238         bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
4239                         CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4240                         sizeof(struct cstorm_status_block)/4);
4241 }
4242
4243 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4244                           dma_addr_t mapping, int sb_id)
4245 {
4246         int port = BP_PORT(bp);
4247         int func = BP_FUNC(bp);
4248         int index;
4249         u64 section;
4250
4251         /* USTORM */
4252         section = ((u64)mapping) + offsetof(struct host_status_block,
4253                                             u_status_block);
4254         sb->u_status_block.status_block_id = sb_id;
4255
4256         REG_WR(bp, BAR_USTRORM_INTMEM +
4257                USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4258         REG_WR(bp, BAR_USTRORM_INTMEM +
4259                ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4260                U64_HI(section));
4261         REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4262                 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4263
4264         for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4265                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4266                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4267
4268         /* CSTORM */
4269         section = ((u64)mapping) + offsetof(struct host_status_block,
4270                                             c_status_block);
4271         sb->c_status_block.status_block_id = sb_id;
4272
4273         REG_WR(bp, BAR_CSTRORM_INTMEM +
4274                CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4275         REG_WR(bp, BAR_CSTRORM_INTMEM +
4276                ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4277                U64_HI(section));
4278         REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4279                 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4280
4281         for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4282                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4283                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4284
4285         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4286 }
4287
4288 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4289 {
4290         int func = BP_FUNC(bp);
4291
4292         bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR +
4293                         TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4294                         sizeof(struct tstorm_def_status_block)/4);
4295         bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
4296                         USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4297                         sizeof(struct ustorm_def_status_block)/4);
4298         bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
4299                         CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4300                         sizeof(struct cstorm_def_status_block)/4);
4301         bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR +
4302                         XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4303                         sizeof(struct xstorm_def_status_block)/4);
4304 }
4305
4306 static void bnx2x_init_def_sb(struct bnx2x *bp,
4307                               struct host_def_status_block *def_sb,
4308                               dma_addr_t mapping, int sb_id)
4309 {
4310         int port = BP_PORT(bp);
4311         int func = BP_FUNC(bp);
4312         int index, val, reg_offset;
4313         u64 section;
4314
4315         /* ATTN */
4316         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4317                                             atten_status_block);
4318         def_sb->atten_status_block.status_block_id = sb_id;
4319
4320         bp->attn_state = 0;
4321
4322         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4323                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4324
4325         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4326                 bp->attn_group[index].sig[0] = REG_RD(bp,
4327                                                      reg_offset + 0x10*index);
4328                 bp->attn_group[index].sig[1] = REG_RD(bp,
4329                                                reg_offset + 0x4 + 0x10*index);
4330                 bp->attn_group[index].sig[2] = REG_RD(bp,
4331                                                reg_offset + 0x8 + 0x10*index);
4332                 bp->attn_group[index].sig[3] = REG_RD(bp,
4333                                                reg_offset + 0xc + 0x10*index);
4334         }
4335
4336         reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4337                              HC_REG_ATTN_MSG0_ADDR_L);
4338
4339         REG_WR(bp, reg_offset, U64_LO(section));
4340         REG_WR(bp, reg_offset + 4, U64_HI(section));
4341
4342         reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4343
4344         val = REG_RD(bp, reg_offset);
4345         val |= sb_id;
4346         REG_WR(bp, reg_offset, val);
4347
4348         /* USTORM */
4349         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4350                                             u_def_status_block);
4351         def_sb->u_def_status_block.status_block_id = sb_id;
4352
4353         REG_WR(bp, BAR_USTRORM_INTMEM +
4354                USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4355         REG_WR(bp, BAR_USTRORM_INTMEM +
4356                ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4357                U64_HI(section));
4358         REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4359                 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4360
4361         for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4362                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4363                          USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4364
4365         /* CSTORM */
4366         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4367                                             c_def_status_block);
4368         def_sb->c_def_status_block.status_block_id = sb_id;
4369
4370         REG_WR(bp, BAR_CSTRORM_INTMEM +
4371                CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4372         REG_WR(bp, BAR_CSTRORM_INTMEM +
4373                ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4374                U64_HI(section));
4375         REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4376                 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4377
4378         for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4379                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4380                          CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4381
4382         /* TSTORM */
4383         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4384                                             t_def_status_block);
4385         def_sb->t_def_status_block.status_block_id = sb_id;
4386
4387         REG_WR(bp, BAR_TSTRORM_INTMEM +
4388                TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4389         REG_WR(bp, BAR_TSTRORM_INTMEM +
4390                ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4391                U64_HI(section));
4392         REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4393                 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4394
4395         for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4396                 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4397                          TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4398
4399         /* XSTORM */
4400         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4401                                             x_def_status_block);
4402         def_sb->x_def_status_block.status_block_id = sb_id;
4403
4404         REG_WR(bp, BAR_XSTRORM_INTMEM +
4405                XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4406         REG_WR(bp, BAR_XSTRORM_INTMEM +
4407                ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4408                U64_HI(section));
4409         REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4410                 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4411
4412         for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4413                 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4414                          XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4415
4416         bp->stats_pending = 0;
4417         bp->set_mac_pending = 0;
4418
4419         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4420 }
4421
4422 static void bnx2x_update_coalesce(struct bnx2x *bp)
4423 {
4424         int port = BP_PORT(bp);
4425         int i;
4426
4427         for_each_queue(bp, i) {
4428                 int sb_id = bp->fp[i].sb_id;
4429
4430                 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4431                 REG_WR8(bp, BAR_USTRORM_INTMEM +
4432                         USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4433                                                     U_SB_ETH_RX_CQ_INDEX),
4434                         bp->rx_ticks/12);
4435                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4436                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4437                                                      U_SB_ETH_RX_CQ_INDEX),
4438                          (bp->rx_ticks/12) ? 0 : 1);
4439
4440                 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4441                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4442                         CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4443                                                     C_SB_ETH_TX_CQ_INDEX),
4444                         bp->tx_ticks/12);
4445                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4446                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4447                                                      C_SB_ETH_TX_CQ_INDEX),
4448                          (bp->tx_ticks/12) ? 0 : 1);
4449         }
4450 }
4451
4452 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4453                                        struct bnx2x_fastpath *fp, int last)
4454 {
4455         int i;
4456
4457         for (i = 0; i < last; i++) {
4458                 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4459                 struct sk_buff *skb = rx_buf->skb;
4460
4461                 if (skb == NULL) {
4462                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4463                         continue;
4464                 }
4465
4466                 if (fp->tpa_state[i] == BNX2X_TPA_START)
4467                         pci_unmap_single(bp->pdev,
4468                                          pci_unmap_addr(rx_buf, mapping),
4469                                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4470
4471                 dev_kfree_skb(skb);
4472                 rx_buf->skb = NULL;
4473         }
4474 }
4475
4476 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4477 {
4478         int func = BP_FUNC(bp);
4479         int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4480                                               ETH_MAX_AGGREGATION_QUEUES_E1H;
4481         u16 ring_prod, cqe_ring_prod;
4482         int i, j;
4483
4484         bp->rx_buf_size = bp->dev->mtu + ETH_OVREHEAD + BNX2X_RX_ALIGN;
4485         DP(NETIF_MSG_IFUP,
4486            "mtu %d  rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
4487
4488         if (bp->flags & TPA_ENABLE_FLAG) {
4489
4490                 for_each_rx_queue(bp, j) {
4491                         struct bnx2x_fastpath *fp = &bp->fp[j];
4492
4493                         for (i = 0; i < max_agg_queues; i++) {
4494                                 fp->tpa_pool[i].skb =
4495                                    netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4496                                 if (!fp->tpa_pool[i].skb) {
4497                                         BNX2X_ERR("Failed to allocate TPA "
4498                                                   "skb pool for queue[%d] - "
4499                                                   "disabling TPA on this "
4500                                                   "queue!\n", j);
4501                                         bnx2x_free_tpa_pool(bp, fp, i);
4502                                         fp->disable_tpa = 1;
4503                                         break;
4504                                 }
4505                                 pci_unmap_addr_set((struct sw_rx_bd *)
4506                                                         &bp->fp->tpa_pool[i],
4507                                                    mapping, 0);
4508                                 fp->tpa_state[i] = BNX2X_TPA_STOP;
4509                         }
4510                 }
4511         }
4512
4513         for_each_rx_queue(bp, j) {
4514                 struct bnx2x_fastpath *fp = &bp->fp[j];
4515
4516                 fp->rx_bd_cons = 0;
4517                 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4518                 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4519
4520                 /* "next page" elements initialization */
4521                 /* SGE ring */
4522                 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4523                         struct eth_rx_sge *sge;
4524
4525                         sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4526                         sge->addr_hi =
4527                                 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4528                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4529                         sge->addr_lo =
4530                                 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4531                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4532                 }
4533
4534                 bnx2x_init_sge_ring_bit_mask(fp);
4535
4536                 /* RX BD ring */
4537                 for (i = 1; i <= NUM_RX_RINGS; i++) {
4538                         struct eth_rx_bd *rx_bd;
4539
4540                         rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4541                         rx_bd->addr_hi =
4542                                 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4543                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4544                         rx_bd->addr_lo =
4545                                 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4546                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4547                 }
4548
4549                 /* CQ ring */
4550                 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4551                         struct eth_rx_cqe_next_page *nextpg;
4552
4553                         nextpg = (struct eth_rx_cqe_next_page *)
4554                                 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4555                         nextpg->addr_hi =
4556                                 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4557                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4558                         nextpg->addr_lo =
4559                                 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4560                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4561                 }
4562
4563                 /* Allocate SGEs and initialize the ring elements */
4564                 for (i = 0, ring_prod = 0;
4565                      i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4566
4567                         if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4568                                 BNX2X_ERR("was only able to allocate "
4569                                           "%d rx sges\n", i);
4570                                 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4571                                 /* Cleanup already allocated elements */
4572                                 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4573                                 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4574                                 fp->disable_tpa = 1;
4575                                 ring_prod = 0;
4576                                 break;
4577                         }
4578                         ring_prod = NEXT_SGE_IDX(ring_prod);
4579                 }
4580                 fp->rx_sge_prod = ring_prod;
4581
4582                 /* Allocate BDs and initialize BD ring */
4583                 fp->rx_comp_cons = 0;
4584                 cqe_ring_prod = ring_prod = 0;
4585                 for (i = 0; i < bp->rx_ring_size; i++) {
4586                         if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4587                                 BNX2X_ERR("was only able to allocate "
4588                                           "%d rx skbs on queue[%d]\n", i, j);
4589                                 fp->eth_q_stats.rx_skb_alloc_failed++;
4590                                 break;
4591                         }
4592                         ring_prod = NEXT_RX_IDX(ring_prod);
4593                         cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4594                         WARN_ON(ring_prod <= i);
4595                 }
4596
4597                 fp->rx_bd_prod = ring_prod;
4598                 /* must not have more available CQEs than BDs */
4599                 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4600                                        cqe_ring_prod);
4601                 fp->rx_pkt = fp->rx_calls = 0;
4602
4603                 /* Warning!
4604                  * this will generate an interrupt (to the TSTORM)
4605                  * must only be done after chip is initialized
4606                  */
4607                 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4608                                      fp->rx_sge_prod);
4609                 if (j != 0)
4610                         continue;
4611
4612                 REG_WR(bp, BAR_USTRORM_INTMEM +
4613                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4614                        U64_LO(fp->rx_comp_mapping));
4615                 REG_WR(bp, BAR_USTRORM_INTMEM +
4616                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4617                        U64_HI(fp->rx_comp_mapping));
4618         }
4619 }
4620
4621 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4622 {
4623         int i, j;
4624
4625         for_each_tx_queue(bp, j) {
4626                 struct bnx2x_fastpath *fp = &bp->fp[j];
4627
4628                 for (i = 1; i <= NUM_TX_RINGS; i++) {
4629                         struct eth_tx_bd *tx_bd =
4630                                 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4631
4632                         tx_bd->addr_hi =
4633                                 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4634                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4635                         tx_bd->addr_lo =
4636                                 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4637                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4638                 }
4639
4640                 fp->tx_pkt_prod = 0;
4641                 fp->tx_pkt_cons = 0;
4642                 fp->tx_bd_prod = 0;
4643                 fp->tx_bd_cons = 0;
4644                 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4645                 fp->tx_pkt = 0;
4646         }
4647 }
4648
4649 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4650 {
4651         int func = BP_FUNC(bp);
4652
4653         spin_lock_init(&bp->spq_lock);
4654
4655         bp->spq_left = MAX_SPQ_PENDING;
4656         bp->spq_prod_idx = 0;
4657         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4658         bp->spq_prod_bd = bp->spq;
4659         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4660
4661         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4662                U64_LO(bp->spq_mapping));
4663         REG_WR(bp,
4664                XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4665                U64_HI(bp->spq_mapping));
4666
4667         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4668                bp->spq_prod_idx);
4669 }
4670
4671 static void bnx2x_init_context(struct bnx2x *bp)
4672 {
4673         int i;
4674
4675         for_each_queue(bp, i) {
4676                 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4677                 struct bnx2x_fastpath *fp = &bp->fp[i];
4678                 u8 cl_id = fp->cl_id;
4679                 u8 sb_id = fp->sb_id;
4680
4681                 context->ustorm_st_context.common.sb_index_numbers =
4682                                                 BNX2X_RX_SB_INDEX_NUM;
4683                 context->ustorm_st_context.common.clientId = cl_id;
4684                 context->ustorm_st_context.common.status_block_id = sb_id;
4685                 context->ustorm_st_context.common.flags =
4686                         (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
4687                          USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
4688                 context->ustorm_st_context.common.statistics_counter_id =
4689                                                 cl_id;
4690                 context->ustorm_st_context.common.mc_alignment_log_size =
4691                                                 BNX2X_RX_ALIGN_SHIFT;
4692                 context->ustorm_st_context.common.bd_buff_size =
4693                                                 bp->rx_buf_size;
4694                 context->ustorm_st_context.common.bd_page_base_hi =
4695                                                 U64_HI(fp->rx_desc_mapping);
4696                 context->ustorm_st_context.common.bd_page_base_lo =
4697                                                 U64_LO(fp->rx_desc_mapping);
4698                 if (!fp->disable_tpa) {
4699                         context->ustorm_st_context.common.flags |=
4700                                 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4701                                  USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4702                         context->ustorm_st_context.common.sge_buff_size =
4703                                 (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
4704                                          (u32)0xffff);
4705                         context->ustorm_st_context.common.sge_page_base_hi =
4706                                                 U64_HI(fp->rx_sge_mapping);
4707                         context->ustorm_st_context.common.sge_page_base_lo =
4708                                                 U64_LO(fp->rx_sge_mapping);
4709                 }
4710
4711                 context->ustorm_ag_context.cdu_usage =
4712                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4713                                                CDU_REGION_NUMBER_UCM_AG,
4714                                                ETH_CONNECTION_TYPE);
4715
4716                 context->xstorm_st_context.tx_bd_page_base_hi =
4717                                                 U64_HI(fp->tx_desc_mapping);
4718                 context->xstorm_st_context.tx_bd_page_base_lo =
4719                                                 U64_LO(fp->tx_desc_mapping);
4720                 context->xstorm_st_context.db_data_addr_hi =
4721                                                 U64_HI(fp->tx_prods_mapping);
4722                 context->xstorm_st_context.db_data_addr_lo =
4723                                                 U64_LO(fp->tx_prods_mapping);
4724                 context->xstorm_st_context.statistics_data = (cl_id |
4725                                 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4726                 context->cstorm_st_context.sb_index_number =
4727                                                 C_SB_ETH_TX_CQ_INDEX;
4728                 context->cstorm_st_context.status_block_id = sb_id;
4729
4730                 context->xstorm_ag_context.cdu_reserved =
4731                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4732                                                CDU_REGION_NUMBER_XCM_AG,
4733                                                ETH_CONNECTION_TYPE);
4734         }
4735 }
4736
4737 static void bnx2x_init_ind_table(struct bnx2x *bp)
4738 {
4739         int func = BP_FUNC(bp);
4740         int i;
4741
4742         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4743                 return;
4744
4745         DP(NETIF_MSG_IFUP,
4746            "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
4747         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4748                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4749                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4750                         bp->fp->cl_id + (i % bp->num_rx_queues));
4751 }
4752
4753 static void bnx2x_set_client_config(struct bnx2x *bp)
4754 {
4755         struct tstorm_eth_client_config tstorm_client = {0};
4756         int port = BP_PORT(bp);
4757         int i;
4758
4759         tstorm_client.mtu = bp->dev->mtu;
4760         tstorm_client.config_flags =
4761                                 (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
4762                                  TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
4763 #ifdef BCM_VLAN
4764         if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
4765                 tstorm_client.config_flags |=
4766                                 TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
4767                 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4768         }
4769 #endif
4770
4771         if (bp->flags & TPA_ENABLE_FLAG) {
4772                 tstorm_client.max_sges_for_packet =
4773                         SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT;
4774                 tstorm_client.max_sges_for_packet =
4775                         ((tstorm_client.max_sges_for_packet +
4776                           PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4777                         PAGES_PER_SGE_SHIFT;
4778
4779                 tstorm_client.config_flags |=
4780                                 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4781         }
4782
4783         for_each_queue(bp, i) {
4784                 tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
4785
4786                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4787                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4788                        ((u32 *)&tstorm_client)[0]);
4789                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4790                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4791                        ((u32 *)&tstorm_client)[1]);
4792         }
4793
4794         DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4795            ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4796 }
4797
4798 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4799 {
4800         struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4801         int mode = bp->rx_mode;
4802         int mask = (1 << BP_L_ID(bp));
4803         int func = BP_FUNC(bp);
4804         int i;
4805
4806         DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
4807
4808         switch (mode) {
4809         case BNX2X_RX_MODE_NONE: /* no Rx */
4810                 tstorm_mac_filter.ucast_drop_all = mask;
4811                 tstorm_mac_filter.mcast_drop_all = mask;
4812                 tstorm_mac_filter.bcast_drop_all = mask;
4813                 break;
4814
4815         case BNX2X_RX_MODE_NORMAL:
4816                 tstorm_mac_filter.bcast_accept_all = mask;
4817                 break;
4818
4819         case BNX2X_RX_MODE_ALLMULTI:
4820                 tstorm_mac_filter.mcast_accept_all = mask;
4821                 tstorm_mac_filter.bcast_accept_all = mask;
4822                 break;
4823
4824         case BNX2X_RX_MODE_PROMISC:
4825                 tstorm_mac_filter.ucast_accept_all = mask;
4826                 tstorm_mac_filter.mcast_accept_all = mask;
4827                 tstorm_mac_filter.bcast_accept_all = mask;
4828                 break;
4829
4830         default:
4831                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4832                 break;
4833         }
4834
4835         for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4836                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4837                        TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4838                        ((u32 *)&tstorm_mac_filter)[i]);
4839
4840 /*              DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4841                    ((u32 *)&tstorm_mac_filter)[i]); */
4842         }
4843
4844         if (mode != BNX2X_RX_MODE_NONE)
4845                 bnx2x_set_client_config(bp);
4846 }
4847
4848 static void bnx2x_init_internal_common(struct bnx2x *bp)
4849 {
4850         int i;
4851
4852         if (bp->flags & TPA_ENABLE_FLAG) {
4853                 struct tstorm_eth_tpa_exist tpa = {0};
4854
4855                 tpa.tpa_exist = 1;
4856
4857                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
4858                        ((u32 *)&tpa)[0]);
4859                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
4860                        ((u32 *)&tpa)[1]);
4861         }
4862
4863         /* Zero this manually as its initialization is
4864            currently missing in the initTool */
4865         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4866                 REG_WR(bp, BAR_USTRORM_INTMEM +
4867                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
4868 }
4869
4870 static void bnx2x_init_internal_port(struct bnx2x *bp)
4871 {
4872         int port = BP_PORT(bp);
4873
4874         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4875         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4876         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4877         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4878 }
4879
4880 /* Calculates the sum of vn_min_rates.
4881    It's needed for further normalizing of the min_rates.
4882    Returns:
4883      sum of vn_min_rates.
4884        or
4885      0 - if all the min_rates are 0.
4886      In the later case fainess algorithm should be deactivated.
4887      If not all min_rates are zero then those that are zeroes will be set to 1.
4888  */
4889 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
4890 {
4891         int all_zero = 1;
4892         int port = BP_PORT(bp);
4893         int vn;
4894
4895         bp->vn_weight_sum = 0;
4896         for (vn = VN_0; vn < E1HVN_MAX; vn++) {
4897                 int func = 2*vn + port;
4898                 u32 vn_cfg =
4899                         SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
4900                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
4901                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
4902
4903                 /* Skip hidden vns */
4904                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
4905                         continue;
4906
4907                 /* If min rate is zero - set it to 1 */
4908                 if (!vn_min_rate)
4909                         vn_min_rate = DEF_MIN_RATE;
4910                 else
4911                         all_zero = 0;
4912
4913                 bp->vn_weight_sum += vn_min_rate;
4914         }
4915
4916         /* ... only if all min rates are zeros - disable fairness */
4917         if (all_zero)
4918                 bp->vn_weight_sum = 0;
4919 }
4920
4921 static void bnx2x_init_internal_func(struct bnx2x *bp)
4922 {
4923         struct tstorm_eth_function_common_config tstorm_config = {0};
4924         struct stats_indication_flags stats_flags = {0};
4925         int port = BP_PORT(bp);
4926         int func = BP_FUNC(bp);
4927         int i, j;
4928         u32 offset;
4929         u16 max_agg_size;
4930
4931         if (is_multi(bp)) {
4932                 tstorm_config.config_flags = MULTI_FLAGS(bp);
4933                 tstorm_config.rss_result_mask = MULTI_MASK;
4934         }
4935         if (IS_E1HMF(bp))
4936                 tstorm_config.config_flags |=
4937                                 TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
4938
4939         tstorm_config.leading_client_id = BP_L_ID(bp);
4940
4941         REG_WR(bp, BAR_TSTRORM_INTMEM +
4942                TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4943                (*(u32 *)&tstorm_config));
4944
4945         bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4946         bnx2x_set_storm_rx_mode(bp);
4947
4948         for_each_queue(bp, i) {
4949                 u8 cl_id = bp->fp[i].cl_id;
4950
4951                 /* reset xstorm per client statistics */
4952                 offset = BAR_XSTRORM_INTMEM +
4953                          XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4954                 for (j = 0;
4955                      j < sizeof(struct xstorm_per_client_stats) / 4; j++)
4956                         REG_WR(bp, offset + j*4, 0);
4957
4958                 /* reset tstorm per client statistics */
4959                 offset = BAR_TSTRORM_INTMEM +
4960                          TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4961                 for (j = 0;
4962                      j < sizeof(struct tstorm_per_client_stats) / 4; j++)
4963                         REG_WR(bp, offset + j*4, 0);
4964
4965                 /* reset ustorm per client statistics */
4966                 offset = BAR_USTRORM_INTMEM +
4967                          USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
4968                 for (j = 0;
4969                      j < sizeof(struct ustorm_per_client_stats) / 4; j++)
4970                         REG_WR(bp, offset + j*4, 0);
4971         }
4972
4973         /* Init statistics related context */
4974         stats_flags.collect_eth = 1;
4975
4976         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4977                ((u32 *)&stats_flags)[0]);
4978         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4979                ((u32 *)&stats_flags)[1]);
4980
4981         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4982                ((u32 *)&stats_flags)[0]);
4983         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4984                ((u32 *)&stats_flags)[1]);
4985
4986         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
4987                ((u32 *)&stats_flags)[0]);
4988         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
4989                ((u32 *)&stats_flags)[1]);
4990
4991         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4992                ((u32 *)&stats_flags)[0]);
4993         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4994                ((u32 *)&stats_flags)[1]);
4995
4996         REG_WR(bp, BAR_XSTRORM_INTMEM +
4997                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4998                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4999         REG_WR(bp, BAR_XSTRORM_INTMEM +
5000                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
5001                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
5002
5003         REG_WR(bp, BAR_TSTRORM_INTMEM +
5004                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
5005                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
5006         REG_WR(bp, BAR_TSTRORM_INTMEM +
5007                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
5008                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
5009
5010         REG_WR(bp, BAR_USTRORM_INTMEM +
5011                USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
5012                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
5013         REG_WR(bp, BAR_USTRORM_INTMEM +
5014                USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
5015                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
5016
5017         if (CHIP_IS_E1H(bp)) {
5018                 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
5019                         IS_E1HMF(bp));
5020                 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
5021                         IS_E1HMF(bp));
5022                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
5023                         IS_E1HMF(bp));
5024                 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
5025                         IS_E1HMF(bp));
5026
5027                 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
5028                          bp->e1hov);
5029         }
5030
5031         /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
5032         max_agg_size =
5033                 min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
5034                           SGE_PAGE_SIZE * PAGES_PER_SGE),
5035                     (u32)0xffff);
5036         for_each_rx_queue(bp, i) {
5037                 struct bnx2x_fastpath *fp = &bp->fp[i];
5038
5039                 REG_WR(bp, BAR_USTRORM_INTMEM +
5040                        USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
5041                        U64_LO(fp->rx_comp_mapping));
5042                 REG_WR(bp, BAR_USTRORM_INTMEM +
5043                        USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
5044                        U64_HI(fp->rx_comp_mapping));
5045
5046                 REG_WR16(bp, BAR_USTRORM_INTMEM +
5047                          USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
5048                          max_agg_size);
5049         }
5050
5051         /* dropless flow control */
5052         if (CHIP_IS_E1H(bp)) {
5053                 struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
5054
5055                 rx_pause.bd_thr_low = 250;
5056                 rx_pause.cqe_thr_low = 250;
5057                 rx_pause.cos = 1;
5058                 rx_pause.sge_thr_low = 0;
5059                 rx_pause.bd_thr_high = 350;
5060                 rx_pause.cqe_thr_high = 350;
5061                 rx_pause.sge_thr_high = 0;
5062
5063                 for_each_rx_queue(bp, i) {
5064                         struct bnx2x_fastpath *fp = &bp->fp[i];
5065
5066                         if (!fp->disable_tpa) {
5067                                 rx_pause.sge_thr_low = 150;
5068                                 rx_pause.sge_thr_high = 250;
5069                         }
5070
5071
5072                         offset = BAR_USTRORM_INTMEM +
5073                                  USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
5074                                                                    fp->cl_id);
5075                         for (j = 0;
5076                              j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
5077                              j++)
5078                                 REG_WR(bp, offset + j*4,
5079                                        ((u32 *)&rx_pause)[j]);
5080                 }
5081         }
5082
5083         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
5084
5085         /* Init rate shaping and fairness contexts */
5086         if (IS_E1HMF(bp)) {
5087                 int vn;
5088
5089                 /* During init there is no active link
5090                    Until link is up, set link rate to 10Gbps */
5091                 bp->link_vars.line_speed = SPEED_10000;
5092                 bnx2x_init_port_minmax(bp);
5093
5094                 bnx2x_calc_vn_weight_sum(bp);
5095
5096                 for (vn = VN_0; vn < E1HVN_MAX; vn++)
5097                         bnx2x_init_vn_minmax(bp, 2*vn + port);
5098
5099                 /* Enable rate shaping and fairness */
5100                 bp->cmng.flags.cmng_enables =
5101                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5102                 if (bp->vn_weight_sum)
5103                         bp->cmng.flags.cmng_enables |=
5104                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5105                 else
5106                         DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
5107                            "  fairness will be disabled\n");
5108         } else {
5109                 /* rate shaping and fairness are disabled */
5110                 DP(NETIF_MSG_IFUP,
5111                    "single function mode  minmax will be disabled\n");
5112         }
5113
5114
5115         /* Store it to internal memory */
5116         if (bp->port.pmf)
5117                 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
5118                         REG_WR(bp, BAR_XSTRORM_INTMEM +
5119                                XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
5120                                ((u32 *)(&bp->cmng))[i]);
5121 }
5122
5123 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5124 {
5125         switch (load_code) {
5126         case FW_MSG_CODE_DRV_LOAD_COMMON:
5127                 bnx2x_init_internal_common(bp);
5128                 /* no break */
5129
5130         case FW_MSG_CODE_DRV_LOAD_PORT:
5131                 bnx2x_init_internal_port(bp);
5132                 /* no break */
5133
5134         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5135                 bnx2x_init_internal_func(bp);
5136                 break;
5137
5138         default:
5139                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5140                 break;
5141         }
5142 }
5143
5144 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5145 {
5146         int i;
5147
5148         for_each_queue(bp, i) {
5149                 struct bnx2x_fastpath *fp = &bp->fp[i];
5150
5151                 fp->bp = bp;
5152                 fp->state = BNX2X_FP_STATE_CLOSED;
5153                 fp->index = i;
5154                 fp->cl_id = BP_L_ID(bp) + i;
5155                 fp->sb_id = fp->cl_id;
5156                 DP(NETIF_MSG_IFUP,
5157                    "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  sb %d\n",
5158                    i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
5159                 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
5160                               fp->sb_id);
5161                 bnx2x_update_fpsb_idx(fp);
5162         }
5163
5164         /* ensure status block indices were read */
5165         rmb();
5166
5167
5168         bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
5169                           DEF_SB_ID);
5170         bnx2x_update_dsb_idx(bp);
5171         bnx2x_update_coalesce(bp);
5172         bnx2x_init_rx_rings(bp);
5173         bnx2x_init_tx_ring(bp);
5174         bnx2x_init_sp_ring(bp);
5175         bnx2x_init_context(bp);
5176         bnx2x_init_internal(bp, load_code);
5177         bnx2x_init_ind_table(bp);
5178         bnx2x_stats_init(bp);
5179
5180         /* At this point, we are ready for interrupts */
5181         atomic_set(&bp->intr_sem, 0);
5182
5183         /* flush all before enabling interrupts */
5184         mb();
5185         mmiowb();
5186
5187         bnx2x_int_enable(bp);
5188 }
5189
5190 /* end of nic init */
5191
5192 /*
5193  * gzip service functions
5194  */
5195
5196 static int bnx2x_gunzip_init(struct bnx2x *bp)
5197 {
5198         bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
5199                                               &bp->gunzip_mapping);
5200         if (bp->gunzip_buf  == NULL)
5201                 goto gunzip_nomem1;
5202
5203         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5204         if (bp->strm  == NULL)
5205                 goto gunzip_nomem2;
5206
5207         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
5208                                       GFP_KERNEL);
5209         if (bp->strm->workspace == NULL)
5210                 goto gunzip_nomem3;
5211
5212         return 0;
5213
5214 gunzip_nomem3:
5215         kfree(bp->strm);
5216         bp->strm = NULL;
5217
5218 gunzip_nomem2:
5219         pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5220                             bp->gunzip_mapping);
5221         bp->gunzip_buf = NULL;
5222
5223 gunzip_nomem1:
5224         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
5225                " un-compression\n", bp->dev->name);
5226         return -ENOMEM;
5227 }
5228
5229 static void bnx2x_gunzip_end(struct bnx2x *bp)
5230 {
5231         kfree(bp->strm->workspace);
5232
5233         kfree(bp->strm);
5234         bp->strm = NULL;
5235
5236         if (bp->gunzip_buf) {
5237                 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
5238                                     bp->gunzip_mapping);
5239                 bp->gunzip_buf = NULL;
5240         }
5241 }
5242
5243 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5244 {
5245         int n, rc;
5246
5247         /* check gzip header */
5248         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5249                 BNX2X_ERR("Bad gzip header\n");
5250                 return -EINVAL;
5251         }
5252
5253         n = 10;
5254
5255 #define FNAME                           0x8
5256
5257         if (zbuf[3] & FNAME)
5258                 while ((zbuf[n++] != 0) && (n < len));
5259
5260         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5261         bp->strm->avail_in = len - n;
5262         bp->strm->next_out = bp->gunzip_buf;
5263         bp->strm->avail_out = FW_BUF_SIZE;
5264
5265         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5266         if (rc != Z_OK)
5267                 return rc;
5268
5269         rc = zlib_inflate(bp->strm, Z_FINISH);
5270         if ((rc != Z_OK) && (rc != Z_STREAM_END))
5271                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
5272                        bp->dev->name, bp->strm->msg);
5273
5274         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5275         if (bp->gunzip_outlen & 0x3)
5276                 printk(KERN_ERR PFX "%s: Firmware decompression error:"
5277                                     " gunzip_outlen (%d) not aligned\n",
5278                        bp->dev->name, bp->gunzip_outlen);
5279         bp->gunzip_outlen >>= 2;
5280
5281         zlib_inflateEnd(bp->strm);
5282
5283         if (rc == Z_STREAM_END)
5284                 return 0;
5285
5286         return rc;
5287 }
5288
5289 /* nic load/unload */
5290
5291 /*
5292  * General service functions
5293  */
5294
5295 /* send a NIG loopback debug packet */
5296 static void bnx2x_lb_pckt(struct bnx2x *bp)
5297 {
5298         u32 wb_write[3];
5299
5300         /* Ethernet source and destination addresses */
5301         wb_write[0] = 0x55555555;
5302         wb_write[1] = 0x55555555;
5303         wb_write[2] = 0x20;             /* SOP */
5304         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5305
5306         /* NON-IP protocol */
5307         wb_write[0] = 0x09000000;
5308         wb_write[1] = 0x55555555;
5309         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
5310         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5311 }
5312
5313 /* some of the internal memories
5314  * are not directly readable from the driver
5315  * to test them we send debug packets
5316  */
5317 static int bnx2x_int_mem_test(struct bnx2x *bp)
5318 {
5319         int factor;
5320         int count, i;
5321         u32 val = 0;
5322
5323         if (CHIP_REV_IS_FPGA(bp))
5324                 factor = 120;
5325         else if (CHIP_REV_IS_EMUL(bp))
5326                 factor = 200;
5327         else
5328                 factor = 1;
5329
5330         DP(NETIF_MSG_HW, "start part1\n");
5331
5332         /* Disable inputs of parser neighbor blocks */
5333         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5334         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5335         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5336         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5337
5338         /*  Write 0 to parser credits for CFC search request */
5339         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5340
5341         /* send Ethernet packet */
5342         bnx2x_lb_pckt(bp);
5343
5344         /* TODO do i reset NIG statistic? */
5345         /* Wait until NIG register shows 1 packet of size 0x10 */
5346         count = 1000 * factor;
5347         while (count) {
5348
5349                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5350                 val = *bnx2x_sp(bp, wb_data[0]);
5351                 if (val == 0x10)
5352                         break;
5353
5354                 msleep(10);
5355                 count--;
5356         }
5357         if (val != 0x10) {
5358                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5359                 return -1;
5360         }
5361
5362         /* Wait until PRS register shows 1 packet */
5363         count = 1000 * factor;
5364         while (count) {
5365                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5366                 if (val == 1)
5367                         break;
5368
5369                 msleep(10);
5370                 count--;
5371         }
5372         if (val != 0x1) {
5373                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5374                 return -2;
5375         }
5376
5377         /* Reset and init BRB, PRS */
5378         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5379         msleep(50);
5380         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5381         msleep(50);
5382         bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5383         bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5384
5385         DP(NETIF_MSG_HW, "part2\n");
5386
5387         /* Disable inputs of parser neighbor blocks */
5388         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5389         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5390         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5391         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5392
5393         /* Write 0 to parser credits for CFC search request */
5394         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5395
5396         /* send 10 Ethernet packets */
5397         for (i = 0; i < 10; i++)
5398                 bnx2x_lb_pckt(bp);
5399
5400         /* Wait until NIG register shows 10 + 1
5401            packets of size 11*0x10 = 0xb0 */
5402         count = 1000 * factor;
5403         while (count) {
5404
5405                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5406                 val = *bnx2x_sp(bp, wb_data[0]);
5407                 if (val == 0xb0)
5408                         break;
5409
5410                 msleep(10);
5411                 count--;
5412         }
5413         if (val != 0xb0) {
5414                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5415                 return -3;
5416         }
5417
5418         /* Wait until PRS register shows 2 packets */
5419         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5420         if (val != 2)
5421                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5422
5423         /* Write 1 to parser credits for CFC search request */
5424         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5425
5426         /* Wait until PRS register shows 3 packets */
5427         msleep(10 * factor);
5428         /* Wait until NIG register shows 1 packet of size 0x10 */
5429         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5430         if (val != 3)
5431                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5432
5433         /* clear NIG EOP FIFO */
5434         for (i = 0; i < 11; i++)
5435                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5436         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5437         if (val != 1) {
5438                 BNX2X_ERR("clear of NIG failed\n");
5439                 return -4;
5440         }
5441
5442         /* Reset and init BRB, PRS, NIG */
5443         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5444         msleep(50);
5445         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5446         msleep(50);
5447         bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5448         bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5449 #ifndef BCM_ISCSI
5450         /* set NIC mode */
5451         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5452 #endif
5453
5454         /* Enable inputs of parser neighbor blocks */
5455         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5456         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5457         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5458         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5459
5460         DP(NETIF_MSG_HW, "done\n");
5461
5462         return 0; /* OK */
5463 }
5464
5465 static void enable_blocks_attention(struct bnx2x *bp)
5466 {
5467         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5468         REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5469         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5470         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5471         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5472         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5473         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5474         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5475         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5476 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5477 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5478         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5479         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5480         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5481 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5482 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5483         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5484         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5485         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5486         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5487 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5488 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5489         if (CHIP_REV_IS_FPGA(bp))
5490                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5491         else
5492                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5493         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5494         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5495         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5496 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5497 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5498         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5499         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5500 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5501         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
5502 }
5503
5504
5505 static void bnx2x_reset_common(struct bnx2x *bp)
5506 {
5507         /* reset_common */
5508         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5509                0xd3ffff7f);
5510         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
5511 }
5512
5513
5514 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5515 {
5516         u32 val;
5517         u8 port;
5518         u8 is_required = 0;
5519
5520         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5521               SHARED_HW_CFG_FAN_FAILURE_MASK;
5522
5523         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5524                 is_required = 1;
5525
5526         /*
5527          * The fan failure mechanism is usually related to the PHY type since
5528          * the power consumption of the board is affected by the PHY. Currently,
5529          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5530          */
5531         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5532                 for (port = PORT_0; port < PORT_MAX; port++) {
5533                         u32 phy_type =
5534                                 SHMEM_RD(bp, dev_info.port_hw_config[port].
5535                                          external_phy_config) &
5536                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
5537                         is_required |=
5538                                 ((phy_type ==
5539                                   PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
5540                                  (phy_type ==
5541                                   PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
5542                 }
5543
5544         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5545
5546         if (is_required == 0)
5547                 return;
5548
5549         /* Fan failure is indicated by SPIO 5 */
5550         bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5551                        MISC_REGISTERS_SPIO_INPUT_HI_Z);
5552
5553         /* set to active low mode */
5554         val = REG_RD(bp, MISC_REG_SPIO_INT);
5555         val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5556                                 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5557         REG_WR(bp, MISC_REG_SPIO_INT, val);
5558
5559         /* enable interrupt to signal the IGU */
5560         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5561         val |= (1 << MISC_REGISTERS_SPIO_5);
5562         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5563 }
5564
5565 static int bnx2x_init_common(struct bnx2x *bp)
5566 {
5567         u32 val, i;
5568
5569         DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
5570
5571         bnx2x_reset_common(bp);
5572         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5573         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5574
5575         bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
5576         if (CHIP_IS_E1H(bp))
5577                 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5578
5579         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5580         msleep(30);
5581         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5582
5583         bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
5584         if (CHIP_IS_E1(bp)) {
5585                 /* enable HW interrupt from PXP on USDM overflow
5586                    bit 16 on INT_MASK_0 */
5587                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5588         }
5589
5590         bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
5591         bnx2x_init_pxp(bp);
5592
5593 #ifdef __BIG_ENDIAN
5594         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5595         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5596         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5597         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5598         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5599         /* make sure this value is 0 */
5600         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5601
5602 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5603         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5604         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5605         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5606         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5607 #endif
5608
5609         REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5610 #ifdef BCM_ISCSI
5611         REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5612         REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5613         REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5614 #endif
5615
5616         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5617                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5618
5619         /* let the HW do it's magic ... */
5620         msleep(100);
5621         /* finish PXP init */
5622         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5623         if (val != 1) {
5624                 BNX2X_ERR("PXP2 CFG failed\n");
5625                 return -EBUSY;
5626         }
5627         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5628         if (val != 1) {
5629                 BNX2X_ERR("PXP2 RD_INIT failed\n");
5630                 return -EBUSY;
5631         }
5632
5633         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5634         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5635
5636         bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5637
5638         /* clean the DMAE memory */
5639         bp->dmae_ready = 1;
5640         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5641
5642         bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5643         bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5644         bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5645         bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5646
5647         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5648         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5649         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5650         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5651
5652         bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5653         /* soft reset pulse */
5654         REG_WR(bp, QM_REG_SOFT_RESET, 1);
5655         REG_WR(bp, QM_REG_SOFT_RESET, 0);
5656
5657 #ifdef BCM_ISCSI
5658         bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5659 #endif
5660
5661         bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5662         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5663         if (!CHIP_REV_IS_SLOW(bp)) {
5664                 /* enable hw interrupt from doorbell Q */
5665                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5666         }
5667
5668         bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5669         bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5670         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5671         /* set NIC mode */
5672         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5673         if (CHIP_IS_E1H(bp))
5674                 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5675
5676         bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5677         bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5678         bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5679         bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5680
5681         bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5682         bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5683         bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5684         bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5685
5686         bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5687         bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5688         bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5689         bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5690
5691         /* sync semi rtc */
5692         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5693                0x80000000);
5694         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5695                0x80000000);
5696
5697         bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5698         bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5699         bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5700
5701         REG_WR(bp, SRC_REG_SOFT_RST, 1);
5702         for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5703                 REG_WR(bp, i, 0xc0cac01a);
5704                 /* TODO: replace with something meaningful */
5705         }
5706         bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5707         REG_WR(bp, SRC_REG_SOFT_RST, 0);
5708
5709         if (sizeof(union cdu_context) != 1024)
5710                 /* we currently assume that a context is 1024 bytes */
5711                 printk(KERN_ALERT PFX "please adjust the size of"
5712                        " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5713
5714         bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5715         val = (4 << 24) + (0 << 12) + 1024;
5716         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5717         if (CHIP_IS_E1(bp)) {
5718                 /* !!! fix pxp client crdit until excel update */
5719                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5720                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5721         }
5722
5723         bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5724         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5725         /* enable context validation interrupt from CFC */
5726         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5727
5728         /* set the thresholds to prevent CFC/CDU race */
5729         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5730
5731         bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5732         bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5733
5734         /* PXPCS COMMON comes here */
5735         bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5736         /* Reset PCIE errors for debug */
5737         REG_WR(bp, 0x2814, 0xffffffff);
5738         REG_WR(bp, 0x3820, 0xffffffff);
5739
5740         /* EMAC0 COMMON comes here */
5741         bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5742         /* EMAC1 COMMON comes here */
5743         bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5744         /* DBU COMMON comes here */
5745         bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5746         /* DBG COMMON comes here */
5747         bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5748
5749         bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5750         if (CHIP_IS_E1H(bp)) {
5751                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5752                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5753         }
5754
5755         if (CHIP_REV_IS_SLOW(bp))
5756                 msleep(200);
5757
5758         /* finish CFC init */
5759         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5760         if (val != 1) {
5761                 BNX2X_ERR("CFC LL_INIT failed\n");
5762                 return -EBUSY;
5763         }
5764         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5765         if (val != 1) {
5766                 BNX2X_ERR("CFC AC_INIT failed\n");
5767                 return -EBUSY;
5768         }
5769         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5770         if (val != 1) {
5771                 BNX2X_ERR("CFC CAM_INIT failed\n");
5772                 return -EBUSY;
5773         }
5774         REG_WR(bp, CFC_REG_DEBUG0, 0);
5775
5776         /* read NIG statistic
5777            to see if this is our first up since powerup */
5778         bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5779         val = *bnx2x_sp(bp, wb_data[0]);
5780
5781         /* do internal memory self test */
5782         if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5783                 BNX2X_ERR("internal mem self test failed\n");
5784                 return -EBUSY;
5785         }
5786
5787         switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
5788         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5789         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
5790         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5791                 bp->port.need_hw_lock = 1;
5792                 break;
5793
5794         default:
5795                 break;
5796         }
5797
5798         bnx2x_setup_fan_failure_detection(bp);
5799
5800         /* clear PXP2 attentions */
5801         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5802
5803         enable_blocks_attention(bp);
5804
5805         if (!BP_NOMCP(bp)) {
5806                 bnx2x_acquire_phy_lock(bp);
5807                 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5808                 bnx2x_release_phy_lock(bp);
5809         } else
5810                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5811
5812         return 0;
5813 }
5814
5815 static int bnx2x_init_port(struct bnx2x *bp)
5816 {
5817         int port = BP_PORT(bp);
5818         int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5819         u32 low, high;
5820         u32 val;
5821
5822         DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);
5823
5824         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5825
5826         /* Port PXP comes here */
5827         bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5828         /* Port PXP2 comes here */
5829         bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5830 #ifdef BCM_ISCSI
5831         /* Port0  1
5832          * Port1  385 */
5833         i++;
5834         wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5835         wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5836         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5837         REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5838
5839         /* Port0  2
5840          * Port1  386 */
5841         i++;
5842         wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5843         wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5844         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5845         REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5846
5847         /* Port0  3
5848          * Port1  387 */
5849         i++;
5850         wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5851         wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5852         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5853         REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5854 #endif
5855         /* Port CMs come here */
5856         bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5857
5858         /* Port QM comes here */
5859 #ifdef BCM_ISCSI
5860         REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5861         REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5862
5863         bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5864 #endif
5865         /* Port DQ comes here */
5866         bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5867
5868         bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5869         if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
5870                 /* no pause for emulation and FPGA */
5871                 low = 0;
5872                 high = 513;
5873         } else {
5874                 if (IS_E1HMF(bp))
5875                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5876                 else if (bp->dev->mtu > 4096) {
5877                         if (bp->flags & ONE_PORT_FLAG)
5878                                 low = 160;
5879                         else {
5880                                 val = bp->dev->mtu;
5881                                 /* (24*1024 + val*4)/256 */
5882                                 low = 96 + (val/64) + ((val % 64) ? 1 : 0);
5883                         }
5884                 } else
5885                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5886                 high = low + 56;        /* 14*1024/256 */
5887         }
5888         REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5889         REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5890
5891
5892         /* Port PRS comes here */
5893         bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5894         /* Port TSDM comes here */
5895         bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5896         /* Port CSDM comes here */
5897         bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5898         /* Port USDM comes here */
5899         bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5900         /* Port XSDM comes here */
5901         bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5902
5903         bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5904         bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5905         bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5906         bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5907
5908         /* Port UPB comes here */
5909         bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5910         /* Port XPB comes here */
5911         bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5912
5913         bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5914
5915         /* configure PBF to work without PAUSE mtu 9000 */
5916         REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5917
5918         /* update threshold */
5919         REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5920         /* update init credit */
5921         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5922
5923         /* probe changes */
5924         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5925         msleep(5);
5926         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5927
5928 #ifdef BCM_ISCSI
5929         /* tell the searcher where the T2 table is */
5930         REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5931
5932         wb_write[0] = U64_LO(bp->t2_mapping);
5933         wb_write[1] = U64_HI(bp->t2_mapping);
5934         REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5935         wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5936         wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5937         REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5938
5939         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5940         /* Port SRCH comes here */
5941 #endif
5942         /* Port CDU comes here */
5943         bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5944         /* Port CFC comes here */
5945         bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5946
5947         if (CHIP_IS_E1(bp)) {
5948                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5949                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5950         }
5951         bnx2x_init_block(bp, HC_BLOCK, init_stage);
5952
5953         bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5954         /* init aeu_mask_attn_func_0/1:
5955          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5956          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5957          *             bits 4-7 are used for "per vn group attention" */
5958         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
5959                (IS_E1HMF(bp) ? 0xF7 : 0x7));
5960
5961         /* Port PXPCS comes here */
5962         bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5963         /* Port EMAC0 comes here */
5964         bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5965         /* Port EMAC1 comes here */
5966         bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5967         /* Port DBU comes here */
5968         bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5969         /* Port DBG comes here */
5970         bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5971
5972         bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5973
5974         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5975
5976         if (CHIP_IS_E1H(bp)) {
5977                 /* 0x2 disable e1hov, 0x1 enable */
5978                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5979                        (IS_E1HMF(bp) ? 0x1 : 0x2));
5980
5981                 /* support pause requests from USDM, TSDM and BRB */
5982                 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 + port*4, 0x7);
5983
5984                 {
5985                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5986                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5987                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5988                 }
5989         }
5990
5991         /* Port MCP comes here */
5992         bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5993         /* Port DMAE comes here */
5994         bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5995
5996         switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
5997         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5998                 {
5999                 u32 swap_val, swap_override, aeu_gpio_mask, offset;
6000
6001                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6002                                MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
6003
6004                 /* The GPIO should be swapped if the swap register is
6005                    set and active */
6006                 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6007                 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6008
6009                 /* Select function upon port-swap configuration */
6010                 if (port == 0) {
6011                         offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
6012                         aeu_gpio_mask = (swap_val && swap_override) ?
6013                                 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
6014                                 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
6015                 } else {
6016                         offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
6017                         aeu_gpio_mask = (swap_val && swap_override) ?
6018                                 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
6019                                 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
6020                 }
6021                 val = REG_RD(bp, offset);
6022                 /* add GPIO3 to group */
6023                 val |= aeu_gpio_mask;
6024                 REG_WR(bp, offset, val);
6025                 }
6026                 break;
6027
6028         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6029                 /* add SPIO 5 to group 0 */
6030                 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6031                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6032                 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
6033                 break;
6034
6035         default:
6036                 break;
6037         }
6038
6039         bnx2x__link_reset(bp);
6040
6041         return 0;
6042 }
6043
6044 #define ILT_PER_FUNC            (768/2)
6045 #define FUNC_ILT_BASE(func)     (func * ILT_PER_FUNC)
6046 /* the phys address is shifted right 12 bits and has an added
6047    1=valid bit added to the 53rd bit
6048    then since this is a wide register(TM)
6049    we split it into two 32 bit writes
6050  */
6051 #define ONCHIP_ADDR1(x)         ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
6052 #define ONCHIP_ADDR2(x)         ((u32)((1 << 20) | ((u64)x >> 44)))
6053 #define PXP_ONE_ILT(x)          (((x) << 10) | x)
6054 #define PXP_ILT_RANGE(f, l)     (((l) << 10) | f)
6055
6056 #define CNIC_ILT_LINES          0
6057
6058 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6059 {
6060         int reg;
6061
6062         if (CHIP_IS_E1H(bp))
6063                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6064         else /* E1 */
6065                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6066
6067         bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6068 }
6069
6070 static int bnx2x_init_func(struct bnx2x *bp)
6071 {
6072         int port = BP_PORT(bp);
6073         int func = BP_FUNC(bp);
6074         u32 addr, val;
6075         int i;
6076
6077         DP(BNX2X_MSG_MCP, "starting func init  func %x\n", func);
6078
6079         /* set MSI reconfigure capability */
6080         addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6081         val = REG_RD(bp, addr);
6082         val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6083         REG_WR(bp, addr, val);
6084
6085         i = FUNC_ILT_BASE(func);
6086
6087         bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
6088         if (CHIP_IS_E1H(bp)) {
6089                 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
6090                 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
6091         } else /* E1 */
6092                 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
6093                        PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
6094
6095
6096         if (CHIP_IS_E1H(bp)) {
6097                 for (i = 0; i < 9; i++)
6098                         bnx2x_init_block(bp,
6099                                          cm_blocks[i], FUNC0_STAGE + func);
6100
6101                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6102                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
6103         }
6104
6105         /* HC init per function */
6106         if (CHIP_IS_E1H(bp)) {
6107                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6108
6109                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6110                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6111         }
6112         bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
6113
6114         /* Reset PCIE errors for debug */
6115         REG_WR(bp, 0x2114, 0xffffffff);
6116         REG_WR(bp, 0x2120, 0xffffffff);
6117
6118         return 0;
6119 }
6120
6121 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
6122 {
6123         int i, rc = 0;
6124
6125         DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
6126            BP_FUNC(bp), load_code);
6127
6128         bp->dmae_ready = 0;
6129         mutex_init(&bp->dmae_mutex);
6130         bnx2x_gunzip_init(bp);
6131
6132         switch (load_code) {
6133         case FW_MSG_CODE_DRV_LOAD_COMMON:
6134                 rc = bnx2x_init_common(bp);
6135                 if (rc)
6136                         goto init_hw_err;
6137                 /* no break */
6138
6139         case FW_MSG_CODE_DRV_LOAD_PORT:
6140                 bp->dmae_ready = 1;
6141                 rc = bnx2x_init_port(bp);
6142                 if (rc)
6143                         goto init_hw_err;
6144                 /* no break */
6145
6146         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6147                 bp->dmae_ready = 1;
6148                 rc = bnx2x_init_func(bp);
6149                 if (rc)
6150                         goto init_hw_err;
6151                 break;
6152
6153         default:
6154                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6155                 break;
6156         }
6157
6158         if (!BP_NOMCP(bp)) {
6159                 int func = BP_FUNC(bp);
6160
6161                 bp->fw_drv_pulse_wr_seq =
6162                                 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
6163                                  DRV_PULSE_SEQ_MASK);
6164                 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
6165                 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x  func_stx 0x%x\n",
6166                    bp->fw_drv_pulse_wr_seq, bp->func_stx);
6167         } else
6168                 bp->func_stx = 0;
6169
6170         /* this needs to be done before gunzip end */
6171         bnx2x_zero_def_sb(bp);
6172         for_each_queue(bp, i)
6173                 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
6174
6175 init_hw_err:
6176         bnx2x_gunzip_end(bp);
6177
6178         return rc;
6179 }
6180
6181 /* send the MCP a request, block until there is a reply */
6182 static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
6183 {
6184         int func = BP_FUNC(bp);
6185         u32 seq = ++bp->fw_seq;
6186         u32 rc = 0;
6187         u32 cnt = 1;
6188         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
6189
6190         SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
6191         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
6192
6193         do {
6194                 /* let the FW do it's magic ... */
6195                 msleep(delay);
6196
6197                 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
6198
6199                 /* Give the FW up to 2 second (200*10ms) */
6200         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
6201
6202         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
6203            cnt*delay, rc, seq);
6204
6205         /* is this a reply to our command? */
6206         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
6207                 rc &= FW_MSG_CODE_MASK;
6208
6209         } else {
6210                 /* FW BUG! */
6211                 BNX2X_ERR("FW failed to respond!\n");
6212                 bnx2x_fw_dump(bp);
6213                 rc = 0;
6214         }
6215
6216         return rc;
6217 }
6218
6219 static void bnx2x_free_mem(struct bnx2x *bp)
6220 {
6221
6222 #define BNX2X_PCI_FREE(x, y, size) \
6223         do { \
6224                 if (x) { \
6225                         pci_free_consistent(bp->pdev, size, x, y); \
6226                         x = NULL; \
6227                         y = 0; \
6228                 } \
6229         } while (0)
6230
6231 #define BNX2X_FREE(x) \
6232         do { \
6233                 if (x) { \
6234                         vfree(x); \
6235                         x = NULL; \
6236                 } \
6237         } while (0)
6238
6239         int i;
6240
6241         /* fastpath */
6242         /* Common */
6243         for_each_queue(bp, i) {
6244
6245                 /* status blocks */
6246                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
6247                                bnx2x_fp(bp, i, status_blk_mapping),
6248                                sizeof(struct host_status_block) +
6249                                sizeof(struct eth_tx_db_data));
6250         }
6251         /* Rx */
6252         for_each_rx_queue(bp, i) {
6253
6254                 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6255                 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
6256                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
6257                                bnx2x_fp(bp, i, rx_desc_mapping),
6258                                sizeof(struct eth_rx_bd) * NUM_RX_BD);
6259
6260                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
6261                                bnx2x_fp(bp, i, rx_comp_mapping),
6262                                sizeof(struct eth_fast_path_rx_cqe) *
6263                                NUM_RCQ_BD);
6264
6265                 /* SGE ring */
6266                 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
6267                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
6268                                bnx2x_fp(bp, i, rx_sge_mapping),
6269                                BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6270         }
6271         /* Tx */
6272         for_each_tx_queue(bp, i) {
6273
6274                 /* fastpath tx rings: tx_buf tx_desc */
6275                 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
6276                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
6277                                bnx2x_fp(bp, i, tx_desc_mapping),
6278                                sizeof(struct eth_tx_bd) * NUM_TX_BD);
6279         }
6280         /* end of fastpath */
6281
6282         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6283                        sizeof(struct host_def_status_block));
6284
6285         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6286                        sizeof(struct bnx2x_slowpath));
6287
6288 #ifdef BCM_ISCSI
6289         BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
6290         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
6291         BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
6292         BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
6293 #endif
6294         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6295
6296 #undef BNX2X_PCI_FREE
6297 #undef BNX2X_KFREE
6298 }
6299
6300 static int bnx2x_alloc_mem(struct bnx2x *bp)
6301 {
6302
6303 #define BNX2X_PCI_ALLOC(x, y, size) \
6304         do { \
6305                 x = pci_alloc_consistent(bp->pdev, size, y); \
6306                 if (x == NULL) \
6307                         goto alloc_mem_err; \
6308                 memset(x, 0, size); \
6309         } while (0)
6310
6311 #define BNX2X_ALLOC(x, size) \
6312         do { \
6313                 x = vmalloc(size); \
6314                 if (x == NULL) \
6315                         goto alloc_mem_err; \
6316                 memset(x, 0, size); \
6317         } while (0)
6318
6319         int i;
6320
6321         /* fastpath */
6322         /* Common */
6323         for_each_queue(bp, i) {
6324                 bnx2x_fp(bp, i, bp) = bp;
6325
6326                 /* status blocks */
6327                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
6328                                 &bnx2x_fp(bp, i, status_blk_mapping),
6329                                 sizeof(struct host_status_block) +
6330                                 sizeof(struct eth_tx_db_data));
6331         }
6332         /* Rx */
6333         for_each_rx_queue(bp, i) {
6334
6335                 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6336                 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6337                                 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6338                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6339                                 &bnx2x_fp(bp, i, rx_desc_mapping),
6340                                 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6341
6342                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6343                                 &bnx2x_fp(bp, i, rx_comp_mapping),
6344                                 sizeof(struct eth_fast_path_rx_cqe) *
6345                                 NUM_RCQ_BD);
6346
6347                 /* SGE ring */
6348                 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6349                                 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6350                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6351                                 &bnx2x_fp(bp, i, rx_sge_mapping),
6352                                 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6353         }
6354         /* Tx */
6355         for_each_tx_queue(bp, i) {
6356
6357                 bnx2x_fp(bp, i, hw_tx_prods) =
6358                                 (void *)(bnx2x_fp(bp, i, status_blk) + 1);
6359
6360                 bnx2x_fp(bp, i, tx_prods_mapping) =
6361                                 bnx2x_fp(bp, i, status_blk_mapping) +
6362                                 sizeof(struct host_status_block);
6363
6364                 /* fastpath tx rings: tx_buf tx_desc */
6365                 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6366                                 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6367                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6368                                 &bnx2x_fp(bp, i, tx_desc_mapping),
6369                                 sizeof(struct eth_tx_bd) * NUM_TX_BD);
6370         }
6371         /* end of fastpath */
6372
6373         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6374                         sizeof(struct host_def_status_block));
6375
6376         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6377                         sizeof(struct bnx2x_slowpath));
6378
6379 #ifdef BCM_ISCSI
6380         BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
6381
6382         /* Initialize T1 */
6383         for (i = 0; i < 64*1024; i += 64) {
6384                 *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
6385                 *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
6386         }
6387
6388         /* allocate searcher T2 table
6389            we allocate 1/4 of alloc num for T2
6390           (which is not entered into the ILT) */
6391         BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
6392
6393         /* Initialize T2 */
6394         for (i = 0; i < 16*1024; i += 64)
6395                 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
6396
6397         /* now fixup the last line in the block to point to the next block */
6398         *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
6399
6400         /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
6401         BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
6402
6403         /* QM queues (128*MAX_CONN) */
6404         BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
6405 #endif
6406
6407         /* Slow path ring */
6408         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6409
6410         return 0;
6411
6412 alloc_mem_err:
6413         bnx2x_free_mem(bp);
6414         return -ENOMEM;
6415
6416 #undef BNX2X_PCI_ALLOC
6417 #undef BNX2X_ALLOC
6418 }
6419
6420 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
6421 {
6422         int i;
6423
6424         for_each_tx_queue(bp, i) {
6425                 struct bnx2x_fastpath *fp = &bp->fp[i];
6426
6427                 u16 bd_cons = fp->tx_bd_cons;
6428                 u16 sw_prod = fp->tx_pkt_prod;
6429                 u16 sw_cons = fp->tx_pkt_cons;
6430
6431                 while (sw_cons != sw_prod) {
6432                         bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
6433                         sw_cons++;
6434                 }
6435         }
6436 }
6437
6438 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
6439 {
6440         int i, j;
6441
6442         for_each_rx_queue(bp, j) {
6443                 struct bnx2x_fastpath *fp = &bp->fp[j];
6444
6445                 for (i = 0; i < NUM_RX_BD; i++) {
6446                         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
6447                         struct sk_buff *skb = rx_buf->skb;
6448
6449                         if (skb == NULL)
6450                                 continue;
6451
6452                         pci_unmap_single(bp->pdev,
6453                                          pci_unmap_addr(rx_buf, mapping),
6454                                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
6455
6456                         rx_buf->skb = NULL;
6457                         dev_kfree_skb(skb);
6458                 }
6459                 if (!fp->disable_tpa)
6460                         bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
6461                                             ETH_MAX_AGGREGATION_QUEUES_E1 :
6462                                             ETH_MAX_AGGREGATION_QUEUES_E1H);
6463         }
6464 }
6465
6466 static void bnx2x_free_skbs(struct bnx2x *bp)
6467 {
6468         bnx2x_free_tx_skbs(bp);
6469         bnx2x_free_rx_skbs(bp);
6470 }
6471
6472 static void bnx2x_free_msix_irqs(struct bnx2x *bp)
6473 {
6474         int i, offset = 1;
6475
6476         free_irq(bp->msix_table[0].vector, bp->dev);
6477         DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
6478            bp->msix_table[0].vector);
6479
6480         for_each_queue(bp, i) {
6481                 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq  "
6482                    "state %x\n", i, bp->msix_table[i + offset].vector,
6483                    bnx2x_fp(bp, i, state));
6484
6485                 free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
6486         }
6487 }
6488
6489 static void bnx2x_free_irq(struct bnx2x *bp)
6490 {
6491         if (bp->flags & USING_MSIX_FLAG) {
6492                 bnx2x_free_msix_irqs(bp);
6493                 pci_disable_msix(bp->pdev);
6494                 bp->flags &= ~USING_MSIX_FLAG;
6495
6496         } else if (bp->flags & USING_MSI_FLAG) {
6497                 free_irq(bp->pdev->irq, bp->dev);
6498                 pci_disable_msi(bp->pdev);
6499                 bp->flags &= ~USING_MSI_FLAG;
6500
6501         } else
6502                 free_irq(bp->pdev->irq, bp->dev);
6503 }
6504
6505 static int bnx2x_enable_msix(struct bnx2x *bp)
6506 {
6507         int i, rc, offset = 1;
6508         int igu_vec = 0;
6509
6510         bp->msix_table[0].entry = igu_vec;
6511         DP(NETIF_MSG_IFUP, "msix_table[0].entry = %d (slowpath)\n", igu_vec);
6512
6513         for_each_queue(bp, i) {
6514                 igu_vec = BP_L_ID(bp) + offset + i;
6515                 bp->msix_table[i + offset].entry = igu_vec;
6516                 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
6517                    "(fastpath #%u)\n", i + offset, igu_vec, i);
6518         }
6519
6520         rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
6521                              BNX2X_NUM_QUEUES(bp) + offset);
6522         if (rc) {
6523                 DP(NETIF_MSG_IFUP, "MSI-X is not attainable  rc %d\n", rc);
6524                 return rc;
6525         }
6526
6527         bp->flags |= USING_MSIX_FLAG;
6528
6529         return 0;
6530 }
6531
6532 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
6533 {
6534         int i, rc, offset = 1;
6535
6536         rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
6537                          bp->dev->name, bp->dev);
6538         if (rc) {
6539                 BNX2X_ERR("request sp irq failed\n");
6540                 return -EBUSY;
6541         }
6542
6543         for_each_queue(bp, i) {
6544                 struct bnx2x_fastpath *fp = &bp->fp[i];
6545
6546                 sprintf(fp->name, "%s.fp%d", bp->dev->name, i);
6547                 rc = request_irq(bp->msix_table[i + offset].vector,
6548                                  bnx2x_msix_fp_int, 0, fp->name, fp);
6549                 if (rc) {
6550                         BNX2X_ERR("request fp #%d irq failed  rc %d\n", i, rc);
6551                         bnx2x_free_msix_irqs(bp);
6552                         return -EBUSY;
6553                 }
6554
6555                 fp->state = BNX2X_FP_STATE_IRQ;
6556         }
6557
6558         i = BNX2X_NUM_QUEUES(bp);
6559         if (is_multi(bp))
6560                 printk(KERN_INFO PFX
6561                        "%s: using MSI-X  IRQs: sp %d  fp %d - %d\n",
6562                        bp->dev->name, bp->msix_table[0].vector,
6563                        bp->msix_table[offset].vector,
6564                        bp->msix_table[offset + i - 1].vector);
6565         else
6566                 printk(KERN_INFO PFX "%s: using MSI-X  IRQs: sp %d  fp %d\n",
6567                        bp->dev->name, bp->msix_table[0].vector,
6568                        bp->msix_table[offset + i - 1].vector);
6569
6570         return 0;
6571 }
6572
6573 static int bnx2x_enable_msi(struct bnx2x *bp)
6574 {
6575         int rc;
6576
6577         rc = pci_enable_msi(bp->pdev);
6578         if (rc) {
6579                 DP(NETIF_MSG_IFUP, "MSI is not attainable\n");
6580                 return -1;
6581         }
6582         bp->flags |= USING_MSI_FLAG;
6583
6584         return 0;
6585 }
6586
6587 static int bnx2x_req_irq(struct bnx2x *bp)
6588 {
6589         unsigned long flags;
6590         int rc;
6591
6592         if (bp->flags & USING_MSI_FLAG)
6593                 flags = 0;
6594         else
6595                 flags = IRQF_SHARED;
6596
6597         rc = request_irq(bp->pdev->irq, bnx2x_interrupt, flags,
6598                          bp->dev->name, bp->dev);
6599         if (!rc)
6600                 bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
6601
6602         return rc;
6603 }
6604
6605 static void bnx2x_napi_enable(struct bnx2x *bp)
6606 {
6607         int i;
6608
6609         for_each_rx_queue(bp, i)
6610                 napi_enable(&bnx2x_fp(bp, i, napi));
6611 }
6612
6613 static void bnx2x_napi_disable(struct bnx2x *bp)
6614 {
6615         int i;
6616
6617         for_each_rx_queue(bp, i)
6618                 napi_disable(&bnx2x_fp(bp, i, napi));
6619 }
6620
6621 static void bnx2x_netif_start(struct bnx2x *bp)
6622 {
6623         if (atomic_dec_and_test(&bp->intr_sem)) {
6624                 if (netif_running(bp->dev)) {
6625                         bnx2x_napi_enable(bp);
6626                         bnx2x_int_enable(bp);
6627                         if (bp->state == BNX2X_STATE_OPEN)
6628                                 netif_tx_wake_all_queues(bp->dev);
6629                 }
6630         }
6631 }
6632
6633 static void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
6634 {
6635         bnx2x_int_disable_sync(bp, disable_hw);
6636         bnx2x_napi_disable(bp);
6637         netif_tx_disable(bp->dev);
6638         bp->dev->trans_start = jiffies; /* prevent tx timeout */
6639 }
6640
6641 /*
6642  * Init service functions
6643  */
6644
6645 static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
6646 {
6647         struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6648         int port = BP_PORT(bp);
6649
6650         /* CAM allocation
6651          * unicasts 0-31:port0 32-63:port1
6652          * multicast 64-127:port0 128-191:port1
6653          */
6654         config->hdr.length = 2;
6655         config->hdr.offset = port ? 32 : 0;
6656         config->hdr.client_id = bp->fp->cl_id;
6657         config->hdr.reserved1 = 0;
6658
6659         /* primary MAC */
6660         config->config_table[0].cam_entry.msb_mac_addr =
6661                                         swab16(*(u16 *)&bp->dev->dev_addr[0]);
6662         config->config_table[0].cam_entry.middle_mac_addr =
6663                                         swab16(*(u16 *)&bp->dev->dev_addr[2]);
6664         config->config_table[0].cam_entry.lsb_mac_addr =
6665                                         swab16(*(u16 *)&bp->dev->dev_addr[4]);
6666         config->config_table[0].cam_entry.flags = cpu_to_le16(port);
6667         if (set)
6668                 config->config_table[0].target_table_entry.flags = 0;
6669         else
6670                 CAM_INVALIDATE(config->config_table[0]);
6671         config->config_table[0].target_table_entry.client_id = 0;
6672         config->config_table[0].target_table_entry.vlan_id = 0;
6673
6674         DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
6675            (set ? "setting" : "clearing"),
6676            config->config_table[0].cam_entry.msb_mac_addr,
6677            config->config_table[0].cam_entry.middle_mac_addr,
6678            config->config_table[0].cam_entry.lsb_mac_addr);
6679
6680         /* broadcast */
6681         config->config_table[1].cam_entry.msb_mac_addr = cpu_to_le16(0xffff);
6682         config->config_table[1].cam_entry.middle_mac_addr = cpu_to_le16(0xffff);
6683         config->config_table[1].cam_entry.lsb_mac_addr = cpu_to_le16(0xffff);
6684         config->config_table[1].cam_entry.flags = cpu_to_le16(port);
6685         if (set)
6686                 config->config_table[1].target_table_entry.flags =
6687                                 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
6688         else
6689                 CAM_INVALIDATE(config->config_table[1]);
6690         config->config_table[1].target_table_entry.client_id = 0;
6691         config->config_table[1].target_table_entry.vlan_id = 0;
6692
6693         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6694                       U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6695                       U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6696 }
6697
6698 static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
6699 {
6700         struct mac_configuration_cmd_e1h *config =
6701                 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
6702
6703         if (set && (bp->state != BNX2X_STATE_OPEN)) {
6704                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
6705                 return;
6706         }
6707
6708         /* CAM allocation for E1H
6709          * unicasts: by func number
6710          * multicast: 20+FUNC*20, 20 each
6711          */
6712         config->hdr.length = 1;
6713         config->hdr.offset = BP_FUNC(bp);
6714         config->hdr.client_id = bp->fp->cl_id;
6715         config->hdr.reserved1 = 0;
6716
6717         /* primary MAC */
6718         config->config_table[0].msb_mac_addr =
6719                                         swab16(*(u16 *)&bp->dev->dev_addr[0]);
6720         config->config_table[0].middle_mac_addr =
6721                                         swab16(*(u16 *)&bp->dev->dev_addr[2]);
6722         config->config_table[0].lsb_mac_addr =
6723                                         swab16(*(u16 *)&bp->dev->dev_addr[4]);
6724         config->config_table[0].client_id = BP_L_ID(bp);
6725         config->config_table[0].vlan_id = 0;
6726         config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
6727         if (set)
6728                 config->config_table[0].flags = BP_PORT(bp);
6729         else
6730                 config->config_table[0].flags =
6731                                 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
6732
6733         DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)  E1HOV %d  CLID %d\n",
6734            (set ? "setting" : "clearing"),
6735            config->config_table[0].msb_mac_addr,
6736            config->config_table[0].middle_mac_addr,
6737            config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));
6738
6739         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6740                       U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6741                       U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6742 }
6743
6744 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6745                              int *state_p, int poll)
6746 {
6747         /* can take a while if any port is running */
6748         int cnt = 5000;
6749
6750         DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6751            poll ? "polling" : "waiting", state, idx);
6752
6753         might_sleep();
6754         while (cnt--) {
6755                 if (poll) {
6756                         bnx2x_rx_int(bp->fp, 10);
6757                         /* if index is different from 0
6758                          * the reply for some commands will
6759                          * be on the non default queue
6760                          */
6761                         if (idx)
6762                                 bnx2x_rx_int(&bp->fp[idx], 10);
6763                 }
6764
6765                 mb(); /* state is changed by bnx2x_sp_event() */
6766                 if (*state_p == state) {
6767 #ifdef BNX2X_STOP_ON_ERROR
6768                         DP(NETIF_MSG_IFUP, "exit  (cnt %d)\n", 5000 - cnt);
6769 #endif
6770                         return 0;
6771                 }
6772
6773                 msleep(1);
6774         }
6775
6776         /* timeout! */
6777         BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6778                   poll ? "polling" : "waiting", state, idx);
6779 #ifdef BNX2X_STOP_ON_ERROR
6780         bnx2x_panic();
6781 #endif
6782
6783         return -EBUSY;
6784 }
6785
6786 static int bnx2x_setup_leading(struct bnx2x *bp)
6787 {
6788         int rc;
6789
6790         /* reset IGU state */
6791         bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6792
6793         /* SETUP ramrod */
6794         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
6795
6796         /* Wait for completion */
6797         rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
6798
6799         return rc;
6800 }
6801
6802 static int bnx2x_setup_multi(struct bnx2x *bp, int index)
6803 {
6804         struct bnx2x_fastpath *fp = &bp->fp[index];
6805
6806         /* reset IGU state */
6807         bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6808
6809         /* SETUP ramrod */
6810         fp->state = BNX2X_FP_STATE_OPENING;
6811         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0,
6812                       fp->cl_id, 0);
6813
6814         /* Wait for completion */
6815         return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
6816                                  &(fp->state), 0);
6817 }
6818
6819 static int bnx2x_poll(struct napi_struct *napi, int budget);
6820
6821 static void bnx2x_set_int_mode(struct bnx2x *bp)
6822 {
6823         int num_queues;
6824
6825         switch (int_mode) {
6826         case INT_MODE_INTx:
6827         case INT_MODE_MSI:
6828                 num_queues = 1;
6829                 bp->num_rx_queues = num_queues;
6830                 bp->num_tx_queues = num_queues;
6831                 DP(NETIF_MSG_IFUP,
6832                    "set number of queues to %d\n", num_queues);
6833                 break;
6834
6835         case INT_MODE_MSIX:
6836         default:
6837                 if (bp->multi_mode == ETH_RSS_MODE_REGULAR)
6838                         num_queues = min_t(u32, num_online_cpus(),
6839                                            BNX2X_MAX_QUEUES(bp));
6840                 else
6841                         num_queues = 1;
6842                 bp->num_rx_queues = num_queues;
6843                 bp->num_tx_queues = num_queues;
6844                 DP(NETIF_MSG_IFUP, "set number of rx queues to %d"
6845                    "  number of tx queues to %d\n",
6846                    bp->num_rx_queues, bp->num_tx_queues);
6847                 /* if we can't use MSI-X we only need one fp,
6848                  * so try to enable MSI-X with the requested number of fp's
6849                  * and fallback to MSI or legacy INTx with one fp
6850                  */
6851                 if (bnx2x_enable_msix(bp)) {
6852                         /* failed to enable MSI-X */
6853                         num_queues = 1;
6854                         bp->num_rx_queues = num_queues;
6855                         bp->num_tx_queues = num_queues;
6856                         if (bp->multi_mode)
6857                                 BNX2X_ERR("Multi requested but failed to "
6858                                           "enable MSI-X  set number of "
6859                                           "queues to %d\n", num_queues);
6860                 }
6861                 break;
6862         }
6863         bp->dev->real_num_tx_queues = bp->num_tx_queues;
6864 }
6865
6866 static void bnx2x_set_rx_mode(struct net_device *dev);
6867
6868 /* must be called with rtnl_lock */
6869 static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6870 {
6871         u32 load_code;
6872         int i, rc = 0;
6873 #ifdef BNX2X_STOP_ON_ERROR
6874         DP(NETIF_MSG_IFUP, "enter  load_mode %d\n", load_mode);
6875         if (unlikely(bp->panic))
6876                 return -EPERM;
6877 #endif
6878
6879         bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
6880
6881         bnx2x_set_int_mode(bp);
6882
6883         if (bnx2x_alloc_mem(bp))
6884                 return -ENOMEM;
6885
6886         for_each_rx_queue(bp, i)
6887                 bnx2x_fp(bp, i, disable_tpa) =
6888                                         ((bp->flags & TPA_ENABLE_FLAG) == 0);
6889
6890         for_each_rx_queue(bp, i)
6891                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
6892                                bnx2x_poll, 128);
6893
6894 #ifdef BNX2X_STOP_ON_ERROR
6895         for_each_rx_queue(bp, i) {
6896                 struct bnx2x_fastpath *fp = &bp->fp[i];
6897
6898                 fp->poll_no_work = 0;
6899                 fp->poll_calls = 0;
6900                 fp->poll_max_calls = 0;
6901                 fp->poll_complete = 0;
6902                 fp->poll_exit = 0;
6903         }
6904 #endif
6905         bnx2x_napi_enable(bp);
6906
6907         if (bp->flags & USING_MSIX_FLAG) {
6908                 rc = bnx2x_req_msix_irqs(bp);
6909                 if (rc) {
6910                         pci_disable_msix(bp->pdev);
6911                         goto load_error1;
6912                 }
6913         } else {
6914                 if ((rc != -ENOMEM) && (int_mode != INT_MODE_INTx))
6915                         bnx2x_enable_msi(bp);
6916                 bnx2x_ack_int(bp);
6917                 rc = bnx2x_req_irq(bp);
6918                 if (rc) {
6919                         BNX2X_ERR("IRQ request failed  rc %d, aborting\n", rc);
6920                         if (bp->flags & USING_MSI_FLAG)
6921                                 pci_disable_msi(bp->pdev);
6922                         goto load_error1;
6923                 }
6924                 if (bp->flags & USING_MSI_FLAG) {
6925                         bp->dev->irq = bp->pdev->irq;
6926                         printk(KERN_INFO PFX "%s: using MSI  IRQ %d\n",
6927                                bp->dev->name, bp->pdev->irq);
6928                 }
6929         }
6930
6931         /* Send LOAD_REQUEST command to MCP
6932            Returns the type of LOAD command:
6933            if it is the first port to be initialized
6934            common blocks should be initialized, otherwise - not
6935         */
6936         if (!BP_NOMCP(bp)) {
6937                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
6938                 if (!load_code) {
6939                         BNX2X_ERR("MCP response failure, aborting\n");
6940                         rc = -EBUSY;
6941                         goto load_error2;
6942                 }
6943                 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) {
6944                         rc = -EBUSY; /* other port in diagnostic mode */
6945                         goto load_error2;
6946                 }
6947
6948         } else {
6949                 int port = BP_PORT(bp);
6950
6951                 DP(NETIF_MSG_IFUP, "NO MCP - load counts      %d, %d, %d\n",
6952                    load_count[0], load_count[1], load_count[2]);
6953                 load_count[0]++;
6954                 load_count[1 + port]++;
6955                 DP(NETIF_MSG_IFUP, "NO MCP - new load counts  %d, %d, %d\n",
6956                    load_count[0], load_count[1], load_count[2]);
6957                 if (load_count[0] == 1)
6958                         load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
6959                 else if (load_count[1 + port] == 1)
6960                         load_code = FW_MSG_CODE_DRV_LOAD_PORT;
6961                 else
6962                         load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
6963         }
6964
6965         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6966             (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
6967                 bp->port.pmf = 1;
6968         else
6969                 bp->port.pmf = 0;
6970         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
6971
6972         /* Initialize HW */
6973         rc = bnx2x_init_hw(bp, load_code);
6974         if (rc) {
6975                 BNX2X_ERR("HW init failed, aborting\n");
6976                 goto load_error2;
6977         }
6978
6979         /* Setup NIC internals and enable interrupts */
6980         bnx2x_nic_init(bp, load_code);
6981
6982         /* Send LOAD_DONE command to MCP */
6983         if (!BP_NOMCP(bp)) {
6984                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
6985                 if (!load_code) {
6986                         BNX2X_ERR("MCP response failure, aborting\n");
6987                         rc = -EBUSY;
6988                         goto load_error3;
6989                 }
6990         }
6991
6992         bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
6993
6994         rc = bnx2x_setup_leading(bp);
6995         if (rc) {
6996                 BNX2X_ERR("Setup leading failed!\n");
6997                 goto load_error3;
6998         }
6999
7000         if (CHIP_IS_E1H(bp))
7001                 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
7002                         DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
7003                         bp->state = BNX2X_STATE_DISABLED;
7004                 }
7005
7006         if (bp->state == BNX2X_STATE_OPEN)
7007                 for_each_nondefault_queue(bp, i) {
7008                         rc = bnx2x_setup_multi(bp, i);
7009                         if (rc)
7010                                 goto load_error3;
7011                 }
7012
7013         if (CHIP_IS_E1(bp))
7014                 bnx2x_set_mac_addr_e1(bp, 1);
7015         else
7016                 bnx2x_set_mac_addr_e1h(bp, 1);
7017
7018         if (bp->port.pmf)
7019                 bnx2x_initial_phy_init(bp, load_mode);
7020
7021         /* Start fast path */
7022         switch (load_mode) {
7023         case LOAD_NORMAL:
7024                 /* Tx queue should be only reenabled */
7025                 netif_tx_wake_all_queues(bp->dev);
7026                 /* Initialize the receive filter. */
7027                 bnx2x_set_rx_mode(bp->dev);
7028                 break;
7029
7030         case LOAD_OPEN:
7031                 netif_tx_start_all_queues(bp->dev);
7032                 /* Initialize the receive filter. */
7033                 bnx2x_set_rx_mode(bp->dev);
7034                 break;
7035
7036         case LOAD_DIAG:
7037                 /* Initialize the receive filter. */
7038                 bnx2x_set_rx_mode(bp->dev);
7039                 bp->state = BNX2X_STATE_DIAG;
7040                 break;
7041
7042         default:
7043                 break;
7044         }
7045
7046         if (!bp->port.pmf)
7047                 bnx2x__link_status_update(bp);
7048
7049         /* start the timer */
7050         mod_timer(&bp->timer, jiffies + bp->current_interval);
7051
7052
7053         return 0;
7054
7055 load_error3:
7056         bnx2x_int_disable_sync(bp, 1);
7057         if (!BP_NOMCP(bp)) {
7058                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
7059                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
7060         }
7061         bp->port.pmf = 0;
7062         /* Free SKBs, SGEs, TPA pool and driver internals */
7063         bnx2x_free_skbs(bp);
7064         for_each_rx_queue(bp, i)
7065                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
7066 load_error2:
7067         /* Release IRQs */
7068         bnx2x_free_irq(bp);
7069 load_error1:
7070         bnx2x_napi_disable(bp);
7071         for_each_rx_queue(bp, i)
7072                 netif_napi_del(&bnx2x_fp(bp, i, napi));
7073         bnx2x_free_mem(bp);
7074
7075         return rc;
7076 }
7077
7078 static int bnx2x_stop_multi(struct bnx2x *bp, int index)
7079 {
7080         struct bnx2x_fastpath *fp = &bp->fp[index];
7081         int rc;
7082
7083         /* halt the connection */
7084         fp->state = BNX2X_FP_STATE_HALTING;
7085         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0);
7086
7087         /* Wait for completion */
7088         rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
7089                                &(fp->state), 1);
7090         if (rc) /* timeout */
7091                 return rc;
7092
7093         /* delete cfc entry */
7094         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
7095
7096         /* Wait for completion */
7097         rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
7098                                &(fp->state), 1);
7099         return rc;
7100 }
7101
7102 static int bnx2x_stop_leading(struct bnx2x *bp)
7103 {
7104         __le16 dsb_sp_prod_idx;
7105         /* if the other port is handling traffic,
7106            this can take a lot of time */
7107         int cnt = 500;
7108         int rc;
7109
7110         might_sleep();
7111
7112         /* Send HALT ramrod */
7113         bp->fp[0].state = BNX2X_FP_STATE_HALTING;
7114         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, bp->fp->cl_id, 0);
7115
7116         /* Wait for completion */
7117         rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
7118                                &(bp->fp[0].state), 1);
7119         if (rc) /* timeout */
7120                 return rc;
7121
7122         dsb_sp_prod_idx = *bp->dsb_sp_prod;
7123
7124         /* Send PORT_DELETE ramrod */
7125         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
7126
7127         /* Wait for completion to arrive on default status block
7128            we are going to reset the chip anyway
7129            so there is not much to do if this times out
7130          */
7131         while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
7132                 if (!cnt) {
7133                         DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
7134                            "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
7135                            *bp->dsb_sp_prod, dsb_sp_prod_idx);
7136 #ifdef BNX2X_STOP_ON_ERROR
7137                         bnx2x_panic();
7138 #endif
7139                         rc = -EBUSY;
7140                         break;
7141                 }
7142                 cnt--;
7143                 msleep(1);
7144                 rmb(); /* Refresh the dsb_sp_prod */
7145         }
7146         bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
7147         bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
7148
7149         return rc;
7150 }
7151
7152 static void bnx2x_reset_func(struct bnx2x *bp)
7153 {
7154         int port = BP_PORT(bp);
7155         int func = BP_FUNC(bp);
7156         int base, i;
7157
7158         /* Configure IGU */
7159         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7160         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7161
7162         /* Clear ILT */
7163         base = FUNC_ILT_BASE(func);
7164         for (i = base; i < base + ILT_PER_FUNC; i++)
7165                 bnx2x_ilt_wr(bp, i, 0);
7166 }
7167
7168 static void bnx2x_reset_port(struct bnx2x *bp)
7169 {
7170         int port = BP_PORT(bp);
7171         u32 val;
7172
7173         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7174
7175         /* Do not rcv packets to BRB */
7176         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7177         /* Do not direct rcv packets that are not for MCP to the BRB */
7178         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7179                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7180
7181         /* Configure AEU */
7182         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7183
7184         msleep(100);
7185         /* Check for BRB port occupancy */
7186         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7187         if (val)
7188                 DP(NETIF_MSG_IFDOWN,
7189                    "BRB1 is not empty  %d blocks are occupied\n", val);
7190
7191         /* TODO: Close Doorbell port? */
7192 }
7193
7194 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7195 {
7196         DP(BNX2X_MSG_MCP, "function %d  reset_code %x\n",
7197            BP_FUNC(bp), reset_code);
7198
7199         switch (reset_code) {
7200         case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7201                 bnx2x_reset_port(bp);
7202                 bnx2x_reset_func(bp);
7203                 bnx2x_reset_common(bp);
7204                 break;
7205
7206         case FW_MSG_CODE_DRV_UNLOAD_PORT:
7207                 bnx2x_reset_port(bp);
7208                 bnx2x_reset_func(bp);
7209                 break;
7210
7211         case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7212                 bnx2x_reset_func(bp);
7213                 break;
7214
7215         default:
7216                 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7217                 break;
7218         }
7219 }
7220
7221 /* must be called with rtnl_lock */
7222 static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
7223 {
7224         int port = BP_PORT(bp);
7225         u32 reset_code = 0;
7226         int i, cnt, rc;
7227
7228         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
7229
7230         bp->rx_mode = BNX2X_RX_MODE_NONE;
7231         bnx2x_set_storm_rx_mode(bp);
7232
7233         bnx2x_netif_stop(bp, 1);
7234
7235         del_timer_sync(&bp->timer);
7236         SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb,
7237                  (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
7238         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7239
7240         /* Release IRQs */
7241         bnx2x_free_irq(bp);
7242
7243         /* Wait until tx fastpath tasks complete */
7244         for_each_tx_queue(bp, i) {
7245                 struct bnx2x_fastpath *fp = &bp->fp[i];
7246
7247                 cnt = 1000;
7248                 while (bnx2x_has_tx_work_unload(fp)) {
7249
7250                         bnx2x_tx_int(fp);
7251                         if (!cnt) {
7252                                 BNX2X_ERR("timeout waiting for queue[%d]\n",
7253                                           i);
7254 #ifdef BNX2X_STOP_ON_ERROR
7255                                 bnx2x_panic();
7256                                 return -EBUSY;
7257 #else
7258                                 break;
7259 #endif
7260                         }
7261                         cnt--;
7262                         msleep(1);
7263                 }
7264         }
7265         /* Give HW time to discard old tx messages */
7266         msleep(1);
7267
7268         if (CHIP_IS_E1(bp)) {
7269                 struct mac_configuration_cmd *config =
7270                                                 bnx2x_sp(bp, mcast_config);
7271
7272                 bnx2x_set_mac_addr_e1(bp, 0);
7273
7274                 for (i = 0; i < config->hdr.length; i++)
7275                         CAM_INVALIDATE(config->config_table[i]);
7276
7277                 config->hdr.length = i;
7278                 if (CHIP_REV_IS_SLOW(bp))
7279                         config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
7280                 else
7281                         config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
7282                 config->hdr.client_id = bp->fp->cl_id;
7283                 config->hdr.reserved1 = 0;
7284
7285                 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
7286                               U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
7287                               U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
7288
7289         } else { /* E1H */
7290                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7291
7292                 bnx2x_set_mac_addr_e1h(bp, 0);
7293
7294                 for (i = 0; i < MC_HASH_SIZE; i++)
7295                         REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
7296         }
7297
7298         if (unload_mode == UNLOAD_NORMAL)
7299                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7300
7301         else if (bp->flags & NO_WOL_FLAG) {
7302                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7303                 if (CHIP_IS_E1H(bp))
7304                         REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
7305
7306         } else if (bp->wol) {
7307                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7308                 u8 *mac_addr = bp->dev->dev_addr;
7309                 u32 val;
7310                 /* The mac address is written to entries 1-4 to
7311                    preserve entry 0 which is used by the PMF */
7312                 u8 entry = (BP_E1HVN(bp) + 1)*8;
7313
7314                 val = (mac_addr[0] << 8) | mac_addr[1];
7315                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7316
7317                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7318                       (mac_addr[4] << 8) | mac_addr[5];
7319                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7320
7321                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7322
7323         } else
7324                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7325
7326         /* Close multi and leading connections
7327            Completions for ramrods are collected in a synchronous way */
7328         for_each_nondefault_queue(bp, i)
7329                 if (bnx2x_stop_multi(bp, i))
7330                         goto unload_error;
7331
7332         rc = bnx2x_stop_leading(bp);
7333         if (rc) {
7334                 BNX2X_ERR("Stop leading failed!\n");
7335 #ifdef BNX2X_STOP_ON_ERROR
7336                 return -EBUSY;
7337 #else
7338                 goto unload_error;
7339 #endif
7340         }
7341
7342 unload_error:
7343         if (!BP_NOMCP(bp))
7344                 reset_code = bnx2x_fw_command(bp, reset_code);
7345         else {
7346                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts      %d, %d, %d\n",
7347                    load_count[0], load_count[1], load_count[2]);
7348                 load_count[0]--;
7349                 load_count[1 + port]--;
7350                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts  %d, %d, %d\n",
7351                    load_count[0], load_count[1], load_count[2]);
7352                 if (load_count[0] == 0)
7353                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7354                 else if (load_count[1 + port] == 0)
7355                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7356                 else
7357                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7358         }
7359
7360         if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7361             (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7362                 bnx2x__link_reset(bp);
7363
7364         /* Reset the chip */
7365         bnx2x_reset_chip(bp, reset_code);
7366
7367         /* Report UNLOAD_DONE to MCP */
7368         if (!BP_NOMCP(bp))
7369                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
7370
7371         bp->port.pmf = 0;
7372
7373         /* Free SKBs, SGEs, TPA pool and driver internals */
7374         bnx2x_free_skbs(bp);
7375         for_each_rx_queue(bp, i)
7376                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
7377         for_each_rx_queue(bp, i)
7378                 netif_napi_del(&bnx2x_fp(bp, i, napi));
7379         bnx2x_free_mem(bp);
7380
7381         bp->state = BNX2X_STATE_CLOSED;
7382
7383         netif_carrier_off(bp->dev);
7384
7385         return 0;
7386 }
7387
7388 static void bnx2x_reset_task(struct work_struct *work)
7389 {
7390         struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
7391
7392 #ifdef BNX2X_STOP_ON_ERROR
7393         BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7394                   " so reset not done to allow debug dump,\n"
7395          KERN_ERR " you will need to reboot when done\n");
7396         return;
7397 #endif
7398
7399         rtnl_lock();
7400
7401         if (!netif_running(bp->dev))
7402                 goto reset_task_exit;
7403
7404         bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7405         bnx2x_nic_load(bp, LOAD_NORMAL);
7406
7407 reset_task_exit:
7408         rtnl_unlock();
7409 }
7410
7411 /* end of nic load/unload */
7412
7413 /* ethtool_ops */
7414
7415 /*
7416  * Init service functions
7417  */
7418
7419 static inline u32 bnx2x_get_pretend_reg(struct bnx2x *bp, int func)
7420 {
7421         switch (func) {
7422         case 0: return PXP2_REG_PGL_PRETEND_FUNC_F0;
7423         case 1: return PXP2_REG_PGL_PRETEND_FUNC_F1;
7424         case 2: return PXP2_REG_PGL_PRETEND_FUNC_F2;
7425         case 3: return PXP2_REG_PGL_PRETEND_FUNC_F3;
7426         case 4: return PXP2_REG_PGL_PRETEND_FUNC_F4;
7427         case 5: return PXP2_REG_PGL_PRETEND_FUNC_F5;
7428         case 6: return PXP2_REG_PGL_PRETEND_FUNC_F6;
7429         case 7: return PXP2_REG_PGL_PRETEND_FUNC_F7;
7430         default:
7431                 BNX2X_ERR("Unsupported function index: %d\n", func);
7432                 return (u32)(-1);
7433         }
7434 }
7435
7436 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func)
7437 {
7438         u32 reg = bnx2x_get_pretend_reg(bp, orig_func), new_val;
7439
7440         /* Flush all outstanding writes */
7441         mmiowb();
7442
7443         /* Pretend to be function 0 */
7444         REG_WR(bp, reg, 0);
7445         /* Flush the GRC transaction (in the chip) */
7446         new_val = REG_RD(bp, reg);
7447         if (new_val != 0) {
7448                 BNX2X_ERR("Hmmm... Pretend register wasn't updated: (0,%d)!\n",
7449                           new_val);
7450                 BUG();
7451         }
7452
7453         /* From now we are in the "like-E1" mode */
7454         bnx2x_int_disable(bp);
7455
7456         /* Flush all outstanding writes */
7457         mmiowb();
7458
7459         /* Restore the original funtion settings */
7460         REG_WR(bp, reg, orig_func);
7461         new_val = REG_RD(bp, reg);
7462         if (new_val != orig_func) {
7463                 BNX2X_ERR("Hmmm... Pretend register wasn't updated: (%d,%d)!\n",
7464                           orig_func, new_val);
7465                 BUG();
7466         }
7467 }
7468
7469 static inline void bnx2x_undi_int_disable(struct bnx2x *bp, int func)
7470 {
7471         if (CHIP_IS_E1H(bp))
7472                 bnx2x_undi_int_disable_e1h(bp, func);
7473         else
7474                 bnx2x_int_disable(bp);
7475 }
7476
7477 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7478 {
7479         u32 val;
7480
7481         /* Check if there is any driver already loaded */
7482         val = REG_RD(bp, MISC_REG_UNPREPARED);
7483         if (val == 0x1) {
7484                 /* Check if it is the UNDI driver
7485                  * UNDI driver initializes CID offset for normal bell to 0x7
7486                  */
7487                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7488                 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7489                 if (val == 0x7) {
7490                         u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7491                         /* save our func */
7492                         int func = BP_FUNC(bp);
7493                         u32 swap_en;
7494                         u32 swap_val;
7495
7496                         /* clear the UNDI indication */
7497                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7498
7499                         BNX2X_DEV_INFO("UNDI is active! reset device\n");
7500
7501                         /* try unload UNDI on port 0 */
7502                         bp->func = 0;
7503                         bp->fw_seq =
7504                                (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
7505                                 DRV_MSG_SEQ_NUMBER_MASK);
7506                         reset_code = bnx2x_fw_command(bp, reset_code);
7507
7508                         /* if UNDI is loaded on the other port */
7509                         if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7510
7511                                 /* send "DONE" for previous unload */
7512                                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
7513
7514                                 /* unload UNDI on port 1 */
7515                                 bp->func = 1;
7516                                 bp->fw_seq =
7517                                (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
7518                                         DRV_MSG_SEQ_NUMBER_MASK);
7519                                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7520
7521                                 bnx2x_fw_command(bp, reset_code);
7522                         }
7523
7524                         /* now it's safe to release the lock */
7525                         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7526
7527                         bnx2x_undi_int_disable(bp, func);
7528
7529                         /* close input traffic and wait for it */
7530                         /* Do not rcv packets to BRB */
7531                         REG_WR(bp,
7532                               (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7533                                              NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7534                         /* Do not direct rcv packets that are not for MCP to
7535                          * the BRB */
7536                         REG_WR(bp,
7537                                (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7538                                               NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7539                         /* clear AEU */
7540                         REG_WR(bp,
7541                              (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7542                                             MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7543                         msleep(10);
7544
7545                         /* save NIG port swap info */
7546                         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7547                         swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7548                         /* reset device */
7549                         REG_WR(bp,
7550                                GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7551                                0xd3ffffff);
7552                         REG_WR(bp,
7553                                GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7554                                0x1403);
7555                         /* take the NIG out of reset and restore swap values */
7556                         REG_WR(bp,
7557                                GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7558                                MISC_REGISTERS_RESET_REG_1_RST_NIG);
7559                         REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7560                         REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7561
7562                         /* send unload done to the MCP */
7563                         bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
7564
7565                         /* restore our func and fw_seq */
7566                         bp->func = func;
7567                         bp->fw_seq =
7568                                (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
7569                                 DRV_MSG_SEQ_NUMBER_MASK);
7570
7571                 } else
7572                         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7573         }
7574 }
7575
7576 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7577 {
7578         u32 val, val2, val3, val4, id;
7579         u16 pmc;
7580
7581         /* Get the chip revision id and number. */
7582         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7583         val = REG_RD(bp, MISC_REG_CHIP_NUM);
7584         id = ((val & 0xffff) << 16);
7585         val = REG_RD(bp, MISC_REG_CHIP_REV);
7586         id |= ((val & 0xf) << 12);
7587         val = REG_RD(bp, MISC_REG_CHIP_METAL);
7588         id |= ((val & 0xff) << 4);
7589         val = REG_RD(bp, MISC_REG_BOND_ID);
7590         id |= (val & 0xf);
7591         bp->common.chip_id = id;
7592         bp->link_params.chip_id = bp->common.chip_id;
7593         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7594
7595         val = (REG_RD(bp, 0x2874) & 0x55);
7596         if ((bp->common.chip_id & 0x1) ||
7597             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7598                 bp->flags |= ONE_PORT_FLAG;
7599                 BNX2X_DEV_INFO("single port device\n");
7600         }
7601
7602         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7603         bp->common.flash_size = (NVRAM_1MB_SIZE <<
7604                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
7605         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7606                        bp->common.flash_size, bp->common.flash_size);
7607
7608         bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7609         bp->link_params.shmem_base = bp->common.shmem_base;
7610         BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
7611
7612         if (!bp->common.shmem_base ||
7613             (bp->common.shmem_base < 0xA0000) ||
7614             (bp->common.shmem_base >= 0xC0000)) {
7615                 BNX2X_DEV_INFO("MCP not active\n");
7616                 bp->flags |= NO_MCP_FLAG;
7617                 return;
7618         }
7619
7620         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7621         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7622                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7623                 BNX2X_ERR("BAD MCP validity signature\n");
7624
7625         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7626         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
7627
7628         bp->link_params.hw_led_mode = ((bp->common.hw_config &
7629                                         SHARED_HW_CFG_LED_MODE_MASK) >>
7630                                        SHARED_HW_CFG_LED_MODE_SHIFT);
7631
7632         bp->link_params.feature_config_flags = 0;
7633         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7634         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7635                 bp->link_params.feature_config_flags |=
7636                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7637         else
7638                 bp->link_params.feature_config_flags &=
7639                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7640
7641         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7642         bp->common.bc_ver = val;
7643         BNX2X_DEV_INFO("bc_ver %X\n", val);
7644         if (val < BNX2X_BC_VER) {
7645                 /* for now only warn
7646                  * later we might need to enforce this */
7647                 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
7648                           " please upgrade BC\n", BNX2X_BC_VER, val);
7649         }
7650
7651         if (BP_E1HVN(bp) == 0) {
7652                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7653                 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7654         } else {
7655                 /* no WOL capability for E1HVN != 0 */
7656                 bp->flags |= NO_WOL_FLAG;
7657         }
7658         BNX2X_DEV_INFO("%sWoL capable\n",
7659                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
7660
7661         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7662         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7663         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7664         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7665
7666         printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
7667                val, val2, val3, val4);
7668 }
7669
7670 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7671                                                     u32 switch_cfg)
7672 {
7673         int port = BP_PORT(bp);
7674         u32 ext_phy_type;
7675
7676         switch (switch_cfg) {
7677         case SWITCH_CFG_1G:
7678                 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
7679
7680                 ext_phy_type =
7681                         SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7682                 switch (ext_phy_type) {
7683                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
7684                         BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7685                                        ext_phy_type);
7686
7687                         bp->port.supported |= (SUPPORTED_10baseT_Half |
7688                                                SUPPORTED_10baseT_Full |
7689                                                SUPPORTED_100baseT_Half |
7690                                                SUPPORTED_100baseT_Full |
7691                                                SUPPORTED_1000baseT_Full |
7692                                                SUPPORTED_2500baseX_Full |
7693                                                SUPPORTED_TP |
7694                                                SUPPORTED_FIBRE |
7695                                                SUPPORTED_Autoneg |
7696                                                SUPPORTED_Pause |
7697                                                SUPPORTED_Asym_Pause);
7698                         break;
7699
7700                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
7701                         BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
7702                                        ext_phy_type);
7703
7704                         bp->port.supported |= (SUPPORTED_10baseT_Half |
7705                                                SUPPORTED_10baseT_Full |
7706                                                SUPPORTED_100baseT_Half |
7707                                                SUPPORTED_100baseT_Full |
7708                                                SUPPORTED_1000baseT_Full |
7709                                                SUPPORTED_TP |
7710                                                SUPPORTED_FIBRE |
7711                                                SUPPORTED_Autoneg |
7712                                                SUPPORTED_Pause |
7713                                                SUPPORTED_Asym_Pause);
7714                         break;
7715
7716                 default:
7717                         BNX2X_ERR("NVRAM config error. "
7718                                   "BAD SerDes ext_phy_config 0x%x\n",
7719                                   bp->link_params.ext_phy_config);
7720                         return;
7721                 }
7722
7723                 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
7724                                            port*0x10);
7725                 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7726                 break;
7727
7728         case SWITCH_CFG_10G:
7729                 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
7730
7731                 ext_phy_type =
7732                         XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7733                 switch (ext_phy_type) {
7734                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7735                         BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7736                                        ext_phy_type);
7737
7738                         bp->port.supported |= (SUPPORTED_10baseT_Half |
7739                                                SUPPORTED_10baseT_Full |
7740                                                SUPPORTED_100baseT_Half |
7741                                                SUPPORTED_100baseT_Full |
7742                                                SUPPORTED_1000baseT_Full |
7743                                                SUPPORTED_2500baseX_Full |
7744                                                SUPPORTED_10000baseT_Full |
7745                                                SUPPORTED_TP |
7746                                                SUPPORTED_FIBRE |
7747                                                SUPPORTED_Autoneg |
7748                                                SUPPORTED_Pause |
7749                                                SUPPORTED_Asym_Pause);
7750                         break;
7751
7752                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7753                         BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
7754                                        ext_phy_type);
7755
7756                         bp->port.supported |= (SUPPORTED_10000baseT_Full |
7757                                                SUPPORTED_1000baseT_Full |
7758                                                SUPPORTED_FIBRE |
7759                                                SUPPORTED_Autoneg |
7760                                                SUPPORTED_Pause |
7761                                                SUPPORTED_Asym_Pause);
7762                         break;
7763
7764                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7765                         BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
7766                                        ext_phy_type);
7767
7768                         bp->port.supported |= (SUPPORTED_10000baseT_Full |
7769                                                SUPPORTED_2500baseX_Full |
7770                                                SUPPORTED_1000baseT_Full |
7771                                                SUPPORTED_FIBRE |
7772                                                SUPPORTED_Autoneg |
7773                                                SUPPORTED_Pause |
7774                                                SUPPORTED_Asym_Pause);
7775                         break;
7776
7777                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7778                         BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
7779                                        ext_phy_type);
7780
7781                         bp->port.supported |= (SUPPORTED_10000baseT_Full |
7782                                                SUPPORTED_FIBRE |
7783                                                SUPPORTED_Pause |
7784                                                SUPPORTED_Asym_Pause);
7785                         break;
7786
7787                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7788                         BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
7789                                        ext_phy_type);
7790
7791                         bp->port.supported |= (SUPPORTED_10000baseT_Full |
7792                                                SUPPORTED_1000baseT_Full |
7793                                                SUPPORTED_FIBRE |
7794                                                SUPPORTED_Pause |
7795                                                SUPPORTED_Asym_Pause);
7796                         break;
7797
7798                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7799                         BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
7800                                        ext_phy_type);
7801
7802                         bp->port.supported |= (SUPPORTED_10000baseT_Full |
7803                                                SUPPORTED_1000baseT_Full |
7804                                                SUPPORTED_Autoneg |
7805                                                SUPPORTED_FIBRE |
7806                                                SUPPORTED_Pause |
7807                                                SUPPORTED_Asym_Pause);
7808                         break;
7809
7810                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7811                         BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
7812                                        ext_phy_type);
7813
7814                         bp->port.supported |= (SUPPORTED_10000baseT_Full |
7815                                                SUPPORTED_TP |
7816                                                SUPPORTED_Autoneg |
7817                                                SUPPORTED_Pause |
7818                                                SUPPORTED_Asym_Pause);
7819                         break;
7820
7821                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7822                         BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n",
7823                                        ext_phy_type);
7824
7825                         bp->port.supported |= (SUPPORTED_10baseT_Half |
7826                                                SUPPORTED_10baseT_Full |
7827                                                SUPPORTED_100baseT_Half |
7828                                                SUPPORTED_100baseT_Full |
7829                                                SUPPORTED_1000baseT_Full |
7830                                                SUPPORTED_10000baseT_Full |
7831                                                SUPPORTED_TP |
7832                                                SUPPORTED_Autoneg |
7833                                                SUPPORTED_Pause |
7834                                                SUPPORTED_Asym_Pause);
7835                         break;
7836
7837                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7838                         BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7839                                   bp->link_params.ext_phy_config);
7840                         break;
7841
7842                 default:
7843                         BNX2X_ERR("NVRAM config error. "
7844                                   "BAD XGXS ext_phy_config 0x%x\n",
7845                                   bp->link_params.ext_phy_config);
7846                         return;
7847                 }
7848
7849                 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
7850                                            port*0x18);
7851                 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7852
7853                 break;
7854
7855         default:
7856                 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
7857                           bp->port.link_config);
7858                 return;
7859         }
7860         bp->link_params.phy_addr = bp->port.phy_addr;
7861
7862         /* mask what we support according to speed_cap_mask */
7863         if (!(bp->link_params.speed_cap_mask &
7864                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
7865                 bp->port.supported &= ~SUPPORTED_10baseT_Half;
7866
7867         if (!(bp->link_params.speed_cap_mask &
7868                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
7869                 bp->port.supported &= ~SUPPORTED_10baseT_Full;
7870
7871         if (!(bp->link_params.speed_cap_mask &
7872                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
7873                 bp->port.supported &= ~SUPPORTED_100baseT_Half;
7874
7875         if (!(bp->link_params.speed_cap_mask &
7876                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
7877                 bp->port.supported &= ~SUPPORTED_100baseT_Full;
7878
7879         if (!(bp->link_params.speed_cap_mask &
7880                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
7881                 bp->port.supported &= ~(SUPPORTED_1000baseT_Half |
7882                                         SUPPORTED_1000baseT_Full);
7883
7884         if (!(bp->link_params.speed_cap_mask &
7885                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7886                 bp->port.supported &= ~SUPPORTED_2500baseX_Full;
7887
7888         if (!(bp->link_params.speed_cap_mask &
7889                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
7890                 bp->port.supported &= ~SUPPORTED_10000baseT_Full;
7891
7892         BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported);
7893 }
7894
7895 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
7896 {
7897         bp->link_params.req_duplex = DUPLEX_FULL;
7898
7899         switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7900         case PORT_FEATURE_LINK_SPEED_AUTO:
7901                 if (bp->port.supported & SUPPORTED_Autoneg) {
7902                         bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7903                         bp->port.advertising = bp->port.supported;
7904                 } else {
7905                         u32 ext_phy_type =
7906                             XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7907
7908                         if ((ext_phy_type ==
7909                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
7910                             (ext_phy_type ==
7911                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
7912                                 /* force 10G, no AN */
7913                                 bp->link_params.req_line_speed = SPEED_10000;
7914                                 bp->port.advertising =
7915                                                 (ADVERTISED_10000baseT_Full |
7916                                                  ADVERTISED_FIBRE);
7917                                 break;
7918                         }
7919                         BNX2X_ERR("NVRAM config error. "
7920                                   "Invalid link_config 0x%x"
7921                                   "  Autoneg not supported\n",
7922                                   bp->port.link_config);
7923                         return;
7924                 }
7925                 break;
7926
7927         case PORT_FEATURE_LINK_SPEED_10M_FULL:
7928                 if (bp->port.supported & SUPPORTED_10baseT_Full) {
7929                         bp->link_params.req_line_speed = SPEED_10;
7930                         bp->port.advertising = (ADVERTISED_10baseT_Full |
7931                                                 ADVERTISED_TP);
7932                 } else {
7933                         BNX2X_ERR("NVRAM config error. "
7934                                   "Invalid link_config 0x%x"
7935                                   "  speed_cap_mask 0x%x\n",
7936                                   bp->port.link_config,
7937                                   bp->link_params.speed_cap_mask);
7938                         return;
7939                 }
7940                 break;
7941
7942         case PORT_FEATURE_LINK_SPEED_10M_HALF:
7943                 if (bp->port.supported & SUPPORTED_10baseT_Half) {
7944                         bp->link_params.req_line_speed = SPEED_10;
7945                         bp->link_params.req_duplex = DUPLEX_HALF;
7946                         bp->port.advertising = (ADVERTISED_10baseT_Half |
7947                                                 ADVERTISED_TP);
7948                 } else {
7949                         BNX2X_ERR("NVRAM config error. "
7950                                   "Invalid link_config 0x%x"
7951                                   "  speed_cap_mask 0x%x\n",
7952                                   bp->port.link_config,
7953                                   bp->link_params.speed_cap_mask);
7954                         return;
7955                 }
7956                 break;
7957
7958         case PORT_FEATURE_LINK_SPEED_100M_FULL:
7959                 if (bp->port.supported & SUPPORTED_100baseT_Full) {
7960                         bp->link_params.req_line_speed = SPEED_100;
7961                         bp->port.advertising = (ADVERTISED_100baseT_Full |
7962                                                 ADVERTISED_TP);
7963                 } else {
7964                         BNX2X_ERR("NVRAM config error. "
7965                                   "Invalid link_config 0x%x"
7966                                   "  speed_cap_mask 0x%x\n",
7967                                   bp->port.link_config,
7968                                   bp->link_params.speed_cap_mask);
7969                         return;
7970                 }
7971                 break;
7972
7973         case PORT_FEATURE_LINK_SPEED_100M_HALF:
7974                 if (bp->port.supported & SUPPORTED_100baseT_Half) {
7975                         bp->link_params.req_line_speed = SPEED_100;
7976                         bp->link_params.req_duplex = DUPLEX_HALF;
7977                         bp->port.advertising = (ADVERTISED_100baseT_Half |
7978                                                 ADVERTISED_TP);
7979                 } else {
7980                         BNX2X_ERR("NVRAM config error. "
7981                                   "Invalid link_config 0x%x"
7982                                   "  speed_cap_mask 0x%x\n",
7983                                   bp->port.link_config,
7984                                   bp->link_params.speed_cap_mask);
7985                         return;
7986                 }
7987                 break;
7988
7989         case PORT_FEATURE_LINK_SPEED_1G:
7990                 if (bp->port.supported & SUPPORTED_1000baseT_Full) {
7991                         bp->link_params.req_line_speed = SPEED_1000;
7992                         bp->port.advertising = (ADVERTISED_1000baseT_Full |
7993                                                 ADVERTISED_TP);
7994                 } else {
7995                         BNX2X_ERR("NVRAM config error. "
7996                                   "Invalid link_config 0x%x"
7997                                   "  speed_cap_mask 0x%x\n",
7998                                   bp->port.link_config,
7999                                   bp->link_params.speed_cap_mask);
8000                         return;
8001                 }
8002                 break;
8003
8004         case PORT_FEATURE_LINK_SPEED_2_5G:
8005                 if (bp->port.supported & SUPPORTED_2500baseX_Full) {
8006                         bp->link_params.req_line_speed = SPEED_2500;
8007                         bp->port.advertising = (ADVERTISED_2500baseX_Full |
8008                                                 ADVERTISED_TP);
8009                 } else {
8010                         BNX2X_ERR("NVRAM config error. "
8011                                   "Invalid link_config 0x%x"
8012                                   "  speed_cap_mask 0x%x\n",
8013                                   bp->port.link_config,
8014                                   bp->link_params.speed_cap_mask);
8015                         return;
8016                 }
8017                 break;
8018
8019         case PORT_FEATURE_LINK_SPEED_10G_CX4:
8020         case PORT_FEATURE_LINK_SPEED_10G_KX4:
8021         case PORT_FEATURE_LINK_SPEED_10G_KR:
8022                 if (bp->port.supported & SUPPORTED_10000baseT_Full) {
8023                         bp->link_params.req_line_speed = SPEED_10000;
8024                         bp->port.advertising = (ADVERTISED_10000baseT_Full |
8025                                                 ADVERTISED_FIBRE);
8026                 } else {
8027                         BNX2X_ERR("NVRAM config error. "
8028                                   "Invalid link_config 0x%x"
8029                                   "  speed_cap_mask 0x%x\n",
8030                                   bp->port.link_config,
8031                                   bp->link_params.speed_cap_mask);
8032                         return;
8033                 }
8034                 break;
8035
8036         default:
8037                 BNX2X_ERR("NVRAM config error. "
8038                           "BAD link speed link_config 0x%x\n",
8039                           bp->port.link_config);
8040                 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
8041                 bp->port.advertising = bp->port.supported;
8042                 break;
8043         }
8044
8045         bp->link_params.req_flow_ctrl = (bp->port.link_config &
8046                                          PORT_FEATURE_FLOW_CONTROL_MASK);
8047         if ((bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
8048             !(bp->port.supported & SUPPORTED_Autoneg))
8049                 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8050
8051         BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d  req_flow_ctrl 0x%x"
8052                        "  advertising 0x%x\n",
8053                        bp->link_params.req_line_speed,
8054                        bp->link_params.req_duplex,
8055                        bp->link_params.req_flow_ctrl, bp->port.advertising);
8056 }
8057
8058 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8059 {
8060         int port = BP_PORT(bp);
8061         u32 val, val2;
8062         u32 config;
8063         u16 i;
8064
8065         bp->link_params.bp = bp;
8066         bp->link_params.port = port;
8067
8068         bp->link_params.lane_config =
8069                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8070         bp->link_params.ext_phy_config =
8071                 SHMEM_RD(bp,
8072                          dev_info.port_hw_config[port].external_phy_config);
8073         bp->link_params.speed_cap_mask =
8074                 SHMEM_RD(bp,
8075                          dev_info.port_hw_config[port].speed_capability_mask);
8076
8077         bp->port.link_config =
8078                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8079
8080         /* Get the 4 lanes xgxs config rx and tx */
8081         for (i = 0; i < 2; i++) {
8082                 val = SHMEM_RD(bp,
8083                            dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
8084                 bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
8085                 bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
8086
8087                 val = SHMEM_RD(bp,
8088                            dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
8089                 bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
8090                 bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
8091         }
8092
8093         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8094         if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED)
8095                 bp->link_params.feature_config_flags |=
8096                                 FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
8097         else
8098                 bp->link_params.feature_config_flags &=
8099                                 ~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
8100
8101         /* If the device is capable of WoL, set the default state according
8102          * to the HW
8103          */
8104         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8105                    (config & PORT_FEATURE_WOL_ENABLED));
8106
8107         BNX2X_DEV_INFO("lane_config 0x%08x  ext_phy_config 0x%08x"
8108                        "  speed_cap_mask 0x%08x  link_config 0x%08x\n",
8109                        bp->link_params.lane_config,
8110                        bp->link_params.ext_phy_config,
8111                        bp->link_params.speed_cap_mask, bp->port.link_config);
8112
8113         bp->link_params.switch_cfg = (bp->port.link_config &
8114                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
8115         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8116
8117         bnx2x_link_settings_requested(bp);
8118
8119         val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8120         val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8121         bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
8122         bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
8123         bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
8124         bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
8125         bp->dev->dev_addr[4] = (u8)(val >> 8  & 0xff);
8126         bp->dev->dev_addr[5] = (u8)(val & 0xff);
8127         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8128         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8129 }
8130
8131 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8132 {
8133         int func = BP_FUNC(bp);
8134         u32 val, val2;
8135         int rc = 0;
8136
8137         bnx2x_get_common_hwinfo(bp);
8138
8139         bp->e1hov = 0;
8140         bp->e1hmf = 0;
8141         if (CHIP_IS_E1H(bp)) {
8142                 bp->mf_config =
8143                         SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
8144
8145                 val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
8146                        FUNC_MF_CFG_E1HOV_TAG_MASK);
8147                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8148
8149                         bp->e1hov = val;
8150                         bp->e1hmf = 1;
8151                         BNX2X_DEV_INFO("MF mode  E1HOV for func %d is %d "
8152                                        "(0x%04x)\n",
8153                                        func, bp->e1hov, bp->e1hov);
8154                 } else {
8155                         BNX2X_DEV_INFO("single function mode\n");
8156                         if (BP_E1HVN(bp)) {
8157                                 BNX2X_ERR("!!!  No valid E1HOV for func %d,"
8158                                           "  aborting\n", func);
8159                                 rc = -EPERM;
8160                         }
8161                 }
8162         }
8163
8164         if (!BP_NOMCP(bp)) {
8165                 bnx2x_get_port_hwinfo(bp);
8166
8167                 bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) &
8168                               DRV_MSG_SEQ_NUMBER_MASK);
8169                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8170         }
8171
8172         if (IS_E1HMF(bp)) {
8173                 val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper);
8174                 val = SHMEM_RD(bp,  mf_cfg.func_mf_config[func].mac_lower);
8175                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8176                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
8177                         bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
8178                         bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
8179                         bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
8180                         bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
8181                         bp->dev->dev_addr[4] = (u8)(val >> 8  & 0xff);
8182                         bp->dev->dev_addr[5] = (u8)(val & 0xff);
8183                         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
8184                                ETH_ALEN);
8185                         memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
8186                                ETH_ALEN);
8187                 }
8188
8189                 return rc;
8190         }
8191
8192         if (BP_NOMCP(bp)) {
8193                 /* only supposed to happen on emulation/FPGA */
8194                 BNX2X_ERR("warning random MAC workaround active\n");
8195                 random_ether_addr(bp->dev->dev_addr);
8196                 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8197         }
8198
8199         return rc;
8200 }
8201
8202 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8203 {
8204         int func = BP_FUNC(bp);
8205         int timer_interval;
8206         int rc;
8207
8208         /* Disable interrupt handling until HW is initialized */
8209         atomic_set(&bp->intr_sem, 1);
8210
8211         mutex_init(&bp->port.phy_mutex);
8212
8213         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8214         INIT_WORK(&bp->reset_task, bnx2x_reset_task);
8215
8216         rc = bnx2x_get_hwinfo(bp);
8217
8218         /* need to reset chip if undi was active */
8219         if (!BP_NOMCP(bp))
8220                 bnx2x_undi_unload(bp);
8221
8222         if (CHIP_REV_IS_FPGA(bp))
8223                 printk(KERN_ERR PFX "FPGA detected\n");
8224
8225         if (BP_NOMCP(bp) && (func == 0))
8226                 printk(KERN_ERR PFX
8227                        "MCP disabled, must load devices in order!\n");
8228
8229         /* Set multi queue mode */
8230         if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
8231             ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
8232                 printk(KERN_ERR PFX
8233                       "Multi disabled since int_mode requested is not MSI-X\n");
8234                 multi_mode = ETH_RSS_MODE_DISABLED;
8235         }
8236         bp->multi_mode = multi_mode;
8237
8238
8239         /* Set TPA flags */
8240         if (disable_tpa) {
8241                 bp->flags &= ~TPA_ENABLE_FLAG;
8242                 bp->dev->features &= ~NETIF_F_LRO;
8243         } else {
8244                 bp->flags |= TPA_ENABLE_FLAG;
8245                 bp->dev->features |= NETIF_F_LRO;
8246         }
8247
8248         bp->mrrs = mrrs;
8249
8250         bp->tx_ring_size = MAX_TX_AVAIL;
8251         bp->rx_ring_size = MAX_RX_AVAIL;
8252
8253         bp->rx_csum = 1;
8254
8255         bp->tx_ticks = 50;
8256         bp->rx_ticks = 25;
8257
8258         timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8259         bp->current_interval = (poll ? poll : timer_interval);
8260
8261         init_timer(&bp->timer);
8262         bp->timer.expires = jiffies + bp->current_interval;
8263         bp->timer.data = (unsigned long) bp;
8264         bp->timer.function = bnx2x_timer;
8265
8266         return rc;
8267 }
8268
8269 /*
8270  * ethtool service functions
8271  */
8272
8273 /* All ethtool functions called with rtnl_lock */
8274
8275 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8276 {
8277         struct bnx2x *bp = netdev_priv(dev);
8278
8279         cmd->supported = bp->port.supported;
8280         cmd->advertising = bp->port.advertising;
8281
8282         if (netif_carrier_ok(dev)) {
8283                 cmd->speed = bp->link_vars.line_speed;
8284                 cmd->duplex = bp->link_vars.duplex;
8285         } else {
8286                 cmd->speed = bp->link_params.req_line_speed;
8287                 cmd->duplex = bp->link_params.req_duplex;
8288         }
8289         if (IS_E1HMF(bp)) {
8290                 u16 vn_max_rate;
8291
8292                 vn_max_rate = ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
8293                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
8294                 if (vn_max_rate < cmd->speed)
8295                         cmd->speed = vn_max_rate;
8296         }
8297
8298         if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
8299                 u32 ext_phy_type =
8300                         XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
8301
8302                 switch (ext_phy_type) {
8303                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8304                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
8305                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
8306                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
8307                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
8308                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8309                         cmd->port = PORT_FIBRE;
8310                         break;
8311
8312                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
8313                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
8314                         cmd->port = PORT_TP;
8315                         break;
8316
8317                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8318                         BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
8319                                   bp->link_params.ext_phy_config);
8320                         break;
8321
8322                 default:
8323                         DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
8324                            bp->link_params.ext_phy_config);
8325                         break;
8326                 }
8327         } else
8328                 cmd->port = PORT_TP;
8329
8330         cmd->phy_address = bp->port.phy_addr;
8331         cmd->transceiver = XCVR_INTERNAL;
8332
8333         if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
8334                 cmd->autoneg = AUTONEG_ENABLE;
8335         else
8336                 cmd->autoneg = AUTONEG_DISABLE;
8337
8338         cmd->maxtxpkt = 0;
8339         cmd->maxrxpkt = 0;
8340
8341         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
8342            DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
8343            DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
8344            DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
8345            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
8346            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
8347            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
8348
8349         return 0;
8350 }
8351
8352 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8353 {
8354         struct bnx2x *bp = netdev_priv(dev);
8355         u32 advertising;
8356
8357         if (IS_E1HMF(bp))
8358                 return 0;
8359
8360         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
8361            DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
8362            DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
8363            DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
8364            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
8365            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
8366            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
8367
8368         if (cmd->autoneg == AUTONEG_ENABLE) {
8369                 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
8370                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
8371                         return -EINVAL;
8372                 }
8373
8374                 /* advertise the requested speed and duplex if supported */
8375                 cmd->advertising &= bp->port.supported;
8376
8377                 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
8378                 bp->link_params.req_duplex = DUPLEX_FULL;
8379                 bp->port.advertising |= (ADVERTISED_Autoneg |
8380                                          cmd->advertising);
8381
8382         } else { /* forced speed */
8383                 /* advertise the requested speed and duplex if supported */
8384                 switch (cmd->speed) {
8385                 case SPEED_10:
8386                         if (cmd->duplex == DUPLEX_FULL) {
8387                                 if (!(bp->port.supported &
8388                                       SUPPORTED_10baseT_Full)) {
8389                                         DP(NETIF_MSG_LINK,
8390                                            "10M full not supported\n");
8391                                         return -EINVAL;
8392                                 }
8393
8394                                 advertising = (ADVERTISED_10baseT_Full |
8395                                                ADVERTISED_TP);
8396                         } else {
8397                                 if (!(bp->port.supported &
8398                                       SUPPORTED_10baseT_Half)) {
8399                                         DP(NETIF_MSG_LINK,
8400                                            "10M half not supported\n");
8401                                         return -EINVAL;
8402                                 }
8403
8404                                 advertising = (ADVERTISED_10baseT_Half |
8405                                                ADVERTISED_TP);
8406                         }
8407                         break;
8408
8409                 case SPEED_100:
8410                         if (cmd->duplex == DUPLEX_FULL) {
8411                                 if (!(bp->port.supported &
8412                                                 SUPPORTED_100baseT_Full)) {
8413                                         DP(NETIF_MSG_LINK,
8414                                            "100M full not supported\n");
8415                                         return -EINVAL;
8416                                 }
8417
8418                                 advertising = (ADVERTISED_100baseT_Full |
8419                                                ADVERTISED_TP);
8420                         } else {
8421                                 if (!(bp->port.supported &
8422                                                 SUPPORTED_100baseT_Half)) {
8423                                         DP(NETIF_MSG_LINK,
8424                                            "100M half not supported\n");
8425                                         return -EINVAL;
8426                                 }
8427
8428                                 advertising = (ADVERTISED_100baseT_Half |
8429                                                ADVERTISED_TP);
8430                         }
8431                         break;
8432
8433                 case SPEED_1000:
8434                         if (cmd->duplex != DUPLEX_FULL) {
8435                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
8436                                 return -EINVAL;
8437                         }
8438
8439                         if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
8440                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
8441                                 return -EINVAL;
8442                         }
8443
8444                         advertising = (ADVERTISED_1000baseT_Full |
8445                                        ADVERTISED_TP);
8446                         break;
8447
8448                 case SPEED_2500:
8449                         if (cmd->duplex != DUPLEX_FULL) {
8450                                 DP(NETIF_MSG_LINK,
8451                                    "2.5G half not supported\n");
8452                                 return -EINVAL;
8453                         }
8454
8455                         if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
8456                                 DP(NETIF_MSG_LINK,
8457                                    "2.5G full not supported\n");
8458                                 return -EINVAL;
8459                         }
8460
8461                         advertising = (ADVERTISED_2500baseX_Full |
8462                                        ADVERTISED_TP);
8463                         break;
8464
8465                 case SPEED_10000:
8466                         if (cmd->duplex != DUPLEX_FULL) {
8467                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
8468                                 return -EINVAL;
8469                         }
8470
8471                         if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
8472                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
8473                                 return -EINVAL;
8474                         }
8475
8476                         advertising = (ADVERTISED_10000baseT_Full |
8477                                        ADVERTISED_FIBRE);
8478                         break;
8479
8480                 default:
8481                         DP(NETIF_MSG_LINK, "Unsupported speed\n");
8482                         return -EINVAL;
8483                 }
8484
8485                 bp->link_params.req_line_speed = cmd->speed;
8486                 bp->link_params.req_duplex = cmd->duplex;
8487                 bp->port.advertising = advertising;
8488         }
8489
8490         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
8491            DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
8492            bp->link_params.req_line_speed, bp->link_params.req_duplex,
8493            bp->port.advertising);
8494
8495         if (netif_running(dev)) {
8496                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8497                 bnx2x_link_set(bp);
8498         }
8499
8500         return 0;
8501 }
8502
8503 #define PHY_FW_VER_LEN                  10
8504
8505 static void bnx2x_get_drvinfo(struct net_device *dev,
8506                               struct ethtool_drvinfo *info)
8507 {
8508         struct bnx2x *bp = netdev_priv(dev);
8509         u8 phy_fw_ver[PHY_FW_VER_LEN];
8510
8511         strcpy(info->driver, DRV_MODULE_NAME);
8512         strcpy(info->version, DRV_MODULE_VERSION);
8513
8514         phy_fw_ver[0] = '\0';
8515         if (bp->port.pmf) {
8516                 bnx2x_acquire_phy_lock(bp);
8517                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
8518                                              (bp->state != BNX2X_STATE_CLOSED),
8519                                              phy_fw_ver, PHY_FW_VER_LEN);
8520                 bnx2x_release_phy_lock(bp);
8521         }
8522
8523         snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s",
8524                  (bp->common.bc_ver & 0xff0000) >> 16,
8525                  (bp->common.bc_ver & 0xff00) >> 8,
8526                  (bp->common.bc_ver & 0xff),
8527                  ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver);
8528         strcpy(info->bus_info, pci_name(bp->pdev));
8529         info->n_stats = BNX2X_NUM_STATS;
8530         info->testinfo_len = BNX2X_NUM_TESTS;
8531         info->eedump_len = bp->common.flash_size;
8532         info->regdump_len = 0;
8533 }
8534
8535 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
8536 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
8537
8538 static int bnx2x_get_regs_len(struct net_device *dev)
8539 {
8540         static u32 regdump_len;
8541         struct bnx2x *bp = netdev_priv(dev);
8542         int i;
8543
8544         if (regdump_len)
8545                 return regdump_len;
8546
8547         if (CHIP_IS_E1(bp)) {
8548                 for (i = 0; i < REGS_COUNT; i++)
8549                         if (IS_E1_ONLINE(reg_addrs[i].info))
8550                                 regdump_len += reg_addrs[i].size;
8551
8552                 for (i = 0; i < WREGS_COUNT_E1; i++)
8553                         if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
8554                                 regdump_len += wreg_addrs_e1[i].size *
8555                                         (1 + wreg_addrs_e1[i].read_regs_count);
8556
8557         } else { /* E1H */
8558                 for (i = 0; i < REGS_COUNT; i++)
8559                         if (IS_E1H_ONLINE(reg_addrs[i].info))
8560                                 regdump_len += reg_addrs[i].size;
8561
8562                 for (i = 0; i < WREGS_COUNT_E1H; i++)
8563                         if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
8564                                 regdump_len += wreg_addrs_e1h[i].size *
8565                                         (1 + wreg_addrs_e1h[i].read_regs_count);
8566         }
8567         regdump_len *= 4;
8568         regdump_len += sizeof(struct dump_hdr);
8569
8570         return regdump_len;
8571 }
8572
8573 static void bnx2x_get_regs(struct net_device *dev,
8574                            struct ethtool_regs *regs, void *_p)
8575 {
8576         u32 *p = _p, i, j;
8577         struct bnx2x *bp = netdev_priv(dev);
8578         struct dump_hdr dump_hdr = {0};
8579
8580         regs->version = 0;
8581         memset(p, 0, regs->len);
8582
8583         if (!netif_running(bp->dev))
8584                 return;
8585
8586         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
8587         dump_hdr.dump_sign = dump_sign_all;
8588         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
8589         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
8590         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
8591         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
8592         dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE;
8593
8594         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
8595         p += dump_hdr.hdr_size + 1;
8596
8597         if (CHIP_IS_E1(bp)) {
8598                 for (i = 0; i < REGS_COUNT; i++)
8599                         if (IS_E1_ONLINE(reg_addrs[i].info))
8600                                 for (j = 0; j < reg_addrs[i].size; j++)
8601                                         *p++ = REG_RD(bp,
8602                                                       reg_addrs[i].addr + j*4);
8603
8604         } else { /* E1H */
8605                 for (i = 0; i < REGS_COUNT; i++)
8606                         if (IS_E1H_ONLINE(reg_addrs[i].info))
8607                                 for (j = 0; j < reg_addrs[i].size; j++)
8608                                         *p++ = REG_RD(bp,
8609                                                       reg_addrs[i].addr + j*4);
8610         }
8611 }
8612
8613 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8614 {
8615         struct bnx2x *bp = netdev_priv(dev);
8616
8617         if (bp->flags & NO_WOL_FLAG) {
8618                 wol->supported = 0;
8619                 wol->wolopts = 0;
8620         } else {
8621                 wol->supported = WAKE_MAGIC;
8622                 if (bp->wol)
8623                         wol->wolopts = WAKE_MAGIC;
8624                 else
8625                         wol->wolopts = 0;
8626         }
8627         memset(&wol->sopass, 0, sizeof(wol->sopass));
8628 }
8629
8630 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8631 {
8632         struct bnx2x *bp = netdev_priv(dev);
8633
8634         if (wol->wolopts & ~WAKE_MAGIC)
8635                 return -EINVAL;
8636
8637         if (wol->wolopts & WAKE_MAGIC) {
8638                 if (bp->flags & NO_WOL_FLAG)
8639                         return -EINVAL;
8640
8641                 bp->wol = 1;
8642         } else
8643                 bp->wol = 0;
8644
8645         return 0;
8646 }
8647
8648 static u32 bnx2x_get_msglevel(struct net_device *dev)
8649 {
8650         struct bnx2x *bp = netdev_priv(dev);
8651
8652         return bp->msglevel;
8653 }
8654
8655 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
8656 {
8657         struct bnx2x *bp = netdev_priv(dev);
8658
8659         if (capable(CAP_NET_ADMIN))
8660                 bp->msglevel = level;
8661 }
8662
8663 static int bnx2x_nway_reset(struct net_device *dev)
8664 {
8665         struct bnx2x *bp = netdev_priv(dev);
8666
8667         if (!bp->port.pmf)
8668                 return 0;
8669
8670         if (netif_running(dev)) {
8671                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8672                 bnx2x_link_set(bp);
8673         }
8674
8675         return 0;
8676 }
8677
8678 static u32
8679 bnx2x_get_link(struct net_device *dev)
8680 {
8681         struct bnx2x *bp = netdev_priv(dev);
8682
8683         return bp->link_vars.link_up;
8684 }
8685
8686 static int bnx2x_get_eeprom_len(struct net_device *dev)
8687 {
8688         struct bnx2x *bp = netdev_priv(dev);
8689
8690         return bp->common.flash_size;
8691 }
8692
8693 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
8694 {
8695         int port = BP_PORT(bp);
8696         int count, i;
8697         u32 val = 0;
8698
8699         /* adjust timeout for emulation/FPGA */
8700         count = NVRAM_TIMEOUT_COUNT;
8701         if (CHIP_REV_IS_SLOW(bp))
8702                 count *= 100;
8703
8704         /* request access to nvram interface */
8705         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
8706                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
8707
8708         for (i = 0; i < count*10; i++) {
8709                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
8710                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
8711                         break;
8712
8713                 udelay(5);
8714         }
8715
8716         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
8717                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
8718                 return -EBUSY;
8719         }
8720
8721         return 0;
8722 }
8723
8724 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
8725 {
8726         int port = BP_PORT(bp);
8727         int count, i;
8728         u32 val = 0;
8729
8730         /* adjust timeout for emulation/FPGA */
8731         count = NVRAM_TIMEOUT_COUNT;
8732         if (CHIP_REV_IS_SLOW(bp))
8733                 count *= 100;
8734
8735         /* relinquish nvram interface */
8736         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
8737                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
8738
8739         for (i = 0; i < count*10; i++) {
8740                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
8741                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
8742                         break;
8743
8744                 udelay(5);
8745         }
8746
8747         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
8748                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
8749                 return -EBUSY;
8750         }
8751
8752         return 0;
8753 }
8754
8755 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
8756 {
8757         u32 val;
8758
8759         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
8760
8761         /* enable both bits, even on read */
8762         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
8763                (val | MCPR_NVM_ACCESS_ENABLE_EN |
8764                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
8765 }
8766
8767 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
8768 {
8769         u32 val;
8770
8771         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
8772
8773         /* disable both bits, even after read */
8774         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
8775                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
8776                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
8777 }
8778
8779 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
8780                                   u32 cmd_flags)
8781 {
8782         int count, i, rc;
8783         u32 val;
8784
8785         /* build the command word */
8786         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
8787
8788         /* need to clear DONE bit separately */
8789         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8790
8791         /* address of the NVRAM to read from */
8792         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8793                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8794
8795         /* issue a read command */
8796         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8797
8798         /* adjust timeout for emulation/FPGA */
8799         count = NVRAM_TIMEOUT_COUNT;
8800         if (CHIP_REV_IS_SLOW(bp))
8801                 count *= 100;
8802
8803         /* wait for completion */
8804         *ret_val = 0;
8805         rc = -EBUSY;
8806         for (i = 0; i < count; i++) {
8807                 udelay(5);
8808                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8809
8810                 if (val & MCPR_NVM_COMMAND_DONE) {
8811                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
8812                         /* we read nvram data in cpu order
8813                          * but ethtool sees it as an array of bytes
8814                          * converting to big-endian will do the work */
8815                         *ret_val = cpu_to_be32(val);
8816                         rc = 0;
8817                         break;
8818                 }
8819         }
8820
8821         return rc;
8822 }
8823
8824 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
8825                             int buf_size)
8826 {
8827         int rc;
8828         u32 cmd_flags;
8829         __be32 val;
8830
8831         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8832                 DP(BNX2X_MSG_NVM,
8833                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
8834                    offset, buf_size);
8835                 return -EINVAL;
8836         }
8837
8838         if (offset + buf_size > bp->common.flash_size) {
8839                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8840                                   " buf_size (0x%x) > flash_size (0x%x)\n",
8841                    offset, buf_size, bp->common.flash_size);
8842                 return -EINVAL;
8843         }
8844
8845         /* request access to nvram interface */
8846         rc = bnx2x_acquire_nvram_lock(bp);
8847         if (rc)
8848                 return rc;
8849
8850         /* enable access to nvram interface */
8851         bnx2x_enable_nvram_access(bp);
8852
8853         /* read the first word(s) */
8854         cmd_flags = MCPR_NVM_COMMAND_FIRST;
8855         while ((buf_size > sizeof(u32)) && (rc == 0)) {
8856                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8857                 memcpy(ret_buf, &val, 4);
8858
8859                 /* advance to the next dword */
8860                 offset += sizeof(u32);
8861                 ret_buf += sizeof(u32);
8862                 buf_size -= sizeof(u32);
8863                 cmd_flags = 0;
8864         }
8865
8866         if (rc == 0) {
8867                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8868                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8869                 memcpy(ret_buf, &val, 4);
8870         }
8871
8872         /* disable access to nvram interface */
8873         bnx2x_disable_nvram_access(bp);
8874         bnx2x_release_nvram_lock(bp);
8875
8876         return rc;
8877 }
8878
8879 static int bnx2x_get_eeprom(struct net_device *dev,
8880                             struct ethtool_eeprom *eeprom, u8 *eebuf)
8881 {
8882         struct bnx2x *bp = netdev_priv(dev);
8883         int rc;
8884
8885         if (!netif_running(dev))
8886                 return -EAGAIN;
8887
8888         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8889            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
8890            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8891            eeprom->len, eeprom->len);
8892
8893         /* parameters already validated in ethtool_get_eeprom */
8894
8895         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
8896
8897         return rc;
8898 }
8899
8900 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
8901                                    u32 cmd_flags)
8902 {
8903         int count, i, rc;
8904
8905         /* build the command word */
8906         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
8907
8908         /* need to clear DONE bit separately */
8909         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8910
8911         /* write the data */
8912         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
8913
8914         /* address of the NVRAM to write to */
8915         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8916                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8917
8918         /* issue the write command */
8919         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8920
8921         /* adjust timeout for emulation/FPGA */
8922         count = NVRAM_TIMEOUT_COUNT;
8923         if (CHIP_REV_IS_SLOW(bp))
8924                 count *= 100;
8925
8926         /* wait for completion */
8927         rc = -EBUSY;
8928         for (i = 0; i < count; i++) {
8929                 udelay(5);
8930                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8931                 if (val & MCPR_NVM_COMMAND_DONE) {
8932                         rc = 0;
8933                         break;
8934                 }
8935         }
8936
8937         return rc;
8938 }
8939
8940 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
8941
8942 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
8943                               int buf_size)
8944 {
8945         int rc;
8946         u32 cmd_flags;
8947         u32 align_offset;
8948         __be32 val;
8949
8950         if (offset + buf_size > bp->common.flash_size) {
8951                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8952                                   " buf_size (0x%x) > flash_size (0x%x)\n",
8953                    offset, buf_size, bp->common.flash_size);
8954                 return -EINVAL;
8955         }
8956
8957         /* request access to nvram interface */
8958         rc = bnx2x_acquire_nvram_lock(bp);
8959         if (rc)
8960                 return rc;
8961
8962         /* enable access to nvram interface */
8963         bnx2x_enable_nvram_access(bp);
8964
8965         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
8966         align_offset = (offset & ~0x03);
8967         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
8968
8969         if (rc == 0) {
8970                 val &= ~(0xff << BYTE_OFFSET(offset));
8971                 val |= (*data_buf << BYTE_OFFSET(offset));
8972
8973                 /* nvram data is returned as an array of bytes
8974                  * convert it back to cpu order */
8975                 val = be32_to_cpu(val);
8976
8977                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
8978                                              cmd_flags);
8979         }
8980
8981         /* disable access to nvram interface */
8982         bnx2x_disable_nvram_access(bp);
8983         bnx2x_release_nvram_lock(bp);
8984
8985         return rc;
8986 }
8987
8988 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
8989                              int buf_size)
8990 {
8991         int rc;
8992         u32 cmd_flags;
8993         u32 val;
8994         u32 written_so_far;
8995
8996         if (buf_size == 1)      /* ethtool */
8997                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
8998
8999         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
9000                 DP(BNX2X_MSG_NVM,
9001                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
9002                    offset, buf_size);
9003                 return -EINVAL;
9004         }
9005
9006         if (offset + buf_size > bp->common.flash_size) {
9007                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
9008                                   " buf_size (0x%x) > flash_size (0x%x)\n",
9009                    offset, buf_size, bp->common.flash_size);
9010                 return -EINVAL;
9011         }
9012
9013         /* request access to nvram interface */
9014         rc = bnx2x_acquire_nvram_lock(bp);
9015         if (rc)
9016                 return rc;
9017
9018         /* enable access to nvram interface */
9019         bnx2x_enable_nvram_access(bp);
9020
9021         written_so_far = 0;
9022         cmd_flags = MCPR_NVM_COMMAND_FIRST;
9023         while ((written_so_far < buf_size) && (rc == 0)) {
9024                 if (written_so_far == (buf_size - sizeof(u32)))
9025                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
9026                 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
9027                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
9028                 else if ((offset % NVRAM_PAGE_SIZE) == 0)
9029                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
9030
9031                 memcpy(&val, data_buf, 4);
9032
9033                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
9034
9035                 /* advance to the next dword */
9036                 offset += sizeof(u32);
9037                 data_buf += sizeof(u32);
9038                 written_so_far += sizeof(u32);
9039                 cmd_flags = 0;
9040         }
9041
9042         /* disable access to nvram interface */
9043         bnx2x_disable_nvram_access(bp);
9044         bnx2x_release_nvram_lock(bp);
9045
9046         return rc;
9047 }
9048
9049 static int bnx2x_set_eeprom(struct net_device *dev,
9050                             struct ethtool_eeprom *eeprom, u8 *eebuf)
9051 {
9052         struct bnx2x *bp = netdev_priv(dev);
9053         int rc;
9054
9055         if (!netif_running(dev))
9056                 return -EAGAIN;
9057
9058         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
9059            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
9060            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
9061            eeprom->len, eeprom->len);
9062
9063         /* parameters already validated in ethtool_set_eeprom */
9064
9065         /* If the magic number is PHY (0x00504859) upgrade the PHY FW */
9066         if (eeprom->magic == 0x00504859)
9067                 if (bp->port.pmf) {
9068
9069                         bnx2x_acquire_phy_lock(bp);
9070                         rc = bnx2x_flash_download(bp, BP_PORT(bp),
9071                                              bp->link_params.ext_phy_config,
9072                                              (bp->state != BNX2X_STATE_CLOSED),
9073                                              eebuf, eeprom->len);
9074                         if ((bp->state == BNX2X_STATE_OPEN) ||
9075                             (bp->state == BNX2X_STATE_DISABLED)) {
9076                                 rc |= bnx2x_link_reset(&bp->link_params,
9077                                                        &bp->link_vars, 1);
9078                                 rc |= bnx2x_phy_init(&bp->link_params,
9079                                                      &bp->link_vars);
9080                         }
9081                         bnx2x_release_phy_lock(bp);
9082
9083                 } else /* Only the PMF can access the PHY */
9084                         return -EINVAL;
9085         else
9086                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
9087
9088         return rc;
9089 }
9090
9091 static int bnx2x_get_coalesce(struct net_device *dev,
9092                               struct ethtool_coalesce *coal)
9093 {
9094         struct bnx2x *bp = netdev_priv(dev);
9095
9096         memset(coal, 0, sizeof(struct ethtool_coalesce));
9097
9098         coal->rx_coalesce_usecs = bp->rx_ticks;
9099         coal->tx_coalesce_usecs = bp->tx_ticks;
9100
9101         return 0;
9102 }
9103
9104 static int bnx2x_set_coalesce(struct net_device *dev,
9105                               struct ethtool_coalesce *coal)
9106 {
9107         struct bnx2x *bp = netdev_priv(dev);
9108
9109         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
9110         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
9111                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
9112
9113         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
9114         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
9115                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
9116
9117         if (netif_running(dev))
9118                 bnx2x_update_coalesce(bp);
9119
9120         return 0;
9121 }
9122
9123 static void bnx2x_get_ringparam(struct net_device *dev,
9124                                 struct ethtool_ringparam *ering)
9125 {
9126         struct bnx2x *bp = netdev_priv(dev);
9127
9128         ering->rx_max_pending = MAX_RX_AVAIL;
9129         ering->rx_mini_max_pending = 0;
9130         ering->rx_jumbo_max_pending = 0;
9131
9132         ering->rx_pending = bp->rx_ring_size;
9133         ering->rx_mini_pending = 0;
9134         ering->rx_jumbo_pending = 0;
9135
9136         ering->tx_max_pending = MAX_TX_AVAIL;
9137         ering->tx_pending = bp->tx_ring_size;
9138 }
9139
9140 static int bnx2x_set_ringparam(struct net_device *dev,
9141                                struct ethtool_ringparam *ering)
9142 {
9143         struct bnx2x *bp = netdev_priv(dev);
9144         int rc = 0;
9145
9146         if ((ering->rx_pending > MAX_RX_AVAIL) ||
9147             (ering->tx_pending > MAX_TX_AVAIL) ||
9148             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
9149                 return -EINVAL;
9150
9151         bp->rx_ring_size = ering->rx_pending;
9152         bp->tx_ring_size = ering->tx_pending;
9153
9154         if (netif_running(dev)) {
9155                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9156                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
9157         }
9158
9159         return rc;
9160 }
9161
9162 static void bnx2x_get_pauseparam(struct net_device *dev,
9163                                  struct ethtool_pauseparam *epause)
9164 {
9165         struct bnx2x *bp = netdev_priv(dev);
9166
9167         epause->autoneg = (bp->link_params.req_flow_ctrl ==
9168                            BNX2X_FLOW_CTRL_AUTO) &&
9169                           (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
9170
9171         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
9172                             BNX2X_FLOW_CTRL_RX);
9173         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
9174                             BNX2X_FLOW_CTRL_TX);
9175
9176         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
9177            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
9178            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
9179 }
9180
9181 static int bnx2x_set_pauseparam(struct net_device *dev,
9182                                 struct ethtool_pauseparam *epause)
9183 {
9184         struct bnx2x *bp = netdev_priv(dev);
9185
9186         if (IS_E1HMF(bp))
9187                 return 0;
9188
9189         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
9190            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
9191            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
9192
9193         bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
9194
9195         if (epause->rx_pause)
9196                 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_RX;
9197
9198         if (epause->tx_pause)
9199                 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_TX;
9200
9201         if (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
9202                 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
9203
9204         if (epause->autoneg) {
9205                 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
9206                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
9207                         return -EINVAL;
9208                 }
9209
9210                 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
9211                         bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
9212         }
9213
9214         DP(NETIF_MSG_LINK,
9215            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
9216
9217         if (netif_running(dev)) {
9218                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
9219                 bnx2x_link_set(bp);
9220         }
9221
9222         return 0;
9223 }
9224
9225 static int bnx2x_set_flags(struct net_device *dev, u32 data)
9226 {
9227         struct bnx2x *bp = netdev_priv(dev);
9228         int changed = 0;
9229         int rc = 0;
9230
9231         /* TPA requires Rx CSUM offloading */
9232         if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
9233                 if (!(dev->features & NETIF_F_LRO)) {
9234                         dev->features |= NETIF_F_LRO;
9235                         bp->flags |= TPA_ENABLE_FLAG;
9236                         changed = 1;
9237                 }
9238
9239         } else if (dev->features & NETIF_F_LRO) {
9240                 dev->features &= ~NETIF_F_LRO;
9241                 bp->flags &= ~TPA_ENABLE_FLAG;
9242                 changed = 1;
9243         }
9244
9245         if (changed && netif_running(dev)) {
9246                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9247                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
9248         }
9249
9250         return rc;
9251 }
9252
9253 static u32 bnx2x_get_rx_csum(struct net_device *dev)
9254 {
9255         struct bnx2x *bp = netdev_priv(dev);
9256
9257         return bp->rx_csum;
9258 }
9259
9260 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
9261 {
9262         struct bnx2x *bp = netdev_priv(dev);
9263         int rc = 0;
9264
9265         bp->rx_csum = data;
9266
9267         /* Disable TPA, when Rx CSUM is disabled. Otherwise all
9268            TPA'ed packets will be discarded due to wrong TCP CSUM */
9269         if (!data) {
9270                 u32 flags = ethtool_op_get_flags(dev);
9271
9272                 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
9273         }
9274
9275         return rc;
9276 }
9277
9278 static int bnx2x_set_tso(struct net_device *dev, u32 data)
9279 {
9280         if (data) {
9281                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9282                 dev->features |= NETIF_F_TSO6;
9283         } else {
9284                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
9285                 dev->features &= ~NETIF_F_TSO6;
9286         }
9287
9288         return 0;
9289 }
9290
9291 static const struct {
9292         char string[ETH_GSTRING_LEN];
9293 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
9294         { "register_test (offline)" },
9295         { "memory_test (offline)" },
9296         { "loopback_test (offline)" },
9297         { "nvram_test (online)" },
9298         { "interrupt_test (online)" },
9299         { "link_test (online)" },
9300         { "idle check (online)" }
9301 };
9302
9303 static int bnx2x_self_test_count(struct net_device *dev)
9304 {
9305         return BNX2X_NUM_TESTS;
9306 }
9307
9308 static int bnx2x_test_registers(struct bnx2x *bp)
9309 {
9310         int idx, i, rc = -ENODEV;
9311         u32 wr_val = 0;
9312         int port = BP_PORT(bp);
9313         static const struct {
9314                 u32  offset0;
9315                 u32  offset1;
9316                 u32  mask;
9317         } reg_tbl[] = {
9318 /* 0 */         { BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
9319                 { DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
9320                 { HC_REG_AGG_INT_0,                    4, 0x000003ff },
9321                 { PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
9322                 { PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
9323                 { PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
9324                 { PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
9325                 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
9326                 { PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
9327                 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
9328 /* 10 */        { PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
9329                 { QM_REG_CONNNUM_0,                    4, 0x000fffff },
9330                 { TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
9331                 { SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
9332                 { SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
9333                 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
9334                 { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
9335                 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
9336                 { NIG_REG_EGRESS_MNG0_FIFO,           20, 0xffffffff },
9337                 { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
9338 /* 20 */        { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
9339                 { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
9340                 { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
9341                 { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
9342                 { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
9343                 { NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
9344                 { NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
9345                 { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
9346                 { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
9347                 { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
9348 /* 30 */        { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
9349                 { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
9350                 { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
9351                 { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
9352                 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
9353                 { NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
9354                 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
9355                 { NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },
9356
9357                 { 0xffffffff, 0, 0x00000000 }
9358         };
9359
9360         if (!netif_running(bp->dev))
9361                 return rc;
9362
9363         /* Repeat the test twice:
9364            First by writing 0x00000000, second by writing 0xffffffff */
9365         for (idx = 0; idx < 2; idx++) {
9366
9367                 switch (idx) {
9368                 case 0:
9369                         wr_val = 0;
9370                         break;
9371                 case 1:
9372                         wr_val = 0xffffffff;
9373                         break;
9374                 }
9375
9376                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
9377                         u32 offset, mask, save_val, val;
9378
9379                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
9380                         mask = reg_tbl[i].mask;
9381
9382                         save_val = REG_RD(bp, offset);
9383
9384                         REG_WR(bp, offset, wr_val);
9385                         val = REG_RD(bp, offset);
9386
9387                         /* Restore the original register's value */
9388                         REG_WR(bp, offset, save_val);
9389
9390                         /* verify that value is as expected value */
9391                         if ((val & mask) != (wr_val & mask))
9392                                 goto test_reg_exit;
9393                 }
9394         }
9395
9396         rc = 0;
9397
9398 test_reg_exit:
9399         return rc;
9400 }
9401
9402 static int bnx2x_test_memory(struct bnx2x *bp)
9403 {
9404         int i, j, rc = -ENODEV;
9405         u32 val;
9406         static const struct {
9407                 u32 offset;
9408                 int size;
9409         } mem_tbl[] = {
9410                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
9411                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
9412                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
9413                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
9414                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
9415                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
9416                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
9417
9418                 { 0xffffffff, 0 }
9419         };
9420         static const struct {
9421                 char *name;
9422                 u32 offset;
9423                 u32 e1_mask;
9424                 u32 e1h_mask;
9425         } prty_tbl[] = {
9426                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0 },
9427                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2 },
9428                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0 },
9429                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0 },
9430                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0 },
9431                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0 },
9432
9433                 { NULL, 0xffffffff, 0, 0 }
9434         };
9435
9436         if (!netif_running(bp->dev))
9437                 return rc;
9438
9439         /* Go through all the memories */
9440         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
9441                 for (j = 0; j < mem_tbl[i].size; j++)
9442                         REG_RD(bp, mem_tbl[i].offset + j*4);
9443
9444         /* Check the parity status */
9445         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
9446                 val = REG_RD(bp, prty_tbl[i].offset);
9447                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
9448                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
9449                         DP(NETIF_MSG_HW,
9450                            "%s is 0x%x\n", prty_tbl[i].name, val);
9451                         goto test_mem_exit;
9452                 }
9453         }
9454
9455         rc = 0;
9456
9457 test_mem_exit:
9458         return rc;
9459 }
9460
9461 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
9462 {
9463         int cnt = 1000;
9464
9465         if (link_up)
9466                 while (bnx2x_link_test(bp) && cnt--)
9467                         msleep(10);
9468 }
9469
9470 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
9471 {
9472         unsigned int pkt_size, num_pkts, i;
9473         struct sk_buff *skb;
9474         unsigned char *packet;
9475         struct bnx2x_fastpath *fp = &bp->fp[0];
9476         u16 tx_start_idx, tx_idx;
9477         u16 rx_start_idx, rx_idx;
9478         u16 pkt_prod;
9479         struct sw_tx_bd *tx_buf;
9480         struct eth_tx_bd *tx_bd;
9481         dma_addr_t mapping;
9482         union eth_rx_cqe *cqe;
9483         u8 cqe_fp_flags;
9484         struct sw_rx_bd *rx_buf;
9485         u16 len;
9486         int rc = -ENODEV;
9487
9488         /* check the loopback mode */
9489         switch (loopback_mode) {
9490         case BNX2X_PHY_LOOPBACK:
9491                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10)
9492                         return -EINVAL;
9493                 break;
9494         case BNX2X_MAC_LOOPBACK:
9495                 bp->link_params.loopback_mode = LOOPBACK_BMAC;
9496                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
9497                 break;
9498         default:
9499                 return -EINVAL;
9500         }
9501
9502         /* prepare the loopback packet */
9503         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
9504                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
9505         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
9506         if (!skb) {
9507                 rc = -ENOMEM;
9508                 goto test_loopback_exit;
9509         }
9510         packet = skb_put(skb, pkt_size);
9511         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
9512         memset(packet + ETH_ALEN, 0, (ETH_HLEN - ETH_ALEN));
9513         for (i = ETH_HLEN; i < pkt_size; i++)
9514                 packet[i] = (unsigned char) (i & 0xff);
9515
9516         /* send the loopback packet */
9517         num_pkts = 0;
9518         tx_start_idx = le16_to_cpu(*fp->tx_cons_sb);
9519         rx_start_idx = le16_to_cpu(*fp->rx_cons_sb);
9520
9521         pkt_prod = fp->tx_pkt_prod++;
9522         tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
9523         tx_buf->first_bd = fp->tx_bd_prod;
9524         tx_buf->skb = skb;
9525
9526         tx_bd = &fp->tx_desc_ring[TX_BD(fp->tx_bd_prod)];
9527         mapping = pci_map_single(bp->pdev, skb->data,
9528                                  skb_headlen(skb), PCI_DMA_TODEVICE);
9529         tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9530         tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9531         tx_bd->nbd = cpu_to_le16(1);
9532         tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9533         tx_bd->vlan = cpu_to_le16(pkt_prod);
9534         tx_bd->bd_flags.as_bitfield = (ETH_TX_BD_FLAGS_START_BD |
9535                                        ETH_TX_BD_FLAGS_END_BD);
9536         tx_bd->general_data = ((UNICAST_ADDRESS <<
9537                                 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT) | 1);
9538
9539         wmb();
9540
9541         le16_add_cpu(&fp->hw_tx_prods->bds_prod, 1);
9542         mb(); /* FW restriction: must not reorder writing nbd and packets */
9543         le32_add_cpu(&fp->hw_tx_prods->packets_prod, 1);
9544         DOORBELL(bp, fp->index, 0);
9545
9546         mmiowb();
9547
9548         num_pkts++;
9549         fp->tx_bd_prod++;
9550         bp->dev->trans_start = jiffies;
9551
9552         udelay(100);
9553
9554         tx_idx = le16_to_cpu(*fp->tx_cons_sb);
9555         if (tx_idx != tx_start_idx + num_pkts)
9556                 goto test_loopback_exit;
9557
9558         rx_idx = le16_to_cpu(*fp->rx_cons_sb);
9559         if (rx_idx != rx_start_idx + num_pkts)
9560                 goto test_loopback_exit;
9561
9562         cqe = &fp->rx_comp_ring[RCQ_BD(fp->rx_comp_cons)];
9563         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
9564         if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
9565                 goto test_loopback_rx_exit;
9566
9567         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
9568         if (len != pkt_size)
9569                 goto test_loopback_rx_exit;
9570
9571         rx_buf = &fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)];
9572         skb = rx_buf->skb;
9573         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
9574         for (i = ETH_HLEN; i < pkt_size; i++)
9575                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
9576                         goto test_loopback_rx_exit;
9577
9578         rc = 0;
9579
9580 test_loopback_rx_exit:
9581
9582         fp->rx_bd_cons = NEXT_RX_IDX(fp->rx_bd_cons);
9583         fp->rx_bd_prod = NEXT_RX_IDX(fp->rx_bd_prod);
9584         fp->rx_comp_cons = NEXT_RCQ_IDX(fp->rx_comp_cons);
9585         fp->rx_comp_prod = NEXT_RCQ_IDX(fp->rx_comp_prod);
9586
9587         /* Update producers */
9588         bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
9589                              fp->rx_sge_prod);
9590
9591 test_loopback_exit:
9592         bp->link_params.loopback_mode = LOOPBACK_NONE;
9593
9594         return rc;
9595 }
9596
9597 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
9598 {
9599         int rc = 0, res;
9600
9601         if (!netif_running(bp->dev))
9602                 return BNX2X_LOOPBACK_FAILED;
9603
9604         bnx2x_netif_stop(bp, 1);
9605         bnx2x_acquire_phy_lock(bp);
9606
9607         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
9608         if (res) {
9609                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
9610                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
9611         }
9612
9613         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
9614         if (res) {
9615                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
9616                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
9617         }
9618
9619         bnx2x_release_phy_lock(bp);
9620         bnx2x_netif_start(bp);
9621
9622         return rc;
9623 }
9624
9625 #define CRC32_RESIDUAL                  0xdebb20e3
9626
9627 static int bnx2x_test_nvram(struct bnx2x *bp)
9628 {
9629         static const struct {
9630                 int offset;
9631                 int size;
9632         } nvram_tbl[] = {
9633                 {     0,  0x14 }, /* bootstrap */
9634                 {  0x14,  0xec }, /* dir */
9635                 { 0x100, 0x350 }, /* manuf_info */
9636                 { 0x450,  0xf0 }, /* feature_info */
9637                 { 0x640,  0x64 }, /* upgrade_key_info */
9638                 { 0x6a4,  0x64 },
9639                 { 0x708,  0x70 }, /* manuf_key_info */
9640                 { 0x778,  0x70 },
9641                 {     0,     0 }
9642         };
9643         __be32 buf[0x350 / 4];
9644         u8 *data = (u8 *)buf;
9645         int i, rc;
9646         u32 magic, csum;
9647
9648         rc = bnx2x_nvram_read(bp, 0, data, 4);
9649         if (rc) {
9650                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
9651                 goto test_nvram_exit;
9652         }
9653
9654         magic = be32_to_cpu(buf[0]);
9655         if (magic != 0x669955aa) {
9656                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
9657                 rc = -ENODEV;
9658                 goto test_nvram_exit;
9659         }
9660
9661         for (i = 0; nvram_tbl[i].size; i++) {
9662
9663                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
9664                                       nvram_tbl[i].size);
9665                 if (rc) {
9666                         DP(NETIF_MSG_PROBE,
9667                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
9668                         goto test_nvram_exit;
9669                 }
9670
9671                 csum = ether_crc_le(nvram_tbl[i].size, data);
9672                 if (csum != CRC32_RESIDUAL) {
9673                         DP(NETIF_MSG_PROBE,
9674                            "nvram_tbl[%d] csum value (0x%08x)\n", i, csum);
9675                         rc = -ENODEV;
9676                         goto test_nvram_exit;
9677                 }
9678         }
9679
9680 test_nvram_exit:
9681         return rc;
9682 }
9683
9684 static int bnx2x_test_intr(struct bnx2x *bp)
9685 {
9686         struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
9687         int i, rc;
9688
9689         if (!netif_running(bp->dev))
9690                 return -ENODEV;
9691
9692         config->hdr.length = 0;
9693         if (CHIP_IS_E1(bp))
9694                 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
9695         else
9696                 config->hdr.offset = BP_FUNC(bp);
9697         config->hdr.client_id = bp->fp->cl_id;
9698         config->hdr.reserved1 = 0;
9699
9700         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
9701                            U64_HI(bnx2x_sp_mapping(bp, mac_config)),
9702                            U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
9703         if (rc == 0) {
9704                 bp->set_mac_pending++;
9705                 for (i = 0; i < 10; i++) {
9706                         if (!bp->set_mac_pending)
9707                                 break;
9708                         msleep_interruptible(10);
9709                 }
9710                 if (i == 10)
9711                         rc = -ENODEV;
9712         }
9713
9714         return rc;
9715 }
9716
9717 static void bnx2x_self_test(struct net_device *dev,
9718                             struct ethtool_test *etest, u64 *buf)
9719 {
9720         struct bnx2x *bp = netdev_priv(dev);
9721
9722         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
9723
9724         if (!netif_running(dev))
9725                 return;
9726
9727         /* offline tests are not supported in MF mode */
9728         if (IS_E1HMF(bp))
9729                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
9730
9731         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9732                 int port = BP_PORT(bp);
9733                 u32 val;
9734                 u8 link_up;
9735
9736                 /* save current value of input enable for TX port IF */
9737                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
9738                 /* disable input for TX port IF */
9739                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
9740
9741                 link_up = bp->link_vars.link_up;
9742                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9743                 bnx2x_nic_load(bp, LOAD_DIAG);
9744                 /* wait until link state is restored */
9745                 bnx2x_wait_for_link(bp, link_up);
9746
9747                 if (bnx2x_test_registers(bp) != 0) {
9748                         buf[0] = 1;
9749                         etest->flags |= ETH_TEST_FL_FAILED;
9750                 }
9751                 if (bnx2x_test_memory(bp) != 0) {
9752                         buf[1] = 1;
9753                         etest->flags |= ETH_TEST_FL_FAILED;
9754                 }
9755                 buf[2] = bnx2x_test_loopback(bp, link_up);
9756                 if (buf[2] != 0)
9757                         etest->flags |= ETH_TEST_FL_FAILED;
9758
9759                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9760
9761                 /* restore input for TX port IF */
9762                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
9763
9764                 bnx2x_nic_load(bp, LOAD_NORMAL);
9765                 /* wait until link state is restored */
9766                 bnx2x_wait_for_link(bp, link_up);
9767         }
9768         if (bnx2x_test_nvram(bp) != 0) {
9769                 buf[3] = 1;
9770                 etest->flags |= ETH_TEST_FL_FAILED;
9771         }
9772         if (bnx2x_test_intr(bp) != 0) {
9773                 buf[4] = 1;
9774                 etest->flags |= ETH_TEST_FL_FAILED;
9775         }
9776         if (bp->port.pmf)
9777                 if (bnx2x_link_test(bp) != 0) {
9778                         buf[5] = 1;
9779                         etest->flags |= ETH_TEST_FL_FAILED;
9780                 }
9781
9782 #ifdef BNX2X_EXTRA_DEBUG
9783         bnx2x_panic_dump(bp);
9784 #endif
9785 }
9786
9787 static const struct {
9788         long offset;
9789         int size;
9790         u8 string[ETH_GSTRING_LEN];
9791 } bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
9792 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
9793         { Q_STATS_OFFSET32(error_bytes_received_hi),
9794                                                 8, "[%d]: rx_error_bytes" },
9795         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
9796                                                 8, "[%d]: rx_ucast_packets" },
9797         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
9798                                                 8, "[%d]: rx_mcast_packets" },
9799         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
9800                                                 8, "[%d]: rx_bcast_packets" },
9801         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
9802         { Q_STATS_OFFSET32(rx_err_discard_pkt),
9803                                          4, "[%d]: rx_phy_ip_err_discards"},
9804         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
9805                                          4, "[%d]: rx_skb_alloc_discard" },
9806         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
9807
9808 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
9809         { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
9810                                                         8, "[%d]: tx_packets" }
9811 };
9812
9813 static const struct {
9814         long offset;
9815         int size;
9816         u32 flags;
9817 #define STATS_FLAGS_PORT                1
9818 #define STATS_FLAGS_FUNC                2
9819 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
9820         u8 string[ETH_GSTRING_LEN];
9821 } bnx2x_stats_arr[BNX2X_NUM_STATS] = {
9822 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
9823                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
9824         { STATS_OFFSET32(error_bytes_received_hi),
9825                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
9826         { STATS_OFFSET32(total_unicast_packets_received_hi),
9827                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
9828         { STATS_OFFSET32(total_multicast_packets_received_hi),
9829                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
9830         { STATS_OFFSET32(total_broadcast_packets_received_hi),
9831                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
9832         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
9833                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
9834         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
9835                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
9836         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
9837                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
9838         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
9839                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
9840 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
9841                                 8, STATS_FLAGS_PORT, "rx_fragments" },
9842         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
9843                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
9844         { STATS_OFFSET32(no_buff_discard_hi),
9845                                 8, STATS_FLAGS_BOTH, "rx_discards" },
9846         { STATS_OFFSET32(mac_filter_discard),
9847                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
9848         { STATS_OFFSET32(xxoverflow_discard),
9849                                 4, STATS_FLAGS_PORT, "rx_fw_discards" },
9850         { STATS_OFFSET32(brb_drop_hi),
9851                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
9852         { STATS_OFFSET32(brb_truncate_hi),
9853                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
9854         { STATS_OFFSET32(pause_frames_received_hi),
9855                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
9856         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
9857                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
9858         { STATS_OFFSET32(nig_timer_max),
9859                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
9860 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
9861                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
9862         { STATS_OFFSET32(rx_skb_alloc_failed),
9863                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
9864         { STATS_OFFSET32(hw_csum_err),
9865                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
9866
9867         { STATS_OFFSET32(total_bytes_transmitted_hi),
9868                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
9869         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
9870                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
9871         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
9872                                 8, STATS_FLAGS_BOTH, "tx_packets" },
9873         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
9874                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
9875         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
9876                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
9877         { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
9878                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
9879         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
9880                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
9881 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
9882                                 8, STATS_FLAGS_PORT, "tx_deferred" },
9883         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
9884                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
9885         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
9886                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
9887         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
9888                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
9889         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
9890                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
9891         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
9892                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
9893         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
9894                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
9895         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
9896                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
9897         { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
9898                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
9899         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
9900                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
9901 /* 40 */{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
9902                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
9903         { STATS_OFFSET32(pause_frames_sent_hi),
9904                                 8, STATS_FLAGS_PORT, "tx_pause_frames" }
9905 };
9906
9907 #define IS_PORT_STAT(i) \
9908         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
9909 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
9910 #define IS_E1HMF_MODE_STAT(bp) \
9911                         (IS_E1HMF(bp) && !(bp->msglevel & BNX2X_MSG_STATS))
9912
9913 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
9914 {
9915         struct bnx2x *bp = netdev_priv(dev);
9916         int i, j, k;
9917
9918         switch (stringset) {
9919         case ETH_SS_STATS:
9920                 if (is_multi(bp)) {
9921                         k = 0;
9922                         for_each_queue(bp, i) {
9923                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
9924                                         sprintf(buf + (k + j)*ETH_GSTRING_LEN,
9925                                                 bnx2x_q_stats_arr[j].string, i);
9926                                 k += BNX2X_NUM_Q_STATS;
9927                         }
9928                         if (IS_E1HMF_MODE_STAT(bp))
9929                                 break;
9930                         for (j = 0; j < BNX2X_NUM_STATS; j++)
9931                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
9932                                        bnx2x_stats_arr[j].string);
9933                 } else {
9934                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
9935                                 if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
9936                                         continue;
9937                                 strcpy(buf + j*ETH_GSTRING_LEN,
9938                                        bnx2x_stats_arr[i].string);
9939                                 j++;
9940                         }
9941                 }
9942                 break;
9943
9944         case ETH_SS_TEST:
9945                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
9946                 break;
9947         }
9948 }
9949
9950 static int bnx2x_get_stats_count(struct net_device *dev)
9951 {
9952         struct bnx2x *bp = netdev_priv(dev);
9953         int i, num_stats;
9954
9955         if (is_multi(bp)) {
9956                 num_stats = BNX2X_NUM_Q_STATS * BNX2X_NUM_QUEUES(bp);
9957                 if (!IS_E1HMF_MODE_STAT(bp))
9958                         num_stats += BNX2X_NUM_STATS;
9959         } else {
9960                 if (IS_E1HMF_MODE_STAT(bp)) {
9961                         num_stats = 0;
9962                         for (i = 0; i < BNX2X_NUM_STATS; i++)
9963                                 if (IS_FUNC_STAT(i))
9964                                         num_stats++;
9965                 } else
9966                         num_stats = BNX2X_NUM_STATS;
9967         }
9968
9969         return num_stats;
9970 }
9971
9972 static void bnx2x_get_ethtool_stats(struct net_device *dev,
9973                                     struct ethtool_stats *stats, u64 *buf)
9974 {
9975         struct bnx2x *bp = netdev_priv(dev);
9976         u32 *hw_stats, *offset;
9977         int i, j, k;
9978
9979         if (is_multi(bp)) {
9980                 k = 0;
9981                 for_each_queue(bp, i) {
9982                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
9983                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
9984                                 if (bnx2x_q_stats_arr[j].size == 0) {
9985                                         /* skip this counter */
9986                                         buf[k + j] = 0;
9987                                         continue;
9988                                 }
9989                                 offset = (hw_stats +
9990                                           bnx2x_q_stats_arr[j].offset);
9991                                 if (bnx2x_q_stats_arr[j].size == 4) {
9992                                         /* 4-byte counter */
9993                                         buf[k + j] = (u64) *offset;
9994                                         continue;
9995                                 }
9996                                 /* 8-byte counter */
9997                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
9998                         }
9999                         k += BNX2X_NUM_Q_STATS;
10000                 }
10001                 if (IS_E1HMF_MODE_STAT(bp))
10002                         return;
10003                 hw_stats = (u32 *)&bp->eth_stats;
10004                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
10005                         if (bnx2x_stats_arr[j].size == 0) {
10006                                 /* skip this counter */
10007                                 buf[k + j] = 0;
10008                                 continue;
10009                         }
10010                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
10011                         if (bnx2x_stats_arr[j].size == 4) {
10012                                 /* 4-byte counter */
10013                                 buf[k + j] = (u64) *offset;
10014                                 continue;
10015                         }
10016                         /* 8-byte counter */
10017                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
10018                 }
10019         } else {
10020                 hw_stats = (u32 *)&bp->eth_stats;
10021                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
10022                         if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
10023                                 continue;
10024                         if (bnx2x_stats_arr[i].size == 0) {
10025                                 /* skip this counter */
10026                                 buf[j] = 0;
10027                                 j++;
10028                                 continue;
10029                         }
10030                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
10031                         if (bnx2x_stats_arr[i].size == 4) {
10032                                 /* 4-byte counter */
10033                                 buf[j] = (u64) *offset;
10034                                 j++;
10035                                 continue;
10036                         }
10037                         /* 8-byte counter */
10038                         buf[j] = HILO_U64(*offset, *(offset + 1));
10039                         j++;
10040                 }
10041         }
10042 }
10043
10044 static int bnx2x_phys_id(struct net_device *dev, u32 data)
10045 {
10046         struct bnx2x *bp = netdev_priv(dev);
10047         int port = BP_PORT(bp);
10048         int i;
10049
10050         if (!netif_running(dev))
10051                 return 0;
10052
10053         if (!bp->port.pmf)
10054                 return 0;
10055
10056         if (data == 0)
10057                 data = 2;
10058
10059         for (i = 0; i < (data * 2); i++) {
10060                 if ((i % 2) == 0)
10061                         bnx2x_set_led(bp, port, LED_MODE_OPER, SPEED_1000,
10062                                       bp->link_params.hw_led_mode,
10063                                       bp->link_params.chip_id);
10064                 else
10065                         bnx2x_set_led(bp, port, LED_MODE_OFF, 0,
10066                                       bp->link_params.hw_led_mode,
10067                                       bp->link_params.chip_id);
10068
10069                 msleep_interruptible(500);
10070                 if (signal_pending(current))
10071                         break;
10072         }
10073
10074         if (bp->link_vars.link_up)
10075                 bnx2x_set_led(bp, port, LED_MODE_OPER,
10076                               bp->link_vars.line_speed,
10077                               bp->link_params.hw_led_mode,
10078                               bp->link_params.chip_id);
10079
10080         return 0;
10081 }
10082
10083 static struct ethtool_ops bnx2x_ethtool_ops = {
10084         .get_settings           = bnx2x_get_settings,
10085         .set_settings           = bnx2x_set_settings,
10086         .get_drvinfo            = bnx2x_get_drvinfo,
10087         .get_regs_len           = bnx2x_get_regs_len,
10088         .get_regs               = bnx2x_get_regs,
10089         .get_wol                = bnx2x_get_wol,
10090         .set_wol                = bnx2x_set_wol,
10091         .get_msglevel           = bnx2x_get_msglevel,
10092         .set_msglevel           = bnx2x_set_msglevel,
10093         .nway_reset             = bnx2x_nway_reset,
10094         .get_link               = bnx2x_get_link,
10095         .get_eeprom_len         = bnx2x_get_eeprom_len,
10096         .get_eeprom             = bnx2x_get_eeprom,
10097         .set_eeprom             = bnx2x_set_eeprom,
10098         .get_coalesce           = bnx2x_get_coalesce,
10099         .set_coalesce           = bnx2x_set_coalesce,
10100         .get_ringparam          = bnx2x_get_ringparam,
10101         .set_ringparam          = bnx2x_set_ringparam,
10102         .get_pauseparam         = bnx2x_get_pauseparam,
10103         .set_pauseparam         = bnx2x_set_pauseparam,
10104         .get_rx_csum            = bnx2x_get_rx_csum,
10105         .set_rx_csum            = bnx2x_set_rx_csum,
10106         .get_tx_csum            = ethtool_op_get_tx_csum,
10107         .set_tx_csum            = ethtool_op_set_tx_hw_csum,
10108         .set_flags              = bnx2x_set_flags,
10109         .get_flags              = ethtool_op_get_flags,
10110         .get_sg                 = ethtool_op_get_sg,
10111         .set_sg                 = ethtool_op_set_sg,
10112         .get_tso                = ethtool_op_get_tso,
10113         .set_tso                = bnx2x_set_tso,
10114         .self_test_count        = bnx2x_self_test_count,
10115         .self_test              = bnx2x_self_test,
10116         .get_strings            = bnx2x_get_strings,
10117         .phys_id                = bnx2x_phys_id,
10118         .get_stats_count        = bnx2x_get_stats_count,
10119         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
10120 };
10121
10122 /* end of ethtool_ops */
10123
10124 /****************************************************************************
10125 * General service functions
10126 ****************************************************************************/
10127
10128 static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
10129 {
10130         u16 pmcsr;
10131
10132         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
10133
10134         switch (state) {
10135         case PCI_D0:
10136                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
10137                                       ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
10138                                        PCI_PM_CTRL_PME_STATUS));
10139
10140                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
10141                         /* delay required during transition out of D3hot */
10142                         msleep(20);
10143                 break;
10144
10145         case PCI_D3hot:
10146                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10147                 pmcsr |= 3;
10148
10149                 if (bp->wol)
10150                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
10151
10152                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
10153                                       pmcsr);
10154
10155                 /* No more memory access after this point until
10156                 * device is brought back to D0.
10157                 */
10158                 break;
10159
10160         default:
10161                 return -EINVAL;
10162         }
10163         return 0;
10164 }
10165
10166 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
10167 {
10168         u16 rx_cons_sb;
10169
10170         /* Tell compiler that status block fields can change */
10171         barrier();
10172         rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
10173         if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
10174                 rx_cons_sb++;
10175         return (fp->rx_comp_cons != rx_cons_sb);
10176 }
10177
10178 /*
10179  * net_device service functions
10180  */
10181
10182 static int bnx2x_poll(struct napi_struct *napi, int budget)
10183 {
10184         struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
10185                                                  napi);
10186         struct bnx2x *bp = fp->bp;
10187         int work_done = 0;
10188
10189 #ifdef BNX2X_STOP_ON_ERROR
10190         if (unlikely(bp->panic))
10191                 goto poll_panic;
10192 #endif
10193
10194         prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
10195         prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
10196         prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
10197
10198         bnx2x_update_fpsb_idx(fp);
10199
10200         if (bnx2x_has_tx_work(fp))
10201                 bnx2x_tx_int(fp);
10202
10203         if (bnx2x_has_rx_work(fp)) {
10204                 work_done = bnx2x_rx_int(fp, budget);
10205
10206                 /* must not complete if we consumed full budget */
10207                 if (work_done >= budget)
10208                         goto poll_again;
10209         }
10210
10211         /* BNX2X_HAS_WORK() reads the status block, thus we need to
10212          * ensure that status block indices have been actually read
10213          * (bnx2x_update_fpsb_idx) prior to this check (BNX2X_HAS_WORK)
10214          * so that we won't write the "newer" value of the status block to IGU
10215          * (if there was a DMA right after BNX2X_HAS_WORK and
10216          * if there is no rmb, the memory reading (bnx2x_update_fpsb_idx)
10217          * may be postponed to right before bnx2x_ack_sb). In this case
10218          * there will never be another interrupt until there is another update
10219          * of the status block, while there is still unhandled work.
10220          */
10221         rmb();
10222
10223         if (!BNX2X_HAS_WORK(fp)) {
10224 #ifdef BNX2X_STOP_ON_ERROR
10225 poll_panic:
10226 #endif
10227                 napi_complete(napi);
10228
10229                 bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
10230                              le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
10231                 bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
10232                              le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
10233         }
10234
10235 poll_again:
10236         return work_done;
10237 }
10238
10239
10240 /* we split the first BD into headers and data BDs
10241  * to ease the pain of our fellow microcode engineers
10242  * we use one mapping for both BDs
10243  * So far this has only been observed to happen
10244  * in Other Operating Systems(TM)
10245  */
10246 static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
10247                                    struct bnx2x_fastpath *fp,
10248                                    struct eth_tx_bd **tx_bd, u16 hlen,
10249                                    u16 bd_prod, int nbd)
10250 {
10251         struct eth_tx_bd *h_tx_bd = *tx_bd;
10252         struct eth_tx_bd *d_tx_bd;
10253         dma_addr_t mapping;
10254         int old_len = le16_to_cpu(h_tx_bd->nbytes);
10255
10256         /* first fix first BD */
10257         h_tx_bd->nbd = cpu_to_le16(nbd);
10258         h_tx_bd->nbytes = cpu_to_le16(hlen);
10259
10260         DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d "
10261            "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi,
10262            h_tx_bd->addr_lo, h_tx_bd->nbd);
10263
10264         /* now get a new data BD
10265          * (after the pbd) and fill it */
10266         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
10267         d_tx_bd = &fp->tx_desc_ring[bd_prod];
10268
10269         mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
10270                            le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
10271
10272         d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
10273         d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
10274         d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
10275         d_tx_bd->vlan = 0;
10276         /* this marks the BD as one that has no individual mapping
10277          * the FW ignores this flag in a BD not marked start
10278          */
10279         d_tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
10280         DP(NETIF_MSG_TX_QUEUED,
10281            "TSO split data size is %d (%x:%x)\n",
10282            d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
10283
10284         /* update tx_bd for marking the last BD flag */
10285         *tx_bd = d_tx_bd;
10286
10287         return bd_prod;
10288 }
10289
10290 static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
10291 {
10292         if (fix > 0)
10293                 csum = (u16) ~csum_fold(csum_sub(csum,
10294                                 csum_partial(t_header - fix, fix, 0)));
10295
10296         else if (fix < 0)
10297                 csum = (u16) ~csum_fold(csum_add(csum,
10298                                 csum_partial(t_header, -fix, 0)));
10299
10300         return swab16(csum);
10301 }
10302
10303 static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
10304 {
10305         u32 rc;
10306
10307         if (skb->ip_summed != CHECKSUM_PARTIAL)
10308                 rc = XMIT_PLAIN;
10309
10310         else {
10311                 if (skb->protocol == htons(ETH_P_IPV6)) {
10312                         rc = XMIT_CSUM_V6;
10313                         if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
10314                                 rc |= XMIT_CSUM_TCP;
10315
10316                 } else {
10317                         rc = XMIT_CSUM_V4;
10318                         if (ip_hdr(skb)->protocol == IPPROTO_TCP)
10319                                 rc |= XMIT_CSUM_TCP;
10320                 }
10321         }
10322
10323         if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
10324                 rc |= XMIT_GSO_V4;
10325
10326         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
10327                 rc |= XMIT_GSO_V6;
10328
10329         return rc;
10330 }
10331
10332 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
10333 /* check if packet requires linearization (packet is too fragmented)
10334    no need to check fragmentation if page size > 8K (there will be no
10335    violation to FW restrictions) */
10336 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
10337                              u32 xmit_type)
10338 {
10339         int to_copy = 0;
10340         int hlen = 0;
10341         int first_bd_sz = 0;
10342
10343         /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
10344         if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
10345
10346                 if (xmit_type & XMIT_GSO) {
10347                         unsigned short lso_mss = skb_shinfo(skb)->gso_size;
10348                         /* Check if LSO packet needs to be copied:
10349                            3 = 1 (for headers BD) + 2 (for PBD and last BD) */
10350                         int wnd_size = MAX_FETCH_BD - 3;
10351                         /* Number of windows to check */
10352                         int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
10353                         int wnd_idx = 0;
10354                         int frag_idx = 0;
10355                         u32 wnd_sum = 0;
10356
10357                         /* Headers length */
10358                         hlen = (int)(skb_transport_header(skb) - skb->data) +
10359                                 tcp_hdrlen(skb);
10360
10361                         /* Amount of data (w/o headers) on linear part of SKB*/
10362                         first_bd_sz = skb_headlen(skb) - hlen;
10363
10364                         wnd_sum  = first_bd_sz;
10365
10366                         /* Calculate the first sum - it's special */
10367                         for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
10368                                 wnd_sum +=
10369                                         skb_shinfo(skb)->frags[frag_idx].size;
10370
10371                         /* If there was data on linear skb data - check it */
10372                         if (first_bd_sz > 0) {
10373                                 if (unlikely(wnd_sum < lso_mss)) {
10374                                         to_copy = 1;
10375                                         goto exit_lbl;
10376                                 }
10377
10378                                 wnd_sum -= first_bd_sz;
10379                         }
10380
10381                         /* Others are easier: run through the frag list and
10382                            check all windows */
10383                         for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
10384                                 wnd_sum +=
10385                           skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1].size;
10386
10387                                 if (unlikely(wnd_sum < lso_mss)) {
10388                                         to_copy = 1;
10389                                         break;
10390                                 }
10391                                 wnd_sum -=
10392                                         skb_shinfo(skb)->frags[wnd_idx].size;
10393                         }
10394                 } else {
10395                         /* in non-LSO too fragmented packet should always
10396                            be linearized */
10397                         to_copy = 1;
10398                 }
10399         }
10400
10401 exit_lbl:
10402         if (unlikely(to_copy))
10403                 DP(NETIF_MSG_TX_QUEUED,
10404                    "Linearization IS REQUIRED for %s packet. "
10405                    "num_frags %d  hlen %d  first_bd_sz %d\n",
10406                    (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
10407                    skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
10408
10409         return to_copy;
10410 }
10411 #endif
10412
10413 /* called with netif_tx_lock
10414  * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
10415  * netif_wake_queue()
10416  */
10417 static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
10418 {
10419         struct bnx2x *bp = netdev_priv(dev);
10420         struct bnx2x_fastpath *fp;
10421         struct netdev_queue *txq;
10422         struct sw_tx_bd *tx_buf;
10423         struct eth_tx_bd *tx_bd;
10424         struct eth_tx_parse_bd *pbd = NULL;
10425         u16 pkt_prod, bd_prod;
10426         int nbd, fp_index;
10427         dma_addr_t mapping;
10428         u32 xmit_type = bnx2x_xmit_type(bp, skb);
10429         int vlan_off = (bp->e1hov ? 4 : 0);
10430         int i;
10431         u8 hlen = 0;
10432
10433 #ifdef BNX2X_STOP_ON_ERROR
10434         if (unlikely(bp->panic))
10435                 return NETDEV_TX_BUSY;
10436 #endif
10437
10438         fp_index = skb_get_queue_mapping(skb);
10439         txq = netdev_get_tx_queue(dev, fp_index);
10440
10441         fp = &bp->fp[fp_index];
10442
10443         if (unlikely(bnx2x_tx_avail(fp) < (skb_shinfo(skb)->nr_frags + 3))) {
10444                 fp->eth_q_stats.driver_xoff++,
10445                 netif_tx_stop_queue(txq);
10446                 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
10447                 return NETDEV_TX_BUSY;
10448         }
10449
10450         DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x  protocol %x  protocol(%x,%x)"
10451            "  gso type %x  xmit_type %x\n",
10452            skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
10453            ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
10454
10455 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
10456         /* First, check if we need to linearize the skb (due to FW
10457            restrictions). No need to check fragmentation if page size > 8K
10458            (there will be no violation to FW restrictions) */
10459         if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
10460                 /* Statistics of linearization */
10461                 bp->lin_cnt++;
10462                 if (skb_linearize(skb) != 0) {
10463                         DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
10464                            "silently dropping this SKB\n");
10465                         dev_kfree_skb_any(skb);
10466                         return NETDEV_TX_OK;
10467                 }
10468         }
10469 #endif
10470
10471         /*
10472         Please read carefully. First we use one BD which we mark as start,
10473         then for TSO or xsum we have a parsing info BD,
10474         and only then we have the rest of the TSO BDs.
10475         (don't forget to mark the last one as last,
10476         and to unmap only AFTER you write to the BD ...)
10477         And above all, all pdb sizes are in words - NOT DWORDS!
10478         */
10479
10480         pkt_prod = fp->tx_pkt_prod++;
10481         bd_prod = TX_BD(fp->tx_bd_prod);
10482
10483         /* get a tx_buf and first BD */
10484         tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
10485         tx_bd = &fp->tx_desc_ring[bd_prod];
10486
10487         tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
10488         tx_bd->general_data = (UNICAST_ADDRESS <<
10489                                ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
10490         /* header nbd */
10491         tx_bd->general_data |= (1 << ETH_TX_BD_HDR_NBDS_SHIFT);
10492
10493         /* remember the first BD of the packet */
10494         tx_buf->first_bd = fp->tx_bd_prod;
10495         tx_buf->skb = skb;
10496
10497         DP(NETIF_MSG_TX_QUEUED,
10498            "sending pkt %u @%p  next_idx %u  bd %u @%p\n",
10499            pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd);
10500
10501 #ifdef BCM_VLAN
10502         if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb) &&
10503             (bp->flags & HW_VLAN_TX_FLAG)) {
10504                 tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
10505                 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
10506                 vlan_off += 4;
10507         } else
10508 #endif
10509                 tx_bd->vlan = cpu_to_le16(pkt_prod);
10510
10511         if (xmit_type) {
10512                 /* turn on parsing and get a BD */
10513                 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
10514                 pbd = (void *)&fp->tx_desc_ring[bd_prod];
10515
10516                 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
10517         }
10518
10519         if (xmit_type & XMIT_CSUM) {
10520                 hlen = (skb_network_header(skb) - skb->data + vlan_off) / 2;
10521
10522                 /* for now NS flag is not used in Linux */
10523                 pbd->global_data =
10524                         (hlen | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
10525                                  ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
10526
10527                 pbd->ip_hlen = (skb_transport_header(skb) -
10528                                 skb_network_header(skb)) / 2;
10529
10530                 hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
10531
10532                 pbd->total_hlen = cpu_to_le16(hlen);
10533                 hlen = hlen*2 - vlan_off;
10534
10535                 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_TCP_CSUM;
10536
10537                 if (xmit_type & XMIT_CSUM_V4)
10538                         tx_bd->bd_flags.as_bitfield |=
10539                                                 ETH_TX_BD_FLAGS_IP_CSUM;
10540                 else
10541                         tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
10542
10543                 if (xmit_type & XMIT_CSUM_TCP) {
10544                         pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
10545
10546                 } else {
10547                         s8 fix = SKB_CS_OFF(skb); /* signed! */
10548
10549                         pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
10550                         pbd->cs_offset = fix / 2;
10551
10552                         DP(NETIF_MSG_TX_QUEUED,
10553                            "hlen %d  offset %d  fix %d  csum before fix %x\n",
10554                            le16_to_cpu(pbd->total_hlen), pbd->cs_offset, fix,
10555                            SKB_CS(skb));
10556
10557                         /* HW bug: fixup the CSUM */
10558                         pbd->tcp_pseudo_csum =
10559                                 bnx2x_csum_fix(skb_transport_header(skb),
10560                                                SKB_CS(skb), fix);
10561
10562                         DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
10563                            pbd->tcp_pseudo_csum);
10564                 }
10565         }
10566
10567         mapping = pci_map_single(bp->pdev, skb->data,
10568                                  skb_headlen(skb), PCI_DMA_TODEVICE);
10569
10570         tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
10571         tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
10572         nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL) ? 1 : 2);
10573         tx_bd->nbd = cpu_to_le16(nbd);
10574         tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
10575
10576         DP(NETIF_MSG_TX_QUEUED, "first bd @%p  addr (%x:%x)  nbd %d"
10577            "  nbytes %d  flags %x  vlan %x\n",
10578            tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, le16_to_cpu(tx_bd->nbd),
10579            le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield,
10580            le16_to_cpu(tx_bd->vlan));
10581
10582         if (xmit_type & XMIT_GSO) {
10583
10584                 DP(NETIF_MSG_TX_QUEUED,
10585                    "TSO packet len %d  hlen %d  total len %d  tso size %d\n",
10586                    skb->len, hlen, skb_headlen(skb),
10587                    skb_shinfo(skb)->gso_size);
10588
10589                 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
10590
10591                 if (unlikely(skb_headlen(skb) > hlen))
10592                         bd_prod = bnx2x_tx_split(bp, fp, &tx_bd, hlen,
10593                                                  bd_prod, ++nbd);
10594
10595                 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
10596                 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
10597                 pbd->tcp_flags = pbd_tcp_flags(skb);
10598
10599                 if (xmit_type & XMIT_GSO_V4) {
10600                         pbd->ip_id = swab16(ip_hdr(skb)->id);
10601                         pbd->tcp_pseudo_csum =
10602                                 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
10603                                                           ip_hdr(skb)->daddr,
10604                                                           0, IPPROTO_TCP, 0));
10605
10606                 } else
10607                         pbd->tcp_pseudo_csum =
10608                                 swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
10609                                                         &ipv6_hdr(skb)->daddr,
10610                                                         0, IPPROTO_TCP, 0));
10611
10612                 pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
10613         }
10614
10615         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
10616                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
10617
10618                 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
10619                 tx_bd = &fp->tx_desc_ring[bd_prod];
10620
10621                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
10622                                        frag->size, PCI_DMA_TODEVICE);
10623
10624                 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
10625                 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
10626                 tx_bd->nbytes = cpu_to_le16(frag->size);
10627                 tx_bd->vlan = cpu_to_le16(pkt_prod);
10628                 tx_bd->bd_flags.as_bitfield = 0;
10629
10630                 DP(NETIF_MSG_TX_QUEUED,
10631                    "frag %d  bd @%p  addr (%x:%x)  nbytes %d  flags %x\n",
10632                    i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo,
10633                    le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield);
10634         }
10635
10636         /* now at last mark the BD as the last BD */
10637         tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
10638
10639         DP(NETIF_MSG_TX_QUEUED, "last bd @%p  flags %x\n",
10640            tx_bd, tx_bd->bd_flags.as_bitfield);
10641
10642         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
10643
10644         /* now send a tx doorbell, counting the next BD
10645          * if the packet contains or ends with it
10646          */
10647         if (TX_BD_POFF(bd_prod) < nbd)
10648                 nbd++;
10649
10650         if (pbd)
10651                 DP(NETIF_MSG_TX_QUEUED,
10652                    "PBD @%p  ip_data %x  ip_hlen %u  ip_id %u  lso_mss %u"
10653                    "  tcp_flags %x  xsum %x  seq %u  hlen %u\n",
10654                    pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
10655                    pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
10656                    pbd->tcp_send_seq, le16_to_cpu(pbd->total_hlen));
10657
10658         DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d  bd %u\n", nbd, bd_prod);
10659
10660         /*
10661          * Make sure that the BD data is updated before updating the producer
10662          * since FW might read the BD right after the producer is updated.
10663          * This is only applicable for weak-ordered memory model archs such
10664          * as IA-64. The following barrier is also mandatory since FW will
10665          * assumes packets must have BDs.
10666          */
10667         wmb();
10668
10669         le16_add_cpu(&fp->hw_tx_prods->bds_prod, nbd);
10670         mb(); /* FW restriction: must not reorder writing nbd and packets */
10671         le32_add_cpu(&fp->hw_tx_prods->packets_prod, 1);
10672         DOORBELL(bp, fp->index, 0);
10673
10674         mmiowb();
10675
10676         fp->tx_bd_prod += nbd;
10677
10678         if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
10679                 /* We want bnx2x_tx_int to "see" the updated tx_bd_prod
10680                    if we put Tx into XOFF state. */
10681                 smp_mb();
10682                 netif_tx_stop_queue(txq);
10683                 fp->eth_q_stats.driver_xoff++;
10684                 if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
10685                         netif_tx_wake_queue(txq);
10686         }
10687         fp->tx_pkt++;
10688
10689         return NETDEV_TX_OK;
10690 }
10691
10692 /* called with rtnl_lock */
10693 static int bnx2x_open(struct net_device *dev)
10694 {
10695         struct bnx2x *bp = netdev_priv(dev);
10696
10697         netif_carrier_off(dev);
10698
10699         bnx2x_set_power_state(bp, PCI_D0);
10700
10701         return bnx2x_nic_load(bp, LOAD_OPEN);
10702 }
10703
10704 /* called with rtnl_lock */
10705 static int bnx2x_close(struct net_device *dev)
10706 {
10707         struct bnx2x *bp = netdev_priv(dev);
10708
10709         /* Unload the driver, release IRQs */
10710         bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10711         if (atomic_read(&bp->pdev->enable_cnt) == 1)
10712                 if (!CHIP_REV_IS_SLOW(bp))
10713                         bnx2x_set_power_state(bp, PCI_D3hot);
10714
10715         return 0;
10716 }
10717
10718 /* called with netif_tx_lock from dev_mcast.c */
10719 static void bnx2x_set_rx_mode(struct net_device *dev)
10720 {
10721         struct bnx2x *bp = netdev_priv(dev);
10722         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10723         int port = BP_PORT(bp);
10724
10725         if (bp->state != BNX2X_STATE_OPEN) {
10726                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10727                 return;
10728         }
10729
10730         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
10731
10732         if (dev->flags & IFF_PROMISC)
10733                 rx_mode = BNX2X_RX_MODE_PROMISC;
10734
10735         else if ((dev->flags & IFF_ALLMULTI) ||
10736                  ((dev->mc_count > BNX2X_MAX_MULTICAST) && CHIP_IS_E1(bp)))
10737                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10738
10739         else { /* some multicasts */
10740                 if (CHIP_IS_E1(bp)) {
10741                         int i, old, offset;
10742                         struct dev_mc_list *mclist;
10743                         struct mac_configuration_cmd *config =
10744                                                 bnx2x_sp(bp, mcast_config);
10745
10746                         for (i = 0, mclist = dev->mc_list;
10747                              mclist && (i < dev->mc_count);
10748                              i++, mclist = mclist->next) {
10749
10750                                 config->config_table[i].
10751                                         cam_entry.msb_mac_addr =
10752                                         swab16(*(u16 *)&mclist->dmi_addr[0]);
10753                                 config->config_table[i].
10754                                         cam_entry.middle_mac_addr =
10755                                         swab16(*(u16 *)&mclist->dmi_addr[2]);
10756                                 config->config_table[i].
10757                                         cam_entry.lsb_mac_addr =
10758                                         swab16(*(u16 *)&mclist->dmi_addr[4]);
10759                                 config->config_table[i].cam_entry.flags =
10760                                                         cpu_to_le16(port);
10761                                 config->config_table[i].
10762                                         target_table_entry.flags = 0;
10763                                 config->config_table[i].
10764                                         target_table_entry.client_id = 0;
10765                                 config->config_table[i].
10766                                         target_table_entry.vlan_id = 0;
10767
10768                                 DP(NETIF_MSG_IFUP,
10769                                    "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
10770                                    config->config_table[i].
10771                                                 cam_entry.msb_mac_addr,
10772                                    config->config_table[i].
10773                                                 cam_entry.middle_mac_addr,
10774                                    config->config_table[i].
10775                                                 cam_entry.lsb_mac_addr);
10776                         }
10777                         old = config->hdr.length;
10778                         if (old > i) {
10779                                 for (; i < old; i++) {
10780                                         if (CAM_IS_INVALID(config->
10781                                                            config_table[i])) {
10782                                                 /* already invalidated */
10783                                                 break;
10784                                         }
10785                                         /* invalidate */
10786                                         CAM_INVALIDATE(config->
10787                                                        config_table[i]);
10788                                 }
10789                         }
10790
10791                         if (CHIP_REV_IS_SLOW(bp))
10792                                 offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
10793                         else
10794                                 offset = BNX2X_MAX_MULTICAST*(1 + port);
10795
10796                         config->hdr.length = i;
10797                         config->hdr.offset = offset;
10798                         config->hdr.client_id = bp->fp->cl_id;
10799                         config->hdr.reserved1 = 0;
10800
10801                         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
10802                                    U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
10803                                    U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
10804                                       0);
10805                 } else { /* E1H */
10806                         /* Accept one or more multicasts */
10807                         struct dev_mc_list *mclist;
10808                         u32 mc_filter[MC_HASH_SIZE];
10809                         u32 crc, bit, regidx;
10810                         int i;
10811
10812                         memset(mc_filter, 0, 4 * MC_HASH_SIZE);
10813
10814                         for (i = 0, mclist = dev->mc_list;
10815                              mclist && (i < dev->mc_count);
10816                              i++, mclist = mclist->next) {
10817
10818                                 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
10819                                    mclist->dmi_addr);
10820
10821                                 crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN);
10822                                 bit = (crc >> 24) & 0xff;
10823                                 regidx = bit >> 5;
10824                                 bit &= 0x1f;
10825                                 mc_filter[regidx] |= (1 << bit);
10826                         }
10827
10828                         for (i = 0; i < MC_HASH_SIZE; i++)
10829                                 REG_WR(bp, MC_HASH_OFFSET(bp, i),
10830                                        mc_filter[i]);
10831                 }
10832         }
10833
10834         bp->rx_mode = rx_mode;
10835         bnx2x_set_storm_rx_mode(bp);
10836 }
10837
10838 /* called with rtnl_lock */
10839 static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
10840 {
10841         struct sockaddr *addr = p;
10842         struct bnx2x *bp = netdev_priv(dev);
10843
10844         if (!is_valid_ether_addr((u8 *)(addr->sa_data)))
10845                 return -EINVAL;
10846
10847         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
10848         if (netif_running(dev)) {
10849                 if (CHIP_IS_E1(bp))
10850                         bnx2x_set_mac_addr_e1(bp, 1);
10851                 else
10852                         bnx2x_set_mac_addr_e1h(bp, 1);
10853         }
10854
10855         return 0;
10856 }
10857
10858 /* called with rtnl_lock */
10859 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10860 {
10861         struct mii_ioctl_data *data = if_mii(ifr);
10862         struct bnx2x *bp = netdev_priv(dev);
10863         int port = BP_PORT(bp);
10864         int err;
10865
10866         switch (cmd) {
10867         case SIOCGMIIPHY:
10868                 data->phy_id = bp->port.phy_addr;
10869
10870                 /* fallthrough */
10871
10872         case SIOCGMIIREG: {
10873                 u16 mii_regval;
10874
10875                 if (!netif_running(dev))
10876                         return -EAGAIN;
10877
10878                 mutex_lock(&bp->port.phy_mutex);
10879                 err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr,
10880                                       DEFAULT_PHY_DEV_ADDR,
10881                                       (data->reg_num & 0x1f), &mii_regval);
10882                 data->val_out = mii_regval;
10883                 mutex_unlock(&bp->port.phy_mutex);
10884                 return err;
10885         }
10886
10887         case SIOCSMIIREG:
10888                 if (!capable(CAP_NET_ADMIN))
10889                         return -EPERM;
10890
10891                 if (!netif_running(dev))
10892                         return -EAGAIN;
10893
10894                 mutex_lock(&bp->port.phy_mutex);
10895                 err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr,
10896                                        DEFAULT_PHY_DEV_ADDR,
10897                                        (data->reg_num & 0x1f), data->val_in);
10898                 mutex_unlock(&bp->port.phy_mutex);
10899                 return err;
10900
10901         default:
10902                 /* do nothing */
10903                 break;
10904         }
10905
10906         return -EOPNOTSUPP;
10907 }
10908
10909 /* called with rtnl_lock */
10910 static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
10911 {
10912         struct bnx2x *bp = netdev_priv(dev);
10913         int rc = 0;
10914
10915         if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
10916             ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
10917                 return -EINVAL;
10918
10919         /* This does not race with packet allocation
10920          * because the actual alloc size is
10921          * only updated as part of load
10922          */
10923         dev->mtu = new_mtu;
10924
10925         if (netif_running(dev)) {
10926                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
10927                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
10928         }
10929
10930         return rc;
10931 }
10932
10933 static void bnx2x_tx_timeout(struct net_device *dev)
10934 {
10935         struct bnx2x *bp = netdev_priv(dev);
10936
10937 #ifdef BNX2X_STOP_ON_ERROR
10938         if (!bp->panic)
10939                 bnx2x_panic();
10940 #endif
10941         /* This allows the netif to be shutdown gracefully before resetting */
10942         schedule_work(&bp->reset_task);
10943 }
10944
10945 #ifdef BCM_VLAN
10946 /* called with rtnl_lock */
10947 static void bnx2x_vlan_rx_register(struct net_device *dev,
10948                                    struct vlan_group *vlgrp)
10949 {
10950         struct bnx2x *bp = netdev_priv(dev);
10951
10952         bp->vlgrp = vlgrp;
10953
10954         /* Set flags according to the required capabilities */
10955         bp->flags &= ~(HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);
10956
10957         if (dev->features & NETIF_F_HW_VLAN_TX)
10958                 bp->flags |= HW_VLAN_TX_FLAG;
10959
10960         if (dev->features & NETIF_F_HW_VLAN_RX)
10961                 bp->flags |= HW_VLAN_RX_FLAG;
10962
10963         if (netif_running(dev))
10964                 bnx2x_set_client_config(bp);
10965 }
10966
10967 #endif
10968
10969 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
10970 static void poll_bnx2x(struct net_device *dev)
10971 {
10972         struct bnx2x *bp = netdev_priv(dev);
10973
10974         disable_irq(bp->pdev->irq);
10975         bnx2x_interrupt(bp->pdev->irq, dev);
10976         enable_irq(bp->pdev->irq);
10977 }
10978 #endif
10979
10980 static const struct net_device_ops bnx2x_netdev_ops = {
10981         .ndo_open               = bnx2x_open,
10982         .ndo_stop               = bnx2x_close,
10983         .ndo_start_xmit         = bnx2x_start_xmit,
10984         .ndo_set_multicast_list = bnx2x_set_rx_mode,
10985         .ndo_set_mac_address    = bnx2x_change_mac_addr,
10986         .ndo_validate_addr      = eth_validate_addr,
10987         .ndo_do_ioctl           = bnx2x_ioctl,
10988         .ndo_change_mtu         = bnx2x_change_mtu,
10989         .ndo_tx_timeout         = bnx2x_tx_timeout,
10990 #ifdef BCM_VLAN
10991         .ndo_vlan_rx_register   = bnx2x_vlan_rx_register,
10992 #endif
10993 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
10994         .ndo_poll_controller    = poll_bnx2x,
10995 #endif
10996 };
10997
10998 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10999                                     struct net_device *dev)
11000 {
11001         struct bnx2x *bp;
11002         int rc;
11003
11004         SET_NETDEV_DEV(dev, &pdev->dev);
11005         bp = netdev_priv(dev);
11006
11007         bp->dev = dev;
11008         bp->pdev = pdev;
11009         bp->flags = 0;
11010         bp->func = PCI_FUNC(pdev->devfn);
11011
11012         rc = pci_enable_device(pdev);
11013         if (rc) {
11014                 printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
11015                 goto err_out;
11016         }
11017
11018         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11019                 printk(KERN_ERR PFX "Cannot find PCI device base address,"
11020                        " aborting\n");
11021                 rc = -ENODEV;
11022                 goto err_out_disable;
11023         }
11024
11025         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11026                 printk(KERN_ERR PFX "Cannot find second PCI device"
11027                        " base address, aborting\n");
11028                 rc = -ENODEV;
11029                 goto err_out_disable;
11030         }
11031
11032         if (atomic_read(&pdev->enable_cnt) == 1) {
11033                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11034                 if (rc) {
11035                         printk(KERN_ERR PFX "Cannot obtain PCI resources,"
11036                                " aborting\n");
11037                         goto err_out_disable;
11038                 }
11039
11040                 pci_set_master(pdev);
11041                 pci_save_state(pdev);
11042         }
11043
11044         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11045         if (bp->pm_cap == 0) {
11046                 printk(KERN_ERR PFX "Cannot find power management"
11047                        " capability, aborting\n");
11048                 rc = -EIO;
11049                 goto err_out_release;
11050         }
11051
11052         bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
11053         if (bp->pcie_cap == 0) {
11054                 printk(KERN_ERR PFX "Cannot find PCI Express capability,"
11055                        " aborting\n");
11056                 rc = -EIO;
11057                 goto err_out_release;
11058         }
11059
11060         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
11061                 bp->flags |= USING_DAC_FLAG;
11062                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
11063                         printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
11064                                " failed, aborting\n");
11065                         rc = -EIO;
11066                         goto err_out_release;
11067                 }
11068
11069         } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
11070                 printk(KERN_ERR PFX "System does not support DMA,"
11071                        " aborting\n");
11072                 rc = -EIO;
11073                 goto err_out_release;
11074         }
11075
11076         dev->mem_start = pci_resource_start(pdev, 0);
11077         dev->base_addr = dev->mem_start;
11078         dev->mem_end = pci_resource_end(pdev, 0);
11079
11080         dev->irq = pdev->irq;
11081
11082         bp->regview = pci_ioremap_bar(pdev, 0);
11083         if (!bp->regview) {
11084                 printk(KERN_ERR PFX "Cannot map register space, aborting\n");
11085                 rc = -ENOMEM;
11086                 goto err_out_release;
11087         }
11088
11089         bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11090                                         min_t(u64, BNX2X_DB_SIZE,
11091                                               pci_resource_len(pdev, 2)));
11092         if (!bp->doorbells) {
11093                 printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
11094                 rc = -ENOMEM;
11095                 goto err_out_unmap;
11096         }
11097
11098         bnx2x_set_power_state(bp, PCI_D0);
11099
11100         /* clean indirect addresses */
11101         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11102                                PCICFG_VENDOR_ID_OFFSET);
11103         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
11104         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
11105         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
11106         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
11107
11108         dev->watchdog_timeo = TX_TIMEOUT;
11109
11110         dev->netdev_ops = &bnx2x_netdev_ops;
11111         dev->ethtool_ops = &bnx2x_ethtool_ops;
11112         dev->features |= NETIF_F_SG;
11113         dev->features |= NETIF_F_HW_CSUM;
11114         if (bp->flags & USING_DAC_FLAG)
11115                 dev->features |= NETIF_F_HIGHDMA;
11116 #ifdef BCM_VLAN
11117         dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
11118         bp->flags |= (HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);
11119 #endif
11120         dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
11121         dev->features |= NETIF_F_TSO6;
11122
11123         return 0;
11124
11125 err_out_unmap:
11126         if (bp->regview) {
11127                 iounmap(bp->regview);
11128                 bp->regview = NULL;
11129         }
11130         if (bp->doorbells) {
11131                 iounmap(bp->doorbells);
11132                 bp->doorbells = NULL;
11133         }
11134
11135 err_out_release:
11136         if (atomic_read(&pdev->enable_cnt) == 1)
11137                 pci_release_regions(pdev);
11138
11139 err_out_disable:
11140         pci_disable_device(pdev);
11141         pci_set_drvdata(pdev, NULL);
11142
11143 err_out:
11144         return rc;
11145 }
11146
11147 static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp)
11148 {
11149         u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11150
11151         val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11152         return val;
11153 }
11154
11155 /* return value of 1=2.5GHz 2=5GHz */
11156 static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp)
11157 {
11158         u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11159
11160         val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11161         return val;
11162 }
11163 static int __devinit bnx2x_check_firmware(struct bnx2x *bp)
11164 {
11165         struct bnx2x_fw_file_hdr *fw_hdr;
11166         struct bnx2x_fw_file_section *sections;
11167         u16 *ops_offsets;
11168         u32 offset, len, num_ops;
11169         int i;
11170         const struct firmware *firmware = bp->firmware;
11171         const u8 * fw_ver;
11172
11173         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
11174                 return -EINVAL;
11175
11176         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11177         sections = (struct bnx2x_fw_file_section *)fw_hdr;
11178
11179         /* Make sure none of the offsets and sizes make us read beyond
11180          * the end of the firmware data */
11181         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11182                 offset = be32_to_cpu(sections[i].offset);
11183                 len = be32_to_cpu(sections[i].len);
11184                 if (offset + len > firmware->size) {
11185                         printk(KERN_ERR PFX "Section %d length is out of bounds\n", i);
11186                         return -EINVAL;
11187                 }
11188         }
11189
11190         /* Likewise for the init_ops offsets */
11191         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11192         ops_offsets = (u16 *)(firmware->data + offset);
11193         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11194
11195         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11196                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11197                         printk(KERN_ERR PFX "Section offset %d is out of bounds\n", i);
11198                         return -EINVAL;
11199                 }
11200         }
11201
11202         /* Check FW version */
11203         offset = be32_to_cpu(fw_hdr->fw_version.offset);
11204         fw_ver = firmware->data + offset;
11205         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11206             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11207             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11208             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11209                 printk(KERN_ERR PFX "Bad FW version:%d.%d.%d.%d."
11210                                     " Should be %d.%d.%d.%d\n",
11211                        fw_ver[0], fw_ver[1], fw_ver[2],
11212                        fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
11213                        BCM_5710_FW_MINOR_VERSION,
11214                        BCM_5710_FW_REVISION_VERSION,
11215                        BCM_5710_FW_ENGINEERING_VERSION);
11216                 return -EINVAL;
11217         }
11218
11219         return 0;
11220 }
11221
11222 static void inline be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11223 {
11224         u32 i;
11225         const __be32 *source = (const __be32*)_source;
11226         u32 *target = (u32*)_target;
11227
11228         for (i = 0; i < n/4; i++)
11229                 target[i] = be32_to_cpu(source[i]);
11230 }
11231
11232 /*
11233    Ops array is stored in the following format:
11234    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11235  */
11236 static void inline bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11237 {
11238         u32 i, j, tmp;
11239         const __be32 *source = (const __be32*)_source;
11240         struct raw_op *target = (struct raw_op*)_target;
11241
11242         for (i = 0, j = 0; i < n/8; i++, j+=2) {
11243                 tmp = be32_to_cpu(source[j]);
11244                 target[i].op = (tmp >> 24) & 0xff;
11245                 target[i].offset =  tmp & 0xffffff;
11246                 target[i].raw_data = be32_to_cpu(source[j+1]);
11247         }
11248 }
11249 static void inline be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11250 {
11251         u32 i;
11252         u16 *target = (u16*)_target;
11253         const __be16 *source = (const __be16*)_source;
11254
11255         for (i = 0; i < n/2; i++)
11256                 target[i] = be16_to_cpu(source[i]);
11257 }
11258
11259 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11260         do {   \
11261                 u32 len = be32_to_cpu(fw_hdr->arr.len);   \
11262                 bp->arr = kmalloc(len, GFP_KERNEL);  \
11263                 if (!bp->arr) { \
11264                         printk(KERN_ERR PFX "Failed to allocate %d bytes for "#arr"\n", len); \
11265                         goto lbl; \
11266                 } \
11267                 func(bp->firmware->data + \
11268                         be32_to_cpu(fw_hdr->arr.offset), \
11269                         (u8*)bp->arr, len); \
11270         } while (0)
11271
11272
11273 static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
11274 {
11275         char fw_file_name[40] = {0};
11276         int rc, offset;
11277         struct bnx2x_fw_file_hdr *fw_hdr;
11278
11279         /* Create a FW file name */
11280         if (CHIP_IS_E1(bp))
11281                 offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1);
11282         else
11283                 offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1H);
11284
11285         sprintf(fw_file_name + offset, "%d.%d.%d.%d.fw",
11286                 BCM_5710_FW_MAJOR_VERSION,
11287                 BCM_5710_FW_MINOR_VERSION,
11288                 BCM_5710_FW_REVISION_VERSION,
11289                 BCM_5710_FW_ENGINEERING_VERSION);
11290
11291         printk(KERN_INFO PFX "Loading %s\n", fw_file_name);
11292
11293         rc = request_firmware(&bp->firmware, fw_file_name, dev);
11294         if (rc) {
11295                 printk(KERN_ERR PFX "Can't load firmware file %s\n", fw_file_name);
11296                 goto request_firmware_exit;
11297         }
11298
11299         rc = bnx2x_check_firmware(bp);
11300         if (rc) {
11301                 printk(KERN_ERR PFX "Corrupt firmware file %s\n", fw_file_name);
11302                 goto request_firmware_exit;
11303         }
11304
11305         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11306
11307         /* Initialize the pointers to the init arrays */
11308         /* Blob */
11309         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11310
11311         /* Opcodes */
11312         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11313
11314         /* Offsets */
11315         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, be16_to_cpu_n);
11316
11317         /* STORMs firmware */
11318         bp->tsem_int_table_data = bp->firmware->data +
11319                 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11320         bp->tsem_pram_data      = bp->firmware->data +
11321                 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11322         bp->usem_int_table_data = bp->firmware->data +
11323                 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11324         bp->usem_pram_data      = bp->firmware->data +
11325                 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11326         bp->xsem_int_table_data = bp->firmware->data +
11327                 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11328         bp->xsem_pram_data      = bp->firmware->data +
11329                 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11330         bp->csem_int_table_data = bp->firmware->data +
11331                 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11332         bp->csem_pram_data      = bp->firmware->data +
11333                 be32_to_cpu(fw_hdr->csem_pram_data.offset);
11334
11335         return 0;
11336 init_offsets_alloc_err:
11337         kfree(bp->init_ops);
11338 init_ops_alloc_err:
11339         kfree(bp->init_data);
11340 request_firmware_exit:
11341         release_firmware(bp->firmware);
11342
11343         return rc;
11344 }
11345
11346
11347
11348 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11349                                     const struct pci_device_id *ent)
11350 {
11351         static int version_printed;
11352         struct net_device *dev = NULL;
11353         struct bnx2x *bp;
11354         int rc;
11355
11356         if (version_printed++ == 0)
11357                 printk(KERN_INFO "%s", version);
11358
11359         /* dev zeroed in init_etherdev */
11360         dev = alloc_etherdev_mq(sizeof(*bp), MAX_CONTEXT);
11361         if (!dev) {
11362                 printk(KERN_ERR PFX "Cannot allocate net device\n");
11363                 return -ENOMEM;
11364         }
11365
11366         bp = netdev_priv(dev);
11367         bp->msglevel = debug;
11368
11369         rc = bnx2x_init_dev(pdev, dev);
11370         if (rc < 0) {
11371                 free_netdev(dev);
11372                 return rc;
11373         }
11374
11375         pci_set_drvdata(pdev, dev);
11376
11377         rc = bnx2x_init_bp(bp);
11378         if (rc)
11379                 goto init_one_exit;
11380
11381         /* Set init arrays */
11382         rc = bnx2x_init_firmware(bp, &pdev->dev);
11383         if (rc) {
11384                 printk(KERN_ERR PFX "Error loading firmware\n");
11385                 goto init_one_exit;
11386         }
11387
11388         rc = register_netdev(dev);
11389         if (rc) {
11390                 dev_err(&pdev->dev, "Cannot register net device\n");
11391                 goto init_one_exit;
11392         }
11393
11394         printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
11395                " IRQ %d, ", dev->name, board_info[ent->driver_data].name,
11396                (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11397                bnx2x_get_pcie_width(bp),
11398                (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
11399                dev->base_addr, bp->pdev->irq);
11400         printk(KERN_CONT "node addr %pM\n", dev->dev_addr);
11401
11402         return 0;
11403
11404 init_one_exit:
11405         if (bp->regview)
11406                 iounmap(bp->regview);
11407
11408         if (bp->doorbells)
11409                 iounmap(bp->doorbells);
11410
11411         free_netdev(dev);
11412
11413         if (atomic_read(&pdev->enable_cnt) == 1)
11414                 pci_release_regions(pdev);
11415
11416         pci_disable_device(pdev);
11417         pci_set_drvdata(pdev, NULL);
11418
11419         return rc;
11420 }
11421
11422 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11423 {
11424         struct net_device *dev = pci_get_drvdata(pdev);
11425         struct bnx2x *bp;
11426
11427         if (!dev) {
11428                 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
11429                 return;
11430         }
11431         bp = netdev_priv(dev);
11432
11433         unregister_netdev(dev);
11434
11435         kfree(bp->init_ops_offsets);
11436         kfree(bp->init_ops);
11437         kfree(bp->init_data);
11438         release_firmware(bp->firmware);
11439
11440         if (bp->regview)
11441                 iounmap(bp->regview);
11442
11443         if (bp->doorbells)
11444                 iounmap(bp->doorbells);
11445
11446         free_netdev(dev);
11447
11448         if (atomic_read(&pdev->enable_cnt) == 1)
11449                 pci_release_regions(pdev);
11450
11451         pci_disable_device(pdev);
11452         pci_set_drvdata(pdev, NULL);
11453 }
11454
11455 static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
11456 {
11457         struct net_device *dev = pci_get_drvdata(pdev);
11458         struct bnx2x *bp;
11459
11460         if (!dev) {
11461                 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
11462                 return -ENODEV;
11463         }
11464         bp = netdev_priv(dev);
11465
11466         rtnl_lock();
11467
11468         pci_save_state(pdev);
11469
11470         if (!netif_running(dev)) {
11471                 rtnl_unlock();
11472                 return 0;
11473         }
11474
11475         netif_device_detach(dev);
11476
11477         bnx2x_nic_unload(bp, UNLOAD_CLOSE);
11478
11479         bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
11480
11481         rtnl_unlock();
11482
11483         return 0;
11484 }
11485
11486 static int bnx2x_resume(struct pci_dev *pdev)
11487 {
11488         struct net_device *dev = pci_get_drvdata(pdev);
11489         struct bnx2x *bp;
11490         int rc;
11491
11492         if (!dev) {
11493                 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
11494                 return -ENODEV;
11495         }
11496         bp = netdev_priv(dev);
11497
11498         rtnl_lock();
11499
11500         pci_restore_state(pdev);
11501
11502         if (!netif_running(dev)) {
11503                 rtnl_unlock();
11504                 return 0;
11505         }
11506
11507         bnx2x_set_power_state(bp, PCI_D0);
11508         netif_device_attach(dev);
11509
11510         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11511
11512         rtnl_unlock();
11513
11514         return rc;
11515 }
11516
11517 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
11518 {
11519         int i;
11520
11521         bp->state = BNX2X_STATE_ERROR;
11522
11523         bp->rx_mode = BNX2X_RX_MODE_NONE;
11524
11525         bnx2x_netif_stop(bp, 0);
11526
11527         del_timer_sync(&bp->timer);
11528         bp->stats_state = STATS_STATE_DISABLED;
11529         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
11530
11531         /* Release IRQs */
11532         bnx2x_free_irq(bp);
11533
11534         if (CHIP_IS_E1(bp)) {
11535                 struct mac_configuration_cmd *config =
11536                                                 bnx2x_sp(bp, mcast_config);
11537
11538                 for (i = 0; i < config->hdr.length; i++)
11539                         CAM_INVALIDATE(config->config_table[i]);
11540         }
11541
11542         /* Free SKBs, SGEs, TPA pool and driver internals */
11543         bnx2x_free_skbs(bp);
11544         for_each_rx_queue(bp, i)
11545                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
11546         for_each_rx_queue(bp, i)
11547                 netif_napi_del(&bnx2x_fp(bp, i, napi));
11548         bnx2x_free_mem(bp);
11549
11550         bp->state = BNX2X_STATE_CLOSED;
11551
11552         netif_carrier_off(bp->dev);
11553
11554         return 0;
11555 }
11556
11557 static void bnx2x_eeh_recover(struct bnx2x *bp)
11558 {
11559         u32 val;
11560
11561         mutex_init(&bp->port.phy_mutex);
11562
11563         bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
11564         bp->link_params.shmem_base = bp->common.shmem_base;
11565         BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
11566
11567         if (!bp->common.shmem_base ||
11568             (bp->common.shmem_base < 0xA0000) ||
11569             (bp->common.shmem_base >= 0xC0000)) {
11570                 BNX2X_DEV_INFO("MCP not active\n");
11571                 bp->flags |= NO_MCP_FLAG;
11572                 return;
11573         }
11574
11575         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11576         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11577                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11578                 BNX2X_ERR("BAD MCP validity signature\n");
11579
11580         if (!BP_NOMCP(bp)) {
11581                 bp->fw_seq = (SHMEM_RD(bp, func_mb[BP_FUNC(bp)].drv_mb_header)
11582                               & DRV_MSG_SEQ_NUMBER_MASK);
11583                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11584         }
11585 }
11586
11587 /**
11588  * bnx2x_io_error_detected - called when PCI error is detected
11589  * @pdev: Pointer to PCI device
11590  * @state: The current pci connection state
11591  *
11592  * This function is called after a PCI bus error affecting
11593  * this device has been detected.
11594  */
11595 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11596                                                 pci_channel_state_t state)
11597 {
11598         struct net_device *dev = pci_get_drvdata(pdev);
11599         struct bnx2x *bp = netdev_priv(dev);
11600
11601         rtnl_lock();
11602
11603         netif_device_detach(dev);
11604
11605         if (netif_running(dev))
11606                 bnx2x_eeh_nic_unload(bp);
11607
11608         pci_disable_device(pdev);
11609
11610         rtnl_unlock();
11611
11612         /* Request a slot reset */
11613         return PCI_ERS_RESULT_NEED_RESET;
11614 }
11615
11616 /**
11617  * bnx2x_io_slot_reset - called after the PCI bus has been reset
11618  * @pdev: Pointer to PCI device
11619  *
11620  * Restart the card from scratch, as if from a cold-boot.
11621  */
11622 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11623 {
11624         struct net_device *dev = pci_get_drvdata(pdev);
11625         struct bnx2x *bp = netdev_priv(dev);
11626
11627         rtnl_lock();
11628
11629         if (pci_enable_device(pdev)) {
11630                 dev_err(&pdev->dev,
11631                         "Cannot re-enable PCI device after reset\n");
11632                 rtnl_unlock();
11633                 return PCI_ERS_RESULT_DISCONNECT;
11634         }
11635
11636         pci_set_master(pdev);
11637         pci_restore_state(pdev);
11638
11639         if (netif_running(dev))
11640                 bnx2x_set_power_state(bp, PCI_D0);
11641
11642         rtnl_unlock();
11643
11644         return PCI_ERS_RESULT_RECOVERED;
11645 }
11646
11647 /**
11648  * bnx2x_io_resume - called when traffic can start flowing again
11649  * @pdev: Pointer to PCI device
11650  *
11651  * This callback is called when the error recovery driver tells us that
11652  * its OK to resume normal operation.
11653  */
11654 static void bnx2x_io_resume(struct pci_dev *pdev)
11655 {
11656         struct net_device *dev = pci_get_drvdata(pdev);
11657         struct bnx2x *bp = netdev_priv(dev);
11658
11659         rtnl_lock();
11660
11661         bnx2x_eeh_recover(bp);
11662
11663         if (netif_running(dev))
11664                 bnx2x_nic_load(bp, LOAD_NORMAL);
11665
11666         netif_device_attach(dev);
11667
11668         rtnl_unlock();
11669 }
11670
11671 static struct pci_error_handlers bnx2x_err_handler = {
11672         .error_detected = bnx2x_io_error_detected,
11673         .slot_reset     = bnx2x_io_slot_reset,
11674         .resume         = bnx2x_io_resume,
11675 };
11676
11677 static struct pci_driver bnx2x_pci_driver = {
11678         .name        = DRV_MODULE_NAME,
11679         .id_table    = bnx2x_pci_tbl,
11680         .probe       = bnx2x_init_one,
11681         .remove      = __devexit_p(bnx2x_remove_one),
11682         .suspend     = bnx2x_suspend,
11683         .resume      = bnx2x_resume,
11684         .err_handler = &bnx2x_err_handler,
11685 };
11686
11687 static int __init bnx2x_init(void)
11688 {
11689         int ret;
11690
11691         bnx2x_wq = create_singlethread_workqueue("bnx2x");
11692         if (bnx2x_wq == NULL) {
11693                 printk(KERN_ERR PFX "Cannot create workqueue\n");
11694                 return -ENOMEM;
11695         }
11696
11697         ret = pci_register_driver(&bnx2x_pci_driver);
11698         if (ret) {
11699                 printk(KERN_ERR PFX "Cannot register driver\n");
11700                 destroy_workqueue(bnx2x_wq);
11701         }
11702         return ret;
11703 }
11704
11705 static void __exit bnx2x_cleanup(void)
11706 {
11707         pci_unregister_driver(&bnx2x_pci_driver);
11708
11709         destroy_workqueue(bnx2x_wq);
11710 }
11711
11712 module_init(bnx2x_init);
11713 module_exit(bnx2x_cleanup);
11714
11715