1 /* Copyright 2008-2009 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/delay.h>
22 #include <linux/ethtool.h>
23 #include <linux/mutex.h>
27 /********************************************************/
29 #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
30 #define ETH_MIN_PACKET_SIZE 60
31 #define ETH_MAX_PACKET_SIZE 1500
32 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
33 #define MDIO_ACCESS_TIMEOUT 1000
34 #define BMAC_CONTROL_RX_ENABLE 2
36 /***********************************************************/
37 /* Shortcut definitions */
38 /***********************************************************/
40 #define NIG_LATCH_BC_ENABLE_MI_INT 0
42 #define NIG_STATUS_EMAC0_MI_INT \
43 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
44 #define NIG_STATUS_XGXS0_LINK10G \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
46 #define NIG_STATUS_XGXS0_LINK_STATUS \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
48 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
50 #define NIG_STATUS_SERDES0_LINK_STATUS \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
52 #define NIG_MASK_MI_INT \
53 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
54 #define NIG_MASK_XGXS0_LINK10G \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
56 #define NIG_MASK_XGXS0_LINK_STATUS \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
58 #define NIG_MASK_SERDES0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
61 #define MDIO_AN_CL73_OR_37_COMPLETE \
62 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
63 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
65 #define XGXS_RESET_BITS \
66 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
67 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
68 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
72 #define SERDES_RESET_BITS \
73 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
74 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
75 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
78 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
79 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
80 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
81 #define AUTONEG_PARALLEL \
82 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
83 #define AUTONEG_SGMII_FIBER_AUTODET \
84 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
85 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
87 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
88 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
89 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
91 #define GP_STATUS_SPEED_MASK \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
93 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
94 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
95 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
96 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
97 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
98 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
99 #define GP_STATUS_10G_HIG \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
101 #define GP_STATUS_10G_CX4 \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
103 #define GP_STATUS_12G_HIG \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
105 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
106 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
107 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
108 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
109 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
110 #define GP_STATUS_10G_KX4 \
111 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
113 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
114 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
115 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
116 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
117 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
118 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
119 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
120 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
121 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
122 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
123 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
124 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
125 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
126 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
127 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
128 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
129 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
130 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
131 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
132 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
133 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
134 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
135 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
137 #define PHY_XGXS_FLAG 0x1
138 #define PHY_SGMII_FLAG 0x2
139 #define PHY_SERDES_FLAG 0x4
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
166 /**********************************************************/
168 /**********************************************************/
169 #define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
170 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
171 DEFAULT_PHY_DEV_ADDR, \
172 (_bank + (_addr & 0xf)), \
175 #define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
176 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
177 DEFAULT_PHY_DEV_ADDR, \
178 (_bank + (_addr & 0xf)), \
181 static void bnx2x_set_serdes_access(struct link_params *params)
183 struct bnx2x *bp = params->bp;
184 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
186 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
187 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
189 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
192 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
194 static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
196 struct bnx2x *bp = params->bp;
197 if (phy_flags & PHY_XGXS_FLAG) {
198 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
199 params->port*0x18, 0);
200 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
201 DEFAULT_PHY_DEV_ADDR);
203 bnx2x_set_serdes_access(params);
205 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
207 DEFAULT_PHY_DEV_ADDR);
211 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
213 u32 val = REG_RD(bp, reg);
216 REG_WR(bp, reg, val);
220 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
222 u32 val = REG_RD(bp, reg);
225 REG_WR(bp, reg, val);
229 static void bnx2x_emac_init(struct link_params *params,
230 struct link_vars *vars)
232 /* reset and unreset the emac core */
233 struct bnx2x *bp = params->bp;
234 u8 port = params->port;
235 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
239 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
240 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
242 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
243 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
245 /* init emac - use read-modify-write */
246 /* self clear reset */
247 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
248 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
252 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
253 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
255 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
259 } while (val & EMAC_MODE_RESET);
261 /* Set mac address */
262 val = ((params->mac_addr[0] << 8) |
263 params->mac_addr[1]);
264 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
266 val = ((params->mac_addr[2] << 24) |
267 (params->mac_addr[3] << 16) |
268 (params->mac_addr[4] << 8) |
269 params->mac_addr[5]);
270 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
273 static u8 bnx2x_emac_enable(struct link_params *params,
274 struct link_vars *vars, u8 lb)
276 struct bnx2x *bp = params->bp;
277 u8 port = params->port;
278 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
281 DP(NETIF_MSG_LINK, "enabling EMAC\n");
283 /* enable emac and not bmac */
284 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
287 if (CHIP_REV_IS_EMUL(bp)) {
288 /* Use lane 1 (of lanes 0-3) */
289 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
290 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
296 if (CHIP_REV_IS_FPGA(bp)) {
297 /* Use lane 1 (of lanes 0-3) */
298 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
300 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
301 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
305 if (vars->phy_flags & PHY_XGXS_FLAG) {
306 u32 ser_lane = ((params->lane_config &
307 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
308 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
310 DP(NETIF_MSG_LINK, "XGXS\n");
311 /* select the master lanes (out of 0-3) */
312 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
315 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
318 } else { /* SerDes */
319 DP(NETIF_MSG_LINK, "SerDes\n");
321 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
325 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
327 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
330 if (CHIP_REV_IS_SLOW(bp)) {
331 /* config GMII mode */
332 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
333 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
334 (val | EMAC_MODE_PORT_GMII));
336 /* pause enable/disable */
337 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
338 EMAC_RX_MODE_FLOW_EN);
339 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
340 bnx2x_bits_en(bp, emac_base +
341 EMAC_REG_EMAC_RX_MODE,
342 EMAC_RX_MODE_FLOW_EN);
344 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
345 (EMAC_TX_MODE_EXT_PAUSE_EN |
346 EMAC_TX_MODE_FLOW_EN));
347 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
348 bnx2x_bits_en(bp, emac_base +
349 EMAC_REG_EMAC_TX_MODE,
350 (EMAC_TX_MODE_EXT_PAUSE_EN |
351 EMAC_TX_MODE_FLOW_EN));
354 /* KEEP_VLAN_TAG, promiscuous */
355 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
356 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
357 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
360 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
365 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
368 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
370 /* enable emac for jumbo packets */
371 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
372 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
373 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
376 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
378 /* disable the NIG in/out to the bmac */
379 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
380 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
381 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
383 /* enable the NIG in/out to the emac */
384 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
386 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
389 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
390 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
392 if (CHIP_REV_IS_EMUL(bp)) {
393 /* take the BigMac out of reset */
395 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
396 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
398 /* enable access for bmac registers */
399 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
402 vars->mac_type = MAC_TYPE_EMAC;
408 static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
411 struct bnx2x *bp = params->bp;
412 u8 port = params->port;
413 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
414 NIG_REG_INGRESS_BMAC0_MEM;
418 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
419 /* reset and unreset the BigMac */
420 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
421 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
424 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
425 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
427 /* enable access for bmac registers */
428 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
433 REG_WR_DMAE(bp, bmac_addr +
434 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
438 wb_data[0] = ((params->mac_addr[2] << 24) |
439 (params->mac_addr[3] << 16) |
440 (params->mac_addr[4] << 8) |
441 params->mac_addr[5]);
442 wb_data[1] = ((params->mac_addr[0] << 8) |
443 params->mac_addr[1]);
444 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
449 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
453 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
460 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
464 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
469 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
471 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
474 /* rx control set to don't strip crc */
476 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
480 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
484 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
486 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
489 /* set cnt max size */
490 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
492 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
496 wb_data[0] = 0x1000200;
498 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
500 /* fix for emulation */
501 if (CHIP_REV_IS_EMUL(bp)) {
505 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
509 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
510 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
511 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
513 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
515 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
516 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
517 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
518 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
519 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
520 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
522 vars->mac_type = MAC_TYPE_BMAC;
526 static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
528 struct bnx2x *bp = params->bp;
531 if (phy_flags & PHY_XGXS_FLAG) {
532 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
533 val = XGXS_RESET_BITS;
535 } else { /* SerDes */
536 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
537 val = SERDES_RESET_BITS;
540 val = val << (params->port*16);
542 /* reset and unreset the SerDes/XGXS */
543 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
546 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
548 bnx2x_set_phy_mdio(params, phy_flags);
551 void bnx2x_link_status_update(struct link_params *params,
552 struct link_vars *vars)
554 struct bnx2x *bp = params->bp;
556 u8 port = params->port;
558 if (params->switch_cfg == SWITCH_CFG_1G)
559 vars->phy_flags = PHY_SERDES_FLAG;
561 vars->phy_flags = PHY_XGXS_FLAG;
562 vars->link_status = REG_RD(bp, params->shmem_base +
563 offsetof(struct shmem_region,
564 port_mb[port].link_status));
566 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
569 DP(NETIF_MSG_LINK, "phy link up\n");
571 vars->phy_link_up = 1;
572 vars->duplex = DUPLEX_FULL;
573 switch (vars->link_status &
574 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
576 vars->duplex = DUPLEX_HALF;
579 vars->line_speed = SPEED_10;
583 vars->duplex = DUPLEX_HALF;
587 vars->line_speed = SPEED_100;
591 vars->duplex = DUPLEX_HALF;
594 vars->line_speed = SPEED_1000;
598 vars->duplex = DUPLEX_HALF;
601 vars->line_speed = SPEED_2500;
605 vars->line_speed = SPEED_10000;
609 vars->line_speed = SPEED_12000;
613 vars->line_speed = SPEED_12500;
617 vars->line_speed = SPEED_13000;
621 vars->line_speed = SPEED_15000;
625 vars->line_speed = SPEED_16000;
632 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
633 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
635 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX;
637 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
638 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
640 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX;
642 if (vars->phy_flags & PHY_XGXS_FLAG) {
643 if (vars->line_speed &&
644 ((vars->line_speed == SPEED_10) ||
645 (vars->line_speed == SPEED_100))) {
646 vars->phy_flags |= PHY_SGMII_FLAG;
648 vars->phy_flags &= ~PHY_SGMII_FLAG;
652 /* anything 10 and over uses the bmac */
653 link_10g = ((vars->line_speed == SPEED_10000) ||
654 (vars->line_speed == SPEED_12000) ||
655 (vars->line_speed == SPEED_12500) ||
656 (vars->line_speed == SPEED_13000) ||
657 (vars->line_speed == SPEED_15000) ||
658 (vars->line_speed == SPEED_16000));
660 vars->mac_type = MAC_TYPE_BMAC;
662 vars->mac_type = MAC_TYPE_EMAC;
664 } else { /* link down */
665 DP(NETIF_MSG_LINK, "phy link down\n");
667 vars->phy_link_up = 0;
669 vars->line_speed = 0;
670 vars->duplex = DUPLEX_FULL;
671 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
673 /* indicate no mac active */
674 vars->mac_type = MAC_TYPE_NONE;
677 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
678 vars->link_status, vars->phy_link_up);
679 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
680 vars->line_speed, vars->duplex, vars->flow_ctrl);
683 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
685 struct bnx2x *bp = params->bp;
686 REG_WR(bp, params->shmem_base +
687 offsetof(struct shmem_region,
688 port_mb[params->port].link_status),
692 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
694 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
695 NIG_REG_INGRESS_BMAC0_MEM;
697 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
699 /* Only if the bmac is out of reset */
700 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
701 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
704 /* Clear Rx Enable bit in BMAC_CONTROL register */
705 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
707 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
708 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
715 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
718 struct bnx2x *bp = params->bp;
719 u8 port = params->port;
724 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
726 /* wait for init credit */
727 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
728 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
729 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
731 while ((init_crd != crd) && count) {
734 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
737 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
738 if (init_crd != crd) {
739 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
744 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
745 line_speed == SPEED_10 ||
746 line_speed == SPEED_100 ||
747 line_speed == SPEED_1000 ||
748 line_speed == SPEED_2500) {
749 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
750 /* update threshold */
751 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
752 /* update init credit */
753 init_crd = 778; /* (800-18-4) */
756 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
758 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
759 /* update threshold */
760 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
761 /* update init credit */
762 switch (line_speed) {
764 init_crd = thresh + 553 - 22;
768 init_crd = thresh + 664 - 22;
772 init_crd = thresh + 742 - 22;
776 init_crd = thresh + 778 - 22;
779 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
785 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
786 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
787 line_speed, init_crd);
789 /* probe the credit changes */
790 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
792 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
795 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
799 static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
802 switch (ext_phy_type) {
803 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
804 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
805 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
806 /* All MDC/MDIO is directed through single EMAC */
807 if (REG_RD(bp, NIG_REG_PORT_SWAP))
808 emac_base = GRCBASE_EMAC0;
810 emac_base = GRCBASE_EMAC1;
812 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
813 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
816 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
823 u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
824 u8 phy_addr, u8 devad, u16 reg, u16 val)
828 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
830 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
831 * (a value of 49==0x31) and make sure that the AUTO poll is off
834 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
835 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
836 EMAC_MDIO_MODE_CLOCK_CNT);
837 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
838 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
839 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
840 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
845 tmp = ((phy_addr << 21) | (devad << 16) | reg |
846 EMAC_MDIO_COMM_COMMAND_ADDRESS |
847 EMAC_MDIO_COMM_START_BUSY);
848 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
850 for (i = 0; i < 50; i++) {
853 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
854 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
859 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
860 DP(NETIF_MSG_LINK, "write phy register failed\n");
864 tmp = ((phy_addr << 21) | (devad << 16) | val |
865 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
866 EMAC_MDIO_COMM_START_BUSY);
867 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
869 for (i = 0; i < 50; i++) {
872 tmp = REG_RD(bp, mdio_ctrl +
873 EMAC_REG_EMAC_MDIO_COMM);
874 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
879 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
880 DP(NETIF_MSG_LINK, "write phy register failed\n");
885 /* Restore the saved mode */
886 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
891 u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
892 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
898 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
899 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
900 * (a value of 49==0x31) and make sure that the AUTO poll is off
903 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
904 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
905 EMAC_MDIO_MODE_CLOCK_CNT));
906 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
907 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
908 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
909 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
913 val = ((phy_addr << 21) | (devad << 16) | reg |
914 EMAC_MDIO_COMM_COMMAND_ADDRESS |
915 EMAC_MDIO_COMM_START_BUSY);
916 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
918 for (i = 0; i < 50; i++) {
921 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
922 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
927 if (val & EMAC_MDIO_COMM_START_BUSY) {
928 DP(NETIF_MSG_LINK, "read phy register failed\n");
935 val = ((phy_addr << 21) | (devad << 16) |
936 EMAC_MDIO_COMM_COMMAND_READ_45 |
937 EMAC_MDIO_COMM_START_BUSY);
938 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
940 for (i = 0; i < 50; i++) {
943 val = REG_RD(bp, mdio_ctrl +
944 EMAC_REG_EMAC_MDIO_COMM);
945 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
946 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
950 if (val & EMAC_MDIO_COMM_START_BUSY) {
951 DP(NETIF_MSG_LINK, "read phy register failed\n");
958 /* Restore the saved mode */
959 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
964 static void bnx2x_set_aer_mmd(struct link_params *params,
965 struct link_vars *vars)
967 struct bnx2x *bp = params->bp;
971 ser_lane = ((params->lane_config &
972 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
973 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
975 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
976 (params->phy_addr + ser_lane) : 0;
978 CL45_WR_OVER_CL22(bp, params->port,
980 MDIO_REG_BANK_AER_BLOCK,
981 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
984 static void bnx2x_set_master_ln(struct link_params *params)
986 struct bnx2x *bp = params->bp;
987 u16 new_master_ln, ser_lane;
988 ser_lane = ((params->lane_config &
989 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
990 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
992 /* set the master_ln for AN */
993 CL45_RD_OVER_CL22(bp, params->port,
995 MDIO_REG_BANK_XGXS_BLOCK2,
996 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
999 CL45_WR_OVER_CL22(bp, params->port,
1001 MDIO_REG_BANK_XGXS_BLOCK2 ,
1002 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1003 (new_master_ln | ser_lane));
1006 static u8 bnx2x_reset_unicore(struct link_params *params)
1008 struct bnx2x *bp = params->bp;
1012 CL45_RD_OVER_CL22(bp, params->port,
1014 MDIO_REG_BANK_COMBO_IEEE0,
1015 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1017 /* reset the unicore */
1018 CL45_WR_OVER_CL22(bp, params->port,
1020 MDIO_REG_BANK_COMBO_IEEE0,
1021 MDIO_COMBO_IEEE0_MII_CONTROL,
1023 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1025 bnx2x_set_serdes_access(params);
1027 /* wait for the reset to self clear */
1028 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1031 /* the reset erased the previous bank value */
1032 CL45_RD_OVER_CL22(bp, params->port,
1034 MDIO_REG_BANK_COMBO_IEEE0,
1035 MDIO_COMBO_IEEE0_MII_CONTROL,
1038 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1044 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1049 static void bnx2x_set_swap_lanes(struct link_params *params)
1051 struct bnx2x *bp = params->bp;
1052 /* Each two bits represents a lane number:
1053 No swap is 0123 => 0x1b no need to enable the swap */
1054 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1056 ser_lane = ((params->lane_config &
1057 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1058 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1059 rx_lane_swap = ((params->lane_config &
1060 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1061 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1062 tx_lane_swap = ((params->lane_config &
1063 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1064 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1066 if (rx_lane_swap != 0x1b) {
1067 CL45_WR_OVER_CL22(bp, params->port,
1069 MDIO_REG_BANK_XGXS_BLOCK2,
1070 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1072 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1073 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1075 CL45_WR_OVER_CL22(bp, params->port,
1077 MDIO_REG_BANK_XGXS_BLOCK2,
1078 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1081 if (tx_lane_swap != 0x1b) {
1082 CL45_WR_OVER_CL22(bp, params->port,
1084 MDIO_REG_BANK_XGXS_BLOCK2,
1085 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1087 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1089 CL45_WR_OVER_CL22(bp, params->port,
1091 MDIO_REG_BANK_XGXS_BLOCK2,
1092 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1096 static void bnx2x_set_parallel_detection(struct link_params *params,
1099 struct bnx2x *bp = params->bp;
1102 CL45_RD_OVER_CL22(bp, params->port,
1104 MDIO_REG_BANK_SERDES_DIGITAL,
1105 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1109 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1112 CL45_WR_OVER_CL22(bp, params->port,
1114 MDIO_REG_BANK_SERDES_DIGITAL,
1115 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1118 if (phy_flags & PHY_XGXS_FLAG) {
1119 DP(NETIF_MSG_LINK, "XGXS\n");
1121 CL45_WR_OVER_CL22(bp, params->port,
1123 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1124 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1125 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1127 CL45_RD_OVER_CL22(bp, params->port,
1129 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1130 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1135 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1137 CL45_WR_OVER_CL22(bp, params->port,
1139 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1140 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1143 /* Disable parallel detection of HiG */
1144 CL45_WR_OVER_CL22(bp, params->port,
1146 MDIO_REG_BANK_XGXS_BLOCK2,
1147 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1148 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1149 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1153 static void bnx2x_set_autoneg(struct link_params *params,
1154 struct link_vars *vars)
1156 struct bnx2x *bp = params->bp;
1161 CL45_RD_OVER_CL22(bp, params->port,
1163 MDIO_REG_BANK_COMBO_IEEE0,
1164 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1166 /* CL37 Autoneg Enabled */
1167 if (vars->line_speed == SPEED_AUTO_NEG)
1168 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1169 else /* CL37 Autoneg Disabled */
1170 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1171 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1173 CL45_WR_OVER_CL22(bp, params->port,
1175 MDIO_REG_BANK_COMBO_IEEE0,
1176 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1178 /* Enable/Disable Autodetection */
1180 CL45_RD_OVER_CL22(bp, params->port,
1182 MDIO_REG_BANK_SERDES_DIGITAL,
1183 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
1184 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
1185 if (vars->line_speed == SPEED_AUTO_NEG)
1186 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1188 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1190 CL45_WR_OVER_CL22(bp, params->port,
1192 MDIO_REG_BANK_SERDES_DIGITAL,
1193 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1195 /* Enable TetonII and BAM autoneg */
1196 CL45_RD_OVER_CL22(bp, params->port,
1198 MDIO_REG_BANK_BAM_NEXT_PAGE,
1199 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1201 if (vars->line_speed == SPEED_AUTO_NEG) {
1202 /* Enable BAM aneg Mode and TetonII aneg Mode */
1203 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1204 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1206 /* TetonII and BAM Autoneg Disabled */
1207 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1210 CL45_WR_OVER_CL22(bp, params->port,
1212 MDIO_REG_BANK_BAM_NEXT_PAGE,
1213 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1216 /* CL73 Autoneg Disabled */
1219 CL45_WR_OVER_CL22(bp, params->port,
1221 MDIO_REG_BANK_CL73_IEEEB0,
1222 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1225 /* program SerDes, forced speed */
1226 static void bnx2x_program_serdes(struct link_params *params,
1227 struct link_vars *vars)
1229 struct bnx2x *bp = params->bp;
1232 /* program duplex, disable autoneg */
1234 CL45_RD_OVER_CL22(bp, params->port,
1236 MDIO_REG_BANK_COMBO_IEEE0,
1237 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1238 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
1239 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
1240 if (params->req_duplex == DUPLEX_FULL)
1241 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1242 CL45_WR_OVER_CL22(bp, params->port,
1244 MDIO_REG_BANK_COMBO_IEEE0,
1245 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1248 - needed only if the speed is greater than 1G (2.5G or 10G) */
1249 CL45_RD_OVER_CL22(bp, params->port,
1251 MDIO_REG_BANK_SERDES_DIGITAL,
1252 MDIO_SERDES_DIGITAL_MISC1, ®_val);
1253 /* clearing the speed value before setting the right speed */
1254 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1256 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1257 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1259 if (!((vars->line_speed == SPEED_1000) ||
1260 (vars->line_speed == SPEED_100) ||
1261 (vars->line_speed == SPEED_10))) {
1263 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1264 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1265 if (vars->line_speed == SPEED_10000)
1267 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1268 if (vars->line_speed == SPEED_13000)
1270 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1273 CL45_WR_OVER_CL22(bp, params->port,
1275 MDIO_REG_BANK_SERDES_DIGITAL,
1276 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1280 static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1282 struct bnx2x *bp = params->bp;
1285 /* configure the 48 bits for BAM AN */
1287 /* set extended capabilities */
1288 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1289 val |= MDIO_OVER_1G_UP1_2_5G;
1290 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1291 val |= MDIO_OVER_1G_UP1_10G;
1292 CL45_WR_OVER_CL22(bp, params->port,
1294 MDIO_REG_BANK_OVER_1G,
1295 MDIO_OVER_1G_UP1, val);
1297 CL45_WR_OVER_CL22(bp, params->port,
1299 MDIO_REG_BANK_OVER_1G,
1300 MDIO_OVER_1G_UP3, 0);
1303 static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
1305 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1306 /* resolve pause mode and advertisement
1307 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1309 switch (params->req_flow_ctrl) {
1310 case BNX2X_FLOW_CTRL_AUTO:
1311 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
1313 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1316 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1319 case BNX2X_FLOW_CTRL_TX:
1321 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1324 case BNX2X_FLOW_CTRL_RX:
1325 case BNX2X_FLOW_CTRL_BOTH:
1326 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1329 case BNX2X_FLOW_CTRL_NONE:
1331 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1336 static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1339 struct bnx2x *bp = params->bp;
1340 /* for AN, we are always publishing full duplex */
1342 CL45_WR_OVER_CL22(bp, params->port,
1344 MDIO_REG_BANK_COMBO_IEEE0,
1345 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
1348 static void bnx2x_restart_autoneg(struct link_params *params)
1350 struct bnx2x *bp = params->bp;
1352 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
1353 /* Enable and restart BAM/CL37 aneg */
1355 CL45_RD_OVER_CL22(bp, params->port,
1357 MDIO_REG_BANK_COMBO_IEEE0,
1358 MDIO_COMBO_IEEE0_MII_CONTROL,
1361 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1363 CL45_WR_OVER_CL22(bp, params->port,
1365 MDIO_REG_BANK_COMBO_IEEE0,
1366 MDIO_COMBO_IEEE0_MII_CONTROL,
1368 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1369 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1372 static void bnx2x_initialize_sgmii_process(struct link_params *params,
1373 struct link_vars *vars)
1375 struct bnx2x *bp = params->bp;
1378 /* in SGMII mode, the unicore is always slave */
1380 CL45_RD_OVER_CL22(bp, params->port,
1382 MDIO_REG_BANK_SERDES_DIGITAL,
1383 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1385 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1386 /* set sgmii mode (and not fiber) */
1387 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1388 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1389 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1390 CL45_WR_OVER_CL22(bp, params->port,
1392 MDIO_REG_BANK_SERDES_DIGITAL,
1393 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1396 /* if forced speed */
1397 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
1398 /* set speed, disable autoneg */
1401 CL45_RD_OVER_CL22(bp, params->port,
1403 MDIO_REG_BANK_COMBO_IEEE0,
1404 MDIO_COMBO_IEEE0_MII_CONTROL,
1406 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1407 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1408 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1410 switch (vars->line_speed) {
1413 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1417 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1420 /* there is nothing to set for 10M */
1423 /* invalid speed for SGMII */
1424 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1429 /* setting the full duplex */
1430 if (params->req_duplex == DUPLEX_FULL)
1432 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1433 CL45_WR_OVER_CL22(bp, params->port,
1435 MDIO_REG_BANK_COMBO_IEEE0,
1436 MDIO_COMBO_IEEE0_MII_CONTROL,
1439 } else { /* AN mode */
1440 /* enable and restart AN */
1441 bnx2x_restart_autoneg(params);
1450 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1452 switch (pause_result) { /* ASYM P ASYM P */
1453 case 0xb: /* 1 0 1 1 */
1454 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
1457 case 0xe: /* 1 1 1 0 */
1458 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
1461 case 0x5: /* 0 1 0 1 */
1462 case 0x7: /* 0 1 1 1 */
1463 case 0xd: /* 1 1 0 1 */
1464 case 0xf: /* 1 1 1 1 */
1465 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
1473 static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1474 struct link_vars *vars)
1476 struct bnx2x *bp = params->bp;
1478 u16 ld_pause; /* local */
1479 u16 lp_pause; /* link partner */
1480 u16 an_complete; /* AN complete */
1484 u8 port = params->port;
1485 ext_phy_addr = ((params->ext_phy_config &
1486 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1487 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1489 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1492 bnx2x_cl45_read(bp, port,
1496 MDIO_AN_REG_STATUS, &an_complete);
1497 bnx2x_cl45_read(bp, port,
1501 MDIO_AN_REG_STATUS, &an_complete);
1503 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1505 bnx2x_cl45_read(bp, port,
1509 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1510 bnx2x_cl45_read(bp, port,
1514 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1515 pause_result = (ld_pause &
1516 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1517 pause_result |= (lp_pause &
1518 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1519 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1521 bnx2x_pause_resolve(vars, pause_result);
1522 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
1523 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1524 bnx2x_cl45_read(bp, port,
1528 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1530 bnx2x_cl45_read(bp, port,
1534 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1535 pause_result = (ld_pause &
1536 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1537 pause_result |= (lp_pause &
1538 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1540 bnx2x_pause_resolve(vars, pause_result);
1541 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1549 static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1550 struct link_vars *vars,
1553 struct bnx2x *bp = params->bp;
1554 u16 ld_pause; /* local driver */
1555 u16 lp_pause; /* link partner */
1558 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1560 /* resolve from gp_status in case of AN complete and not sgmii */
1561 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1562 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1563 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1564 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1565 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1566 CL45_RD_OVER_CL22(bp, params->port,
1568 MDIO_REG_BANK_COMBO_IEEE0,
1569 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1571 CL45_RD_OVER_CL22(bp, params->port,
1573 MDIO_REG_BANK_COMBO_IEEE0,
1574 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1576 pause_result = (ld_pause &
1577 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1578 pause_result |= (lp_pause &
1579 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1580 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1581 bnx2x_pause_resolve(vars, pause_result);
1582 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1583 (bnx2x_ext_phy_resove_fc(params, vars))) {
1586 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
1587 vars->flow_ctrl = params->req_fc_auto_adv;
1589 vars->flow_ctrl = params->req_flow_ctrl;
1591 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1595 static u8 bnx2x_link_settings_status(struct link_params *params,
1596 struct link_vars *vars,
1600 struct bnx2x *bp = params->bp;
1603 vars->link_status = 0;
1605 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1606 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1609 vars->phy_link_up = 1;
1610 vars->link_status |= LINK_STATUS_LINK_UP;
1612 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1613 vars->duplex = DUPLEX_FULL;
1615 vars->duplex = DUPLEX_HALF;
1617 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1619 switch (gp_status & GP_STATUS_SPEED_MASK) {
1621 new_line_speed = SPEED_10;
1622 if (vars->duplex == DUPLEX_FULL)
1623 vars->link_status |= LINK_10TFD;
1625 vars->link_status |= LINK_10THD;
1628 case GP_STATUS_100M:
1629 new_line_speed = SPEED_100;
1630 if (vars->duplex == DUPLEX_FULL)
1631 vars->link_status |= LINK_100TXFD;
1633 vars->link_status |= LINK_100TXHD;
1637 case GP_STATUS_1G_KX:
1638 new_line_speed = SPEED_1000;
1639 if (vars->duplex == DUPLEX_FULL)
1640 vars->link_status |= LINK_1000TFD;
1642 vars->link_status |= LINK_1000THD;
1645 case GP_STATUS_2_5G:
1646 new_line_speed = SPEED_2500;
1647 if (vars->duplex == DUPLEX_FULL)
1648 vars->link_status |= LINK_2500TFD;
1650 vars->link_status |= LINK_2500THD;
1656 "link speed unsupported gp_status 0x%x\n",
1660 case GP_STATUS_10G_KX4:
1661 case GP_STATUS_10G_HIG:
1662 case GP_STATUS_10G_CX4:
1663 new_line_speed = SPEED_10000;
1664 vars->link_status |= LINK_10GTFD;
1667 case GP_STATUS_12G_HIG:
1668 new_line_speed = SPEED_12000;
1669 vars->link_status |= LINK_12GTFD;
1672 case GP_STATUS_12_5G:
1673 new_line_speed = SPEED_12500;
1674 vars->link_status |= LINK_12_5GTFD;
1678 new_line_speed = SPEED_13000;
1679 vars->link_status |= LINK_13GTFD;
1683 new_line_speed = SPEED_15000;
1684 vars->link_status |= LINK_15GTFD;
1688 new_line_speed = SPEED_16000;
1689 vars->link_status |= LINK_16GTFD;
1694 "link speed unsupported gp_status 0x%x\n",
1700 /* Upon link speed change set the NIG into drain mode.
1701 Comes to deals with possible FIFO glitch due to clk change
1702 when speed is decreased without link down indicator */
1703 if (new_line_speed != vars->line_speed) {
1704 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
1705 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
1707 DP(NETIF_MSG_LINK, "Internal link speed %d is"
1708 " different than the external"
1709 " link speed %d\n", new_line_speed,
1711 vars->phy_link_up = 0;
1714 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
1715 + params->port*4, 0);
1718 vars->line_speed = new_line_speed;
1719 vars->link_status |= LINK_STATUS_SERDES_LINK;
1721 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1722 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1723 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1724 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1725 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1726 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1727 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
1728 vars->autoneg = AUTO_NEG_ENABLED;
1730 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1731 vars->autoneg |= AUTO_NEG_COMPLETE;
1732 vars->link_status |=
1733 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1736 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1737 vars->link_status |=
1738 LINK_STATUS_PARALLEL_DETECTION_USED;
1741 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1742 vars->link_status |=
1743 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1745 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1746 vars->link_status |=
1747 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1749 } else { /* link_down */
1750 DP(NETIF_MSG_LINK, "phy link down\n");
1752 vars->phy_link_up = 0;
1754 vars->duplex = DUPLEX_FULL;
1755 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1756 vars->autoneg = AUTO_NEG_DISABLED;
1757 vars->mac_type = MAC_TYPE_NONE;
1760 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1761 gp_status, vars->phy_link_up, vars->line_speed);
1762 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1765 vars->flow_ctrl, vars->autoneg);
1766 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1771 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
1773 struct bnx2x *bp = params->bp;
1779 CL45_RD_OVER_CL22(bp, params->port,
1781 MDIO_REG_BANK_OVER_1G,
1782 MDIO_OVER_1G_LP_UP2, &lp_up2);
1784 /* bits [10:7] at lp_up2, positioned at [15:12] */
1785 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1786 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1787 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1792 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
1793 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
1794 CL45_RD_OVER_CL22(bp, params->port,
1797 MDIO_TX0_TX_DRIVER, &tx_driver);
1799 /* replace tx_driver bits [15:12] */
1801 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
1802 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1803 tx_driver |= lp_up2;
1804 CL45_WR_OVER_CL22(bp, params->port,
1807 MDIO_TX0_TX_DRIVER, tx_driver);
1812 static u8 bnx2x_emac_program(struct link_params *params,
1813 u32 line_speed, u32 duplex)
1815 struct bnx2x *bp = params->bp;
1816 u8 port = params->port;
1819 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1820 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1822 (EMAC_MODE_25G_MODE |
1823 EMAC_MODE_PORT_MII_10M |
1824 EMAC_MODE_HALF_DUPLEX));
1825 switch (line_speed) {
1827 mode |= EMAC_MODE_PORT_MII_10M;
1831 mode |= EMAC_MODE_PORT_MII;
1835 mode |= EMAC_MODE_PORT_GMII;
1839 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1843 /* 10G not valid for EMAC */
1844 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
1848 if (duplex == DUPLEX_HALF)
1849 mode |= EMAC_MODE_HALF_DUPLEX;
1851 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1854 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
1855 line_speed, params->hw_led_mode, params->chip_id);
1859 /*****************************************************************************/
1860 /* External Phy section */
1861 /*****************************************************************************/
1862 static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
1864 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1865 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
1867 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1868 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
1871 static void bnx2x_ext_phy_reset(struct link_params *params,
1872 struct link_vars *vars)
1874 struct bnx2x *bp = params->bp;
1876 u8 ext_phy_addr = ((params->ext_phy_config &
1877 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1878 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1879 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
1880 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1881 /* The PHY reset is controled by GPIO 1
1882 * Give it 1ms of reset pulse
1884 if (vars->phy_flags & PHY_XGXS_FLAG) {
1886 switch (ext_phy_type) {
1887 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1888 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1891 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1892 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
1893 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
1895 /* Restore normal power mode*/
1896 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1897 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1901 bnx2x_hw_reset(bp, params->port);
1903 bnx2x_cl45_write(bp, params->port,
1907 MDIO_PMA_REG_CTRL, 0xa040);
1910 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
1913 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
1915 /* Restore normal power mode*/
1916 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1917 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1920 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1921 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1924 bnx2x_cl45_write(bp, params->port,
1932 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
1933 /* Unset Low Power Mode and SW reset */
1934 /* Restore normal power mode*/
1935 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1936 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1939 DP(NETIF_MSG_LINK, "XGXS 8072\n");
1940 bnx2x_cl45_write(bp, params->port,
1947 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
1950 /* Restore normal power mode*/
1951 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1952 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1955 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1956 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1959 DP(NETIF_MSG_LINK, "XGXS 8073\n");
1963 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
1964 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
1966 /* Restore normal power mode*/
1967 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1968 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1972 bnx2x_hw_reset(bp, params->port);
1976 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
1978 /* Restore normal power mode*/
1979 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1980 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1984 bnx2x_hw_reset(bp, params->port);
1986 bnx2x_cl45_write(bp, params->port,
1993 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
1994 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
1998 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
1999 params->ext_phy_config);
2003 } else { /* SerDes */
2004 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2005 switch (ext_phy_type) {
2006 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2007 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2010 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2011 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2012 bnx2x_hw_reset(bp, params->port);
2017 "BAD SerDes ext_phy_config 0x%x\n",
2018 params->ext_phy_config);
2025 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
2026 u32 shmem_base, u32 spirom_ver)
2028 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n",
2029 (u16)(spirom_ver>>16), (u16)spirom_ver);
2030 REG_WR(bp, shmem_base +
2031 offsetof(struct shmem_region,
2032 port_mb[port].ext_phy_fw_version),
2036 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
2037 u32 ext_phy_type, u8 ext_phy_addr,
2040 u16 fw_ver1, fw_ver2;
2041 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2042 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2043 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2044 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2045 bnx2x_save_spirom_version(bp, port, shmem_base,
2046 (u32)(fw_ver1<<16 | fw_ver2));
2050 static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2051 u8 ext_phy_addr, u32 shmem_base)
2053 u16 val, fw_ver1, fw_ver2, cnt;
2054 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2055 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2056 bnx2x_cl45_write(bp, port,
2057 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2058 ext_phy_addr, MDIO_PMA_DEVAD,
2060 bnx2x_cl45_write(bp, port,
2061 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2066 bnx2x_cl45_write(bp, port,
2067 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2072 bnx2x_cl45_write(bp, port,
2073 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2078 bnx2x_cl45_write(bp, port,
2079 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2085 for (cnt = 0; cnt < 100; cnt++) {
2086 bnx2x_cl45_read(bp, port,
2087 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2097 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
2098 bnx2x_save_spirom_version(bp, port,
2104 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2105 bnx2x_cl45_write(bp, port,
2106 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2107 ext_phy_addr, MDIO_PMA_DEVAD,
2109 bnx2x_cl45_write(bp, port,
2110 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2111 ext_phy_addr, MDIO_PMA_DEVAD,
2113 bnx2x_cl45_write(bp, port,
2114 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2115 ext_phy_addr, MDIO_PMA_DEVAD,
2117 for (cnt = 0; cnt < 100; cnt++) {
2118 bnx2x_cl45_read(bp, port,
2119 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2129 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
2130 bnx2x_save_spirom_version(bp, port,
2135 /* lower 16 bits of the register SPI_FW_STATUS */
2136 bnx2x_cl45_read(bp, port,
2137 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2142 /* upper 16 bits of register SPI_FW_STATUS */
2143 bnx2x_cl45_read(bp, port,
2144 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2150 bnx2x_save_spirom_version(bp, port,
2151 shmem_base, (fw_ver2<<16) | fw_ver1);
2154 static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
2156 struct bnx2x *bp = params->bp;
2157 u8 port = params->port;
2158 u8 ext_phy_addr = ((params->ext_phy_config &
2159 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2160 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2161 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2163 /* Need to wait 200ms after reset */
2165 /* Boot port from external ROM
2166 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2168 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2170 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2172 /* Reset internal microprocessor */
2173 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2175 MDIO_PMA_REG_GEN_CTRL,
2176 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2177 /* set micro reset = 0 */
2178 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2180 MDIO_PMA_REG_GEN_CTRL,
2181 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2182 /* Reset internal microprocessor */
2183 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2185 MDIO_PMA_REG_GEN_CTRL,
2186 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2187 /* wait for 100ms for code download via SPI port */
2190 /* Clear ser_boot_ctl bit */
2191 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2193 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2197 bnx2x_save_bcm_spirom_ver(bp, port,
2200 params->shmem_base);
2203 static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2205 /* This is only required for 8073A1, version 102 only */
2207 struct bnx2x *bp = params->bp;
2208 u8 ext_phy_addr = ((params->ext_phy_config &
2209 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2210 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2213 /* Read 8073 HW revision*/
2214 bnx2x_cl45_read(bp, params->port,
2215 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2218 MDIO_PMA_REG_8073_CHIP_REV, &val);
2221 /* No need to workaround in 8073 A1 */
2225 bnx2x_cl45_read(bp, params->port,
2226 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2229 MDIO_PMA_REG_ROM_VER2, &val);
2231 /* SNR should be applied only for version 0x102 */
2238 static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2240 struct bnx2x *bp = params->bp;
2241 u8 ext_phy_addr = ((params->ext_phy_config &
2242 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2243 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2244 u16 val, cnt, cnt1 ;
2246 bnx2x_cl45_read(bp, params->port,
2247 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2250 MDIO_PMA_REG_8073_CHIP_REV, &val);
2253 /* No need to workaround in 8073 A1 */
2256 /* XAUI workaround in 8073 A0: */
2258 /* After loading the boot ROM and restarting Autoneg,
2259 poll Dev1, Reg $C820: */
2261 for (cnt = 0; cnt < 1000; cnt++) {
2262 bnx2x_cl45_read(bp, params->port,
2263 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2266 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2268 /* If bit [14] = 0 or bit [13] = 0, continue on with
2269 system initialization (XAUI work-around not required,
2270 as these bits indicate 2.5G or 1G link up). */
2271 if (!(val & (1<<14)) || !(val & (1<<13))) {
2272 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2274 } else if (!(val & (1<<15))) {
2275 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2276 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2277 it's MSB (bit 15) goes to 1 (indicating that the
2278 XAUI workaround has completed),
2279 then continue on with system initialization.*/
2280 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2281 bnx2x_cl45_read(bp, params->port,
2282 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2285 MDIO_PMA_REG_8073_XAUI_WA, &val);
2286 if (val & (1<<15)) {
2288 "XAUI workaround has completed\n");
2297 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2302 static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2307 /* Boot port from external ROM */
2309 bnx2x_cl45_write(bp, port,
2313 MDIO_PMA_REG_GEN_CTRL,
2316 /* ucode reboot and rst */
2317 bnx2x_cl45_write(bp, port,
2321 MDIO_PMA_REG_GEN_CTRL,
2324 bnx2x_cl45_write(bp, port,
2328 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2330 /* Reset internal microprocessor */
2331 bnx2x_cl45_write(bp, port,
2335 MDIO_PMA_REG_GEN_CTRL,
2336 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2338 /* Release srst bit */
2339 bnx2x_cl45_write(bp, port,
2343 MDIO_PMA_REG_GEN_CTRL,
2344 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2346 /* wait for 100ms for code download via SPI port */
2349 /* Clear ser_boot_ctl bit */
2350 bnx2x_cl45_write(bp, port,
2354 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2356 bnx2x_save_bcm_spirom_ver(bp, port,
2362 static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2366 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2367 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2371 static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2375 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2376 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2381 static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2383 struct bnx2x *bp = params->bp;
2384 u8 port = params->port;
2385 u8 ext_phy_addr = ((params->ext_phy_config &
2386 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2387 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2388 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2390 /* Need to wait 100ms after reset */
2393 /* Set serial boot control for external load */
2394 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2396 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2398 /* Micro controller re-boot */
2399 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2401 MDIO_PMA_REG_GEN_CTRL,
2402 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2404 /* Set soft reset */
2405 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2407 MDIO_PMA_REG_GEN_CTRL,
2408 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2410 /* Set PLL register value to be same like in P13 ver */
2411 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2413 MDIO_PMA_REG_PLL_CTRL,
2416 /* Clear soft reset.
2417 Will automatically reset micro-controller re-boot */
2418 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2420 MDIO_PMA_REG_GEN_CTRL,
2421 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2423 /* wait for 150ms for microcode load */
2426 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2427 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2429 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2432 bnx2x_save_bcm_spirom_ver(bp, port,
2435 params->shmem_base);
2438 static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
2439 u32 ext_phy_type, u8 ext_phy_addr,
2443 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
2445 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2446 bnx2x_cl45_read(bp, port,
2450 MDIO_PMA_REG_PHY_IDENTIFIER,
2458 bnx2x_cl45_write(bp, port,
2462 MDIO_PMA_REG_PHY_IDENTIFIER,
2466 static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
2467 u16 addr, u8 byte_cnt, u8 *o_buf)
2469 struct bnx2x *bp = params->bp;
2472 u8 port = params->port;
2473 u8 ext_phy_addr = ((params->ext_phy_config &
2474 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2475 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2476 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2477 if (byte_cnt > 16) {
2478 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2479 " is limited to 0xf\n");
2482 /* Set the read command byte count */
2483 bnx2x_cl45_write(bp, port,
2487 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2488 (byte_cnt | 0xa000));
2490 /* Set the read command address */
2491 bnx2x_cl45_write(bp, port,
2495 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2498 /* Activate read command */
2499 bnx2x_cl45_write(bp, port,
2503 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2506 /* Wait up to 500us for command complete status */
2507 for (i = 0; i < 100; i++) {
2508 bnx2x_cl45_read(bp, port,
2512 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2513 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2514 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2519 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2520 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2522 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2523 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2527 /* Read the buffer */
2528 for (i = 0; i < byte_cnt; i++) {
2529 bnx2x_cl45_read(bp, port,
2533 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2534 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2537 for (i = 0; i < 100; i++) {
2538 bnx2x_cl45_read(bp, port,
2542 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2543 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2544 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2551 static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2552 u16 addr, u8 byte_cnt, u8 *o_buf)
2554 struct bnx2x *bp = params->bp;
2556 u8 port = params->port;
2557 u8 ext_phy_addr = ((params->ext_phy_config &
2558 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2559 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2560 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2562 if (byte_cnt > 16) {
2563 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2564 " is limited to 0xf\n");
2568 /* Need to read from 1.8000 to clear it */
2569 bnx2x_cl45_read(bp, port,
2570 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2573 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2576 /* Set the read command byte count */
2577 bnx2x_cl45_write(bp, port,
2581 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2582 ((byte_cnt < 2) ? 2 : byte_cnt));
2584 /* Set the read command address */
2585 bnx2x_cl45_write(bp, port,
2589 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2591 /* Set the destination address */
2592 bnx2x_cl45_write(bp, port,
2597 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2599 /* Activate read command */
2600 bnx2x_cl45_write(bp, port,
2604 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2606 /* Wait appropriate time for two-wire command to finish before
2607 polling the status register */
2610 /* Wait up to 500us for command complete status */
2611 for (i = 0; i < 100; i++) {
2612 bnx2x_cl45_read(bp, port,
2616 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2617 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2618 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2623 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2624 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2626 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2627 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2631 /* Read the buffer */
2632 for (i = 0; i < byte_cnt; i++) {
2633 bnx2x_cl45_read(bp, port,
2637 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2638 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2641 for (i = 0; i < 100; i++) {
2642 bnx2x_cl45_read(bp, port,
2646 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2647 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2648 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2656 u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
2657 u8 byte_cnt, u8 *o_buf)
2659 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2661 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2662 return bnx2x_8726_read_sfp_module_eeprom(params, addr,
2664 else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2665 return bnx2x_8727_read_sfp_module_eeprom(params, addr,
2670 static u8 bnx2x_get_edc_mode(struct link_params *params,
2673 struct bnx2x *bp = params->bp;
2674 u8 val, check_limiting_mode = 0;
2675 *edc_mode = EDC_MODE_LIMITING;
2677 /* First check for copper cable */
2678 if (bnx2x_read_sfp_module_eeprom(params,
2679 SFP_EEPROM_CON_TYPE_ADDR,
2682 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
2687 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
2689 u8 copper_module_type;
2690 /* Check if its active cable( includes SFP+ module)
2692 if (bnx2x_read_sfp_module_eeprom(params,
2693 SFP_EEPROM_FC_TX_TECH_ADDR,
2695 &copper_module_type) !=
2698 "Failed to read copper-cable-type"
2699 " from SFP+ EEPROM\n");
2703 if (copper_module_type &
2704 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
2705 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
2706 check_limiting_mode = 1;
2707 } else if (copper_module_type &
2708 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
2709 DP(NETIF_MSG_LINK, "Passive Copper"
2710 " cable detected\n");
2712 EDC_MODE_PASSIVE_DAC;
2714 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
2715 "type 0x%x !!!\n", copper_module_type);
2720 case SFP_EEPROM_CON_TYPE_VAL_LC:
2721 DP(NETIF_MSG_LINK, "Optic module detected\n");
2722 check_limiting_mode = 1;
2726 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
2731 if (check_limiting_mode) {
2732 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2733 if (bnx2x_read_sfp_module_eeprom(params,
2734 SFP_EEPROM_OPTIONS_ADDR,
2735 SFP_EEPROM_OPTIONS_SIZE,
2737 DP(NETIF_MSG_LINK, "Failed to read Option"
2738 " field from module EEPROM\n");
2741 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
2742 *edc_mode = EDC_MODE_LINEAR;
2744 *edc_mode = EDC_MODE_LIMITING;
2746 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
2750 /* This function read the relevant field from the module ( SFP+ ),
2751 and verify it is compliant with this board */
2752 static u8 bnx2x_verify_sfp_module(struct link_params *params)
2754 struct bnx2x *bp = params->bp;
2757 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
2758 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
2760 val = REG_RD(bp, params->shmem_base +
2761 offsetof(struct shmem_region, dev_info.
2762 port_feature_config[params->port].config));
2763 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2764 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
2765 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
2769 /* Ask the FW to validate the module */
2770 if (!(params->feature_config_flags &
2771 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
2772 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
2777 fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
2778 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
2779 DP(NETIF_MSG_LINK, "Approved module\n");
2783 /* format the warning message */
2784 if (bnx2x_read_sfp_module_eeprom(params,
2785 SFP_EEPROM_VENDOR_NAME_ADDR,
2786 SFP_EEPROM_VENDOR_NAME_SIZE,
2788 vendor_name[0] = '\0';
2790 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2791 if (bnx2x_read_sfp_module_eeprom(params,
2792 SFP_EEPROM_PART_NO_ADDR,
2793 SFP_EEPROM_PART_NO_SIZE,
2795 vendor_pn[0] = '\0';
2797 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
2799 printk(KERN_INFO PFX "Warning: "
2800 "Unqualified SFP+ module "
2801 "detected on %s, Port %d from %s part number %s\n"
2802 , bp->dev->name, params->port,
2803 vendor_name, vendor_pn);
2807 static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
2810 struct bnx2x *bp = params->bp;
2811 u8 port = params->port;
2812 u8 ext_phy_addr = ((params->ext_phy_config &
2813 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2814 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2815 u16 cur_limiting_mode;
2817 bnx2x_cl45_read(bp, port,
2818 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2821 MDIO_PMA_REG_ROM_VER2,
2822 &cur_limiting_mode);
2823 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
2826 if (edc_mode == EDC_MODE_LIMITING) {
2828 "Setting LIMITING MODE\n");
2829 bnx2x_cl45_write(bp, port,
2830 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2833 MDIO_PMA_REG_ROM_VER2,
2835 } else { /* LRM mode ( default )*/
2837 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
2839 /* Changing to LRM mode takes quite few seconds.
2840 So do it only if current mode is limiting
2841 ( default is LRM )*/
2842 if (cur_limiting_mode != EDC_MODE_LIMITING)
2845 bnx2x_cl45_write(bp, port,
2846 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2849 MDIO_PMA_REG_LRM_MODE,
2851 bnx2x_cl45_write(bp, port,
2852 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2855 MDIO_PMA_REG_ROM_VER2,
2857 bnx2x_cl45_write(bp, port,
2858 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2861 MDIO_PMA_REG_MISC_CTRL0,
2863 bnx2x_cl45_write(bp, port,
2864 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2867 MDIO_PMA_REG_LRM_MODE,
2873 static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
2876 struct bnx2x *bp = params->bp;
2877 u8 port = params->port;
2880 u8 ext_phy_addr = ((params->ext_phy_config &
2881 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2882 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2884 bnx2x_cl45_read(bp, port,
2885 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2888 MDIO_PMA_REG_PHY_IDENTIFIER,
2891 bnx2x_cl45_write(bp, port,
2892 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2895 MDIO_PMA_REG_PHY_IDENTIFIER,
2896 (phy_identifier & ~(1<<9)));
2898 bnx2x_cl45_read(bp, port,
2899 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2902 MDIO_PMA_REG_ROM_VER2,
2904 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
2905 bnx2x_cl45_write(bp, port,
2906 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2909 MDIO_PMA_REG_ROM_VER2,
2910 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
2912 bnx2x_cl45_write(bp, port,
2913 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2916 MDIO_PMA_REG_PHY_IDENTIFIER,
2917 (phy_identifier | (1<<9)));
2923 static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
2926 struct bnx2x *bp = params->bp;
2928 /* Initialization time after hot-plug may take up to 300ms for some
2929 phys type ( e.g. JDSU ) */
2930 for (timeout = 0; timeout < 60; timeout++) {
2931 if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
2933 DP(NETIF_MSG_LINK, "SFP+ module initialization "
2934 "took %d ms\n", timeout * 5);
2942 static void bnx2x_8727_power_module(struct bnx2x *bp,
2943 struct link_params *params,
2944 u8 ext_phy_addr, u8 is_power_up) {
2945 /* Make sure GPIOs are not using for LED mode */
2947 u8 port = params->port;
2949 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
2950 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
2952 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
2953 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
2954 * where the 1st bit is the over-current(only input), and 2nd bit is
2955 * for power( only output )
2959 * In case of NOC feature is disabled and power is up, set GPIO control
2960 * as input to enable listening of over-current indication
2963 if (!(params->feature_config_flags &
2964 FEATURE_CONFIG_BCM8727_NOC) && is_power_up)
2968 * Set GPIO control to OUTPUT, and set the power bit
2969 * to according to the is_power_up
2971 val = ((!(is_power_up)) << 1);
2973 bnx2x_cl45_write(bp, port,
2974 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2977 MDIO_PMA_REG_8727_GPIO_CTRL,
2981 static u8 bnx2x_sfp_module_detection(struct link_params *params)
2983 struct bnx2x *bp = params->bp;
2986 u8 ext_phy_addr = ((params->ext_phy_config &
2987 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2988 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2989 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2990 u32 val = REG_RD(bp, params->shmem_base +
2991 offsetof(struct shmem_region, dev_info.
2992 port_feature_config[params->port].config));
2994 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
2997 if (bnx2x_get_edc_mode(params, &edc_mode) != 0) {
2998 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
3000 } else if (bnx2x_verify_sfp_module(params) !=
3002 /* check SFP+ module compatibility */
3003 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
3005 /* Turn on fault module-detected led */
3006 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3007 MISC_REGISTERS_GPIO_HIGH,
3009 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
3010 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3011 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
3012 /* Shutdown SFP+ module */
3013 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
3014 bnx2x_8727_power_module(bp, params,
3019 /* Turn off fault module-detected led */
3020 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
3021 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3022 MISC_REGISTERS_GPIO_LOW,
3026 /* power up the SFP module */
3027 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3028 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
3030 /* Check and set limiting mode / LRM mode on 8726.
3031 On 8727 it is done automatically */
3032 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3033 bnx2x_bcm8726_set_limiting_mode(params, edc_mode);
3035 bnx2x_bcm8727_set_limiting_mode(params, edc_mode);
3037 * Enable transmit for this module if the module is approved, or
3038 * if unapproved modules should also enable the Tx laser
3041 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
3042 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3043 bnx2x_sfp_set_transmitter(bp, params->port,
3044 ext_phy_type, ext_phy_addr, 1);
3046 bnx2x_sfp_set_transmitter(bp, params->port,
3047 ext_phy_type, ext_phy_addr, 0);
3052 void bnx2x_handle_module_detect_int(struct link_params *params)
3054 struct bnx2x *bp = params->bp;
3056 u8 port = params->port;
3057 /* Set valid module led off */
3058 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3059 MISC_REGISTERS_GPIO_HIGH,
3062 /* Get current gpio val refelecting module plugged in / out*/
3063 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
3065 /* Call the handling function in case module is detected */
3066 if (gpio_val == 0) {
3068 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3069 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3072 if (bnx2x_wait_for_sfp_module_initialized(params) ==
3074 bnx2x_sfp_module_detection(params);
3076 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3078 u8 ext_phy_addr = ((params->ext_phy_config &
3079 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3080 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3082 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3083 u32 val = REG_RD(bp, params->shmem_base +
3084 offsetof(struct shmem_region, dev_info.
3085 port_feature_config[params->port].
3088 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3089 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3091 /* Module was plugged out. */
3092 /* Disable transmit for this module */
3093 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3094 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3095 bnx2x_sfp_set_transmitter(bp, params->port,
3096 ext_phy_type, ext_phy_addr, 0);
3100 static void bnx2x_bcm807x_force_10G(struct link_params *params)
3102 struct bnx2x *bp = params->bp;
3103 u8 port = params->port;
3104 u8 ext_phy_addr = ((params->ext_phy_config &
3105 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3106 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3107 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3109 /* Force KR or KX */
3110 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3114 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3116 MDIO_PMA_REG_10G_CTRL2,
3118 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3120 MDIO_PMA_REG_BCM_CTRL,
3122 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3127 static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
3129 struct bnx2x *bp = params->bp;
3130 u8 port = params->port;
3132 u8 ext_phy_addr = ((params->ext_phy_config &
3133 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3134 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3135 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3137 bnx2x_cl45_read(bp, params->port,
3138 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3141 MDIO_PMA_REG_8073_CHIP_REV, &val);
3144 /* Mustn't set low power mode in 8073 A0 */
3148 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3149 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3151 MDIO_XS_PLL_SEQUENCER, &val);
3153 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3154 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3157 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3158 MDIO_XS_DEVAD, 0x805E, 0x1077);
3159 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3160 MDIO_XS_DEVAD, 0x805D, 0x0000);
3161 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3162 MDIO_XS_DEVAD, 0x805C, 0x030B);
3163 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3164 MDIO_XS_DEVAD, 0x805B, 0x1240);
3165 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3166 MDIO_XS_DEVAD, 0x805A, 0x2490);
3169 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3170 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3171 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3172 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3173 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3174 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3177 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3178 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3179 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3180 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3181 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3182 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3184 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3185 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3187 MDIO_XS_PLL_SEQUENCER, &val);
3189 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3190 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3193 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3194 struct link_vars *vars)
3197 struct bnx2x *bp = params->bp;
3199 u8 ext_phy_addr = ((params->ext_phy_config &
3200 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3201 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3202 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3204 bnx2x_cl45_read(bp, params->port,
3208 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3210 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3211 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3213 if ((vars->ieee_fc &
3214 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3215 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3216 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3218 if ((vars->ieee_fc &
3219 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3220 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3221 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3223 if ((vars->ieee_fc &
3224 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3225 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3226 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3229 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3231 bnx2x_cl45_write(bp, params->port,
3235 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3239 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3240 struct link_vars *vars)
3242 struct bnx2x *bp = params->bp;
3244 u8 ext_phy_addr = ((params->ext_phy_config &
3245 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3246 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3247 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3249 /* read modify write pause advertizing */
3250 bnx2x_cl45_read(bp, params->port,
3254 MDIO_AN_REG_ADV_PAUSE, &val);
3256 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3258 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3260 if ((vars->ieee_fc &
3261 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3262 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3263 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3265 if ((vars->ieee_fc &
3266 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3267 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3269 MDIO_AN_REG_ADV_PAUSE_PAUSE;
3272 "Ext phy AN advertize 0x%x\n", val);
3273 bnx2x_cl45_write(bp, params->port,
3277 MDIO_AN_REG_ADV_PAUSE, val);
3279 static void bnx2x_set_preemphasis(struct link_params *params)
3282 struct bnx2x *bp = params->bp;
3284 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3285 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3286 CL45_WR_OVER_CL22(bp, params->port,
3289 MDIO_RX0_RX_EQ_BOOST,
3290 params->xgxs_config_rx[i]);
3293 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3294 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3295 CL45_WR_OVER_CL22(bp, params->port,
3299 params->xgxs_config_tx[i]);
3304 static void bnx2x_8481_set_led4(struct link_params *params,
3305 u32 ext_phy_type, u8 ext_phy_addr)
3307 struct bnx2x *bp = params->bp;
3309 /* PHYC_CTL_LED_CTL */
3310 bnx2x_cl45_write(bp, params->port,
3314 MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
3316 /* Unmask LED4 for 10G link */
3317 bnx2x_cl45_write(bp, params->port,
3321 MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
3322 /* 'Interrupt Mask' */
3323 bnx2x_cl45_write(bp, params->port,
3329 static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
3330 u32 ext_phy_type, u8 ext_phy_addr)
3332 struct bnx2x *bp = params->bp;
3334 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3335 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3336 bnx2x_cl45_write(bp, params->port,
3340 MDIO_AN_REG_8481_LEGACY_SHADOW,
3341 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3344 static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3345 u32 ext_phy_type, u8 ext_phy_addr)
3347 struct bnx2x *bp = params->bp;
3350 /* LED1 (10G Link) */
3351 /* Enable continuse based on source 7(10G-link) */
3352 bnx2x_cl45_read(bp, params->port,
3356 MDIO_PMA_REG_8481_LINK_SIGNAL,
3358 /* Set bit 2 to 0, and bits [1:0] to 10 */
3359 val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/
3360 val1 |= (1<<1); /* Set bit 1 */
3362 bnx2x_cl45_write(bp, params->port,
3366 MDIO_PMA_REG_8481_LINK_SIGNAL,
3369 /* Unmask LED1 for 10G link */
3370 bnx2x_cl45_read(bp, params->port,
3374 MDIO_PMA_REG_8481_LED1_MASK,
3376 /* Set bit 2 to 0, and bits [1:0] to 10 */
3378 bnx2x_cl45_write(bp, params->port,
3382 MDIO_PMA_REG_8481_LED1_MASK,
3385 /* LED2 (1G/100/10G Link) */
3386 /* Mask LED2 for 10G link */
3387 bnx2x_cl45_write(bp, params->port,
3391 MDIO_PMA_REG_8481_LED2_MASK,
3394 /* LED3 (10G/1G/100/10G Activity) */
3395 bnx2x_cl45_read(bp, params->port,
3399 MDIO_PMA_REG_8481_LINK_SIGNAL,
3401 /* Enable blink based on source 4(Activity) */
3402 val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3403 val1 |= (1<<6); /* Set only bit 6 */
3404 bnx2x_cl45_write(bp, params->port,
3408 MDIO_PMA_REG_8481_LINK_SIGNAL,
3411 bnx2x_cl45_read(bp, params->port,
3415 MDIO_PMA_REG_8481_LED3_MASK,
3417 val1 |= (1<<4); /* Unmask LED3 for 10G link */
3418 bnx2x_cl45_write(bp, params->port,
3422 MDIO_PMA_REG_8481_LED3_MASK,
3427 static void bnx2x_init_internal_phy(struct link_params *params,
3428 struct link_vars *vars)
3430 struct bnx2x *bp = params->bp;
3431 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
3432 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3433 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3434 (params->feature_config_flags &
3435 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3436 bnx2x_set_preemphasis(params);
3438 /* forced speed requested? */
3439 if (vars->line_speed != SPEED_AUTO_NEG) {
3440 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3442 /* disable autoneg */
3443 bnx2x_set_autoneg(params, vars);
3445 /* program speed and duplex */
3446 bnx2x_program_serdes(params, vars);
3448 } else { /* AN_mode */
3449 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3452 bnx2x_set_brcm_cl37_advertisment(params);
3454 /* program duplex & pause advertisement (for aneg) */
3455 bnx2x_set_ieee_aneg_advertisment(params,
3458 /* enable autoneg */
3459 bnx2x_set_autoneg(params, vars);
3461 /* enable and restart AN */
3462 bnx2x_restart_autoneg(params);
3465 } else { /* SGMII mode */
3466 DP(NETIF_MSG_LINK, "SGMII\n");
3468 bnx2x_initialize_sgmii_process(params, vars);
3472 static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3474 struct bnx2x *bp = params->bp;
3481 if (vars->phy_flags & PHY_XGXS_FLAG) {
3482 ext_phy_addr = ((params->ext_phy_config &
3483 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3484 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3486 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3487 /* Make sure that the soft reset is off (expect for the 8072:
3488 * due to the lock, it will be done inside the specific
3491 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3492 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3493 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3494 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3495 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3496 /* Wait for soft reset to get cleared upto 1 sec */
3497 for (cnt = 0; cnt < 1000; cnt++) {
3498 bnx2x_cl45_read(bp, params->port,
3502 MDIO_PMA_REG_CTRL, &ctrl);
3503 if (!(ctrl & (1<<15)))
3507 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
3511 switch (ext_phy_type) {
3512 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3515 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3516 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3518 bnx2x_cl45_write(bp, params->port,
3522 MDIO_PMA_REG_MISC_CTRL,
3524 bnx2x_cl45_write(bp, params->port,
3528 MDIO_PMA_REG_PHY_IDENTIFIER,
3530 bnx2x_cl45_write(bp, params->port,
3534 MDIO_PMA_REG_CMU_PLL_BYPASS,
3536 bnx2x_cl45_write(bp, params->port,
3540 MDIO_WIS_REG_LASI_CNTL, 0x1);
3542 /* BCM8705 doesn't have microcode, hence the 0 */
3543 bnx2x_save_spirom_version(bp, params->port,
3544 params->shmem_base, 0);
3547 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3548 /* Wait until fw is loaded */
3549 for (cnt = 0; cnt < 100; cnt++) {
3550 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3551 ext_phy_addr, MDIO_PMA_DEVAD,
3552 MDIO_PMA_REG_ROM_VER1, &val);
3557 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3558 "after %d ms\n", cnt);
3559 if ((params->feature_config_flags &
3560 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3563 for (i = 0; i < 4; i++) {
3564 reg = MDIO_XS_8706_REG_BANK_RX0 +
3565 i*(MDIO_XS_8706_REG_BANK_RX1 -
3566 MDIO_XS_8706_REG_BANK_RX0);
3567 bnx2x_cl45_read(bp, params->port,
3572 /* Clear first 3 bits of the control */
3574 /* Set control bits according to
3576 val |= (params->xgxs_config_rx[i] &
3578 DP(NETIF_MSG_LINK, "Setting RX"
3579 "Equalizer to BCM8706 reg 0x%x"
3580 " <-- val 0x%x\n", reg, val);
3581 bnx2x_cl45_write(bp, params->port,
3589 /* First enable LASI */
3590 bnx2x_cl45_write(bp, params->port,
3594 MDIO_PMA_REG_RX_ALARM_CTRL,
3596 bnx2x_cl45_write(bp, params->port,
3600 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3602 if (params->req_line_speed == SPEED_10000) {
3603 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3605 bnx2x_cl45_write(bp, params->port,
3609 MDIO_PMA_REG_DIGITAL_CTRL,
3612 /* Force 1Gbps using autoneg with 1G
3615 /* Allow CL37 through CL73 */
3616 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3617 bnx2x_cl45_write(bp, params->port,
3621 MDIO_AN_REG_CL37_CL73,
3624 /* Enable Full-Duplex advertisment on CL37 */
3625 bnx2x_cl45_write(bp, params->port,
3629 MDIO_AN_REG_CL37_FC_LP,
3631 /* Enable CL37 AN */
3632 bnx2x_cl45_write(bp, params->port,
3636 MDIO_AN_REG_CL37_AN,
3639 bnx2x_cl45_write(bp, params->port,
3643 MDIO_AN_REG_ADV, (1<<5));
3645 /* Enable clause 73 AN */
3646 bnx2x_cl45_write(bp, params->port,
3654 bnx2x_save_bcm_spirom_ver(bp, params->port,
3657 params->shmem_base);
3659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3660 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3661 bnx2x_bcm8726_external_rom_boot(params);
3663 /* Need to call module detected on initialization since
3664 the module detection triggered by actual module
3665 insertion might occur before driver is loaded, and when
3666 driver is loaded, it reset all registers, including the
3668 bnx2x_sfp_module_detection(params);
3670 /* Set Flow control */
3671 bnx2x_ext_phy_set_pause(params, vars);
3672 if (params->req_line_speed == SPEED_1000) {
3673 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3674 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3675 ext_phy_addr, MDIO_PMA_DEVAD,
3676 MDIO_PMA_REG_CTRL, 0x40);
3677 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3678 ext_phy_addr, MDIO_PMA_DEVAD,
3679 MDIO_PMA_REG_10G_CTRL2, 0xD);
3680 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3681 ext_phy_addr, MDIO_PMA_DEVAD,
3682 MDIO_PMA_REG_LASI_CTRL, 0x5);
3683 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3684 ext_phy_addr, MDIO_PMA_DEVAD,
3685 MDIO_PMA_REG_RX_ALARM_CTRL,
3687 } else if ((params->req_line_speed ==
3689 ((params->speed_cap_mask &
3690 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
3691 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
3692 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3693 ext_phy_addr, MDIO_AN_DEVAD,
3694 MDIO_AN_REG_ADV, 0x20);
3695 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3696 ext_phy_addr, MDIO_AN_DEVAD,
3697 MDIO_AN_REG_CL37_CL73, 0x040c);
3698 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3699 ext_phy_addr, MDIO_AN_DEVAD,
3700 MDIO_AN_REG_CL37_FC_LD, 0x0020);
3701 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3702 ext_phy_addr, MDIO_AN_DEVAD,
3703 MDIO_AN_REG_CL37_AN, 0x1000);
3704 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3705 ext_phy_addr, MDIO_AN_DEVAD,
3706 MDIO_AN_REG_CTRL, 0x1200);
3708 /* Enable RX-ALARM control to receive
3709 interrupt for 1G speed change */
3710 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3711 ext_phy_addr, MDIO_PMA_DEVAD,
3712 MDIO_PMA_REG_LASI_CTRL, 0x4);
3713 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3714 ext_phy_addr, MDIO_PMA_DEVAD,
3715 MDIO_PMA_REG_RX_ALARM_CTRL,
3718 } else { /* Default 10G. Set only LASI control */
3719 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3720 ext_phy_addr, MDIO_PMA_DEVAD,
3721 MDIO_PMA_REG_LASI_CTRL, 1);
3724 /* Set TX PreEmphasis if needed */
3725 if ((params->feature_config_flags &
3726 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3727 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3729 params->xgxs_config_tx[0],
3730 params->xgxs_config_tx[1]);
3731 bnx2x_cl45_write(bp, params->port,
3735 MDIO_PMA_REG_8726_TX_CTRL1,
3736 params->xgxs_config_tx[0]);
3738 bnx2x_cl45_write(bp, params->port,
3742 MDIO_PMA_REG_8726_TX_CTRL2,
3743 params->xgxs_config_tx[1]);
3746 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3747 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3750 u16 rx_alarm_ctrl_val;
3753 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3754 rx_alarm_ctrl_val = 0x400;
3755 lasi_ctrl_val = 0x0004;
3757 rx_alarm_ctrl_val = (1<<2);
3758 lasi_ctrl_val = 0x0004;
3762 bnx2x_cl45_write(bp, params->port,
3766 MDIO_PMA_REG_RX_ALARM_CTRL,
3769 bnx2x_cl45_write(bp, params->port,
3773 MDIO_PMA_REG_LASI_CTRL,
3776 bnx2x_8073_set_pause_cl37(params, vars);
3779 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
3780 bnx2x_bcm8072_external_rom_boot(params);
3783 /* In case of 8073 with long xaui lines,
3784 don't set the 8073 xaui low power*/
3785 bnx2x_bcm8073_set_xaui_low_power_mode(params);
3788 bnx2x_cl45_read(bp, params->port,
3792 MDIO_PMA_REG_M8051_MSGOUT_REG,
3795 bnx2x_cl45_read(bp, params->port,
3799 MDIO_PMA_REG_RX_ALARM, &tmp1);
3801 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
3804 /* If this is forced speed, set to KR or KX
3805 * (all other are not supported)
3807 if (params->loopback_mode == LOOPBACK_EXT) {
3808 bnx2x_bcm807x_force_10G(params);
3810 "Forced speed 10G on 807X\n");
3813 bnx2x_cl45_write(bp, params->port,
3814 ext_phy_type, ext_phy_addr,
3816 MDIO_PMA_REG_BCM_CTRL,
3819 if (params->req_line_speed != SPEED_AUTO_NEG) {
3820 if (params->req_line_speed == SPEED_10000) {
3822 } else if (params->req_line_speed ==
3825 /* Note that 2.5G works only
3826 when used with 1G advertisment */
3832 if (params->speed_cap_mask &
3833 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3836 /* Note that 2.5G works only when
3837 used with 1G advertisment */
3838 if (params->speed_cap_mask &
3839 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3840 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
3843 "807x autoneg val = 0x%x\n", val);
3846 bnx2x_cl45_write(bp, params->port,
3850 MDIO_AN_REG_ADV, val);
3853 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3855 bnx2x_cl45_read(bp, params->port,
3859 MDIO_AN_REG_8073_2_5G, &tmp1);
3861 if (((params->speed_cap_mask &
3862 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
3863 (params->req_line_speed ==
3865 (params->req_line_speed ==
3868 /* Allow 2.5G for A1 and above */
3869 bnx2x_cl45_read(bp, params->port,
3870 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3873 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
3874 DP(NETIF_MSG_LINK, "Add 2.5G\n");
3880 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
3884 bnx2x_cl45_write(bp, params->port,
3888 MDIO_AN_REG_8073_2_5G, tmp1);
3891 /* Add support for CL37 (passive mode) II */
3893 bnx2x_cl45_read(bp, params->port,
3897 MDIO_AN_REG_CL37_FC_LD,
3900 bnx2x_cl45_write(bp, params->port,
3904 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
3905 ((params->req_duplex == DUPLEX_FULL) ?
3908 /* Add support for CL37 (passive mode) III */
3909 bnx2x_cl45_write(bp, params->port,
3913 MDIO_AN_REG_CL37_AN, 0x1000);
3916 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3917 /* The SNR will improve about 2db by changing
3918 BW and FEE main tap. Rest commands are executed
3920 /*Change FFE main cursor to 5 in EDC register*/
3921 if (bnx2x_8073_is_snr_needed(params))
3922 bnx2x_cl45_write(bp, params->port,
3926 MDIO_PMA_REG_EDC_FFE_MAIN,
3929 /* Enable FEC (Forware Error Correction)
3930 Request in the AN */
3931 bnx2x_cl45_read(bp, params->port,
3935 MDIO_AN_REG_ADV2, &tmp1);
3939 bnx2x_cl45_write(bp, params->port,
3943 MDIO_AN_REG_ADV2, tmp1);
3947 bnx2x_ext_phy_set_pause(params, vars);
3949 /* Restart autoneg */
3951 bnx2x_cl45_write(bp, params->port,
3955 MDIO_AN_REG_CTRL, 0x1200);
3956 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
3957 "Advertise 1G=%x, 10G=%x\n",
3958 ((val & (1<<5)) > 0),
3959 ((val & (1<<7)) > 0));
3963 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
3966 u16 rx_alarm_ctrl_val;
3969 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
3972 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
3973 lasi_ctrl_val = 0x0004;
3975 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
3977 bnx2x_cl45_write(bp, params->port,
3981 MDIO_PMA_REG_RX_ALARM_CTRL,
3984 bnx2x_cl45_write(bp, params->port,
3988 MDIO_PMA_REG_LASI_CTRL,
3991 /* Initially configure MOD_ABS to interrupt when
3992 module is presence( bit 8) */
3993 bnx2x_cl45_read(bp, params->port,
3997 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
3998 /* Set EDC off by setting OPTXLOS signal input to low
4000 When the EDC is off it locks onto a reference clock and
4001 avoids becoming 'lost'.*/
4002 mod_abs &= ~((1<<8) | (1<<9));
4003 bnx2x_cl45_write(bp, params->port,
4007 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4009 /* Make MOD_ABS give interrupt on change */
4010 bnx2x_cl45_read(bp, params->port,
4014 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4017 bnx2x_cl45_write(bp, params->port,
4021 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4024 /* Set 8727 GPIOs to input to allow reading from the
4025 8727 GPIO0 status which reflect SFP+ module
4028 bnx2x_cl45_read(bp, params->port,
4029 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4032 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4034 val &= 0xff8f; /* Reset bits 4-6 */
4035 bnx2x_cl45_write(bp, params->port,
4036 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4039 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4042 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
4043 bnx2x_bcm8073_set_xaui_low_power_mode(params);
4045 bnx2x_cl45_read(bp, params->port,
4049 MDIO_PMA_REG_M8051_MSGOUT_REG,
4052 bnx2x_cl45_read(bp, params->port,
4056 MDIO_PMA_REG_RX_ALARM, &tmp1);
4058 /* Set option 1G speed */
4059 if (params->req_line_speed == SPEED_1000) {
4061 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4062 bnx2x_cl45_write(bp, params->port,
4066 MDIO_PMA_REG_CTRL, 0x40);
4067 bnx2x_cl45_write(bp, params->port,
4071 MDIO_PMA_REG_10G_CTRL2, 0xD);
4072 bnx2x_cl45_read(bp, params->port,
4076 MDIO_PMA_REG_10G_CTRL2, &tmp1);
4077 DP(NETIF_MSG_LINK, "1.7 = 0x%x \n", tmp1);
4079 } else if ((params->req_line_speed ==
4081 ((params->speed_cap_mask &
4082 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
4084 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
4085 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4086 ext_phy_addr, MDIO_AN_DEVAD,
4087 MDIO_PMA_REG_8727_MISC_CTRL, 0);
4088 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4089 ext_phy_addr, MDIO_AN_DEVAD,
4090 MDIO_AN_REG_CL37_AN, 0x1300);
4092 /* Since the 8727 has only single reset pin,
4093 need to set the 10G registers although it is
4095 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4096 ext_phy_addr, MDIO_AN_DEVAD,
4097 MDIO_AN_REG_CTRL, 0x0020);
4098 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4099 ext_phy_addr, MDIO_AN_DEVAD,
4101 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4102 ext_phy_addr, MDIO_PMA_DEVAD,
4103 MDIO_PMA_REG_CTRL, 0x2040);
4104 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4105 ext_phy_addr, MDIO_PMA_DEVAD,
4106 MDIO_PMA_REG_10G_CTRL2, 0x0008);
4109 /* Set 2-wire transfer rate to 400Khz since 100Khz
4110 is not operational */
4111 bnx2x_cl45_write(bp, params->port,
4115 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4118 /* Set TX PreEmphasis if needed */
4119 if ((params->feature_config_flags &
4120 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4121 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4123 params->xgxs_config_tx[0],
4124 params->xgxs_config_tx[1]);
4125 bnx2x_cl45_write(bp, params->port,
4129 MDIO_PMA_REG_8727_TX_CTRL1,
4130 params->xgxs_config_tx[0]);
4132 bnx2x_cl45_write(bp, params->port,
4136 MDIO_PMA_REG_8727_TX_CTRL2,
4137 params->xgxs_config_tx[1]);
4143 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4145 u16 fw_ver1, fw_ver2;
4147 "Setting the SFX7101 LASI indication\n");
4149 bnx2x_cl45_write(bp, params->port,
4153 MDIO_PMA_REG_LASI_CTRL, 0x1);
4155 "Setting the SFX7101 LED to blink on traffic\n");
4156 bnx2x_cl45_write(bp, params->port,
4160 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4162 bnx2x_ext_phy_set_pause(params, vars);
4163 /* Restart autoneg */
4164 bnx2x_cl45_read(bp, params->port,
4168 MDIO_AN_REG_CTRL, &val);
4170 bnx2x_cl45_write(bp, params->port,
4174 MDIO_AN_REG_CTRL, val);
4176 /* Save spirom version */
4177 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4178 ext_phy_addr, MDIO_PMA_DEVAD,
4179 MDIO_PMA_REG_7101_VER1, &fw_ver1);
4181 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4182 ext_phy_addr, MDIO_PMA_DEVAD,
4183 MDIO_PMA_REG_7101_VER2, &fw_ver2);
4185 bnx2x_save_spirom_version(params->bp, params->port,
4187 (u32)(fw_ver1<<16 | fw_ver2));
4191 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
4192 /* This phy uses the NIG latch mechanism since link
4193 indication arrives through its LED4 and not via
4194 its LASI signal, so we get steady signal
4195 instead of clear on read */
4196 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4197 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4199 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4200 if (params->req_line_speed == SPEED_AUTO_NEG) {
4202 u16 autoneg_val, an_1000_val, an_10_100_val;
4203 /* set 1000 speed advertisement */
4204 bnx2x_cl45_read(bp, params->port,
4208 MDIO_AN_REG_8481_1000T_CTRL,
4211 if (params->speed_cap_mask &
4212 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
4213 an_1000_val |= (1<<8);
4214 if (params->req_duplex == DUPLEX_FULL)
4215 an_1000_val |= (1<<9);
4216 DP(NETIF_MSG_LINK, "Advertising 1G\n");
4218 an_1000_val &= ~((1<<8) | (1<<9));
4220 bnx2x_cl45_write(bp, params->port,
4224 MDIO_AN_REG_8481_1000T_CTRL,
4227 /* set 100 speed advertisement */
4228 bnx2x_cl45_read(bp, params->port,
4232 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4235 if (params->speed_cap_mask &
4236 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4237 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
4238 an_10_100_val |= (1<<7);
4239 if (params->req_duplex == DUPLEX_FULL)
4240 an_10_100_val |= (1<<8);
4242 "Advertising 100M\n");
4244 an_10_100_val &= ~((1<<7) | (1<<8));
4246 /* set 10 speed advertisement */
4247 if (params->speed_cap_mask &
4248 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4249 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
4250 an_10_100_val |= (1<<5);
4251 if (params->req_duplex == DUPLEX_FULL)
4252 an_10_100_val |= (1<<6);
4253 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4256 an_10_100_val &= ~((1<<5) | (1<<6));
4258 bnx2x_cl45_write(bp, params->port,
4262 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4265 bnx2x_cl45_read(bp, params->port,
4269 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4272 /* Disable forced speed */
4273 autoneg_val &= ~(1<<6|1<<13);
4275 /* Enable autoneg and restart autoneg
4276 for legacy speeds */
4277 autoneg_val |= (1<<9|1<<12);
4279 if (params->req_duplex == DUPLEX_FULL)
4280 autoneg_val |= (1<<8);
4282 autoneg_val &= ~(1<<8);
4284 bnx2x_cl45_write(bp, params->port,
4288 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4291 if (params->speed_cap_mask &
4292 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4293 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4294 /* Restart autoneg for 10G*/
4295 bnx2x_cl45_read(bp, params->port,
4299 MDIO_AN_REG_CTRL, &val);
4301 bnx2x_cl45_write(bp, params->port,
4305 MDIO_AN_REG_CTRL, val);
4309 u16 autoneg_ctrl, pma_ctrl;
4310 bnx2x_cl45_read(bp, params->port,
4314 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4317 /* Disable autoneg */
4318 autoneg_ctrl &= ~(1<<12);
4320 /* Set 1000 force */
4321 switch (params->req_line_speed) {
4324 "Unable to set 10G force !\n");
4327 bnx2x_cl45_read(bp, params->port,
4333 autoneg_ctrl &= ~(1<<13);
4334 autoneg_ctrl |= (1<<6);
4335 pma_ctrl &= ~(1<<13);
4338 "Setting 1000M force\n");
4339 bnx2x_cl45_write(bp, params->port,
4347 autoneg_ctrl |= (1<<13);
4348 autoneg_ctrl &= ~(1<<6);
4350 "Setting 100M force\n");
4353 autoneg_ctrl &= ~(1<<13);
4354 autoneg_ctrl &= ~(1<<6);
4356 "Setting 10M force\n");
4361 if (params->req_duplex == DUPLEX_FULL) {
4362 autoneg_ctrl |= (1<<8);
4364 "Setting full duplex\n");
4366 autoneg_ctrl &= ~(1<<8);
4368 /* Update autoneg ctrl and pma ctrl */
4369 bnx2x_cl45_write(bp, params->port,
4373 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4377 /* Save spirom version */
4378 bnx2x_save_8481_spirom_version(bp, params->port,
4380 params->shmem_base);
4382 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4384 "XGXS PHY Failure detected 0x%x\n",
4385 params->ext_phy_config);
4389 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
4390 params->ext_phy_config);
4395 } else { /* SerDes */
4397 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
4398 switch (ext_phy_type) {
4399 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
4400 DP(NETIF_MSG_LINK, "SerDes Direct\n");
4403 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
4404 DP(NETIF_MSG_LINK, "SerDes 5482\n");
4408 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
4409 params->ext_phy_config);
4416 static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4418 struct bnx2x *bp = params->bp;
4419 u16 mod_abs, rx_alarm_status;
4420 u8 ext_phy_addr = ((params->ext_phy_config &
4421 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4422 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4423 u32 val = REG_RD(bp, params->shmem_base +
4424 offsetof(struct shmem_region, dev_info.
4425 port_feature_config[params->port].
4427 bnx2x_cl45_read(bp, params->port,
4428 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4431 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4432 if (mod_abs & (1<<8)) {
4434 /* Module is absent */
4435 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4436 "show module is absent\n");
4438 /* 1. Set mod_abs to detect next module
4440 2. Set EDC off by setting OPTXLOS signal input to low
4442 When the EDC is off it locks onto a reference clock and
4443 avoids becoming 'lost'.*/
4444 mod_abs &= ~((1<<8)|(1<<9));
4445 bnx2x_cl45_write(bp, params->port,
4446 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4449 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4451 /* Clear RX alarm since it stays up as long as
4452 the mod_abs wasn't changed */
4453 bnx2x_cl45_read(bp, params->port,
4454 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4457 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4460 /* Module is present */
4461 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4462 "show module is present\n");
4463 /* First thing, disable transmitter,
4464 and if the module is ok, the
4465 module_detection will enable it*/
4467 /* 1. Set mod_abs to detect next module
4468 absent event ( bit 8)
4469 2. Restore the default polarity of the OPRXLOS signal and
4470 this signal will then correctly indicate the presence or
4471 absence of the Rx signal. (bit 9) */
4472 mod_abs |= ((1<<8)|(1<<9));
4473 bnx2x_cl45_write(bp, params->port,
4474 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4477 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4479 /* Clear RX alarm since it stays up as long as
4480 the mod_abs wasn't changed. This is need to be done
4481 before calling the module detection, otherwise it will clear
4482 the link update alarm */
4483 bnx2x_cl45_read(bp, params->port,
4484 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4487 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4490 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4491 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4492 bnx2x_sfp_set_transmitter(bp, params->port,
4493 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4496 if (bnx2x_wait_for_sfp_module_initialized(params)
4498 bnx2x_sfp_module_detection(params);
4500 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4503 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4505 /* No need to check link status in case of
4506 module plugged in/out */
4510 static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4511 struct link_vars *vars,
4514 struct bnx2x *bp = params->bp;
4518 u16 rx_sd, pcs_status;
4519 u8 ext_phy_link_up = 0;
4520 u8 port = params->port;
4521 if (vars->phy_flags & PHY_XGXS_FLAG) {
4522 ext_phy_addr = ((params->ext_phy_config &
4523 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4524 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4526 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4527 switch (ext_phy_type) {
4528 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4529 DP(NETIF_MSG_LINK, "XGXS Direct\n");
4530 ext_phy_link_up = 1;
4533 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4534 DP(NETIF_MSG_LINK, "XGXS 8705\n");
4535 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4538 MDIO_WIS_REG_LASI_STATUS, &val1);
4539 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4541 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4544 MDIO_WIS_REG_LASI_STATUS, &val1);
4545 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4547 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4550 MDIO_PMA_REG_RX_SD, &rx_sd);
4552 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4556 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4561 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4562 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9))
4563 && ((val1 & (1<<8)) == 0));
4564 if (ext_phy_link_up)
4565 vars->line_speed = SPEED_10000;
4568 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
4569 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4570 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4572 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4574 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4576 /* clear LASI indication*/
4577 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4579 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4581 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4583 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4585 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4586 "0x%x\n", val1, val2);
4588 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4590 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
4592 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4594 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
4596 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4598 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4600 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4602 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4605 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
4606 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4607 rx_sd, pcs_status, val2);
4608 /* link is up if both bit 0 of pmd_rx_sd and
4609 * bit 0 of pcs_status are set, or if the autoneg bit
4612 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
4614 if (ext_phy_link_up) {
4616 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
4617 /* If transmitter is disabled,
4618 ignore false link up indication */
4619 bnx2x_cl45_read(bp, params->port,
4623 MDIO_PMA_REG_PHY_IDENTIFIER,
4625 if (val1 & (1<<15)) {
4626 DP(NETIF_MSG_LINK, "Tx is "
4628 ext_phy_link_up = 0;
4634 vars->line_speed = SPEED_1000;
4636 vars->line_speed = SPEED_10000;
4640 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4642 u16 link_status = 0;
4643 u16 rx_alarm_status;
4644 /* Check the LASI */
4645 bnx2x_cl45_read(bp, params->port,
4649 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4651 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4654 bnx2x_cl45_read(bp, params->port,
4658 MDIO_PMA_REG_LASI_STATUS, &val1);
4661 "8727 LASI status 0x%x\n",
4665 bnx2x_cl45_read(bp, params->port,
4669 MDIO_PMA_REG_M8051_MSGOUT_REG,
4673 * If a module is present and there is need to check
4676 if (!(params->feature_config_flags &
4677 FEATURE_CONFIG_BCM8727_NOC) &&
4678 !(rx_alarm_status & (1<<5))) {
4679 /* Check over-current using 8727 GPIO0 input*/
4680 bnx2x_cl45_read(bp, params->port,
4684 MDIO_PMA_REG_8727_GPIO_CTRL,
4687 if ((val1 & (1<<8)) == 0) {
4688 DP(NETIF_MSG_LINK, "8727 Power fault"
4689 " has been detected on port"
4690 " %d\n", params->port);
4691 printk(KERN_ERR PFX "Error: Power"
4692 " fault on %s Port %d has"
4693 " been detected and the"
4694 " power to that SFP+ module"
4695 " has been removed to prevent"
4696 " failure of the card. Please"
4697 " remove the SFP+ module and"
4698 " restart the system to clear"
4700 , bp->dev->name, params->port);
4702 * Disable all RX_ALARMs except for
4705 bnx2x_cl45_write(bp, params->port,
4709 MDIO_PMA_REG_RX_ALARM_CTRL,
4712 bnx2x_cl45_read(bp, params->port,
4716 MDIO_PMA_REG_PHY_IDENTIFIER,
4718 /* Wait for module_absent_event */
4720 bnx2x_cl45_write(bp, params->port,
4724 MDIO_PMA_REG_PHY_IDENTIFIER,
4726 /* Clear RX alarm */
4727 bnx2x_cl45_read(bp, params->port,
4731 MDIO_PMA_REG_RX_ALARM,
4735 } /* Over current check */
4737 /* When module absent bit is set, check module */
4738 if (rx_alarm_status & (1<<5)) {
4739 bnx2x_8727_handle_mod_abs(params);
4740 /* Enable all mod_abs and link detection bits */
4741 bnx2x_cl45_write(bp, params->port,
4745 MDIO_PMA_REG_RX_ALARM_CTRL,
4749 /* If transmitter is disabled,
4750 ignore false link up indication */
4751 bnx2x_cl45_read(bp, params->port,
4755 MDIO_PMA_REG_PHY_IDENTIFIER,
4757 if (val1 & (1<<15)) {
4758 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4759 ext_phy_link_up = 0;
4763 bnx2x_cl45_read(bp, params->port,
4767 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4770 /* Bits 0..2 --> speed detected,
4771 bits 13..15--> link is down */
4772 if ((link_status & (1<<2)) &&
4773 (!(link_status & (1<<15)))) {
4774 ext_phy_link_up = 1;
4775 vars->line_speed = SPEED_10000;
4776 } else if ((link_status & (1<<0)) &&
4777 (!(link_status & (1<<13)))) {
4778 ext_phy_link_up = 1;
4779 vars->line_speed = SPEED_1000;
4781 "port %x: External link"
4782 " up in 1G\n", params->port);
4784 ext_phy_link_up = 0;
4786 "port %x: External link"
4787 " is down\n", params->port);
4792 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4793 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4795 u16 link_status = 0;
4796 u16 an1000_status = 0;
4798 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
4799 bnx2x_cl45_read(bp, params->port,
4803 MDIO_PCS_REG_LASI_STATUS, &val1);
4804 bnx2x_cl45_read(bp, params->port,
4808 MDIO_PCS_REG_LASI_STATUS, &val2);
4810 "870x LASI status 0x%x->0x%x\n",
4814 /* In 8073, port1 is directed through emac0 and
4815 * port0 is directed through emac1
4817 bnx2x_cl45_read(bp, params->port,
4821 MDIO_PMA_REG_LASI_STATUS, &val1);
4824 "8703 LASI status 0x%x\n",
4828 /* clear the interrupt LASI status register */
4829 bnx2x_cl45_read(bp, params->port,
4833 MDIO_PCS_REG_STATUS, &val2);
4834 bnx2x_cl45_read(bp, params->port,
4838 MDIO_PCS_REG_STATUS, &val1);
4839 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
4842 bnx2x_cl45_read(bp, params->port,
4846 MDIO_PMA_REG_M8051_MSGOUT_REG,
4849 /* Check the LASI */
4850 bnx2x_cl45_read(bp, params->port,
4854 MDIO_PMA_REG_RX_ALARM, &val2);
4856 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4858 /* Check the link status */
4859 bnx2x_cl45_read(bp, params->port,
4863 MDIO_PCS_REG_STATUS, &val2);
4864 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4866 bnx2x_cl45_read(bp, params->port,
4870 MDIO_PMA_REG_STATUS, &val2);
4871 bnx2x_cl45_read(bp, params->port,
4875 MDIO_PMA_REG_STATUS, &val1);
4876 ext_phy_link_up = ((val1 & 4) == 4);
4877 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4879 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4881 if (ext_phy_link_up &&
4882 ((params->req_line_speed !=
4884 if (bnx2x_bcm8073_xaui_wa(params)
4886 ext_phy_link_up = 0;
4890 bnx2x_cl45_read(bp, params->port,
4894 MDIO_AN_REG_LINK_STATUS,
4896 bnx2x_cl45_read(bp, params->port,
4900 MDIO_AN_REG_LINK_STATUS,
4903 /* Check the link status on 1.1.2 */
4904 bnx2x_cl45_read(bp, params->port,
4908 MDIO_PMA_REG_STATUS, &val2);
4909 bnx2x_cl45_read(bp, params->port,
4913 MDIO_PMA_REG_STATUS, &val1);
4914 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4915 "an_link_status=0x%x\n",
4916 val2, val1, an1000_status);
4918 ext_phy_link_up = (((val1 & 4) == 4) ||
4919 (an1000_status & (1<<1)));
4920 if (ext_phy_link_up &&
4921 bnx2x_8073_is_snr_needed(params)) {
4922 /* The SNR will improve about 2dbby
4923 changing the BW and FEE main tap.*/
4925 /* The 1st write to change FFE main
4926 tap is set before restart AN */
4927 /* Change PLL Bandwidth in EDC
4929 bnx2x_cl45_write(bp, port, ext_phy_type,
4932 MDIO_PMA_REG_PLL_BANDWIDTH,
4935 /* Change CDR Bandwidth in EDC
4937 bnx2x_cl45_write(bp, port, ext_phy_type,
4940 MDIO_PMA_REG_CDR_BANDWIDTH,
4945 bnx2x_cl45_read(bp, params->port,
4949 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4952 /* Bits 0..2 --> speed detected,
4953 bits 13..15--> link is down */
4954 if ((link_status & (1<<2)) &&
4955 (!(link_status & (1<<15)))) {
4956 ext_phy_link_up = 1;
4957 vars->line_speed = SPEED_10000;
4959 "port %x: External link"
4960 " up in 10G\n", params->port);
4961 } else if ((link_status & (1<<1)) &&
4962 (!(link_status & (1<<14)))) {
4963 ext_phy_link_up = 1;
4964 vars->line_speed = SPEED_2500;
4966 "port %x: External link"
4967 " up in 2.5G\n", params->port);
4968 } else if ((link_status & (1<<0)) &&
4969 (!(link_status & (1<<13)))) {
4970 ext_phy_link_up = 1;
4971 vars->line_speed = SPEED_1000;
4973 "port %x: External link"
4974 " up in 1G\n", params->port);
4976 ext_phy_link_up = 0;
4978 "port %x: External link"
4979 " is down\n", params->port);
4982 /* See if 1G link is up for the 8072 */
4983 bnx2x_cl45_read(bp, params->port,
4987 MDIO_AN_REG_LINK_STATUS,
4989 bnx2x_cl45_read(bp, params->port,
4993 MDIO_AN_REG_LINK_STATUS,
4995 if (an1000_status & (1<<1)) {
4996 ext_phy_link_up = 1;
4997 vars->line_speed = SPEED_1000;
4999 "port %x: External link"
5000 " up in 1G\n", params->port);
5001 } else if (ext_phy_link_up) {
5002 ext_phy_link_up = 1;
5003 vars->line_speed = SPEED_10000;
5005 "port %x: External link"
5006 " up in 10G\n", params->port);
5013 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5014 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5017 MDIO_PMA_REG_LASI_STATUS, &val2);
5018 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5021 MDIO_PMA_REG_LASI_STATUS, &val1);
5023 "10G-base-T LASI status 0x%x->0x%x\n",
5025 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5028 MDIO_PMA_REG_STATUS, &val2);
5029 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5032 MDIO_PMA_REG_STATUS, &val1);
5034 "10G-base-T PMA status 0x%x->0x%x\n",
5036 ext_phy_link_up = ((val1 & 4) == 4);
5038 * print the AN outcome of the SFX7101 PHY
5040 if (ext_phy_link_up) {
5041 bnx2x_cl45_read(bp, params->port,
5045 MDIO_AN_REG_MASTER_STATUS,
5047 vars->line_speed = SPEED_10000;
5049 "SFX7101 AN status 0x%x->Master=%x\n",
5054 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5055 /* Check 10G-BaseT link status */
5056 /* Check PMD signal ok */
5057 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5062 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5065 MDIO_PMA_REG_8481_PMD_SIGNAL,
5067 DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
5069 /* Check link 10G */
5070 if (val2 & (1<<11)) {
5071 vars->line_speed = SPEED_10000;
5072 ext_phy_link_up = 1;
5073 bnx2x_8481_set_10G_led_mode(params,
5076 } else { /* Check Legacy speed link */
5077 u16 legacy_status, legacy_speed;
5079 /* Enable expansion register 0x42
5080 (Operation mode status) */
5081 bnx2x_cl45_write(bp, params->port,
5085 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
5088 /* Get legacy speed operation status */
5089 bnx2x_cl45_read(bp, params->port,
5093 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5096 DP(NETIF_MSG_LINK, "Legacy speed status"
5097 " = 0x%x\n", legacy_status);
5098 ext_phy_link_up = ((legacy_status & (1<<11))
5100 if (ext_phy_link_up) {
5101 legacy_speed = (legacy_status & (3<<9));
5102 if (legacy_speed == (0<<9))
5103 vars->line_speed = SPEED_10;
5104 else if (legacy_speed == (1<<9))
5107 else if (legacy_speed == (2<<9))
5110 else /* Should not happen */
5111 vars->line_speed = 0;
5113 if (legacy_status & (1<<8))
5114 vars->duplex = DUPLEX_FULL;
5116 vars->duplex = DUPLEX_HALF;
5118 DP(NETIF_MSG_LINK, "Link is up "
5119 "in %dMbps, is_duplex_full"
5122 (vars->duplex == DUPLEX_FULL));
5123 bnx2x_8481_set_legacy_led_mode(params,
5131 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
5132 params->ext_phy_config);
5133 ext_phy_link_up = 0;
5137 } else { /* SerDes */
5138 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5139 switch (ext_phy_type) {
5140 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
5141 DP(NETIF_MSG_LINK, "SerDes Direct\n");
5142 ext_phy_link_up = 1;
5145 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
5146 DP(NETIF_MSG_LINK, "SerDes 5482\n");
5147 ext_phy_link_up = 1;
5152 "BAD SerDes ext_phy_config 0x%x\n",
5153 params->ext_phy_config);
5154 ext_phy_link_up = 0;
5159 return ext_phy_link_up;
5162 static void bnx2x_link_int_enable(struct link_params *params)
5164 u8 port = params->port;
5167 struct bnx2x *bp = params->bp;
5168 /* setting the status to report on link up
5169 for either XGXS or SerDes */
5171 if (params->switch_cfg == SWITCH_CFG_10G) {
5172 mask = (NIG_MASK_XGXS0_LINK10G |
5173 NIG_MASK_XGXS0_LINK_STATUS);
5174 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5175 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5176 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5177 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
5179 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
5180 mask |= NIG_MASK_MI_INT;
5181 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5184 } else { /* SerDes */
5185 mask = NIG_MASK_SERDES0_LINK_STATUS;
5186 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5187 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5188 if ((ext_phy_type !=
5189 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
5191 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
5192 mask |= NIG_MASK_MI_INT;
5193 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5197 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5199 DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port,
5200 (params->switch_cfg == SWITCH_CFG_10G),
5201 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5203 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5204 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5205 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5206 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5207 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5208 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5209 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5212 static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
5215 u32 latch_status = 0, is_mi_int_status;
5216 /* Disable the MI INT ( external phy int )
5217 * by writing 1 to the status register. Link down indication
5218 * is high-active-signal, so in this case we need to write the
5219 * status to clear the XOR
5221 /* Read Latched signals */
5222 latch_status = REG_RD(bp,
5223 NIG_REG_LATCH_STATUS_0 + port*8);
5224 is_mi_int_status = REG_RD(bp,
5225 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
5226 DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
5227 "latch_status = 0x%x\n",
5228 is_mi_int, is_mi_int_status, latch_status);
5229 /* Handle only those with latched-signal=up.*/
5230 if (latch_status & 1) {
5231 /* For all latched-signal=up,Write original_signal to status */
5234 NIG_REG_STATUS_INTERRUPT_PORT0
5236 NIG_STATUS_EMAC0_MI_INT);
5239 NIG_REG_STATUS_INTERRUPT_PORT0
5241 NIG_STATUS_EMAC0_MI_INT);
5242 /* For all latched-signal=up : Re-Arm Latch signals */
5243 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5244 (latch_status & 0xfffe) | (latch_status & 1));
5250 static void bnx2x_link_int_ack(struct link_params *params,
5251 struct link_vars *vars, u8 is_10g,
5254 struct bnx2x *bp = params->bp;
5255 u8 port = params->port;
5257 /* first reset all status
5258 * we assume only one line will be change at a time */
5259 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5260 (NIG_STATUS_XGXS0_LINK10G |
5261 NIG_STATUS_XGXS0_LINK_STATUS |
5262 NIG_STATUS_SERDES0_LINK_STATUS));
5263 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5264 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
5265 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5267 if (vars->phy_link_up) {
5269 /* Disable the 10G link interrupt
5270 * by writing 1 to the status register
5272 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
5274 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5275 NIG_STATUS_XGXS0_LINK10G);
5277 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5278 /* Disable the link interrupt
5279 * by writing 1 to the relevant lane
5280 * in the status register
5282 u32 ser_lane = ((params->lane_config &
5283 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5284 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5286 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
5289 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5291 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
5293 } else { /* SerDes */
5294 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
5295 /* Disable the link interrupt
5296 * by writing 1 to the status register
5299 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5300 NIG_STATUS_SERDES0_LINK_STATUS);
5303 } else { /* link_down */
5307 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
5310 u32 mask = 0xf0000000;
5314 /* Need more than 10chars for this format */
5321 digit = ((num & mask) >> shift);
5323 *str_ptr = digit + '0';
5325 *str_ptr = digit - 0xa + 'a';
5338 static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
5343 /* Enable EMAC0 in to enable MDIO */
5344 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
5345 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
5348 /* take ext phy out of reset */
5350 MISC_REGISTERS_GPIO_2,
5351 MISC_REGISTERS_GPIO_HIGH,
5355 MISC_REGISTERS_GPIO_1,
5356 MISC_REGISTERS_GPIO_HIGH,
5362 for (cnt = 0; cnt < 1000; cnt++) {
5364 bnx2x_cl45_read(bp, port,
5370 if (!(ctrl & (1<<15))) {
5371 DP(NETIF_MSG_LINK, "Reset completed\n\n");
5377 static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
5379 /* put sf to reset */
5381 MISC_REGISTERS_GPIO_1,
5382 MISC_REGISTERS_GPIO_LOW,
5385 MISC_REGISTERS_GPIO_2,
5386 MISC_REGISTERS_GPIO_LOW,
5390 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5391 u8 *version, u16 len)
5394 u32 ext_phy_type = 0;
5398 if (version == NULL || params == NULL)
5402 spirom_ver = REG_RD(bp, params->shmem_base +
5403 offsetof(struct shmem_region,
5404 port_mb[params->port].ext_phy_fw_version));
5407 /* reset the returned value to zero */
5408 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5409 switch (ext_phy_type) {
5410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5415 version[0] = (spirom_ver & 0xFF);
5416 version[1] = (spirom_ver & 0xFF00) >> 8;
5417 version[2] = (spirom_ver & 0xFF0000) >> 16;
5418 version[3] = (spirom_ver & 0xFF000000) >> 24;
5422 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5423 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
5424 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5425 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5426 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5427 status = bnx2x_format_ver(spirom_ver, version, len);
5429 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5430 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5431 (spirom_ver & 0x7F);
5432 status = bnx2x_format_ver(spirom_ver, version, len);
5434 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5435 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5439 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5440 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
5441 " type is FAILURE!\n");
5451 static void bnx2x_set_xgxs_loopback(struct link_params *params,
5452 struct link_vars *vars,
5455 u8 port = params->port;
5456 struct bnx2x *bp = params->bp;
5461 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5463 /* change the uni_phy_addr in the nig */
5464 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5467 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
5469 bnx2x_cl45_write(bp, port, 0,
5472 (MDIO_REG_BANK_AER_BLOCK +
5473 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5476 bnx2x_cl45_write(bp, port, 0,
5479 (MDIO_REG_BANK_CL73_IEEEB0 +
5480 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5483 /* set aer mmd back */
5484 bnx2x_set_aer_mmd(params, vars);
5487 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5493 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5495 CL45_RD_OVER_CL22(bp, port,
5497 MDIO_REG_BANK_COMBO_IEEE0,
5498 MDIO_COMBO_IEEE0_MII_CONTROL,
5501 CL45_WR_OVER_CL22(bp, port,
5503 MDIO_REG_BANK_COMBO_IEEE0,
5504 MDIO_COMBO_IEEE0_MII_CONTROL,
5506 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
5511 static void bnx2x_ext_phy_loopback(struct link_params *params)
5513 struct bnx2x *bp = params->bp;
5517 if (params->switch_cfg == SWITCH_CFG_10G) {
5518 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5519 /* CL37 Autoneg Enabled */
5520 ext_phy_addr = ((params->ext_phy_config &
5521 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
5522 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
5523 switch (ext_phy_type) {
5524 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5525 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
5527 "ext_phy_loopback: We should not get here\n");
5529 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5530 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
5532 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5533 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
5535 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5536 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5537 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5543 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5544 /* SFX7101_XGXS_TEST1 */
5545 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5548 MDIO_XS_SFX7101_XGXS_TEST1,
5551 "ext_phy_loopback: set ext phy loopback\n");
5553 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5556 } /* switch external PHY type */
5559 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5560 ext_phy_addr = (params->ext_phy_config &
5561 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
5562 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
5568 *------------------------------------------------------------------------
5569 * bnx2x_override_led_value -
5571 * Override the led value of the requsted led
5573 *------------------------------------------------------------------------
5575 u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5576 u32 led_idx, u32 value)
5580 /* If port 0 then use EMAC0, else use EMAC1*/
5581 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5584 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5585 port, led_idx, value);
5588 case 0: /* 10MB led */
5589 /* Read the current value of the LED register in
5591 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5592 /* Set the OVERRIDE bit to 1 */
5593 reg_val |= EMAC_LED_OVERRIDE;
5594 /* If value is 1, set the 10M_OVERRIDE bit,
5595 otherwise reset it.*/
5596 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
5597 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
5598 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5600 case 1: /*100MB led */
5601 /*Read the current value of the LED register in
5603 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5604 /* Set the OVERRIDE bit to 1 */
5605 reg_val |= EMAC_LED_OVERRIDE;
5606 /* If value is 1, set the 100M_OVERRIDE bit,
5607 otherwise reset it.*/
5608 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
5609 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
5610 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5612 case 2: /* 1000MB led */
5613 /* Read the current value of the LED register in the
5615 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5616 /* Set the OVERRIDE bit to 1 */
5617 reg_val |= EMAC_LED_OVERRIDE;
5618 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5620 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
5621 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
5622 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5624 case 3: /* 2500MB led */
5625 /* Read the current value of the LED register in the
5627 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5628 /* Set the OVERRIDE bit to 1 */
5629 reg_val |= EMAC_LED_OVERRIDE;
5630 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5632 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
5633 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
5634 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5636 case 4: /*10G led */
5638 REG_WR(bp, NIG_REG_LED_10G_P0,
5641 REG_WR(bp, NIG_REG_LED_10G_P1,
5645 case 5: /* TRAFFIC led */
5646 /* Find if the traffic control is via BMAC or EMAC */
5648 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
5650 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
5652 /* Override the traffic led in the EMAC:*/
5654 /* Read the current value of the LED register in
5656 reg_val = REG_RD(bp, emac_base +
5658 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5659 reg_val |= EMAC_LED_OVERRIDE;
5660 /* If value is 1, set the TRAFFIC bit, otherwise
5662 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
5663 (reg_val & ~EMAC_LED_TRAFFIC);
5664 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5665 } else { /* Override the traffic led in the BMAC: */
5666 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5668 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
5674 "bnx2x_override_led_value() unknown led index %d "
5675 "(should be 0-5)\n", led_idx);
5683 u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5684 u16 hw_led_mode, u32 chip_id)
5688 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5689 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5690 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5691 speed, hw_led_mode);
5694 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5695 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5696 SHARED_HW_CFG_LED_MAC1);
5698 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5699 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5703 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5704 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5706 /* Set blinking rate to ~15.9Hz */
5707 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5708 LED_BLINK_RATE_VAL);
5709 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5711 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5712 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5713 (tmp & (~EMAC_LED_OVERRIDE)));
5715 if (!CHIP_IS_E1H(bp) &&
5716 ((speed == SPEED_2500) ||
5717 (speed == SPEED_1000) ||
5718 (speed == SPEED_100) ||
5719 (speed == SPEED_10))) {
5720 /* On Everest 1 Ax chip versions for speeds less than
5721 10G LED scheme is different */
5722 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5724 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5726 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5733 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5741 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
5743 struct bnx2x *bp = params->bp;
5746 CL45_RD_OVER_CL22(bp, params->port,
5748 MDIO_REG_BANK_GP_STATUS,
5749 MDIO_GP_STATUS_TOP_AN_STATUS1,
5751 /* link is up only if both local phy and external phy are up */
5752 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
5753 bnx2x_ext_phy_is_link_up(params, vars, 1))
5759 static u8 bnx2x_link_initialize(struct link_params *params,
5760 struct link_vars *vars)
5762 struct bnx2x *bp = params->bp;
5763 u8 port = params->port;
5766 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5767 /* Activate the external PHY */
5768 bnx2x_ext_phy_reset(params, vars);
5770 bnx2x_set_aer_mmd(params, vars);
5772 if (vars->phy_flags & PHY_XGXS_FLAG)
5773 bnx2x_set_master_ln(params);
5775 rc = bnx2x_reset_unicore(params);
5776 /* reset the SerDes and wait for reset bit return low */
5780 bnx2x_set_aer_mmd(params, vars);
5782 /* setting the masterLn_def again after the reset */
5783 if (vars->phy_flags & PHY_XGXS_FLAG) {
5784 bnx2x_set_master_ln(params);
5785 bnx2x_set_swap_lanes(params);
5788 if (vars->phy_flags & PHY_XGXS_FLAG) {
5789 if ((params->req_line_speed &&
5790 ((params->req_line_speed == SPEED_100) ||
5791 (params->req_line_speed == SPEED_10))) ||
5792 (!params->req_line_speed &&
5793 (params->speed_cap_mask >=
5794 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5795 (params->speed_cap_mask <
5796 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5798 vars->phy_flags |= PHY_SGMII_FLAG;
5800 vars->phy_flags &= ~PHY_SGMII_FLAG;
5803 /* In case of external phy existance, the line speed would be the
5804 line speed linked up by the external phy. In case it is direct only,
5805 then the line_speed during initialization will be equal to the
5807 vars->line_speed = params->req_line_speed;
5809 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
5811 /* init ext phy and enable link state int */
5812 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
5813 (params->loopback_mode == LOOPBACK_XGXS_10));
5816 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5817 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
5818 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
5819 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5820 if (params->req_line_speed == SPEED_AUTO_NEG)
5821 bnx2x_set_parallel_detection(params, vars->phy_flags);
5822 bnx2x_init_internal_phy(params, vars);
5826 rc |= bnx2x_ext_phy_init(params, vars);
5828 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5829 (NIG_STATUS_XGXS0_LINK10G |
5830 NIG_STATUS_XGXS0_LINK_STATUS |
5831 NIG_STATUS_SERDES0_LINK_STATUS));
5838 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5840 struct bnx2x *bp = params->bp;
5843 DP(NETIF_MSG_LINK, "Phy Initialization started \n");
5844 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
5845 params->req_line_speed, params->req_flow_ctrl);
5846 vars->link_status = 0;
5847 vars->phy_link_up = 0;
5849 vars->line_speed = 0;
5850 vars->duplex = DUPLEX_FULL;
5851 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5852 vars->mac_type = MAC_TYPE_NONE;
5854 if (params->switch_cfg == SWITCH_CFG_1G)
5855 vars->phy_flags = PHY_SERDES_FLAG;
5857 vars->phy_flags = PHY_XGXS_FLAG;
5860 /* disable attentions */
5861 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
5862 (NIG_MASK_XGXS0_LINK_STATUS |
5863 NIG_MASK_XGXS0_LINK10G |
5864 NIG_MASK_SERDES0_LINK_STATUS |
5867 bnx2x_emac_init(params, vars);
5869 if (CHIP_REV_IS_FPGA(bp)) {
5871 vars->line_speed = SPEED_10000;
5872 vars->duplex = DUPLEX_FULL;
5873 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5874 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5875 /* enable on E1.5 FPGA */
5876 if (CHIP_IS_E1H(bp)) {
5878 (BNX2X_FLOW_CTRL_TX | BNX2X_FLOW_CTRL_RX);
5879 vars->link_status |=
5880 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
5881 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
5884 bnx2x_emac_enable(params, vars, 0);
5885 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5887 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5888 + params->port*4, 0);
5890 /* update shared memory */
5891 bnx2x_update_mng(params, vars->link_status);
5896 if (CHIP_REV_IS_EMUL(bp)) {
5899 vars->line_speed = SPEED_10000;
5900 vars->duplex = DUPLEX_FULL;
5901 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5902 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5904 bnx2x_bmac_enable(params, vars, 0);
5906 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5908 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5909 + params->port*4, 0);
5911 /* update shared memory */
5912 bnx2x_update_mng(params, vars->link_status);
5917 if (params->loopback_mode == LOOPBACK_BMAC) {
5919 vars->line_speed = SPEED_10000;
5920 vars->duplex = DUPLEX_FULL;
5921 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5922 vars->mac_type = MAC_TYPE_BMAC;
5924 vars->phy_flags = PHY_XGXS_FLAG;
5926 bnx2x_phy_deassert(params, vars->phy_flags);
5927 /* set bmac loopback */
5928 bnx2x_bmac_enable(params, vars, 1);
5930 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5932 } else if (params->loopback_mode == LOOPBACK_EMAC) {
5934 vars->line_speed = SPEED_1000;
5935 vars->duplex = DUPLEX_FULL;
5936 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5937 vars->mac_type = MAC_TYPE_EMAC;
5939 vars->phy_flags = PHY_XGXS_FLAG;
5941 bnx2x_phy_deassert(params, vars->phy_flags);
5942 /* set bmac loopback */
5943 bnx2x_emac_enable(params, vars, 1);
5944 bnx2x_emac_program(params, vars->line_speed,
5946 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5948 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
5949 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5951 vars->line_speed = SPEED_10000;
5952 vars->duplex = DUPLEX_FULL;
5953 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5955 vars->phy_flags = PHY_XGXS_FLAG;
5958 NIG_REG_XGXS0_CTRL_PHY_ADDR+
5960 params->phy_addr = (u8)val;
5962 bnx2x_phy_deassert(params, vars->phy_flags);
5963 bnx2x_link_initialize(params, vars);
5965 vars->mac_type = MAC_TYPE_BMAC;
5967 bnx2x_bmac_enable(params, vars, 0);
5969 if (params->loopback_mode == LOOPBACK_XGXS_10) {
5970 /* set 10G XGXS loopback */
5971 bnx2x_set_xgxs_loopback(params, vars, 1);
5973 /* set external phy loopback */
5974 bnx2x_ext_phy_loopback(params);
5976 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5979 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
5980 vars->line_speed, params->hw_led_mode,
5987 bnx2x_phy_deassert(params, vars->phy_flags);
5988 switch (params->switch_cfg) {
5990 vars->phy_flags |= PHY_SERDES_FLAG;
5991 if ((params->ext_phy_config &
5992 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
5993 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
5999 NIG_REG_SERDES0_CTRL_PHY_ADDR+
6002 params->phy_addr = (u8)val;
6005 case SWITCH_CFG_10G:
6006 vars->phy_flags |= PHY_XGXS_FLAG;
6008 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6010 params->phy_addr = (u8)val;
6014 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6018 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
6020 bnx2x_link_initialize(params, vars);
6022 bnx2x_link_int_enable(params);
6027 static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
6029 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
6031 /* Set serial boot control for external load */
6032 bnx2x_cl45_write(bp, port,
6033 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
6035 MDIO_PMA_REG_GEN_CTRL, 0x0001);
6038 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6042 struct bnx2x *bp = params->bp;
6043 u32 ext_phy_config = params->ext_phy_config;
6044 u16 hw_led_mode = params->hw_led_mode;
6045 u32 chip_id = params->chip_id;
6046 u8 port = params->port;
6047 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6048 u32 val = REG_RD(bp, params->shmem_base +
6049 offsetof(struct shmem_region, dev_info.
6050 port_feature_config[params->port].
6053 /* disable attentions */
6055 vars->link_status = 0;
6056 bnx2x_update_mng(params, vars->link_status);
6057 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6058 (NIG_MASK_XGXS0_LINK_STATUS |
6059 NIG_MASK_XGXS0_LINK10G |
6060 NIG_MASK_SERDES0_LINK_STATUS |
6063 /* activate nig drain */
6064 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6066 /* disable nig egress interface */
6067 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6068 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6070 /* Stop BigMac rx */
6071 bnx2x_bmac_rx_disable(bp, port);
6074 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6077 /* The PHY reset is controled by GPIO 1
6078 * Hold it as vars low
6080 /* clear link led */
6081 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
6082 if (reset_ext_phy) {
6083 switch (ext_phy_type) {
6084 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6088 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6091 /* Disable Transmitter */
6092 u8 ext_phy_addr = ((params->ext_phy_config &
6093 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6094 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6095 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6096 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6097 bnx2x_sfp_set_transmitter(bp, port,
6098 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6102 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6103 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
6106 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6107 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6110 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6112 u8 ext_phy_addr = ((params->ext_phy_config &
6113 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6114 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6115 /* Set soft reset */
6116 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6121 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6122 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6124 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6125 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6127 DP(NETIF_MSG_LINK, "reset external PHY\n");
6130 /* reset the SerDes/XGXS */
6131 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6132 (0x1ff << (port*16)));
6135 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6136 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6138 /* disable nig ingress interface */
6139 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
6140 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
6141 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6142 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6147 static u8 bnx2x_update_link_down(struct link_params *params,
6148 struct link_vars *vars)
6150 struct bnx2x *bp = params->bp;
6151 u8 port = params->port;
6152 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6153 bnx2x_set_led(bp, port, LED_MODE_OFF,
6154 0, params->hw_led_mode,
6157 /* indicate no mac active */
6158 vars->mac_type = MAC_TYPE_NONE;
6160 /* update shared memory */
6161 vars->link_status = 0;
6162 vars->line_speed = 0;
6163 bnx2x_update_mng(params, vars->link_status);
6165 /* activate nig drain */
6166 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6169 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6174 bnx2x_bmac_rx_disable(bp, params->port);
6175 REG_WR(bp, GRCBASE_MISC +
6176 MISC_REGISTERS_RESET_REG_2_CLEAR,
6177 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6181 static u8 bnx2x_update_link_up(struct link_params *params,
6182 struct link_vars *vars,
6183 u8 link_10g, u32 gp_status)
6185 struct bnx2x *bp = params->bp;
6186 u8 port = params->port;
6188 vars->link_status |= LINK_STATUS_LINK_UP;
6190 bnx2x_bmac_enable(params, vars, 0);
6191 bnx2x_set_led(bp, port, LED_MODE_OPER,
6192 SPEED_10000, params->hw_led_mode,
6196 bnx2x_emac_enable(params, vars, 0);
6197 rc = bnx2x_emac_program(params, vars->line_speed,
6201 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6202 if (!(vars->phy_flags &
6204 bnx2x_set_gmii_tx_driver(params);
6209 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6213 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6215 /* update shared memory */
6216 bnx2x_update_mng(params, vars->link_status);
6220 /* This function should called upon link interrupt */
6221 /* In case vars->link_up, driver needs to
6224 3. Update the shared memory
6228 1. Update shared memory
6233 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6235 struct bnx2x *bp = params->bp;
6236 u8 port = params->port;
6239 u8 ext_phy_link_up, rc = 0;
6243 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6244 port, (vars->phy_flags & PHY_XGXS_FLAG),
6245 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6247 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6249 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6250 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6253 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6255 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6256 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6257 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6260 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6262 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
6264 /* Check external link change only for non-direct */
6265 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int);
6267 /* Read gp_status */
6268 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
6269 MDIO_REG_BANK_GP_STATUS,
6270 MDIO_GP_STATUS_TOP_AN_STATUS1,
6273 rc = bnx2x_link_settings_status(params, vars, gp_status,
6278 /* anything 10 and over uses the bmac */
6279 link_10g = ((vars->line_speed == SPEED_10000) ||
6280 (vars->line_speed == SPEED_12000) ||
6281 (vars->line_speed == SPEED_12500) ||
6282 (vars->line_speed == SPEED_13000) ||
6283 (vars->line_speed == SPEED_15000) ||
6284 (vars->line_speed == SPEED_16000));
6286 bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
6288 /* In case external phy link is up, and internal link is down
6289 ( not initialized yet probably after link initialization, it needs
6291 Note that after link down-up as result of cable plug,
6292 the xgxs link would probably become up again without the need to
6295 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6296 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
6297 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
6298 (ext_phy_link_up && !vars->phy_link_up))
6299 bnx2x_init_internal_phy(params, vars);
6301 /* link is up only if both local phy and external phy are up */
6302 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
6305 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
6307 rc = bnx2x_update_link_down(params, vars);
6312 static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6314 u8 ext_phy_addr[PORT_MAX];
6318 /* PART1 - Reset both phys */
6319 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6320 /* Extract the ext phy address for the port */
6321 u32 ext_phy_config = REG_RD(bp, shmem_base +
6322 offsetof(struct shmem_region,
6323 dev_info.port_hw_config[port].external_phy_config));
6325 /* disable attentions */
6326 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6327 (NIG_MASK_XGXS0_LINK_STATUS |
6328 NIG_MASK_XGXS0_LINK10G |
6329 NIG_MASK_SERDES0_LINK_STATUS |
6332 ext_phy_addr[port] =
6334 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6335 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6337 /* Need to take the phy out of low power mode in order
6338 to write to access its registers */
6339 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6340 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6343 bnx2x_cl45_write(bp, port,
6344 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6351 /* Add delay of 150ms after reset */
6354 /* PART2 - Download firmware to both phys */
6355 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6358 bnx2x_bcm8073_external_rom_boot(bp, port,
6359 ext_phy_addr[port], shmem_base);
6361 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6364 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6365 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6367 "bnx2x_8073_common_init_phy port %x:"
6368 "Download failed. fw version = 0x%x\n",
6373 /* Only set bit 10 = 1 (Tx power down) */
6374 bnx2x_cl45_read(bp, port,
6375 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6378 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6380 /* Phase1 of TX_POWER_DOWN reset */
6381 bnx2x_cl45_write(bp, port,
6382 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6385 MDIO_PMA_REG_TX_POWER_DOWN,
6389 /* Toggle Transmitter: Power down and then up with 600ms
6393 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6394 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6395 /* Phase2 of POWER_DOWN_RESET */
6396 /* Release bit 10 (Release Tx power down) */
6397 bnx2x_cl45_read(bp, port,
6398 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6401 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6403 bnx2x_cl45_write(bp, port,
6404 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6407 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6410 /* Read modify write the SPI-ROM version select register */
6411 bnx2x_cl45_read(bp, port,
6412 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6415 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
6416 bnx2x_cl45_write(bp, port,
6417 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6420 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6422 /* set GPIO2 back to LOW */
6423 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6424 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6430 static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6432 u8 ext_phy_addr[PORT_MAX];
6433 s8 port, first_port, i;
6434 u32 swap_val, swap_override;
6435 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6436 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6437 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6439 bnx2x_hw_reset(bp, 1 ^ (swap_val && swap_override));
6442 if (swap_val && swap_override)
6443 first_port = PORT_0;
6445 first_port = PORT_1;
6447 /* PART1 - Reset both phys */
6448 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
6449 /* Extract the ext phy address for the port */
6450 u32 ext_phy_config = REG_RD(bp, shmem_base +
6451 offsetof(struct shmem_region,
6452 dev_info.port_hw_config[port].external_phy_config));
6454 /* disable attentions */
6455 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6456 (NIG_MASK_XGXS0_LINK_STATUS |
6457 NIG_MASK_XGXS0_LINK10G |
6458 NIG_MASK_SERDES0_LINK_STATUS |
6461 ext_phy_addr[port] = ((ext_phy_config &
6462 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6463 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6466 bnx2x_cl45_write(bp, port,
6467 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6474 /* Add delay of 150ms after reset */
6477 /* PART2 - Download firmware to both phys */
6478 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
6481 bnx2x_bcm8727_external_rom_boot(bp, port,
6482 ext_phy_addr[port], shmem_base);
6484 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6487 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6488 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6490 "bnx2x_8727_common_init_phy port %x:"
6491 "Download failed. fw version = 0x%x\n",
6501 static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6506 /* Use port1 because of the static port-swap */
6507 /* Enable the module detection interrupt */
6508 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6509 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6510 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6511 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6513 bnx2x_hw_reset(bp, 1);
6515 for (port = 0; port < PORT_MAX; port++) {
6516 /* Extract the ext phy address for the port */
6517 u32 ext_phy_config = REG_RD(bp, shmem_base +
6518 offsetof(struct shmem_region,
6519 dev_info.port_hw_config[port].external_phy_config));
6523 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6524 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6525 DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
6528 bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
6530 /* Set fault module detected LED on */
6531 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6532 MISC_REGISTERS_GPIO_HIGH,
6539 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6544 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6546 /* Read the ext_phy_type for arbitrary port(0) */
6547 ext_phy_type = XGXS_EXT_PHY_TYPE(
6548 REG_RD(bp, shmem_base +
6549 offsetof(struct shmem_region,
6550 dev_info.port_hw_config[0].external_phy_config)));
6552 switch (ext_phy_type) {
6553 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6555 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
6559 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6560 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6561 rc = bnx2x_8727_common_init_phy(bp, shmem_base);
6564 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6565 /* GPIO1 affects both ports, so there's need to pull
6566 it for single port alone */
6567 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6572 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6582 static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
6586 bnx2x_cl45_read(bp, port,
6587 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6590 MDIO_PMA_REG_7101_RESET, &val);
6592 for (cnt = 0; cnt < 10; cnt++) {
6594 /* Writes a self-clearing reset */
6595 bnx2x_cl45_write(bp, port,
6596 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6599 MDIO_PMA_REG_7101_RESET,
6601 /* Wait for clear */
6602 bnx2x_cl45_read(bp, port,
6603 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6606 MDIO_PMA_REG_7101_RESET, &val);
6608 if ((val & (1<<15)) == 0)
6612 #define RESERVED_SIZE 256
6613 /* max application is 160K bytes - data at end of RAM */
6614 #define MAX_APP_SIZE (160*1024 - RESERVED_SIZE)
6616 /* Header is 14 bytes */
6617 #define HEADER_SIZE 14
6618 #define DATA_OFFSET HEADER_SIZE
6620 #define SPI_START_TRANSFER(bp, port, ext_phy_addr) \
6621 bnx2x_cl45_write(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, \
6624 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 1)
6626 /* Programs an image to DSP's flash via the SPI port*/
6627 static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
6629 char data[], u32 size)
6631 const u16 num_trans = size/4; /* 4 bytes can be sent at a time */
6632 /* Doesn't include last trans!*/
6633 const u16 last_trans_size = size%4; /* Num bytes on last trans */
6634 u16 trans_cnt, byte_cnt;
6637 u16 code_started = 0;
6638 u16 image_revision1, image_revision2;
6641 DP(NETIF_MSG_LINK, "bnx2x_sfx7101_flash_download file_size=%d\n", size);
6643 if ((size-HEADER_SIZE) > MAX_APP_SIZE) {
6644 /* This very often will be the case, because the image is built
6645 with 160Kbytes size whereas the total image size must actually
6646 be 160Kbytes-RESERVED_SIZE */
6647 DP(NETIF_MSG_LINK, "Warning, file size was %d bytes "
6648 "truncated to %d bytes\n", size, MAX_APP_SIZE);
6649 size = MAX_APP_SIZE+HEADER_SIZE;
6651 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
6652 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
6653 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
6654 and issuing a reset.*/
6656 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6657 MISC_REGISTERS_GPIO_HIGH, port);
6659 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
6662 for (cnt = 0; cnt < 100; cnt++)
6665 /* Make sure we can access the DSP
6666 And it's in the correct mode (waiting for download) */
6668 bnx2x_cl45_read(bp, port,
6669 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6672 MDIO_PCS_REG_7101_DSP_ACCESS, &tmp);
6674 if (tmp != 0x000A) {
6675 DP(NETIF_MSG_LINK, "DSP is not in waiting on download mode. "
6676 "Expected 0x000A, read 0x%04X\n", tmp);
6677 DP(NETIF_MSG_LINK, "Download failed\n");
6681 /* Mux the SPI interface away from the internal processor */
6682 bnx2x_cl45_write(bp, port,
6683 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6686 MDIO_PCS_REG_7101_SPI_MUX, 1);
6688 /* Reset the SPI port */
6689 bnx2x_cl45_write(bp, port,
6690 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6693 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
6694 bnx2x_cl45_write(bp, port,
6695 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6698 MDIO_PCS_REG_7101_SPI_CTRL_ADDR,
6699 (1<<MDIO_PCS_REG_7101_SPI_RESET_BIT));
6700 bnx2x_cl45_write(bp, port,
6701 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6704 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
6706 /* Erase the flash */
6707 bnx2x_cl45_write(bp, port,
6708 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6711 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6712 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6714 bnx2x_cl45_write(bp, port,
6715 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6718 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6721 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6722 bnx2x_cl45_write(bp, port,
6723 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6726 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6727 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD);
6729 bnx2x_cl45_write(bp, port,
6730 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6733 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6735 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6737 /* Wait 10 seconds, the maximum time for the erase to complete */
6738 DP(NETIF_MSG_LINK, "Erasing flash, this takes 10 seconds...\n");
6739 for (cnt = 0; cnt < 1000; cnt++)
6742 DP(NETIF_MSG_LINK, "Downloading flash, please wait...\n");
6744 for (trans_cnt = 0; trans_cnt < num_trans; trans_cnt++) {
6745 bnx2x_cl45_write(bp, port,
6746 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6749 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6750 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6752 bnx2x_cl45_write(bp, port,
6753 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6756 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6758 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6760 bnx2x_cl45_write(bp, port,
6761 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6764 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6765 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
6767 /* Bits 23-16 of address */
6768 bnx2x_cl45_write(bp, port,
6769 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6772 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6774 /* Bits 15-8 of address */
6775 bnx2x_cl45_write(bp, port,
6776 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6779 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6782 /* Bits 7-0 of address */
6783 bnx2x_cl45_write(bp, port,
6784 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6787 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6791 while (byte_cnt < 4 && data_index < size) {
6792 bnx2x_cl45_write(bp, port,
6793 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6796 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6797 data[data_index++]);
6801 bnx2x_cl45_write(bp, port,
6802 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6805 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6808 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6809 msleep(5); /* Wait 5 ms minimum between transs */
6811 /* Let the user know something's going on.*/
6812 /* a pacifier ever 4K */
6813 if ((data_index % 1023) == 0)
6814 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
6817 DP(NETIF_MSG_LINK, "\n");
6818 /* Transfer the last block if there is data remaining */
6819 if (last_trans_size) {
6820 bnx2x_cl45_write(bp, port,
6821 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6824 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6825 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6827 bnx2x_cl45_write(bp, port,
6828 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6831 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6834 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6836 bnx2x_cl45_write(bp, port,
6837 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6840 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6841 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
6843 /* Bits 23-16 of address */
6844 bnx2x_cl45_write(bp, port,
6845 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6848 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6850 /* Bits 15-8 of address */
6851 bnx2x_cl45_write(bp, port,
6852 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6855 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6858 /* Bits 7-0 of address */
6859 bnx2x_cl45_write(bp, port,
6860 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6863 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6867 while (byte_cnt < last_trans_size && data_index < size) {
6868 /* Bits 7-0 of address */
6869 bnx2x_cl45_write(bp, port,
6870 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6873 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6874 data[data_index++]);
6878 bnx2x_cl45_write(bp, port,
6879 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6882 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6885 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6888 /* DSP Remove Download Mode */
6889 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6890 MISC_REGISTERS_GPIO_LOW, port);
6892 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
6894 /* wait 0.5 sec to allow it to run */
6895 for (cnt = 0; cnt < 100; cnt++)
6898 bnx2x_hw_reset(bp, port);
6900 for (cnt = 0; cnt < 100; cnt++)
6903 /* Check that the code is started. In case the download
6904 checksum failed, the code won't be started. */
6905 bnx2x_cl45_read(bp, port,
6906 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6909 MDIO_PCS_REG_7101_DSP_ACCESS,
6912 code_started = (tmp & (1<<4));
6913 if (!code_started) {
6914 DP(NETIF_MSG_LINK, "Download failed. Please check file.\n");
6918 /* Verify that the file revision is now equal to the image
6919 revision within the DSP */
6920 bnx2x_cl45_read(bp, port,
6921 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6924 MDIO_PMA_REG_7101_VER1,
6927 bnx2x_cl45_read(bp, port,
6928 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6931 MDIO_PMA_REG_7101_VER2,
6934 if (data[0x14e] != (image_revision2&0xFF) ||
6935 data[0x14f] != ((image_revision2&0xFF00)>>8) ||
6936 data[0x150] != (image_revision1&0xFF) ||
6937 data[0x151] != ((image_revision1&0xFF00)>>8)) {
6938 DP(NETIF_MSG_LINK, "Download failed.\n");
6941 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
6945 u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
6946 u8 driver_loaded, char data[], u32 size)
6951 ext_phy_addr = ((ext_phy_config &
6952 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6953 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6955 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6957 switch (ext_phy_type) {
6958 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6960 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6961 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6963 "Flash download not supported for this ext phy\n");
6966 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6967 /* Take ext phy out of reset */
6969 bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
6970 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
6973 bnx2x_turn_off_sf(bp, port);
6975 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6976 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6977 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
6979 DP(NETIF_MSG_LINK, "Invalid ext phy type\n");