1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
15 /****************************************************************************
16 * Shared HW configuration *
17 ****************************************************************************/
18 struct shared_hw_cfg { /* NVRAM Offset */
19 /* Up to 16 bytes of NULL-terminated string */
20 u8 part_num[16]; /* 0x104 */
22 u32 config; /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
29 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
31 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
33 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
35 /* Whatever MFW found in NVM
36 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
41 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
44 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
47 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
51 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
53 #define SHARED_HW_CFG_LED_MAC1 0x00000000
54 #define SHARED_HW_CFG_LED_PHY1 0x00010000
55 #define SHARED_HW_CFG_LED_PHY2 0x00020000
56 #define SHARED_HW_CFG_LED_PHY3 0x00030000
57 #define SHARED_HW_CFG_LED_MAC2 0x00040000
58 #define SHARED_HW_CFG_LED_PHY4 0x00050000
59 #define SHARED_HW_CFG_LED_PHY5 0x00060000
60 #define SHARED_HW_CFG_LED_PHY6 0x00070000
61 #define SHARED_HW_CFG_LED_MAC3 0x00080000
62 #define SHARED_HW_CFG_LED_PHY7 0x00090000
63 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
68 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
77 u32 config2; /* 0x118 */
78 /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
84 /* The default value for the core clock is 250MHz and it is
85 achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
92 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
94 /* The fan failure mechanism is usually related to the PHY type
95 since the power consumption of the board is determined by the PHY.
96 Currently, fan is required for most designs with SFX7101, BCM8727
97 and BCM8481. If a fan is not required for a board which uses one
98 of those PHYs, this field should be set to "Disabled". If a fan is
99 required for a different PHY type, this option should be set to
101 The fan failure indication is expected on
103 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
104 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
105 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
106 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
107 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
109 u32 power_dissipated; /* 0x11c */
110 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
111 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
113 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
114 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
115 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
116 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
117 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
118 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
120 u32 ump_nc_si_config; /* 0x120 */
121 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
122 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
123 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
124 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
125 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
126 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
128 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
129 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
131 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
132 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
133 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
134 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
136 u32 board; /* 0x124 */
137 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
138 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
140 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
141 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
143 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
144 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
146 u32 reserved; /* 0x128 */
151 /****************************************************************************
152 * Port HW configuration *
153 ****************************************************************************/
154 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
157 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
158 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
161 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
162 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
164 u32 power_dissipated;
165 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
166 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
167 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
168 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
169 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
170 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
171 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
172 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
175 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
176 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
177 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
178 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
179 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
180 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
181 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
182 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
185 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
186 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
189 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
192 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
196 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
197 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
199 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
200 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
203 u32 Reserved0[16]; /* 0x158 */
205 /* for external PHY, or forced mode or during AN */
206 u16 xgxs_config_rx[4]; /* 0x198 */
208 u16 xgxs_config_tx[4]; /* 0x1A0 */
210 u32 Reserved1[64]; /* 0x1A8 */
213 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
214 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
215 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
216 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
217 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
218 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
219 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
220 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
222 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
224 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
226 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
228 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
230 u32 external_phy_config;
231 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
232 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
233 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
234 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
235 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
237 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
238 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
240 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
241 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
242 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
243 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
244 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
245 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
246 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
247 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
248 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
249 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
250 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
251 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
252 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
254 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
255 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
257 u32 speed_capability_mask;
258 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
259 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
260 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
261 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
262 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
263 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
264 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
265 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
266 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
267 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
268 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
269 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
270 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
271 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
272 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
274 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
275 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
276 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
277 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
278 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
279 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
280 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
281 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
282 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
283 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
284 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
285 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
286 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
287 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
288 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
295 /****************************************************************************
296 * Shared Feature configuration *
297 ****************************************************************************/
298 struct shared_feat_cfg { /* NVRAM Offset */
300 u32 config; /* 0x450 */
301 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
303 /* Use the values from options 47 and 48 instead of the HW default
305 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
306 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
308 #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
313 /****************************************************************************
314 * Port Feature configuration *
315 ****************************************************************************/
316 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
319 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
320 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
321 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
322 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
323 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
324 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
325 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
326 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
327 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
328 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
329 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
330 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
331 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
332 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
333 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
334 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
335 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
336 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
337 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
338 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
339 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
340 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
341 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
342 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
343 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
344 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
345 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
346 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
347 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
348 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
349 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
350 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
351 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
352 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
353 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
354 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
355 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
356 #define PORT_FEATURE_EN_SIZE_SHIFT 24
357 #define PORT_FEATURE_WOL_ENABLED 0x01000000
358 #define PORT_FEATURE_MBA_ENABLED 0x02000000
359 #define PORT_FEATURE_MFW_ENABLED 0x04000000
361 /* Check the optic vendor via i2c before allowing it to be used by
363 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLED 0x00000000
364 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED 0x08000000
367 /* Default is used when driver sets to "auto" mode */
368 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
369 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
370 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
371 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
372 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
373 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
374 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
375 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
376 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
379 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
380 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
381 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
382 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
383 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
384 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
385 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
386 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
387 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
388 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
389 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
390 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
391 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
392 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
393 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
394 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
395 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
396 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
397 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
398 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
399 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
400 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
401 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
402 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
403 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
404 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
405 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
406 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
407 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
408 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
409 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
410 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
411 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
412 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
413 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
414 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
415 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
416 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
417 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
418 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
419 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
420 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
421 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
422 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
423 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
424 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
425 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
426 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
427 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
428 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
429 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
430 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
431 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
432 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
435 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
436 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
439 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
440 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
441 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
444 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
445 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
446 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
447 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
448 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
452 #define PORT_FEATURE_SMBUS_EN 0x00000001
453 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
454 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
458 u32 link_config; /* Used as HW defaults for the driver */
459 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
460 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
461 /* (forced) low speed switch (< 10G) */
462 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
463 /* (forced) high speed switch (>= 10G) */
464 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
465 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
466 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
468 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
469 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
470 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
471 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
472 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
473 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
474 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
475 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
476 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
477 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
478 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
479 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
480 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
481 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
482 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
483 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
484 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
486 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
487 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
488 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
489 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
490 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
491 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
492 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
494 /* The default for MCP link configuration,
495 uses the same defines as link_config */
496 u32 mfw_wol_link_cfg;
503 /****************************************************************************
504 * Device Information *
505 ****************************************************************************/
506 struct shm_dev_info { /* size */
508 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
510 struct shared_hw_cfg shared_hw_config; /* 40 */
512 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
514 struct shared_feat_cfg shared_feature_config; /* 4 */
516 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
529 #define E1_FUNC_MAX 2
530 #define E1H_FUNC_MAX 8
540 /* This value (in milliseconds) determines the frequency of the driver
541 * issuing the PULSE message code. The firmware monitors this periodic
542 * pulse to determine when to switch to an OS-absent mode. */
543 #define DRV_PULSE_PERIOD_MS 250
545 /* This value (in milliseconds) determines how long the driver should
546 * wait for an acknowledgement from the firmware before timing out. Once
547 * the firmware has timed out, the driver will assume there is no firmware
548 * running and there won't be any firmware-driver synchronization during a
550 #define FW_ACK_TIME_OUT_MS 5000
552 #define FW_ACK_POLL_TIME_MS 1
554 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
556 /* LED Blink rate that will achieve ~15.9Hz */
557 #define LED_BLINK_RATE_VAL 480
559 /****************************************************************************
560 * Driver <-> FW Mailbox *
561 ****************************************************************************/
565 /* Driver should update this field on any link change event */
567 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
568 #define LINK_STATUS_LINK_UP 0x00000001
569 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
570 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
571 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
572 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
573 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
574 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
575 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
576 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
577 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
578 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
579 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
580 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
581 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
582 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
583 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
584 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
585 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
586 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
587 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
588 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
589 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
590 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
591 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
592 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
593 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
595 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
596 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
598 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
599 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
600 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
602 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
603 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
604 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
605 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
606 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
607 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
608 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
610 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
611 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
613 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
614 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
616 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
617 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
618 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
619 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
620 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
622 #define LINK_STATUS_SERDES_LINK 0x00100000
624 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
625 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
626 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
627 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
628 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
629 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
630 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
631 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
637 /* MCP firmware does not use this field */
638 u32 ext_phy_fw_version;
646 #define DRV_MSG_CODE_MASK 0xffff0000
647 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
648 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
649 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
650 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
651 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
652 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
653 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
654 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
655 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
656 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
657 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
658 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
659 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
661 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
662 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
663 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
664 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
666 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
671 #define FW_MSG_CODE_MASK 0xffff0000
672 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
673 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
674 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
675 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
676 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
677 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
678 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
679 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
680 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
681 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
682 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
683 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
684 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
685 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
686 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
687 #define FW_MSG_CODE_NO_KEY 0x80f00000
688 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
689 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
690 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
691 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
692 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
693 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
695 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
696 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
697 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
698 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
700 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
705 #define DRV_PULSE_SEQ_MASK 0x00007fff
706 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
707 /* The system time is in the format of
708 * (year-2001)*12*32 + month*32 + day. */
709 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
710 /* Indicate to the firmware not to go into the
711 * OS-absent when it is not getting driver pulse.
712 * This is used for debugging as well for PXE(MBA). */
715 #define MCP_PULSE_SEQ_MASK 0x00007fff
716 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
717 /* Indicates to the driver not to assert due to lack
719 #define MCP_EVENT_MASK 0xffff0000
720 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
722 u32 iscsi_boot_signature;
723 u32 iscsi_boot_block_offset;
726 #define DRV_STATUS_PMF 0x00000001
729 #define VIRT_MAC_SIGN_MASK 0xffff0000
730 #define VIRT_MAC_SIGNATURE 0x564d0000
736 /****************************************************************************
737 * Management firmware state *
738 ****************************************************************************/
739 /* Allocate 440 bytes for management firmware */
740 #define MGMTFW_STATE_WORD_SIZE 110
742 struct mgmtfw_state {
743 u32 opaque[MGMTFW_STATE_WORD_SIZE];
747 /****************************************************************************
748 * Multi-Function configuration *
749 ****************************************************************************/
750 struct shared_mf_cfg {
753 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
755 #define SHARED_MF_CLP_EXIT 0x00000001
757 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
763 u32 dynamic_cfg; /* device control channel */
764 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
765 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
766 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
767 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
777 /* function 0 of each port cannot be hidden */
778 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
780 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
781 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
782 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
783 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
784 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
785 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
787 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
790 /* 0 - low priority, 3 - high priority */
791 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
792 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
793 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
796 /* value range - 0..100, increments in 100Mbps */
797 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
798 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
799 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
800 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
801 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
802 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
804 u32 mac_upper; /* MAC */
805 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
806 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
807 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
809 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
811 u32 e1hov_tag; /* VNI */
812 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
813 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
814 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
822 struct shared_mf_cfg shared_mf_config;
823 struct port_mf_cfg port_mf_config[PORT_MAX];
824 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
829 /****************************************************************************
830 * Shared Memory Region *
831 ****************************************************************************/
832 struct shmem_region { /* SharedMem Offset (size) */
834 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
835 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
836 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
838 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
839 #define SHR_MEM_VALIDITY_MB 0x00200000
840 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
841 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
842 /* One licensing bit should be set */
843 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
844 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
845 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
846 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
848 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
849 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
850 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
851 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
852 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
853 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
855 struct shm_dev_info dev_info; /* 0x8 (0x438) */
857 u8 reserved[52*PORT_MAX];
859 /* FW information (for internal FW use) */
860 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
861 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
863 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
864 struct drv_func_mb func_mb[E1H_FUNC_MAX];
866 struct mf_cfg mf_cfg;
872 u32 rx_stat_ifhcinoctets;
873 u32 rx_stat_ifhcinbadoctets;
874 u32 rx_stat_etherstatsfragments;
875 u32 rx_stat_ifhcinucastpkts;
876 u32 rx_stat_ifhcinmulticastpkts;
877 u32 rx_stat_ifhcinbroadcastpkts;
878 u32 rx_stat_dot3statsfcserrors;
879 u32 rx_stat_dot3statsalignmenterrors;
880 u32 rx_stat_dot3statscarriersenseerrors;
881 u32 rx_stat_xonpauseframesreceived;
882 u32 rx_stat_xoffpauseframesreceived;
883 u32 rx_stat_maccontrolframesreceived;
884 u32 rx_stat_xoffstateentered;
885 u32 rx_stat_dot3statsframestoolong;
886 u32 rx_stat_etherstatsjabbers;
887 u32 rx_stat_etherstatsundersizepkts;
888 u32 rx_stat_etherstatspkts64octets;
889 u32 rx_stat_etherstatspkts65octetsto127octets;
890 u32 rx_stat_etherstatspkts128octetsto255octets;
891 u32 rx_stat_etherstatspkts256octetsto511octets;
892 u32 rx_stat_etherstatspkts512octetsto1023octets;
893 u32 rx_stat_etherstatspkts1024octetsto1522octets;
894 u32 rx_stat_etherstatspktsover1522octets;
896 u32 rx_stat_falsecarriererrors;
898 u32 tx_stat_ifhcoutoctets;
899 u32 tx_stat_ifhcoutbadoctets;
900 u32 tx_stat_etherstatscollisions;
901 u32 tx_stat_outxonsent;
902 u32 tx_stat_outxoffsent;
903 u32 tx_stat_flowcontroldone;
904 u32 tx_stat_dot3statssinglecollisionframes;
905 u32 tx_stat_dot3statsmultiplecollisionframes;
906 u32 tx_stat_dot3statsdeferredtransmissions;
907 u32 tx_stat_dot3statsexcessivecollisions;
908 u32 tx_stat_dot3statslatecollisions;
909 u32 tx_stat_ifhcoutucastpkts;
910 u32 tx_stat_ifhcoutmulticastpkts;
911 u32 tx_stat_ifhcoutbroadcastpkts;
912 u32 tx_stat_etherstatspkts64octets;
913 u32 tx_stat_etherstatspkts65octetsto127octets;
914 u32 tx_stat_etherstatspkts128octetsto255octets;
915 u32 tx_stat_etherstatspkts256octetsto511octets;
916 u32 tx_stat_etherstatspkts512octetsto1023octets;
917 u32 tx_stat_etherstatspkts1024octetsto1522octets;
918 u32 tx_stat_etherstatspktsover1522octets;
919 u32 tx_stat_dot3statsinternalmactransmiterrors;
924 u32 tx_stat_gtpkt_lo;
925 u32 tx_stat_gtpkt_hi;
926 u32 tx_stat_gtxpf_lo;
927 u32 tx_stat_gtxpf_hi;
928 u32 tx_stat_gtfcs_lo;
929 u32 tx_stat_gtfcs_hi;
930 u32 tx_stat_gtmca_lo;
931 u32 tx_stat_gtmca_hi;
932 u32 tx_stat_gtbca_lo;
933 u32 tx_stat_gtbca_hi;
934 u32 tx_stat_gtfrg_lo;
935 u32 tx_stat_gtfrg_hi;
936 u32 tx_stat_gtovr_lo;
937 u32 tx_stat_gtovr_hi;
940 u32 tx_stat_gt127_lo;
941 u32 tx_stat_gt127_hi;
942 u32 tx_stat_gt255_lo;
943 u32 tx_stat_gt255_hi;
944 u32 tx_stat_gt511_lo;
945 u32 tx_stat_gt511_hi;
946 u32 tx_stat_gt1023_lo;
947 u32 tx_stat_gt1023_hi;
948 u32 tx_stat_gt1518_lo;
949 u32 tx_stat_gt1518_hi;
950 u32 tx_stat_gt2047_lo;
951 u32 tx_stat_gt2047_hi;
952 u32 tx_stat_gt4095_lo;
953 u32 tx_stat_gt4095_hi;
954 u32 tx_stat_gt9216_lo;
955 u32 tx_stat_gt9216_hi;
956 u32 tx_stat_gt16383_lo;
957 u32 tx_stat_gt16383_hi;
958 u32 tx_stat_gtmax_lo;
959 u32 tx_stat_gtmax_hi;
960 u32 tx_stat_gtufl_lo;
961 u32 tx_stat_gtufl_hi;
962 u32 tx_stat_gterr_lo;
963 u32 tx_stat_gterr_hi;
964 u32 tx_stat_gtbyt_lo;
965 u32 tx_stat_gtbyt_hi;
969 u32 rx_stat_gr127_lo;
970 u32 rx_stat_gr127_hi;
971 u32 rx_stat_gr255_lo;
972 u32 rx_stat_gr255_hi;
973 u32 rx_stat_gr511_lo;
974 u32 rx_stat_gr511_hi;
975 u32 rx_stat_gr1023_lo;
976 u32 rx_stat_gr1023_hi;
977 u32 rx_stat_gr1518_lo;
978 u32 rx_stat_gr1518_hi;
979 u32 rx_stat_gr2047_lo;
980 u32 rx_stat_gr2047_hi;
981 u32 rx_stat_gr4095_lo;
982 u32 rx_stat_gr4095_hi;
983 u32 rx_stat_gr9216_lo;
984 u32 rx_stat_gr9216_hi;
985 u32 rx_stat_gr16383_lo;
986 u32 rx_stat_gr16383_hi;
987 u32 rx_stat_grmax_lo;
988 u32 rx_stat_grmax_hi;
989 u32 rx_stat_grpkt_lo;
990 u32 rx_stat_grpkt_hi;
991 u32 rx_stat_grfcs_lo;
992 u32 rx_stat_grfcs_hi;
993 u32 rx_stat_grmca_lo;
994 u32 rx_stat_grmca_hi;
995 u32 rx_stat_grbca_lo;
996 u32 rx_stat_grbca_hi;
997 u32 rx_stat_grxcf_lo;
998 u32 rx_stat_grxcf_hi;
999 u32 rx_stat_grxpf_lo;
1000 u32 rx_stat_grxpf_hi;
1001 u32 rx_stat_grxuo_lo;
1002 u32 rx_stat_grxuo_hi;
1003 u32 rx_stat_grjbr_lo;
1004 u32 rx_stat_grjbr_hi;
1005 u32 rx_stat_grovr_lo;
1006 u32 rx_stat_grovr_hi;
1007 u32 rx_stat_grflr_lo;
1008 u32 rx_stat_grflr_hi;
1009 u32 rx_stat_grmeg_lo;
1010 u32 rx_stat_grmeg_hi;
1011 u32 rx_stat_grmeb_lo;
1012 u32 rx_stat_grmeb_hi;
1013 u32 rx_stat_grbyt_lo;
1014 u32 rx_stat_grbyt_hi;
1015 u32 rx_stat_grund_lo;
1016 u32 rx_stat_grund_hi;
1017 u32 rx_stat_grfrg_lo;
1018 u32 rx_stat_grfrg_hi;
1019 u32 rx_stat_grerb_lo;
1020 u32 rx_stat_grerb_hi;
1021 u32 rx_stat_grfre_lo;
1022 u32 rx_stat_grfre_hi;
1023 u32 rx_stat_gripj_lo;
1024 u32 rx_stat_gripj_hi;
1029 struct emac_stats emac_stats;
1030 struct bmac_stats bmac_stats;
1036 u32 rx_stat_ifhcinbadoctets_hi;
1037 u32 rx_stat_ifhcinbadoctets_lo;
1039 /* out_bad_octets */
1040 u32 tx_stat_ifhcoutbadoctets_hi;
1041 u32 tx_stat_ifhcoutbadoctets_lo;
1043 /* crc_receive_errors */
1044 u32 rx_stat_dot3statsfcserrors_hi;
1045 u32 rx_stat_dot3statsfcserrors_lo;
1046 /* alignment_errors */
1047 u32 rx_stat_dot3statsalignmenterrors_hi;
1048 u32 rx_stat_dot3statsalignmenterrors_lo;
1049 /* carrier_sense_errors */
1050 u32 rx_stat_dot3statscarriersenseerrors_hi;
1051 u32 rx_stat_dot3statscarriersenseerrors_lo;
1052 /* false_carrier_detections */
1053 u32 rx_stat_falsecarriererrors_hi;
1054 u32 rx_stat_falsecarriererrors_lo;
1056 /* runt_packets_received */
1057 u32 rx_stat_etherstatsundersizepkts_hi;
1058 u32 rx_stat_etherstatsundersizepkts_lo;
1059 /* jabber_packets_received */
1060 u32 rx_stat_dot3statsframestoolong_hi;
1061 u32 rx_stat_dot3statsframestoolong_lo;
1063 /* error_runt_packets_received */
1064 u32 rx_stat_etherstatsfragments_hi;
1065 u32 rx_stat_etherstatsfragments_lo;
1066 /* error_jabber_packets_received */
1067 u32 rx_stat_etherstatsjabbers_hi;
1068 u32 rx_stat_etherstatsjabbers_lo;
1070 /* control_frames_received */
1071 u32 rx_stat_maccontrolframesreceived_hi;
1072 u32 rx_stat_maccontrolframesreceived_lo;
1073 u32 rx_stat_bmac_xpf_hi;
1074 u32 rx_stat_bmac_xpf_lo;
1075 u32 rx_stat_bmac_xcf_hi;
1076 u32 rx_stat_bmac_xcf_lo;
1078 /* xoff_state_entered */
1079 u32 rx_stat_xoffstateentered_hi;
1080 u32 rx_stat_xoffstateentered_lo;
1081 /* pause_xon_frames_received */
1082 u32 rx_stat_xonpauseframesreceived_hi;
1083 u32 rx_stat_xonpauseframesreceived_lo;
1084 /* pause_xoff_frames_received */
1085 u32 rx_stat_xoffpauseframesreceived_hi;
1086 u32 rx_stat_xoffpauseframesreceived_lo;
1087 /* pause_xon_frames_transmitted */
1088 u32 tx_stat_outxonsent_hi;
1089 u32 tx_stat_outxonsent_lo;
1090 /* pause_xoff_frames_transmitted */
1091 u32 tx_stat_outxoffsent_hi;
1092 u32 tx_stat_outxoffsent_lo;
1093 /* flow_control_done */
1094 u32 tx_stat_flowcontroldone_hi;
1095 u32 tx_stat_flowcontroldone_lo;
1097 /* ether_stats_collisions */
1098 u32 tx_stat_etherstatscollisions_hi;
1099 u32 tx_stat_etherstatscollisions_lo;
1100 /* single_collision_transmit_frames */
1101 u32 tx_stat_dot3statssinglecollisionframes_hi;
1102 u32 tx_stat_dot3statssinglecollisionframes_lo;
1103 /* multiple_collision_transmit_frames */
1104 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1105 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1106 /* deferred_transmissions */
1107 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1108 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1109 /* excessive_collision_frames */
1110 u32 tx_stat_dot3statsexcessivecollisions_hi;
1111 u32 tx_stat_dot3statsexcessivecollisions_lo;
1112 /* late_collision_frames */
1113 u32 tx_stat_dot3statslatecollisions_hi;
1114 u32 tx_stat_dot3statslatecollisions_lo;
1116 /* frames_transmitted_64_bytes */
1117 u32 tx_stat_etherstatspkts64octets_hi;
1118 u32 tx_stat_etherstatspkts64octets_lo;
1119 /* frames_transmitted_65_127_bytes */
1120 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1121 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1122 /* frames_transmitted_128_255_bytes */
1123 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1124 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1125 /* frames_transmitted_256_511_bytes */
1126 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1127 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1128 /* frames_transmitted_512_1023_bytes */
1129 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1130 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1131 /* frames_transmitted_1024_1522_bytes */
1132 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1133 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1134 /* frames_transmitted_1523_9022_bytes */
1135 u32 tx_stat_etherstatspktsover1522octets_hi;
1136 u32 tx_stat_etherstatspktsover1522octets_lo;
1137 u32 tx_stat_bmac_2047_hi;
1138 u32 tx_stat_bmac_2047_lo;
1139 u32 tx_stat_bmac_4095_hi;
1140 u32 tx_stat_bmac_4095_lo;
1141 u32 tx_stat_bmac_9216_hi;
1142 u32 tx_stat_bmac_9216_lo;
1143 u32 tx_stat_bmac_16383_hi;
1144 u32 tx_stat_bmac_16383_lo;
1146 /* internal_mac_transmit_errors */
1147 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1148 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1150 /* if_out_discards */
1151 u32 tx_stat_bmac_ufl_hi;
1152 u32 tx_stat_bmac_ufl_lo;
1156 #define MAC_STX_IDX_MAX 2
1158 struct host_port_stats {
1159 u32 host_port_stats_start;
1161 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1166 u32 host_port_stats_end;
1170 struct host_func_stats {
1171 u32 host_func_stats_start;
1173 u32 total_bytes_received_hi;
1174 u32 total_bytes_received_lo;
1176 u32 total_bytes_transmitted_hi;
1177 u32 total_bytes_transmitted_lo;
1179 u32 total_unicast_packets_received_hi;
1180 u32 total_unicast_packets_received_lo;
1182 u32 total_multicast_packets_received_hi;
1183 u32 total_multicast_packets_received_lo;
1185 u32 total_broadcast_packets_received_hi;
1186 u32 total_broadcast_packets_received_lo;
1188 u32 total_unicast_packets_transmitted_hi;
1189 u32 total_unicast_packets_transmitted_lo;
1191 u32 total_multicast_packets_transmitted_hi;
1192 u32 total_multicast_packets_transmitted_lo;
1194 u32 total_broadcast_packets_transmitted_hi;
1195 u32 total_broadcast_packets_transmitted_lo;
1197 u32 valid_bytes_received_hi;
1198 u32 valid_bytes_received_lo;
1200 u32 host_func_stats_end;
1204 #define BCM_5710_FW_MAJOR_VERSION 4
1205 #define BCM_5710_FW_MINOR_VERSION 8
1206 #define BCM_5710_FW_REVISION_VERSION 53
1207 #define BCM_5710_FW_ENGINEERING_VERSION 0
1208 #define BCM_5710_FW_COMPILE_FLAGS 1
1214 struct atten_def_status_block {
1216 __le32 attn_bits_ack;
1219 __le16 attn_bits_index;
1225 * common data for all protocols
1227 struct doorbell_hdr {
1229 #define DOORBELL_HDR_RX (0x1<<0)
1230 #define DOORBELL_HDR_RX_SHIFT 0
1231 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1232 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1233 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1234 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1235 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1236 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1240 * doorbell message sent to the chip
1243 #if defined(__BIG_ENDIAN)
1246 struct doorbell_hdr header;
1247 #elif defined(__LITTLE_ENDIAN)
1248 struct doorbell_hdr header;
1256 * IGU driver acknowledgement register
1258 struct igu_ack_register {
1259 #if defined(__BIG_ENDIAN)
1260 u16 sb_id_and_flags;
1261 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1262 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1263 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1264 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1265 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1266 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1267 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1268 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1269 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1270 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1271 u16 status_block_index;
1272 #elif defined(__LITTLE_ENDIAN)
1273 u16 status_block_index;
1274 u16 sb_id_and_flags;
1275 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1276 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1277 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1278 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1279 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1280 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1281 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1282 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1283 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1284 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1290 * Parser parsing flags field
1292 struct parsing_flags {
1294 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1295 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1296 #define PARSING_FLAGS_VLAN (0x1<<1)
1297 #define PARSING_FLAGS_VLAN_SHIFT 1
1298 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1299 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1300 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1301 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1302 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1303 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1304 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1305 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1306 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1307 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1308 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1309 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1310 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1311 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1312 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1313 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1314 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1315 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1316 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1317 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1318 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1319 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1330 * dmae command structure
1332 struct dmae_command {
1334 #define DMAE_COMMAND_SRC (0x1<<0)
1335 #define DMAE_COMMAND_SRC_SHIFT 0
1336 #define DMAE_COMMAND_DST (0x3<<1)
1337 #define DMAE_COMMAND_DST_SHIFT 1
1338 #define DMAE_COMMAND_C_DST (0x1<<3)
1339 #define DMAE_COMMAND_C_DST_SHIFT 3
1340 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1341 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1342 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1343 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1344 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1345 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1346 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1347 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1348 #define DMAE_COMMAND_PORT (0x1<<11)
1349 #define DMAE_COMMAND_PORT_SHIFT 11
1350 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1351 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1352 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1353 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1354 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1355 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1356 #define DMAE_COMMAND_E1HVN (0x3<<15)
1357 #define DMAE_COMMAND_E1HVN_SHIFT 15
1358 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1359 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1364 #if defined(__BIG_ENDIAN)
1367 #elif defined(__LITTLE_ENDIAN)
1376 #if defined(__BIG_ENDIAN)
1379 #elif defined(__LITTLE_ENDIAN)
1383 #if defined(__BIG_ENDIAN)
1386 #elif defined(__LITTLE_ENDIAN)
1390 #if defined(__BIG_ENDIAN)
1393 #elif defined(__LITTLE_ENDIAN)
1400 struct double_regpair {
1409 * The eth storm context of Ustorm (configuration part)
1411 struct ustorm_eth_st_context_config {
1412 #if defined(__BIG_ENDIAN)
1414 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1415 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1416 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1417 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1418 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1419 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1420 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1421 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1422 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1423 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1424 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1425 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1428 u8 sb_index_numbers;
1429 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1430 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1431 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1432 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1433 #elif defined(__LITTLE_ENDIAN)
1434 u8 sb_index_numbers;
1435 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1436 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1437 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1438 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1442 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1443 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1444 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1445 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1446 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1447 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1448 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1449 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1450 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1451 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1452 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1453 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1455 #if defined(__BIG_ENDIAN)
1457 u8 statistics_counter_id;
1458 u8 mc_alignment_log_size;
1459 #elif defined(__LITTLE_ENDIAN)
1460 u8 mc_alignment_log_size;
1461 u8 statistics_counter_id;
1464 #if defined(__BIG_ENDIAN)
1465 u8 __local_sge_prod;
1468 #elif defined(__LITTLE_ENDIAN)
1471 u8 __local_sge_prod;
1474 u32 bd_page_base_lo;
1475 u32 bd_page_base_hi;
1476 u32 sge_page_base_lo;
1477 u32 sge_page_base_hi;
1481 * The eth Rx Buffer Descriptor
1489 * The eth Rx SGE Descriptor
1497 * Local BDs and SGEs rings (in ETH)
1499 struct eth_local_rx_rings {
1500 struct eth_rx_bd __local_bd_ring[16];
1501 struct eth_rx_sge __local_sge_ring[12];
1505 * The eth storm context of Ustorm
1507 struct ustorm_eth_st_context {
1508 struct ustorm_eth_st_context_config common;
1509 struct eth_local_rx_rings __rings;
1513 * The eth storm context of Tstorm
1515 struct tstorm_eth_st_context {
1516 u32 __reserved0[28];
1520 * The eth aggregative context section of Xstorm
1522 struct xstorm_eth_extra_ag_context_section {
1523 #if defined(__BIG_ENDIAN)
1527 #elif defined(__LITTLE_ENDIAN)
1536 #if defined(__BIG_ENDIAN)
1539 u16 __tcp_agg_vars2;
1540 #elif defined(__LITTLE_ENDIAN)
1541 u16 __tcp_agg_vars2;
1549 #if defined(__BIG_ENDIAN)
1552 #elif defined(__LITTLE_ENDIAN)
1556 #if defined(__BIG_ENDIAN)
1561 #elif defined(__LITTLE_ENDIAN)
1567 u32 __tcp_agg_vars6;
1568 #if defined(__BIG_ENDIAN)
1570 u16 __tcp_agg_vars7;
1571 #elif defined(__LITTLE_ENDIAN)
1572 u16 __tcp_agg_vars7;
1577 #if defined(__BIG_ENDIAN)
1581 #elif defined(__LITTLE_ENDIAN)
1589 * The eth aggregative context of Xstorm
1591 struct xstorm_eth_ag_context {
1592 #if defined(__BIG_ENDIAN)
1596 #elif defined(__LITTLE_ENDIAN)
1601 #if defined(__BIG_ENDIAN)
1606 #elif defined(__LITTLE_ENDIAN)
1612 u32 __more_packets_to_send;
1613 #if defined(__BIG_ENDIAN)
1616 #elif defined(__LITTLE_ENDIAN)
1620 struct xstorm_eth_extra_ag_context_section __extra_section;
1621 #if defined(__BIG_ENDIAN)
1625 #elif defined(__LITTLE_ENDIAN)
1630 #if defined(__BIG_ENDIAN)
1633 #elif defined(__LITTLE_ENDIAN)
1637 #if defined(__BIG_ENDIAN)
1641 #elif defined(__LITTLE_ENDIAN)
1646 #if defined(__BIG_ENDIAN)
1649 #elif defined(__LITTLE_ENDIAN)
1654 #if defined(__BIG_ENDIAN)
1657 #elif defined(__LITTLE_ENDIAN)
1661 #if defined(__BIG_ENDIAN)
1666 #elif defined(__LITTLE_ENDIAN)
1672 #if defined(__BIG_ENDIAN)
1674 u16 __bd_ind_max_val;
1675 #elif defined(__LITTLE_ENDIAN)
1676 u16 __bd_ind_max_val;
1685 * The eth extra aggregative context section of Tstorm
1687 struct tstorm_eth_extra_ag_context_section {
1689 #if defined(__BIG_ENDIAN)
1693 #elif defined(__LITTLE_ENDIAN)
1698 #if defined(__BIG_ENDIAN)
1702 #elif defined(__LITTLE_ENDIAN)
1712 u32 __tcp_agg_vars1;
1719 * The eth aggregative context of Tstorm
1721 struct tstorm_eth_ag_context {
1722 #if defined(__BIG_ENDIAN)
1726 #elif defined(__LITTLE_ENDIAN)
1731 #if defined(__BIG_ENDIAN)
1734 #elif defined(__LITTLE_ENDIAN)
1738 struct tstorm_eth_extra_ag_context_section __extra_section;
1742 * The eth aggregative context of Cstorm
1744 struct cstorm_eth_ag_context {
1746 #if defined(__BIG_ENDIAN)
1750 #elif defined(__LITTLE_ENDIAN)
1755 u32 __num_of_treated_packet;
1756 u32 __last_packet_treated;
1757 #if defined(__BIG_ENDIAN)
1760 #elif defined(__LITTLE_ENDIAN)
1764 #if defined(__BIG_ENDIAN)
1769 #elif defined(__LITTLE_ENDIAN)
1775 #if defined(__BIG_ENDIAN)
1778 #elif defined(__LITTLE_ENDIAN)
1783 #if defined(__BIG_ENDIAN)
1786 #elif defined(__LITTLE_ENDIAN)
1790 #if defined(__BIG_ENDIAN)
1791 u16 __packet_index_th;
1793 #elif defined(__LITTLE_ENDIAN)
1795 u16 __packet_index_th;
1800 * The eth aggregative context of Ustorm
1802 struct ustorm_eth_ag_context {
1803 #if defined(__BIG_ENDIAN)
1804 u8 __aux_counter_flags;
1808 #elif defined(__LITTLE_ENDIAN)
1812 u8 __aux_counter_flags;
1814 #if defined(__BIG_ENDIAN)
1818 #elif defined(__LITTLE_ENDIAN)
1824 #if defined(__BIG_ENDIAN)
1828 #elif defined(__LITTLE_ENDIAN)
1835 #if defined(__BIG_ENDIAN)
1838 #elif defined(__LITTLE_ENDIAN)
1842 #if defined(__BIG_ENDIAN)
1844 u8 __decision_rules;
1845 u8 __decision_rule_enable_bits;
1846 #elif defined(__LITTLE_ENDIAN)
1847 u8 __decision_rule_enable_bits;
1848 u8 __decision_rules;
1854 * Timers connection context
1856 struct timers_block_context {
1861 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1862 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1863 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1864 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1865 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1866 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1870 * structure for easy accessibility to assembler
1872 struct eth_tx_bd_flags {
1874 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1875 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1876 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1877 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1878 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1879 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1880 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1881 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1882 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1883 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1884 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1885 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1886 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1887 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1888 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1889 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1893 * The eth Tx Buffer Descriptor
1901 struct eth_tx_bd_flags bd_flags;
1903 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1904 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1905 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1906 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1910 * Tx parsing BD structure for ETH,Relevant in START
1912 struct eth_tx_parse_bd {
1914 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1915 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1916 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1917 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1918 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1919 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1920 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1921 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1922 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1923 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1925 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1926 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1927 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1928 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1929 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1930 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1931 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1932 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1933 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1934 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1935 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1936 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1937 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1938 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1939 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1940 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1945 __le16 tcp_pseudo_csum;
1947 __le32 tcp_send_seq;
1951 * The last BD in the BD memory will hold a pointer to the next BD memory
1953 struct eth_tx_next_bd {
1960 * union for 3 Bd types
1962 union eth_tx_bd_types {
1963 struct eth_tx_bd reg_bd;
1964 struct eth_tx_parse_bd parse_bd;
1965 struct eth_tx_next_bd next_bd;
1969 * The eth storm context of Xstorm
1971 struct xstorm_eth_st_context {
1972 u32 tx_bd_page_base_lo;
1973 u32 tx_bd_page_base_hi;
1974 #if defined(__BIG_ENDIAN)
1977 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1978 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1979 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1980 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1981 u8 __local_tx_bd_prod;
1982 #elif defined(__LITTLE_ENDIAN)
1983 u8 __local_tx_bd_prod;
1985 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1986 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1987 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1988 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1991 u32 db_data_addr_lo;
1992 u32 db_data_addr_hi;
1996 union eth_tx_bd_types __bds[13];
2000 * The eth storm context of Cstorm
2002 struct cstorm_eth_st_context {
2003 #if defined(__BIG_ENDIAN)
2007 #elif defined(__LITTLE_ENDIAN)
2016 * Ethernet connection context
2018 struct eth_context {
2019 struct ustorm_eth_st_context ustorm_st_context;
2020 struct tstorm_eth_st_context tstorm_st_context;
2021 struct xstorm_eth_ag_context xstorm_ag_context;
2022 struct tstorm_eth_ag_context tstorm_ag_context;
2023 struct cstorm_eth_ag_context cstorm_ag_context;
2024 struct ustorm_eth_ag_context ustorm_ag_context;
2025 struct timers_block_context timers_context;
2026 struct xstorm_eth_st_context xstorm_st_context;
2027 struct cstorm_eth_st_context cstorm_st_context;
2034 struct eth_tx_doorbell {
2035 #if defined(__BIG_ENDIAN)
2038 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2039 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2040 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2041 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2042 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2043 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2044 struct doorbell_hdr hdr;
2045 #elif defined(__LITTLE_ENDIAN)
2046 struct doorbell_hdr hdr;
2048 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2049 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2050 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2051 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2052 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2053 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2060 * ustorm status block
2062 struct ustorm_def_status_block {
2063 __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2064 __le16 status_block_index;
2071 * cstorm status block
2073 struct cstorm_def_status_block {
2074 __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2075 __le16 status_block_index;
2082 * xstorm status block
2084 struct xstorm_def_status_block {
2085 __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2086 __le16 status_block_index;
2093 * tstorm status block
2095 struct tstorm_def_status_block {
2096 __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2097 __le16 status_block_index;
2106 struct host_def_status_block {
2107 struct atten_def_status_block atten_status_block;
2108 struct ustorm_def_status_block u_def_status_block;
2109 struct cstorm_def_status_block c_def_status_block;
2110 struct xstorm_def_status_block x_def_status_block;
2111 struct tstorm_def_status_block t_def_status_block;
2116 * ustorm status block
2118 struct ustorm_status_block {
2119 __le16 index_values[HC_USTORM_SB_NUM_INDICES];
2120 __le16 status_block_index;
2127 * cstorm status block
2129 struct cstorm_status_block {
2130 __le16 index_values[HC_CSTORM_SB_NUM_INDICES];
2131 __le16 status_block_index;
2140 struct host_status_block {
2141 struct ustorm_status_block u_status_block;
2142 struct cstorm_status_block c_status_block;
2147 * The data for RSS setup ramrod
2149 struct eth_client_setup_ramrod_data {
2158 * L2 dynamic host coalescing init parameters
2160 struct eth_dynamic_hc_config {
2167 * regular eth FP CQE parameters struct
2169 struct eth_fast_path_rx_cqe {
2170 u8 type_error_flags;
2171 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2172 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2173 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2174 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2175 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2176 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2177 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2178 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2179 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2180 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2181 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2182 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2183 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2184 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2186 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2187 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2188 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2189 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2190 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2191 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2192 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2193 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2194 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2195 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2196 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2197 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2198 u8 placement_offset;
2200 __le32 rss_hash_result;
2204 struct parsing_flags pars_flags;
2210 * The data for RSS setup ramrod
2212 struct eth_halt_ramrod_data {
2219 * The data for statistics query ramrod
2221 struct eth_query_ramrod_data {
2222 #if defined(__BIG_ENDIAN)
2226 #elif defined(__LITTLE_ENDIAN)
2236 * Place holder for ramrods protocol specific data
2238 struct ramrod_data {
2244 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2246 union eth_ramrod_data {
2247 struct ramrod_data general;
2252 * Eth Rx Cqe structure- general structure for ramrods
2254 struct common_ramrod_eth_rx_cqe {
2256 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2257 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2258 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2259 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2262 __le32 conn_and_cmd_data;
2263 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2264 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2265 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2266 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2267 struct ramrod_data protocol_data;
2268 __le32 reserved2[4];
2272 * Rx Last CQE in page (in ETH)
2274 struct eth_rx_cqe_next_page {
2281 * union for all eth rx cqe types (fix their sizes)
2284 struct eth_fast_path_rx_cqe fast_path_cqe;
2285 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2286 struct eth_rx_cqe_next_page next_page_cqe;
2291 * common data for all protocols
2294 __le32 conn_and_cmd_data;
2295 #define SPE_HDR_CID (0xFFFFFF<<0)
2296 #define SPE_HDR_CID_SHIFT 0
2297 #define SPE_HDR_CMD_ID (0xFF<<24)
2298 #define SPE_HDR_CMD_ID_SHIFT 24
2300 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2301 #define SPE_HDR_CONN_TYPE_SHIFT 0
2302 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2303 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2308 * Ethernet slow path element
2310 union eth_specific_data {
2311 u8 protocol_data[8];
2312 struct regpair mac_config_addr;
2313 struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2314 struct eth_halt_ramrod_data halt_ramrod_data;
2315 struct regpair leading_cqe_addr;
2316 struct regpair update_data_addr;
2317 struct eth_query_ramrod_data query_ramrod_data;
2321 * Ethernet slow path element
2325 union eth_specific_data data;
2330 * doorbell data in host memory
2332 struct eth_tx_db_data {
2333 __le32 packets_prod;
2340 * Common configuration parameters per function in Tstorm
2342 struct tstorm_eth_function_common_config {
2343 #if defined(__BIG_ENDIAN)
2344 u8 leading_client_id;
2347 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2348 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2349 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2350 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2351 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2352 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2353 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2354 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2355 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2356 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2357 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2358 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2359 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2360 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2361 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2362 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2363 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2364 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2365 #elif defined(__LITTLE_ENDIAN)
2367 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2368 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2372 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2373 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2374 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2375 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2377 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2378 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2379 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2380 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2383 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2384 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2386 u8 leading_client_id;
2392 * parameters for eth update ramrod
2394 struct eth_update_ramrod_data {
2395 struct tstorm_eth_function_common_config func_config;
2396 u8 indirectionTable[128];
2401 * MAC filtering configuration command header
2403 struct mac_configuration_hdr {
2411 * MAC address in list for ramrod
2413 struct tstorm_cam_entry {
2414 __le16 lsb_mac_addr;
2415 __le16 middle_mac_addr;
2416 __le16 msb_mac_addr;
2418 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2419 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2420 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2421 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2422 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2423 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2427 * MAC filtering: CAM target table entry
2429 struct tstorm_cam_target_table_entry {
2431 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2432 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2433 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2434 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2435 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2436 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2437 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2438 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2439 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2440 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2446 * MAC address in list for ramrod
2448 struct mac_configuration_entry {
2449 struct tstorm_cam_entry cam_entry;
2450 struct tstorm_cam_target_table_entry target_table_entry;
2454 * MAC filtering configuration command
2456 struct mac_configuration_cmd {
2457 struct mac_configuration_hdr hdr;
2458 struct mac_configuration_entry config_table[64];
2463 * MAC address in list for ramrod
2465 struct mac_configuration_entry_e1h {
2466 __le16 lsb_mac_addr;
2467 __le16 middle_mac_addr;
2468 __le16 msb_mac_addr;
2473 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2474 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2475 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2476 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2477 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2478 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2479 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2480 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2484 * MAC filtering configuration command
2486 struct mac_configuration_cmd_e1h {
2487 struct mac_configuration_hdr hdr;
2488 struct mac_configuration_entry_e1h config_table[32];
2493 * approximate-match multicast filtering for E1H per function in Tstorm
2495 struct tstorm_eth_approximate_match_multicast_filtering {
2496 u32 mcast_add_hash_bit_array[8];
2501 * Configuration parameters per client in Tstorm
2503 struct tstorm_eth_client_config {
2504 #if defined(__BIG_ENDIAN)
2505 u8 max_sges_for_packet;
2506 u8 statistics_counter_id;
2508 #elif defined(__LITTLE_ENDIAN)
2510 u8 statistics_counter_id;
2511 u8 max_sges_for_packet;
2513 #if defined(__BIG_ENDIAN)
2515 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2516 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2517 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2518 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2519 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2520 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2521 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2522 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2523 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2524 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2526 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2527 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2528 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2529 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2530 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2531 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2532 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2533 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2534 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2535 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2536 #elif defined(__LITTLE_ENDIAN)
2538 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2539 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2540 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2541 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2542 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2543 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2544 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2545 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2546 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2547 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2549 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2550 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2551 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2552 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2553 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2554 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2555 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2556 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2557 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2558 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2564 * MAC filtering configuration parameters per port in Tstorm
2566 struct tstorm_eth_mac_filter_config {
2568 u32 ucast_accept_all;
2570 u32 mcast_accept_all;
2572 u32 bcast_accept_all;
2580 * common flag to indicate existance of TPA.
2582 struct tstorm_eth_tpa_exist {
2583 #if defined(__BIG_ENDIAN)
2587 #elif defined(__LITTLE_ENDIAN)
2597 * rx rings pause data for E1h only
2599 struct ustorm_eth_rx_pause_data_e1h {
2600 #if defined(__BIG_ENDIAN)
2603 #elif defined(__LITTLE_ENDIAN)
2607 #if defined(__BIG_ENDIAN)
2610 #elif defined(__LITTLE_ENDIAN)
2614 #if defined(__BIG_ENDIAN)
2617 #elif defined(__LITTLE_ENDIAN)
2621 #if defined(__BIG_ENDIAN)
2624 #elif defined(__LITTLE_ENDIAN)
2632 * Three RX producers for ETH
2634 struct ustorm_eth_rx_producers {
2635 #if defined(__BIG_ENDIAN)
2638 #elif defined(__LITTLE_ENDIAN)
2642 #if defined(__BIG_ENDIAN)
2645 #elif defined(__LITTLE_ENDIAN)
2653 * per-port SAFC demo variables
2655 struct cmng_flags_per_port {
2656 u8 con_number[NUM_OF_PROTOCOLS];
2658 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2659 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2660 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2661 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2662 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2663 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2664 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2665 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2666 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2667 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2668 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2669 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2674 * per-port rate shaping variables
2676 struct rate_shaping_vars_per_port {
2677 u32 rs_periodic_timeout;
2683 * per-port fairness variables
2685 struct fairness_vars_per_port {
2688 u32 fairness_timeout;
2693 * per-port SAFC variables
2695 struct safc_struct_per_port {
2696 #if defined(__BIG_ENDIAN)
2699 u8 safc_timeout_usec;
2700 #elif defined(__LITTLE_ENDIAN)
2701 u8 safc_timeout_usec;
2705 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2710 * Per-port congestion management variables
2712 struct cmng_struct_per_port {
2713 struct rate_shaping_vars_per_port rs_vars;
2714 struct fairness_vars_per_port fair_vars;
2715 struct safc_struct_per_port safc_vars;
2716 struct cmng_flags_per_port flags;
2721 * Protocol-common statistics collected by the Xstorm (per client)
2723 struct xstorm_per_client_stats {
2724 struct regpair total_sent_bytes;
2725 __le32 total_sent_pkts;
2726 __le32 unicast_pkts_sent;
2727 struct regpair unicast_bytes_sent;
2728 struct regpair multicast_bytes_sent;
2729 __le32 multicast_pkts_sent;
2730 __le32 broadcast_pkts_sent;
2731 struct regpair broadcast_bytes_sent;
2732 __le16 stats_counter;
2739 * Common statistics collected by the Xstorm (per port)
2741 struct xstorm_common_stats {
2742 struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2747 * Protocol-common statistics collected by the Tstorm (per port)
2749 struct tstorm_per_port_stats {
2750 __le32 mac_filter_discard;
2751 __le32 xxoverflow_discard;
2752 __le32 brb_truncate_discard;
2758 * Protocol-common statistics collected by the Tstorm (per client)
2760 struct tstorm_per_client_stats {
2761 struct regpair total_rcv_bytes;
2762 struct regpair rcv_unicast_bytes;
2763 struct regpair rcv_broadcast_bytes;
2764 struct regpair rcv_multicast_bytes;
2765 struct regpair rcv_error_bytes;
2766 __le32 checksum_discard;
2767 __le32 packets_too_big_discard;
2768 __le32 total_rcv_pkts;
2769 __le32 rcv_unicast_pkts;
2770 __le32 rcv_broadcast_pkts;
2771 __le32 rcv_multicast_pkts;
2772 __le32 no_buff_discard;
2773 __le32 ttl0_discard;
2774 __le16 stats_counter;
2780 * Protocol-common statistics collected by the Tstorm
2782 struct tstorm_common_stats {
2783 struct tstorm_per_port_stats port_statistics;
2784 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2788 * Protocol-common statistics collected by the Ustorm (per client)
2790 struct ustorm_per_client_stats {
2791 struct regpair ucast_no_buff_bytes;
2792 struct regpair mcast_no_buff_bytes;
2793 struct regpair bcast_no_buff_bytes;
2794 __le32 ucast_no_buff_pkts;
2795 __le32 mcast_no_buff_pkts;
2796 __le32 bcast_no_buff_pkts;
2797 __le16 stats_counter;
2802 * Protocol-common statistics collected by the Ustorm
2804 struct ustorm_common_stats {
2805 struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
2809 * Eth statistics query structure for the eth_stats_query ramrod
2811 struct eth_stats_query {
2812 struct xstorm_common_stats xstorm_common;
2813 struct tstorm_common_stats tstorm_common;
2814 struct ustorm_common_stats ustorm_common;
2819 * per-vnic fairness variables
2821 struct fairness_vars_per_vn {
2822 u32 cos_credit_delta[MAX_COS_NUMBER];
2823 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2824 u32 vn_credit_delta;
2830 * FW version stored in the Xstorm RAM
2833 #if defined(__BIG_ENDIAN)
2838 #elif defined(__LITTLE_ENDIAN)
2845 #define FW_VERSION_OPTIMIZED (0x1<<0)
2846 #define FW_VERSION_OPTIMIZED_SHIFT 0
2847 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2848 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2849 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2850 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2851 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2852 #define __FW_VERSION_RESERVED_SHIFT 4
2857 * FW version stored in first line of pram
2859 struct pram_fw_version {
2865 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2866 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2867 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2868 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2869 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2870 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2871 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2872 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2873 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2874 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2879 * a single rate shaping counter. can be used as protocol or vnic counter
2881 struct rate_shaping_counter {
2883 #if defined(__BIG_ENDIAN)
2886 #elif defined(__LITTLE_ENDIAN)
2894 * per-vnic rate shaping variables
2896 struct rate_shaping_vars_per_vn {
2897 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2898 struct rate_shaping_counter vn_counter;
2903 * The send queue element
2905 struct slow_path_element {
2907 u8 protocol_data[8];
2912 * eth/toe flags that indicate if to query
2914 struct stats_indication_flags {