1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/firmware.h>
50 #include <linux/log2.h>
51 #include <linux/list.h>
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
60 #define DRV_MODULE_NAME "bnx2"
61 #define PFX DRV_MODULE_NAME ": "
62 #define DRV_MODULE_VERSION "2.0.2"
63 #define DRV_MODULE_RELDATE "Aug 21, 2009"
64 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j3.fw"
65 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
66 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j3.fw"
67 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j3.fw"
68 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j3.fw"
70 #define RUN_AT(x) (jiffies + (x))
72 /* Time in jiffies before concluding the transmitter is hung. */
73 #define TX_TIMEOUT (5*HZ)
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
79 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
80 MODULE_LICENSE("GPL");
81 MODULE_VERSION(DRV_MODULE_VERSION);
82 MODULE_FIRMWARE(FW_MIPS_FILE_06);
83 MODULE_FIRMWARE(FW_RV2P_FILE_06);
84 MODULE_FIRMWARE(FW_MIPS_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09);
86 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
88 static int disable_msi = 0;
90 module_param(disable_msi, int, 0);
91 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
107 /* indexed by board_t, above */
110 } board_info[] __devinitdata = {
111 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
112 { "HP NC370T Multifunction Gigabit Server Adapter" },
113 { "HP NC370i Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
115 { "HP NC370F Multifunction Gigabit Server Adapter" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
119 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
121 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
124 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
141 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
143 { PCI_VENDOR_ID_BROADCOM, 0x163b,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
145 { PCI_VENDOR_ID_BROADCOM, 0x163c,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
150 static const struct flash_spec flash_table[] =
152 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
153 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
155 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
156 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
157 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
159 /* Expansion entry 0001 */
160 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
162 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
164 /* Saifun SA25F010 (non-buffered flash) */
165 /* strap, cfg1, & write1 need updates */
166 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
168 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
169 "Non-buffered flash (128kB)"},
170 /* Saifun SA25F020 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
175 "Non-buffered flash (256kB)"},
176 /* Expansion entry 0100 */
177 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
181 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
182 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
184 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
185 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
186 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
187 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
189 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
190 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
191 /* Saifun SA25F005 (non-buffered flash) */
192 /* strap, cfg1, & write1 need updates */
193 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
196 "Non-buffered flash (64kB)"},
198 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
199 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
200 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
202 /* Expansion entry 1001 */
203 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
204 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
205 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
207 /* Expansion entry 1010 */
208 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
210 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
212 /* ATMEL AT45DB011B (buffered flash) */
213 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
214 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
215 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
216 "Buffered flash (128kB)"},
217 /* Expansion entry 1100 */
218 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222 /* Expansion entry 1101 */
223 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
227 /* Ateml Expansion entry 1110 */
228 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
230 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
231 "Entry 1110 (Atmel)"},
232 /* ATMEL AT45DB021B (buffered flash) */
233 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
234 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
235 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
236 "Buffered flash (256kB)"},
239 static const struct flash_spec flash_5709 = {
240 .flags = BNX2_NV_BUFFERED,
241 .page_bits = BCM5709_FLASH_PAGE_BITS,
242 .page_size = BCM5709_FLASH_PAGE_SIZE,
243 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
244 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
245 .name = "5709 Buffered flash (256kB)",
248 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
250 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
256 /* The ring uses 256 indices for 255 entries, one of them
257 * needs to be skipped.
259 diff = txr->tx_prod - txr->tx_cons;
260 if (unlikely(diff >= TX_DESC_CNT)) {
262 if (diff == TX_DESC_CNT)
263 diff = MAX_TX_DESC_CNT;
265 return (bp->tx_ring_size - diff);
269 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
273 spin_lock_bh(&bp->indirect_lock);
274 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
275 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
276 spin_unlock_bh(&bp->indirect_lock);
281 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
283 spin_lock_bh(&bp->indirect_lock);
284 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
285 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
286 spin_unlock_bh(&bp->indirect_lock);
290 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
292 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
296 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
298 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
302 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305 spin_lock_bh(&bp->indirect_lock);
306 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
310 REG_WR(bp, BNX2_CTX_CTX_CTRL,
311 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
312 for (i = 0; i < 5; i++) {
313 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
314 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
319 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
320 REG_WR(bp, BNX2_CTX_DATA, val);
322 spin_unlock_bh(&bp->indirect_lock);
327 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
329 struct bnx2 *bp = netdev_priv(dev);
330 struct drv_ctl_io *io = &info->data.io;
333 case DRV_CTL_IO_WR_CMD:
334 bnx2_reg_wr_ind(bp, io->offset, io->data);
336 case DRV_CTL_IO_RD_CMD:
337 io->data = bnx2_reg_rd_ind(bp, io->offset);
339 case DRV_CTL_CTX_WR_CMD:
340 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
348 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
351 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 if (bp->flags & BNX2_FLAG_USING_MSIX) {
355 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
356 bnapi->cnic_present = 0;
357 sb_id = bp->irq_nvecs;
358 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
360 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
361 bnapi->cnic_tag = bnapi->last_status_idx;
362 bnapi->cnic_present = 1;
364 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
368 cp->irq_arr[0].status_blk = (void *)
369 ((unsigned long) bnapi->status_blk.msi +
370 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
371 cp->irq_arr[0].status_blk_num = sb_id;
375 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 struct bnx2 *bp = netdev_priv(dev);
379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
384 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 bp->cnic_data = data;
388 rcu_assign_pointer(bp->cnic_ops, ops);
391 cp->drv_state = CNIC_DRV_STATE_REGD;
393 bnx2_setup_cnic_irq_info(bp);
398 static int bnx2_unregister_cnic(struct net_device *dev)
400 struct bnx2 *bp = netdev_priv(dev);
401 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
402 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
404 mutex_lock(&bp->cnic_lock);
406 bnapi->cnic_present = 0;
407 rcu_assign_pointer(bp->cnic_ops, NULL);
408 mutex_unlock(&bp->cnic_lock);
413 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
415 struct bnx2 *bp = netdev_priv(dev);
416 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
418 cp->drv_owner = THIS_MODULE;
419 cp->chip_id = bp->chip_id;
421 cp->io_base = bp->regview;
422 cp->drv_ctl = bnx2_drv_ctl;
423 cp->drv_register_cnic = bnx2_register_cnic;
424 cp->drv_unregister_cnic = bnx2_unregister_cnic;
428 EXPORT_SYMBOL(bnx2_cnic_probe);
431 bnx2_cnic_stop(struct bnx2 *bp)
433 struct cnic_ops *c_ops;
434 struct cnic_ctl_info info;
436 mutex_lock(&bp->cnic_lock);
437 c_ops = bp->cnic_ops;
439 info.cmd = CNIC_CTL_STOP_CMD;
440 c_ops->cnic_ctl(bp->cnic_data, &info);
442 mutex_unlock(&bp->cnic_lock);
446 bnx2_cnic_start(struct bnx2 *bp)
448 struct cnic_ops *c_ops;
449 struct cnic_ctl_info info;
451 mutex_lock(&bp->cnic_lock);
452 c_ops = bp->cnic_ops;
454 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
455 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
457 bnapi->cnic_tag = bnapi->last_status_idx;
459 info.cmd = CNIC_CTL_START_CMD;
460 c_ops->cnic_ctl(bp->cnic_data, &info);
462 mutex_unlock(&bp->cnic_lock);
468 bnx2_cnic_stop(struct bnx2 *bp)
473 bnx2_cnic_start(struct bnx2 *bp)
480 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
485 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
486 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
487 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
489 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
490 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
495 val1 = (bp->phy_addr << 21) | (reg << 16) |
496 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
497 BNX2_EMAC_MDIO_COMM_START_BUSY;
498 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
500 for (i = 0; i < 50; i++) {
503 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
504 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
507 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
508 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
514 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
523 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
524 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
525 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
527 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
528 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
537 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
542 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
543 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
544 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
546 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
547 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
552 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
553 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
554 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
555 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
557 for (i = 0; i < 50; i++) {
560 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
561 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
567 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
572 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
573 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
574 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
576 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
577 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
586 bnx2_disable_int(struct bnx2 *bp)
589 struct bnx2_napi *bnapi;
591 for (i = 0; i < bp->irq_nvecs; i++) {
592 bnapi = &bp->bnx2_napi[i];
593 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
594 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
596 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
600 bnx2_enable_int(struct bnx2 *bp)
603 struct bnx2_napi *bnapi;
605 for (i = 0; i < bp->irq_nvecs; i++) {
606 bnapi = &bp->bnx2_napi[i];
608 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
609 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
610 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
611 bnapi->last_status_idx);
613 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
614 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
615 bnapi->last_status_idx);
617 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
621 bnx2_disable_int_sync(struct bnx2 *bp)
625 atomic_inc(&bp->intr_sem);
626 if (!netif_running(bp->dev))
629 bnx2_disable_int(bp);
630 for (i = 0; i < bp->irq_nvecs; i++)
631 synchronize_irq(bp->irq_tbl[i].vector);
635 bnx2_napi_disable(struct bnx2 *bp)
639 for (i = 0; i < bp->irq_nvecs; i++)
640 napi_disable(&bp->bnx2_napi[i].napi);
644 bnx2_napi_enable(struct bnx2 *bp)
648 for (i = 0; i < bp->irq_nvecs; i++)
649 napi_enable(&bp->bnx2_napi[i].napi);
653 bnx2_netif_stop(struct bnx2 *bp)
656 bnx2_disable_int_sync(bp);
657 if (netif_running(bp->dev)) {
658 bnx2_napi_disable(bp);
659 netif_tx_disable(bp->dev);
660 bp->dev->trans_start = jiffies; /* prevent tx timeout */
665 bnx2_netif_start(struct bnx2 *bp)
667 if (atomic_dec_and_test(&bp->intr_sem)) {
668 if (netif_running(bp->dev)) {
669 netif_tx_wake_all_queues(bp->dev);
670 bnx2_napi_enable(bp);
678 bnx2_free_tx_mem(struct bnx2 *bp)
682 for (i = 0; i < bp->num_tx_rings; i++) {
683 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
684 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
686 if (txr->tx_desc_ring) {
687 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
689 txr->tx_desc_mapping);
690 txr->tx_desc_ring = NULL;
692 kfree(txr->tx_buf_ring);
693 txr->tx_buf_ring = NULL;
698 bnx2_free_rx_mem(struct bnx2 *bp)
702 for (i = 0; i < bp->num_rx_rings; i++) {
703 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
704 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
707 for (j = 0; j < bp->rx_max_ring; j++) {
708 if (rxr->rx_desc_ring[j])
709 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
710 rxr->rx_desc_ring[j],
711 rxr->rx_desc_mapping[j]);
712 rxr->rx_desc_ring[j] = NULL;
714 vfree(rxr->rx_buf_ring);
715 rxr->rx_buf_ring = NULL;
717 for (j = 0; j < bp->rx_max_pg_ring; j++) {
718 if (rxr->rx_pg_desc_ring[j])
719 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
720 rxr->rx_pg_desc_ring[j],
721 rxr->rx_pg_desc_mapping[j]);
722 rxr->rx_pg_desc_ring[j] = NULL;
724 vfree(rxr->rx_pg_ring);
725 rxr->rx_pg_ring = NULL;
730 bnx2_alloc_tx_mem(struct bnx2 *bp)
734 for (i = 0; i < bp->num_tx_rings; i++) {
735 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
736 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
738 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
739 if (txr->tx_buf_ring == NULL)
743 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
744 &txr->tx_desc_mapping);
745 if (txr->tx_desc_ring == NULL)
752 bnx2_alloc_rx_mem(struct bnx2 *bp)
756 for (i = 0; i < bp->num_rx_rings; i++) {
757 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
758 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
762 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
763 if (rxr->rx_buf_ring == NULL)
766 memset(rxr->rx_buf_ring, 0,
767 SW_RXBD_RING_SIZE * bp->rx_max_ring);
769 for (j = 0; j < bp->rx_max_ring; j++) {
770 rxr->rx_desc_ring[j] =
771 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
772 &rxr->rx_desc_mapping[j]);
773 if (rxr->rx_desc_ring[j] == NULL)
778 if (bp->rx_pg_ring_size) {
779 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
781 if (rxr->rx_pg_ring == NULL)
784 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
788 for (j = 0; j < bp->rx_max_pg_ring; j++) {
789 rxr->rx_pg_desc_ring[j] =
790 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
791 &rxr->rx_pg_desc_mapping[j]);
792 if (rxr->rx_pg_desc_ring[j] == NULL)
801 bnx2_free_mem(struct bnx2 *bp)
804 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
806 bnx2_free_tx_mem(bp);
807 bnx2_free_rx_mem(bp);
809 for (i = 0; i < bp->ctx_pages; i++) {
810 if (bp->ctx_blk[i]) {
811 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
813 bp->ctx_blk_mapping[i]);
814 bp->ctx_blk[i] = NULL;
817 if (bnapi->status_blk.msi) {
818 pci_free_consistent(bp->pdev, bp->status_stats_size,
819 bnapi->status_blk.msi,
820 bp->status_blk_mapping);
821 bnapi->status_blk.msi = NULL;
822 bp->stats_blk = NULL;
827 bnx2_alloc_mem(struct bnx2 *bp)
829 int i, status_blk_size, err;
830 struct bnx2_napi *bnapi;
833 /* Combine status and statistics blocks into one allocation. */
834 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
835 if (bp->flags & BNX2_FLAG_MSIX_CAP)
836 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
837 BNX2_SBLK_MSIX_ALIGN_SIZE);
838 bp->status_stats_size = status_blk_size +
839 sizeof(struct statistics_block);
841 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
842 &bp->status_blk_mapping);
843 if (status_blk == NULL)
846 memset(status_blk, 0, bp->status_stats_size);
848 bnapi = &bp->bnx2_napi[0];
849 bnapi->status_blk.msi = status_blk;
850 bnapi->hw_tx_cons_ptr =
851 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
852 bnapi->hw_rx_cons_ptr =
853 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
854 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
855 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
856 struct status_block_msix *sblk;
858 bnapi = &bp->bnx2_napi[i];
860 sblk = (void *) (status_blk +
861 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
862 bnapi->status_blk.msix = sblk;
863 bnapi->hw_tx_cons_ptr =
864 &sblk->status_tx_quick_consumer_index;
865 bnapi->hw_rx_cons_ptr =
866 &sblk->status_rx_quick_consumer_index;
867 bnapi->int_num = i << 24;
871 bp->stats_blk = status_blk + status_blk_size;
873 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
875 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
876 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
877 if (bp->ctx_pages == 0)
879 for (i = 0; i < bp->ctx_pages; i++) {
880 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
882 &bp->ctx_blk_mapping[i]);
883 if (bp->ctx_blk[i] == NULL)
888 err = bnx2_alloc_rx_mem(bp);
892 err = bnx2_alloc_tx_mem(bp);
904 bnx2_report_fw_link(struct bnx2 *bp)
906 u32 fw_link_status = 0;
908 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
914 switch (bp->line_speed) {
916 if (bp->duplex == DUPLEX_HALF)
917 fw_link_status = BNX2_LINK_STATUS_10HALF;
919 fw_link_status = BNX2_LINK_STATUS_10FULL;
922 if (bp->duplex == DUPLEX_HALF)
923 fw_link_status = BNX2_LINK_STATUS_100HALF;
925 fw_link_status = BNX2_LINK_STATUS_100FULL;
928 if (bp->duplex == DUPLEX_HALF)
929 fw_link_status = BNX2_LINK_STATUS_1000HALF;
931 fw_link_status = BNX2_LINK_STATUS_1000FULL;
934 if (bp->duplex == DUPLEX_HALF)
935 fw_link_status = BNX2_LINK_STATUS_2500HALF;
937 fw_link_status = BNX2_LINK_STATUS_2500FULL;
941 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
944 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
946 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
947 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
949 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
950 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
951 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
953 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
957 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
959 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
963 bnx2_xceiver_str(struct bnx2 *bp)
965 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
966 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
971 bnx2_report_link(struct bnx2 *bp)
974 netif_carrier_on(bp->dev);
975 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
976 bnx2_xceiver_str(bp));
978 printk("%d Mbps ", bp->line_speed);
980 if (bp->duplex == DUPLEX_FULL)
981 printk("full duplex");
983 printk("half duplex");
986 if (bp->flow_ctrl & FLOW_CTRL_RX) {
987 printk(", receive ");
988 if (bp->flow_ctrl & FLOW_CTRL_TX)
989 printk("& transmit ");
992 printk(", transmit ");
994 printk("flow control ON");
999 netif_carrier_off(bp->dev);
1000 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
1001 bnx2_xceiver_str(bp));
1004 bnx2_report_fw_link(bp);
1008 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1010 u32 local_adv, remote_adv;
1013 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1014 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1016 if (bp->duplex == DUPLEX_FULL) {
1017 bp->flow_ctrl = bp->req_flow_ctrl;
1022 if (bp->duplex != DUPLEX_FULL) {
1026 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1027 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1030 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1031 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1032 bp->flow_ctrl |= FLOW_CTRL_TX;
1033 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1034 bp->flow_ctrl |= FLOW_CTRL_RX;
1038 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1039 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1041 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1042 u32 new_local_adv = 0;
1043 u32 new_remote_adv = 0;
1045 if (local_adv & ADVERTISE_1000XPAUSE)
1046 new_local_adv |= ADVERTISE_PAUSE_CAP;
1047 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1048 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1049 if (remote_adv & ADVERTISE_1000XPAUSE)
1050 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1051 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1052 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1054 local_adv = new_local_adv;
1055 remote_adv = new_remote_adv;
1058 /* See Table 28B-3 of 802.3ab-1999 spec. */
1059 if (local_adv & ADVERTISE_PAUSE_CAP) {
1060 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1061 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1062 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1064 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1065 bp->flow_ctrl = FLOW_CTRL_RX;
1069 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1070 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1074 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1075 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1076 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1078 bp->flow_ctrl = FLOW_CTRL_TX;
1084 bnx2_5709s_linkup(struct bnx2 *bp)
1090 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1091 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1092 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1094 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1095 bp->line_speed = bp->req_line_speed;
1096 bp->duplex = bp->req_duplex;
1099 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1101 case MII_BNX2_GP_TOP_AN_SPEED_10:
1102 bp->line_speed = SPEED_10;
1104 case MII_BNX2_GP_TOP_AN_SPEED_100:
1105 bp->line_speed = SPEED_100;
1107 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1108 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1109 bp->line_speed = SPEED_1000;
1111 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1112 bp->line_speed = SPEED_2500;
1115 if (val & MII_BNX2_GP_TOP_AN_FD)
1116 bp->duplex = DUPLEX_FULL;
1118 bp->duplex = DUPLEX_HALF;
1123 bnx2_5708s_linkup(struct bnx2 *bp)
1128 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1129 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1130 case BCM5708S_1000X_STAT1_SPEED_10:
1131 bp->line_speed = SPEED_10;
1133 case BCM5708S_1000X_STAT1_SPEED_100:
1134 bp->line_speed = SPEED_100;
1136 case BCM5708S_1000X_STAT1_SPEED_1G:
1137 bp->line_speed = SPEED_1000;
1139 case BCM5708S_1000X_STAT1_SPEED_2G5:
1140 bp->line_speed = SPEED_2500;
1143 if (val & BCM5708S_1000X_STAT1_FD)
1144 bp->duplex = DUPLEX_FULL;
1146 bp->duplex = DUPLEX_HALF;
1152 bnx2_5706s_linkup(struct bnx2 *bp)
1154 u32 bmcr, local_adv, remote_adv, common;
1157 bp->line_speed = SPEED_1000;
1159 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1160 if (bmcr & BMCR_FULLDPLX) {
1161 bp->duplex = DUPLEX_FULL;
1164 bp->duplex = DUPLEX_HALF;
1167 if (!(bmcr & BMCR_ANENABLE)) {
1171 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1172 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1174 common = local_adv & remote_adv;
1175 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1177 if (common & ADVERTISE_1000XFULL) {
1178 bp->duplex = DUPLEX_FULL;
1181 bp->duplex = DUPLEX_HALF;
1189 bnx2_copper_linkup(struct bnx2 *bp)
1193 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1194 if (bmcr & BMCR_ANENABLE) {
1195 u32 local_adv, remote_adv, common;
1197 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1198 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1200 common = local_adv & (remote_adv >> 2);
1201 if (common & ADVERTISE_1000FULL) {
1202 bp->line_speed = SPEED_1000;
1203 bp->duplex = DUPLEX_FULL;
1205 else if (common & ADVERTISE_1000HALF) {
1206 bp->line_speed = SPEED_1000;
1207 bp->duplex = DUPLEX_HALF;
1210 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1211 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1213 common = local_adv & remote_adv;
1214 if (common & ADVERTISE_100FULL) {
1215 bp->line_speed = SPEED_100;
1216 bp->duplex = DUPLEX_FULL;
1218 else if (common & ADVERTISE_100HALF) {
1219 bp->line_speed = SPEED_100;
1220 bp->duplex = DUPLEX_HALF;
1222 else if (common & ADVERTISE_10FULL) {
1223 bp->line_speed = SPEED_10;
1224 bp->duplex = DUPLEX_FULL;
1226 else if (common & ADVERTISE_10HALF) {
1227 bp->line_speed = SPEED_10;
1228 bp->duplex = DUPLEX_HALF;
1237 if (bmcr & BMCR_SPEED100) {
1238 bp->line_speed = SPEED_100;
1241 bp->line_speed = SPEED_10;
1243 if (bmcr & BMCR_FULLDPLX) {
1244 bp->duplex = DUPLEX_FULL;
1247 bp->duplex = DUPLEX_HALF;
1255 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1257 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1259 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1260 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1263 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1264 u32 lo_water, hi_water;
1266 if (bp->flow_ctrl & FLOW_CTRL_TX)
1267 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1269 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1270 if (lo_water >= bp->rx_ring_size)
1273 hi_water = bp->rx_ring_size / 4;
1275 if (hi_water <= lo_water)
1278 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1279 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1283 else if (hi_water == 0)
1285 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1287 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1291 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1296 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1299 bnx2_init_rx_context(bp, cid);
1304 bnx2_set_mac_link(struct bnx2 *bp)
1308 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1309 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1310 (bp->duplex == DUPLEX_HALF)) {
1311 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1314 /* Configure the EMAC mode register. */
1315 val = REG_RD(bp, BNX2_EMAC_MODE);
1317 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1318 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1319 BNX2_EMAC_MODE_25G_MODE);
1322 switch (bp->line_speed) {
1324 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1325 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1330 val |= BNX2_EMAC_MODE_PORT_MII;
1333 val |= BNX2_EMAC_MODE_25G_MODE;
1336 val |= BNX2_EMAC_MODE_PORT_GMII;
1341 val |= BNX2_EMAC_MODE_PORT_GMII;
1344 /* Set the MAC to operate in the appropriate duplex mode. */
1345 if (bp->duplex == DUPLEX_HALF)
1346 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1347 REG_WR(bp, BNX2_EMAC_MODE, val);
1349 /* Enable/disable rx PAUSE. */
1350 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1352 if (bp->flow_ctrl & FLOW_CTRL_RX)
1353 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1354 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1356 /* Enable/disable tx PAUSE. */
1357 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1358 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1360 if (bp->flow_ctrl & FLOW_CTRL_TX)
1361 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1362 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1364 /* Acknowledge the interrupt. */
1365 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1367 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1368 bnx2_init_all_rx_contexts(bp);
1372 bnx2_enable_bmsr1(struct bnx2 *bp)
1374 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1375 (CHIP_NUM(bp) == CHIP_NUM_5709))
1376 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1377 MII_BNX2_BLK_ADDR_GP_STATUS);
1381 bnx2_disable_bmsr1(struct bnx2 *bp)
1383 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1384 (CHIP_NUM(bp) == CHIP_NUM_5709))
1385 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1386 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1390 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1395 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1398 if (bp->autoneg & AUTONEG_SPEED)
1399 bp->advertising |= ADVERTISED_2500baseX_Full;
1401 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1402 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1404 bnx2_read_phy(bp, bp->mii_up1, &up1);
1405 if (!(up1 & BCM5708S_UP1_2G5)) {
1406 up1 |= BCM5708S_UP1_2G5;
1407 bnx2_write_phy(bp, bp->mii_up1, up1);
1411 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1412 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1413 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1419 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1424 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1427 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1428 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1430 bnx2_read_phy(bp, bp->mii_up1, &up1);
1431 if (up1 & BCM5708S_UP1_2G5) {
1432 up1 &= ~BCM5708S_UP1_2G5;
1433 bnx2_write_phy(bp, bp->mii_up1, up1);
1437 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1438 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1439 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1445 bnx2_enable_forced_2g5(struct bnx2 *bp)
1449 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1452 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1455 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1456 MII_BNX2_BLK_ADDR_SERDES_DIG);
1457 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1458 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1459 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1460 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1462 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1463 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1464 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1466 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1467 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1468 bmcr |= BCM5708S_BMCR_FORCE_2500;
1473 if (bp->autoneg & AUTONEG_SPEED) {
1474 bmcr &= ~BMCR_ANENABLE;
1475 if (bp->req_duplex == DUPLEX_FULL)
1476 bmcr |= BMCR_FULLDPLX;
1478 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1482 bnx2_disable_forced_2g5(struct bnx2 *bp)
1486 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1489 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1492 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1493 MII_BNX2_BLK_ADDR_SERDES_DIG);
1494 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1495 val &= ~MII_BNX2_SD_MISC1_FORCE;
1496 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1498 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1499 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1500 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1502 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1503 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1504 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1509 if (bp->autoneg & AUTONEG_SPEED)
1510 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1511 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1515 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1519 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1520 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1522 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1524 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1528 bnx2_set_link(struct bnx2 *bp)
1533 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1538 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1541 link_up = bp->link_up;
1543 bnx2_enable_bmsr1(bp);
1544 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_disable_bmsr1(bp);
1548 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1549 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1552 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1553 bnx2_5706s_force_link_dn(bp, 0);
1554 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1556 val = REG_RD(bp, BNX2_EMAC_STATUS);
1558 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1559 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562 if ((val & BNX2_EMAC_STATUS_LINK) &&
1563 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1564 bmsr |= BMSR_LSTATUS;
1566 bmsr &= ~BMSR_LSTATUS;
1569 if (bmsr & BMSR_LSTATUS) {
1572 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1573 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1574 bnx2_5706s_linkup(bp);
1575 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1576 bnx2_5708s_linkup(bp);
1577 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1578 bnx2_5709s_linkup(bp);
1581 bnx2_copper_linkup(bp);
1583 bnx2_resolve_flow_ctrl(bp);
1586 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1587 (bp->autoneg & AUTONEG_SPEED))
1588 bnx2_disable_forced_2g5(bp);
1590 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1593 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1594 bmcr |= BMCR_ANENABLE;
1595 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1597 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1602 if (bp->link_up != link_up) {
1603 bnx2_report_link(bp);
1606 bnx2_set_mac_link(bp);
1612 bnx2_reset_phy(struct bnx2 *bp)
1617 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1619 #define PHY_RESET_MAX_WAIT 100
1620 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1623 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1624 if (!(reg & BMCR_RESET)) {
1629 if (i == PHY_RESET_MAX_WAIT) {
1636 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1640 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1641 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1643 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1644 adv = ADVERTISE_1000XPAUSE;
1647 adv = ADVERTISE_PAUSE_CAP;
1650 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1651 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1652 adv = ADVERTISE_1000XPSE_ASYM;
1655 adv = ADVERTISE_PAUSE_ASYM;
1658 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1659 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1660 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1663 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1669 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1672 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1673 __releases(&bp->phy_lock)
1674 __acquires(&bp->phy_lock)
1676 u32 speed_arg = 0, pause_adv;
1678 pause_adv = bnx2_phy_get_pause_adv(bp);
1680 if (bp->autoneg & AUTONEG_SPEED) {
1681 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1682 if (bp->advertising & ADVERTISED_10baseT_Half)
1683 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1684 if (bp->advertising & ADVERTISED_10baseT_Full)
1685 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1686 if (bp->advertising & ADVERTISED_100baseT_Half)
1687 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1688 if (bp->advertising & ADVERTISED_100baseT_Full)
1689 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1690 if (bp->advertising & ADVERTISED_1000baseT_Full)
1691 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1692 if (bp->advertising & ADVERTISED_2500baseX_Full)
1693 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 if (bp->req_line_speed == SPEED_2500)
1696 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1697 else if (bp->req_line_speed == SPEED_1000)
1698 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1699 else if (bp->req_line_speed == SPEED_100) {
1700 if (bp->req_duplex == DUPLEX_FULL)
1701 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1703 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1704 } else if (bp->req_line_speed == SPEED_10) {
1705 if (bp->req_duplex == DUPLEX_FULL)
1706 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1708 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1712 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1713 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1714 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1715 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1717 if (port == PORT_TP)
1718 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1719 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1721 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1723 spin_unlock_bh(&bp->phy_lock);
1724 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1725 spin_lock_bh(&bp->phy_lock);
1731 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1732 __releases(&bp->phy_lock)
1733 __acquires(&bp->phy_lock)
1738 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1739 return (bnx2_setup_remote_phy(bp, port));
1741 if (!(bp->autoneg & AUTONEG_SPEED)) {
1743 int force_link_down = 0;
1745 if (bp->req_line_speed == SPEED_2500) {
1746 if (!bnx2_test_and_enable_2g5(bp))
1747 force_link_down = 1;
1748 } else if (bp->req_line_speed == SPEED_1000) {
1749 if (bnx2_test_and_disable_2g5(bp))
1750 force_link_down = 1;
1752 bnx2_read_phy(bp, bp->mii_adv, &adv);
1753 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1755 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1756 new_bmcr = bmcr & ~BMCR_ANENABLE;
1757 new_bmcr |= BMCR_SPEED1000;
1759 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1760 if (bp->req_line_speed == SPEED_2500)
1761 bnx2_enable_forced_2g5(bp);
1762 else if (bp->req_line_speed == SPEED_1000) {
1763 bnx2_disable_forced_2g5(bp);
1764 new_bmcr &= ~0x2000;
1767 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1768 if (bp->req_line_speed == SPEED_2500)
1769 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1771 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1774 if (bp->req_duplex == DUPLEX_FULL) {
1775 adv |= ADVERTISE_1000XFULL;
1776 new_bmcr |= BMCR_FULLDPLX;
1779 adv |= ADVERTISE_1000XHALF;
1780 new_bmcr &= ~BMCR_FULLDPLX;
1782 if ((new_bmcr != bmcr) || (force_link_down)) {
1783 /* Force a link down visible on the other side */
1785 bnx2_write_phy(bp, bp->mii_adv, adv &
1786 ~(ADVERTISE_1000XFULL |
1787 ADVERTISE_1000XHALF));
1788 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1789 BMCR_ANRESTART | BMCR_ANENABLE);
1792 netif_carrier_off(bp->dev);
1793 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1794 bnx2_report_link(bp);
1796 bnx2_write_phy(bp, bp->mii_adv, adv);
1797 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1799 bnx2_resolve_flow_ctrl(bp);
1800 bnx2_set_mac_link(bp);
1805 bnx2_test_and_enable_2g5(bp);
1807 if (bp->advertising & ADVERTISED_1000baseT_Full)
1808 new_adv |= ADVERTISE_1000XFULL;
1810 new_adv |= bnx2_phy_get_pause_adv(bp);
1812 bnx2_read_phy(bp, bp->mii_adv, &adv);
1813 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1815 bp->serdes_an_pending = 0;
1816 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1817 /* Force a link down visible on the other side */
1819 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1820 spin_unlock_bh(&bp->phy_lock);
1822 spin_lock_bh(&bp->phy_lock);
1825 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1826 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1828 /* Speed up link-up time when the link partner
1829 * does not autonegotiate which is very common
1830 * in blade servers. Some blade servers use
1831 * IPMI for kerboard input and it's important
1832 * to minimize link disruptions. Autoneg. involves
1833 * exchanging base pages plus 3 next pages and
1834 * normally completes in about 120 msec.
1836 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1837 bp->serdes_an_pending = 1;
1838 mod_timer(&bp->timer, jiffies + bp->current_interval);
1840 bnx2_resolve_flow_ctrl(bp);
1841 bnx2_set_mac_link(bp);
1847 #define ETHTOOL_ALL_FIBRE_SPEED \
1848 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1849 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1850 (ADVERTISED_1000baseT_Full)
1852 #define ETHTOOL_ALL_COPPER_SPEED \
1853 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1854 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1855 ADVERTISED_1000baseT_Full)
1857 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1858 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1860 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1863 bnx2_set_default_remote_link(struct bnx2 *bp)
1867 if (bp->phy_port == PORT_TP)
1868 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1870 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1872 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1873 bp->req_line_speed = 0;
1874 bp->autoneg |= AUTONEG_SPEED;
1875 bp->advertising = ADVERTISED_Autoneg;
1876 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1877 bp->advertising |= ADVERTISED_10baseT_Half;
1878 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1879 bp->advertising |= ADVERTISED_10baseT_Full;
1880 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1881 bp->advertising |= ADVERTISED_100baseT_Half;
1882 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1883 bp->advertising |= ADVERTISED_100baseT_Full;
1884 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1885 bp->advertising |= ADVERTISED_1000baseT_Full;
1886 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1887 bp->advertising |= ADVERTISED_2500baseX_Full;
1890 bp->advertising = 0;
1891 bp->req_duplex = DUPLEX_FULL;
1892 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1893 bp->req_line_speed = SPEED_10;
1894 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1895 bp->req_duplex = DUPLEX_HALF;
1897 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1898 bp->req_line_speed = SPEED_100;
1899 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1900 bp->req_duplex = DUPLEX_HALF;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1903 bp->req_line_speed = SPEED_1000;
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1905 bp->req_line_speed = SPEED_2500;
1910 bnx2_set_default_link(struct bnx2 *bp)
1912 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1913 bnx2_set_default_remote_link(bp);
1917 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1918 bp->req_line_speed = 0;
1919 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1922 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1924 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1925 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1926 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1928 bp->req_line_speed = bp->line_speed = SPEED_1000;
1929 bp->req_duplex = DUPLEX_FULL;
1932 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1936 bnx2_send_heart_beat(struct bnx2 *bp)
1941 spin_lock(&bp->indirect_lock);
1942 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1943 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1944 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1946 spin_unlock(&bp->indirect_lock);
1950 bnx2_remote_phy_event(struct bnx2 *bp)
1953 u8 link_up = bp->link_up;
1956 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1958 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1959 bnx2_send_heart_beat(bp);
1961 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1963 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1969 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1970 bp->duplex = DUPLEX_FULL;
1972 case BNX2_LINK_STATUS_10HALF:
1973 bp->duplex = DUPLEX_HALF;
1974 case BNX2_LINK_STATUS_10FULL:
1975 bp->line_speed = SPEED_10;
1977 case BNX2_LINK_STATUS_100HALF:
1978 bp->duplex = DUPLEX_HALF;
1979 case BNX2_LINK_STATUS_100BASE_T4:
1980 case BNX2_LINK_STATUS_100FULL:
1981 bp->line_speed = SPEED_100;
1983 case BNX2_LINK_STATUS_1000HALF:
1984 bp->duplex = DUPLEX_HALF;
1985 case BNX2_LINK_STATUS_1000FULL:
1986 bp->line_speed = SPEED_1000;
1988 case BNX2_LINK_STATUS_2500HALF:
1989 bp->duplex = DUPLEX_HALF;
1990 case BNX2_LINK_STATUS_2500FULL:
1991 bp->line_speed = SPEED_2500;
1999 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2000 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2001 if (bp->duplex == DUPLEX_FULL)
2002 bp->flow_ctrl = bp->req_flow_ctrl;
2004 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2005 bp->flow_ctrl |= FLOW_CTRL_TX;
2006 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2007 bp->flow_ctrl |= FLOW_CTRL_RX;
2010 old_port = bp->phy_port;
2011 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2012 bp->phy_port = PORT_FIBRE;
2014 bp->phy_port = PORT_TP;
2016 if (old_port != bp->phy_port)
2017 bnx2_set_default_link(bp);
2020 if (bp->link_up != link_up)
2021 bnx2_report_link(bp);
2023 bnx2_set_mac_link(bp);
2027 bnx2_set_remote_link(struct bnx2 *bp)
2031 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2033 case BNX2_FW_EVT_CODE_LINK_EVENT:
2034 bnx2_remote_phy_event(bp);
2036 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2038 bnx2_send_heart_beat(bp);
2045 bnx2_setup_copper_phy(struct bnx2 *bp)
2046 __releases(&bp->phy_lock)
2047 __acquires(&bp->phy_lock)
2052 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2054 if (bp->autoneg & AUTONEG_SPEED) {
2055 u32 adv_reg, adv1000_reg;
2056 u32 new_adv_reg = 0;
2057 u32 new_adv1000_reg = 0;
2059 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2060 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2061 ADVERTISE_PAUSE_ASYM);
2063 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2064 adv1000_reg &= PHY_ALL_1000_SPEED;
2066 if (bp->advertising & ADVERTISED_10baseT_Half)
2067 new_adv_reg |= ADVERTISE_10HALF;
2068 if (bp->advertising & ADVERTISED_10baseT_Full)
2069 new_adv_reg |= ADVERTISE_10FULL;
2070 if (bp->advertising & ADVERTISED_100baseT_Half)
2071 new_adv_reg |= ADVERTISE_100HALF;
2072 if (bp->advertising & ADVERTISED_100baseT_Full)
2073 new_adv_reg |= ADVERTISE_100FULL;
2074 if (bp->advertising & ADVERTISED_1000baseT_Full)
2075 new_adv1000_reg |= ADVERTISE_1000FULL;
2077 new_adv_reg |= ADVERTISE_CSMA;
2079 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2081 if ((adv1000_reg != new_adv1000_reg) ||
2082 (adv_reg != new_adv_reg) ||
2083 ((bmcr & BMCR_ANENABLE) == 0)) {
2085 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2086 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2087 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2090 else if (bp->link_up) {
2091 /* Flow ctrl may have changed from auto to forced */
2092 /* or vice-versa. */
2094 bnx2_resolve_flow_ctrl(bp);
2095 bnx2_set_mac_link(bp);
2101 if (bp->req_line_speed == SPEED_100) {
2102 new_bmcr |= BMCR_SPEED100;
2104 if (bp->req_duplex == DUPLEX_FULL) {
2105 new_bmcr |= BMCR_FULLDPLX;
2107 if (new_bmcr != bmcr) {
2110 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2111 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113 if (bmsr & BMSR_LSTATUS) {
2114 /* Force link down */
2115 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2116 spin_unlock_bh(&bp->phy_lock);
2118 spin_lock_bh(&bp->phy_lock);
2120 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2124 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2126 /* Normally, the new speed is setup after the link has
2127 * gone down and up again. In some cases, link will not go
2128 * down so we need to set up the new speed here.
2130 if (bmsr & BMSR_LSTATUS) {
2131 bp->line_speed = bp->req_line_speed;
2132 bp->duplex = bp->req_duplex;
2133 bnx2_resolve_flow_ctrl(bp);
2134 bnx2_set_mac_link(bp);
2137 bnx2_resolve_flow_ctrl(bp);
2138 bnx2_set_mac_link(bp);
2144 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2145 __releases(&bp->phy_lock)
2146 __acquires(&bp->phy_lock)
2148 if (bp->loopback == MAC_LOOPBACK)
2151 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2152 return (bnx2_setup_serdes_phy(bp, port));
2155 return (bnx2_setup_copper_phy(bp));
2160 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2164 bp->mii_bmcr = MII_BMCR + 0x10;
2165 bp->mii_bmsr = MII_BMSR + 0x10;
2166 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2167 bp->mii_adv = MII_ADVERTISE + 0x10;
2168 bp->mii_lpa = MII_LPA + 0x10;
2169 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2171 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2172 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2174 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2178 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2180 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2181 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2182 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2183 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2186 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2187 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2188 val |= BCM5708S_UP1_2G5;
2190 val &= ~BCM5708S_UP1_2G5;
2191 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2193 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2194 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2195 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2196 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2198 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2200 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2201 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2202 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2204 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2210 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2217 bp->mii_up1 = BCM5708S_UP1;
2219 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2220 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2221 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2223 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2224 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2225 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2227 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2228 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2229 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2231 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2232 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2233 val |= BCM5708S_UP1_2G5;
2234 bnx2_write_phy(bp, BCM5708S_UP1, val);
2237 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2238 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2239 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2240 /* increase tx signal amplitude */
2241 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2242 BCM5708S_BLK_ADDR_TX_MISC);
2243 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2244 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2245 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2246 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2249 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2250 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2255 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2256 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2257 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2258 BCM5708S_BLK_ADDR_TX_MISC);
2259 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2260 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2261 BCM5708S_BLK_ADDR_DIG);
2268 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2273 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2275 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2276 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2278 if (bp->dev->mtu > 1500) {
2281 /* Set extended packet length bit */
2282 bnx2_write_phy(bp, 0x18, 0x7);
2283 bnx2_read_phy(bp, 0x18, &val);
2284 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2286 bnx2_write_phy(bp, 0x1c, 0x6c00);
2287 bnx2_read_phy(bp, 0x1c, &val);
2288 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2293 bnx2_write_phy(bp, 0x18, 0x7);
2294 bnx2_read_phy(bp, 0x18, &val);
2295 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2297 bnx2_write_phy(bp, 0x1c, 0x6c00);
2298 bnx2_read_phy(bp, 0x1c, &val);
2299 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2306 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2313 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2314 bnx2_write_phy(bp, 0x18, 0x0c00);
2315 bnx2_write_phy(bp, 0x17, 0x000a);
2316 bnx2_write_phy(bp, 0x15, 0x310b);
2317 bnx2_write_phy(bp, 0x17, 0x201f);
2318 bnx2_write_phy(bp, 0x15, 0x9506);
2319 bnx2_write_phy(bp, 0x17, 0x401f);
2320 bnx2_write_phy(bp, 0x15, 0x14e2);
2321 bnx2_write_phy(bp, 0x18, 0x0400);
2324 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2325 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2326 MII_BNX2_DSP_EXPAND_REG | 0x8);
2327 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2329 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2332 if (bp->dev->mtu > 1500) {
2333 /* Set extended packet length bit */
2334 bnx2_write_phy(bp, 0x18, 0x7);
2335 bnx2_read_phy(bp, 0x18, &val);
2336 bnx2_write_phy(bp, 0x18, val | 0x4000);
2338 bnx2_read_phy(bp, 0x10, &val);
2339 bnx2_write_phy(bp, 0x10, val | 0x1);
2342 bnx2_write_phy(bp, 0x18, 0x7);
2343 bnx2_read_phy(bp, 0x18, &val);
2344 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2346 bnx2_read_phy(bp, 0x10, &val);
2347 bnx2_write_phy(bp, 0x10, val & ~0x1);
2350 /* ethernet@wirespeed */
2351 bnx2_write_phy(bp, 0x18, 0x7007);
2352 bnx2_read_phy(bp, 0x18, &val);
2353 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2359 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2360 __releases(&bp->phy_lock)
2361 __acquires(&bp->phy_lock)
2366 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2367 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2369 bp->mii_bmcr = MII_BMCR;
2370 bp->mii_bmsr = MII_BMSR;
2371 bp->mii_bmsr1 = MII_BMSR;
2372 bp->mii_adv = MII_ADVERTISE;
2373 bp->mii_lpa = MII_LPA;
2375 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2377 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2380 bnx2_read_phy(bp, MII_PHYSID1, &val);
2381 bp->phy_id = val << 16;
2382 bnx2_read_phy(bp, MII_PHYSID2, &val);
2383 bp->phy_id |= val & 0xffff;
2385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2386 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2387 rc = bnx2_init_5706s_phy(bp, reset_phy);
2388 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2389 rc = bnx2_init_5708s_phy(bp, reset_phy);
2390 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2391 rc = bnx2_init_5709s_phy(bp, reset_phy);
2394 rc = bnx2_init_copper_phy(bp, reset_phy);
2399 rc = bnx2_setup_phy(bp, bp->phy_port);
2405 bnx2_set_mac_loopback(struct bnx2 *bp)
2409 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2410 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2411 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2412 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2417 static int bnx2_test_link(struct bnx2 *);
2420 bnx2_set_phy_loopback(struct bnx2 *bp)
2425 spin_lock_bh(&bp->phy_lock);
2426 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2428 spin_unlock_bh(&bp->phy_lock);
2432 for (i = 0; i < 10; i++) {
2433 if (bnx2_test_link(bp) == 0)
2438 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2439 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2440 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2441 BNX2_EMAC_MODE_25G_MODE);
2443 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2444 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2450 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2456 msg_data |= bp->fw_wr_seq;
2458 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2463 /* wait for an acknowledgement. */
2464 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2467 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2469 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2472 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2475 /* If we timed out, inform the firmware that this is the case. */
2476 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2478 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2481 msg_data &= ~BNX2_DRV_MSG_CODE;
2482 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2484 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2489 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2496 bnx2_init_5709_context(struct bnx2 *bp)
2501 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2502 val |= (BCM_PAGE_BITS - 8) << 16;
2503 REG_WR(bp, BNX2_CTX_COMMAND, val);
2504 for (i = 0; i < 10; i++) {
2505 val = REG_RD(bp, BNX2_CTX_COMMAND);
2506 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2510 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2513 for (i = 0; i < bp->ctx_pages; i++) {
2517 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2521 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2522 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2523 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2524 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2525 (u64) bp->ctx_blk_mapping[i] >> 32);
2526 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2527 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2528 for (j = 0; j < 10; j++) {
2530 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2531 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2535 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2544 bnx2_init_context(struct bnx2 *bp)
2550 u32 vcid_addr, pcid_addr, offset;
2555 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2558 vcid_addr = GET_PCID_ADDR(vcid);
2560 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2565 pcid_addr = GET_PCID_ADDR(new_vcid);
2568 vcid_addr = GET_CID_ADDR(vcid);
2569 pcid_addr = vcid_addr;
2572 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2573 vcid_addr += (i << PHY_CTX_SHIFT);
2574 pcid_addr += (i << PHY_CTX_SHIFT);
2576 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2577 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2579 /* Zero out the context. */
2580 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2581 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2587 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2593 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2594 if (good_mbuf == NULL) {
2595 printk(KERN_ERR PFX "Failed to allocate memory in "
2596 "bnx2_alloc_bad_rbuf\n");
2600 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2601 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2605 /* Allocate a bunch of mbufs and save the good ones in an array. */
2606 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2607 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2608 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2609 BNX2_RBUF_COMMAND_ALLOC_REQ);
2611 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2613 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2615 /* The addresses with Bit 9 set are bad memory blocks. */
2616 if (!(val & (1 << 9))) {
2617 good_mbuf[good_mbuf_cnt] = (u16) val;
2621 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2624 /* Free the good ones back to the mbuf pool thus discarding
2625 * all the bad ones. */
2626 while (good_mbuf_cnt) {
2629 val = good_mbuf[good_mbuf_cnt];
2630 val = (val << 9) | val | 1;
2632 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2639 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2643 val = (mac_addr[0] << 8) | mac_addr[1];
2645 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2647 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2648 (mac_addr[4] << 8) | mac_addr[5];
2650 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2654 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2657 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2658 struct rx_bd *rxbd =
2659 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2660 struct page *page = alloc_page(GFP_ATOMIC);
2664 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2665 PCI_DMA_FROMDEVICE);
2666 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2672 pci_unmap_addr_set(rx_pg, mapping, mapping);
2673 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2674 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2679 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2681 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2682 struct page *page = rx_pg->page;
2687 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2688 PCI_DMA_FROMDEVICE);
2695 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2697 struct sk_buff *skb;
2698 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2700 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2701 unsigned long align;
2703 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2708 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2709 skb_reserve(skb, BNX2_RX_ALIGN - align);
2711 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2712 PCI_DMA_FROMDEVICE);
2713 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2719 pci_unmap_addr_set(rx_buf, mapping, mapping);
2721 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2722 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2724 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2730 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2732 struct status_block *sblk = bnapi->status_blk.msi;
2733 u32 new_link_state, old_link_state;
2736 new_link_state = sblk->status_attn_bits & event;
2737 old_link_state = sblk->status_attn_bits_ack & event;
2738 if (new_link_state != old_link_state) {
2740 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2742 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2750 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2752 spin_lock(&bp->phy_lock);
2754 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2756 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2757 bnx2_set_remote_link(bp);
2759 spin_unlock(&bp->phy_lock);
2764 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2768 /* Tell compiler that status block fields can change. */
2770 cons = *bnapi->hw_tx_cons_ptr;
2772 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2778 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2780 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2781 u16 hw_cons, sw_cons, sw_ring_cons;
2782 int tx_pkt = 0, index;
2783 struct netdev_queue *txq;
2785 index = (bnapi - bp->bnx2_napi);
2786 txq = netdev_get_tx_queue(bp->dev, index);
2788 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2789 sw_cons = txr->tx_cons;
2791 while (sw_cons != hw_cons) {
2792 struct sw_tx_bd *tx_buf;
2793 struct sk_buff *skb;
2796 sw_ring_cons = TX_RING_IDX(sw_cons);
2798 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2801 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2802 prefetch(&skb->end);
2804 /* partial BD completions possible with TSO packets */
2805 if (tx_buf->is_gso) {
2806 u16 last_idx, last_ring_idx;
2808 last_idx = sw_cons + tx_buf->nr_frags + 1;
2809 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2810 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2813 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2818 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2819 skb_headlen(skb), PCI_DMA_TODEVICE);
2822 last = tx_buf->nr_frags;
2824 for (i = 0; i < last; i++) {
2825 sw_cons = NEXT_TX_BD(sw_cons);
2827 pci_unmap_page(bp->pdev,
2829 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2831 skb_shinfo(skb)->frags[i].size,
2835 sw_cons = NEXT_TX_BD(sw_cons);
2839 if (tx_pkt == budget)
2842 if (hw_cons == sw_cons)
2843 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2846 txr->hw_tx_cons = hw_cons;
2847 txr->tx_cons = sw_cons;
2849 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2850 * before checking for netif_tx_queue_stopped(). Without the
2851 * memory barrier, there is a small possibility that bnx2_start_xmit()
2852 * will miss it and cause the queue to be stopped forever.
2856 if (unlikely(netif_tx_queue_stopped(txq)) &&
2857 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2858 __netif_tx_lock(txq, smp_processor_id());
2859 if ((netif_tx_queue_stopped(txq)) &&
2860 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2861 netif_tx_wake_queue(txq);
2862 __netif_tx_unlock(txq);
2869 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2870 struct sk_buff *skb, int count)
2872 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2873 struct rx_bd *cons_bd, *prod_bd;
2876 u16 cons = rxr->rx_pg_cons;
2878 cons_rx_pg = &rxr->rx_pg_ring[cons];
2880 /* The caller was unable to allocate a new page to replace the
2881 * last one in the frags array, so we need to recycle that page
2882 * and then free the skb.
2886 struct skb_shared_info *shinfo;
2888 shinfo = skb_shinfo(skb);
2890 page = shinfo->frags[shinfo->nr_frags].page;
2891 shinfo->frags[shinfo->nr_frags].page = NULL;
2893 cons_rx_pg->page = page;
2897 hw_prod = rxr->rx_pg_prod;
2899 for (i = 0; i < count; i++) {
2900 prod = RX_PG_RING_IDX(hw_prod);
2902 prod_rx_pg = &rxr->rx_pg_ring[prod];
2903 cons_rx_pg = &rxr->rx_pg_ring[cons];
2904 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2905 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2908 prod_rx_pg->page = cons_rx_pg->page;
2909 cons_rx_pg->page = NULL;
2910 pci_unmap_addr_set(prod_rx_pg, mapping,
2911 pci_unmap_addr(cons_rx_pg, mapping));
2913 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2914 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2917 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2918 hw_prod = NEXT_RX_BD(hw_prod);
2920 rxr->rx_pg_prod = hw_prod;
2921 rxr->rx_pg_cons = cons;
2925 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2926 struct sk_buff *skb, u16 cons, u16 prod)
2928 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2929 struct rx_bd *cons_bd, *prod_bd;
2931 cons_rx_buf = &rxr->rx_buf_ring[cons];
2932 prod_rx_buf = &rxr->rx_buf_ring[prod];
2934 pci_dma_sync_single_for_device(bp->pdev,
2935 pci_unmap_addr(cons_rx_buf, mapping),
2936 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2938 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2940 prod_rx_buf->skb = skb;
2945 pci_unmap_addr_set(prod_rx_buf, mapping,
2946 pci_unmap_addr(cons_rx_buf, mapping));
2948 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2949 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2950 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2951 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2955 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2956 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2960 u16 prod = ring_idx & 0xffff;
2962 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2963 if (unlikely(err)) {
2964 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2966 unsigned int raw_len = len + 4;
2967 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2969 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2974 skb_reserve(skb, BNX2_RX_OFFSET);
2975 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2976 PCI_DMA_FROMDEVICE);
2982 unsigned int i, frag_len, frag_size, pages;
2983 struct sw_pg *rx_pg;
2984 u16 pg_cons = rxr->rx_pg_cons;
2985 u16 pg_prod = rxr->rx_pg_prod;
2987 frag_size = len + 4 - hdr_len;
2988 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2989 skb_put(skb, hdr_len);
2991 for (i = 0; i < pages; i++) {
2992 dma_addr_t mapping_old;
2994 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2995 if (unlikely(frag_len <= 4)) {
2996 unsigned int tail = 4 - frag_len;
2998 rxr->rx_pg_cons = pg_cons;
2999 rxr->rx_pg_prod = pg_prod;
3000 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3007 &skb_shinfo(skb)->frags[i - 1];
3009 skb->data_len -= tail;
3010 skb->truesize -= tail;
3014 rx_pg = &rxr->rx_pg_ring[pg_cons];
3016 /* Don't unmap yet. If we're unable to allocate a new
3017 * page, we need to recycle the page and the DMA addr.
3019 mapping_old = pci_unmap_addr(rx_pg, mapping);
3023 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3026 err = bnx2_alloc_rx_page(bp, rxr,
3027 RX_PG_RING_IDX(pg_prod));
3028 if (unlikely(err)) {
3029 rxr->rx_pg_cons = pg_cons;
3030 rxr->rx_pg_prod = pg_prod;
3031 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3036 pci_unmap_page(bp->pdev, mapping_old,
3037 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3039 frag_size -= frag_len;
3040 skb->data_len += frag_len;
3041 skb->truesize += frag_len;
3042 skb->len += frag_len;
3044 pg_prod = NEXT_RX_BD(pg_prod);
3045 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3047 rxr->rx_pg_prod = pg_prod;
3048 rxr->rx_pg_cons = pg_cons;
3054 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3058 /* Tell compiler that status block fields can change. */
3060 cons = *bnapi->hw_rx_cons_ptr;
3062 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3068 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3070 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3071 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3072 struct l2_fhdr *rx_hdr;
3073 int rx_pkt = 0, pg_ring_used = 0;
3075 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3076 sw_cons = rxr->rx_cons;
3077 sw_prod = rxr->rx_prod;
3079 /* Memory barrier necessary as speculative reads of the rx
3080 * buffer can be ahead of the index in the status block
3083 while (sw_cons != hw_cons) {
3084 unsigned int len, hdr_len;
3086 struct sw_bd *rx_buf;
3087 struct sk_buff *skb;
3088 dma_addr_t dma_addr;
3090 int hw_vlan __maybe_unused = 0;
3092 sw_ring_cons = RX_RING_IDX(sw_cons);
3093 sw_ring_prod = RX_RING_IDX(sw_prod);
3095 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3100 dma_addr = pci_unmap_addr(rx_buf, mapping);
3102 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3103 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3104 PCI_DMA_FROMDEVICE);
3106 rx_hdr = (struct l2_fhdr *) skb->data;
3107 len = rx_hdr->l2_fhdr_pkt_len;
3108 status = rx_hdr->l2_fhdr_status;
3111 if (status & L2_FHDR_STATUS_SPLIT) {
3112 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3114 } else if (len > bp->rx_jumbo_thresh) {
3115 hdr_len = bp->rx_jumbo_thresh;
3119 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3120 L2_FHDR_ERRORS_PHY_DECODE |
3121 L2_FHDR_ERRORS_ALIGNMENT |
3122 L2_FHDR_ERRORS_TOO_SHORT |
3123 L2_FHDR_ERRORS_GIANT_FRAME))) {
3125 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3130 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3132 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3139 if (len <= bp->rx_copy_thresh) {
3140 struct sk_buff *new_skb;
3142 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3143 if (new_skb == NULL) {
3144 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3150 skb_copy_from_linear_data_offset(skb,
3152 new_skb->data, len + 6);
3153 skb_reserve(new_skb, 6);
3154 skb_put(new_skb, len);
3156 bnx2_reuse_rx_skb(bp, rxr, skb,
3157 sw_ring_cons, sw_ring_prod);
3160 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3161 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3164 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3165 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3166 vtag = rx_hdr->l2_fhdr_vlan_tag;
3173 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3176 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3177 ve->h_vlan_proto = htons(ETH_P_8021Q);
3178 ve->h_vlan_TCI = htons(vtag);
3183 skb->protocol = eth_type_trans(skb, bp->dev);
3185 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3186 (ntohs(skb->protocol) != 0x8100)) {
3193 skb->ip_summed = CHECKSUM_NONE;
3195 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3196 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3198 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3199 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3200 skb->ip_summed = CHECKSUM_UNNECESSARY;
3203 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3207 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3210 netif_receive_skb(skb);
3215 sw_cons = NEXT_RX_BD(sw_cons);
3216 sw_prod = NEXT_RX_BD(sw_prod);
3218 if ((rx_pkt == budget))
3221 /* Refresh hw_cons to see if there is new work */
3222 if (sw_cons == hw_cons) {
3223 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3227 rxr->rx_cons = sw_cons;
3228 rxr->rx_prod = sw_prod;
3231 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3233 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3235 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3243 /* MSI ISR - The only difference between this and the INTx ISR
3244 * is that the MSI interrupt is always serviced.
3247 bnx2_msi(int irq, void *dev_instance)
3249 struct bnx2_napi *bnapi = dev_instance;
3250 struct bnx2 *bp = bnapi->bp;
3252 prefetch(bnapi->status_blk.msi);
3253 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3254 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3255 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3257 /* Return here if interrupt is disabled. */
3258 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3261 napi_schedule(&bnapi->napi);
3267 bnx2_msi_1shot(int irq, void *dev_instance)
3269 struct bnx2_napi *bnapi = dev_instance;
3270 struct bnx2 *bp = bnapi->bp;
3272 prefetch(bnapi->status_blk.msi);
3274 /* Return here if interrupt is disabled. */
3275 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3278 napi_schedule(&bnapi->napi);
3284 bnx2_interrupt(int irq, void *dev_instance)
3286 struct bnx2_napi *bnapi = dev_instance;
3287 struct bnx2 *bp = bnapi->bp;
3288 struct status_block *sblk = bnapi->status_blk.msi;
3290 /* When using INTx, it is possible for the interrupt to arrive
3291 * at the CPU before the status block posted prior to the
3292 * interrupt. Reading a register will flush the status block.
3293 * When using MSI, the MSI message will always complete after
3294 * the status block write.
3296 if ((sblk->status_idx == bnapi->last_status_idx) &&
3297 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3298 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3301 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3302 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3303 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3305 /* Read back to deassert IRQ immediately to avoid too many
3306 * spurious interrupts.
3308 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3310 /* Return here if interrupt is shared and is disabled. */
3311 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3314 if (napi_schedule_prep(&bnapi->napi)) {
3315 bnapi->last_status_idx = sblk->status_idx;
3316 __napi_schedule(&bnapi->napi);
3323 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3325 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3326 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3328 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3329 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3334 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3335 STATUS_ATTN_BITS_TIMER_ABORT)
3338 bnx2_has_work(struct bnx2_napi *bnapi)
3340 struct status_block *sblk = bnapi->status_blk.msi;
3342 if (bnx2_has_fast_work(bnapi))
3346 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3350 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3351 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3358 bnx2_chk_missed_msi(struct bnx2 *bp)
3360 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3363 if (bnx2_has_work(bnapi)) {
3364 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3365 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3368 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3369 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3370 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3371 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3372 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3376 bp->idle_chk_status_idx = bnapi->last_status_idx;
3380 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3382 struct cnic_ops *c_ops;
3384 if (!bnapi->cnic_present)
3388 c_ops = rcu_dereference(bp->cnic_ops);
3390 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3391 bnapi->status_blk.msi);
3396 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3398 struct status_block *sblk = bnapi->status_blk.msi;
3399 u32 status_attn_bits = sblk->status_attn_bits;
3400 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3402 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3403 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3405 bnx2_phy_int(bp, bnapi);
3407 /* This is needed to take care of transient status
3408 * during link changes.
3410 REG_WR(bp, BNX2_HC_COMMAND,
3411 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3412 REG_RD(bp, BNX2_HC_COMMAND);
3416 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3417 int work_done, int budget)
3419 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3420 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3422 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3423 bnx2_tx_int(bp, bnapi, 0);
3425 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3426 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3431 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3433 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3434 struct bnx2 *bp = bnapi->bp;
3436 struct status_block_msix *sblk = bnapi->status_blk.msix;
3439 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3440 if (unlikely(work_done >= budget))
3443 bnapi->last_status_idx = sblk->status_idx;
3444 /* status idx must be read before checking for more work. */
3446 if (likely(!bnx2_has_fast_work(bnapi))) {
3448 napi_complete(napi);
3449 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3450 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3451 bnapi->last_status_idx);
3458 static int bnx2_poll(struct napi_struct *napi, int budget)
3460 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3461 struct bnx2 *bp = bnapi->bp;
3463 struct status_block *sblk = bnapi->status_blk.msi;
3466 bnx2_poll_link(bp, bnapi);
3468 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3471 bnx2_poll_cnic(bp, bnapi);
3474 /* bnapi->last_status_idx is used below to tell the hw how
3475 * much work has been processed, so we must read it before
3476 * checking for more work.
3478 bnapi->last_status_idx = sblk->status_idx;
3480 if (unlikely(work_done >= budget))
3484 if (likely(!bnx2_has_work(bnapi))) {
3485 napi_complete(napi);
3486 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3487 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3488 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3489 bnapi->last_status_idx);
3492 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3493 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3494 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3495 bnapi->last_status_idx);
3497 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3498 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3499 bnapi->last_status_idx);
3507 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3508 * from set_multicast.
3511 bnx2_set_rx_mode(struct net_device *dev)
3513 struct bnx2 *bp = netdev_priv(dev);
3514 u32 rx_mode, sort_mode;
3515 struct netdev_hw_addr *ha;
3518 if (!netif_running(dev))
3521 spin_lock_bh(&bp->phy_lock);
3523 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3524 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3525 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3527 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3528 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3530 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3531 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3533 if (dev->flags & IFF_PROMISC) {
3534 /* Promiscuous mode. */
3535 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3536 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3537 BNX2_RPM_SORT_USER0_PROM_VLAN;
3539 else if (dev->flags & IFF_ALLMULTI) {
3540 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3541 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3544 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3547 /* Accept one or more multicast(s). */
3548 struct dev_mc_list *mclist;
3549 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3554 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3556 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3557 i++, mclist = mclist->next) {
3559 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3561 regidx = (bit & 0xe0) >> 5;
3563 mc_filter[regidx] |= (1 << bit);
3566 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3567 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3571 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3574 if (dev->uc.count > BNX2_MAX_UNICAST_ADDRESSES) {
3575 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3576 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3577 BNX2_RPM_SORT_USER0_PROM_VLAN;
3578 } else if (!(dev->flags & IFF_PROMISC)) {
3579 /* Add all entries into to the match filter list */
3581 list_for_each_entry(ha, &dev->uc.list, list) {
3582 bnx2_set_mac_addr(bp, ha->addr,
3583 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3585 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3591 if (rx_mode != bp->rx_mode) {
3592 bp->rx_mode = rx_mode;
3593 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3596 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3597 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3598 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3600 spin_unlock_bh(&bp->phy_lock);
3603 static int __devinit
3604 check_fw_section(const struct firmware *fw,
3605 const struct bnx2_fw_file_section *section,
3606 u32 alignment, bool non_empty)
3608 u32 offset = be32_to_cpu(section->offset);
3609 u32 len = be32_to_cpu(section->len);
3611 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3613 if ((non_empty && len == 0) || len > fw->size - offset ||
3614 len & (alignment - 1))
3619 static int __devinit
3620 check_mips_fw_entry(const struct firmware *fw,
3621 const struct bnx2_mips_fw_file_entry *entry)
3623 if (check_fw_section(fw, &entry->text, 4, true) ||
3624 check_fw_section(fw, &entry->data, 4, false) ||
3625 check_fw_section(fw, &entry->rodata, 4, false))
3630 static int __devinit
3631 bnx2_request_firmware(struct bnx2 *bp)
3633 const char *mips_fw_file, *rv2p_fw_file;
3634 const struct bnx2_mips_fw_file *mips_fw;
3635 const struct bnx2_rv2p_fw_file *rv2p_fw;
3638 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3639 mips_fw_file = FW_MIPS_FILE_09;
3640 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3641 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3642 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3644 rv2p_fw_file = FW_RV2P_FILE_09;
3646 mips_fw_file = FW_MIPS_FILE_06;
3647 rv2p_fw_file = FW_RV2P_FILE_06;
3650 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3652 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3657 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3659 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3663 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3664 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3665 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3666 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3667 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3668 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3669 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3670 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3671 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3675 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3676 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3677 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3678 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3687 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3690 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3691 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3692 rv2p_code |= RV2P_BD_PAGE_SIZE;
3699 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3700 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3702 u32 rv2p_code_len, file_offset;
3707 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3708 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3710 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3712 if (rv2p_proc == RV2P_PROC1) {
3713 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3714 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3716 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3717 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3720 for (i = 0; i < rv2p_code_len; i += 8) {
3721 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3723 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3726 val = (i / 8) | cmd;
3727 REG_WR(bp, addr, val);
3730 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3731 for (i = 0; i < 8; i++) {
3734 loc = be32_to_cpu(fw_entry->fixup[i]);
3735 if (loc && ((loc * 4) < rv2p_code_len)) {
3736 code = be32_to_cpu(*(rv2p_code + loc - 1));
3737 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3738 code = be32_to_cpu(*(rv2p_code + loc));
3739 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3740 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3742 val = (loc / 2) | cmd;
3743 REG_WR(bp, addr, val);
3747 /* Reset the processor, un-stall is done later. */
3748 if (rv2p_proc == RV2P_PROC1) {
3749 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3752 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3759 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3760 const struct bnx2_mips_fw_file_entry *fw_entry)
3762 u32 addr, len, file_offset;
3768 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3769 val |= cpu_reg->mode_value_halt;
3770 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3771 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3773 /* Load the Text area. */
3774 addr = be32_to_cpu(fw_entry->text.addr);
3775 len = be32_to_cpu(fw_entry->text.len);
3776 file_offset = be32_to_cpu(fw_entry->text.offset);
3777 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3779 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3783 for (j = 0; j < (len / 4); j++, offset += 4)
3784 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3787 /* Load the Data area. */
3788 addr = be32_to_cpu(fw_entry->data.addr);
3789 len = be32_to_cpu(fw_entry->data.len);
3790 file_offset = be32_to_cpu(fw_entry->data.offset);
3791 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3793 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3797 for (j = 0; j < (len / 4); j++, offset += 4)
3798 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3801 /* Load the Read-Only area. */
3802 addr = be32_to_cpu(fw_entry->rodata.addr);
3803 len = be32_to_cpu(fw_entry->rodata.len);
3804 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3805 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3807 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3811 for (j = 0; j < (len / 4); j++, offset += 4)
3812 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3815 /* Clear the pre-fetch instruction. */
3816 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3818 val = be32_to_cpu(fw_entry->start_addr);
3819 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3821 /* Start the CPU. */
3822 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3823 val &= ~cpu_reg->mode_value_halt;
3824 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3825 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3831 bnx2_init_cpus(struct bnx2 *bp)
3833 const struct bnx2_mips_fw_file *mips_fw =
3834 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3835 const struct bnx2_rv2p_fw_file *rv2p_fw =
3836 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3839 /* Initialize the RV2P processor. */
3840 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3841 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3843 /* Initialize the RX Processor. */
3844 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3848 /* Initialize the TX Processor. */
3849 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3853 /* Initialize the TX Patch-up Processor. */
3854 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3858 /* Initialize the Completion Processor. */
3859 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3863 /* Initialize the Command Processor. */
3864 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3871 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3875 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3881 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3882 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3883 PCI_PM_CTRL_PME_STATUS);
3885 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3886 /* delay required during transition out of D3hot */
3889 val = REG_RD(bp, BNX2_EMAC_MODE);
3890 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3891 val &= ~BNX2_EMAC_MODE_MPKT;
3892 REG_WR(bp, BNX2_EMAC_MODE, val);
3894 val = REG_RD(bp, BNX2_RPM_CONFIG);
3895 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3896 REG_WR(bp, BNX2_RPM_CONFIG, val);
3907 autoneg = bp->autoneg;
3908 advertising = bp->advertising;
3910 if (bp->phy_port == PORT_TP) {
3911 bp->autoneg = AUTONEG_SPEED;
3912 bp->advertising = ADVERTISED_10baseT_Half |
3913 ADVERTISED_10baseT_Full |
3914 ADVERTISED_100baseT_Half |
3915 ADVERTISED_100baseT_Full |
3919 spin_lock_bh(&bp->phy_lock);
3920 bnx2_setup_phy(bp, bp->phy_port);
3921 spin_unlock_bh(&bp->phy_lock);
3923 bp->autoneg = autoneg;
3924 bp->advertising = advertising;
3926 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3928 val = REG_RD(bp, BNX2_EMAC_MODE);
3930 /* Enable port mode. */
3931 val &= ~BNX2_EMAC_MODE_PORT;
3932 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3933 BNX2_EMAC_MODE_ACPI_RCVD |
3934 BNX2_EMAC_MODE_MPKT;
3935 if (bp->phy_port == PORT_TP)
3936 val |= BNX2_EMAC_MODE_PORT_MII;
3938 val |= BNX2_EMAC_MODE_PORT_GMII;
3939 if (bp->line_speed == SPEED_2500)
3940 val |= BNX2_EMAC_MODE_25G_MODE;
3943 REG_WR(bp, BNX2_EMAC_MODE, val);
3945 /* receive all multicast */
3946 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3947 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3950 REG_WR(bp, BNX2_EMAC_RX_MODE,
3951 BNX2_EMAC_RX_MODE_SORT_MODE);
3953 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3954 BNX2_RPM_SORT_USER0_MC_EN;
3955 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3956 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3957 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3958 BNX2_RPM_SORT_USER0_ENA);
3960 /* Need to enable EMAC and RPM for WOL. */
3961 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3962 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3963 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3964 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3966 val = REG_RD(bp, BNX2_RPM_CONFIG);
3967 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3968 REG_WR(bp, BNX2_RPM_CONFIG, val);
3970 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3973 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3976 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3977 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3980 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3981 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3982 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3991 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3993 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3996 /* No more memory access after this point until
3997 * device is brought back to D0.
4009 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4014 /* Request access to the flash interface. */
4015 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4016 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4017 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4018 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4024 if (j >= NVRAM_TIMEOUT_COUNT)
4031 bnx2_release_nvram_lock(struct bnx2 *bp)
4036 /* Relinquish nvram interface. */
4037 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4039 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4040 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4041 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4047 if (j >= NVRAM_TIMEOUT_COUNT)
4055 bnx2_enable_nvram_write(struct bnx2 *bp)
4059 val = REG_RD(bp, BNX2_MISC_CFG);
4060 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4062 if (bp->flash_info->flags & BNX2_NV_WREN) {
4065 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4066 REG_WR(bp, BNX2_NVM_COMMAND,
4067 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4069 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4072 val = REG_RD(bp, BNX2_NVM_COMMAND);
4073 if (val & BNX2_NVM_COMMAND_DONE)
4077 if (j >= NVRAM_TIMEOUT_COUNT)
4084 bnx2_disable_nvram_write(struct bnx2 *bp)
4088 val = REG_RD(bp, BNX2_MISC_CFG);
4089 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4094 bnx2_enable_nvram_access(struct bnx2 *bp)
4098 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4099 /* Enable both bits, even on read. */
4100 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4101 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4105 bnx2_disable_nvram_access(struct bnx2 *bp)
4109 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4110 /* Disable both bits, even after read. */
4111 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4112 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4113 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4117 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4122 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4123 /* Buffered flash, no erase needed */
4126 /* Build an erase command */
4127 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4128 BNX2_NVM_COMMAND_DOIT;
4130 /* Need to clear DONE bit separately. */
4131 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4133 /* Address of the NVRAM to read from. */
4134 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4136 /* Issue an erase command. */
4137 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4139 /* Wait for completion. */
4140 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4145 val = REG_RD(bp, BNX2_NVM_COMMAND);
4146 if (val & BNX2_NVM_COMMAND_DONE)
4150 if (j >= NVRAM_TIMEOUT_COUNT)
4157 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4162 /* Build the command word. */
4163 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4165 /* Calculate an offset of a buffered flash, not needed for 5709. */
4166 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4167 offset = ((offset / bp->flash_info->page_size) <<
4168 bp->flash_info->page_bits) +
4169 (offset % bp->flash_info->page_size);
4172 /* Need to clear DONE bit separately. */
4173 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4175 /* Address of the NVRAM to read from. */
4176 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4178 /* Issue a read command. */
4179 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4181 /* Wait for completion. */
4182 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4187 val = REG_RD(bp, BNX2_NVM_COMMAND);
4188 if (val & BNX2_NVM_COMMAND_DONE) {
4189 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4190 memcpy(ret_val, &v, 4);
4194 if (j >= NVRAM_TIMEOUT_COUNT)
4202 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4208 /* Build the command word. */
4209 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4211 /* Calculate an offset of a buffered flash, not needed for 5709. */
4212 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4213 offset = ((offset / bp->flash_info->page_size) <<
4214 bp->flash_info->page_bits) +
4215 (offset % bp->flash_info->page_size);
4218 /* Need to clear DONE bit separately. */
4219 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4221 memcpy(&val32, val, 4);
4223 /* Write the data. */
4224 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4226 /* Address of the NVRAM to write to. */
4227 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4229 /* Issue the write command. */
4230 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4232 /* Wait for completion. */
4233 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4236 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4239 if (j >= NVRAM_TIMEOUT_COUNT)
4246 bnx2_init_nvram(struct bnx2 *bp)
4249 int j, entry_count, rc = 0;
4250 const struct flash_spec *flash;
4252 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4253 bp->flash_info = &flash_5709;
4254 goto get_flash_size;
4257 /* Determine the selected interface. */
4258 val = REG_RD(bp, BNX2_NVM_CFG1);
4260 entry_count = ARRAY_SIZE(flash_table);
4262 if (val & 0x40000000) {
4264 /* Flash interface has been reconfigured */
4265 for (j = 0, flash = &flash_table[0]; j < entry_count;
4267 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4268 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4269 bp->flash_info = flash;
4276 /* Not yet been reconfigured */
4278 if (val & (1 << 23))
4279 mask = FLASH_BACKUP_STRAP_MASK;
4281 mask = FLASH_STRAP_MASK;
4283 for (j = 0, flash = &flash_table[0]; j < entry_count;
4286 if ((val & mask) == (flash->strapping & mask)) {
4287 bp->flash_info = flash;
4289 /* Request access to the flash interface. */
4290 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4293 /* Enable access to flash interface */
4294 bnx2_enable_nvram_access(bp);
4296 /* Reconfigure the flash interface */
4297 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4298 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4299 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4300 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4302 /* Disable access to flash interface */
4303 bnx2_disable_nvram_access(bp);
4304 bnx2_release_nvram_lock(bp);
4309 } /* if (val & 0x40000000) */
4311 if (j == entry_count) {
4312 bp->flash_info = NULL;
4313 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4318 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4319 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4321 bp->flash_size = val;
4323 bp->flash_size = bp->flash_info->total_size;
4329 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4333 u32 cmd_flags, offset32, len32, extra;
4338 /* Request access to the flash interface. */
4339 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4342 /* Enable access to flash interface */
4343 bnx2_enable_nvram_access(bp);
4356 pre_len = 4 - (offset & 3);
4358 if (pre_len >= len32) {
4360 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4361 BNX2_NVM_COMMAND_LAST;
4364 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4367 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4372 memcpy(ret_buf, buf + (offset & 3), pre_len);
4379 extra = 4 - (len32 & 3);
4380 len32 = (len32 + 4) & ~3;
4387 cmd_flags = BNX2_NVM_COMMAND_LAST;
4389 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4390 BNX2_NVM_COMMAND_LAST;
4392 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4394 memcpy(ret_buf, buf, 4 - extra);
4396 else if (len32 > 0) {
4399 /* Read the first word. */
4403 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4405 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4407 /* Advance to the next dword. */
4412 while (len32 > 4 && rc == 0) {
4413 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4415 /* Advance to the next dword. */
4424 cmd_flags = BNX2_NVM_COMMAND_LAST;
4425 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4427 memcpy(ret_buf, buf, 4 - extra);
4430 /* Disable access to flash interface */
4431 bnx2_disable_nvram_access(bp);
4433 bnx2_release_nvram_lock(bp);
4439 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4442 u32 written, offset32, len32;
4443 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4445 int align_start, align_end;
4450 align_start = align_end = 0;
4452 if ((align_start = (offset32 & 3))) {
4454 len32 += align_start;
4457 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4462 align_end = 4 - (len32 & 3);
4464 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4468 if (align_start || align_end) {
4469 align_buf = kmalloc(len32, GFP_KERNEL);
4470 if (align_buf == NULL)
4473 memcpy(align_buf, start, 4);
4476 memcpy(align_buf + len32 - 4, end, 4);
4478 memcpy(align_buf + align_start, data_buf, buf_size);
4482 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4483 flash_buffer = kmalloc(264, GFP_KERNEL);
4484 if (flash_buffer == NULL) {
4486 goto nvram_write_end;
4491 while ((written < len32) && (rc == 0)) {
4492 u32 page_start, page_end, data_start, data_end;
4493 u32 addr, cmd_flags;
4496 /* Find the page_start addr */
4497 page_start = offset32 + written;
4498 page_start -= (page_start % bp->flash_info->page_size);
4499 /* Find the page_end addr */
4500 page_end = page_start + bp->flash_info->page_size;
4501 /* Find the data_start addr */
4502 data_start = (written == 0) ? offset32 : page_start;
4503 /* Find the data_end addr */
4504 data_end = (page_end > offset32 + len32) ?
4505 (offset32 + len32) : page_end;
4507 /* Request access to the flash interface. */
4508 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4509 goto nvram_write_end;
4511 /* Enable access to flash interface */
4512 bnx2_enable_nvram_access(bp);
4514 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4515 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4518 /* Read the whole page into the buffer
4519 * (non-buffer flash only) */
4520 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4521 if (j == (bp->flash_info->page_size - 4)) {
4522 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4524 rc = bnx2_nvram_read_dword(bp,
4530 goto nvram_write_end;
4536 /* Enable writes to flash interface (unlock write-protect) */
4537 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4538 goto nvram_write_end;
4540 /* Loop to write back the buffer data from page_start to
4543 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4544 /* Erase the page */
4545 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4546 goto nvram_write_end;
4548 /* Re-enable the write again for the actual write */
4549 bnx2_enable_nvram_write(bp);
4551 for (addr = page_start; addr < data_start;
4552 addr += 4, i += 4) {
4554 rc = bnx2_nvram_write_dword(bp, addr,
4555 &flash_buffer[i], cmd_flags);
4558 goto nvram_write_end;
4564 /* Loop to write the new data from data_start to data_end */
4565 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4566 if ((addr == page_end - 4) ||
4567 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4568 (addr == data_end - 4))) {
4570 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4572 rc = bnx2_nvram_write_dword(bp, addr, buf,
4576 goto nvram_write_end;
4582 /* Loop to write back the buffer data from data_end
4584 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4585 for (addr = data_end; addr < page_end;
4586 addr += 4, i += 4) {
4588 if (addr == page_end-4) {
4589 cmd_flags = BNX2_NVM_COMMAND_LAST;
4591 rc = bnx2_nvram_write_dword(bp, addr,
4592 &flash_buffer[i], cmd_flags);
4595 goto nvram_write_end;
4601 /* Disable writes to flash interface (lock write-protect) */
4602 bnx2_disable_nvram_write(bp);
4604 /* Disable access to flash interface */
4605 bnx2_disable_nvram_access(bp);
4606 bnx2_release_nvram_lock(bp);
4608 /* Increment written */
4609 written += data_end - data_start;
4613 kfree(flash_buffer);
4619 bnx2_init_fw_cap(struct bnx2 *bp)
4623 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4624 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4626 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4627 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4629 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4630 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4633 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4634 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4635 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4638 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4639 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4642 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4644 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4645 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4646 bp->phy_port = PORT_FIBRE;
4648 bp->phy_port = PORT_TP;
4650 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4651 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4654 if (netif_running(bp->dev) && sig)
4655 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4659 bnx2_setup_msix_tbl(struct bnx2 *bp)
4661 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4663 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4664 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4668 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4674 /* Wait for the current PCI transaction to complete before
4675 * issuing a reset. */
4676 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4677 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4678 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4679 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4680 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4681 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4684 /* Wait for the firmware to tell us it is ok to issue a reset. */
4685 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4687 /* Deposit a driver reset signature so the firmware knows that
4688 * this is a soft reset. */
4689 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4690 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4692 /* Do a dummy read to force the chip to complete all current transaction
4693 * before we issue a reset. */
4694 val = REG_RD(bp, BNX2_MISC_ID);
4696 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4697 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4698 REG_RD(bp, BNX2_MISC_COMMAND);
4701 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4702 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4704 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4707 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4708 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4709 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4712 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4714 /* Reading back any register after chip reset will hang the
4715 * bus on 5706 A0 and A1. The msleep below provides plenty
4716 * of margin for write posting.
4718 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4719 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4722 /* Reset takes approximate 30 usec */
4723 for (i = 0; i < 10; i++) {
4724 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4725 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4726 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4731 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4732 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4733 printk(KERN_ERR PFX "Chip reset did not complete\n");
4738 /* Make sure byte swapping is properly configured. */
4739 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4740 if (val != 0x01020304) {
4741 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4745 /* Wait for the firmware to finish its initialization. */
4746 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4750 spin_lock_bh(&bp->phy_lock);
4751 old_port = bp->phy_port;
4752 bnx2_init_fw_cap(bp);
4753 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4754 old_port != bp->phy_port)
4755 bnx2_set_default_remote_link(bp);
4756 spin_unlock_bh(&bp->phy_lock);
4758 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4759 /* Adjust the voltage regular to two steps lower. The default
4760 * of this register is 0x0000000e. */
4761 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4763 /* Remove bad rbuf memory from the free pool. */
4764 rc = bnx2_alloc_bad_rbuf(bp);
4767 if (bp->flags & BNX2_FLAG_USING_MSIX)
4768 bnx2_setup_msix_tbl(bp);
4774 bnx2_init_chip(struct bnx2 *bp)
4779 /* Make sure the interrupt is not active. */
4780 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4782 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4783 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4785 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4787 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4788 DMA_READ_CHANS << 12 |
4789 DMA_WRITE_CHANS << 16;
4791 val |= (0x2 << 20) | (1 << 11);
4793 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4796 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4797 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4798 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4800 REG_WR(bp, BNX2_DMA_CONFIG, val);
4802 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4803 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4804 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4805 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4808 if (bp->flags & BNX2_FLAG_PCIX) {
4811 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4813 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4814 val16 & ~PCI_X_CMD_ERO);
4817 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4818 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4819 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4820 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4822 /* Initialize context mapping and zero out the quick contexts. The
4823 * context block must have already been enabled. */
4824 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4825 rc = bnx2_init_5709_context(bp);
4829 bnx2_init_context(bp);
4831 if ((rc = bnx2_init_cpus(bp)) != 0)
4834 bnx2_init_nvram(bp);
4836 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4838 val = REG_RD(bp, BNX2_MQ_CONFIG);
4839 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4840 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4841 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4842 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4843 if (CHIP_REV(bp) == CHIP_REV_Ax)
4844 val |= BNX2_MQ_CONFIG_HALT_DIS;
4847 REG_WR(bp, BNX2_MQ_CONFIG, val);
4849 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4850 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4851 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4853 val = (BCM_PAGE_BITS - 8) << 24;
4854 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4856 /* Configure page size. */
4857 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4858 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4859 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4860 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4862 val = bp->mac_addr[0] +
4863 (bp->mac_addr[1] << 8) +
4864 (bp->mac_addr[2] << 16) +
4866 (bp->mac_addr[4] << 8) +
4867 (bp->mac_addr[5] << 16);
4868 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4870 /* Program the MTU. Also include 4 bytes for CRC32. */
4872 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4873 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4874 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4875 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4880 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4881 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4882 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4884 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4885 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4886 bp->bnx2_napi[i].last_status_idx = 0;
4888 bp->idle_chk_status_idx = 0xffff;
4890 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4892 /* Set up how to generate a link change interrupt. */
4893 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4895 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4896 (u64) bp->status_blk_mapping & 0xffffffff);
4897 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4899 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4900 (u64) bp->stats_blk_mapping & 0xffffffff);
4901 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4902 (u64) bp->stats_blk_mapping >> 32);
4904 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4905 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4907 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4908 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4910 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4911 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4913 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4915 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4917 REG_WR(bp, BNX2_HC_COM_TICKS,
4918 (bp->com_ticks_int << 16) | bp->com_ticks);
4920 REG_WR(bp, BNX2_HC_CMD_TICKS,
4921 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4923 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4924 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4926 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4927 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4929 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4930 val = BNX2_HC_CONFIG_COLLECT_STATS;
4932 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4933 BNX2_HC_CONFIG_COLLECT_STATS;
4936 if (bp->irq_nvecs > 1) {
4937 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4938 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4940 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4943 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4944 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4946 REG_WR(bp, BNX2_HC_CONFIG, val);
4948 for (i = 1; i < bp->irq_nvecs; i++) {
4949 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4950 BNX2_HC_SB_CONFIG_1;
4953 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4954 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4955 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4957 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4958 (bp->tx_quick_cons_trip_int << 16) |
4959 bp->tx_quick_cons_trip);
4961 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4962 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4964 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4965 (bp->rx_quick_cons_trip_int << 16) |
4966 bp->rx_quick_cons_trip);
4968 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4969 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4972 /* Clear internal stats counters. */
4973 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4975 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4977 /* Initialize the receive filter. */
4978 bnx2_set_rx_mode(bp->dev);
4980 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4981 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4982 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4983 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4985 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4988 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4989 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4993 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4999 bnx2_clear_ring_states(struct bnx2 *bp)
5001 struct bnx2_napi *bnapi;
5002 struct bnx2_tx_ring_info *txr;
5003 struct bnx2_rx_ring_info *rxr;
5006 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5007 bnapi = &bp->bnx2_napi[i];
5008 txr = &bnapi->tx_ring;
5009 rxr = &bnapi->rx_ring;
5012 txr->hw_tx_cons = 0;
5013 rxr->rx_prod_bseq = 0;
5016 rxr->rx_pg_prod = 0;
5017 rxr->rx_pg_cons = 0;
5022 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5024 u32 val, offset0, offset1, offset2, offset3;
5025 u32 cid_addr = GET_CID_ADDR(cid);
5027 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5028 offset0 = BNX2_L2CTX_TYPE_XI;
5029 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5030 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5031 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5033 offset0 = BNX2_L2CTX_TYPE;
5034 offset1 = BNX2_L2CTX_CMD_TYPE;
5035 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5036 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5038 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5039 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5041 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5042 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5044 val = (u64) txr->tx_desc_mapping >> 32;
5045 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5047 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5048 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5052 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5056 struct bnx2_napi *bnapi;
5057 struct bnx2_tx_ring_info *txr;
5059 bnapi = &bp->bnx2_napi[ring_num];
5060 txr = &bnapi->tx_ring;
5065 cid = TX_TSS_CID + ring_num - 1;
5067 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5069 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5071 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5072 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5075 txr->tx_prod_bseq = 0;
5077 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5078 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5080 bnx2_init_tx_context(bp, cid, txr);
5084 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5090 for (i = 0; i < num_rings; i++) {
5093 rxbd = &rx_ring[i][0];
5094 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5095 rxbd->rx_bd_len = buf_size;
5096 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5098 if (i == (num_rings - 1))
5102 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5103 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5108 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5111 u16 prod, ring_prod;
5112 u32 cid, rx_cid_addr, val;
5113 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5114 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5119 cid = RX_RSS_CID + ring_num - 1;
5121 rx_cid_addr = GET_CID_ADDR(cid);
5123 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5124 bp->rx_buf_use_size, bp->rx_max_ring);
5126 bnx2_init_rx_context(bp, cid);
5128 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5129 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5130 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5133 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5134 if (bp->rx_pg_ring_size) {
5135 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5136 rxr->rx_pg_desc_mapping,
5137 PAGE_SIZE, bp->rx_max_pg_ring);
5138 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5139 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5140 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5141 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5143 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5144 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5146 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5147 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5149 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5150 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5153 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5154 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5156 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5157 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5159 ring_prod = prod = rxr->rx_pg_prod;
5160 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5161 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
5163 prod = NEXT_RX_BD(prod);
5164 ring_prod = RX_PG_RING_IDX(prod);
5166 rxr->rx_pg_prod = prod;
5168 ring_prod = prod = rxr->rx_prod;
5169 for (i = 0; i < bp->rx_ring_size; i++) {
5170 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
5172 prod = NEXT_RX_BD(prod);
5173 ring_prod = RX_RING_IDX(prod);
5175 rxr->rx_prod = prod;
5177 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5178 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5179 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5181 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5182 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5184 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5188 bnx2_init_all_rings(struct bnx2 *bp)
5193 bnx2_clear_ring_states(bp);
5195 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5196 for (i = 0; i < bp->num_tx_rings; i++)
5197 bnx2_init_tx_ring(bp, i);
5199 if (bp->num_tx_rings > 1)
5200 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5203 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5204 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5206 for (i = 0; i < bp->num_rx_rings; i++)
5207 bnx2_init_rx_ring(bp, i);
5209 if (bp->num_rx_rings > 1) {
5211 u8 *tbl = (u8 *) &tbl_32;
5213 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5214 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5216 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5217 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5220 BNX2_RXP_SCRATCH_RSS_TBL + i,
5221 cpu_to_be32(tbl_32));
5224 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5225 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5227 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5232 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5234 u32 max, num_rings = 1;
5236 while (ring_size > MAX_RX_DESC_CNT) {
5237 ring_size -= MAX_RX_DESC_CNT;
5240 /* round to next power of 2 */
5242 while ((max & num_rings) == 0)
5245 if (num_rings != max)
5252 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5254 u32 rx_size, rx_space, jumbo_size;
5256 /* 8 for CRC and VLAN */
5257 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5259 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5260 sizeof(struct skb_shared_info);
5262 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5263 bp->rx_pg_ring_size = 0;
5264 bp->rx_max_pg_ring = 0;
5265 bp->rx_max_pg_ring_idx = 0;
5266 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5267 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5269 jumbo_size = size * pages;
5270 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5271 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5273 bp->rx_pg_ring_size = jumbo_size;
5274 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5276 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5277 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5278 bp->rx_copy_thresh = 0;
5281 bp->rx_buf_use_size = rx_size;
5283 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5284 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5285 bp->rx_ring_size = size;
5286 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5287 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5291 bnx2_free_tx_skbs(struct bnx2 *bp)
5295 for (i = 0; i < bp->num_tx_rings; i++) {
5296 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5297 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5300 if (txr->tx_buf_ring == NULL)
5303 for (j = 0; j < TX_DESC_CNT; ) {
5304 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5305 struct sk_buff *skb = tx_buf->skb;
5313 pci_unmap_single(bp->pdev,
5314 pci_unmap_addr(tx_buf, mapping),
5320 last = tx_buf->nr_frags;
5322 for (k = 0; k < last; k++, j++) {
5323 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5324 pci_unmap_page(bp->pdev,
5325 pci_unmap_addr(tx_buf, mapping),
5326 skb_shinfo(skb)->frags[k].size,
5335 bnx2_free_rx_skbs(struct bnx2 *bp)
5339 for (i = 0; i < bp->num_rx_rings; i++) {
5340 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5341 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5344 if (rxr->rx_buf_ring == NULL)
5347 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5348 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5349 struct sk_buff *skb = rx_buf->skb;
5354 pci_unmap_single(bp->pdev,
5355 pci_unmap_addr(rx_buf, mapping),
5356 bp->rx_buf_use_size,
5357 PCI_DMA_FROMDEVICE);
5363 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5364 bnx2_free_rx_page(bp, rxr, j);
5369 bnx2_free_skbs(struct bnx2 *bp)
5371 bnx2_free_tx_skbs(bp);
5372 bnx2_free_rx_skbs(bp);
5376 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5380 rc = bnx2_reset_chip(bp, reset_code);
5385 if ((rc = bnx2_init_chip(bp)) != 0)
5388 bnx2_init_all_rings(bp);
5393 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5397 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5400 spin_lock_bh(&bp->phy_lock);
5401 bnx2_init_phy(bp, reset_phy);
5403 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5404 bnx2_remote_phy_event(bp);
5405 spin_unlock_bh(&bp->phy_lock);
5410 bnx2_shutdown_chip(struct bnx2 *bp)
5414 if (bp->flags & BNX2_FLAG_NO_WOL)
5415 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5417 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5419 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5421 return bnx2_reset_chip(bp, reset_code);
5425 bnx2_test_registers(struct bnx2 *bp)
5429 static const struct {
5432 #define BNX2_FL_NOT_5709 1
5436 { 0x006c, 0, 0x00000000, 0x0000003f },
5437 { 0x0090, 0, 0xffffffff, 0x00000000 },
5438 { 0x0094, 0, 0x00000000, 0x00000000 },
5440 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5441 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5442 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5443 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5444 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5445 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5446 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5447 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5448 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5450 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5451 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5452 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5453 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5454 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5455 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5457 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5458 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5459 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5461 { 0x1000, 0, 0x00000000, 0x00000001 },
5462 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5464 { 0x1408, 0, 0x01c00800, 0x00000000 },
5465 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5466 { 0x14a8, 0, 0x00000000, 0x000001ff },
5467 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5468 { 0x14b0, 0, 0x00000002, 0x00000001 },
5469 { 0x14b8, 0, 0x00000000, 0x00000000 },
5470 { 0x14c0, 0, 0x00000000, 0x00000009 },
5471 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5472 { 0x14cc, 0, 0x00000000, 0x00000001 },
5473 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5475 { 0x1800, 0, 0x00000000, 0x00000001 },
5476 { 0x1804, 0, 0x00000000, 0x00000003 },
5478 { 0x2800, 0, 0x00000000, 0x00000001 },
5479 { 0x2804, 0, 0x00000000, 0x00003f01 },
5480 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5481 { 0x2810, 0, 0xffff0000, 0x00000000 },
5482 { 0x2814, 0, 0xffff0000, 0x00000000 },
5483 { 0x2818, 0, 0xffff0000, 0x00000000 },
5484 { 0x281c, 0, 0xffff0000, 0x00000000 },
5485 { 0x2834, 0, 0xffffffff, 0x00000000 },
5486 { 0x2840, 0, 0x00000000, 0xffffffff },
5487 { 0x2844, 0, 0x00000000, 0xffffffff },
5488 { 0x2848, 0, 0xffffffff, 0x00000000 },
5489 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5491 { 0x2c00, 0, 0x00000000, 0x00000011 },
5492 { 0x2c04, 0, 0x00000000, 0x00030007 },
5494 { 0x3c00, 0, 0x00000000, 0x00000001 },
5495 { 0x3c04, 0, 0x00000000, 0x00070000 },
5496 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5497 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5498 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5499 { 0x3c14, 0, 0x00000000, 0xffffffff },
5500 { 0x3c18, 0, 0x00000000, 0xffffffff },
5501 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5502 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5504 { 0x5004, 0, 0x00000000, 0x0000007f },
5505 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5507 { 0x5c00, 0, 0x00000000, 0x00000001 },
5508 { 0x5c04, 0, 0x00000000, 0x0003000f },
5509 { 0x5c08, 0, 0x00000003, 0x00000000 },
5510 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5511 { 0x5c10, 0, 0x00000000, 0xffffffff },
5512 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5513 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5514 { 0x5c88, 0, 0x00000000, 0x00077373 },
5515 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5517 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5518 { 0x680c, 0, 0xffffffff, 0x00000000 },
5519 { 0x6810, 0, 0xffffffff, 0x00000000 },
5520 { 0x6814, 0, 0xffffffff, 0x00000000 },
5521 { 0x6818, 0, 0xffffffff, 0x00000000 },
5522 { 0x681c, 0, 0xffffffff, 0x00000000 },
5523 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5524 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5525 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5526 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5527 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5528 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5529 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5530 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5531 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5532 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5533 { 0x684c, 0, 0xffffffff, 0x00000000 },
5534 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5535 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5536 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5537 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5538 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5539 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5541 { 0xffff, 0, 0x00000000, 0x00000000 },
5546 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5549 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5550 u32 offset, rw_mask, ro_mask, save_val, val;
5551 u16 flags = reg_tbl[i].flags;
5553 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5556 offset = (u32) reg_tbl[i].offset;
5557 rw_mask = reg_tbl[i].rw_mask;
5558 ro_mask = reg_tbl[i].ro_mask;
5560 save_val = readl(bp->regview + offset);
5562 writel(0, bp->regview + offset);
5564 val = readl(bp->regview + offset);
5565 if ((val & rw_mask) != 0) {
5569 if ((val & ro_mask) != (save_val & ro_mask)) {
5573 writel(0xffffffff, bp->regview + offset);
5575 val = readl(bp->regview + offset);
5576 if ((val & rw_mask) != rw_mask) {
5580 if ((val & ro_mask) != (save_val & ro_mask)) {
5584 writel(save_val, bp->regview + offset);
5588 writel(save_val, bp->regview + offset);
5596 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5598 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5599 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5602 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5605 for (offset = 0; offset < size; offset += 4) {
5607 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5609 if (bnx2_reg_rd_ind(bp, start + offset) !=
5619 bnx2_test_memory(struct bnx2 *bp)
5623 static struct mem_entry {
5626 } mem_tbl_5706[] = {
5627 { 0x60000, 0x4000 },
5628 { 0xa0000, 0x3000 },
5629 { 0xe0000, 0x4000 },
5630 { 0x120000, 0x4000 },
5631 { 0x1a0000, 0x4000 },
5632 { 0x160000, 0x4000 },
5636 { 0x60000, 0x4000 },
5637 { 0xa0000, 0x3000 },
5638 { 0xe0000, 0x4000 },
5639 { 0x120000, 0x4000 },
5640 { 0x1a0000, 0x4000 },
5643 struct mem_entry *mem_tbl;
5645 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5646 mem_tbl = mem_tbl_5709;
5648 mem_tbl = mem_tbl_5706;
5650 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5651 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5652 mem_tbl[i].len)) != 0) {
5660 #define BNX2_MAC_LOOPBACK 0
5661 #define BNX2_PHY_LOOPBACK 1
5664 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5666 unsigned int pkt_size, num_pkts, i;
5667 struct sk_buff *skb, *rx_skb;
5668 unsigned char *packet;
5669 u16 rx_start_idx, rx_idx;
5672 struct sw_bd *rx_buf;
5673 struct l2_fhdr *rx_hdr;
5675 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5676 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5677 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5681 txr = &tx_napi->tx_ring;
5682 rxr = &bnapi->rx_ring;
5683 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5684 bp->loopback = MAC_LOOPBACK;
5685 bnx2_set_mac_loopback(bp);
5687 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5688 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5691 bp->loopback = PHY_LOOPBACK;
5692 bnx2_set_phy_loopback(bp);
5697 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5698 skb = netdev_alloc_skb(bp->dev, pkt_size);
5701 packet = skb_put(skb, pkt_size);
5702 memcpy(packet, bp->dev->dev_addr, 6);
5703 memset(packet + 6, 0x0, 8);
5704 for (i = 14; i < pkt_size; i++)
5705 packet[i] = (unsigned char) (i & 0xff);
5707 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5709 if (pci_dma_mapping_error(bp->pdev, map)) {
5714 REG_WR(bp, BNX2_HC_COMMAND,
5715 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5717 REG_RD(bp, BNX2_HC_COMMAND);
5720 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5724 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5726 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5727 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5728 txbd->tx_bd_mss_nbytes = pkt_size;
5729 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5732 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5733 txr->tx_prod_bseq += pkt_size;
5735 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5736 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5740 REG_WR(bp, BNX2_HC_COMMAND,
5741 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5743 REG_RD(bp, BNX2_HC_COMMAND);
5747 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5750 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5751 goto loopback_test_done;
5753 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5754 if (rx_idx != rx_start_idx + num_pkts) {
5755 goto loopback_test_done;
5758 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5759 rx_skb = rx_buf->skb;
5761 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5762 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5764 pci_dma_sync_single_for_cpu(bp->pdev,
5765 pci_unmap_addr(rx_buf, mapping),
5766 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5768 if (rx_hdr->l2_fhdr_status &
5769 (L2_FHDR_ERRORS_BAD_CRC |
5770 L2_FHDR_ERRORS_PHY_DECODE |
5771 L2_FHDR_ERRORS_ALIGNMENT |
5772 L2_FHDR_ERRORS_TOO_SHORT |
5773 L2_FHDR_ERRORS_GIANT_FRAME)) {
5775 goto loopback_test_done;
5778 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5779 goto loopback_test_done;
5782 for (i = 14; i < pkt_size; i++) {
5783 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5784 goto loopback_test_done;
5795 #define BNX2_MAC_LOOPBACK_FAILED 1
5796 #define BNX2_PHY_LOOPBACK_FAILED 2
5797 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5798 BNX2_PHY_LOOPBACK_FAILED)
5801 bnx2_test_loopback(struct bnx2 *bp)
5805 if (!netif_running(bp->dev))
5806 return BNX2_LOOPBACK_FAILED;
5808 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5809 spin_lock_bh(&bp->phy_lock);
5810 bnx2_init_phy(bp, 1);
5811 spin_unlock_bh(&bp->phy_lock);
5812 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5813 rc |= BNX2_MAC_LOOPBACK_FAILED;
5814 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5815 rc |= BNX2_PHY_LOOPBACK_FAILED;
5819 #define NVRAM_SIZE 0x200
5820 #define CRC32_RESIDUAL 0xdebb20e3
5823 bnx2_test_nvram(struct bnx2 *bp)
5825 __be32 buf[NVRAM_SIZE / 4];
5826 u8 *data = (u8 *) buf;
5830 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5831 goto test_nvram_done;
5833 magic = be32_to_cpu(buf[0]);
5834 if (magic != 0x669955aa) {
5836 goto test_nvram_done;
5839 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5840 goto test_nvram_done;
5842 csum = ether_crc_le(0x100, data);
5843 if (csum != CRC32_RESIDUAL) {
5845 goto test_nvram_done;
5848 csum = ether_crc_le(0x100, data + 0x100);
5849 if (csum != CRC32_RESIDUAL) {
5858 bnx2_test_link(struct bnx2 *bp)
5862 if (!netif_running(bp->dev))
5865 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5870 spin_lock_bh(&bp->phy_lock);
5871 bnx2_enable_bmsr1(bp);
5872 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5873 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5874 bnx2_disable_bmsr1(bp);
5875 spin_unlock_bh(&bp->phy_lock);
5877 if (bmsr & BMSR_LSTATUS) {
5884 bnx2_test_intr(struct bnx2 *bp)
5889 if (!netif_running(bp->dev))
5892 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5894 /* This register is not touched during run-time. */
5895 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5896 REG_RD(bp, BNX2_HC_COMMAND);
5898 for (i = 0; i < 10; i++) {
5899 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5905 msleep_interruptible(10);
5913 /* Determining link for parallel detection. */
5915 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5917 u32 mode_ctl, an_dbg, exp;
5919 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5922 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5923 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5925 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5928 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5929 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5930 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5932 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5935 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5936 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5937 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5939 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5946 bnx2_5706_serdes_timer(struct bnx2 *bp)
5950 spin_lock(&bp->phy_lock);
5951 if (bp->serdes_an_pending) {
5952 bp->serdes_an_pending--;
5954 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5957 bp->current_interval = BNX2_TIMER_INTERVAL;
5959 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5961 if (bmcr & BMCR_ANENABLE) {
5962 if (bnx2_5706_serdes_has_link(bp)) {
5963 bmcr &= ~BMCR_ANENABLE;
5964 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5965 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5966 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5970 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5971 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5974 bnx2_write_phy(bp, 0x17, 0x0f01);
5975 bnx2_read_phy(bp, 0x15, &phy2);
5979 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5980 bmcr |= BMCR_ANENABLE;
5981 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5983 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5986 bp->current_interval = BNX2_TIMER_INTERVAL;
5991 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5992 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5993 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5995 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5996 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5997 bnx2_5706s_force_link_dn(bp, 1);
5998 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6001 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6004 spin_unlock(&bp->phy_lock);
6008 bnx2_5708_serdes_timer(struct bnx2 *bp)
6010 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6013 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6014 bp->serdes_an_pending = 0;
6018 spin_lock(&bp->phy_lock);
6019 if (bp->serdes_an_pending)
6020 bp->serdes_an_pending--;
6021 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6024 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6025 if (bmcr & BMCR_ANENABLE) {
6026 bnx2_enable_forced_2g5(bp);
6027 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6029 bnx2_disable_forced_2g5(bp);
6030 bp->serdes_an_pending = 2;
6031 bp->current_interval = BNX2_TIMER_INTERVAL;
6035 bp->current_interval = BNX2_TIMER_INTERVAL;
6037 spin_unlock(&bp->phy_lock);
6041 bnx2_timer(unsigned long data)
6043 struct bnx2 *bp = (struct bnx2 *) data;
6045 if (!netif_running(bp->dev))
6048 if (atomic_read(&bp->intr_sem) != 0)
6049 goto bnx2_restart_timer;
6051 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6052 BNX2_FLAG_USING_MSI)
6053 bnx2_chk_missed_msi(bp);
6055 bnx2_send_heart_beat(bp);
6057 bp->stats_blk->stat_FwRxDrop =
6058 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6060 /* workaround occasional corrupted counters */
6061 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6062 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6063 BNX2_HC_COMMAND_STATS_NOW);
6065 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6066 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6067 bnx2_5706_serdes_timer(bp);
6069 bnx2_5708_serdes_timer(bp);
6073 mod_timer(&bp->timer, jiffies + bp->current_interval);
6077 bnx2_request_irq(struct bnx2 *bp)
6079 unsigned long flags;
6080 struct bnx2_irq *irq;
6083 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6086 flags = IRQF_SHARED;
6088 for (i = 0; i < bp->irq_nvecs; i++) {
6089 irq = &bp->irq_tbl[i];
6090 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6100 bnx2_free_irq(struct bnx2 *bp)
6102 struct bnx2_irq *irq;
6105 for (i = 0; i < bp->irq_nvecs; i++) {
6106 irq = &bp->irq_tbl[i];
6108 free_irq(irq->vector, &bp->bnx2_napi[i]);
6111 if (bp->flags & BNX2_FLAG_USING_MSI)
6112 pci_disable_msi(bp->pdev);
6113 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6114 pci_disable_msix(bp->pdev);
6116 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6120 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6123 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6124 struct net_device *dev = bp->dev;
6125 const int len = sizeof(bp->irq_tbl[0].name);
6127 bnx2_setup_msix_tbl(bp);
6128 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6129 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6130 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6132 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6133 msix_ent[i].entry = i;
6134 msix_ent[i].vector = 0;
6137 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6141 bp->irq_nvecs = msix_vecs;
6142 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6143 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6144 bp->irq_tbl[i].vector = msix_ent[i].vector;
6145 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6146 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6151 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6153 int cpus = num_online_cpus();
6154 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6156 bp->irq_tbl[0].handler = bnx2_interrupt;
6157 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6159 bp->irq_tbl[0].vector = bp->pdev->irq;
6161 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6162 bnx2_enable_msix(bp, msix_vecs);
6164 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6165 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6166 if (pci_enable_msi(bp->pdev) == 0) {
6167 bp->flags |= BNX2_FLAG_USING_MSI;
6168 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6169 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6170 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6172 bp->irq_tbl[0].handler = bnx2_msi;
6174 bp->irq_tbl[0].vector = bp->pdev->irq;
6178 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6179 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6181 bp->num_rx_rings = bp->irq_nvecs;
6184 /* Called with rtnl_lock */
6186 bnx2_open(struct net_device *dev)
6188 struct bnx2 *bp = netdev_priv(dev);
6191 netif_carrier_off(dev);
6193 bnx2_set_power_state(bp, PCI_D0);
6194 bnx2_disable_int(bp);
6196 bnx2_setup_int_mode(bp, disable_msi);
6197 bnx2_napi_enable(bp);
6198 rc = bnx2_alloc_mem(bp);
6202 rc = bnx2_request_irq(bp);
6206 rc = bnx2_init_nic(bp, 1);
6210 mod_timer(&bp->timer, jiffies + bp->current_interval);
6212 atomic_set(&bp->intr_sem, 0);
6214 bnx2_enable_int(bp);
6216 if (bp->flags & BNX2_FLAG_USING_MSI) {
6217 /* Test MSI to make sure it is working
6218 * If MSI test fails, go back to INTx mode
6220 if (bnx2_test_intr(bp) != 0) {
6221 printk(KERN_WARNING PFX "%s: No interrupt was generated"
6222 " using MSI, switching to INTx mode. Please"
6223 " report this failure to the PCI maintainer"
6224 " and include system chipset information.\n",
6227 bnx2_disable_int(bp);
6230 bnx2_setup_int_mode(bp, 1);
6232 rc = bnx2_init_nic(bp, 0);
6235 rc = bnx2_request_irq(bp);
6238 del_timer_sync(&bp->timer);
6241 bnx2_enable_int(bp);
6244 if (bp->flags & BNX2_FLAG_USING_MSI)
6245 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
6246 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6247 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
6249 netif_tx_start_all_queues(dev);
6254 bnx2_napi_disable(bp);
6262 bnx2_reset_task(struct work_struct *work)
6264 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6266 if (!netif_running(bp->dev))
6269 bnx2_netif_stop(bp);
6271 bnx2_init_nic(bp, 1);
6273 atomic_set(&bp->intr_sem, 1);
6274 bnx2_netif_start(bp);
6278 bnx2_tx_timeout(struct net_device *dev)
6280 struct bnx2 *bp = netdev_priv(dev);
6282 /* This allows the netif to be shutdown gracefully before resetting */
6283 schedule_work(&bp->reset_task);
6287 /* Called with rtnl_lock */
6289 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6291 struct bnx2 *bp = netdev_priv(dev);
6293 if (netif_running(dev))
6294 bnx2_netif_stop(bp);
6298 if (!netif_running(dev))
6301 bnx2_set_rx_mode(dev);
6302 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6303 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6305 bnx2_netif_start(bp);
6309 /* Called with netif_tx_lock.
6310 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6311 * netif_wake_queue().
6314 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6316 struct bnx2 *bp = netdev_priv(dev);
6319 struct sw_tx_bd *tx_buf;
6320 u32 len, vlan_tag_flags, last_frag, mss;
6321 u16 prod, ring_prod;
6323 struct bnx2_napi *bnapi;
6324 struct bnx2_tx_ring_info *txr;
6325 struct netdev_queue *txq;
6327 /* Determine which tx ring we will be placed on */
6328 i = skb_get_queue_mapping(skb);
6329 bnapi = &bp->bnx2_napi[i];
6330 txr = &bnapi->tx_ring;
6331 txq = netdev_get_tx_queue(dev, i);
6333 if (unlikely(bnx2_tx_avail(bp, txr) <
6334 (skb_shinfo(skb)->nr_frags + 1))) {
6335 netif_tx_stop_queue(txq);
6336 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6339 return NETDEV_TX_BUSY;
6341 len = skb_headlen(skb);
6342 prod = txr->tx_prod;
6343 ring_prod = TX_RING_IDX(prod);
6346 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6347 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6351 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6353 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6356 if ((mss = skb_shinfo(skb)->gso_size)) {
6360 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6362 tcp_opt_len = tcp_optlen(skb);
6364 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6365 u32 tcp_off = skb_transport_offset(skb) -
6366 sizeof(struct ipv6hdr) - ETH_HLEN;
6368 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6369 TX_BD_FLAGS_SW_FLAGS;
6370 if (likely(tcp_off == 0))
6371 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6374 vlan_tag_flags |= ((tcp_off & 0x3) <<
6375 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6376 ((tcp_off & 0x10) <<
6377 TX_BD_FLAGS_TCP6_OFF4_SHL);
6378 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6382 if (tcp_opt_len || (iph->ihl > 5)) {
6383 vlan_tag_flags |= ((iph->ihl - 5) +
6384 (tcp_opt_len >> 2)) << 8;
6390 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6391 if (pci_dma_mapping_error(bp->pdev, mapping)) {
6393 return NETDEV_TX_OK;
6396 tx_buf = &txr->tx_buf_ring[ring_prod];
6398 pci_unmap_addr_set(tx_buf, mapping, mapping);
6400 txbd = &txr->tx_desc_ring[ring_prod];
6402 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6403 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6404 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6405 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6407 last_frag = skb_shinfo(skb)->nr_frags;
6408 tx_buf->nr_frags = last_frag;
6409 tx_buf->is_gso = skb_is_gso(skb);
6411 for (i = 0; i < last_frag; i++) {
6412 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6414 prod = NEXT_TX_BD(prod);
6415 ring_prod = TX_RING_IDX(prod);
6416 txbd = &txr->tx_desc_ring[ring_prod];
6419 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6420 len, PCI_DMA_TODEVICE);
6421 if (pci_dma_mapping_error(bp->pdev, mapping))
6423 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6426 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6427 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6428 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6429 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6432 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6434 prod = NEXT_TX_BD(prod);
6435 txr->tx_prod_bseq += skb->len;
6437 REG_WR16(bp, txr->tx_bidx_addr, prod);
6438 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6442 txr->tx_prod = prod;
6444 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6445 netif_tx_stop_queue(txq);
6446 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6447 netif_tx_wake_queue(txq);
6450 return NETDEV_TX_OK;
6452 /* save value of frag that failed */
6455 /* start back at beginning and unmap skb */
6456 prod = txr->tx_prod;
6457 ring_prod = TX_RING_IDX(prod);
6458 tx_buf = &txr->tx_buf_ring[ring_prod];
6460 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6461 skb_headlen(skb), PCI_DMA_TODEVICE);
6463 /* unmap remaining mapped pages */
6464 for (i = 0; i < last_frag; i++) {
6465 prod = NEXT_TX_BD(prod);
6466 ring_prod = TX_RING_IDX(prod);
6467 tx_buf = &txr->tx_buf_ring[ring_prod];
6468 pci_unmap_page(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6469 skb_shinfo(skb)->frags[i].size,
6474 return NETDEV_TX_OK;
6477 /* Called with rtnl_lock */
6479 bnx2_close(struct net_device *dev)
6481 struct bnx2 *bp = netdev_priv(dev);
6483 cancel_work_sync(&bp->reset_task);
6485 bnx2_disable_int_sync(bp);
6486 bnx2_napi_disable(bp);
6487 del_timer_sync(&bp->timer);
6488 bnx2_shutdown_chip(bp);
6493 netif_carrier_off(bp->dev);
6494 bnx2_set_power_state(bp, PCI_D3hot);
6498 #define GET_NET_STATS64(ctr) \
6499 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6500 (unsigned long) (ctr##_lo)
6502 #define GET_NET_STATS32(ctr) \
6505 #if (BITS_PER_LONG == 64)
6506 #define GET_NET_STATS GET_NET_STATS64
6508 #define GET_NET_STATS GET_NET_STATS32
6511 static struct net_device_stats *
6512 bnx2_get_stats(struct net_device *dev)
6514 struct bnx2 *bp = netdev_priv(dev);
6515 struct statistics_block *stats_blk = bp->stats_blk;
6516 struct net_device_stats *net_stats = &dev->stats;
6518 if (bp->stats_blk == NULL) {
6521 net_stats->rx_packets =
6522 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6523 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6524 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6526 net_stats->tx_packets =
6527 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6528 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6529 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6531 net_stats->rx_bytes =
6532 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6534 net_stats->tx_bytes =
6535 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6537 net_stats->multicast =
6538 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6540 net_stats->collisions =
6541 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6543 net_stats->rx_length_errors =
6544 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6545 stats_blk->stat_EtherStatsOverrsizePkts);
6547 net_stats->rx_over_errors =
6548 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6549 stats_blk->stat_IfInMBUFDiscards);
6551 net_stats->rx_frame_errors =
6552 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6554 net_stats->rx_crc_errors =
6555 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6557 net_stats->rx_errors = net_stats->rx_length_errors +
6558 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6559 net_stats->rx_crc_errors;
6561 net_stats->tx_aborted_errors =
6562 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6563 stats_blk->stat_Dot3StatsLateCollisions);
6565 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6566 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6567 net_stats->tx_carrier_errors = 0;
6569 net_stats->tx_carrier_errors =
6571 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6574 net_stats->tx_errors =
6576 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6578 net_stats->tx_aborted_errors +
6579 net_stats->tx_carrier_errors;
6581 net_stats->rx_missed_errors =
6582 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6583 stats_blk->stat_IfInMBUFDiscards + stats_blk->stat_FwRxDrop);
6588 /* All ethtool functions called with rtnl_lock */
6591 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6593 struct bnx2 *bp = netdev_priv(dev);
6594 int support_serdes = 0, support_copper = 0;
6596 cmd->supported = SUPPORTED_Autoneg;
6597 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6600 } else if (bp->phy_port == PORT_FIBRE)
6605 if (support_serdes) {
6606 cmd->supported |= SUPPORTED_1000baseT_Full |
6608 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6609 cmd->supported |= SUPPORTED_2500baseX_Full;
6612 if (support_copper) {
6613 cmd->supported |= SUPPORTED_10baseT_Half |
6614 SUPPORTED_10baseT_Full |
6615 SUPPORTED_100baseT_Half |
6616 SUPPORTED_100baseT_Full |
6617 SUPPORTED_1000baseT_Full |
6622 spin_lock_bh(&bp->phy_lock);
6623 cmd->port = bp->phy_port;
6624 cmd->advertising = bp->advertising;
6626 if (bp->autoneg & AUTONEG_SPEED) {
6627 cmd->autoneg = AUTONEG_ENABLE;
6630 cmd->autoneg = AUTONEG_DISABLE;
6633 if (netif_carrier_ok(dev)) {
6634 cmd->speed = bp->line_speed;
6635 cmd->duplex = bp->duplex;
6641 spin_unlock_bh(&bp->phy_lock);
6643 cmd->transceiver = XCVR_INTERNAL;
6644 cmd->phy_address = bp->phy_addr;
6650 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6652 struct bnx2 *bp = netdev_priv(dev);
6653 u8 autoneg = bp->autoneg;
6654 u8 req_duplex = bp->req_duplex;
6655 u16 req_line_speed = bp->req_line_speed;
6656 u32 advertising = bp->advertising;
6659 spin_lock_bh(&bp->phy_lock);
6661 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6662 goto err_out_unlock;
6664 if (cmd->port != bp->phy_port &&
6665 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6666 goto err_out_unlock;
6668 /* If device is down, we can store the settings only if the user
6669 * is setting the currently active port.
6671 if (!netif_running(dev) && cmd->port != bp->phy_port)
6672 goto err_out_unlock;
6674 if (cmd->autoneg == AUTONEG_ENABLE) {
6675 autoneg |= AUTONEG_SPEED;
6677 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6679 /* allow advertising 1 speed */
6680 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6681 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6682 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6683 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6685 if (cmd->port == PORT_FIBRE)
6686 goto err_out_unlock;
6688 advertising = cmd->advertising;
6690 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6691 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6692 (cmd->port == PORT_TP))
6693 goto err_out_unlock;
6694 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6695 advertising = cmd->advertising;
6696 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6697 goto err_out_unlock;
6699 if (cmd->port == PORT_FIBRE)
6700 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6702 advertising = ETHTOOL_ALL_COPPER_SPEED;
6704 advertising |= ADVERTISED_Autoneg;
6707 if (cmd->port == PORT_FIBRE) {
6708 if ((cmd->speed != SPEED_1000 &&
6709 cmd->speed != SPEED_2500) ||
6710 (cmd->duplex != DUPLEX_FULL))
6711 goto err_out_unlock;
6713 if (cmd->speed == SPEED_2500 &&
6714 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6715 goto err_out_unlock;
6717 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6718 goto err_out_unlock;
6720 autoneg &= ~AUTONEG_SPEED;
6721 req_line_speed = cmd->speed;
6722 req_duplex = cmd->duplex;
6726 bp->autoneg = autoneg;
6727 bp->advertising = advertising;
6728 bp->req_line_speed = req_line_speed;
6729 bp->req_duplex = req_duplex;
6732 /* If device is down, the new settings will be picked up when it is
6735 if (netif_running(dev))
6736 err = bnx2_setup_phy(bp, cmd->port);
6739 spin_unlock_bh(&bp->phy_lock);
6745 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6747 struct bnx2 *bp = netdev_priv(dev);
6749 strcpy(info->driver, DRV_MODULE_NAME);
6750 strcpy(info->version, DRV_MODULE_VERSION);
6751 strcpy(info->bus_info, pci_name(bp->pdev));
6752 strcpy(info->fw_version, bp->fw_version);
6755 #define BNX2_REGDUMP_LEN (32 * 1024)
6758 bnx2_get_regs_len(struct net_device *dev)
6760 return BNX2_REGDUMP_LEN;
6764 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6766 u32 *p = _p, i, offset;
6768 struct bnx2 *bp = netdev_priv(dev);
6769 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6770 0x0800, 0x0880, 0x0c00, 0x0c10,
6771 0x0c30, 0x0d08, 0x1000, 0x101c,
6772 0x1040, 0x1048, 0x1080, 0x10a4,
6773 0x1400, 0x1490, 0x1498, 0x14f0,
6774 0x1500, 0x155c, 0x1580, 0x15dc,
6775 0x1600, 0x1658, 0x1680, 0x16d8,
6776 0x1800, 0x1820, 0x1840, 0x1854,
6777 0x1880, 0x1894, 0x1900, 0x1984,
6778 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6779 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6780 0x2000, 0x2030, 0x23c0, 0x2400,
6781 0x2800, 0x2820, 0x2830, 0x2850,
6782 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6783 0x3c00, 0x3c94, 0x4000, 0x4010,
6784 0x4080, 0x4090, 0x43c0, 0x4458,
6785 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6786 0x4fc0, 0x5010, 0x53c0, 0x5444,
6787 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6788 0x5fc0, 0x6000, 0x6400, 0x6428,
6789 0x6800, 0x6848, 0x684c, 0x6860,
6790 0x6888, 0x6910, 0x8000 };
6794 memset(p, 0, BNX2_REGDUMP_LEN);
6796 if (!netif_running(bp->dev))
6800 offset = reg_boundaries[0];
6802 while (offset < BNX2_REGDUMP_LEN) {
6803 *p++ = REG_RD(bp, offset);
6805 if (offset == reg_boundaries[i + 1]) {
6806 offset = reg_boundaries[i + 2];
6807 p = (u32 *) (orig_p + offset);
6814 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6816 struct bnx2 *bp = netdev_priv(dev);
6818 if (bp->flags & BNX2_FLAG_NO_WOL) {
6823 wol->supported = WAKE_MAGIC;
6825 wol->wolopts = WAKE_MAGIC;
6829 memset(&wol->sopass, 0, sizeof(wol->sopass));
6833 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6835 struct bnx2 *bp = netdev_priv(dev);
6837 if (wol->wolopts & ~WAKE_MAGIC)
6840 if (wol->wolopts & WAKE_MAGIC) {
6841 if (bp->flags & BNX2_FLAG_NO_WOL)
6853 bnx2_nway_reset(struct net_device *dev)
6855 struct bnx2 *bp = netdev_priv(dev);
6858 if (!netif_running(dev))
6861 if (!(bp->autoneg & AUTONEG_SPEED)) {
6865 spin_lock_bh(&bp->phy_lock);
6867 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6870 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6871 spin_unlock_bh(&bp->phy_lock);
6875 /* Force a link down visible on the other side */
6876 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6877 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6878 spin_unlock_bh(&bp->phy_lock);
6882 spin_lock_bh(&bp->phy_lock);
6884 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6885 bp->serdes_an_pending = 1;
6886 mod_timer(&bp->timer, jiffies + bp->current_interval);
6889 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6890 bmcr &= ~BMCR_LOOPBACK;
6891 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6893 spin_unlock_bh(&bp->phy_lock);
6899 bnx2_get_link(struct net_device *dev)
6901 struct bnx2 *bp = netdev_priv(dev);
6907 bnx2_get_eeprom_len(struct net_device *dev)
6909 struct bnx2 *bp = netdev_priv(dev);
6911 if (bp->flash_info == NULL)
6914 return (int) bp->flash_size;
6918 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6921 struct bnx2 *bp = netdev_priv(dev);
6924 if (!netif_running(dev))
6927 /* parameters already validated in ethtool_get_eeprom */
6929 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6935 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6938 struct bnx2 *bp = netdev_priv(dev);
6941 if (!netif_running(dev))
6944 /* parameters already validated in ethtool_set_eeprom */
6946 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6952 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6954 struct bnx2 *bp = netdev_priv(dev);
6956 memset(coal, 0, sizeof(struct ethtool_coalesce));
6958 coal->rx_coalesce_usecs = bp->rx_ticks;
6959 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6960 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6961 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6963 coal->tx_coalesce_usecs = bp->tx_ticks;
6964 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6965 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6966 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6968 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6974 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6976 struct bnx2 *bp = netdev_priv(dev);
6978 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6979 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6981 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6982 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6984 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6985 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6987 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6988 if (bp->rx_quick_cons_trip_int > 0xff)
6989 bp->rx_quick_cons_trip_int = 0xff;
6991 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6992 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6994 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6995 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6997 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6998 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7000 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7001 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7004 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7005 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7006 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7007 bp->stats_ticks = USEC_PER_SEC;
7009 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7010 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7011 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7013 if (netif_running(bp->dev)) {
7014 bnx2_netif_stop(bp);
7015 bnx2_init_nic(bp, 0);
7016 bnx2_netif_start(bp);
7023 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7025 struct bnx2 *bp = netdev_priv(dev);
7027 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7028 ering->rx_mini_max_pending = 0;
7029 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7031 ering->rx_pending = bp->rx_ring_size;
7032 ering->rx_mini_pending = 0;
7033 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7035 ering->tx_max_pending = MAX_TX_DESC_CNT;
7036 ering->tx_pending = bp->tx_ring_size;
7040 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7042 if (netif_running(bp->dev)) {
7043 bnx2_netif_stop(bp);
7044 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7049 bnx2_set_rx_ring_size(bp, rx);
7050 bp->tx_ring_size = tx;
7052 if (netif_running(bp->dev)) {
7055 rc = bnx2_alloc_mem(bp);
7057 rc = bnx2_init_nic(bp, 0);
7060 bnx2_napi_enable(bp);
7064 bnx2_netif_start(bp);
7070 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7072 struct bnx2 *bp = netdev_priv(dev);
7075 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7076 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7077 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7081 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7086 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7088 struct bnx2 *bp = netdev_priv(dev);
7090 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7091 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7092 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7096 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7098 struct bnx2 *bp = netdev_priv(dev);
7100 bp->req_flow_ctrl = 0;
7101 if (epause->rx_pause)
7102 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7103 if (epause->tx_pause)
7104 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7106 if (epause->autoneg) {
7107 bp->autoneg |= AUTONEG_FLOW_CTRL;
7110 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7113 if (netif_running(dev)) {
7114 spin_lock_bh(&bp->phy_lock);
7115 bnx2_setup_phy(bp, bp->phy_port);
7116 spin_unlock_bh(&bp->phy_lock);
7123 bnx2_get_rx_csum(struct net_device *dev)
7125 struct bnx2 *bp = netdev_priv(dev);
7131 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7133 struct bnx2 *bp = netdev_priv(dev);
7140 bnx2_set_tso(struct net_device *dev, u32 data)
7142 struct bnx2 *bp = netdev_priv(dev);
7145 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7146 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7147 dev->features |= NETIF_F_TSO6;
7149 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7155 char string[ETH_GSTRING_LEN];
7156 } bnx2_stats_str_arr[] = {
7158 { "rx_error_bytes" },
7160 { "tx_error_bytes" },
7161 { "rx_ucast_packets" },
7162 { "rx_mcast_packets" },
7163 { "rx_bcast_packets" },
7164 { "tx_ucast_packets" },
7165 { "tx_mcast_packets" },
7166 { "tx_bcast_packets" },
7167 { "tx_mac_errors" },
7168 { "tx_carrier_errors" },
7169 { "rx_crc_errors" },
7170 { "rx_align_errors" },
7171 { "tx_single_collisions" },
7172 { "tx_multi_collisions" },
7174 { "tx_excess_collisions" },
7175 { "tx_late_collisions" },
7176 { "tx_total_collisions" },
7179 { "rx_undersize_packets" },
7180 { "rx_oversize_packets" },
7181 { "rx_64_byte_packets" },
7182 { "rx_65_to_127_byte_packets" },
7183 { "rx_128_to_255_byte_packets" },
7184 { "rx_256_to_511_byte_packets" },
7185 { "rx_512_to_1023_byte_packets" },
7186 { "rx_1024_to_1522_byte_packets" },
7187 { "rx_1523_to_9022_byte_packets" },
7188 { "tx_64_byte_packets" },
7189 { "tx_65_to_127_byte_packets" },
7190 { "tx_128_to_255_byte_packets" },
7191 { "tx_256_to_511_byte_packets" },
7192 { "tx_512_to_1023_byte_packets" },
7193 { "tx_1024_to_1522_byte_packets" },
7194 { "tx_1523_to_9022_byte_packets" },
7195 { "rx_xon_frames" },
7196 { "rx_xoff_frames" },
7197 { "tx_xon_frames" },
7198 { "tx_xoff_frames" },
7199 { "rx_mac_ctrl_frames" },
7200 { "rx_filtered_packets" },
7201 { "rx_ftq_discards" },
7203 { "rx_fw_discards" },
7206 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7207 sizeof(bnx2_stats_str_arr[0]))
7209 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7211 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7212 STATS_OFFSET32(stat_IfHCInOctets_hi),
7213 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7214 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7215 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7216 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7217 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7218 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7219 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7220 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7221 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7222 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7223 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7224 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7225 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7226 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7227 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7228 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7229 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7230 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7231 STATS_OFFSET32(stat_EtherStatsCollisions),
7232 STATS_OFFSET32(stat_EtherStatsFragments),
7233 STATS_OFFSET32(stat_EtherStatsJabbers),
7234 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7235 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7236 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7237 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7238 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7239 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7240 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7241 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7242 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7243 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7244 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7245 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7246 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7247 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7248 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7249 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7250 STATS_OFFSET32(stat_XonPauseFramesReceived),
7251 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7252 STATS_OFFSET32(stat_OutXonSent),
7253 STATS_OFFSET32(stat_OutXoffSent),
7254 STATS_OFFSET32(stat_MacControlFramesReceived),
7255 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7256 STATS_OFFSET32(stat_IfInFTQDiscards),
7257 STATS_OFFSET32(stat_IfInMBUFDiscards),
7258 STATS_OFFSET32(stat_FwRxDrop),
7261 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7262 * skipped because of errata.
7264 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7265 8,0,8,8,8,8,8,8,8,8,
7266 4,0,4,4,4,4,4,4,4,4,
7267 4,4,4,4,4,4,4,4,4,4,
7268 4,4,4,4,4,4,4,4,4,4,
7272 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7273 8,0,8,8,8,8,8,8,8,8,
7274 4,4,4,4,4,4,4,4,4,4,
7275 4,4,4,4,4,4,4,4,4,4,
7276 4,4,4,4,4,4,4,4,4,4,
7280 #define BNX2_NUM_TESTS 6
7283 char string[ETH_GSTRING_LEN];
7284 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7285 { "register_test (offline)" },
7286 { "memory_test (offline)" },
7287 { "loopback_test (offline)" },
7288 { "nvram_test (online)" },
7289 { "interrupt_test (online)" },
7290 { "link_test (online)" },
7294 bnx2_get_sset_count(struct net_device *dev, int sset)
7298 return BNX2_NUM_TESTS;
7300 return BNX2_NUM_STATS;
7307 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7309 struct bnx2 *bp = netdev_priv(dev);
7311 bnx2_set_power_state(bp, PCI_D0);
7313 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7314 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7317 bnx2_netif_stop(bp);
7318 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7321 if (bnx2_test_registers(bp) != 0) {
7323 etest->flags |= ETH_TEST_FL_FAILED;
7325 if (bnx2_test_memory(bp) != 0) {
7327 etest->flags |= ETH_TEST_FL_FAILED;
7329 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7330 etest->flags |= ETH_TEST_FL_FAILED;
7332 if (!netif_running(bp->dev))
7333 bnx2_shutdown_chip(bp);
7335 bnx2_init_nic(bp, 1);
7336 bnx2_netif_start(bp);
7339 /* wait for link up */
7340 for (i = 0; i < 7; i++) {
7343 msleep_interruptible(1000);
7347 if (bnx2_test_nvram(bp) != 0) {
7349 etest->flags |= ETH_TEST_FL_FAILED;
7351 if (bnx2_test_intr(bp) != 0) {
7353 etest->flags |= ETH_TEST_FL_FAILED;
7356 if (bnx2_test_link(bp) != 0) {
7358 etest->flags |= ETH_TEST_FL_FAILED;
7361 if (!netif_running(bp->dev))
7362 bnx2_set_power_state(bp, PCI_D3hot);
7366 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7368 switch (stringset) {
7370 memcpy(buf, bnx2_stats_str_arr,
7371 sizeof(bnx2_stats_str_arr));
7374 memcpy(buf, bnx2_tests_str_arr,
7375 sizeof(bnx2_tests_str_arr));
7381 bnx2_get_ethtool_stats(struct net_device *dev,
7382 struct ethtool_stats *stats, u64 *buf)
7384 struct bnx2 *bp = netdev_priv(dev);
7386 u32 *hw_stats = (u32 *) bp->stats_blk;
7387 u8 *stats_len_arr = NULL;
7389 if (hw_stats == NULL) {
7390 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7394 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7395 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7396 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7397 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7398 stats_len_arr = bnx2_5706_stats_len_arr;
7400 stats_len_arr = bnx2_5708_stats_len_arr;
7402 for (i = 0; i < BNX2_NUM_STATS; i++) {
7403 if (stats_len_arr[i] == 0) {
7404 /* skip this counter */
7408 if (stats_len_arr[i] == 4) {
7409 /* 4-byte counter */
7411 *(hw_stats + bnx2_stats_offset_arr[i]);
7414 /* 8-byte counter */
7415 buf[i] = (((u64) *(hw_stats +
7416 bnx2_stats_offset_arr[i])) << 32) +
7417 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7422 bnx2_phys_id(struct net_device *dev, u32 data)
7424 struct bnx2 *bp = netdev_priv(dev);
7428 bnx2_set_power_state(bp, PCI_D0);
7433 save = REG_RD(bp, BNX2_MISC_CFG);
7434 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7436 for (i = 0; i < (data * 2); i++) {
7438 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7441 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7442 BNX2_EMAC_LED_1000MB_OVERRIDE |
7443 BNX2_EMAC_LED_100MB_OVERRIDE |
7444 BNX2_EMAC_LED_10MB_OVERRIDE |
7445 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7446 BNX2_EMAC_LED_TRAFFIC);
7448 msleep_interruptible(500);
7449 if (signal_pending(current))
7452 REG_WR(bp, BNX2_EMAC_LED, 0);
7453 REG_WR(bp, BNX2_MISC_CFG, save);
7455 if (!netif_running(dev))
7456 bnx2_set_power_state(bp, PCI_D3hot);
7462 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7464 struct bnx2 *bp = netdev_priv(dev);
7466 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7467 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7469 return (ethtool_op_set_tx_csum(dev, data));
7472 static const struct ethtool_ops bnx2_ethtool_ops = {
7473 .get_settings = bnx2_get_settings,
7474 .set_settings = bnx2_set_settings,
7475 .get_drvinfo = bnx2_get_drvinfo,
7476 .get_regs_len = bnx2_get_regs_len,
7477 .get_regs = bnx2_get_regs,
7478 .get_wol = bnx2_get_wol,
7479 .set_wol = bnx2_set_wol,
7480 .nway_reset = bnx2_nway_reset,
7481 .get_link = bnx2_get_link,
7482 .get_eeprom_len = bnx2_get_eeprom_len,
7483 .get_eeprom = bnx2_get_eeprom,
7484 .set_eeprom = bnx2_set_eeprom,
7485 .get_coalesce = bnx2_get_coalesce,
7486 .set_coalesce = bnx2_set_coalesce,
7487 .get_ringparam = bnx2_get_ringparam,
7488 .set_ringparam = bnx2_set_ringparam,
7489 .get_pauseparam = bnx2_get_pauseparam,
7490 .set_pauseparam = bnx2_set_pauseparam,
7491 .get_rx_csum = bnx2_get_rx_csum,
7492 .set_rx_csum = bnx2_set_rx_csum,
7493 .set_tx_csum = bnx2_set_tx_csum,
7494 .set_sg = ethtool_op_set_sg,
7495 .set_tso = bnx2_set_tso,
7496 .self_test = bnx2_self_test,
7497 .get_strings = bnx2_get_strings,
7498 .phys_id = bnx2_phys_id,
7499 .get_ethtool_stats = bnx2_get_ethtool_stats,
7500 .get_sset_count = bnx2_get_sset_count,
7503 /* Called with rtnl_lock */
7505 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7507 struct mii_ioctl_data *data = if_mii(ifr);
7508 struct bnx2 *bp = netdev_priv(dev);
7513 data->phy_id = bp->phy_addr;
7519 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7522 if (!netif_running(dev))
7525 spin_lock_bh(&bp->phy_lock);
7526 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7527 spin_unlock_bh(&bp->phy_lock);
7529 data->val_out = mii_regval;
7535 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7538 if (!netif_running(dev))
7541 spin_lock_bh(&bp->phy_lock);
7542 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7543 spin_unlock_bh(&bp->phy_lock);
7554 /* Called with rtnl_lock */
7556 bnx2_change_mac_addr(struct net_device *dev, void *p)
7558 struct sockaddr *addr = p;
7559 struct bnx2 *bp = netdev_priv(dev);
7561 if (!is_valid_ether_addr(addr->sa_data))
7564 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7565 if (netif_running(dev))
7566 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7571 /* Called with rtnl_lock */
7573 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7575 struct bnx2 *bp = netdev_priv(dev);
7577 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7578 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7582 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7585 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7587 poll_bnx2(struct net_device *dev)
7589 struct bnx2 *bp = netdev_priv(dev);
7592 for (i = 0; i < bp->irq_nvecs; i++) {
7593 disable_irq(bp->irq_tbl[i].vector);
7594 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7595 enable_irq(bp->irq_tbl[i].vector);
7600 static void __devinit
7601 bnx2_get_5709_media(struct bnx2 *bp)
7603 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7604 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7607 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7609 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7610 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7614 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7615 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7617 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7619 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7624 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7632 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7638 static void __devinit
7639 bnx2_get_pci_speed(struct bnx2 *bp)
7643 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7644 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7647 bp->flags |= BNX2_FLAG_PCIX;
7649 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7651 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7653 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7654 bp->bus_speed_mhz = 133;
7657 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7658 bp->bus_speed_mhz = 100;
7661 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7662 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7663 bp->bus_speed_mhz = 66;
7666 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7667 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7668 bp->bus_speed_mhz = 50;
7671 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7672 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7673 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7674 bp->bus_speed_mhz = 33;
7679 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7680 bp->bus_speed_mhz = 66;
7682 bp->bus_speed_mhz = 33;
7685 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7686 bp->flags |= BNX2_FLAG_PCI_32BIT;
7690 static int __devinit
7691 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7694 unsigned long mem_len;
7697 u64 dma_mask, persist_dma_mask;
7699 SET_NETDEV_DEV(dev, &pdev->dev);
7700 bp = netdev_priv(dev);
7705 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7706 rc = pci_enable_device(pdev);
7708 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7712 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7714 "Cannot find PCI device base address, aborting.\n");
7716 goto err_out_disable;
7719 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7721 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7722 goto err_out_disable;
7725 pci_set_master(pdev);
7726 pci_save_state(pdev);
7728 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7729 if (bp->pm_cap == 0) {
7731 "Cannot find power management capability, aborting.\n");
7733 goto err_out_release;
7739 spin_lock_init(&bp->phy_lock);
7740 spin_lock_init(&bp->indirect_lock);
7742 mutex_init(&bp->cnic_lock);
7744 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7746 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7747 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7748 dev->mem_end = dev->mem_start + mem_len;
7749 dev->irq = pdev->irq;
7751 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7754 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7756 goto err_out_release;
7759 /* Configure byte swap and enable write to the reg_window registers.
7760 * Rely on CPU to do target byte swapping on big endian systems
7761 * The chip's target access swapping will not swap all accesses
7763 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7764 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7765 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7767 bnx2_set_power_state(bp, PCI_D0);
7769 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7771 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7772 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7774 "Cannot find PCIE capability, aborting.\n");
7778 bp->flags |= BNX2_FLAG_PCIE;
7779 if (CHIP_REV(bp) == CHIP_REV_Ax)
7780 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7782 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7783 if (bp->pcix_cap == 0) {
7785 "Cannot find PCIX capability, aborting.\n");
7789 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7792 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7793 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7794 bp->flags |= BNX2_FLAG_MSIX_CAP;
7797 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7798 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7799 bp->flags |= BNX2_FLAG_MSI_CAP;
7802 /* 5708 cannot support DMA addresses > 40-bit. */
7803 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7804 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7806 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7808 /* Configure DMA attributes. */
7809 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7810 dev->features |= NETIF_F_HIGHDMA;
7811 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7814 "pci_set_consistent_dma_mask failed, aborting.\n");
7817 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7818 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7822 if (!(bp->flags & BNX2_FLAG_PCIE))
7823 bnx2_get_pci_speed(bp);
7825 /* 5706A0 may falsely detect SERR and PERR. */
7826 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7827 reg = REG_RD(bp, PCI_COMMAND);
7828 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7829 REG_WR(bp, PCI_COMMAND, reg);
7831 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7832 !(bp->flags & BNX2_FLAG_PCIX)) {
7835 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7839 bnx2_init_nvram(bp);
7841 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7843 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7844 BNX2_SHM_HDR_SIGNATURE_SIG) {
7845 u32 off = PCI_FUNC(pdev->devfn) << 2;
7847 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7849 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7851 /* Get the permanent MAC address. First we need to make sure the
7852 * firmware is actually running.
7854 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7856 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7857 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7858 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7863 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7864 for (i = 0, j = 0; i < 3; i++) {
7867 num = (u8) (reg >> (24 - (i * 8)));
7868 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7869 if (num >= k || !skip0 || k == 1) {
7870 bp->fw_version[j++] = (num / k) + '0';
7875 bp->fw_version[j++] = '.';
7877 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7878 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7881 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7882 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7884 for (i = 0; i < 30; i++) {
7885 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7886 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7891 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7892 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7893 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7894 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7895 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7897 bp->fw_version[j++] = ' ';
7898 for (i = 0; i < 3; i++) {
7899 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7901 memcpy(&bp->fw_version[j], ®, 4);
7906 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7907 bp->mac_addr[0] = (u8) (reg >> 8);
7908 bp->mac_addr[1] = (u8) reg;
7910 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7911 bp->mac_addr[2] = (u8) (reg >> 24);
7912 bp->mac_addr[3] = (u8) (reg >> 16);
7913 bp->mac_addr[4] = (u8) (reg >> 8);
7914 bp->mac_addr[5] = (u8) reg;
7916 bp->tx_ring_size = MAX_TX_DESC_CNT;
7917 bnx2_set_rx_ring_size(bp, 255);
7921 bp->tx_quick_cons_trip_int = 2;
7922 bp->tx_quick_cons_trip = 20;
7923 bp->tx_ticks_int = 18;
7926 bp->rx_quick_cons_trip_int = 2;
7927 bp->rx_quick_cons_trip = 12;
7928 bp->rx_ticks_int = 18;
7931 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7933 bp->current_interval = BNX2_TIMER_INTERVAL;
7937 /* Disable WOL support if we are running on a SERDES chip. */
7938 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7939 bnx2_get_5709_media(bp);
7940 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7941 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7943 bp->phy_port = PORT_TP;
7944 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7945 bp->phy_port = PORT_FIBRE;
7946 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7947 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7948 bp->flags |= BNX2_FLAG_NO_WOL;
7951 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7952 /* Don't do parallel detect on this board because of
7953 * some board problems. The link will not go down
7954 * if we do parallel detect.
7956 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7957 pdev->subsystem_device == 0x310c)
7958 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7961 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7962 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7964 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7965 CHIP_NUM(bp) == CHIP_NUM_5708)
7966 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7967 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7968 (CHIP_REV(bp) == CHIP_REV_Ax ||
7969 CHIP_REV(bp) == CHIP_REV_Bx))
7970 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7972 bnx2_init_fw_cap(bp);
7974 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7975 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7976 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7977 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7978 bp->flags |= BNX2_FLAG_NO_WOL;
7982 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7983 bp->tx_quick_cons_trip_int =
7984 bp->tx_quick_cons_trip;
7985 bp->tx_ticks_int = bp->tx_ticks;
7986 bp->rx_quick_cons_trip_int =
7987 bp->rx_quick_cons_trip;
7988 bp->rx_ticks_int = bp->rx_ticks;
7989 bp->comp_prod_trip_int = bp->comp_prod_trip;
7990 bp->com_ticks_int = bp->com_ticks;
7991 bp->cmd_ticks_int = bp->cmd_ticks;
7994 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7996 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7997 * with byte enables disabled on the unused 32-bit word. This is legal
7998 * but causes problems on the AMD 8132 which will eventually stop
7999 * responding after a while.
8001 * AMD believes this incompatibility is unique to the 5706, and
8002 * prefers to locally disable MSI rather than globally disabling it.
8004 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8005 struct pci_dev *amd_8132 = NULL;
8007 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8008 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8011 if (amd_8132->revision >= 0x10 &&
8012 amd_8132->revision <= 0x13) {
8014 pci_dev_put(amd_8132);
8020 bnx2_set_default_link(bp);
8021 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8023 init_timer(&bp->timer);
8024 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8025 bp->timer.data = (unsigned long) bp;
8026 bp->timer.function = bnx2_timer;
8032 iounmap(bp->regview);
8037 pci_release_regions(pdev);
8040 pci_disable_device(pdev);
8041 pci_set_drvdata(pdev, NULL);
8047 static char * __devinit
8048 bnx2_bus_string(struct bnx2 *bp, char *str)
8052 if (bp->flags & BNX2_FLAG_PCIE) {
8053 s += sprintf(s, "PCI Express");
8055 s += sprintf(s, "PCI");
8056 if (bp->flags & BNX2_FLAG_PCIX)
8057 s += sprintf(s, "-X");
8058 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8059 s += sprintf(s, " 32-bit");
8061 s += sprintf(s, " 64-bit");
8062 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8067 static void __devinit
8068 bnx2_init_napi(struct bnx2 *bp)
8072 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
8073 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8074 int (*poll)(struct napi_struct *, int);
8079 poll = bnx2_poll_msix;
8081 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8086 static const struct net_device_ops bnx2_netdev_ops = {
8087 .ndo_open = bnx2_open,
8088 .ndo_start_xmit = bnx2_start_xmit,
8089 .ndo_stop = bnx2_close,
8090 .ndo_get_stats = bnx2_get_stats,
8091 .ndo_set_rx_mode = bnx2_set_rx_mode,
8092 .ndo_do_ioctl = bnx2_ioctl,
8093 .ndo_validate_addr = eth_validate_addr,
8094 .ndo_set_mac_address = bnx2_change_mac_addr,
8095 .ndo_change_mtu = bnx2_change_mtu,
8096 .ndo_tx_timeout = bnx2_tx_timeout,
8098 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8100 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8101 .ndo_poll_controller = poll_bnx2,
8105 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8108 dev->vlan_features |= flags;
8112 static int __devinit
8113 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8115 static int version_printed = 0;
8116 struct net_device *dev = NULL;
8121 if (version_printed++ == 0)
8122 printk(KERN_INFO "%s", version);
8124 /* dev zeroed in init_etherdev */
8125 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8130 rc = bnx2_init_board(pdev, dev);
8136 dev->netdev_ops = &bnx2_netdev_ops;
8137 dev->watchdog_timeo = TX_TIMEOUT;
8138 dev->ethtool_ops = &bnx2_ethtool_ops;
8140 bp = netdev_priv(dev);
8143 pci_set_drvdata(pdev, dev);
8145 rc = bnx2_request_firmware(bp);
8149 memcpy(dev->dev_addr, bp->mac_addr, 6);
8150 memcpy(dev->perm_addr, bp->mac_addr, 6);
8152 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
8153 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8154 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8155 dev->features |= NETIF_F_IPV6_CSUM;
8156 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8159 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8161 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8162 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8163 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8164 dev->features |= NETIF_F_TSO6;
8165 vlan_features_add(dev, NETIF_F_TSO6);
8167 if ((rc = register_netdev(dev))) {
8168 dev_err(&pdev->dev, "Cannot register net device\n");
8172 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
8173 "IRQ %d, node addr %pM\n",
8175 board_info[ent->driver_data].name,
8176 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8177 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8178 bnx2_bus_string(bp, str),
8180 bp->pdev->irq, dev->dev_addr);
8185 if (bp->mips_firmware)
8186 release_firmware(bp->mips_firmware);
8187 if (bp->rv2p_firmware)
8188 release_firmware(bp->rv2p_firmware);
8191 iounmap(bp->regview);
8192 pci_release_regions(pdev);
8193 pci_disable_device(pdev);
8194 pci_set_drvdata(pdev, NULL);
8199 static void __devexit
8200 bnx2_remove_one(struct pci_dev *pdev)
8202 struct net_device *dev = pci_get_drvdata(pdev);
8203 struct bnx2 *bp = netdev_priv(dev);
8205 flush_scheduled_work();
8207 unregister_netdev(dev);
8209 if (bp->mips_firmware)
8210 release_firmware(bp->mips_firmware);
8211 if (bp->rv2p_firmware)
8212 release_firmware(bp->rv2p_firmware);
8215 iounmap(bp->regview);
8218 pci_release_regions(pdev);
8219 pci_disable_device(pdev);
8220 pci_set_drvdata(pdev, NULL);
8224 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8226 struct net_device *dev = pci_get_drvdata(pdev);
8227 struct bnx2 *bp = netdev_priv(dev);
8229 /* PCI register 4 needs to be saved whether netif_running() or not.
8230 * MSI address and data need to be saved if using MSI and
8233 pci_save_state(pdev);
8234 if (!netif_running(dev))
8237 flush_scheduled_work();
8238 bnx2_netif_stop(bp);
8239 netif_device_detach(dev);
8240 del_timer_sync(&bp->timer);
8241 bnx2_shutdown_chip(bp);
8243 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8248 bnx2_resume(struct pci_dev *pdev)
8250 struct net_device *dev = pci_get_drvdata(pdev);
8251 struct bnx2 *bp = netdev_priv(dev);
8253 pci_restore_state(pdev);
8254 if (!netif_running(dev))
8257 bnx2_set_power_state(bp, PCI_D0);
8258 netif_device_attach(dev);
8259 bnx2_init_nic(bp, 1);
8260 bnx2_netif_start(bp);
8265 * bnx2_io_error_detected - called when PCI error is detected
8266 * @pdev: Pointer to PCI device
8267 * @state: The current pci connection state
8269 * This function is called after a PCI bus error affecting
8270 * this device has been detected.
8272 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8273 pci_channel_state_t state)
8275 struct net_device *dev = pci_get_drvdata(pdev);
8276 struct bnx2 *bp = netdev_priv(dev);
8279 netif_device_detach(dev);
8281 if (state == pci_channel_io_perm_failure) {
8283 return PCI_ERS_RESULT_DISCONNECT;
8286 if (netif_running(dev)) {
8287 bnx2_netif_stop(bp);
8288 del_timer_sync(&bp->timer);
8289 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8292 pci_disable_device(pdev);
8295 /* Request a slot slot reset. */
8296 return PCI_ERS_RESULT_NEED_RESET;
8300 * bnx2_io_slot_reset - called after the pci bus has been reset.
8301 * @pdev: Pointer to PCI device
8303 * Restart the card from scratch, as if from a cold-boot.
8305 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8307 struct net_device *dev = pci_get_drvdata(pdev);
8308 struct bnx2 *bp = netdev_priv(dev);
8311 if (pci_enable_device(pdev)) {
8313 "Cannot re-enable PCI device after reset.\n");
8315 return PCI_ERS_RESULT_DISCONNECT;
8317 pci_set_master(pdev);
8318 pci_restore_state(pdev);
8319 pci_save_state(pdev);
8321 if (netif_running(dev)) {
8322 bnx2_set_power_state(bp, PCI_D0);
8323 bnx2_init_nic(bp, 1);
8327 return PCI_ERS_RESULT_RECOVERED;
8331 * bnx2_io_resume - called when traffic can start flowing again.
8332 * @pdev: Pointer to PCI device
8334 * This callback is called when the error recovery driver tells us that
8335 * its OK to resume normal operation.
8337 static void bnx2_io_resume(struct pci_dev *pdev)
8339 struct net_device *dev = pci_get_drvdata(pdev);
8340 struct bnx2 *bp = netdev_priv(dev);
8343 if (netif_running(dev))
8344 bnx2_netif_start(bp);
8346 netif_device_attach(dev);
8350 static struct pci_error_handlers bnx2_err_handler = {
8351 .error_detected = bnx2_io_error_detected,
8352 .slot_reset = bnx2_io_slot_reset,
8353 .resume = bnx2_io_resume,
8356 static struct pci_driver bnx2_pci_driver = {
8357 .name = DRV_MODULE_NAME,
8358 .id_table = bnx2_pci_tbl,
8359 .probe = bnx2_init_one,
8360 .remove = __devexit_p(bnx2_remove_one),
8361 .suspend = bnx2_suspend,
8362 .resume = bnx2_resume,
8363 .err_handler = &bnx2_err_handler,
8366 static int __init bnx2_init(void)
8368 return pci_register_driver(&bnx2_pci_driver);
8371 static void __exit bnx2_cleanup(void)
8373 pci_unregister_driver(&bnx2_pci_driver);
8376 module_init(bnx2_init);
8377 module_exit(bnx2_cleanup);