SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #include <linux/if_vlan.h>
  39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50 #include <linux/log2.h>
  51
  52 #include "bnx2.h"
  53 #include "bnx2_fw.h"
  54 #include "bnx2_fw2.h"
  55
  56 #define FW_BUF_SIZE             0x10000
  57
  58 #define DRV_MODULE_NAME         "bnx2"
  59 #define PFX DRV_MODULE_NAME     ": "
  60 #define DRV_MODULE_VERSION      "1.8.0"
  61 #define DRV_MODULE_RELDATE      "Aug 14, 2008"
  62
  63 #define RUN_AT(x) (jiffies + (x))
  64
  65 /* Time in jiffies before concluding the transmitter is hung. */
  66 #define TX_TIMEOUT  (5*HZ)
  67
  68 static char version[] __devinitdata =
  69         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  70
  71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
  73 MODULE_LICENSE("GPL");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 static int disable_msi = 0;
  77
  78 module_param(disable_msi, int, 0);
  79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  80
  81 typedef enum {
  82         BCM5706 = 0,
  83         NC370T,
  84         NC370I,
  85         BCM5706S,
  86         NC370F,
  87         BCM5708,
  88         BCM5708S,
  89         BCM5709,
  90         BCM5709S,
  91         BCM5716,
  92 } board_t;
  93
  94 /* indexed by board_t, above */
  95 static struct {
  96         char *name;
  97 } board_info[] __devinitdata = {
  98         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  99         { "HP NC370T Multifunction Gigabit Server Adapter" },
 100         { "HP NC370i Multifunction Gigabit Server Adapter" },
 101         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 102         { "HP NC370F Multifunction Gigabit Server Adapter" },
 103         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 104         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 105         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 106         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 107         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
 108         };
 109
 110 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
 111         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 112           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 113         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 114           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 116           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 118           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 120           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 121         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 122           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 123         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 124           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 125         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 126           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 127         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 128           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 129         { PCI_VENDOR_ID_BROADCOM, 0x163b,
 130           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 131         { 0, }
 132 };
 133
 134 static struct flash_spec flash_table[] =
 135 {
 136 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 137 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 138         /* Slow EEPROM */
 139         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 140          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 141          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 142          "EEPROM - slow"},
 143         /* Expansion entry 0001 */
 144         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 145          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 146          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 147          "Entry 0001"},
 148         /* Saifun SA25F010 (non-buffered flash) */
 149         /* strap, cfg1, & write1 need updates */
 150         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 151          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 152          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 153          "Non-buffered flash (128kB)"},
 154         /* Saifun SA25F020 (non-buffered flash) */
 155         /* strap, cfg1, & write1 need updates */
 156         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 158          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 159          "Non-buffered flash (256kB)"},
 160         /* Expansion entry 0100 */
 161         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 162          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 163          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 164          "Entry 0100"},
 165         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 166         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 169          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 170         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 171         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 172          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 173          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 174          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 175         /* Saifun SA25F005 (non-buffered flash) */
 176         /* strap, cfg1, & write1 need updates */
 177         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 178          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 179          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 180          "Non-buffered flash (64kB)"},
 181         /* Fast EEPROM */
 182         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 183          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 184          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 185          "EEPROM - fast"},
 186         /* Expansion entry 1001 */
 187         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 190          "Entry 1001"},
 191         /* Expansion entry 1010 */
 192         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 193          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 195          "Entry 1010"},
 196         /* ATMEL AT45DB011B (buffered flash) */
 197         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 198          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 199          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 200          "Buffered flash (128kB)"},
 201         /* Expansion entry 1100 */
 202         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1100"},
 206         /* Expansion entry 1101 */
 207         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 208          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 210          "Entry 1101"},
 211         /* Ateml Expansion entry 1110 */
 212         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 214          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 215          "Entry 1110 (Atmel)"},
 216         /* ATMEL AT45DB021B (buffered flash) */
 217         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 218          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 219          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 220          "Buffered flash (256kB)"},
 221 };
 222
 223 static struct flash_spec flash_5709 = {
 224         .flags          = BNX2_NV_BUFFERED,
 225         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 226         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 227         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 228         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 229         .name           = "5709 Buffered flash (256kB)",
 230 };
 231
 232 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 233
 234 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
 235 {
 236         u32 diff;
 237
 238         smp_mb();
 239
 240         /* The ring uses 256 indices for 255 entries, one of them
 241          * needs to be skipped.
 242          */
 243         diff = txr->tx_prod - txr->tx_cons;
 244         if (unlikely(diff >= TX_DESC_CNT)) {
 245                 diff &= 0xffff;
 246                 if (diff == TX_DESC_CNT)
 247                         diff = MAX_TX_DESC_CNT;
 248         }
 249         return (bp->tx_ring_size - diff);
 250 }
 251
 252 static u32
 253 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 254 {
 255         u32 val;
 256
 257         spin_lock_bh(&bp->indirect_lock);
 258         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 259         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 260         spin_unlock_bh(&bp->indirect_lock);
 261         return val;
 262 }
 263
 264 static void
 265 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 266 {
 267         spin_lock_bh(&bp->indirect_lock);
 268         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 269         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 270         spin_unlock_bh(&bp->indirect_lock);
 271 }
 272
 273 static void
 274 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 275 {
 276         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 277 }
 278
 279 static u32
 280 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 281 {
 282         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 283 }
 284
 285 static void
 286 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 287 {
 288         offset += cid_addr;
 289         spin_lock_bh(&bp->indirect_lock);
 290         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 291                 int i;
 292
 293                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 294                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 295                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 296                 for (i = 0; i < 5; i++) {
 297                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 298                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 299                                 break;
 300                         udelay(5);
 301                 }
 302         } else {
 303                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 304                 REG_WR(bp, BNX2_CTX_DATA, val);
 305         }
 306         spin_unlock_bh(&bp->indirect_lock);
 307 }
 308
 309 static int
 310 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 311 {
 312         u32 val1;
 313         int i, ret;
 314
 315         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 316                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 317                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 318
 319                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 320                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 321
 322                 udelay(40);
 323         }
 324
 325         val1 = (bp->phy_addr << 21) | (reg << 16) |
 326                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 327                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 328         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 329
 330         for (i = 0; i < 50; i++) {
 331                 udelay(10);
 332
 333                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 334                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 335                         udelay(5);
 336
 337                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 338                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 339
 340                         break;
 341                 }
 342         }
 343
 344         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 345                 *val = 0x0;
 346                 ret = -EBUSY;
 347         }
 348         else {
 349                 *val = val1;
 350                 ret = 0;
 351         }
 352
 353         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 354                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 355                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 356
 357                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 358                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 359
 360                 udelay(40);
 361         }
 362
 363         return ret;
 364 }
 365
 366 static int
 367 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 368 {
 369         u32 val1;
 370         int i, ret;
 371
 372         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 373                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 374                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 375
 376                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 377                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 378
 379                 udelay(40);
 380         }
 381
 382         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 383                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 384                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 385         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 386
 387         for (i = 0; i < 50; i++) {
 388                 udelay(10);
 389
 390                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 391                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 392                         udelay(5);
 393                         break;
 394                 }
 395         }
 396
 397         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 398                 ret = -EBUSY;
 399         else
 400                 ret = 0;
 401
 402         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 403                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 404                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 405
 406                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 407                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 408
 409                 udelay(40);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static void
 416 bnx2_disable_int(struct bnx2 *bp)
 417 {
 418         int i;
 419         struct bnx2_napi *bnapi;
 420
 421         for (i = 0; i < bp->irq_nvecs; i++) {
 422                 bnapi = &bp->bnx2_napi[i];
 423                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 424                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 425         }
 426         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 427 }
 428
 429 static void
 430 bnx2_enable_int(struct bnx2 *bp)
 431 {
 432         int i;
 433         struct bnx2_napi *bnapi;
 434
 435         for (i = 0; i < bp->irq_nvecs; i++) {
 436                 bnapi = &bp->bnx2_napi[i];
 437
 438                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 439                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 440                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 441                        bnapi->last_status_idx);
 442
 443                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 444                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 445                        bnapi->last_status_idx);
 446         }
 447         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 448 }
 449
 450 static void
 451 bnx2_disable_int_sync(struct bnx2 *bp)
 452 {
 453         int i;
 454
 455         atomic_inc(&bp->intr_sem);
 456         bnx2_disable_int(bp);
 457         for (i = 0; i < bp->irq_nvecs; i++)
 458                 synchronize_irq(bp->irq_tbl[i].vector);
 459 }
 460
 461 static void
 462 bnx2_napi_disable(struct bnx2 *bp)
 463 {
 464         int i;
 465
 466         for (i = 0; i < bp->irq_nvecs; i++)
 467                 napi_disable(&bp->bnx2_napi[i].napi);
 468 }
 469
 470 static void
 471 bnx2_napi_enable(struct bnx2 *bp)
 472 {
 473         int i;
 474
 475         for (i = 0; i < bp->irq_nvecs; i++)
 476                 napi_enable(&bp->bnx2_napi[i].napi);
 477 }
 478
 479 static void
 480 bnx2_netif_stop(struct bnx2 *bp)
 481 {
 482         bnx2_disable_int_sync(bp);
 483         if (netif_running(bp->dev)) {
 484                 bnx2_napi_disable(bp);
 485                 netif_tx_disable(bp->dev);
 486                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 487         }
 488 }
 489
 490 static void
 491 bnx2_netif_start(struct bnx2 *bp)
 492 {
 493         if (atomic_dec_and_test(&bp->intr_sem)) {
 494                 if (netif_running(bp->dev)) {
 495                         netif_tx_wake_all_queues(bp->dev);
 496                         bnx2_napi_enable(bp);
 497                         bnx2_enable_int(bp);
 498                 }
 499         }
 500 }
 501
 502 static void
 503 bnx2_free_tx_mem(struct bnx2 *bp)
 504 {
 505         int i;
 506
 507         for (i = 0; i < bp->num_tx_rings; i++) {
 508                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 509                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 510
 511                 if (txr->tx_desc_ring) {
 512                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 513                                             txr->tx_desc_ring,
 514                                             txr->tx_desc_mapping);
 515                         txr->tx_desc_ring = NULL;
 516                 }
 517                 kfree(txr->tx_buf_ring);
 518                 txr->tx_buf_ring = NULL;
 519         }
 520 }
 521
 522 static void
 523 bnx2_free_rx_mem(struct bnx2 *bp)
 524 {
 525         int i;
 526
 527         for (i = 0; i < bp->num_rx_rings; i++) {
 528                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 529                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 530                 int j;
 531
 532                 for (j = 0; j < bp->rx_max_ring; j++) {
 533                         if (rxr->rx_desc_ring[j])
 534                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 535                                                     rxr->rx_desc_ring[j],
 536                                                     rxr->rx_desc_mapping[j]);
 537                         rxr->rx_desc_ring[j] = NULL;
 538                 }
 539                 if (rxr->rx_buf_ring)
 540                         vfree(rxr->rx_buf_ring);
 541                 rxr->rx_buf_ring = NULL;
 542
 543                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 544                         if (rxr->rx_pg_desc_ring[j])
 545                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 546                                                     rxr->rx_pg_desc_ring[i],
 547                                                     rxr->rx_pg_desc_mapping[i]);
 548                         rxr->rx_pg_desc_ring[i] = NULL;
 549                 }
 550                 if (rxr->rx_pg_ring)
 551                         vfree(rxr->rx_pg_ring);
 552                 rxr->rx_pg_ring = NULL;
 553         }
 554 }
 555
 556 static int
 557 bnx2_alloc_tx_mem(struct bnx2 *bp)
 558 {
 559         int i;
 560
 561         for (i = 0; i < bp->num_tx_rings; i++) {
 562                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 563                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 564
 565                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 566                 if (txr->tx_buf_ring == NULL)
 567                         return -ENOMEM;
 568
 569                 txr->tx_desc_ring =
 570                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 571                                              &txr->tx_desc_mapping);
 572                 if (txr->tx_desc_ring == NULL)
 573                         return -ENOMEM;
 574         }
 575         return 0;
 576 }
 577
 578 static int
 579 bnx2_alloc_rx_mem(struct bnx2 *bp)
 580 {
 581         int i;
 582
 583         for (i = 0; i < bp->num_rx_rings; i++) {
 584                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 585                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 586                 int j;
 587
 588                 rxr->rx_buf_ring =
 589                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 590                 if (rxr->rx_buf_ring == NULL)
 591                         return -ENOMEM;
 592
 593                 memset(rxr->rx_buf_ring, 0,
 594                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
 595
 596                 for (j = 0; j < bp->rx_max_ring; j++) {
 597                         rxr->rx_desc_ring[j] =
 598                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 599                                                      &rxr->rx_desc_mapping[j]);
 600                         if (rxr->rx_desc_ring[j] == NULL)
 601                                 return -ENOMEM;
 602
 603                 }
 604
 605                 if (bp->rx_pg_ring_size) {
 606                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 607                                                   bp->rx_max_pg_ring);
 608                         if (rxr->rx_pg_ring == NULL)
 609                                 return -ENOMEM;
 610
 611                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 612                                bp->rx_max_pg_ring);
 613                 }
 614
 615                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 616                         rxr->rx_pg_desc_ring[j] =
 617                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 618                                                 &rxr->rx_pg_desc_mapping[j]);
 619                         if (rxr->rx_pg_desc_ring[j] == NULL)
 620                                 return -ENOMEM;
 621
 622                 }
 623         }
 624         return 0;
 625 }
 626
 627 static void
 628 bnx2_free_mem(struct bnx2 *bp)
 629 {
 630         int i;
 631         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 632
 633         bnx2_free_tx_mem(bp);
 634         bnx2_free_rx_mem(bp);
 635
 636         for (i = 0; i < bp->ctx_pages; i++) {
 637                 if (bp->ctx_blk[i]) {
 638                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 639                                             bp->ctx_blk[i],
 640                                             bp->ctx_blk_mapping[i]);
 641                         bp->ctx_blk[i] = NULL;
 642                 }
 643         }
 644         if (bnapi->status_blk.msi) {
 645                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 646                                     bnapi->status_blk.msi,
 647                                     bp->status_blk_mapping);
 648                 bnapi->status_blk.msi = NULL;
 649                 bp->stats_blk = NULL;
 650         }
 651 }
 652
 653 static int
 654 bnx2_alloc_mem(struct bnx2 *bp)
 655 {
 656         int i, status_blk_size, err;
 657         struct bnx2_napi *bnapi;
 658         void *status_blk;
 659
 660         /* Combine status and statistics blocks into one allocation. */
 661         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 662         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 663                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 664                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 665         bp->status_stats_size = status_blk_size +
 666                                 sizeof(struct statistics_block);
 667
 668         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 669                                           &bp->status_blk_mapping);
 670         if (status_blk == NULL)
 671                 goto alloc_mem_err;
 672
 673         memset(status_blk, 0, bp->status_stats_size);
 674
 675         bnapi = &bp->bnx2_napi[0];
 676         bnapi->status_blk.msi = status_blk;
 677         bnapi->hw_tx_cons_ptr =
 678                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
 679         bnapi->hw_rx_cons_ptr =
 680                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
 681         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 682                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 683                         struct status_block_msix *sblk;
 684
 685                         bnapi = &bp->bnx2_napi[i];
 686
 687                         sblk = (void *) (status_blk +
 688                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 689                         bnapi->status_blk.msix = sblk;
 690                         bnapi->hw_tx_cons_ptr =
 691                                 &sblk->status_tx_quick_consumer_index;
 692                         bnapi->hw_rx_cons_ptr =
 693                                 &sblk->status_rx_quick_consumer_index;
 694                         bnapi->int_num = i << 24;
 695                 }
 696         }
 697
 698         bp->stats_blk = status_blk + status_blk_size;
 699
 700         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 701
 702         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 703                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 704                 if (bp->ctx_pages == 0)
 705                         bp->ctx_pages = 1;
 706                 for (i = 0; i < bp->ctx_pages; i++) {
 707                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 708                                                 BCM_PAGE_SIZE,
 709                                                 &bp->ctx_blk_mapping[i]);
 710                         if (bp->ctx_blk[i] == NULL)
 711                                 goto alloc_mem_err;
 712                 }
 713         }
 714
 715         err = bnx2_alloc_rx_mem(bp);
 716         if (err)
 717                 goto alloc_mem_err;
 718
 719         err = bnx2_alloc_tx_mem(bp);
 720         if (err)
 721                 goto alloc_mem_err;
 722
 723         return 0;
 724
 725 alloc_mem_err:
 726         bnx2_free_mem(bp);
 727         return -ENOMEM;
 728 }
 729
 730 static void
 731 bnx2_report_fw_link(struct bnx2 *bp)
 732 {
 733         u32 fw_link_status = 0;
 734
 735         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 736                 return;
 737
 738         if (bp->link_up) {
 739                 u32 bmsr;
 740
 741                 switch (bp->line_speed) {
 742                 case SPEED_10:
 743                         if (bp->duplex == DUPLEX_HALF)
 744                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 745                         else
 746                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 747                         break;
 748                 case SPEED_100:
 749                         if (bp->duplex == DUPLEX_HALF)
 750                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 751                         else
 752                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 753                         break;
 754                 case SPEED_1000:
 755                         if (bp->duplex == DUPLEX_HALF)
 756                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 757                         else
 758                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 759                         break;
 760                 case SPEED_2500:
 761                         if (bp->duplex == DUPLEX_HALF)
 762                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 763                         else
 764                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 765                         break;
 766                 }
 767
 768                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 769
 770                 if (bp->autoneg) {
 771                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 772
 773                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 774                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 775
 776                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 777                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 778                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 779                         else
 780                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 781                 }
 782         }
 783         else
 784                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 785
 786         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 787 }
 788
 789 static char *
 790 bnx2_xceiver_str(struct bnx2 *bp)
 791 {
 792         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 793                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 794                  "Copper"));
 795 }
 796
 797 static void
 798 bnx2_report_link(struct bnx2 *bp)
 799 {
 800         if (bp->link_up) {
 801                 netif_carrier_on(bp->dev);
 802                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 803                        bnx2_xceiver_str(bp));
 804
 805                 printk("%d Mbps ", bp->line_speed);
 806
 807                 if (bp->duplex == DUPLEX_FULL)
 808                         printk("full duplex");
 809                 else
 810                         printk("half duplex");
 811
 812                 if (bp->flow_ctrl) {
 813                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 814                                 printk(", receive ");
 815                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 816                                         printk("& transmit ");
 817                         }
 818                         else {
 819                                 printk(", transmit ");
 820                         }
 821                         printk("flow control ON");
 822                 }
 823                 printk("\n");
 824         }
 825         else {
 826                 netif_carrier_off(bp->dev);
 827                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 828                        bnx2_xceiver_str(bp));
 829         }
 830
 831         bnx2_report_fw_link(bp);
 832 }
 833
 834 static void
 835 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 836 {
 837         u32 local_adv, remote_adv;
 838
 839         bp->flow_ctrl = 0;
 840         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 841                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 842
 843                 if (bp->duplex == DUPLEX_FULL) {
 844                         bp->flow_ctrl = bp->req_flow_ctrl;
 845                 }
 846                 return;
 847         }
 848
 849         if (bp->duplex != DUPLEX_FULL) {
 850                 return;
 851         }
 852
 853         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
 854             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 855                 u32 val;
 856
 857                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 858                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 859                         bp->flow_ctrl |= FLOW_CTRL_TX;
 860                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 861                         bp->flow_ctrl |= FLOW_CTRL_RX;
 862                 return;
 863         }
 864
 865         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 866         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 867
 868         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
 869                 u32 new_local_adv = 0;
 870                 u32 new_remote_adv = 0;
 871
 872                 if (local_adv & ADVERTISE_1000XPAUSE)
 873                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 874                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 875                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 876                 if (remote_adv & ADVERTISE_1000XPAUSE)
 877                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 878                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 879                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 880
 881                 local_adv = new_local_adv;
 882                 remote_adv = new_remote_adv;
 883         }
 884
 885         /* See Table 28B-3 of 802.3ab-1999 spec. */
 886         if (local_adv & ADVERTISE_PAUSE_CAP) {
 887                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 888                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 889                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 890                         }
 891                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 892                                 bp->flow_ctrl = FLOW_CTRL_RX;
 893                         }
 894                 }
 895                 else {
 896                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 897                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 898                         }
 899                 }
 900         }
 901         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 902                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 903                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 904
 905                         bp->flow_ctrl = FLOW_CTRL_TX;
 906                 }
 907         }
 908 }
 909
 910 static int
 911 bnx2_5709s_linkup(struct bnx2 *bp)
 912 {
 913         u32 val, speed;
 914
 915         bp->link_up = 1;
 916
 917         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 918         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 919         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 920
 921         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 922                 bp->line_speed = bp->req_line_speed;
 923                 bp->duplex = bp->req_duplex;
 924                 return 0;
 925         }
 926         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 927         switch (speed) {
 928                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 929                         bp->line_speed = SPEED_10;
 930                         break;
 931                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 932                         bp->line_speed = SPEED_100;
 933                         break;
 934                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 935                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 936                         bp->line_speed = SPEED_1000;
 937                         break;
 938                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 939                         bp->line_speed = SPEED_2500;
 940                         break;
 941         }
 942         if (val & MII_BNX2_GP_TOP_AN_FD)
 943                 bp->duplex = DUPLEX_FULL;
 944         else
 945                 bp->duplex = DUPLEX_HALF;
 946         return 0;
 947 }
 948
 949 static int
 950 bnx2_5708s_linkup(struct bnx2 *bp)
 951 {
 952         u32 val;
 953
 954         bp->link_up = 1;
 955         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 956         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 957                 case BCM5708S_1000X_STAT1_SPEED_10:
 958                         bp->line_speed = SPEED_10;
 959                         break;
 960                 case BCM5708S_1000X_STAT1_SPEED_100:
 961                         bp->line_speed = SPEED_100;
 962                         break;
 963                 case BCM5708S_1000X_STAT1_SPEED_1G:
 964                         bp->line_speed = SPEED_1000;
 965                         break;
 966                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 967                         bp->line_speed = SPEED_2500;
 968                         break;
 969         }
 970         if (val & BCM5708S_1000X_STAT1_FD)
 971                 bp->duplex = DUPLEX_FULL;
 972         else
 973                 bp->duplex = DUPLEX_HALF;
 974
 975         return 0;
 976 }
 977
 978 static int
 979 bnx2_5706s_linkup(struct bnx2 *bp)
 980 {
 981         u32 bmcr, local_adv, remote_adv, common;
 982
 983         bp->link_up = 1;
 984         bp->line_speed = SPEED_1000;
 985
 986         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 987         if (bmcr & BMCR_FULLDPLX) {
 988                 bp->duplex = DUPLEX_FULL;
 989         }
 990         else {
 991                 bp->duplex = DUPLEX_HALF;
 992         }
 993
 994         if (!(bmcr & BMCR_ANENABLE)) {
 995                 return 0;
 996         }
 997
 998         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 999         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1000
1001         common = local_adv & remote_adv;
1002         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1003
1004                 if (common & ADVERTISE_1000XFULL) {
1005                         bp->duplex = DUPLEX_FULL;
1006                 }
1007                 else {
1008                         bp->duplex = DUPLEX_HALF;
1009                 }
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int
1016 bnx2_copper_linkup(struct bnx2 *bp)
1017 {
1018         u32 bmcr;
1019
1020         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1021         if (bmcr & BMCR_ANENABLE) {
1022                 u32 local_adv, remote_adv, common;
1023
1024                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1026
1027                 common = local_adv & (remote_adv >> 2);
1028                 if (common & ADVERTISE_1000FULL) {
1029                         bp->line_speed = SPEED_1000;
1030                         bp->duplex = DUPLEX_FULL;
1031                 }
1032                 else if (common & ADVERTISE_1000HALF) {
1033                         bp->line_speed = SPEED_1000;
1034                         bp->duplex = DUPLEX_HALF;
1035                 }
1036                 else {
1037                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1039
1040                         common = local_adv & remote_adv;
1041                         if (common & ADVERTISE_100FULL) {
1042                                 bp->line_speed = SPEED_100;
1043                                 bp->duplex = DUPLEX_FULL;
1044                         }
1045                         else if (common & ADVERTISE_100HALF) {
1046                                 bp->line_speed = SPEED_100;
1047                                 bp->duplex = DUPLEX_HALF;
1048                         }
1049                         else if (common & ADVERTISE_10FULL) {
1050                                 bp->line_speed = SPEED_10;
1051                                 bp->duplex = DUPLEX_FULL;
1052                         }
1053                         else if (common & ADVERTISE_10HALF) {
1054                                 bp->line_speed = SPEED_10;
1055                                 bp->duplex = DUPLEX_HALF;
1056                         }
1057                         else {
1058                                 bp->line_speed = 0;
1059                                 bp->link_up = 0;
1060                         }
1061                 }
1062         }
1063         else {
1064                 if (bmcr & BMCR_SPEED100) {
1065                         bp->line_speed = SPEED_100;
1066                 }
1067                 else {
1068                         bp->line_speed = SPEED_10;
1069                 }
1070                 if (bmcr & BMCR_FULLDPLX) {
1071                         bp->duplex = DUPLEX_FULL;
1072                 }
1073                 else {
1074                         bp->duplex = DUPLEX_HALF;
1075                 }
1076         }
1077
1078         return 0;
1079 }
1080
1081 static void
1082 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1083 {
1084         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1085
1086         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1088         val |= 0x02 << 8;
1089
1090         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091                 u32 lo_water, hi_water;
1092
1093                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1095                 else
1096                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097                 if (lo_water >= bp->rx_ring_size)
1098                         lo_water = 0;
1099
1100                 hi_water = bp->rx_ring_size / 4;
1101
1102                 if (hi_water <= lo_water)
1103                         lo_water = 0;
1104
1105                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1107
1108                 if (hi_water > 0xf)
1109                         hi_water = 0xf;
1110                 else if (hi_water == 0)
1111                         lo_water = 0;
1112                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1113         }
1114         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1115 }
1116
1117 static void
1118 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1119 {
1120         int i;
1121         u32 cid;
1122
1123         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1124                 if (i == 1)
1125                         cid = RX_RSS_CID;
1126                 bnx2_init_rx_context(bp, cid);
1127         }
1128 }
1129
1130 static void
1131 bnx2_set_mac_link(struct bnx2 *bp)
1132 {
1133         u32 val;
1134
1135         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137                 (bp->duplex == DUPLEX_HALF)) {
1138                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1139         }
1140
1141         /* Configure the EMAC mode register. */
1142         val = REG_RD(bp, BNX2_EMAC_MODE);
1143
1144         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1145                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1146                 BNX2_EMAC_MODE_25G_MODE);
1147
1148         if (bp->link_up) {
1149                 switch (bp->line_speed) {
1150                         case SPEED_10:
1151                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1153                                         break;
1154                                 }
1155                                 /* fall through */
1156                         case SPEED_100:
1157                                 val |= BNX2_EMAC_MODE_PORT_MII;
1158                                 break;
1159                         case SPEED_2500:
1160                                 val |= BNX2_EMAC_MODE_25G_MODE;
1161                                 /* fall through */
1162                         case SPEED_1000:
1163                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1164                                 break;
1165                 }
1166         }
1167         else {
1168                 val |= BNX2_EMAC_MODE_PORT_GMII;
1169         }
1170
1171         /* Set the MAC to operate in the appropriate duplex mode. */
1172         if (bp->duplex == DUPLEX_HALF)
1173                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174         REG_WR(bp, BNX2_EMAC_MODE, val);
1175
1176         /* Enable/disable rx PAUSE. */
1177         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1178
1179         if (bp->flow_ctrl & FLOW_CTRL_RX)
1180                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1182
1183         /* Enable/disable tx PAUSE. */
1184         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1186
1187         if (bp->flow_ctrl & FLOW_CTRL_TX)
1188                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1190
1191         /* Acknowledge the interrupt. */
1192         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1193
1194         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1195                 bnx2_init_all_rx_contexts(bp);
1196 }
1197
1198 static void
1199 bnx2_enable_bmsr1(struct bnx2 *bp)
1200 {
1201         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1202             (CHIP_NUM(bp) == CHIP_NUM_5709))
1203                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1204                                MII_BNX2_BLK_ADDR_GP_STATUS);
1205 }
1206
1207 static void
1208 bnx2_disable_bmsr1(struct bnx2 *bp)
1209 {
1210         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1211             (CHIP_NUM(bp) == CHIP_NUM_5709))
1212                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1214 }
1215
1216 static int
1217 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1218 {
1219         u32 up1;
1220         int ret = 1;
1221
1222         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1223                 return 0;
1224
1225         if (bp->autoneg & AUTONEG_SPEED)
1226                 bp->advertising |= ADVERTISED_2500baseX_Full;
1227
1228         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1229                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1230
1231         bnx2_read_phy(bp, bp->mii_up1, &up1);
1232         if (!(up1 & BCM5708S_UP1_2G5)) {
1233                 up1 |= BCM5708S_UP1_2G5;
1234                 bnx2_write_phy(bp, bp->mii_up1, up1);
1235                 ret = 0;
1236         }
1237
1238         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1239                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1240                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1241
1242         return ret;
1243 }
1244
1245 static int
1246 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1247 {
1248         u32 up1;
1249         int ret = 0;
1250
1251         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1252                 return 0;
1253
1254         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1255                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1256
1257         bnx2_read_phy(bp, bp->mii_up1, &up1);
1258         if (up1 & BCM5708S_UP1_2G5) {
1259                 up1 &= ~BCM5708S_UP1_2G5;
1260                 bnx2_write_phy(bp, bp->mii_up1, up1);
1261                 ret = 1;
1262         }
1263
1264         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1265                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1266                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1267
1268         return ret;
1269 }
1270
1271 static void
1272 bnx2_enable_forced_2g5(struct bnx2 *bp)
1273 {
1274         u32 bmcr;
1275
1276         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1277                 return;
1278
1279         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1280                 u32 val;
1281
1282                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1283                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1284                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1285                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1286                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1287                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1288
1289                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1290                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1291                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1292
1293         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1294                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1295                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1296         }
1297
1298         if (bp->autoneg & AUTONEG_SPEED) {
1299                 bmcr &= ~BMCR_ANENABLE;
1300                 if (bp->req_duplex == DUPLEX_FULL)
1301                         bmcr |= BMCR_FULLDPLX;
1302         }
1303         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1304 }
1305
1306 static void
1307 bnx2_disable_forced_2g5(struct bnx2 *bp)
1308 {
1309         u32 bmcr;
1310
1311         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1312                 return;
1313
1314         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1315                 u32 val;
1316
1317                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1318                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1319                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1320                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1321                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1322
1323                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1324                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1325                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1326
1327         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1328                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1329                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1330         }
1331
1332         if (bp->autoneg & AUTONEG_SPEED)
1333                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1334         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1335 }
1336
1337 static void
1338 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1339 {
1340         u32 val;
1341
1342         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1343         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1344         if (start)
1345                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1346         else
1347                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1348 }
1349
1350 static int
1351 bnx2_set_link(struct bnx2 *bp)
1352 {
1353         u32 bmsr;
1354         u8 link_up;
1355
1356         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1357                 bp->link_up = 1;
1358                 return 0;
1359         }
1360
1361         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1362                 return 0;
1363
1364         link_up = bp->link_up;
1365
1366         bnx2_enable_bmsr1(bp);
1367         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1368         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1369         bnx2_disable_bmsr1(bp);
1370
1371         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1372             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1373                 u32 val, an_dbg;
1374
1375                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1376                         bnx2_5706s_force_link_dn(bp, 0);
1377                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1378                 }
1379                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1380
1381                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1382                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1383                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1384
1385                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1386                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1387                         bmsr |= BMSR_LSTATUS;
1388                 else
1389                         bmsr &= ~BMSR_LSTATUS;
1390         }
1391
1392         if (bmsr & BMSR_LSTATUS) {
1393                 bp->link_up = 1;
1394
1395                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1396                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1397                                 bnx2_5706s_linkup(bp);
1398                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1399                                 bnx2_5708s_linkup(bp);
1400                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1401                                 bnx2_5709s_linkup(bp);
1402                 }
1403                 else {
1404                         bnx2_copper_linkup(bp);
1405                 }
1406                 bnx2_resolve_flow_ctrl(bp);
1407         }
1408         else {
1409                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1410                     (bp->autoneg & AUTONEG_SPEED))
1411                         bnx2_disable_forced_2g5(bp);
1412
1413                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1414                         u32 bmcr;
1415
1416                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1417                         bmcr |= BMCR_ANENABLE;
1418                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1419
1420                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1421                 }
1422                 bp->link_up = 0;
1423         }
1424
1425         if (bp->link_up != link_up) {
1426                 bnx2_report_link(bp);
1427         }
1428
1429         bnx2_set_mac_link(bp);
1430
1431         return 0;
1432 }
1433
1434 static int
1435 bnx2_reset_phy(struct bnx2 *bp)
1436 {
1437         int i;
1438         u32 reg;
1439
1440         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1441
1442 #define PHY_RESET_MAX_WAIT 100
1443         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1444                 udelay(10);
1445
1446                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1447                 if (!(reg & BMCR_RESET)) {
1448                         udelay(20);
1449                         break;
1450                 }
1451         }
1452         if (i == PHY_RESET_MAX_WAIT) {
1453                 return -EBUSY;
1454         }
1455         return 0;
1456 }
1457
1458 static u32
1459 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1460 {
1461         u32 adv = 0;
1462
1463         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1464                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1465
1466                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1467                         adv = ADVERTISE_1000XPAUSE;
1468                 }
1469                 else {
1470                         adv = ADVERTISE_PAUSE_CAP;
1471                 }
1472         }
1473         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1474                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1475                         adv = ADVERTISE_1000XPSE_ASYM;
1476                 }
1477                 else {
1478                         adv = ADVERTISE_PAUSE_ASYM;
1479                 }
1480         }
1481         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1482                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1483                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1484                 }
1485                 else {
1486                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1487                 }
1488         }
1489         return adv;
1490 }
1491
1492 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1493
1494 static int
1495 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1496 {
1497         u32 speed_arg = 0, pause_adv;
1498
1499         pause_adv = bnx2_phy_get_pause_adv(bp);
1500
1501         if (bp->autoneg & AUTONEG_SPEED) {
1502                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1503                 if (bp->advertising & ADVERTISED_10baseT_Half)
1504                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1505                 if (bp->advertising & ADVERTISED_10baseT_Full)
1506                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1507                 if (bp->advertising & ADVERTISED_100baseT_Half)
1508                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1509                 if (bp->advertising & ADVERTISED_100baseT_Full)
1510                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1511                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1512                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1513                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1514                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1515         } else {
1516                 if (bp->req_line_speed == SPEED_2500)
1517                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1518                 else if (bp->req_line_speed == SPEED_1000)
1519                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1520                 else if (bp->req_line_speed == SPEED_100) {
1521                         if (bp->req_duplex == DUPLEX_FULL)
1522                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1523                         else
1524                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1525                 } else if (bp->req_line_speed == SPEED_10) {
1526                         if (bp->req_duplex == DUPLEX_FULL)
1527                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1528                         else
1529                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1530                 }
1531         }
1532
1533         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1534                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1535         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1536                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1537
1538         if (port == PORT_TP)
1539                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1540                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1541
1542         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1543
1544         spin_unlock_bh(&bp->phy_lock);
1545         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1546         spin_lock_bh(&bp->phy_lock);
1547
1548         return 0;
1549 }
1550
1551 static int
1552 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1553 {
1554         u32 adv, bmcr;
1555         u32 new_adv = 0;
1556
1557         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1558                 return (bnx2_setup_remote_phy(bp, port));
1559
1560         if (!(bp->autoneg & AUTONEG_SPEED)) {
1561                 u32 new_bmcr;
1562                 int force_link_down = 0;
1563
1564                 if (bp->req_line_speed == SPEED_2500) {
1565                         if (!bnx2_test_and_enable_2g5(bp))
1566                                 force_link_down = 1;
1567                 } else if (bp->req_line_speed == SPEED_1000) {
1568                         if (bnx2_test_and_disable_2g5(bp))
1569                                 force_link_down = 1;
1570                 }
1571                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1572                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1573
1574                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1575                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1576                 new_bmcr |= BMCR_SPEED1000;
1577
1578                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1579                         if (bp->req_line_speed == SPEED_2500)
1580                                 bnx2_enable_forced_2g5(bp);
1581                         else if (bp->req_line_speed == SPEED_1000) {
1582                                 bnx2_disable_forced_2g5(bp);
1583                                 new_bmcr &= ~0x2000;
1584                         }
1585
1586                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1587                         if (bp->req_line_speed == SPEED_2500)
1588                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1589                         else
1590                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1591                 }
1592
1593                 if (bp->req_duplex == DUPLEX_FULL) {
1594                         adv |= ADVERTISE_1000XFULL;
1595                         new_bmcr |= BMCR_FULLDPLX;
1596                 }
1597                 else {
1598                         adv |= ADVERTISE_1000XHALF;
1599                         new_bmcr &= ~BMCR_FULLDPLX;
1600                 }
1601                 if ((new_bmcr != bmcr) || (force_link_down)) {
1602                         /* Force a link down visible on the other side */
1603                         if (bp->link_up) {
1604                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1605                                                ~(ADVERTISE_1000XFULL |
1606                                                  ADVERTISE_1000XHALF));
1607                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1608                                         BMCR_ANRESTART | BMCR_ANENABLE);
1609
1610                                 bp->link_up = 0;
1611                                 netif_carrier_off(bp->dev);
1612                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1613                                 bnx2_report_link(bp);
1614                         }
1615                         bnx2_write_phy(bp, bp->mii_adv, adv);
1616                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1617                 } else {
1618                         bnx2_resolve_flow_ctrl(bp);
1619                         bnx2_set_mac_link(bp);
1620                 }
1621                 return 0;
1622         }
1623
1624         bnx2_test_and_enable_2g5(bp);
1625
1626         if (bp->advertising & ADVERTISED_1000baseT_Full)
1627                 new_adv |= ADVERTISE_1000XFULL;
1628
1629         new_adv |= bnx2_phy_get_pause_adv(bp);
1630
1631         bnx2_read_phy(bp, bp->mii_adv, &adv);
1632         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1633
1634         bp->serdes_an_pending = 0;
1635         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1636                 /* Force a link down visible on the other side */
1637                 if (bp->link_up) {
1638                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1639                         spin_unlock_bh(&bp->phy_lock);
1640                         msleep(20);
1641                         spin_lock_bh(&bp->phy_lock);
1642                 }
1643
1644                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1645                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1646                         BMCR_ANENABLE);
1647                 /* Speed up link-up time when the link partner
1648                  * does not autonegotiate which is very common
1649                  * in blade servers. Some blade servers use
1650                  * IPMI for kerboard input and it's important
1651                  * to minimize link disruptions. Autoneg. involves
1652                  * exchanging base pages plus 3 next pages and
1653                  * normally completes in about 120 msec.
1654                  */
1655                 bp->current_interval = SERDES_AN_TIMEOUT;
1656                 bp->serdes_an_pending = 1;
1657                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1658         } else {
1659                 bnx2_resolve_flow_ctrl(bp);
1660                 bnx2_set_mac_link(bp);
1661         }
1662
1663         return 0;
1664 }
1665
1666 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1667         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1668                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1669                 (ADVERTISED_1000baseT_Full)
1670
1671 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1672         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1673         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1674         ADVERTISED_1000baseT_Full)
1675
1676 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1677         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1678
1679 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1680
1681 static void
1682 bnx2_set_default_remote_link(struct bnx2 *bp)
1683 {
1684         u32 link;
1685
1686         if (bp->phy_port == PORT_TP)
1687                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1688         else
1689                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1690
1691         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1692                 bp->req_line_speed = 0;
1693                 bp->autoneg |= AUTONEG_SPEED;
1694                 bp->advertising = ADVERTISED_Autoneg;
1695                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1696                         bp->advertising |= ADVERTISED_10baseT_Half;
1697                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1698                         bp->advertising |= ADVERTISED_10baseT_Full;
1699                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1700                         bp->advertising |= ADVERTISED_100baseT_Half;
1701                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1702                         bp->advertising |= ADVERTISED_100baseT_Full;
1703                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1704                         bp->advertising |= ADVERTISED_1000baseT_Full;
1705                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1706                         bp->advertising |= ADVERTISED_2500baseX_Full;
1707         } else {
1708                 bp->autoneg = 0;
1709                 bp->advertising = 0;
1710                 bp->req_duplex = DUPLEX_FULL;
1711                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1712                         bp->req_line_speed = SPEED_10;
1713                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1714                                 bp->req_duplex = DUPLEX_HALF;
1715                 }
1716                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1717                         bp->req_line_speed = SPEED_100;
1718                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1719                                 bp->req_duplex = DUPLEX_HALF;
1720                 }
1721                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1722                         bp->req_line_speed = SPEED_1000;
1723                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1724                         bp->req_line_speed = SPEED_2500;
1725         }
1726 }
1727
1728 static void
1729 bnx2_set_default_link(struct bnx2 *bp)
1730 {
1731         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1732                 bnx2_set_default_remote_link(bp);
1733                 return;
1734         }
1735
1736         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1737         bp->req_line_speed = 0;
1738         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1739                 u32 reg;
1740
1741                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1742
1743                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1744                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1745                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1746                         bp->autoneg = 0;
1747                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1748                         bp->req_duplex = DUPLEX_FULL;
1749                 }
1750         } else
1751                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1752 }
1753
1754 static void
1755 bnx2_send_heart_beat(struct bnx2 *bp)
1756 {
1757         u32 msg;
1758         u32 addr;
1759
1760         spin_lock(&bp->indirect_lock);
1761         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1762         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1763         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1764         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1765         spin_unlock(&bp->indirect_lock);
1766 }
1767
1768 static void
1769 bnx2_remote_phy_event(struct bnx2 *bp)
1770 {
1771         u32 msg;
1772         u8 link_up = bp->link_up;
1773         u8 old_port;
1774
1775         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1776
1777         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1778                 bnx2_send_heart_beat(bp);
1779
1780         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1781
1782         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1783                 bp->link_up = 0;
1784         else {
1785                 u32 speed;
1786
1787                 bp->link_up = 1;
1788                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1789                 bp->duplex = DUPLEX_FULL;
1790                 switch (speed) {
1791                         case BNX2_LINK_STATUS_10HALF:
1792                                 bp->duplex = DUPLEX_HALF;
1793                         case BNX2_LINK_STATUS_10FULL:
1794                                 bp->line_speed = SPEED_10;
1795                                 break;
1796                         case BNX2_LINK_STATUS_100HALF:
1797                                 bp->duplex = DUPLEX_HALF;
1798                         case BNX2_LINK_STATUS_100BASE_T4:
1799                         case BNX2_LINK_STATUS_100FULL:
1800                                 bp->line_speed = SPEED_100;
1801                                 break;
1802                         case BNX2_LINK_STATUS_1000HALF:
1803                                 bp->duplex = DUPLEX_HALF;
1804                         case BNX2_LINK_STATUS_1000FULL:
1805                                 bp->line_speed = SPEED_1000;
1806                                 break;
1807                         case BNX2_LINK_STATUS_2500HALF:
1808                                 bp->duplex = DUPLEX_HALF;
1809                         case BNX2_LINK_STATUS_2500FULL:
1810                                 bp->line_speed = SPEED_2500;
1811                                 break;
1812                         default:
1813                                 bp->line_speed = 0;
1814                                 break;
1815                 }
1816
1817                 bp->flow_ctrl = 0;
1818                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1819                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1820                         if (bp->duplex == DUPLEX_FULL)
1821                                 bp->flow_ctrl = bp->req_flow_ctrl;
1822                 } else {
1823                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1824                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1825                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1826                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1827                 }
1828
1829                 old_port = bp->phy_port;
1830                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1831                         bp->phy_port = PORT_FIBRE;
1832                 else
1833                         bp->phy_port = PORT_TP;
1834
1835                 if (old_port != bp->phy_port)
1836                         bnx2_set_default_link(bp);
1837
1838         }
1839         if (bp->link_up != link_up)
1840                 bnx2_report_link(bp);
1841
1842         bnx2_set_mac_link(bp);
1843 }
1844
1845 static int
1846 bnx2_set_remote_link(struct bnx2 *bp)
1847 {
1848         u32 evt_code;
1849
1850         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1851         switch (evt_code) {
1852                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1853                         bnx2_remote_phy_event(bp);
1854                         break;
1855                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1856                 default:
1857                         bnx2_send_heart_beat(bp);
1858                         break;
1859         }
1860         return 0;
1861 }
1862
1863 static int
1864 bnx2_setup_copper_phy(struct bnx2 *bp)
1865 {
1866         u32 bmcr;
1867         u32 new_bmcr;
1868
1869         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1870
1871         if (bp->autoneg & AUTONEG_SPEED) {
1872                 u32 adv_reg, adv1000_reg;
1873                 u32 new_adv_reg = 0;
1874                 u32 new_adv1000_reg = 0;
1875
1876                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1877                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1878                         ADVERTISE_PAUSE_ASYM);
1879
1880                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1881                 adv1000_reg &= PHY_ALL_1000_SPEED;
1882
1883                 if (bp->advertising & ADVERTISED_10baseT_Half)
1884                         new_adv_reg |= ADVERTISE_10HALF;
1885                 if (bp->advertising & ADVERTISED_10baseT_Full)
1886                         new_adv_reg |= ADVERTISE_10FULL;
1887                 if (bp->advertising & ADVERTISED_100baseT_Half)
1888                         new_adv_reg |= ADVERTISE_100HALF;
1889                 if (bp->advertising & ADVERTISED_100baseT_Full)
1890                         new_adv_reg |= ADVERTISE_100FULL;
1891                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1892                         new_adv1000_reg |= ADVERTISE_1000FULL;
1893
1894                 new_adv_reg |= ADVERTISE_CSMA;
1895
1896                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1897
1898                 if ((adv1000_reg != new_adv1000_reg) ||
1899                         (adv_reg != new_adv_reg) ||
1900                         ((bmcr & BMCR_ANENABLE) == 0)) {
1901
1902                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1903                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1904                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1905                                 BMCR_ANENABLE);
1906                 }
1907                 else if (bp->link_up) {
1908                         /* Flow ctrl may have changed from auto to forced */
1909                         /* or vice-versa. */
1910
1911                         bnx2_resolve_flow_ctrl(bp);
1912                         bnx2_set_mac_link(bp);
1913                 }
1914                 return 0;
1915         }
1916
1917         new_bmcr = 0;
1918         if (bp->req_line_speed == SPEED_100) {
1919                 new_bmcr |= BMCR_SPEED100;
1920         }
1921         if (bp->req_duplex == DUPLEX_FULL) {
1922                 new_bmcr |= BMCR_FULLDPLX;
1923         }
1924         if (new_bmcr != bmcr) {
1925                 u32 bmsr;
1926
1927                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1928                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1929
1930                 if (bmsr & BMSR_LSTATUS) {
1931                         /* Force link down */
1932                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1933                         spin_unlock_bh(&bp->phy_lock);
1934                         msleep(50);
1935                         spin_lock_bh(&bp->phy_lock);
1936
1937                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1939                 }
1940
1941                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1942
1943                 /* Normally, the new speed is setup after the link has
1944                  * gone down and up again. In some cases, link will not go
1945                  * down so we need to set up the new speed here.
1946                  */
1947                 if (bmsr & BMSR_LSTATUS) {
1948                         bp->line_speed = bp->req_line_speed;
1949                         bp->duplex = bp->req_duplex;
1950                         bnx2_resolve_flow_ctrl(bp);
1951                         bnx2_set_mac_link(bp);
1952                 }
1953         } else {
1954                 bnx2_resolve_flow_ctrl(bp);
1955                 bnx2_set_mac_link(bp);
1956         }
1957         return 0;
1958 }
1959
1960 static int
1961 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1962 {
1963         if (bp->loopback == MAC_LOOPBACK)
1964                 return 0;
1965
1966         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1967                 return (bnx2_setup_serdes_phy(bp, port));
1968         }
1969         else {
1970                 return (bnx2_setup_copper_phy(bp));
1971         }
1972 }
1973
1974 static int
1975 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1976 {
1977         u32 val;
1978
1979         bp->mii_bmcr = MII_BMCR + 0x10;
1980         bp->mii_bmsr = MII_BMSR + 0x10;
1981         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1982         bp->mii_adv = MII_ADVERTISE + 0x10;
1983         bp->mii_lpa = MII_LPA + 0x10;
1984         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1985
1986         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1987         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1988
1989         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1990         if (reset_phy)
1991                 bnx2_reset_phy(bp);
1992
1993         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1994
1995         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1996         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1997         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1998         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1999
2000         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2001         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2002         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2003                 val |= BCM5708S_UP1_2G5;
2004         else
2005                 val &= ~BCM5708S_UP1_2G5;
2006         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2007
2008         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2009         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2010         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2011         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2012
2013         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2014
2015         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2016               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2017         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2018
2019         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2020
2021         return 0;
2022 }
2023
2024 static int
2025 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2026 {
2027         u32 val;
2028
2029         if (reset_phy)
2030                 bnx2_reset_phy(bp);
2031
2032         bp->mii_up1 = BCM5708S_UP1;
2033
2034         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2035         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2036         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2037
2038         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2039         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2040         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2041
2042         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2043         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2044         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2045
2046         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2047                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2048                 val |= BCM5708S_UP1_2G5;
2049                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2050         }
2051
2052         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2053             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2054             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2055                 /* increase tx signal amplitude */
2056                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2057                                BCM5708S_BLK_ADDR_TX_MISC);
2058                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2059                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2060                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2061                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2062         }
2063
2064         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2065               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2066
2067         if (val) {
2068                 u32 is_backplane;
2069
2070                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2071                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2072                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2073                                        BCM5708S_BLK_ADDR_TX_MISC);
2074                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2075                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2076                                        BCM5708S_BLK_ADDR_DIG);
2077                 }
2078         }
2079         return 0;
2080 }
2081
2082 static int
2083 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2084 {
2085         if (reset_phy)
2086                 bnx2_reset_phy(bp);
2087
2088         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2089
2090         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2091                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2092
2093         if (bp->dev->mtu > 1500) {
2094                 u32 val;
2095
2096                 /* Set extended packet length bit */
2097                 bnx2_write_phy(bp, 0x18, 0x7);
2098                 bnx2_read_phy(bp, 0x18, &val);
2099                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2100
2101                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2102                 bnx2_read_phy(bp, 0x1c, &val);
2103                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2104         }
2105         else {
2106                 u32 val;
2107
2108                 bnx2_write_phy(bp, 0x18, 0x7);
2109                 bnx2_read_phy(bp, 0x18, &val);
2110                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2111
2112                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2113                 bnx2_read_phy(bp, 0x1c, &val);
2114                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int
2121 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2122 {
2123         u32 val;
2124
2125         if (reset_phy)
2126                 bnx2_reset_phy(bp);
2127
2128         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2129                 bnx2_write_phy(bp, 0x18, 0x0c00);
2130                 bnx2_write_phy(bp, 0x17, 0x000a);
2131                 bnx2_write_phy(bp, 0x15, 0x310b);
2132                 bnx2_write_phy(bp, 0x17, 0x201f);
2133                 bnx2_write_phy(bp, 0x15, 0x9506);
2134                 bnx2_write_phy(bp, 0x17, 0x401f);
2135                 bnx2_write_phy(bp, 0x15, 0x14e2);
2136                 bnx2_write_phy(bp, 0x18, 0x0400);
2137         }
2138
2139         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2140                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2141                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2142                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2143                 val &= ~(1 << 8);
2144                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2145         }
2146
2147         if (bp->dev->mtu > 1500) {
2148                 /* Set extended packet length bit */
2149                 bnx2_write_phy(bp, 0x18, 0x7);
2150                 bnx2_read_phy(bp, 0x18, &val);
2151                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2152
2153                 bnx2_read_phy(bp, 0x10, &val);
2154                 bnx2_write_phy(bp, 0x10, val | 0x1);
2155         }
2156         else {
2157                 bnx2_write_phy(bp, 0x18, 0x7);
2158                 bnx2_read_phy(bp, 0x18, &val);
2159                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2160
2161                 bnx2_read_phy(bp, 0x10, &val);
2162                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2163         }
2164
2165         /* ethernet@wirespeed */
2166         bnx2_write_phy(bp, 0x18, 0x7007);
2167         bnx2_read_phy(bp, 0x18, &val);
2168         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2169         return 0;
2170 }
2171
2172
2173 static int
2174 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2175 {
2176         u32 val;
2177         int rc = 0;
2178
2179         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2180         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2181
2182         bp->mii_bmcr = MII_BMCR;
2183         bp->mii_bmsr = MII_BMSR;
2184         bp->mii_bmsr1 = MII_BMSR;
2185         bp->mii_adv = MII_ADVERTISE;
2186         bp->mii_lpa = MII_LPA;
2187
2188         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2189
2190         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2191                 goto setup_phy;
2192
2193         bnx2_read_phy(bp, MII_PHYSID1, &val);
2194         bp->phy_id = val << 16;
2195         bnx2_read_phy(bp, MII_PHYSID2, &val);
2196         bp->phy_id |= val & 0xffff;
2197
2198         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2199                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2200                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2201                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2202                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2203                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2204                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2205         }
2206         else {
2207                 rc = bnx2_init_copper_phy(bp, reset_phy);
2208         }
2209
2210 setup_phy:
2211         if (!rc)
2212                 rc = bnx2_setup_phy(bp, bp->phy_port);
2213
2214         return rc;
2215 }
2216
2217 static int
2218 bnx2_set_mac_loopback(struct bnx2 *bp)
2219 {
2220         u32 mac_mode;
2221
2222         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2223         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2224         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2225         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2226         bp->link_up = 1;
2227         return 0;
2228 }
2229
2230 static int bnx2_test_link(struct bnx2 *);
2231
2232 static int
2233 bnx2_set_phy_loopback(struct bnx2 *bp)
2234 {
2235         u32 mac_mode;
2236         int rc, i;
2237
2238         spin_lock_bh(&bp->phy_lock);
2239         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2240                             BMCR_SPEED1000);
2241         spin_unlock_bh(&bp->phy_lock);
2242         if (rc)
2243                 return rc;
2244
2245         for (i = 0; i < 10; i++) {
2246                 if (bnx2_test_link(bp) == 0)
2247                         break;
2248                 msleep(100);
2249         }
2250
2251         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2252         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2253                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2254                       BNX2_EMAC_MODE_25G_MODE);
2255
2256         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2257         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2258         bp->link_up = 1;
2259         return 0;
2260 }
2261
2262 static int
2263 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2264 {
2265         int i;
2266         u32 val;
2267
2268         bp->fw_wr_seq++;
2269         msg_data |= bp->fw_wr_seq;
2270
2271         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2272
2273         if (!ack)
2274                 return 0;
2275
2276         /* wait for an acknowledgement. */
2277         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2278                 msleep(10);
2279
2280                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2281
2282                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2283                         break;
2284         }
2285         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2286                 return 0;
2287
2288         /* If we timed out, inform the firmware that this is the case. */
2289         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2290                 if (!silent)
2291                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2292                                             "%x\n", msg_data);
2293
2294                 msg_data &= ~BNX2_DRV_MSG_CODE;
2295                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2296
2297                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2298
2299                 return -EBUSY;
2300         }
2301
2302         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2303                 return -EIO;
2304
2305         return 0;
2306 }
2307
2308 static int
2309 bnx2_init_5709_context(struct bnx2 *bp)
2310 {
2311         int i, ret = 0;
2312         u32 val;
2313
2314         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2315         val |= (BCM_PAGE_BITS - 8) << 16;
2316         REG_WR(bp, BNX2_CTX_COMMAND, val);
2317         for (i = 0; i < 10; i++) {
2318                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2319                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2320                         break;
2321                 udelay(2);
2322         }
2323         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2324                 return -EBUSY;
2325
2326         for (i = 0; i < bp->ctx_pages; i++) {
2327                 int j;
2328
2329                 if (bp->ctx_blk[i])
2330                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2331                 else
2332                         return -ENOMEM;
2333
2334                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2335                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2336                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2337                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2338                        (u64) bp->ctx_blk_mapping[i] >> 32);
2339                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2340                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2341                 for (j = 0; j < 10; j++) {
2342
2343                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2344                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2345                                 break;
2346                         udelay(5);
2347                 }
2348                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2349                         ret = -EBUSY;
2350                         break;
2351                 }
2352         }
2353         return ret;
2354 }
2355
2356 static void
2357 bnx2_init_context(struct bnx2 *bp)
2358 {
2359         u32 vcid;
2360
2361         vcid = 96;
2362         while (vcid) {
2363                 u32 vcid_addr, pcid_addr, offset;
2364                 int i;
2365
2366                 vcid--;
2367
2368                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2369                         u32 new_vcid;
2370
2371                         vcid_addr = GET_PCID_ADDR(vcid);
2372                         if (vcid & 0x8) {
2373                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2374                         }
2375                         else {
2376                                 new_vcid = vcid;
2377                         }
2378                         pcid_addr = GET_PCID_ADDR(new_vcid);
2379                 }
2380                 else {
2381                         vcid_addr = GET_CID_ADDR(vcid);
2382                         pcid_addr = vcid_addr;
2383                 }
2384
2385                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2386                         vcid_addr += (i << PHY_CTX_SHIFT);
2387                         pcid_addr += (i << PHY_CTX_SHIFT);
2388
2389                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2390                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2391
2392                         /* Zero out the context. */
2393                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2394                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2395                 }
2396         }
2397 }
2398
2399 static int
2400 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2401 {
2402         u16 *good_mbuf;
2403         u32 good_mbuf_cnt;
2404         u32 val;
2405
2406         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2407         if (good_mbuf == NULL) {
2408                 printk(KERN_ERR PFX "Failed to allocate memory in "
2409                                     "bnx2_alloc_bad_rbuf\n");
2410                 return -ENOMEM;
2411         }
2412
2413         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2414                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2415
2416         good_mbuf_cnt = 0;
2417
2418         /* Allocate a bunch of mbufs and save the good ones in an array. */
2419         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2420         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2421                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2422                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2423
2424                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2425
2426                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2427
2428                 /* The addresses with Bit 9 set are bad memory blocks. */
2429                 if (!(val & (1 << 9))) {
2430                         good_mbuf[good_mbuf_cnt] = (u16) val;
2431                         good_mbuf_cnt++;
2432                 }
2433
2434                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2435         }
2436
2437         /* Free the good ones back to the mbuf pool thus discarding
2438          * all the bad ones. */
2439         while (good_mbuf_cnt) {
2440                 good_mbuf_cnt--;
2441
2442                 val = good_mbuf[good_mbuf_cnt];
2443                 val = (val << 9) | val | 1;
2444
2445                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2446         }
2447         kfree(good_mbuf);
2448         return 0;
2449 }
2450
2451 static void
2452 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2453 {
2454         u32 val;
2455
2456         val = (mac_addr[0] << 8) | mac_addr[1];
2457
2458         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2459
2460         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2461                 (mac_addr[4] << 8) | mac_addr[5];
2462
2463         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2464 }
2465
2466 static inline int
2467 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2468 {
2469         dma_addr_t mapping;
2470         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2471         struct rx_bd *rxbd =
2472                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2473         struct page *page = alloc_page(GFP_ATOMIC);
2474
2475         if (!page)
2476                 return -ENOMEM;
2477         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2478                                PCI_DMA_FROMDEVICE);
2479         rx_pg->page = page;
2480         pci_unmap_addr_set(rx_pg, mapping, mapping);
2481         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2482         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2483         return 0;
2484 }
2485
2486 static void
2487 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2488 {
2489         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2490         struct page *page = rx_pg->page;
2491
2492         if (!page)
2493                 return;
2494
2495         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2496                        PCI_DMA_FROMDEVICE);
2497
2498         __free_page(page);
2499         rx_pg->page = NULL;
2500 }
2501
2502 static inline int
2503 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2504 {
2505         struct sk_buff *skb;
2506         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2507         dma_addr_t mapping;
2508         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2509         unsigned long align;
2510
2511         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2512         if (skb == NULL) {
2513                 return -ENOMEM;
2514         }
2515
2516         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2517                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2518
2519         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2520                 PCI_DMA_FROMDEVICE);
2521
2522         rx_buf->skb = skb;
2523         pci_unmap_addr_set(rx_buf, mapping, mapping);
2524
2525         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2526         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2527
2528         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2529
2530         return 0;
2531 }
2532
2533 static int
2534 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2535 {
2536         struct status_block *sblk = bnapi->status_blk.msi;
2537         u32 new_link_state, old_link_state;
2538         int is_set = 1;
2539
2540         new_link_state = sblk->status_attn_bits & event;
2541         old_link_state = sblk->status_attn_bits_ack & event;
2542         if (new_link_state != old_link_state) {
2543                 if (new_link_state)
2544                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2545                 else
2546                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2547         } else
2548                 is_set = 0;
2549
2550         return is_set;
2551 }
2552
2553 static void
2554 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2555 {
2556         spin_lock(&bp->phy_lock);
2557
2558         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2559                 bnx2_set_link(bp);
2560         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2561                 bnx2_set_remote_link(bp);
2562
2563         spin_unlock(&bp->phy_lock);
2564
2565 }
2566
2567 static inline u16
2568 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2569 {
2570         u16 cons;
2571
2572         /* Tell compiler that status block fields can change. */
2573         barrier();
2574         cons = *bnapi->hw_tx_cons_ptr;
2575         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2576                 cons++;
2577         return cons;
2578 }
2579
2580 static int
2581 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2582 {
2583         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2584         u16 hw_cons, sw_cons, sw_ring_cons;
2585         int tx_pkt = 0, index;
2586         struct netdev_queue *txq;
2587
2588         index = (bnapi - bp->bnx2_napi);
2589         txq = netdev_get_tx_queue(bp->dev, index);
2590
2591         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2592         sw_cons = txr->tx_cons;
2593
2594         while (sw_cons != hw_cons) {
2595                 struct sw_bd *tx_buf;
2596                 struct sk_buff *skb;
2597                 int i, last;
2598
2599                 sw_ring_cons = TX_RING_IDX(sw_cons);
2600
2601                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2602                 skb = tx_buf->skb;
2603
2604                 /* partial BD completions possible with TSO packets */
2605                 if (skb_is_gso(skb)) {
2606                         u16 last_idx, last_ring_idx;
2607
2608                         last_idx = sw_cons +
2609                                 skb_shinfo(skb)->nr_frags + 1;
2610                         last_ring_idx = sw_ring_cons +
2611                                 skb_shinfo(skb)->nr_frags + 1;
2612                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2613                                 last_idx++;
2614                         }
2615                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2616                                 break;
2617                         }
2618                 }
2619
2620                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2621                         skb_headlen(skb), PCI_DMA_TODEVICE);
2622
2623                 tx_buf->skb = NULL;
2624                 last = skb_shinfo(skb)->nr_frags;
2625
2626                 for (i = 0; i < last; i++) {
2627                         sw_cons = NEXT_TX_BD(sw_cons);
2628
2629                         pci_unmap_page(bp->pdev,
2630                                 pci_unmap_addr(
2631                                         &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2632                                         mapping),
2633                                 skb_shinfo(skb)->frags[i].size,
2634                                 PCI_DMA_TODEVICE);
2635                 }
2636
2637                 sw_cons = NEXT_TX_BD(sw_cons);
2638
2639                 dev_kfree_skb(skb);
2640                 tx_pkt++;
2641                 if (tx_pkt == budget)
2642                         break;
2643
2644                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2645         }
2646
2647         txr->hw_tx_cons = hw_cons;
2648         txr->tx_cons = sw_cons;
2649
2650         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2651          * before checking for netif_tx_queue_stopped().  Without the
2652          * memory barrier, there is a small possibility that bnx2_start_xmit()
2653          * will miss it and cause the queue to be stopped forever.
2654          */
2655         smp_mb();
2656
2657         if (unlikely(netif_tx_queue_stopped(txq)) &&
2658                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2659                 __netif_tx_lock(txq, smp_processor_id());
2660                 if ((netif_tx_queue_stopped(txq)) &&
2661                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2662                         netif_tx_wake_queue(txq);
2663                 __netif_tx_unlock(txq);
2664         }
2665
2666         return tx_pkt;
2667 }
2668
2669 static void
2670 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2671                         struct sk_buff *skb, int count)
2672 {
2673         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2674         struct rx_bd *cons_bd, *prod_bd;
2675         dma_addr_t mapping;
2676         int i;
2677         u16 hw_prod = rxr->rx_pg_prod, prod;
2678         u16 cons = rxr->rx_pg_cons;
2679
2680         for (i = 0; i < count; i++) {
2681                 prod = RX_PG_RING_IDX(hw_prod);
2682
2683                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2684                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2685                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2686                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2687
2688                 if (i == 0 && skb) {
2689                         struct page *page;
2690                         struct skb_shared_info *shinfo;
2691
2692                         shinfo = skb_shinfo(skb);
2693                         shinfo->nr_frags--;
2694                         page = shinfo->frags[shinfo->nr_frags].page;
2695                         shinfo->frags[shinfo->nr_frags].page = NULL;
2696                         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2697                                                PCI_DMA_FROMDEVICE);
2698                         cons_rx_pg->page = page;
2699                         pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2700                         dev_kfree_skb(skb);
2701                 }
2702                 if (prod != cons) {
2703                         prod_rx_pg->page = cons_rx_pg->page;
2704                         cons_rx_pg->page = NULL;
2705                         pci_unmap_addr_set(prod_rx_pg, mapping,
2706                                 pci_unmap_addr(cons_rx_pg, mapping));
2707
2708                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2709                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2710
2711                 }
2712                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2713                 hw_prod = NEXT_RX_BD(hw_prod);
2714         }
2715         rxr->rx_pg_prod = hw_prod;
2716         rxr->rx_pg_cons = cons;
2717 }
2718
2719 static inline void
2720 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2721                   struct sk_buff *skb, u16 cons, u16 prod)
2722 {
2723         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2724         struct rx_bd *cons_bd, *prod_bd;
2725
2726         cons_rx_buf = &rxr->rx_buf_ring[cons];
2727         prod_rx_buf = &rxr->rx_buf_ring[prod];
2728
2729         pci_dma_sync_single_for_device(bp->pdev,
2730                 pci_unmap_addr(cons_rx_buf, mapping),
2731                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2732
2733         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2734
2735         prod_rx_buf->skb = skb;
2736
2737         if (cons == prod)
2738                 return;
2739
2740         pci_unmap_addr_set(prod_rx_buf, mapping,
2741                         pci_unmap_addr(cons_rx_buf, mapping));
2742
2743         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2744         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2745         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2746         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2747 }
2748
2749 static int
2750 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2751             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2752             u32 ring_idx)
2753 {
2754         int err;
2755         u16 prod = ring_idx & 0xffff;
2756
2757         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2758         if (unlikely(err)) {
2759                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2760                 if (hdr_len) {
2761                         unsigned int raw_len = len + 4;
2762                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2763
2764                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2765                 }
2766                 return err;
2767         }
2768
2769         skb_reserve(skb, BNX2_RX_OFFSET);
2770         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2771                          PCI_DMA_FROMDEVICE);
2772
2773         if (hdr_len == 0) {
2774                 skb_put(skb, len);
2775                 return 0;
2776         } else {
2777                 unsigned int i, frag_len, frag_size, pages;
2778                 struct sw_pg *rx_pg;
2779                 u16 pg_cons = rxr->rx_pg_cons;
2780                 u16 pg_prod = rxr->rx_pg_prod;
2781
2782                 frag_size = len + 4 - hdr_len;
2783                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2784                 skb_put(skb, hdr_len);
2785
2786                 for (i = 0; i < pages; i++) {
2787                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2788                         if (unlikely(frag_len <= 4)) {
2789                                 unsigned int tail = 4 - frag_len;
2790
2791                                 rxr->rx_pg_cons = pg_cons;
2792                                 rxr->rx_pg_prod = pg_prod;
2793                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2794                                                         pages - i);
2795                                 skb->len -= tail;
2796                                 if (i == 0) {
2797                                         skb->tail -= tail;
2798                                 } else {
2799                                         skb_frag_t *frag =
2800                                                 &skb_shinfo(skb)->frags[i - 1];
2801                                         frag->size -= tail;
2802                                         skb->data_len -= tail;
2803                                         skb->truesize -= tail;
2804                                 }
2805                                 return 0;
2806                         }
2807                         rx_pg = &rxr->rx_pg_ring[pg_cons];
2808
2809                         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2810                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2811
2812                         if (i == pages - 1)
2813                                 frag_len -= 4;
2814
2815                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2816                         rx_pg->page = NULL;
2817
2818                         err = bnx2_alloc_rx_page(bp, rxr,
2819                                                  RX_PG_RING_IDX(pg_prod));
2820                         if (unlikely(err)) {
2821                                 rxr->rx_pg_cons = pg_cons;
2822                                 rxr->rx_pg_prod = pg_prod;
2823                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2824                                                         pages - i);
2825                                 return err;
2826                         }
2827
2828                         frag_size -= frag_len;
2829                         skb->data_len += frag_len;
2830                         skb->truesize += frag_len;
2831                         skb->len += frag_len;
2832
2833                         pg_prod = NEXT_RX_BD(pg_prod);
2834                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2835                 }
2836                 rxr->rx_pg_prod = pg_prod;
2837                 rxr->rx_pg_cons = pg_cons;
2838         }
2839         return 0;
2840 }
2841
2842 static inline u16
2843 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2844 {
2845         u16 cons;
2846
2847         /* Tell compiler that status block fields can change. */
2848         barrier();
2849         cons = *bnapi->hw_rx_cons_ptr;
2850         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2851                 cons++;
2852         return cons;
2853 }
2854
2855 static int
2856 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2857 {
2858         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2859         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2860         struct l2_fhdr *rx_hdr;
2861         int rx_pkt = 0, pg_ring_used = 0;
2862
2863         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2864         sw_cons = rxr->rx_cons;
2865         sw_prod = rxr->rx_prod;
2866
2867         /* Memory barrier necessary as speculative reads of the rx
2868          * buffer can be ahead of the index in the status block
2869          */
2870         rmb();
2871         while (sw_cons != hw_cons) {
2872                 unsigned int len, hdr_len;
2873                 u32 status;
2874                 struct sw_bd *rx_buf;
2875                 struct sk_buff *skb;
2876                 dma_addr_t dma_addr;
2877                 u16 vtag = 0;
2878                 int hw_vlan __maybe_unused = 0;
2879
2880                 sw_ring_cons = RX_RING_IDX(sw_cons);
2881                 sw_ring_prod = RX_RING_IDX(sw_prod);
2882
2883                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2884                 skb = rx_buf->skb;
2885
2886                 rx_buf->skb = NULL;
2887
2888                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2889
2890                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2891                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2892                         PCI_DMA_FROMDEVICE);
2893
2894                 rx_hdr = (struct l2_fhdr *) skb->data;
2895                 len = rx_hdr->l2_fhdr_pkt_len;
2896
2897                 if ((status = rx_hdr->l2_fhdr_status) &
2898                         (L2_FHDR_ERRORS_BAD_CRC |
2899                         L2_FHDR_ERRORS_PHY_DECODE |
2900                         L2_FHDR_ERRORS_ALIGNMENT |
2901                         L2_FHDR_ERRORS_TOO_SHORT |
2902                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2903
2904                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2905                                           sw_ring_prod);
2906                         goto next_rx;
2907                 }
2908                 hdr_len = 0;
2909                 if (status & L2_FHDR_STATUS_SPLIT) {
2910                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2911                         pg_ring_used = 1;
2912                 } else if (len > bp->rx_jumbo_thresh) {
2913                         hdr_len = bp->rx_jumbo_thresh;
2914                         pg_ring_used = 1;
2915                 }
2916
2917                 len -= 4;
2918
2919                 if (len <= bp->rx_copy_thresh) {
2920                         struct sk_buff *new_skb;
2921
2922                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
2923                         if (new_skb == NULL) {
2924                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2925                                                   sw_ring_prod);
2926                                 goto next_rx;
2927                         }
2928
2929                         /* aligned copy */
2930                         skb_copy_from_linear_data_offset(skb,
2931                                                          BNX2_RX_OFFSET - 6,
2932                                       new_skb->data, len + 6);
2933                         skb_reserve(new_skb, 6);
2934                         skb_put(new_skb, len);
2935
2936                         bnx2_reuse_rx_skb(bp, rxr, skb,
2937                                 sw_ring_cons, sw_ring_prod);
2938
2939                         skb = new_skb;
2940                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2941                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2942                         goto next_rx;
2943
2944                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2945                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2946                         vtag = rx_hdr->l2_fhdr_vlan_tag;
2947 #ifdef BCM_VLAN
2948                         if (bp->vlgrp)
2949                                 hw_vlan = 1;
2950                         else
2951 #endif
2952                         {
2953                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2954                                         __skb_push(skb, 4);
2955
2956                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2957                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
2958                                 ve->h_vlan_TCI = htons(vtag);
2959                                 len += 4;
2960                         }
2961                 }
2962
2963                 skb->protocol = eth_type_trans(skb, bp->dev);
2964
2965                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2966                         (ntohs(skb->protocol) != 0x8100)) {
2967
2968                         dev_kfree_skb(skb);
2969                         goto next_rx;
2970
2971                 }
2972
2973                 skb->ip_summed = CHECKSUM_NONE;
2974                 if (bp->rx_csum &&
2975                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2976                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2977
2978                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2979                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2980                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2981                 }
2982
2983 #ifdef BCM_VLAN
2984                 if (hw_vlan)
2985                         vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
2986                 else
2987 #endif
2988                         netif_receive_skb(skb);
2989
2990                 bp->dev->last_rx = jiffies;
2991                 rx_pkt++;
2992
2993 next_rx:
2994                 sw_cons = NEXT_RX_BD(sw_cons);
2995                 sw_prod = NEXT_RX_BD(sw_prod);
2996
2997                 if ((rx_pkt == budget))
2998                         break;
2999
3000                 /* Refresh hw_cons to see if there is new work */
3001                 if (sw_cons == hw_cons) {
3002                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3003                         rmb();
3004                 }
3005         }
3006         rxr->rx_cons = sw_cons;
3007         rxr->rx_prod = sw_prod;
3008
3009         if (pg_ring_used)
3010                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3011
3012         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3013
3014         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3015
3016         mmiowb();
3017
3018         return rx_pkt;
3019
3020 }
3021
3022 /* MSI ISR - The only difference between this and the INTx ISR
3023  * is that the MSI interrupt is always serviced.
3024  */
3025 static irqreturn_t
3026 bnx2_msi(int irq, void *dev_instance)
3027 {
3028         struct bnx2_napi *bnapi = dev_instance;
3029         struct bnx2 *bp = bnapi->bp;
3030         struct net_device *dev = bp->dev;
3031
3032         prefetch(bnapi->status_blk.msi);
3033         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3034                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3035                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3036
3037         /* Return here if interrupt is disabled. */
3038         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3039                 return IRQ_HANDLED;
3040
3041         netif_rx_schedule(dev, &bnapi->napi);
3042
3043         return IRQ_HANDLED;
3044 }
3045
3046 static irqreturn_t
3047 bnx2_msi_1shot(int irq, void *dev_instance)
3048 {
3049         struct bnx2_napi *bnapi = dev_instance;
3050         struct bnx2 *bp = bnapi->bp;
3051         struct net_device *dev = bp->dev;
3052
3053         prefetch(bnapi->status_blk.msi);
3054
3055         /* Return here if interrupt is disabled. */
3056         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3057                 return IRQ_HANDLED;
3058
3059         netif_rx_schedule(dev, &bnapi->napi);
3060
3061         return IRQ_HANDLED;
3062 }
3063
3064 static irqreturn_t
3065 bnx2_interrupt(int irq, void *dev_instance)
3066 {
3067         struct bnx2_napi *bnapi = dev_instance;
3068         struct bnx2 *bp = bnapi->bp;
3069         struct net_device *dev = bp->dev;
3070         struct status_block *sblk = bnapi->status_blk.msi;
3071
3072         /* When using INTx, it is possible for the interrupt to arrive
3073          * at the CPU before the status block posted prior to the
3074          * interrupt. Reading a register will flush the status block.
3075          * When using MSI, the MSI message will always complete after
3076          * the status block write.
3077          */
3078         if ((sblk->status_idx == bnapi->last_status_idx) &&
3079             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3080              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3081                 return IRQ_NONE;
3082
3083         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3084                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3085                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3086
3087         /* Read back to deassert IRQ immediately to avoid too many
3088          * spurious interrupts.
3089          */
3090         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3091
3092         /* Return here if interrupt is shared and is disabled. */
3093         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3094                 return IRQ_HANDLED;
3095
3096         if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3097                 bnapi->last_status_idx = sblk->status_idx;
3098                 __netif_rx_schedule(dev, &bnapi->napi);
3099         }
3100
3101         return IRQ_HANDLED;
3102 }
3103
3104 static inline int
3105 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3106 {
3107         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3108         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3109
3110         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3111             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3112                 return 1;
3113         return 0;
3114 }
3115
3116 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3117                                  STATUS_ATTN_BITS_TIMER_ABORT)
3118
3119 static inline int
3120 bnx2_has_work(struct bnx2_napi *bnapi)
3121 {
3122         struct status_block *sblk = bnapi->status_blk.msi;
3123
3124         if (bnx2_has_fast_work(bnapi))
3125                 return 1;
3126
3127         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3128             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3129                 return 1;
3130
3131         return 0;
3132 }
3133
3134 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3135 {
3136         struct status_block *sblk = bnapi->status_blk.msi;
3137         u32 status_attn_bits = sblk->status_attn_bits;
3138         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3139
3140         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3141             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3142
3143                 bnx2_phy_int(bp, bnapi);
3144
3145                 /* This is needed to take care of transient status
3146                  * during link changes.
3147                  */
3148                 REG_WR(bp, BNX2_HC_COMMAND,
3149                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3150                 REG_RD(bp, BNX2_HC_COMMAND);
3151         }
3152 }
3153
3154 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3155                           int work_done, int budget)
3156 {
3157         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3158         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3159
3160         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3161                 bnx2_tx_int(bp, bnapi, 0);
3162
3163         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3164                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3165
3166         return work_done;
3167 }
3168
3169 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3170 {
3171         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3172         struct bnx2 *bp = bnapi->bp;
3173         int work_done = 0;
3174         struct status_block_msix *sblk = bnapi->status_blk.msix;
3175
3176         while (1) {
3177                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3178                 if (unlikely(work_done >= budget))
3179                         break;
3180
3181                 bnapi->last_status_idx = sblk->status_idx;
3182                 /* status idx must be read before checking for more work. */
3183                 rmb();
3184                 if (likely(!bnx2_has_fast_work(bnapi))) {
3185
3186                         netif_rx_complete(bp->dev, napi);
3187                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3188                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3189                                bnapi->last_status_idx);
3190                         break;
3191                 }
3192         }
3193         return work_done;
3194 }
3195
3196 static int bnx2_poll(struct napi_struct *napi, int budget)
3197 {
3198         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3199         struct bnx2 *bp = bnapi->bp;
3200         int work_done = 0;
3201         struct status_block *sblk = bnapi->status_blk.msi;
3202
3203         while (1) {
3204                 bnx2_poll_link(bp, bnapi);
3205
3206                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3207
3208                 if (unlikely(work_done >= budget))
3209                         break;
3210
3211                 /* bnapi->last_status_idx is used below to tell the hw how
3212                  * much work has been processed, so we must read it before
3213                  * checking for more work.
3214                  */
3215                 bnapi->last_status_idx = sblk->status_idx;
3216                 rmb();
3217                 if (likely(!bnx2_has_work(bnapi))) {
3218                         netif_rx_complete(bp->dev, napi);
3219                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3220                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3221                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3222                                        bnapi->last_status_idx);
3223                                 break;
3224                         }
3225                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3226                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3227                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3228                                bnapi->last_status_idx);
3229
3230                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3231                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3232                                bnapi->last_status_idx);
3233                         break;
3234                 }
3235         }
3236
3237         return work_done;
3238 }
3239
3240 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3241  * from set_multicast.
3242  */
3243 static void
3244 bnx2_set_rx_mode(struct net_device *dev)
3245 {
3246         struct bnx2 *bp = netdev_priv(dev);
3247         u32 rx_mode, sort_mode;
3248         struct dev_addr_list *uc_ptr;
3249         int i;
3250
3251         if (!netif_running(dev))
3252                 return;
3253
3254         spin_lock_bh(&bp->phy_lock);
3255
3256         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3257                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3258         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3259 #ifdef BCM_VLAN
3260         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3261                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3262 #else
3263         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3264                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3265 #endif
3266         if (dev->flags & IFF_PROMISC) {
3267                 /* Promiscuous mode. */
3268                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3269                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3270                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3271         }
3272         else if (dev->flags & IFF_ALLMULTI) {
3273                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3274                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3275                                0xffffffff);
3276                 }
3277                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3278         }
3279         else {
3280                 /* Accept one or more multicast(s). */
3281                 struct dev_mc_list *mclist;
3282                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3283                 u32 regidx;
3284                 u32 bit;
3285                 u32 crc;
3286
3287                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3288
3289                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3290                      i++, mclist = mclist->next) {
3291
3292                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3293                         bit = crc & 0xff;
3294                         regidx = (bit & 0xe0) >> 5;
3295                         bit &= 0x1f;
3296                         mc_filter[regidx] |= (1 << bit);
3297                 }
3298
3299                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3300                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3301                                mc_filter[i]);
3302                 }
3303
3304                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3305         }
3306
3307         uc_ptr = NULL;
3308         if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3309                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3310                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3311                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3312         } else if (!(dev->flags & IFF_PROMISC)) {
3313                 uc_ptr = dev->uc_list;
3314
3315                 /* Add all entries into to the match filter list */
3316                 for (i = 0; i < dev->uc_count; i++) {
3317                         bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3318                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3319                         sort_mode |= (1 <<
3320                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3321                         uc_ptr = uc_ptr->next;
3322                 }
3323
3324         }
3325
3326         if (rx_mode != bp->rx_mode) {
3327                 bp->rx_mode = rx_mode;
3328                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3329         }
3330
3331         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3332         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3333         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3334
3335         spin_unlock_bh(&bp->phy_lock);
3336 }
3337
3338 static void
3339 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3340         u32 rv2p_proc)
3341 {
3342         int i;
3343         u32 val;
3344
3345         if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3346                 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3347                 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3348                 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3349                 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3350         }
3351
3352         for (i = 0; i < rv2p_code_len; i += 8) {
3353                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3354                 rv2p_code++;
3355                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3356                 rv2p_code++;
3357
3358                 if (rv2p_proc == RV2P_PROC1) {
3359                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3360                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3361                 }
3362                 else {
3363                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3364                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3365                 }
3366         }
3367
3368         /* Reset the processor, un-stall is done later. */
3369         if (rv2p_proc == RV2P_PROC1) {
3370                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3371         }
3372         else {
3373                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3374         }
3375 }
3376
3377 static int
3378 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3379 {
3380         u32 offset;
3381         u32 val;
3382         int rc;
3383
3384         /* Halt the CPU. */
3385         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3386         val |= cpu_reg->mode_value_halt;
3387         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3388         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3389
3390         /* Load the Text area. */
3391         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3392         if (fw->gz_text) {
3393                 int j;
3394
3395                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3396                                        fw->gz_text_len);
3397                 if (rc < 0)
3398                         return rc;
3399
3400                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3401                         bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3402                 }
3403         }
3404
3405         /* Load the Data area. */
3406         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3407         if (fw->data) {
3408                 int j;
3409
3410                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3411                         bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3412                 }
3413         }
3414
3415         /* Load the SBSS area. */
3416         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3417         if (fw->sbss_len) {
3418                 int j;
3419
3420                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3421                         bnx2_reg_wr_ind(bp, offset, 0);
3422                 }
3423         }
3424
3425         /* Load the BSS area. */
3426         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3427         if (fw->bss_len) {
3428                 int j;
3429
3430                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3431                         bnx2_reg_wr_ind(bp, offset, 0);
3432                 }
3433         }
3434
3435         /* Load the Read-Only area. */
3436         offset = cpu_reg->spad_base +
3437                 (fw->rodata_addr - cpu_reg->mips_view_base);
3438         if (fw->rodata) {
3439                 int j;
3440
3441                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3442                         bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3443                 }
3444         }
3445
3446         /* Clear the pre-fetch instruction. */
3447         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3448         bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3449
3450         /* Start the CPU. */
3451         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3452         val &= ~cpu_reg->mode_value_halt;
3453         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3454         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3455
3456         return 0;
3457 }
3458
3459 static int
3460 bnx2_init_cpus(struct bnx2 *bp)
3461 {
3462         struct fw_info *fw;
3463         int rc, rv2p_len;
3464         void *text, *rv2p;
3465
3466         /* Initialize the RV2P processor. */
3467         text = vmalloc(FW_BUF_SIZE);
3468         if (!text)
3469                 return -ENOMEM;
3470         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3471                 rv2p = bnx2_xi_rv2p_proc1;
3472                 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3473         } else {
3474                 rv2p = bnx2_rv2p_proc1;
3475                 rv2p_len = sizeof(bnx2_rv2p_proc1);
3476         }
3477         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3478         if (rc < 0)
3479                 goto init_cpu_err;
3480
3481         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3482
3483         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3484                 rv2p = bnx2_xi_rv2p_proc2;
3485                 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3486         } else {
3487                 rv2p = bnx2_rv2p_proc2;
3488                 rv2p_len = sizeof(bnx2_rv2p_proc2);
3489         }
3490         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3491         if (rc < 0)
3492                 goto init_cpu_err;
3493
3494         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3495
3496         /* Initialize the RX Processor. */
3497         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3498                 fw = &bnx2_rxp_fw_09;
3499         else
3500                 fw = &bnx2_rxp_fw_06;
3501
3502         fw->text = text;
3503         rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3504         if (rc)
3505                 goto init_cpu_err;
3506
3507         /* Initialize the TX Processor. */
3508         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3509                 fw = &bnx2_txp_fw_09;
3510         else
3511                 fw = &bnx2_txp_fw_06;
3512
3513         fw->text = text;
3514         rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3515         if (rc)
3516                 goto init_cpu_err;
3517
3518         /* Initialize the TX Patch-up Processor. */
3519         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3520                 fw = &bnx2_tpat_fw_09;
3521         else
3522                 fw = &bnx2_tpat_fw_06;
3523
3524         fw->text = text;
3525         rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3526         if (rc)
3527                 goto init_cpu_err;
3528
3529         /* Initialize the Completion Processor. */
3530         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3531                 fw = &bnx2_com_fw_09;
3532         else
3533                 fw = &bnx2_com_fw_06;
3534
3535         fw->text = text;
3536         rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3537         if (rc)
3538                 goto init_cpu_err;
3539
3540         /* Initialize the Command Processor. */
3541         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3542                 fw = &bnx2_cp_fw_09;
3543         else
3544                 fw = &bnx2_cp_fw_06;
3545
3546         fw->text = text;
3547         rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3548
3549 init_cpu_err:
3550         vfree(text);
3551         return rc;
3552 }
3553
3554 static int
3555 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3556 {
3557         u16 pmcsr;
3558
3559         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3560
3561         switch (state) {
3562         case PCI_D0: {
3563                 u32 val;
3564
3565                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3566                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3567                         PCI_PM_CTRL_PME_STATUS);
3568
3569                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3570                         /* delay required during transition out of D3hot */
3571                         msleep(20);
3572
3573                 val = REG_RD(bp, BNX2_EMAC_MODE);
3574                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3575                 val &= ~BNX2_EMAC_MODE_MPKT;
3576                 REG_WR(bp, BNX2_EMAC_MODE, val);
3577
3578                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3579                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3580                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3581                 break;
3582         }
3583         case PCI_D3hot: {
3584                 int i;
3585                 u32 val, wol_msg;
3586
3587                 if (bp->wol) {
3588                         u32 advertising;
3589                         u8 autoneg;
3590
3591                         autoneg = bp->autoneg;
3592                         advertising = bp->advertising;
3593
3594                         if (bp->phy_port == PORT_TP) {
3595                                 bp->autoneg = AUTONEG_SPEED;
3596                                 bp->advertising = ADVERTISED_10baseT_Half |
3597                                         ADVERTISED_10baseT_Full |
3598                                         ADVERTISED_100baseT_Half |
3599                                         ADVERTISED_100baseT_Full |
3600                                         ADVERTISED_Autoneg;
3601                         }
3602
3603                         spin_lock_bh(&bp->phy_lock);
3604                         bnx2_setup_phy(bp, bp->phy_port);
3605                         spin_unlock_bh(&bp->phy_lock);
3606
3607                         bp->autoneg = autoneg;
3608                         bp->advertising = advertising;
3609
3610                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3611
3612                         val = REG_RD(bp, BNX2_EMAC_MODE);
3613
3614                         /* Enable port mode. */
3615                         val &= ~BNX2_EMAC_MODE_PORT;
3616                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3617                                BNX2_EMAC_MODE_ACPI_RCVD |
3618                                BNX2_EMAC_MODE_MPKT;
3619                         if (bp->phy_port == PORT_TP)
3620                                 val |= BNX2_EMAC_MODE_PORT_MII;
3621                         else {
3622                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3623                                 if (bp->line_speed == SPEED_2500)
3624                                         val |= BNX2_EMAC_MODE_25G_MODE;
3625                         }
3626
3627                         REG_WR(bp, BNX2_EMAC_MODE, val);
3628
3629                         /* receive all multicast */
3630                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3631                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3632                                        0xffffffff);
3633                         }
3634                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3635                                BNX2_EMAC_RX_MODE_SORT_MODE);
3636
3637                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3638                               BNX2_RPM_SORT_USER0_MC_EN;
3639                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3640                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3641                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3642                                BNX2_RPM_SORT_USER0_ENA);
3643
3644                         /* Need to enable EMAC and RPM for WOL. */
3645                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3646                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3647                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3648                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3649
3650                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3651                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3652                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3653
3654                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3655                 }
3656                 else {
3657                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3658                 }
3659
3660                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3661                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3662                                      1, 0);
3663
3664                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3665                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3666                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3667
3668                         if (bp->wol)
3669                                 pmcsr |= 3;
3670                 }
3671                 else {
3672                         pmcsr |= 3;
3673                 }
3674                 if (bp->wol) {
3675                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3676                 }
3677                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3678                                       pmcsr);
3679
3680                 /* No more memory access after this point until
3681                  * device is brought back to D0.
3682                  */
3683                 udelay(50);
3684                 break;
3685         }
3686         default:
3687                 return -EINVAL;
3688         }
3689         return 0;
3690 }
3691
3692 static int
3693 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3694 {
3695         u32 val;
3696         int j;
3697
3698         /* Request access to the flash interface. */
3699         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3700         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3701                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3702                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3703                         break;
3704
3705                 udelay(5);
3706         }
3707
3708         if (j >= NVRAM_TIMEOUT_COUNT)
3709                 return -EBUSY;
3710
3711         return 0;
3712 }
3713
3714 static int
3715 bnx2_release_nvram_lock(struct bnx2 *bp)
3716 {
3717         int j;
3718         u32 val;
3719
3720         /* Relinquish nvram interface. */
3721         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3722
3723         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3724                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3725                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3726                         break;
3727
3728                 udelay(5);
3729         }
3730
3731         if (j >= NVRAM_TIMEOUT_COUNT)
3732                 return -EBUSY;
3733
3734         return 0;
3735 }
3736
3737
3738 static int
3739 bnx2_enable_nvram_write(struct bnx2 *bp)
3740 {
3741         u32 val;
3742
3743         val = REG_RD(bp, BNX2_MISC_CFG);
3744         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3745
3746         if (bp->flash_info->flags & BNX2_NV_WREN) {
3747                 int j;
3748
3749                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3750                 REG_WR(bp, BNX2_NVM_COMMAND,
3751                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3752
3753                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3754                         udelay(5);
3755
3756                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3757                         if (val & BNX2_NVM_COMMAND_DONE)
3758                                 break;
3759                 }
3760
3761                 if (j >= NVRAM_TIMEOUT_COUNT)
3762                         return -EBUSY;
3763         }
3764         return 0;
3765 }
3766
3767 static void
3768 bnx2_disable_nvram_write(struct bnx2 *bp)
3769 {
3770         u32 val;
3771
3772         val = REG_RD(bp, BNX2_MISC_CFG);
3773         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3774 }
3775
3776
3777 static void
3778 bnx2_enable_nvram_access(struct bnx2 *bp)
3779 {
3780         u32 val;
3781
3782         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3783         /* Enable both bits, even on read. */
3784         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3785                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3786 }
3787
3788 static void
3789 bnx2_disable_nvram_access(struct bnx2 *bp)
3790 {
3791         u32 val;
3792
3793         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3794         /* Disable both bits, even after read. */
3795         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3796                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3797                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3798 }
3799
3800 static int
3801 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3802 {
3803         u32 cmd;
3804         int j;
3805
3806         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3807                 /* Buffered flash, no erase needed */
3808                 return 0;
3809
3810         /* Build an erase command */
3811         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3812               BNX2_NVM_COMMAND_DOIT;
3813
3814         /* Need to clear DONE bit separately. */
3815         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3816
3817         /* Address of the NVRAM to read from. */
3818         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3819
3820         /* Issue an erase command. */
3821         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3822
3823         /* Wait for completion. */
3824         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3825                 u32 val;
3826
3827                 udelay(5);
3828
3829                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3830                 if (val & BNX2_NVM_COMMAND_DONE)
3831                         break;
3832         }
3833
3834         if (j >= NVRAM_TIMEOUT_COUNT)
3835                 return -EBUSY;
3836
3837         return 0;
3838 }
3839
3840 static int
3841 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3842 {
3843         u32 cmd;
3844         int j;
3845
3846         /* Build the command word. */
3847         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3848
3849         /* Calculate an offset of a buffered flash, not needed for 5709. */
3850         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3851                 offset = ((offset / bp->flash_info->page_size) <<
3852                            bp->flash_info->page_bits) +
3853                           (offset % bp->flash_info->page_size);
3854         }
3855
3856         /* Need to clear DONE bit separately. */
3857         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3858
3859         /* Address of the NVRAM to read from. */
3860         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3861
3862         /* Issue a read command. */
3863         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3864
3865         /* Wait for completion. */
3866         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3867                 u32 val;
3868
3869                 udelay(5);
3870
3871                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3872                 if (val & BNX2_NVM_COMMAND_DONE) {
3873                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3874                         memcpy(ret_val, &v, 4);
3875                         break;
3876                 }
3877         }
3878         if (j >= NVRAM_TIMEOUT_COUNT)
3879                 return -EBUSY;
3880
3881         return 0;
3882 }
3883
3884
3885 static int
3886 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3887 {
3888         u32 cmd;
3889         __be32 val32;
3890         int j;
3891
3892         /* Build the command word. */
3893         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3894
3895         /* Calculate an offset of a buffered flash, not needed for 5709. */
3896         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3897                 offset = ((offset / bp->flash_info->page_size) <<
3898                           bp->flash_info->page_bits) +
3899                          (offset % bp->flash_info->page_size);
3900         }
3901
3902         /* Need to clear DONE bit separately. */
3903         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3904
3905         memcpy(&val32, val, 4);
3906
3907         /* Write the data. */
3908         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3909
3910         /* Address of the NVRAM to write to. */
3911         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3912
3913         /* Issue the write command. */
3914         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3915
3916         /* Wait for completion. */
3917         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3918                 udelay(5);
3919
3920                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3921                         break;
3922         }
3923         if (j >= NVRAM_TIMEOUT_COUNT)
3924                 return -EBUSY;
3925
3926         return 0;
3927 }
3928
3929 static int
3930 bnx2_init_nvram(struct bnx2 *bp)
3931 {
3932         u32 val;
3933         int j, entry_count, rc = 0;
3934         struct flash_spec *flash;
3935
3936         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3937                 bp->flash_info = &flash_5709;
3938                 goto get_flash_size;
3939         }
3940
3941         /* Determine the selected interface. */
3942         val = REG_RD(bp, BNX2_NVM_CFG1);
3943
3944         entry_count = ARRAY_SIZE(flash_table);
3945
3946         if (val & 0x40000000) {
3947
3948                 /* Flash interface has been reconfigured */
3949                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3950                      j++, flash++) {
3951                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3952                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3953                                 bp->flash_info = flash;
3954                                 break;
3955                         }
3956                 }
3957         }
3958         else {
3959                 u32 mask;
3960                 /* Not yet been reconfigured */
3961
3962                 if (val & (1 << 23))
3963                         mask = FLASH_BACKUP_STRAP_MASK;
3964                 else
3965                         mask = FLASH_STRAP_MASK;
3966
3967                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3968                         j++, flash++) {
3969
3970                         if ((val & mask) == (flash->strapping & mask)) {
3971                                 bp->flash_info = flash;
3972
3973                                 /* Request access to the flash interface. */
3974                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3975                                         return rc;
3976
3977                                 /* Enable access to flash interface */
3978                                 bnx2_enable_nvram_access(bp);
3979
3980                                 /* Reconfigure the flash interface */
3981                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3982                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3983                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3984                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3985
3986                                 /* Disable access to flash interface */
3987                                 bnx2_disable_nvram_access(bp);
3988                                 bnx2_release_nvram_lock(bp);
3989
3990                                 break;
3991                         }
3992                 }
3993         } /* if (val & 0x40000000) */
3994
3995         if (j == entry_count) {
3996                 bp->flash_info = NULL;
3997                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3998                 return -ENODEV;
3999         }
4000
4001 get_flash_size:
4002         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4003         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4004         if (val)
4005                 bp->flash_size = val;
4006         else
4007                 bp->flash_size = bp->flash_info->total_size;
4008
4009         return rc;
4010 }
4011
4012 static int
4013 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4014                 int buf_size)
4015 {
4016         int rc = 0;
4017         u32 cmd_flags, offset32, len32, extra;
4018
4019         if (buf_size == 0)
4020                 return 0;
4021
4022         /* Request access to the flash interface. */
4023         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4024                 return rc;
4025
4026         /* Enable access to flash interface */
4027         bnx2_enable_nvram_access(bp);
4028
4029         len32 = buf_size;
4030         offset32 = offset;
4031         extra = 0;
4032
4033         cmd_flags = 0;
4034
4035         if (offset32 & 3) {
4036                 u8 buf[4];
4037                 u32 pre_len;
4038
4039                 offset32 &= ~3;
4040                 pre_len = 4 - (offset & 3);
4041
4042                 if (pre_len >= len32) {
4043                         pre_len = len32;
4044                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4045                                     BNX2_NVM_COMMAND_LAST;
4046                 }
4047                 else {
4048                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4049                 }
4050
4051                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4052
4053                 if (rc)
4054                         return rc;
4055
4056                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4057
4058                 offset32 += 4;
4059                 ret_buf += pre_len;
4060                 len32 -= pre_len;
4061         }
4062         if (len32 & 3) {
4063                 extra = 4 - (len32 & 3);
4064                 len32 = (len32 + 4) & ~3;
4065         }
4066
4067         if (len32 == 4) {
4068                 u8 buf[4];
4069
4070                 if (cmd_flags)
4071                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4072                 else
4073                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4074                                     BNX2_NVM_COMMAND_LAST;
4075
4076                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4077
4078                 memcpy(ret_buf, buf, 4 - extra);
4079         }
4080         else if (len32 > 0) {
4081                 u8 buf[4];
4082
4083                 /* Read the first word. */
4084                 if (cmd_flags)
4085                         cmd_flags = 0;
4086                 else
4087                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4088
4089                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4090
4091                 /* Advance to the next dword. */
4092                 offset32 += 4;
4093                 ret_buf += 4;
4094                 len32 -= 4;
4095
4096                 while (len32 > 4 && rc == 0) {
4097                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4098
4099                         /* Advance to the next dword. */
4100                         offset32 += 4;
4101                         ret_buf += 4;
4102                         len32 -= 4;
4103                 }
4104
4105                 if (rc)
4106                         return rc;
4107
4108                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4109                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4110
4111                 memcpy(ret_buf, buf, 4 - extra);
4112         }
4113
4114         /* Disable access to flash interface */
4115         bnx2_disable_nvram_access(bp);
4116
4117         bnx2_release_nvram_lock(bp);
4118
4119         return rc;
4120 }
4121
4122 static int
4123 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4124                 int buf_size)
4125 {
4126         u32 written, offset32, len32;
4127         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4128         int rc = 0;
4129         int align_start, align_end;
4130
4131         buf = data_buf;
4132         offset32 = offset;
4133         len32 = buf_size;
4134         align_start = align_end = 0;
4135
4136         if ((align_start = (offset32 & 3))) {
4137                 offset32 &= ~3;
4138                 len32 += align_start;
4139                 if (len32 < 4)
4140                         len32 = 4;
4141                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4142                         return rc;
4143         }
4144
4145         if (len32 & 3) {
4146                 align_end = 4 - (len32 & 3);
4147                 len32 += align_end;
4148                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4149                         return rc;
4150         }
4151
4152         if (align_start || align_end) {
4153                 align_buf = kmalloc(len32, GFP_KERNEL);
4154                 if (align_buf == NULL)
4155                         return -ENOMEM;
4156                 if (align_start) {
4157                         memcpy(align_buf, start, 4);
4158                 }
4159                 if (align_end) {
4160                         memcpy(align_buf + len32 - 4, end, 4);
4161                 }
4162                 memcpy(align_buf + align_start, data_buf, buf_size);
4163                 buf = align_buf;
4164         }
4165
4166         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4167                 flash_buffer = kmalloc(264, GFP_KERNEL);
4168                 if (flash_buffer == NULL) {
4169                         rc = -ENOMEM;
4170                         goto nvram_write_end;
4171                 }
4172         }
4173
4174         written = 0;
4175         while ((written < len32) && (rc == 0)) {
4176                 u32 page_start, page_end, data_start, data_end;
4177                 u32 addr, cmd_flags;
4178                 int i;
4179
4180                 /* Find the page_start addr */
4181                 page_start = offset32 + written;
4182                 page_start -= (page_start % bp->flash_info->page_size);
4183                 /* Find the page_end addr */
4184                 page_end = page_start + bp->flash_info->page_size;
4185                 /* Find the data_start addr */
4186                 data_start = (written == 0) ? offset32 : page_start;
4187                 /* Find the data_end addr */
4188                 data_end = (page_end > offset32 + len32) ?
4189                         (offset32 + len32) : page_end;
4190
4191                 /* Request access to the flash interface. */
4192                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4193                         goto nvram_write_end;
4194
4195                 /* Enable access to flash interface */
4196                 bnx2_enable_nvram_access(bp);
4197
4198                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4199                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4200                         int j;
4201
4202                         /* Read the whole page into the buffer
4203                          * (non-buffer flash only) */
4204                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4205                                 if (j == (bp->flash_info->page_size - 4)) {
4206                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4207                                 }
4208                                 rc = bnx2_nvram_read_dword(bp,
4209                                         page_start + j,
4210                                         &flash_buffer[j],
4211                                         cmd_flags);
4212
4213                                 if (rc)
4214                                         goto nvram_write_end;
4215
4216                                 cmd_flags = 0;
4217                         }
4218                 }
4219
4220                 /* Enable writes to flash interface (unlock write-protect) */
4221                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4222                         goto nvram_write_end;
4223
4224                 /* Loop to write back the buffer data from page_start to
4225                  * data_start */
4226                 i = 0;
4227                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4228                         /* Erase the page */
4229                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4230                                 goto nvram_write_end;
4231
4232                         /* Re-enable the write again for the actual write */
4233                         bnx2_enable_nvram_write(bp);
4234
4235                         for (addr = page_start; addr < data_start;
4236                                 addr += 4, i += 4) {
4237
4238                                 rc = bnx2_nvram_write_dword(bp, addr,
4239                                         &flash_buffer[i], cmd_flags);
4240
4241                                 if (rc != 0)
4242                                         goto nvram_write_end;
4243
4244                                 cmd_flags = 0;
4245                         }
4246                 }
4247
4248                 /* Loop to write the new data from data_start to data_end */
4249                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4250                         if ((addr == page_end - 4) ||
4251                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4252                                  (addr == data_end - 4))) {
4253
4254                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4255                         }
4256                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4257                                 cmd_flags);
4258
4259                         if (rc != 0)
4260                                 goto nvram_write_end;
4261
4262                         cmd_flags = 0;
4263                         buf += 4;
4264                 }
4265
4266                 /* Loop to write back the buffer data from data_end
4267                  * to page_end */
4268                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4269                         for (addr = data_end; addr < page_end;
4270                                 addr += 4, i += 4) {
4271
4272                                 if (addr == page_end-4) {
4273                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4274                                 }
4275                                 rc = bnx2_nvram_write_dword(bp, addr,
4276                                         &flash_buffer[i], cmd_flags);
4277
4278                                 if (rc != 0)
4279                                         goto nvram_write_end;
4280
4281                                 cmd_flags = 0;
4282                         }
4283                 }
4284
4285                 /* Disable writes to flash interface (lock write-protect) */
4286                 bnx2_disable_nvram_write(bp);
4287
4288                 /* Disable access to flash interface */
4289                 bnx2_disable_nvram_access(bp);
4290                 bnx2_release_nvram_lock(bp);
4291
4292                 /* Increment written */
4293                 written += data_end - data_start;
4294         }
4295
4296 nvram_write_end:
4297         kfree(flash_buffer);
4298         kfree(align_buf);
4299         return rc;
4300 }
4301
4302 static void
4303 bnx2_init_fw_cap(struct bnx2 *bp)
4304 {
4305         u32 val, sig = 0;
4306
4307         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4308         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4309
4310         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4311                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4312
4313         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4314         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4315                 return;
4316
4317         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4318                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4319                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4320         }
4321
4322         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4323             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4324                 u32 link;
4325
4326                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4327
4328                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4329                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4330                         bp->phy_port = PORT_FIBRE;
4331                 else
4332                         bp->phy_port = PORT_TP;
4333
4334                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4335                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4336         }
4337
4338         if (netif_running(bp->dev) && sig)
4339                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4340 }
4341
4342 static void
4343 bnx2_setup_msix_tbl(struct bnx2 *bp)
4344 {
4345         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4346
4347         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4348         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4349 }
4350
4351 static int
4352 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4353 {
4354         u32 val;
4355         int i, rc = 0;
4356         u8 old_port;
4357
4358         /* Wait for the current PCI transaction to complete before
4359          * issuing a reset. */
4360         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4361                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4362                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4363                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4364                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4365         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4366         udelay(5);
4367
4368         /* Wait for the firmware to tell us it is ok to issue a reset. */
4369         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4370
4371         /* Deposit a driver reset signature so the firmware knows that
4372          * this is a soft reset. */
4373         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4374                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4375
4376         /* Do a dummy read to force the chip to complete all current transaction
4377          * before we issue a reset. */
4378         val = REG_RD(bp, BNX2_MISC_ID);
4379
4380         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4381                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4382                 REG_RD(bp, BNX2_MISC_COMMAND);
4383                 udelay(5);
4384
4385                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4386                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4387
4388                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4389
4390         } else {
4391                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4392                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4393                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4394
4395                 /* Chip reset. */
4396                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4397
4398                 /* Reading back any register after chip reset will hang the
4399                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4400                  * of margin for write posting.
4401                  */
4402                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4403                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4404                         msleep(20);
4405
4406                 /* Reset takes approximate 30 usec */
4407                 for (i = 0; i < 10; i++) {
4408                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4409                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4410                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4411                                 break;
4412                         udelay(10);
4413                 }
4414
4415                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4416                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4417                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4418                         return -EBUSY;
4419                 }
4420         }
4421
4422         /* Make sure byte swapping is properly configured. */
4423         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4424         if (val != 0x01020304) {
4425                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4426                 return -ENODEV;
4427         }
4428
4429         /* Wait for the firmware to finish its initialization. */
4430         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4431         if (rc)
4432                 return rc;
4433
4434         spin_lock_bh(&bp->phy_lock);
4435         old_port = bp->phy_port;
4436         bnx2_init_fw_cap(bp);
4437         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4438             old_port != bp->phy_port)
4439                 bnx2_set_default_remote_link(bp);
4440         spin_unlock_bh(&bp->phy_lock);
4441
4442         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4443                 /* Adjust the voltage regular to two steps lower.  The default
4444                  * of this register is 0x0000000e. */
4445                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4446
4447                 /* Remove bad rbuf memory from the free pool. */
4448                 rc = bnx2_alloc_bad_rbuf(bp);
4449         }
4450
4451         if (bp->flags & BNX2_FLAG_USING_MSIX)
4452                 bnx2_setup_msix_tbl(bp);
4453
4454         return rc;
4455 }
4456
4457 static int
4458 bnx2_init_chip(struct bnx2 *bp)
4459 {
4460         u32 val;
4461         int rc, i;
4462
4463         /* Make sure the interrupt is not active. */
4464         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4465
4466         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4467               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4468 #ifdef __BIG_ENDIAN
4469               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4470 #endif
4471               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4472               DMA_READ_CHANS << 12 |
4473               DMA_WRITE_CHANS << 16;
4474
4475         val |= (0x2 << 20) | (1 << 11);
4476
4477         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4478                 val |= (1 << 23);
4479
4480         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4481             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4482                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4483
4484         REG_WR(bp, BNX2_DMA_CONFIG, val);
4485
4486         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4487                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4488                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4489                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4490         }
4491
4492         if (bp->flags & BNX2_FLAG_PCIX) {
4493                 u16 val16;
4494
4495                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4496                                      &val16);
4497                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4498                                       val16 & ~PCI_X_CMD_ERO);
4499         }
4500
4501         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4502                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4503                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4504                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4505
4506         /* Initialize context mapping and zero out the quick contexts.  The
4507          * context block must have already been enabled. */
4508         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4509                 rc = bnx2_init_5709_context(bp);
4510                 if (rc)
4511                         return rc;
4512         } else
4513                 bnx2_init_context(bp);
4514
4515         if ((rc = bnx2_init_cpus(bp)) != 0)
4516                 return rc;
4517
4518         bnx2_init_nvram(bp);
4519
4520         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4521
4522         val = REG_RD(bp, BNX2_MQ_CONFIG);
4523         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4524         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4525         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4526                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4527
4528         REG_WR(bp, BNX2_MQ_CONFIG, val);
4529
4530         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4531         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4532         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4533
4534         val = (BCM_PAGE_BITS - 8) << 24;
4535         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4536
4537         /* Configure page size. */
4538         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4539         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4540         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4541         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4542
4543         val = bp->mac_addr[0] +
4544               (bp->mac_addr[1] << 8) +
4545               (bp->mac_addr[2] << 16) +
4546               bp->mac_addr[3] +
4547               (bp->mac_addr[4] << 8) +
4548               (bp->mac_addr[5] << 16);
4549         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4550
4551         /* Program the MTU.  Also include 4 bytes for CRC32. */
4552         val = bp->dev->mtu + ETH_HLEN + 4;
4553         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4554                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4555         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4556
4557         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4558                 bp->bnx2_napi[i].last_status_idx = 0;
4559
4560         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4561
4562         /* Set up how to generate a link change interrupt. */
4563         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4564
4565         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4566                (u64) bp->status_blk_mapping & 0xffffffff);
4567         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4568
4569         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4570                (u64) bp->stats_blk_mapping & 0xffffffff);
4571         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4572                (u64) bp->stats_blk_mapping >> 32);
4573
4574         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4575                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4576
4577         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4578                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4579
4580         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4581                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4582
4583         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4584
4585         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4586
4587         REG_WR(bp, BNX2_HC_COM_TICKS,
4588                (bp->com_ticks_int << 16) | bp->com_ticks);
4589
4590         REG_WR(bp, BNX2_HC_CMD_TICKS,
4591                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4592
4593         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4594                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4595         else
4596                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4597         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4598
4599         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4600                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4601         else {
4602                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4603                       BNX2_HC_CONFIG_COLLECT_STATS;
4604         }
4605
4606         if (bp->irq_nvecs > 1) {
4607                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4608                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4609
4610                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4611         }
4612
4613         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4614                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4615
4616         REG_WR(bp, BNX2_HC_CONFIG, val);
4617
4618         for (i = 1; i < bp->irq_nvecs; i++) {
4619                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4620                            BNX2_HC_SB_CONFIG_1;
4621
4622                 REG_WR(bp, base,
4623                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4624                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4625                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4626
4627                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4628                         (bp->tx_quick_cons_trip_int << 16) |
4629                          bp->tx_quick_cons_trip);
4630
4631                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4632                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4633
4634                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4635                        (bp->rx_quick_cons_trip_int << 16) |
4636                         bp->rx_quick_cons_trip);
4637
4638                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4639                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4640         }
4641
4642         /* Clear internal stats counters. */
4643         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4644
4645         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4646
4647         /* Initialize the receive filter. */
4648         bnx2_set_rx_mode(bp->dev);
4649
4650         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4651                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4652                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4653                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4654         }
4655         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4656                           1, 0);
4657
4658         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4659         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4660
4661         udelay(20);
4662
4663         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4664
4665         return rc;
4666 }
4667
4668 static void
4669 bnx2_clear_ring_states(struct bnx2 *bp)
4670 {
4671         struct bnx2_napi *bnapi;
4672         struct bnx2_tx_ring_info *txr;
4673         struct bnx2_rx_ring_info *rxr;
4674         int i;
4675
4676         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4677                 bnapi = &bp->bnx2_napi[i];
4678                 txr = &bnapi->tx_ring;
4679                 rxr = &bnapi->rx_ring;
4680
4681                 txr->tx_cons = 0;
4682                 txr->hw_tx_cons = 0;
4683                 rxr->rx_prod_bseq = 0;
4684                 rxr->rx_prod = 0;
4685                 rxr->rx_cons = 0;
4686                 rxr->rx_pg_prod = 0;
4687                 rxr->rx_pg_cons = 0;
4688         }
4689 }
4690
4691 static void
4692 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4693 {
4694         u32 val, offset0, offset1, offset2, offset3;
4695         u32 cid_addr = GET_CID_ADDR(cid);
4696
4697         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4698                 offset0 = BNX2_L2CTX_TYPE_XI;
4699                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4700                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4701                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4702         } else {
4703                 offset0 = BNX2_L2CTX_TYPE;
4704                 offset1 = BNX2_L2CTX_CMD_TYPE;
4705                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4706                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4707         }
4708         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4709         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4710
4711         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4712         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4713
4714         val = (u64) txr->tx_desc_mapping >> 32;
4715         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4716
4717         val = (u64) txr->tx_desc_mapping & 0xffffffff;
4718         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4719 }
4720
4721 static void
4722 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4723 {
4724         struct tx_bd *txbd;
4725         u32 cid = TX_CID;
4726         struct bnx2_napi *bnapi;
4727         struct bnx2_tx_ring_info *txr;
4728
4729         bnapi = &bp->bnx2_napi[ring_num];
4730         txr = &bnapi->tx_ring;
4731
4732         if (ring_num == 0)
4733                 cid = TX_CID;
4734         else
4735                 cid = TX_TSS_CID + ring_num - 1;
4736
4737         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4738
4739         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4740
4741         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4742         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4743
4744         txr->tx_prod = 0;
4745         txr->tx_prod_bseq = 0;
4746
4747         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4748         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4749
4750         bnx2_init_tx_context(bp, cid, txr);
4751 }
4752
4753 static void
4754 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4755                      int num_rings)
4756 {
4757         int i;
4758         struct rx_bd *rxbd;
4759
4760         for (i = 0; i < num_rings; i++) {
4761                 int j;
4762
4763                 rxbd = &rx_ring[i][0];
4764                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4765                         rxbd->rx_bd_len = buf_size;
4766                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4767                 }
4768                 if (i == (num_rings - 1))
4769                         j = 0;
4770                 else
4771                         j = i + 1;
4772                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4773                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4774         }
4775 }
4776
4777 static void
4778 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4779 {
4780         int i;
4781         u16 prod, ring_prod;
4782         u32 cid, rx_cid_addr, val;
4783         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4784         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4785
4786         if (ring_num == 0)
4787                 cid = RX_CID;
4788         else
4789                 cid = RX_RSS_CID + ring_num - 1;
4790
4791         rx_cid_addr = GET_CID_ADDR(cid);
4792
4793         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4794                              bp->rx_buf_use_size, bp->rx_max_ring);
4795
4796         bnx2_init_rx_context(bp, cid);
4797
4798         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4799                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4800                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4801         }
4802
4803         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4804         if (bp->rx_pg_ring_size) {
4805                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4806                                      rxr->rx_pg_desc_mapping,
4807                                      PAGE_SIZE, bp->rx_max_pg_ring);
4808                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4809                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4810                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4811                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4812
4813                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4814                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4815
4816                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4817                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4818
4819                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4820                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4821         }
4822
4823         val = (u64) rxr->rx_desc_mapping[0] >> 32;
4824         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4825
4826         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4827         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4828
4829         ring_prod = prod = rxr->rx_pg_prod;
4830         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4831                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4832                         break;
4833                 prod = NEXT_RX_BD(prod);
4834                 ring_prod = RX_PG_RING_IDX(prod);
4835         }
4836         rxr->rx_pg_prod = prod;
4837
4838         ring_prod = prod = rxr->rx_prod;
4839         for (i = 0; i < bp->rx_ring_size; i++) {
4840                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4841                         break;
4842                 prod = NEXT_RX_BD(prod);
4843                 ring_prod = RX_RING_IDX(prod);
4844         }
4845         rxr->rx_prod = prod;
4846
4847         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4848         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4849         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4850
4851         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4852         REG_WR16(bp, rxr->rx_bidx_addr, prod);
4853
4854         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4855 }
4856
4857 static void
4858 bnx2_init_all_rings(struct bnx2 *bp)
4859 {
4860         int i;
4861         u32 val;
4862
4863         bnx2_clear_ring_states(bp);
4864
4865         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4866         for (i = 0; i < bp->num_tx_rings; i++)
4867                 bnx2_init_tx_ring(bp, i);
4868
4869         if (bp->num_tx_rings > 1)
4870                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4871                        (TX_TSS_CID << 7));
4872
4873         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4874         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4875
4876         for (i = 0; i < bp->num_rx_rings; i++)
4877                 bnx2_init_rx_ring(bp, i);
4878
4879         if (bp->num_rx_rings > 1) {
4880                 u32 tbl_32;
4881                 u8 *tbl = (u8 *) &tbl_32;
4882
4883                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4884                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4885
4886                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4887                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
4888                         if ((i % 4) == 3)
4889                                 bnx2_reg_wr_ind(bp,
4890                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
4891                                                 cpu_to_be32(tbl_32));
4892                 }
4893
4894                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4895                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4896
4897                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4898
4899         }
4900 }
4901
4902 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4903 {
4904         u32 max, num_rings = 1;
4905
4906         while (ring_size > MAX_RX_DESC_CNT) {
4907                 ring_size -= MAX_RX_DESC_CNT;
4908                 num_rings++;
4909         }
4910         /* round to next power of 2 */
4911         max = max_size;
4912         while ((max & num_rings) == 0)
4913                 max >>= 1;
4914
4915         if (num_rings != max)
4916                 max <<= 1;
4917
4918         return max;
4919 }
4920
4921 static void
4922 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4923 {
4924         u32 rx_size, rx_space, jumbo_size;
4925
4926         /* 8 for CRC and VLAN */
4927         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4928
4929         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4930                 sizeof(struct skb_shared_info);
4931
4932         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4933         bp->rx_pg_ring_size = 0;
4934         bp->rx_max_pg_ring = 0;
4935         bp->rx_max_pg_ring_idx = 0;
4936         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4937                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4938
4939                 jumbo_size = size * pages;
4940                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4941                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4942
4943                 bp->rx_pg_ring_size = jumbo_size;
4944                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4945                                                         MAX_RX_PG_RINGS);
4946                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4947                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4948                 bp->rx_copy_thresh = 0;
4949         }
4950
4951         bp->rx_buf_use_size = rx_size;
4952         /* hw alignment */
4953         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4954         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4955         bp->rx_ring_size = size;
4956         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4957         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4958 }
4959
4960 static void
4961 bnx2_free_tx_skbs(struct bnx2 *bp)
4962 {
4963         int i;
4964
4965         for (i = 0; i < bp->num_tx_rings; i++) {
4966                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4967                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4968                 int j;
4969
4970                 if (txr->tx_buf_ring == NULL)
4971                         continue;
4972
4973                 for (j = 0; j < TX_DESC_CNT; ) {
4974                         struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
4975                         struct sk_buff *skb = tx_buf->skb;
4976                         int k, last;
4977
4978                         if (skb == NULL) {
4979                                 j++;
4980                                 continue;
4981                         }
4982
4983                         pci_unmap_single(bp->pdev,
4984                                          pci_unmap_addr(tx_buf, mapping),
4985                         skb_headlen(skb), PCI_DMA_TODEVICE);
4986
4987                         tx_buf->skb = NULL;
4988
4989                         last = skb_shinfo(skb)->nr_frags;
4990                         for (k = 0; k < last; k++) {
4991                                 tx_buf = &txr->tx_buf_ring[j + k + 1];
4992                                 pci_unmap_page(bp->pdev,
4993                                         pci_unmap_addr(tx_buf, mapping),
4994                                         skb_shinfo(skb)->frags[j].size,
4995                                         PCI_DMA_TODEVICE);
4996                         }
4997                         dev_kfree_skb(skb);
4998                         j += k + 1;
4999                 }
5000         }
5001 }
5002
5003 static void
5004 bnx2_free_rx_skbs(struct bnx2 *bp)
5005 {
5006         int i;
5007
5008         for (i = 0; i < bp->num_rx_rings; i++) {
5009                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5010                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5011                 int j;
5012
5013                 if (rxr->rx_buf_ring == NULL)
5014                         return;
5015
5016                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5017                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5018                         struct sk_buff *skb = rx_buf->skb;
5019
5020                         if (skb == NULL)
5021                                 continue;
5022
5023                         pci_unmap_single(bp->pdev,
5024                                          pci_unmap_addr(rx_buf, mapping),
5025                                          bp->rx_buf_use_size,
5026                                          PCI_DMA_FROMDEVICE);
5027
5028                         rx_buf->skb = NULL;
5029
5030                         dev_kfree_skb(skb);
5031                 }
5032                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5033                         bnx2_free_rx_page(bp, rxr, j);
5034         }
5035 }
5036
5037 static void
5038 bnx2_free_skbs(struct bnx2 *bp)
5039 {
5040         bnx2_free_tx_skbs(bp);
5041         bnx2_free_rx_skbs(bp);
5042 }
5043
5044 static int
5045 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5046 {
5047         int rc;
5048
5049         rc = bnx2_reset_chip(bp, reset_code);
5050         bnx2_free_skbs(bp);
5051         if (rc)
5052                 return rc;
5053
5054         if ((rc = bnx2_init_chip(bp)) != 0)
5055                 return rc;
5056
5057         bnx2_init_all_rings(bp);
5058         return 0;
5059 }
5060
5061 static int
5062 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5063 {
5064         int rc;
5065
5066         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5067                 return rc;
5068
5069         spin_lock_bh(&bp->phy_lock);
5070         bnx2_init_phy(bp, reset_phy);
5071         bnx2_set_link(bp);
5072         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5073                 bnx2_remote_phy_event(bp);
5074         spin_unlock_bh(&bp->phy_lock);
5075         return 0;
5076 }
5077
5078 static int
5079 bnx2_shutdown_chip(struct bnx2 *bp)
5080 {
5081         u32 reset_code;
5082
5083         if (bp->flags & BNX2_FLAG_NO_WOL)
5084                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5085         else if (bp->wol)
5086                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5087         else
5088                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5089
5090         return bnx2_reset_chip(bp, reset_code);
5091 }
5092
5093 static int
5094 bnx2_test_registers(struct bnx2 *bp)
5095 {
5096         int ret;
5097         int i, is_5709;
5098         static const struct {
5099                 u16   offset;
5100                 u16   flags;
5101 #define BNX2_FL_NOT_5709        1
5102                 u32   rw_mask;
5103                 u32   ro_mask;
5104         } reg_tbl[] = {
5105                 { 0x006c, 0, 0x00000000, 0x0000003f },
5106                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5107                 { 0x0094, 0, 0x00000000, 0x00000000 },
5108
5109                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5110                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5111                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5112                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5113                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5114                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5115                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5116                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5117                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5118
5119                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5120                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5121                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5122                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5123                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5124                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5125
5126                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5127                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5128                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5129
5130                 { 0x1000, 0, 0x00000000, 0x00000001 },
5131                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5132
5133                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5134                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5135                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5136                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5137                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5138                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5139                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5140                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5141                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5142                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5143
5144                 { 0x1800, 0, 0x00000000, 0x00000001 },
5145                 { 0x1804, 0, 0x00000000, 0x00000003 },
5146
5147                 { 0x2800, 0, 0x00000000, 0x00000001 },
5148                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5149                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5150                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5151                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5152                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5153                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5154                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5155                 { 0x2840, 0, 0x00000000, 0xffffffff },
5156                 { 0x2844, 0, 0x00000000, 0xffffffff },
5157                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5158                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5159
5160                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5161                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5162
5163                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5164                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5165                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5166                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5167                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5168                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5169                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5170                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5171                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5172
5173                 { 0x5004, 0, 0x00000000, 0x0000007f },
5174                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5175
5176                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5177                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5178                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5179                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5180                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5181                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5182                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5183                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5184                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5185
5186                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5187                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5188                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5189                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5190                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5191                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5192                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5193                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5194                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5195                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5196                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5197                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5198                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5199                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5200                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5201                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5202                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5203                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5204                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5205                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5206                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5207                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5208                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5209
5210                 { 0xffff, 0, 0x00000000, 0x00000000 },
5211         };
5212
5213         ret = 0;
5214         is_5709 = 0;
5215         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5216                 is_5709 = 1;
5217
5218         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5219                 u32 offset, rw_mask, ro_mask, save_val, val;
5220                 u16 flags = reg_tbl[i].flags;
5221
5222                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5223                         continue;
5224
5225                 offset = (u32) reg_tbl[i].offset;
5226                 rw_mask = reg_tbl[i].rw_mask;
5227                 ro_mask = reg_tbl[i].ro_mask;
5228
5229                 save_val = readl(bp->regview + offset);
5230
5231                 writel(0, bp->regview + offset);
5232
5233                 val = readl(bp->regview + offset);
5234                 if ((val & rw_mask) != 0) {
5235                         goto reg_test_err;
5236                 }
5237
5238                 if ((val & ro_mask) != (save_val & ro_mask)) {
5239                         goto reg_test_err;
5240                 }
5241
5242                 writel(0xffffffff, bp->regview + offset);
5243
5244                 val = readl(bp->regview + offset);
5245                 if ((val & rw_mask) != rw_mask) {
5246                         goto reg_test_err;
5247                 }
5248
5249                 if ((val & ro_mask) != (save_val & ro_mask)) {
5250                         goto reg_test_err;
5251                 }
5252
5253                 writel(save_val, bp->regview + offset);
5254                 continue;
5255
5256 reg_test_err:
5257                 writel(save_val, bp->regview + offset);
5258                 ret = -ENODEV;
5259                 break;
5260         }
5261         return ret;
5262 }
5263
5264 static int
5265 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5266 {
5267         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5268                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5269         int i;
5270
5271         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5272                 u32 offset;
5273
5274                 for (offset = 0; offset < size; offset += 4) {
5275
5276                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5277
5278                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5279                                 test_pattern[i]) {
5280                                 return -ENODEV;
5281                         }
5282                 }
5283         }
5284         return 0;
5285 }
5286
5287 static int
5288 bnx2_test_memory(struct bnx2 *bp)
5289 {
5290         int ret = 0;
5291         int i;
5292         static struct mem_entry {
5293                 u32   offset;
5294                 u32   len;
5295         } mem_tbl_5706[] = {
5296                 { 0x60000,  0x4000 },
5297                 { 0xa0000,  0x3000 },
5298                 { 0xe0000,  0x4000 },
5299                 { 0x120000, 0x4000 },
5300                 { 0x1a0000, 0x4000 },
5301                 { 0x160000, 0x4000 },
5302                 { 0xffffffff, 0    },
5303         },
5304         mem_tbl_5709[] = {
5305                 { 0x60000,  0x4000 },
5306                 { 0xa0000,  0x3000 },
5307                 { 0xe0000,  0x4000 },
5308                 { 0x120000, 0x4000 },
5309                 { 0x1a0000, 0x4000 },
5310                 { 0xffffffff, 0    },
5311         };
5312         struct mem_entry *mem_tbl;
5313
5314         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5315                 mem_tbl = mem_tbl_5709;
5316         else
5317                 mem_tbl = mem_tbl_5706;
5318
5319         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5320                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5321                         mem_tbl[i].len)) != 0) {
5322                         return ret;
5323                 }
5324         }
5325
5326         return ret;
5327 }
5328
5329 #define BNX2_MAC_LOOPBACK       0
5330 #define BNX2_PHY_LOOPBACK       1
5331
5332 static int
5333 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5334 {
5335         unsigned int pkt_size, num_pkts, i;
5336         struct sk_buff *skb, *rx_skb;
5337         unsigned char *packet;
5338         u16 rx_start_idx, rx_idx;
5339         dma_addr_t map;
5340         struct tx_bd *txbd;
5341         struct sw_bd *rx_buf;
5342         struct l2_fhdr *rx_hdr;
5343         int ret = -ENODEV;
5344         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5345         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5346         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5347
5348         tx_napi = bnapi;
5349
5350         txr = &tx_napi->tx_ring;
5351         rxr = &bnapi->rx_ring;
5352         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5353                 bp->loopback = MAC_LOOPBACK;
5354                 bnx2_set_mac_loopback(bp);
5355         }
5356         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5357                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5358                         return 0;
5359
5360                 bp->loopback = PHY_LOOPBACK;
5361                 bnx2_set_phy_loopback(bp);
5362         }
5363         else
5364                 return -EINVAL;
5365
5366         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5367         skb = netdev_alloc_skb(bp->dev, pkt_size);
5368         if (!skb)
5369                 return -ENOMEM;
5370         packet = skb_put(skb, pkt_size);
5371         memcpy(packet, bp->dev->dev_addr, 6);
5372         memset(packet + 6, 0x0, 8);
5373         for (i = 14; i < pkt_size; i++)
5374                 packet[i] = (unsigned char) (i & 0xff);
5375
5376         map = pci_map_single(bp->pdev, skb->data, pkt_size,
5377                 PCI_DMA_TODEVICE);
5378
5379         REG_WR(bp, BNX2_HC_COMMAND,
5380                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5381
5382         REG_RD(bp, BNX2_HC_COMMAND);
5383
5384         udelay(5);
5385         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5386
5387         num_pkts = 0;
5388
5389         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5390
5391         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5392         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5393         txbd->tx_bd_mss_nbytes = pkt_size;
5394         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5395
5396         num_pkts++;
5397         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5398         txr->tx_prod_bseq += pkt_size;
5399
5400         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5401         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5402
5403         udelay(100);
5404
5405         REG_WR(bp, BNX2_HC_COMMAND,
5406                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5407
5408         REG_RD(bp, BNX2_HC_COMMAND);
5409
5410         udelay(5);
5411
5412         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5413         dev_kfree_skb(skb);
5414
5415         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5416                 goto loopback_test_done;
5417
5418         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5419         if (rx_idx != rx_start_idx + num_pkts) {
5420                 goto loopback_test_done;
5421         }
5422
5423         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5424         rx_skb = rx_buf->skb;
5425
5426         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5427         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5428
5429         pci_dma_sync_single_for_cpu(bp->pdev,
5430                 pci_unmap_addr(rx_buf, mapping),
5431                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5432
5433         if (rx_hdr->l2_fhdr_status &
5434                 (L2_FHDR_ERRORS_BAD_CRC |
5435                 L2_FHDR_ERRORS_PHY_DECODE |
5436                 L2_FHDR_ERRORS_ALIGNMENT |
5437                 L2_FHDR_ERRORS_TOO_SHORT |
5438                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5439
5440                 goto loopback_test_done;
5441         }
5442
5443         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5444                 goto loopback_test_done;
5445         }
5446
5447         for (i = 14; i < pkt_size; i++) {
5448                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5449                         goto loopback_test_done;
5450                 }
5451         }
5452
5453         ret = 0;
5454
5455 loopback_test_done:
5456         bp->loopback = 0;
5457         return ret;
5458 }
5459
5460 #define BNX2_MAC_LOOPBACK_FAILED        1
5461 #define BNX2_PHY_LOOPBACK_FAILED        2
5462 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5463                                          BNX2_PHY_LOOPBACK_FAILED)
5464
5465 static int
5466 bnx2_test_loopback(struct bnx2 *bp)
5467 {
5468         int rc = 0;
5469
5470         if (!netif_running(bp->dev))
5471                 return BNX2_LOOPBACK_FAILED;
5472
5473         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5474         spin_lock_bh(&bp->phy_lock);
5475         bnx2_init_phy(bp, 1);
5476         spin_unlock_bh(&bp->phy_lock);
5477         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5478                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5479         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5480                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5481         return rc;
5482 }
5483
5484 #define NVRAM_SIZE 0x200
5485 #define CRC32_RESIDUAL 0xdebb20e3
5486
5487 static int
5488 bnx2_test_nvram(struct bnx2 *bp)
5489 {
5490         __be32 buf[NVRAM_SIZE / 4];
5491         u8 *data = (u8 *) buf;
5492         int rc = 0;
5493         u32 magic, csum;
5494
5495         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5496                 goto test_nvram_done;
5497
5498         magic = be32_to_cpu(buf[0]);
5499         if (magic != 0x669955aa) {
5500                 rc = -ENODEV;
5501                 goto test_nvram_done;
5502         }
5503
5504         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5505                 goto test_nvram_done;
5506
5507         csum = ether_crc_le(0x100, data);
5508         if (csum != CRC32_RESIDUAL) {
5509                 rc = -ENODEV;
5510                 goto test_nvram_done;
5511         }
5512
5513         csum = ether_crc_le(0x100, data + 0x100);
5514         if (csum != CRC32_RESIDUAL) {
5515                 rc = -ENODEV;
5516         }
5517
5518 test_nvram_done:
5519         return rc;
5520 }
5521
5522 static int
5523 bnx2_test_link(struct bnx2 *bp)
5524 {
5525         u32 bmsr;
5526
5527         if (!netif_running(bp->dev))
5528                 return -ENODEV;
5529
5530         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5531                 if (bp->link_up)
5532                         return 0;
5533                 return -ENODEV;
5534         }
5535         spin_lock_bh(&bp->phy_lock);
5536         bnx2_enable_bmsr1(bp);
5537         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5538         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5539         bnx2_disable_bmsr1(bp);
5540         spin_unlock_bh(&bp->phy_lock);
5541
5542         if (bmsr & BMSR_LSTATUS) {
5543                 return 0;
5544         }
5545         return -ENODEV;
5546 }
5547
5548 static int
5549 bnx2_test_intr(struct bnx2 *bp)
5550 {
5551         int i;
5552         u16 status_idx;
5553
5554         if (!netif_running(bp->dev))
5555                 return -ENODEV;
5556
5557         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5558
5559         /* This register is not touched during run-time. */
5560         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5561         REG_RD(bp, BNX2_HC_COMMAND);
5562
5563         for (i = 0; i < 10; i++) {
5564                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5565                         status_idx) {
5566
5567                         break;
5568                 }
5569
5570                 msleep_interruptible(10);
5571         }
5572         if (i < 10)
5573                 return 0;
5574
5575         return -ENODEV;
5576 }
5577
5578 /* Determining link for parallel detection. */
5579 static int
5580 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5581 {
5582         u32 mode_ctl, an_dbg, exp;
5583
5584         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5585                 return 0;
5586
5587         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5588         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5589
5590         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5591                 return 0;
5592
5593         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5594         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5595         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5596
5597         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5598                 return 0;
5599
5600         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5601         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5602         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5603
5604         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5605                 return 0;
5606
5607         return 1;
5608 }
5609
5610 static void
5611 bnx2_5706_serdes_timer(struct bnx2 *bp)
5612 {
5613         int check_link = 1;
5614
5615         spin_lock(&bp->phy_lock);
5616         if (bp->serdes_an_pending) {
5617                 bp->serdes_an_pending--;
5618                 check_link = 0;
5619         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5620                 u32 bmcr;
5621
5622                 bp->current_interval = BNX2_TIMER_INTERVAL;
5623
5624                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5625
5626                 if (bmcr & BMCR_ANENABLE) {
5627                         if (bnx2_5706_serdes_has_link(bp)) {
5628                                 bmcr &= ~BMCR_ANENABLE;
5629                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5630                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5631                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5632                         }
5633                 }
5634         }
5635         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5636                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5637                 u32 phy2;
5638
5639                 bnx2_write_phy(bp, 0x17, 0x0f01);
5640                 bnx2_read_phy(bp, 0x15, &phy2);
5641                 if (phy2 & 0x20) {
5642                         u32 bmcr;
5643
5644                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5645                         bmcr |= BMCR_ANENABLE;
5646                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5647
5648                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5649                 }
5650         } else
5651                 bp->current_interval = BNX2_TIMER_INTERVAL;
5652
5653         if (check_link) {
5654                 u32 val;
5655
5656                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5657                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5658                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5659
5660                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5661                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5662                                 bnx2_5706s_force_link_dn(bp, 1);
5663                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5664                         } else
5665                                 bnx2_set_link(bp);
5666                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5667                         bnx2_set_link(bp);
5668         }
5669         spin_unlock(&bp->phy_lock);
5670 }
5671
5672 static void
5673 bnx2_5708_serdes_timer(struct bnx2 *bp)
5674 {
5675         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5676                 return;
5677
5678         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5679                 bp->serdes_an_pending = 0;
5680                 return;
5681         }
5682
5683         spin_lock(&bp->phy_lock);
5684         if (bp->serdes_an_pending)
5685                 bp->serdes_an_pending--;
5686         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5687                 u32 bmcr;
5688
5689                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5690                 if (bmcr & BMCR_ANENABLE) {
5691                         bnx2_enable_forced_2g5(bp);
5692                         bp->current_interval = SERDES_FORCED_TIMEOUT;
5693                 } else {
5694                         bnx2_disable_forced_2g5(bp);
5695                         bp->serdes_an_pending = 2;
5696                         bp->current_interval = BNX2_TIMER_INTERVAL;
5697                 }
5698
5699         } else
5700                 bp->current_interval = BNX2_TIMER_INTERVAL;
5701
5702         spin_unlock(&bp->phy_lock);
5703 }
5704
5705 static void
5706 bnx2_timer(unsigned long data)
5707 {
5708         struct bnx2 *bp = (struct bnx2 *) data;
5709
5710         if (!netif_running(bp->dev))
5711                 return;
5712
5713         if (atomic_read(&bp->intr_sem) != 0)
5714                 goto bnx2_restart_timer;
5715
5716         bnx2_send_heart_beat(bp);
5717
5718         bp->stats_blk->stat_FwRxDrop =
5719                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5720
5721         /* workaround occasional corrupted counters */
5722         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5723                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5724                                             BNX2_HC_COMMAND_STATS_NOW);
5725
5726         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5727                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5728                         bnx2_5706_serdes_timer(bp);
5729                 else
5730                         bnx2_5708_serdes_timer(bp);
5731         }
5732
5733 bnx2_restart_timer:
5734         mod_timer(&bp->timer, jiffies + bp->current_interval);
5735 }
5736
5737 static int
5738 bnx2_request_irq(struct bnx2 *bp)
5739 {
5740         unsigned long flags;
5741         struct bnx2_irq *irq;
5742         int rc = 0, i;
5743
5744         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5745                 flags = 0;
5746         else
5747                 flags = IRQF_SHARED;
5748
5749         for (i = 0; i < bp->irq_nvecs; i++) {
5750                 irq = &bp->irq_tbl[i];
5751                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5752                                  &bp->bnx2_napi[i]);
5753                 if (rc)
5754                         break;
5755                 irq->requested = 1;
5756         }
5757         return rc;
5758 }
5759
5760 static void
5761 bnx2_free_irq(struct bnx2 *bp)
5762 {
5763         struct bnx2_irq *irq;
5764         int i;
5765
5766         for (i = 0; i < bp->irq_nvecs; i++) {
5767                 irq = &bp->irq_tbl[i];
5768                 if (irq->requested)
5769                         free_irq(irq->vector, &bp->bnx2_napi[i]);
5770                 irq->requested = 0;
5771         }
5772         if (bp->flags & BNX2_FLAG_USING_MSI)
5773                 pci_disable_msi(bp->pdev);
5774         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5775                 pci_disable_msix(bp->pdev);
5776
5777         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5778 }
5779
5780 static void
5781 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5782 {
5783         int i, rc;
5784         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5785
5786         bnx2_setup_msix_tbl(bp);
5787         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5788         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5789         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5790
5791         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5792                 msix_ent[i].entry = i;
5793                 msix_ent[i].vector = 0;
5794
5795                 strcpy(bp->irq_tbl[i].name, bp->dev->name);
5796                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5797         }
5798
5799         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5800         if (rc != 0)
5801                 return;
5802
5803         bp->irq_nvecs = msix_vecs;
5804         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5805         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5806                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5807 }
5808
5809 static void
5810 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5811 {
5812         int cpus = num_online_cpus();
5813         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5814
5815         bp->irq_tbl[0].handler = bnx2_interrupt;
5816         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5817         bp->irq_nvecs = 1;
5818         bp->irq_tbl[0].vector = bp->pdev->irq;
5819
5820         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5821                 bnx2_enable_msix(bp, msix_vecs);
5822
5823         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5824             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5825                 if (pci_enable_msi(bp->pdev) == 0) {
5826                         bp->flags |= BNX2_FLAG_USING_MSI;
5827                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5828                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5829                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5830                         } else
5831                                 bp->irq_tbl[0].handler = bnx2_msi;
5832
5833                         bp->irq_tbl[0].vector = bp->pdev->irq;
5834                 }
5835         }
5836
5837         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5838         bp->dev->real_num_tx_queues = bp->num_tx_rings;
5839
5840         bp->num_rx_rings = bp->irq_nvecs;
5841 }
5842
5843 /* Called with rtnl_lock */
5844 static int
5845 bnx2_open(struct net_device *dev)
5846 {
5847         struct bnx2 *bp = netdev_priv(dev);
5848         int rc;
5849
5850         netif_carrier_off(dev);
5851
5852         bnx2_set_power_state(bp, PCI_D0);
5853         bnx2_disable_int(bp);
5854
5855         bnx2_setup_int_mode(bp, disable_msi);
5856         bnx2_napi_enable(bp);
5857         rc = bnx2_alloc_mem(bp);
5858         if (rc)
5859                 goto open_err;
5860
5861         rc = bnx2_request_irq(bp);
5862         if (rc)
5863                 goto open_err;
5864
5865         rc = bnx2_init_nic(bp, 1);
5866         if (rc)
5867                 goto open_err;
5868
5869         mod_timer(&bp->timer, jiffies + bp->current_interval);
5870
5871         atomic_set(&bp->intr_sem, 0);
5872
5873         bnx2_enable_int(bp);
5874
5875         if (bp->flags & BNX2_FLAG_USING_MSI) {
5876                 /* Test MSI to make sure it is working
5877                  * If MSI test fails, go back to INTx mode
5878                  */
5879                 if (bnx2_test_intr(bp) != 0) {
5880                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5881                                " using MSI, switching to INTx mode. Please"
5882                                " report this failure to the PCI maintainer"
5883                                " and include system chipset information.\n",
5884                                bp->dev->name);
5885
5886                         bnx2_disable_int(bp);
5887                         bnx2_free_irq(bp);
5888
5889                         bnx2_setup_int_mode(bp, 1);
5890
5891                         rc = bnx2_init_nic(bp, 0);
5892
5893                         if (!rc)
5894                                 rc = bnx2_request_irq(bp);
5895
5896                         if (rc) {
5897                                 del_timer_sync(&bp->timer);
5898                                 goto open_err;
5899                         }
5900                         bnx2_enable_int(bp);
5901                 }
5902         }
5903         if (bp->flags & BNX2_FLAG_USING_MSI)
5904                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5905         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5906                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5907
5908         netif_tx_start_all_queues(dev);
5909
5910         return 0;
5911
5912 open_err:
5913         bnx2_napi_disable(bp);
5914         bnx2_free_skbs(bp);
5915         bnx2_free_irq(bp);
5916         bnx2_free_mem(bp);
5917         return rc;
5918 }
5919
5920 static void
5921 bnx2_reset_task(struct work_struct *work)
5922 {
5923         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5924
5925         if (!netif_running(bp->dev))
5926                 return;
5927
5928         bnx2_netif_stop(bp);
5929
5930         bnx2_init_nic(bp, 1);
5931
5932         atomic_set(&bp->intr_sem, 1);
5933         bnx2_netif_start(bp);
5934 }
5935
5936 static void
5937 bnx2_tx_timeout(struct net_device *dev)
5938 {
5939         struct bnx2 *bp = netdev_priv(dev);
5940
5941         /* This allows the netif to be shutdown gracefully before resetting */
5942         schedule_work(&bp->reset_task);
5943 }
5944
5945 #ifdef BCM_VLAN
5946 /* Called with rtnl_lock */
5947 static void
5948 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5949 {
5950         struct bnx2 *bp = netdev_priv(dev);
5951
5952         bnx2_netif_stop(bp);
5953
5954         bp->vlgrp = vlgrp;
5955         bnx2_set_rx_mode(dev);
5956         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5957                 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
5958
5959         bnx2_netif_start(bp);
5960 }
5961 #endif
5962
5963 /* Called with netif_tx_lock.
5964  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5965  * netif_wake_queue().
5966  */
5967 static int
5968 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5969 {
5970         struct bnx2 *bp = netdev_priv(dev);
5971         dma_addr_t mapping;
5972         struct tx_bd *txbd;
5973         struct sw_bd *tx_buf;
5974         u32 len, vlan_tag_flags, last_frag, mss;
5975         u16 prod, ring_prod;
5976         int i;
5977         struct bnx2_napi *bnapi;
5978         struct bnx2_tx_ring_info *txr;
5979         struct netdev_queue *txq;
5980
5981         /*  Determine which tx ring we will be placed on */
5982         i = skb_get_queue_mapping(skb);
5983         bnapi = &bp->bnx2_napi[i];
5984         txr = &bnapi->tx_ring;
5985         txq = netdev_get_tx_queue(dev, i);
5986
5987         if (unlikely(bnx2_tx_avail(bp, txr) <
5988             (skb_shinfo(skb)->nr_frags + 1))) {
5989                 netif_tx_stop_queue(txq);
5990                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5991                         dev->name);
5992
5993                 return NETDEV_TX_BUSY;
5994         }
5995         len = skb_headlen(skb);
5996         prod = txr->tx_prod;
5997         ring_prod = TX_RING_IDX(prod);
5998
5999         vlan_tag_flags = 0;
6000         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6001                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6002         }
6003
6004 #ifdef BCM_VLAN
6005         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6006                 vlan_tag_flags |=
6007                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6008         }
6009 #endif
6010         if ((mss = skb_shinfo(skb)->gso_size)) {
6011                 u32 tcp_opt_len, ip_tcp_len;
6012                 struct iphdr *iph;
6013
6014                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6015
6016                 tcp_opt_len = tcp_optlen(skb);
6017
6018                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6019                         u32 tcp_off = skb_transport_offset(skb) -
6020                                       sizeof(struct ipv6hdr) - ETH_HLEN;
6021
6022                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6023                                           TX_BD_FLAGS_SW_FLAGS;
6024                         if (likely(tcp_off == 0))
6025                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6026                         else {
6027                                 tcp_off >>= 3;
6028                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
6029                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
6030                                                   ((tcp_off & 0x10) <<
6031                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
6032                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6033                         }
6034                 } else {
6035                         if (skb_header_cloned(skb) &&
6036                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6037                                 dev_kfree_skb(skb);
6038                                 return NETDEV_TX_OK;
6039                         }
6040
6041                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6042
6043                         iph = ip_hdr(skb);
6044                         iph->check = 0;
6045                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
6046                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6047                                                                  iph->daddr, 0,
6048                                                                  IPPROTO_TCP,
6049                                                                  0);
6050                         if (tcp_opt_len || (iph->ihl > 5)) {
6051                                 vlan_tag_flags |= ((iph->ihl - 5) +
6052                                                    (tcp_opt_len >> 2)) << 8;
6053                         }
6054                 }
6055         } else
6056                 mss = 0;
6057
6058         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6059
6060         tx_buf = &txr->tx_buf_ring[ring_prod];
6061         tx_buf->skb = skb;
6062         pci_unmap_addr_set(tx_buf, mapping, mapping);
6063
6064         txbd = &txr->tx_desc_ring[ring_prod];
6065
6066         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6067         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6068         txbd->tx_bd_mss_nbytes = len | (mss << 16);
6069         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6070
6071         last_frag = skb_shinfo(skb)->nr_frags;
6072
6073         for (i = 0; i < last_frag; i++) {
6074                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6075
6076                 prod = NEXT_TX_BD(prod);
6077                 ring_prod = TX_RING_IDX(prod);
6078                 txbd = &txr->tx_desc_ring[ring_prod];
6079
6080                 len = frag->size;
6081                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6082                         len, PCI_DMA_TODEVICE);
6083                 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
6084                                 mapping, mapping);
6085
6086                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6087                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6088                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6089                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6090
6091         }
6092         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6093
6094         prod = NEXT_TX_BD(prod);
6095         txr->tx_prod_bseq += skb->len;
6096
6097         REG_WR16(bp, txr->tx_bidx_addr, prod);
6098         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6099
6100         mmiowb();
6101
6102         txr->tx_prod = prod;
6103         dev->trans_start = jiffies;
6104
6105         if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6106                 netif_tx_stop_queue(txq);
6107                 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6108                         netif_tx_wake_queue(txq);
6109         }
6110
6111         return NETDEV_TX_OK;
6112 }
6113
6114 /* Called with rtnl_lock */
6115 static int
6116 bnx2_close(struct net_device *dev)
6117 {
6118         struct bnx2 *bp = netdev_priv(dev);
6119
6120         cancel_work_sync(&bp->reset_task);
6121
6122         bnx2_disable_int_sync(bp);
6123         bnx2_napi_disable(bp);
6124         del_timer_sync(&bp->timer);
6125         bnx2_shutdown_chip(bp);
6126         bnx2_free_irq(bp);
6127         bnx2_free_skbs(bp);
6128         bnx2_free_mem(bp);
6129         bp->link_up = 0;
6130         netif_carrier_off(bp->dev);
6131         bnx2_set_power_state(bp, PCI_D3hot);
6132         return 0;
6133 }
6134
6135 #define GET_NET_STATS64(ctr)                                    \
6136         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
6137         (unsigned long) (ctr##_lo)
6138
6139 #define GET_NET_STATS32(ctr)            \
6140         (ctr##_lo)
6141
6142 #if (BITS_PER_LONG == 64)
6143 #define GET_NET_STATS   GET_NET_STATS64
6144 #else
6145 #define GET_NET_STATS   GET_NET_STATS32
6146 #endif
6147
6148 static struct net_device_stats *
6149 bnx2_get_stats(struct net_device *dev)
6150 {
6151         struct bnx2 *bp = netdev_priv(dev);
6152         struct statistics_block *stats_blk = bp->stats_blk;
6153         struct net_device_stats *net_stats = &bp->net_stats;
6154
6155         if (bp->stats_blk == NULL) {
6156                 return net_stats;
6157         }
6158         net_stats->rx_packets =
6159                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6160                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6161                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6162
6163         net_stats->tx_packets =
6164                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6165                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6166                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6167
6168         net_stats->rx_bytes =
6169                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6170
6171         net_stats->tx_bytes =
6172                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6173
6174         net_stats->multicast =
6175                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6176
6177         net_stats->collisions =
6178                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6179
6180         net_stats->rx_length_errors =
6181                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6182                 stats_blk->stat_EtherStatsOverrsizePkts);
6183
6184         net_stats->rx_over_errors =
6185                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6186
6187         net_stats->rx_frame_errors =
6188                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6189
6190         net_stats->rx_crc_errors =
6191                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6192
6193         net_stats->rx_errors = net_stats->rx_length_errors +
6194                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6195                 net_stats->rx_crc_errors;
6196
6197         net_stats->tx_aborted_errors =
6198                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6199                 stats_blk->stat_Dot3StatsLateCollisions);
6200
6201         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6202             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6203                 net_stats->tx_carrier_errors = 0;
6204         else {
6205                 net_stats->tx_carrier_errors =
6206                         (unsigned long)
6207                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6208         }
6209
6210         net_stats->tx_errors =
6211                 (unsigned long)
6212                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6213                 +
6214                 net_stats->tx_aborted_errors +
6215                 net_stats->tx_carrier_errors;
6216
6217         net_stats->rx_missed_errors =
6218                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6219                 stats_blk->stat_FwRxDrop);
6220
6221         return net_stats;
6222 }
6223
6224 /* All ethtool functions called with rtnl_lock */
6225
6226 static int
6227 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6228 {
6229         struct bnx2 *bp = netdev_priv(dev);
6230         int support_serdes = 0, support_copper = 0;
6231
6232         cmd->supported = SUPPORTED_Autoneg;
6233         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6234                 support_serdes = 1;
6235                 support_copper = 1;
6236         } else if (bp->phy_port == PORT_FIBRE)
6237                 support_serdes = 1;
6238         else
6239                 support_copper = 1;
6240
6241         if (support_serdes) {
6242                 cmd->supported |= SUPPORTED_1000baseT_Full |
6243                         SUPPORTED_FIBRE;
6244                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6245                         cmd->supported |= SUPPORTED_2500baseX_Full;
6246
6247         }
6248         if (support_copper) {
6249                 cmd->supported |= SUPPORTED_10baseT_Half |
6250                         SUPPORTED_10baseT_Full |
6251                         SUPPORTED_100baseT_Half |
6252                         SUPPORTED_100baseT_Full |
6253                         SUPPORTED_1000baseT_Full |
6254                         SUPPORTED_TP;
6255
6256         }
6257
6258         spin_lock_bh(&bp->phy_lock);
6259         cmd->port = bp->phy_port;
6260         cmd->advertising = bp->advertising;
6261
6262         if (bp->autoneg & AUTONEG_SPEED) {
6263                 cmd->autoneg = AUTONEG_ENABLE;
6264         }
6265         else {
6266                 cmd->autoneg = AUTONEG_DISABLE;
6267         }
6268
6269         if (netif_carrier_ok(dev)) {
6270                 cmd->speed = bp->line_speed;
6271                 cmd->duplex = bp->duplex;
6272         }
6273         else {
6274                 cmd->speed = -1;
6275                 cmd->duplex = -1;
6276         }
6277         spin_unlock_bh(&bp->phy_lock);
6278
6279         cmd->transceiver = XCVR_INTERNAL;
6280         cmd->phy_address = bp->phy_addr;
6281
6282         return 0;
6283 }
6284
6285 static int
6286 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6287 {
6288         struct bnx2 *bp = netdev_priv(dev);
6289         u8 autoneg = bp->autoneg;
6290         u8 req_duplex = bp->req_duplex;
6291         u16 req_line_speed = bp->req_line_speed;
6292         u32 advertising = bp->advertising;
6293         int err = -EINVAL;
6294
6295         spin_lock_bh(&bp->phy_lock);
6296
6297         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6298                 goto err_out_unlock;
6299
6300         if (cmd->port != bp->phy_port &&
6301             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6302                 goto err_out_unlock;
6303
6304         /* If device is down, we can store the settings only if the user
6305          * is setting the currently active port.
6306          */
6307         if (!netif_running(dev) && cmd->port != bp->phy_port)
6308                 goto err_out_unlock;
6309
6310         if (cmd->autoneg == AUTONEG_ENABLE) {
6311                 autoneg |= AUTONEG_SPEED;
6312
6313                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6314
6315                 /* allow advertising 1 speed */
6316                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6317                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6318                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6319                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6320
6321                         if (cmd->port == PORT_FIBRE)
6322                                 goto err_out_unlock;
6323
6324                         advertising = cmd->advertising;
6325
6326                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6327                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6328                             (cmd->port == PORT_TP))
6329                                 goto err_out_unlock;
6330                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6331                         advertising = cmd->advertising;
6332                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6333                         goto err_out_unlock;
6334                 else {
6335                         if (cmd->port == PORT_FIBRE)
6336                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6337                         else
6338                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6339                 }
6340                 advertising |= ADVERTISED_Autoneg;
6341         }
6342         else {
6343                 if (cmd->port == PORT_FIBRE) {
6344                         if ((cmd->speed != SPEED_1000 &&
6345                              cmd->speed != SPEED_2500) ||
6346                             (cmd->duplex != DUPLEX_FULL))
6347                                 goto err_out_unlock;
6348
6349                         if (cmd->speed == SPEED_2500 &&
6350                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6351                                 goto err_out_unlock;
6352                 }
6353                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6354                         goto err_out_unlock;
6355
6356                 autoneg &= ~AUTONEG_SPEED;
6357                 req_line_speed = cmd->speed;
6358                 req_duplex = cmd->duplex;
6359                 advertising = 0;
6360         }
6361
6362         bp->autoneg = autoneg;
6363         bp->advertising = advertising;
6364         bp->req_line_speed = req_line_speed;
6365         bp->req_duplex = req_duplex;
6366
6367         err = 0;
6368         /* If device is down, the new settings will be picked up when it is
6369          * brought up.
6370          */
6371         if (netif_running(dev))
6372                 err = bnx2_setup_phy(bp, cmd->port);
6373
6374 err_out_unlock:
6375         spin_unlock_bh(&bp->phy_lock);
6376
6377         return err;
6378 }
6379
6380 static void
6381 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6382 {
6383         struct bnx2 *bp = netdev_priv(dev);
6384
6385         strcpy(info->driver, DRV_MODULE_NAME);
6386         strcpy(info->version, DRV_MODULE_VERSION);
6387         strcpy(info->bus_info, pci_name(bp->pdev));
6388         strcpy(info->fw_version, bp->fw_version);
6389 }
6390
6391 #define BNX2_REGDUMP_LEN                (32 * 1024)
6392
6393 static int
6394 bnx2_get_regs_len(struct net_device *dev)
6395 {
6396         return BNX2_REGDUMP_LEN;
6397 }
6398
6399 static void
6400 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6401 {
6402         u32 *p = _p, i, offset;
6403         u8 *orig_p = _p;
6404         struct bnx2 *bp = netdev_priv(dev);
6405         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6406                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6407                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6408                                  0x1040, 0x1048, 0x1080, 0x10a4,
6409                                  0x1400, 0x1490, 0x1498, 0x14f0,
6410                                  0x1500, 0x155c, 0x1580, 0x15dc,
6411                                  0x1600, 0x1658, 0x1680, 0x16d8,
6412                                  0x1800, 0x1820, 0x1840, 0x1854,
6413                                  0x1880, 0x1894, 0x1900, 0x1984,
6414                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6415                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6416                                  0x2000, 0x2030, 0x23c0, 0x2400,
6417                                  0x2800, 0x2820, 0x2830, 0x2850,
6418                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6419                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6420                                  0x4080, 0x4090, 0x43c0, 0x4458,
6421                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6422                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6423                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6424                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6425                                  0x6800, 0x6848, 0x684c, 0x6860,
6426                                  0x6888, 0x6910, 0x8000 };
6427
6428         regs->version = 0;
6429
6430         memset(p, 0, BNX2_REGDUMP_LEN);
6431
6432         if (!netif_running(bp->dev))
6433                 return;
6434
6435         i = 0;
6436         offset = reg_boundaries[0];
6437         p += offset;
6438         while (offset < BNX2_REGDUMP_LEN) {
6439                 *p++ = REG_RD(bp, offset);
6440                 offset += 4;
6441                 if (offset == reg_boundaries[i + 1]) {
6442                         offset = reg_boundaries[i + 2];
6443                         p = (u32 *) (orig_p + offset);
6444                         i += 2;
6445                 }
6446         }
6447 }
6448
6449 static void
6450 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6451 {
6452         struct bnx2 *bp = netdev_priv(dev);
6453
6454         if (bp->flags & BNX2_FLAG_NO_WOL) {
6455                 wol->supported = 0;
6456                 wol->wolopts = 0;
6457         }
6458         else {
6459                 wol->supported = WAKE_MAGIC;
6460                 if (bp->wol)
6461                         wol->wolopts = WAKE_MAGIC;
6462                 else
6463                         wol->wolopts = 0;
6464         }
6465         memset(&wol->sopass, 0, sizeof(wol->sopass));
6466 }
6467
6468 static int
6469 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6470 {
6471         struct bnx2 *bp = netdev_priv(dev);
6472
6473         if (wol->wolopts & ~WAKE_MAGIC)
6474                 return -EINVAL;
6475
6476         if (wol->wolopts & WAKE_MAGIC) {
6477                 if (bp->flags & BNX2_FLAG_NO_WOL)
6478                         return -EINVAL;
6479
6480                 bp->wol = 1;
6481         }
6482         else {
6483                 bp->wol = 0;
6484         }
6485         return 0;
6486 }
6487
6488 static int
6489 bnx2_nway_reset(struct net_device *dev)
6490 {
6491         struct bnx2 *bp = netdev_priv(dev);
6492         u32 bmcr;
6493
6494         if (!netif_running(dev))
6495                 return -EAGAIN;
6496
6497         if (!(bp->autoneg & AUTONEG_SPEED)) {
6498                 return -EINVAL;
6499         }
6500
6501         spin_lock_bh(&bp->phy_lock);
6502
6503         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6504                 int rc;
6505
6506                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6507                 spin_unlock_bh(&bp->phy_lock);
6508                 return rc;
6509         }
6510
6511         /* Force a link down visible on the other side */
6512         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6513                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6514                 spin_unlock_bh(&bp->phy_lock);
6515
6516                 msleep(20);
6517
6518                 spin_lock_bh(&bp->phy_lock);
6519
6520                 bp->current_interval = SERDES_AN_TIMEOUT;
6521                 bp->serdes_an_pending = 1;
6522                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6523         }
6524
6525         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6526         bmcr &= ~BMCR_LOOPBACK;
6527         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6528
6529         spin_unlock_bh(&bp->phy_lock);
6530
6531         return 0;
6532 }
6533
6534 static int
6535 bnx2_get_eeprom_len(struct net_device *dev)
6536 {
6537         struct bnx2 *bp = netdev_priv(dev);
6538
6539         if (bp->flash_info == NULL)
6540                 return 0;
6541
6542         return (int) bp->flash_size;
6543 }
6544
6545 static int
6546 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6547                 u8 *eebuf)
6548 {
6549         struct bnx2 *bp = netdev_priv(dev);
6550         int rc;
6551
6552         if (!netif_running(dev))
6553                 return -EAGAIN;
6554
6555         /* parameters already validated in ethtool_get_eeprom */
6556
6557         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6558
6559         return rc;
6560 }
6561
6562 static int
6563 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6564                 u8 *eebuf)
6565 {
6566         struct bnx2 *bp = netdev_priv(dev);
6567         int rc;
6568
6569         if (!netif_running(dev))
6570                 return -EAGAIN;
6571
6572         /* parameters already validated in ethtool_set_eeprom */
6573
6574         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6575
6576         return rc;
6577 }
6578
6579 static int
6580 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6581 {
6582         struct bnx2 *bp = netdev_priv(dev);
6583
6584         memset(coal, 0, sizeof(struct ethtool_coalesce));
6585
6586         coal->rx_coalesce_usecs = bp->rx_ticks;
6587         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6588         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6589         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6590
6591         coal->tx_coalesce_usecs = bp->tx_ticks;
6592         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6593         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6594         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6595
6596         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6597
6598         return 0;
6599 }
6600
6601 static int
6602 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6603 {
6604         struct bnx2 *bp = netdev_priv(dev);
6605
6606         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6607         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6608
6609         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6610         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6611
6612         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6613         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6614
6615         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6616         if (bp->rx_quick_cons_trip_int > 0xff)
6617                 bp->rx_quick_cons_trip_int = 0xff;
6618
6619         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6620         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6621
6622         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6623         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6624
6625         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6626         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6627
6628         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6629         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6630                 0xff;
6631
6632         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6633         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6634                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6635                         bp->stats_ticks = USEC_PER_SEC;
6636         }
6637         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6638                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6639         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6640
6641         if (netif_running(bp->dev)) {
6642                 bnx2_netif_stop(bp);
6643                 bnx2_init_nic(bp, 0);
6644                 bnx2_netif_start(bp);
6645         }
6646
6647         return 0;
6648 }
6649
6650 static void
6651 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6652 {
6653         struct bnx2 *bp = netdev_priv(dev);
6654
6655         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6656         ering->rx_mini_max_pending = 0;
6657         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6658
6659         ering->rx_pending = bp->rx_ring_size;
6660         ering->rx_mini_pending = 0;
6661         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6662
6663         ering->tx_max_pending = MAX_TX_DESC_CNT;
6664         ering->tx_pending = bp->tx_ring_size;
6665 }
6666
6667 static int
6668 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6669 {
6670         if (netif_running(bp->dev)) {
6671                 bnx2_netif_stop(bp);
6672                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6673                 bnx2_free_skbs(bp);
6674                 bnx2_free_mem(bp);
6675         }
6676
6677         bnx2_set_rx_ring_size(bp, rx);
6678         bp->tx_ring_size = tx;
6679
6680         if (netif_running(bp->dev)) {
6681                 int rc;
6682
6683                 rc = bnx2_alloc_mem(bp);
6684                 if (rc)
6685                         return rc;
6686                 bnx2_init_nic(bp, 0);
6687                 bnx2_netif_start(bp);
6688         }
6689         return 0;
6690 }
6691
6692 static int
6693 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6694 {
6695         struct bnx2 *bp = netdev_priv(dev);
6696         int rc;
6697
6698         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6699                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6700                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6701
6702                 return -EINVAL;
6703         }
6704         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6705         return rc;
6706 }
6707
6708 static void
6709 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6710 {
6711         struct bnx2 *bp = netdev_priv(dev);
6712
6713         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6714         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6715         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6716 }
6717
6718 static int
6719 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6720 {
6721         struct bnx2 *bp = netdev_priv(dev);
6722
6723         bp->req_flow_ctrl = 0;
6724         if (epause->rx_pause)
6725                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6726         if (epause->tx_pause)
6727                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6728
6729         if (epause->autoneg) {
6730                 bp->autoneg |= AUTONEG_FLOW_CTRL;
6731         }
6732         else {
6733                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6734         }
6735
6736         if (netif_running(dev)) {
6737                 spin_lock_bh(&bp->phy_lock);
6738                 bnx2_setup_phy(bp, bp->phy_port);
6739                 spin_unlock_bh(&bp->phy_lock);
6740         }
6741
6742         return 0;
6743 }
6744
6745 static u32
6746 bnx2_get_rx_csum(struct net_device *dev)
6747 {
6748         struct bnx2 *bp = netdev_priv(dev);
6749
6750         return bp->rx_csum;
6751 }
6752
6753 static int
6754 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6755 {
6756         struct bnx2 *bp = netdev_priv(dev);
6757
6758         bp->rx_csum = data;
6759         return 0;
6760 }
6761
6762 static int
6763 bnx2_set_tso(struct net_device *dev, u32 data)
6764 {
6765         struct bnx2 *bp = netdev_priv(dev);
6766
6767         if (data) {
6768                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6769                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6770                         dev->features |= NETIF_F_TSO6;
6771         } else
6772                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6773                                    NETIF_F_TSO_ECN);
6774         return 0;
6775 }
6776
6777 #define BNX2_NUM_STATS 46
6778
6779 static struct {
6780         char string[ETH_GSTRING_LEN];
6781 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6782         { "rx_bytes" },
6783         { "rx_error_bytes" },
6784         { "tx_bytes" },
6785         { "tx_error_bytes" },
6786         { "rx_ucast_packets" },
6787         { "rx_mcast_packets" },
6788         { "rx_bcast_packets" },
6789         { "tx_ucast_packets" },
6790         { "tx_mcast_packets" },
6791         { "tx_bcast_packets" },
6792         { "tx_mac_errors" },
6793         { "tx_carrier_errors" },
6794         { "rx_crc_errors" },
6795         { "rx_align_errors" },
6796         { "tx_single_collisions" },
6797         { "tx_multi_collisions" },
6798         { "tx_deferred" },
6799         { "tx_excess_collisions" },
6800         { "tx_late_collisions" },
6801         { "tx_total_collisions" },
6802         { "rx_fragments" },
6803         { "rx_jabbers" },
6804         { "rx_undersize_packets" },
6805         { "rx_oversize_packets" },
6806         { "rx_64_byte_packets" },
6807         { "rx_65_to_127_byte_packets" },
6808         { "rx_128_to_255_byte_packets" },
6809         { "rx_256_to_511_byte_packets" },
6810         { "rx_512_to_1023_byte_packets" },
6811         { "rx_1024_to_1522_byte_packets" },
6812         { "rx_1523_to_9022_byte_packets" },
6813         { "tx_64_byte_packets" },
6814         { "tx_65_to_127_byte_packets" },
6815         { "tx_128_to_255_byte_packets" },
6816         { "tx_256_to_511_byte_packets" },
6817         { "tx_512_to_1023_byte_packets" },
6818         { "tx_1024_to_1522_byte_packets" },
6819         { "tx_1523_to_9022_byte_packets" },
6820         { "rx_xon_frames" },
6821         { "rx_xoff_frames" },
6822         { "tx_xon_frames" },
6823         { "tx_xoff_frames" },
6824         { "rx_mac_ctrl_frames" },
6825         { "rx_filtered_packets" },
6826         { "rx_discards" },
6827         { "rx_fw_discards" },
6828 };
6829
6830 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6831
6832 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6833     STATS_OFFSET32(stat_IfHCInOctets_hi),
6834     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6835     STATS_OFFSET32(stat_IfHCOutOctets_hi),
6836     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6837     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6838     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6839     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6840     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6841     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6842     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6843     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6844     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6845     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6846     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6847     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6848     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6849     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6850     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6851     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6852     STATS_OFFSET32(stat_EtherStatsCollisions),
6853     STATS_OFFSET32(stat_EtherStatsFragments),
6854     STATS_OFFSET32(stat_EtherStatsJabbers),
6855     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6856     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6857     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6858     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6859     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6860     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6861     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6862     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6863     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6864     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6865     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6866     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6867     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6868     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6869     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6870     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6871     STATS_OFFSET32(stat_XonPauseFramesReceived),
6872     STATS_OFFSET32(stat_XoffPauseFramesReceived),
6873     STATS_OFFSET32(stat_OutXonSent),
6874     STATS_OFFSET32(stat_OutXoffSent),
6875     STATS_OFFSET32(stat_MacControlFramesReceived),
6876     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6877     STATS_OFFSET32(stat_IfInMBUFDiscards),
6878     STATS_OFFSET32(stat_FwRxDrop),
6879 };
6880
6881 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6882  * skipped because of errata.
6883  */
6884 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6885         8,0,8,8,8,8,8,8,8,8,
6886         4,0,4,4,4,4,4,4,4,4,
6887         4,4,4,4,4,4,4,4,4,4,
6888         4,4,4,4,4,4,4,4,4,4,
6889         4,4,4,4,4,4,
6890 };
6891
6892 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6893         8,0,8,8,8,8,8,8,8,8,
6894         4,4,4,4,4,4,4,4,4,4,
6895         4,4,4,4,4,4,4,4,4,4,
6896         4,4,4,4,4,4,4,4,4,4,
6897         4,4,4,4,4,4,
6898 };
6899
6900 #define BNX2_NUM_TESTS 6
6901
6902 static struct {
6903         char string[ETH_GSTRING_LEN];
6904 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6905         { "register_test (offline)" },
6906         { "memory_test (offline)" },
6907         { "loopback_test (offline)" },
6908         { "nvram_test (online)" },
6909         { "interrupt_test (online)" },
6910         { "link_test (online)" },
6911 };
6912
6913 static int
6914 bnx2_get_sset_count(struct net_device *dev, int sset)
6915 {
6916         switch (sset) {
6917         case ETH_SS_TEST:
6918                 return BNX2_NUM_TESTS;
6919         case ETH_SS_STATS:
6920                 return BNX2_NUM_STATS;
6921         default:
6922                 return -EOPNOTSUPP;
6923         }
6924 }
6925
6926 static void
6927 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6928 {
6929         struct bnx2 *bp = netdev_priv(dev);
6930
6931         bnx2_set_power_state(bp, PCI_D0);
6932
6933         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6934         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6935                 int i;
6936
6937                 bnx2_netif_stop(bp);
6938                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6939                 bnx2_free_skbs(bp);
6940
6941                 if (bnx2_test_registers(bp) != 0) {
6942                         buf[0] = 1;
6943                         etest->flags |= ETH_TEST_FL_FAILED;
6944                 }
6945                 if (bnx2_test_memory(bp) != 0) {
6946                         buf[1] = 1;
6947                         etest->flags |= ETH_TEST_FL_FAILED;
6948                 }
6949                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6950                         etest->flags |= ETH_TEST_FL_FAILED;
6951
6952                 if (!netif_running(bp->dev))
6953                         bnx2_shutdown_chip(bp);
6954                 else {
6955                         bnx2_init_nic(bp, 1);
6956                         bnx2_netif_start(bp);
6957                 }
6958
6959                 /* wait for link up */
6960                 for (i = 0; i < 7; i++) {
6961                         if (bp->link_up)
6962                                 break;
6963                         msleep_interruptible(1000);
6964                 }
6965         }
6966
6967         if (bnx2_test_nvram(bp) != 0) {
6968                 buf[3] = 1;
6969                 etest->flags |= ETH_TEST_FL_FAILED;
6970         }
6971         if (bnx2_test_intr(bp) != 0) {
6972                 buf[4] = 1;
6973                 etest->flags |= ETH_TEST_FL_FAILED;
6974         }
6975
6976         if (bnx2_test_link(bp) != 0) {
6977                 buf[5] = 1;
6978                 etest->flags |= ETH_TEST_FL_FAILED;
6979
6980         }
6981         if (!netif_running(bp->dev))
6982                 bnx2_set_power_state(bp, PCI_D3hot);
6983 }
6984
6985 static void
6986 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6987 {
6988         switch (stringset) {
6989         case ETH_SS_STATS:
6990                 memcpy(buf, bnx2_stats_str_arr,
6991                         sizeof(bnx2_stats_str_arr));
6992                 break;
6993         case ETH_SS_TEST:
6994                 memcpy(buf, bnx2_tests_str_arr,
6995                         sizeof(bnx2_tests_str_arr));
6996                 break;
6997         }
6998 }
6999
7000 static void
7001 bnx2_get_ethtool_stats(struct net_device *dev,
7002                 struct ethtool_stats *stats, u64 *buf)
7003 {
7004         struct bnx2 *bp = netdev_priv(dev);
7005         int i;
7006         u32 *hw_stats = (u32 *) bp->stats_blk;
7007         u8 *stats_len_arr = NULL;
7008
7009         if (hw_stats == NULL) {
7010                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7011                 return;
7012         }
7013
7014         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7015             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7016             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7017             (CHIP_ID(bp) == CHIP_ID_5708_A0))
7018                 stats_len_arr = bnx2_5706_stats_len_arr;
7019         else
7020                 stats_len_arr = bnx2_5708_stats_len_arr;
7021
7022         for (i = 0; i < BNX2_NUM_STATS; i++) {
7023                 if (stats_len_arr[i] == 0) {
7024                         /* skip this counter */
7025                         buf[i] = 0;
7026                         continue;
7027                 }
7028                 if (stats_len_arr[i] == 4) {
7029                         /* 4-byte counter */
7030                         buf[i] = (u64)
7031                                 *(hw_stats + bnx2_stats_offset_arr[i]);
7032                         continue;
7033                 }
7034                 /* 8-byte counter */
7035                 buf[i] = (((u64) *(hw_stats +
7036                                         bnx2_stats_offset_arr[i])) << 32) +
7037                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7038         }
7039 }
7040
7041 static int
7042 bnx2_phys_id(struct net_device *dev, u32 data)
7043 {
7044         struct bnx2 *bp = netdev_priv(dev);
7045         int i;
7046         u32 save;
7047
7048         bnx2_set_power_state(bp, PCI_D0);
7049
7050         if (data == 0)
7051                 data = 2;
7052
7053         save = REG_RD(bp, BNX2_MISC_CFG);
7054         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7055
7056         for (i = 0; i < (data * 2); i++) {
7057                 if ((i % 2) == 0) {
7058                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7059                 }
7060                 else {
7061                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7062                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
7063                                 BNX2_EMAC_LED_100MB_OVERRIDE |
7064                                 BNX2_EMAC_LED_10MB_OVERRIDE |
7065                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7066                                 BNX2_EMAC_LED_TRAFFIC);
7067                 }
7068                 msleep_interruptible(500);
7069                 if (signal_pending(current))
7070                         break;
7071         }
7072         REG_WR(bp, BNX2_EMAC_LED, 0);
7073         REG_WR(bp, BNX2_MISC_CFG, save);
7074
7075         if (!netif_running(dev))
7076                 bnx2_set_power_state(bp, PCI_D3hot);
7077
7078         return 0;
7079 }
7080
7081 static int
7082 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7083 {
7084         struct bnx2 *bp = netdev_priv(dev);
7085
7086         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7087                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7088         else
7089                 return (ethtool_op_set_tx_csum(dev, data));
7090 }
7091
7092 static const struct ethtool_ops bnx2_ethtool_ops = {
7093         .get_settings           = bnx2_get_settings,
7094         .set_settings           = bnx2_set_settings,
7095         .get_drvinfo            = bnx2_get_drvinfo,
7096         .get_regs_len           = bnx2_get_regs_len,
7097         .get_regs               = bnx2_get_regs,
7098         .get_wol                = bnx2_get_wol,
7099         .set_wol                = bnx2_set_wol,
7100         .nway_reset             = bnx2_nway_reset,
7101         .get_link               = ethtool_op_get_link,
7102         .get_eeprom_len         = bnx2_get_eeprom_len,
7103         .get_eeprom             = bnx2_get_eeprom,
7104         .set_eeprom             = bnx2_set_eeprom,
7105         .get_coalesce           = bnx2_get_coalesce,
7106         .set_coalesce           = bnx2_set_coalesce,
7107         .get_ringparam          = bnx2_get_ringparam,
7108         .set_ringparam          = bnx2_set_ringparam,
7109         .get_pauseparam         = bnx2_get_pauseparam,
7110         .set_pauseparam         = bnx2_set_pauseparam,
7111         .get_rx_csum            = bnx2_get_rx_csum,
7112         .set_rx_csum            = bnx2_set_rx_csum,
7113         .set_tx_csum            = bnx2_set_tx_csum,
7114         .set_sg                 = ethtool_op_set_sg,
7115         .set_tso                = bnx2_set_tso,
7116         .self_test              = bnx2_self_test,
7117         .get_strings            = bnx2_get_strings,
7118         .phys_id                = bnx2_phys_id,
7119         .get_ethtool_stats      = bnx2_get_ethtool_stats,
7120         .get_sset_count         = bnx2_get_sset_count,
7121 };
7122
7123 /* Called with rtnl_lock */
7124 static int
7125 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7126 {
7127         struct mii_ioctl_data *data = if_mii(ifr);
7128         struct bnx2 *bp = netdev_priv(dev);
7129         int err;
7130
7131         switch(cmd) {
7132         case SIOCGMIIPHY:
7133                 data->phy_id = bp->phy_addr;
7134
7135                 /* fallthru */
7136         case SIOCGMIIREG: {
7137                 u32 mii_regval;
7138
7139                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7140                         return -EOPNOTSUPP;
7141
7142                 if (!netif_running(dev))
7143                         return -EAGAIN;
7144
7145                 spin_lock_bh(&bp->phy_lock);
7146                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7147                 spin_unlock_bh(&bp->phy_lock);
7148
7149                 data->val_out = mii_regval;
7150
7151                 return err;
7152         }
7153
7154         case SIOCSMIIREG:
7155                 if (!capable(CAP_NET_ADMIN))
7156                         return -EPERM;
7157
7158                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7159                         return -EOPNOTSUPP;
7160
7161                 if (!netif_running(dev))
7162                         return -EAGAIN;
7163
7164                 spin_lock_bh(&bp->phy_lock);
7165                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7166                 spin_unlock_bh(&bp->phy_lock);
7167
7168                 return err;
7169
7170         default:
7171                 /* do nothing */
7172                 break;
7173         }
7174         return -EOPNOTSUPP;
7175 }
7176
7177 /* Called with rtnl_lock */
7178 static int
7179 bnx2_change_mac_addr(struct net_device *dev, void *p)
7180 {
7181         struct sockaddr *addr = p;
7182         struct bnx2 *bp = netdev_priv(dev);
7183
7184         if (!is_valid_ether_addr(addr->sa_data))
7185                 return -EINVAL;
7186
7187         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7188         if (netif_running(dev))
7189                 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7190
7191         return 0;
7192 }
7193
7194 /* Called with rtnl_lock */
7195 static int
7196 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7197 {
7198         struct bnx2 *bp = netdev_priv(dev);
7199
7200         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7201                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7202                 return -EINVAL;
7203
7204         dev->mtu = new_mtu;
7205         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7206 }
7207
7208 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7209 static void
7210 poll_bnx2(struct net_device *dev)
7211 {
7212         struct bnx2 *bp = netdev_priv(dev);
7213
7214         disable_irq(bp->pdev->irq);
7215         bnx2_interrupt(bp->pdev->irq, dev);
7216         enable_irq(bp->pdev->irq);
7217 }
7218 #endif
7219
7220 static void __devinit
7221 bnx2_get_5709_media(struct bnx2 *bp)
7222 {
7223         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7224         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7225         u32 strap;
7226
7227         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7228                 return;
7229         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7230                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7231                 return;
7232         }
7233
7234         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7235                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7236         else
7237                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7238
7239         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7240                 switch (strap) {
7241                 case 0x4:
7242                 case 0x5:
7243                 case 0x6:
7244                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7245                         return;
7246                 }
7247         } else {
7248                 switch (strap) {
7249                 case 0x1:
7250                 case 0x2:
7251                 case 0x4:
7252                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7253                         return;
7254                 }
7255         }
7256 }
7257
7258 static void __devinit
7259 bnx2_get_pci_speed(struct bnx2 *bp)
7260 {
7261         u32 reg;
7262
7263         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7264         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7265                 u32 clkreg;
7266
7267                 bp->flags |= BNX2_FLAG_PCIX;
7268
7269                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7270
7271                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7272                 switch (clkreg) {
7273                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7274                         bp->bus_speed_mhz = 133;
7275                         break;
7276
7277                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7278                         bp->bus_speed_mhz = 100;
7279                         break;
7280
7281                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7282                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7283                         bp->bus_speed_mhz = 66;
7284                         break;
7285
7286                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7287                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7288                         bp->bus_speed_mhz = 50;
7289                         break;
7290
7291                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7292                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7293                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7294                         bp->bus_speed_mhz = 33;
7295                         break;
7296                 }
7297         }
7298         else {
7299                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7300                         bp->bus_speed_mhz = 66;
7301                 else
7302                         bp->bus_speed_mhz = 33;
7303         }
7304
7305         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7306                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7307
7308 }
7309
7310 static int __devinit
7311 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7312 {
7313         struct bnx2 *bp;
7314         unsigned long mem_len;
7315         int rc, i, j;
7316         u32 reg;
7317         u64 dma_mask, persist_dma_mask;
7318
7319         SET_NETDEV_DEV(dev, &pdev->dev);
7320         bp = netdev_priv(dev);
7321
7322         bp->flags = 0;
7323         bp->phy_flags = 0;
7324
7325         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7326         rc = pci_enable_device(pdev);
7327         if (rc) {
7328                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7329                 goto err_out;
7330         }
7331
7332         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7333                 dev_err(&pdev->dev,
7334                         "Cannot find PCI device base address, aborting.\n");
7335                 rc = -ENODEV;
7336                 goto err_out_disable;
7337         }
7338
7339         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7340         if (rc) {
7341                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7342                 goto err_out_disable;
7343         }
7344
7345         pci_set_master(pdev);
7346         pci_save_state(pdev);
7347
7348         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7349         if (bp->pm_cap == 0) {
7350                 dev_err(&pdev->dev,
7351                         "Cannot find power management capability, aborting.\n");
7352                 rc = -EIO;
7353                 goto err_out_release;
7354         }
7355
7356         bp->dev = dev;
7357         bp->pdev = pdev;
7358
7359         spin_lock_init(&bp->phy_lock);
7360         spin_lock_init(&bp->indirect_lock);
7361         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7362
7363         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7364         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7365         dev->mem_end = dev->mem_start + mem_len;
7366         dev->irq = pdev->irq;
7367
7368         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7369
7370         if (!bp->regview) {
7371                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7372                 rc = -ENOMEM;
7373                 goto err_out_release;
7374         }
7375
7376         /* Configure byte swap and enable write to the reg_window registers.
7377          * Rely on CPU to do target byte swapping on big endian systems
7378          * The chip's target access swapping will not swap all accesses
7379          */
7380         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7381                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7382                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7383
7384         bnx2_set_power_state(bp, PCI_D0);
7385
7386         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7387
7388         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7389                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7390                         dev_err(&pdev->dev,
7391                                 "Cannot find PCIE capability, aborting.\n");
7392                         rc = -EIO;
7393                         goto err_out_unmap;
7394                 }
7395                 bp->flags |= BNX2_FLAG_PCIE;
7396                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7397                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7398         } else {
7399                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7400                 if (bp->pcix_cap == 0) {
7401                         dev_err(&pdev->dev,
7402                                 "Cannot find PCIX capability, aborting.\n");
7403                         rc = -EIO;
7404                         goto err_out_unmap;
7405                 }
7406         }
7407
7408         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7409                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7410                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7411         }
7412
7413         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7414                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7415                         bp->flags |= BNX2_FLAG_MSI_CAP;
7416         }
7417
7418         /* 5708 cannot support DMA addresses > 40-bit.  */
7419         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7420                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7421         else
7422                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7423
7424         /* Configure DMA attributes. */
7425         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7426                 dev->features |= NETIF_F_HIGHDMA;
7427                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7428                 if (rc) {
7429                         dev_err(&pdev->dev,
7430                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7431                         goto err_out_unmap;
7432                 }
7433         } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7434                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7435                 goto err_out_unmap;
7436         }
7437
7438         if (!(bp->flags & BNX2_FLAG_PCIE))
7439                 bnx2_get_pci_speed(bp);
7440
7441         /* 5706A0 may falsely detect SERR and PERR. */
7442         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7443                 reg = REG_RD(bp, PCI_COMMAND);
7444                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7445                 REG_WR(bp, PCI_COMMAND, reg);
7446         }
7447         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7448                 !(bp->flags & BNX2_FLAG_PCIX)) {
7449
7450                 dev_err(&pdev->dev,
7451                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7452                 goto err_out_unmap;
7453         }
7454
7455         bnx2_init_nvram(bp);
7456
7457         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7458
7459         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7460             BNX2_SHM_HDR_SIGNATURE_SIG) {
7461                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7462
7463                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7464         } else
7465                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7466
7467         /* Get the permanent MAC address.  First we need to make sure the
7468          * firmware is actually running.
7469          */
7470         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7471
7472         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7473             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7474                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7475                 rc = -ENODEV;
7476                 goto err_out_unmap;
7477         }
7478
7479         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7480         for (i = 0, j = 0; i < 3; i++) {
7481                 u8 num, k, skip0;
7482
7483                 num = (u8) (reg >> (24 - (i * 8)));
7484                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7485                         if (num >= k || !skip0 || k == 1) {
7486                                 bp->fw_version[j++] = (num / k) + '0';
7487                                 skip0 = 0;
7488                         }
7489                 }
7490                 if (i != 2)
7491                         bp->fw_version[j++] = '.';
7492         }
7493         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7494         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7495                 bp->wol = 1;
7496
7497         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7498                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7499
7500                 for (i = 0; i < 30; i++) {
7501                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7502                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7503                                 break;
7504                         msleep(10);
7505                 }
7506         }
7507         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7508         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7509         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7510             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7511                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7512
7513                 bp->fw_version[j++] = ' ';
7514                 for (i = 0; i < 3; i++) {
7515                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7516                         reg = swab32(reg);
7517                         memcpy(&bp->fw_version[j], &reg, 4);
7518                         j += 4;
7519                 }
7520         }
7521
7522         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7523         bp->mac_addr[0] = (u8) (reg >> 8);
7524         bp->mac_addr[1] = (u8) reg;
7525
7526         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7527         bp->mac_addr[2] = (u8) (reg >> 24);
7528         bp->mac_addr[3] = (u8) (reg >> 16);
7529         bp->mac_addr[4] = (u8) (reg >> 8);
7530         bp->mac_addr[5] = (u8) reg;
7531
7532         bp->tx_ring_size = MAX_TX_DESC_CNT;
7533         bnx2_set_rx_ring_size(bp, 255);
7534
7535         bp->rx_csum = 1;
7536
7537         bp->tx_quick_cons_trip_int = 20;
7538         bp->tx_quick_cons_trip = 20;
7539         bp->tx_ticks_int = 80;
7540         bp->tx_ticks = 80;
7541
7542         bp->rx_quick_cons_trip_int = 6;
7543         bp->rx_quick_cons_trip = 6;
7544         bp->rx_ticks_int = 18;
7545         bp->rx_ticks = 18;
7546
7547         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7548
7549         bp->current_interval = BNX2_TIMER_INTERVAL;
7550
7551         bp->phy_addr = 1;
7552
7553         /* Disable WOL support if we are running on a SERDES chip. */
7554         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7555                 bnx2_get_5709_media(bp);
7556         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7557                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7558
7559         bp->phy_port = PORT_TP;
7560         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7561                 bp->phy_port = PORT_FIBRE;
7562                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7563                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7564                         bp->flags |= BNX2_FLAG_NO_WOL;
7565                         bp->wol = 0;
7566                 }
7567                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7568                         /* Don't do parallel detect on this board because of
7569                          * some board problems.  The link will not go down
7570                          * if we do parallel detect.
7571                          */
7572                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7573                             pdev->subsystem_device == 0x310c)
7574                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7575                 } else {
7576                         bp->phy_addr = 2;
7577                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7578                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7579                 }
7580         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7581                    CHIP_NUM(bp) == CHIP_NUM_5708)
7582                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7583         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7584                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7585                   CHIP_REV(bp) == CHIP_REV_Bx))
7586                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7587
7588         bnx2_init_fw_cap(bp);
7589
7590         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7591             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7592             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7593                 bp->flags |= BNX2_FLAG_NO_WOL;
7594                 bp->wol = 0;
7595         }
7596
7597         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7598                 bp->tx_quick_cons_trip_int =
7599                         bp->tx_quick_cons_trip;
7600                 bp->tx_ticks_int = bp->tx_ticks;
7601                 bp->rx_quick_cons_trip_int =
7602                         bp->rx_quick_cons_trip;
7603                 bp->rx_ticks_int = bp->rx_ticks;
7604                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7605                 bp->com_ticks_int = bp->com_ticks;
7606                 bp->cmd_ticks_int = bp->cmd_ticks;
7607         }
7608
7609         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7610          *
7611          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7612          * with byte enables disabled on the unused 32-bit word.  This is legal
7613          * but causes problems on the AMD 8132 which will eventually stop
7614          * responding after a while.
7615          *
7616          * AMD believes this incompatibility is unique to the 5706, and
7617          * prefers to locally disable MSI rather than globally disabling it.
7618          */
7619         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7620                 struct pci_dev *amd_8132 = NULL;
7621
7622                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7623                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7624                                                   amd_8132))) {
7625
7626                         if (amd_8132->revision >= 0x10 &&
7627                             amd_8132->revision <= 0x13) {
7628                                 disable_msi = 1;
7629                                 pci_dev_put(amd_8132);
7630                                 break;
7631                         }
7632                 }
7633         }
7634
7635         bnx2_set_default_link(bp);
7636         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7637
7638         init_timer(&bp->timer);
7639         bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7640         bp->timer.data = (unsigned long) bp;
7641         bp->timer.function = bnx2_timer;
7642
7643         return 0;
7644
7645 err_out_unmap:
7646         if (bp->regview) {
7647                 iounmap(bp->regview);
7648                 bp->regview = NULL;
7649         }
7650
7651 err_out_release:
7652         pci_release_regions(pdev);
7653
7654 err_out_disable:
7655         pci_disable_device(pdev);
7656         pci_set_drvdata(pdev, NULL);
7657
7658 err_out:
7659         return rc;
7660 }
7661
7662 static char * __devinit
7663 bnx2_bus_string(struct bnx2 *bp, char *str)
7664 {
7665         char *s = str;
7666
7667         if (bp->flags & BNX2_FLAG_PCIE) {
7668                 s += sprintf(s, "PCI Express");
7669         } else {
7670                 s += sprintf(s, "PCI");
7671                 if (bp->flags & BNX2_FLAG_PCIX)
7672                         s += sprintf(s, "-X");
7673                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7674                         s += sprintf(s, " 32-bit");
7675                 else
7676                         s += sprintf(s, " 64-bit");
7677                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7678         }
7679         return str;
7680 }
7681
7682 static void __devinit
7683 bnx2_init_napi(struct bnx2 *bp)
7684 {
7685         int i;
7686
7687         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7688                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7689                 int (*poll)(struct napi_struct *, int);
7690
7691                 if (i == 0)
7692                         poll = bnx2_poll;
7693                 else
7694                         poll = bnx2_poll_msix;
7695
7696                 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7697                 bnapi->bp = bp;
7698         }
7699 }
7700
7701 static int __devinit
7702 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7703 {
7704         static int version_printed = 0;
7705         struct net_device *dev = NULL;
7706         struct bnx2 *bp;
7707         int rc;
7708         char str[40];
7709         DECLARE_MAC_BUF(mac);
7710
7711         if (version_printed++ == 0)
7712                 printk(KERN_INFO "%s", version);
7713
7714         /* dev zeroed in init_etherdev */
7715         dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7716
7717         if (!dev)
7718                 return -ENOMEM;
7719
7720         rc = bnx2_init_board(pdev, dev);
7721         if (rc < 0) {
7722                 free_netdev(dev);
7723                 return rc;
7724         }
7725
7726         dev->open = bnx2_open;
7727         dev->hard_start_xmit = bnx2_start_xmit;
7728         dev->stop = bnx2_close;
7729         dev->get_stats = bnx2_get_stats;
7730         dev->set_rx_mode = bnx2_set_rx_mode;
7731         dev->do_ioctl = bnx2_ioctl;
7732         dev->set_mac_address = bnx2_change_mac_addr;
7733         dev->change_mtu = bnx2_change_mtu;
7734         dev->tx_timeout = bnx2_tx_timeout;
7735         dev->watchdog_timeo = TX_TIMEOUT;
7736 #ifdef BCM_VLAN
7737         dev->vlan_rx_register = bnx2_vlan_rx_register;
7738 #endif
7739         dev->ethtool_ops = &bnx2_ethtool_ops;
7740
7741         bp = netdev_priv(dev);
7742         bnx2_init_napi(bp);
7743
7744 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7745         dev->poll_controller = poll_bnx2;
7746 #endif
7747
7748         pci_set_drvdata(pdev, dev);
7749
7750         memcpy(dev->dev_addr, bp->mac_addr, 6);
7751         memcpy(dev->perm_addr, bp->mac_addr, 6);
7752
7753         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7754         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7755                 dev->features |= NETIF_F_IPV6_CSUM;
7756
7757 #ifdef BCM_VLAN
7758         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7759 #endif
7760         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7761         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7762                 dev->features |= NETIF_F_TSO6;
7763
7764         if ((rc = register_netdev(dev))) {
7765                 dev_err(&pdev->dev, "Cannot register net device\n");
7766                 if (bp->regview)
7767                         iounmap(bp->regview);
7768                 pci_release_regions(pdev);
7769                 pci_disable_device(pdev);
7770                 pci_set_drvdata(pdev, NULL);
7771                 free_netdev(dev);
7772                 return rc;
7773         }
7774
7775         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7776                 "IRQ %d, node addr %s\n",
7777                 dev->name,
7778                 board_info[ent->driver_data].name,
7779                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7780                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7781                 bnx2_bus_string(bp, str),
7782                 dev->base_addr,
7783                 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7784
7785         return 0;
7786 }
7787
7788 static void __devexit
7789 bnx2_remove_one(struct pci_dev *pdev)
7790 {
7791         struct net_device *dev = pci_get_drvdata(pdev);
7792         struct bnx2 *bp = netdev_priv(dev);
7793
7794         flush_scheduled_work();
7795
7796         unregister_netdev(dev);
7797
7798         if (bp->regview)
7799                 iounmap(bp->regview);
7800
7801         free_netdev(dev);
7802         pci_release_regions(pdev);
7803         pci_disable_device(pdev);
7804         pci_set_drvdata(pdev, NULL);
7805 }
7806
7807 static int
7808 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7809 {
7810         struct net_device *dev = pci_get_drvdata(pdev);
7811         struct bnx2 *bp = netdev_priv(dev);
7812
7813         /* PCI register 4 needs to be saved whether netif_running() or not.
7814          * MSI address and data need to be saved if using MSI and
7815          * netif_running().
7816          */
7817         pci_save_state(pdev);
7818         if (!netif_running(dev))
7819                 return 0;
7820
7821         flush_scheduled_work();
7822         bnx2_netif_stop(bp);
7823         netif_device_detach(dev);
7824         del_timer_sync(&bp->timer);
7825         bnx2_shutdown_chip(bp);
7826         bnx2_free_skbs(bp);
7827         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7828         return 0;
7829 }
7830
7831 static int
7832 bnx2_resume(struct pci_dev *pdev)
7833 {
7834         struct net_device *dev = pci_get_drvdata(pdev);
7835         struct bnx2 *bp = netdev_priv(dev);
7836
7837         pci_restore_state(pdev);
7838         if (!netif_running(dev))
7839                 return 0;
7840
7841         bnx2_set_power_state(bp, PCI_D0);
7842         netif_device_attach(dev);
7843         bnx2_init_nic(bp, 1);
7844         bnx2_netif_start(bp);
7845         return 0;
7846 }
7847
7848 /**
7849  * bnx2_io_error_detected - called when PCI error is detected
7850  * @pdev: Pointer to PCI device
7851  * @state: The current pci connection state
7852  *
7853  * This function is called after a PCI bus error affecting
7854  * this device has been detected.
7855  */
7856 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7857                                                pci_channel_state_t state)
7858 {
7859         struct net_device *dev = pci_get_drvdata(pdev);
7860         struct bnx2 *bp = netdev_priv(dev);
7861
7862         rtnl_lock();
7863         netif_device_detach(dev);
7864
7865         if (netif_running(dev)) {
7866                 bnx2_netif_stop(bp);
7867                 del_timer_sync(&bp->timer);
7868                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7869         }
7870
7871         pci_disable_device(pdev);
7872         rtnl_unlock();
7873
7874         /* Request a slot slot reset. */
7875         return PCI_ERS_RESULT_NEED_RESET;
7876 }
7877
7878 /**
7879  * bnx2_io_slot_reset - called after the pci bus has been reset.
7880  * @pdev: Pointer to PCI device
7881  *
7882  * Restart the card from scratch, as if from a cold-boot.
7883  */
7884 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7885 {
7886         struct net_device *dev = pci_get_drvdata(pdev);
7887         struct bnx2 *bp = netdev_priv(dev);
7888
7889         rtnl_lock();
7890         if (pci_enable_device(pdev)) {
7891                 dev_err(&pdev->dev,
7892                         "Cannot re-enable PCI device after reset.\n");
7893                 rtnl_unlock();
7894                 return PCI_ERS_RESULT_DISCONNECT;
7895         }
7896         pci_set_master(pdev);
7897         pci_restore_state(pdev);
7898
7899         if (netif_running(dev)) {
7900                 bnx2_set_power_state(bp, PCI_D0);
7901                 bnx2_init_nic(bp, 1);
7902         }
7903
7904         rtnl_unlock();
7905         return PCI_ERS_RESULT_RECOVERED;
7906 }
7907
7908 /**
7909  * bnx2_io_resume - called when traffic can start flowing again.
7910  * @pdev: Pointer to PCI device
7911  *
7912  * This callback is called when the error recovery driver tells us that
7913  * its OK to resume normal operation.
7914  */
7915 static void bnx2_io_resume(struct pci_dev *pdev)
7916 {
7917         struct net_device *dev = pci_get_drvdata(pdev);
7918         struct bnx2 *bp = netdev_priv(dev);
7919
7920         rtnl_lock();
7921         if (netif_running(dev))
7922                 bnx2_netif_start(bp);
7923
7924         netif_device_attach(dev);
7925         rtnl_unlock();
7926 }
7927
7928 static struct pci_error_handlers bnx2_err_handler = {
7929         .error_detected = bnx2_io_error_detected,
7930         .slot_reset     = bnx2_io_slot_reset,
7931         .resume         = bnx2_io_resume,
7932 };
7933
7934 static struct pci_driver bnx2_pci_driver = {
7935         .name           = DRV_MODULE_NAME,
7936         .id_table       = bnx2_pci_tbl,
7937         .probe          = bnx2_init_one,
7938         .remove         = __devexit_p(bnx2_remove_one),
7939         .suspend        = bnx2_suspend,
7940         .resume         = bnx2_resume,
7941         .err_handler    = &bnx2_err_handler,
7942 };
7943
7944 static int __init bnx2_init(void)
7945 {
7946         return pci_register_driver(&bnx2_pci_driver);
7947 }
7948
7949 static void __exit bnx2_cleanup(void)
7950 {
7951         pci_unregister_driver(&bnx2_pci_driver);
7952 }
7953
7954 module_init(bnx2_init);
7955 module_exit(bnx2_cleanup);
7956
7957
7958