SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004, 2005 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12 #include "bnx2.h"
  13 #include "bnx2_fw.h"
  14
  15 #define DRV_MODULE_NAME         "bnx2"
  16 #define PFX DRV_MODULE_NAME     ": "
  17 #define DRV_MODULE_VERSION      "1.4.30"
  18 #define DRV_MODULE_RELDATE      "October 11, 2005"
  19
  20 #define RUN_AT(x) (jiffies + (x))
  21
  22 /* Time in jiffies before concluding the transmitter is hung. */
  23 #define TX_TIMEOUT  (5*HZ)
  24
  25 static char version[] __devinitdata =
  26         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  27
  28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_VERSION(DRV_MODULE_VERSION);
  32
  33 static int disable_msi = 0;
  34
  35 module_param(disable_msi, int, 0);
  36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  37
  38 typedef enum {
  39         BCM5706 = 0,
  40         NC370T,
  41         NC370I,
  42         BCM5706S,
  43         NC370F,
  44         BCM5708,
  45         BCM5708S,
  46 } board_t;
  47
  48 /* indexed by board_t, above */
  49 static struct {
  50         char *name;
  51 } board_info[] __devinitdata = {
  52         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  53         { "HP NC370T Multifunction Gigabit Server Adapter" },
  54         { "HP NC370i Multifunction Gigabit Server Adapter" },
  55         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  56         { "HP NC370F Multifunction Gigabit Server Adapter" },
  57         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
  58         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
  59         };
  60
  61 static struct pci_device_id bnx2_pci_tbl[] = {
  62         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  63           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  64         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  65           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  66         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  68         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
  69           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
  70         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  71           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  72         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  73           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  74         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
  75           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
  76         { 0, }
  77 };
  78
  79 static struct flash_spec flash_table[] =
  80 {
  81         /* Slow EEPROM */
  82         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  83          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  84          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  85          "EEPROM - slow"},
  86         /* Expansion entry 0001 */
  87         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  88          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  89          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  90          "Entry 0001"},
  91         /* Saifun SA25F010 (non-buffered flash) */
  92         /* strap, cfg1, & write1 need updates */
  93         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  94          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  95          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  96          "Non-buffered flash (128kB)"},
  97         /* Saifun SA25F020 (non-buffered flash) */
  98         /* strap, cfg1, & write1 need updates */
  99         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 100          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 101          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 102          "Non-buffered flash (256kB)"},
 103         /* Expansion entry 0100 */
 104         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 105          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 106          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 107          "Entry 0100"},
 108         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 109         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 110          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 111          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 112          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 113         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 114         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 115          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 116          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 117          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 118         /* Saifun SA25F005 (non-buffered flash) */
 119         /* strap, cfg1, & write1 need updates */
 120         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 121          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 122          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 123          "Non-buffered flash (64kB)"},
 124         /* Fast EEPROM */
 125         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 126          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 127          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 128          "EEPROM - fast"},
 129         /* Expansion entry 1001 */
 130         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 131          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 132          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 133          "Entry 1001"},
 134         /* Expansion entry 1010 */
 135         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 136          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 137          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 138          "Entry 1010"},
 139         /* ATMEL AT45DB011B (buffered flash) */
 140         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 141          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 142          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 143          "Buffered flash (128kB)"},
 144         /* Expansion entry 1100 */
 145         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 146          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 147          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 148          "Entry 1100"},
 149         /* Expansion entry 1101 */
 150         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 151          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 152          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 153          "Entry 1101"},
 154         /* Ateml Expansion entry 1110 */
 155         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 156          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 157          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 158          "Entry 1110 (Atmel)"},
 159         /* ATMEL AT45DB021B (buffered flash) */
 160         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 161          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 162          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 163          "Buffered flash (256kB)"},
 164 };
 165
 166 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 167
 168 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 169 {
 170         u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
 171
 172         if (diff > MAX_TX_DESC_CNT)
 173                 diff = (diff & MAX_TX_DESC_CNT) - 1;
 174         return (bp->tx_ring_size - diff);
 175 }
 176
 177 static u32
 178 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 179 {
 180         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 181         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
 182 }
 183
 184 static void
 185 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 186 {
 187         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 188         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 189 }
 190
 191 static void
 192 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 193 {
 194         offset += cid_addr;
 195         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 196         REG_WR(bp, BNX2_CTX_DATA, val);
 197 }
 198
 199 static int
 200 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 201 {
 202         u32 val1;
 203         int i, ret;
 204
 205         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 206                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 207                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 208
 209                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 210                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 211
 212                 udelay(40);
 213         }
 214
 215         val1 = (bp->phy_addr << 21) | (reg << 16) |
 216                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 217                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 218         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 219
 220         for (i = 0; i < 50; i++) {
 221                 udelay(10);
 222
 223                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 224                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 225                         udelay(5);
 226
 227                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 228                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 229
 230                         break;
 231                 }
 232         }
 233
 234         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 235                 *val = 0x0;
 236                 ret = -EBUSY;
 237         }
 238         else {
 239                 *val = val1;
 240                 ret = 0;
 241         }
 242
 243         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 244                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 245                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 246
 247                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 248                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 249
 250                 udelay(40);
 251         }
 252
 253         return ret;
 254 }
 255
 256 static int
 257 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 258 {
 259         u32 val1;
 260         int i, ret;
 261
 262         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 263                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 264                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 265
 266                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 267                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 268
 269                 udelay(40);
 270         }
 271
 272         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 273                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 274                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 275         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 276
 277         for (i = 0; i < 50; i++) {
 278                 udelay(10);
 279
 280                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 281                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 282                         udelay(5);
 283                         break;
 284                 }
 285         }
 286
 287         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 288                 ret = -EBUSY;
 289         else
 290                 ret = 0;
 291
 292         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 293                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 294                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 295
 296                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 297                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 298
 299                 udelay(40);
 300         }
 301
 302         return ret;
 303 }
 304
 305 static void
 306 bnx2_disable_int(struct bnx2 *bp)
 307 {
 308         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 309                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 310         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 311 }
 312
 313 static void
 314 bnx2_enable_int(struct bnx2 *bp)
 315 {
 316         u32 val;
 317
 318         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 319                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 320
 321         val = REG_RD(bp, BNX2_HC_COMMAND);
 322         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
 323 }
 324
 325 static void
 326 bnx2_disable_int_sync(struct bnx2 *bp)
 327 {
 328         atomic_inc(&bp->intr_sem);
 329         bnx2_disable_int(bp);
 330         synchronize_irq(bp->pdev->irq);
 331 }
 332
 333 static void
 334 bnx2_netif_stop(struct bnx2 *bp)
 335 {
 336         bnx2_disable_int_sync(bp);
 337         if (netif_running(bp->dev)) {
 338                 netif_poll_disable(bp->dev);
 339                 netif_tx_disable(bp->dev);
 340                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 341         }
 342 }
 343
 344 static void
 345 bnx2_netif_start(struct bnx2 *bp)
 346 {
 347         if (atomic_dec_and_test(&bp->intr_sem)) {
 348                 if (netif_running(bp->dev)) {
 349                         netif_wake_queue(bp->dev);
 350                         netif_poll_enable(bp->dev);
 351                         bnx2_enable_int(bp);
 352                 }
 353         }
 354 }
 355
 356 static void
 357 bnx2_free_mem(struct bnx2 *bp)
 358 {
 359         if (bp->stats_blk) {
 360                 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
 361                                     bp->stats_blk, bp->stats_blk_mapping);
 362                 bp->stats_blk = NULL;
 363         }
 364         if (bp->status_blk) {
 365                 pci_free_consistent(bp->pdev, sizeof(struct status_block),
 366                                     bp->status_blk, bp->status_blk_mapping);
 367                 bp->status_blk = NULL;
 368         }
 369         if (bp->tx_desc_ring) {
 370                 pci_free_consistent(bp->pdev,
 371                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 372                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 373                 bp->tx_desc_ring = NULL;
 374         }
 375         kfree(bp->tx_buf_ring);
 376         bp->tx_buf_ring = NULL;
 377         if (bp->rx_desc_ring) {
 378                 pci_free_consistent(bp->pdev,
 379                                     sizeof(struct rx_bd) * RX_DESC_CNT,
 380                                     bp->rx_desc_ring, bp->rx_desc_mapping);
 381                 bp->rx_desc_ring = NULL;
 382         }
 383         kfree(bp->rx_buf_ring);
 384         bp->rx_buf_ring = NULL;
 385 }
 386
 387 static int
 388 bnx2_alloc_mem(struct bnx2 *bp)
 389 {
 390         bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 391                                      GFP_KERNEL);
 392         if (bp->tx_buf_ring == NULL)
 393                 return -ENOMEM;
 394
 395         memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
 396         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 397                                                 sizeof(struct tx_bd) *
 398                                                 TX_DESC_CNT,
 399                                                 &bp->tx_desc_mapping);
 400         if (bp->tx_desc_ring == NULL)
 401                 goto alloc_mem_err;
 402
 403         bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
 404                                      GFP_KERNEL);
 405         if (bp->rx_buf_ring == NULL)
 406                 goto alloc_mem_err;
 407
 408         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
 409         bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
 410                                                 sizeof(struct rx_bd) *
 411                                                 RX_DESC_CNT,
 412                                                 &bp->rx_desc_mapping);
 413         if (bp->rx_desc_ring == NULL)
 414                 goto alloc_mem_err;
 415
 416         bp->status_blk = pci_alloc_consistent(bp->pdev,
 417                                               sizeof(struct status_block),
 418                                               &bp->status_blk_mapping);
 419         if (bp->status_blk == NULL)
 420                 goto alloc_mem_err;
 421
 422         memset(bp->status_blk, 0, sizeof(struct status_block));
 423
 424         bp->stats_blk = pci_alloc_consistent(bp->pdev,
 425                                              sizeof(struct statistics_block),
 426                                              &bp->stats_blk_mapping);
 427         if (bp->stats_blk == NULL)
 428                 goto alloc_mem_err;
 429
 430         memset(bp->stats_blk, 0, sizeof(struct statistics_block));
 431
 432         return 0;
 433
 434 alloc_mem_err:
 435         bnx2_free_mem(bp);
 436         return -ENOMEM;
 437 }
 438
 439 static void
 440 bnx2_report_fw_link(struct bnx2 *bp)
 441 {
 442         u32 fw_link_status = 0;
 443
 444         if (bp->link_up) {
 445                 u32 bmsr;
 446
 447                 switch (bp->line_speed) {
 448                 case SPEED_10:
 449                         if (bp->duplex == DUPLEX_HALF)
 450                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 451                         else
 452                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 453                         break;
 454                 case SPEED_100:
 455                         if (bp->duplex == DUPLEX_HALF)
 456                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 457                         else
 458                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 459                         break;
 460                 case SPEED_1000:
 461                         if (bp->duplex == DUPLEX_HALF)
 462                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 463                         else
 464                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 465                         break;
 466                 case SPEED_2500:
 467                         if (bp->duplex == DUPLEX_HALF)
 468                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 469                         else
 470                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 471                         break;
 472                 }
 473
 474                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 475
 476                 if (bp->autoneg) {
 477                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 478
 479                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 480                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 481
 482                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 483                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
 484                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 485                         else
 486                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 487                 }
 488         }
 489         else
 490                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 491
 492         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
 493 }
 494
 495 static void
 496 bnx2_report_link(struct bnx2 *bp)
 497 {
 498         if (bp->link_up) {
 499                 netif_carrier_on(bp->dev);
 500                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
 501
 502                 printk("%d Mbps ", bp->line_speed);
 503
 504                 if (bp->duplex == DUPLEX_FULL)
 505                         printk("full duplex");
 506                 else
 507                         printk("half duplex");
 508
 509                 if (bp->flow_ctrl) {
 510                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 511                                 printk(", receive ");
 512                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 513                                         printk("& transmit ");
 514                         }
 515                         else {
 516                                 printk(", transmit ");
 517                         }
 518                         printk("flow control ON");
 519                 }
 520                 printk("\n");
 521         }
 522         else {
 523                 netif_carrier_off(bp->dev);
 524                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
 525         }
 526
 527         bnx2_report_fw_link(bp);
 528 }
 529
 530 static void
 531 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 532 {
 533         u32 local_adv, remote_adv;
 534
 535         bp->flow_ctrl = 0;
 536         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 537                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 538
 539                 if (bp->duplex == DUPLEX_FULL) {
 540                         bp->flow_ctrl = bp->req_flow_ctrl;
 541                 }
 542                 return;
 543         }
 544
 545         if (bp->duplex != DUPLEX_FULL) {
 546                 return;
 547         }
 548
 549         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 550             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 551                 u32 val;
 552
 553                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 554                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 555                         bp->flow_ctrl |= FLOW_CTRL_TX;
 556                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 557                         bp->flow_ctrl |= FLOW_CTRL_RX;
 558                 return;
 559         }
 560
 561         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 562         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 563
 564         if (bp->phy_flags & PHY_SERDES_FLAG) {
 565                 u32 new_local_adv = 0;
 566                 u32 new_remote_adv = 0;
 567
 568                 if (local_adv & ADVERTISE_1000XPAUSE)
 569                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 570                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 571                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 572                 if (remote_adv & ADVERTISE_1000XPAUSE)
 573                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 574                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 575                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 576
 577                 local_adv = new_local_adv;
 578                 remote_adv = new_remote_adv;
 579         }
 580
 581         /* See Table 28B-3 of 802.3ab-1999 spec. */
 582         if (local_adv & ADVERTISE_PAUSE_CAP) {
 583                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 584                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 585                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 586                         }
 587                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 588                                 bp->flow_ctrl = FLOW_CTRL_RX;
 589                         }
 590                 }
 591                 else {
 592                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 593                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 594                         }
 595                 }
 596         }
 597         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 598                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 599                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 600
 601                         bp->flow_ctrl = FLOW_CTRL_TX;
 602                 }
 603         }
 604 }
 605
 606 static int
 607 bnx2_5708s_linkup(struct bnx2 *bp)
 608 {
 609         u32 val;
 610
 611         bp->link_up = 1;
 612         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 613         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 614                 case BCM5708S_1000X_STAT1_SPEED_10:
 615                         bp->line_speed = SPEED_10;
 616                         break;
 617                 case BCM5708S_1000X_STAT1_SPEED_100:
 618                         bp->line_speed = SPEED_100;
 619                         break;
 620                 case BCM5708S_1000X_STAT1_SPEED_1G:
 621                         bp->line_speed = SPEED_1000;
 622                         break;
 623                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 624                         bp->line_speed = SPEED_2500;
 625                         break;
 626         }
 627         if (val & BCM5708S_1000X_STAT1_FD)
 628                 bp->duplex = DUPLEX_FULL;
 629         else
 630                 bp->duplex = DUPLEX_HALF;
 631
 632         return 0;
 633 }
 634
 635 static int
 636 bnx2_5706s_linkup(struct bnx2 *bp)
 637 {
 638         u32 bmcr, local_adv, remote_adv, common;
 639
 640         bp->link_up = 1;
 641         bp->line_speed = SPEED_1000;
 642
 643         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 644         if (bmcr & BMCR_FULLDPLX) {
 645                 bp->duplex = DUPLEX_FULL;
 646         }
 647         else {
 648                 bp->duplex = DUPLEX_HALF;
 649         }
 650
 651         if (!(bmcr & BMCR_ANENABLE)) {
 652                 return 0;
 653         }
 654
 655         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 656         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 657
 658         common = local_adv & remote_adv;
 659         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 660
 661                 if (common & ADVERTISE_1000XFULL) {
 662                         bp->duplex = DUPLEX_FULL;
 663                 }
 664                 else {
 665                         bp->duplex = DUPLEX_HALF;
 666                 }
 667         }
 668
 669         return 0;
 670 }
 671
 672 static int
 673 bnx2_copper_linkup(struct bnx2 *bp)
 674 {
 675         u32 bmcr;
 676
 677         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 678         if (bmcr & BMCR_ANENABLE) {
 679                 u32 local_adv, remote_adv, common;
 680
 681                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 682                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 683
 684                 common = local_adv & (remote_adv >> 2);
 685                 if (common & ADVERTISE_1000FULL) {
 686                         bp->line_speed = SPEED_1000;
 687                         bp->duplex = DUPLEX_FULL;
 688                 }
 689                 else if (common & ADVERTISE_1000HALF) {
 690                         bp->line_speed = SPEED_1000;
 691                         bp->duplex = DUPLEX_HALF;
 692                 }
 693                 else {
 694                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 695                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 696
 697                         common = local_adv & remote_adv;
 698                         if (common & ADVERTISE_100FULL) {
 699                                 bp->line_speed = SPEED_100;
 700                                 bp->duplex = DUPLEX_FULL;
 701                         }
 702                         else if (common & ADVERTISE_100HALF) {
 703                                 bp->line_speed = SPEED_100;
 704                                 bp->duplex = DUPLEX_HALF;
 705                         }
 706                         else if (common & ADVERTISE_10FULL) {
 707                                 bp->line_speed = SPEED_10;
 708                                 bp->duplex = DUPLEX_FULL;
 709                         }
 710                         else if (common & ADVERTISE_10HALF) {
 711                                 bp->line_speed = SPEED_10;
 712                                 bp->duplex = DUPLEX_HALF;
 713                         }
 714                         else {
 715                                 bp->line_speed = 0;
 716                                 bp->link_up = 0;
 717                         }
 718                 }
 719         }
 720         else {
 721                 if (bmcr & BMCR_SPEED100) {
 722                         bp->line_speed = SPEED_100;
 723                 }
 724                 else {
 725                         bp->line_speed = SPEED_10;
 726                 }
 727                 if (bmcr & BMCR_FULLDPLX) {
 728                         bp->duplex = DUPLEX_FULL;
 729                 }
 730                 else {
 731                         bp->duplex = DUPLEX_HALF;
 732                 }
 733         }
 734
 735         return 0;
 736 }
 737
 738 static int
 739 bnx2_set_mac_link(struct bnx2 *bp)
 740 {
 741         u32 val;
 742
 743         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 744         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 745                 (bp->duplex == DUPLEX_HALF)) {
 746                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 747         }
 748
 749         /* Configure the EMAC mode register. */
 750         val = REG_RD(bp, BNX2_EMAC_MODE);
 751
 752         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 753                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
 754                 BNX2_EMAC_MODE_25G);
 755
 756         if (bp->link_up) {
 757                 switch (bp->line_speed) {
 758                         case SPEED_10:
 759                                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
 760                                         val |= BNX2_EMAC_MODE_PORT_MII_10;
 761                                         break;
 762                                 }
 763                                 /* fall through */
 764                         case SPEED_100:
 765                                 val |= BNX2_EMAC_MODE_PORT_MII;
 766                                 break;
 767                         case SPEED_2500:
 768                                 val |= BNX2_EMAC_MODE_25G;
 769                                 /* fall through */
 770                         case SPEED_1000:
 771                                 val |= BNX2_EMAC_MODE_PORT_GMII;
 772                                 break;
 773                 }
 774         }
 775         else {
 776                 val |= BNX2_EMAC_MODE_PORT_GMII;
 777         }
 778
 779         /* Set the MAC to operate in the appropriate duplex mode. */
 780         if (bp->duplex == DUPLEX_HALF)
 781                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 782         REG_WR(bp, BNX2_EMAC_MODE, val);
 783
 784         /* Enable/disable rx PAUSE. */
 785         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 786
 787         if (bp->flow_ctrl & FLOW_CTRL_RX)
 788                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 789         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 790
 791         /* Enable/disable tx PAUSE. */
 792         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 793         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 794
 795         if (bp->flow_ctrl & FLOW_CTRL_TX)
 796                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 797         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 798
 799         /* Acknowledge the interrupt. */
 800         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 801
 802         return 0;
 803 }
 804
 805 static int
 806 bnx2_set_link(struct bnx2 *bp)
 807 {
 808         u32 bmsr;
 809         u8 link_up;
 810
 811         if (bp->loopback == MAC_LOOPBACK) {
 812                 bp->link_up = 1;
 813                 return 0;
 814         }
 815
 816         link_up = bp->link_up;
 817
 818         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 819         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 820
 821         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 822             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
 823                 u32 val;
 824
 825                 val = REG_RD(bp, BNX2_EMAC_STATUS);
 826                 if (val & BNX2_EMAC_STATUS_LINK)
 827                         bmsr |= BMSR_LSTATUS;
 828                 else
 829                         bmsr &= ~BMSR_LSTATUS;
 830         }
 831
 832         if (bmsr & BMSR_LSTATUS) {
 833                 bp->link_up = 1;
 834
 835                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 836                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
 837                                 bnx2_5706s_linkup(bp);
 838                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
 839                                 bnx2_5708s_linkup(bp);
 840                 }
 841                 else {
 842                         bnx2_copper_linkup(bp);
 843                 }
 844                 bnx2_resolve_flow_ctrl(bp);
 845         }
 846         else {
 847                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 848                         (bp->autoneg & AUTONEG_SPEED)) {
 849
 850                         u32 bmcr;
 851
 852                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 853                         if (!(bmcr & BMCR_ANENABLE)) {
 854                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 855                                         BMCR_ANENABLE);
 856                         }
 857                 }
 858                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 859                 bp->link_up = 0;
 860         }
 861
 862         if (bp->link_up != link_up) {
 863                 bnx2_report_link(bp);
 864         }
 865
 866         bnx2_set_mac_link(bp);
 867
 868         return 0;
 869 }
 870
 871 static int
 872 bnx2_reset_phy(struct bnx2 *bp)
 873 {
 874         int i;
 875         u32 reg;
 876
 877         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
 878
 879 #define PHY_RESET_MAX_WAIT 100
 880         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
 881                 udelay(10);
 882
 883                 bnx2_read_phy(bp, MII_BMCR, &reg);
 884                 if (!(reg & BMCR_RESET)) {
 885                         udelay(20);
 886                         break;
 887                 }
 888         }
 889         if (i == PHY_RESET_MAX_WAIT) {
 890                 return -EBUSY;
 891         }
 892         return 0;
 893 }
 894
 895 static u32
 896 bnx2_phy_get_pause_adv(struct bnx2 *bp)
 897 {
 898         u32 adv = 0;
 899
 900         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
 901                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
 902
 903                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 904                         adv = ADVERTISE_1000XPAUSE;
 905                 }
 906                 else {
 907                         adv = ADVERTISE_PAUSE_CAP;
 908                 }
 909         }
 910         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
 911                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 912                         adv = ADVERTISE_1000XPSE_ASYM;
 913                 }
 914                 else {
 915                         adv = ADVERTISE_PAUSE_ASYM;
 916                 }
 917         }
 918         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
 919                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 920                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
 921                 }
 922                 else {
 923                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 924                 }
 925         }
 926         return adv;
 927 }
 928
 929 static int
 930 bnx2_setup_serdes_phy(struct bnx2 *bp)
 931 {
 932         u32 adv, bmcr, up1;
 933         u32 new_adv = 0;
 934
 935         if (!(bp->autoneg & AUTONEG_SPEED)) {
 936                 u32 new_bmcr;
 937                 int force_link_down = 0;
 938
 939                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
 940                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
 941                         if (up1 & BCM5708S_UP1_2G5) {
 942                                 up1 &= ~BCM5708S_UP1_2G5;
 943                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
 944                                 force_link_down = 1;
 945                         }
 946                 }
 947
 948                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 949                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
 950
 951                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
 952                 new_bmcr = bmcr & ~BMCR_ANENABLE;
 953                 new_bmcr |= BMCR_SPEED1000;
 954                 if (bp->req_duplex == DUPLEX_FULL) {
 955                         adv |= ADVERTISE_1000XFULL;
 956                         new_bmcr |= BMCR_FULLDPLX;
 957                 }
 958                 else {
 959                         adv |= ADVERTISE_1000XHALF;
 960                         new_bmcr &= ~BMCR_FULLDPLX;
 961                 }
 962                 if ((new_bmcr != bmcr) || (force_link_down)) {
 963                         /* Force a link down visible on the other side */
 964                         if (bp->link_up) {
 965                                 bnx2_write_phy(bp, MII_ADVERTISE, adv &
 966                                                ~(ADVERTISE_1000XFULL |
 967                                                  ADVERTISE_1000XHALF));
 968                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 969                                         BMCR_ANRESTART | BMCR_ANENABLE);
 970
 971                                 bp->link_up = 0;
 972                                 netif_carrier_off(bp->dev);
 973                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 974                         }
 975                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
 976                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 977                 }
 978                 return 0;
 979         }
 980
 981         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
 982                 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
 983                 up1 |= BCM5708S_UP1_2G5;
 984                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
 985         }
 986
 987         if (bp->advertising & ADVERTISED_1000baseT_Full)
 988                 new_adv |= ADVERTISE_1000XFULL;
 989
 990         new_adv |= bnx2_phy_get_pause_adv(bp);
 991
 992         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 993         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 994
 995         bp->serdes_an_pending = 0;
 996         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
 997                 /* Force a link down visible on the other side */
 998                 if (bp->link_up) {
 999                         int i;
1000
1001                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1002                         for (i = 0; i < 110; i++) {
1003                                 udelay(100);
1004                         }
1005                 }
1006
1007                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1008                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1009                         BMCR_ANENABLE);
1010                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1011                         /* Speed up link-up time when the link partner
1012                          * does not autonegotiate which is very common
1013                          * in blade servers. Some blade servers use
1014                          * IPMI for kerboard input and it's important
1015                          * to minimize link disruptions. Autoneg. involves
1016                          * exchanging base pages plus 3 next pages and
1017                          * normally completes in about 120 msec.
1018                          */
1019                         bp->current_interval = SERDES_AN_TIMEOUT;
1020                         bp->serdes_an_pending = 1;
1021                         mod_timer(&bp->timer, jiffies + bp->current_interval);
1022                 }
1023         }
1024
1025         return 0;
1026 }
1027
1028 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1029         (ADVERTISED_1000baseT_Full)
1030
1031 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1032         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1033         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1034         ADVERTISED_1000baseT_Full)
1035
1036 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1037         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1038
1039 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1040
1041 static int
1042 bnx2_setup_copper_phy(struct bnx2 *bp)
1043 {
1044         u32 bmcr;
1045         u32 new_bmcr;
1046
1047         bnx2_read_phy(bp, MII_BMCR, &bmcr);
1048
1049         if (bp->autoneg & AUTONEG_SPEED) {
1050                 u32 adv_reg, adv1000_reg;
1051                 u32 new_adv_reg = 0;
1052                 u32 new_adv1000_reg = 0;
1053
1054                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1055                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1056                         ADVERTISE_PAUSE_ASYM);
1057
1058                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1059                 adv1000_reg &= PHY_ALL_1000_SPEED;
1060
1061                 if (bp->advertising & ADVERTISED_10baseT_Half)
1062                         new_adv_reg |= ADVERTISE_10HALF;
1063                 if (bp->advertising & ADVERTISED_10baseT_Full)
1064                         new_adv_reg |= ADVERTISE_10FULL;
1065                 if (bp->advertising & ADVERTISED_100baseT_Half)
1066                         new_adv_reg |= ADVERTISE_100HALF;
1067                 if (bp->advertising & ADVERTISED_100baseT_Full)
1068                         new_adv_reg |= ADVERTISE_100FULL;
1069                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1070                         new_adv1000_reg |= ADVERTISE_1000FULL;
1071
1072                 new_adv_reg |= ADVERTISE_CSMA;
1073
1074                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1075
1076                 if ((adv1000_reg != new_adv1000_reg) ||
1077                         (adv_reg != new_adv_reg) ||
1078                         ((bmcr & BMCR_ANENABLE) == 0)) {
1079
1080                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1081                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1082                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1083                                 BMCR_ANENABLE);
1084                 }
1085                 else if (bp->link_up) {
1086                         /* Flow ctrl may have changed from auto to forced */
1087                         /* or vice-versa. */
1088
1089                         bnx2_resolve_flow_ctrl(bp);
1090                         bnx2_set_mac_link(bp);
1091                 }
1092                 return 0;
1093         }
1094
1095         new_bmcr = 0;
1096         if (bp->req_line_speed == SPEED_100) {
1097                 new_bmcr |= BMCR_SPEED100;
1098         }
1099         if (bp->req_duplex == DUPLEX_FULL) {
1100                 new_bmcr |= BMCR_FULLDPLX;
1101         }
1102         if (new_bmcr != bmcr) {
1103                 u32 bmsr;
1104                 int i = 0;
1105
1106                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1107                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1108
1109                 if (bmsr & BMSR_LSTATUS) {
1110                         /* Force link down */
1111                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1112                         do {
1113                                 udelay(100);
1114                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1115                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1116                                 i++;
1117                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1118                 }
1119
1120                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1121
1122                 /* Normally, the new speed is setup after the link has
1123                  * gone down and up again. In some cases, link will not go
1124                  * down so we need to set up the new speed here.
1125                  */
1126                 if (bmsr & BMSR_LSTATUS) {
1127                         bp->line_speed = bp->req_line_speed;
1128                         bp->duplex = bp->req_duplex;
1129                         bnx2_resolve_flow_ctrl(bp);
1130                         bnx2_set_mac_link(bp);
1131                 }
1132         }
1133         return 0;
1134 }
1135
1136 static int
1137 bnx2_setup_phy(struct bnx2 *bp)
1138 {
1139         if (bp->loopback == MAC_LOOPBACK)
1140                 return 0;
1141
1142         if (bp->phy_flags & PHY_SERDES_FLAG) {
1143                 return (bnx2_setup_serdes_phy(bp));
1144         }
1145         else {
1146                 return (bnx2_setup_copper_phy(bp));
1147         }
1148 }
1149
1150 static int
1151 bnx2_init_5708s_phy(struct bnx2 *bp)
1152 {
1153         u32 val;
1154
1155         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1156         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1157         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1158
1159         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1160         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1161         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1162
1163         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1164         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1165         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1166
1167         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1168                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1169                 val |= BCM5708S_UP1_2G5;
1170                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1171         }
1172
1173         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1174             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1175             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1176                 /* increase tx signal amplitude */
1177                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1178                                BCM5708S_BLK_ADDR_TX_MISC);
1179                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1180                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1181                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1182                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1183         }
1184
1185         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1186               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1187
1188         if (val) {
1189                 u32 is_backplane;
1190
1191                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1192                                           BNX2_SHARED_HW_CFG_CONFIG);
1193                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1194                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1195                                        BCM5708S_BLK_ADDR_TX_MISC);
1196                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1197                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1198                                        BCM5708S_BLK_ADDR_DIG);
1199                 }
1200         }
1201         return 0;
1202 }
1203
1204 static int
1205 bnx2_init_5706s_phy(struct bnx2 *bp)
1206 {
1207         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1208
1209         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1210                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1211         }
1212
1213         if (bp->dev->mtu > 1500) {
1214                 u32 val;
1215
1216                 /* Set extended packet length bit */
1217                 bnx2_write_phy(bp, 0x18, 0x7);
1218                 bnx2_read_phy(bp, 0x18, &val);
1219                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1220
1221                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1222                 bnx2_read_phy(bp, 0x1c, &val);
1223                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1224         }
1225         else {
1226                 u32 val;
1227
1228                 bnx2_write_phy(bp, 0x18, 0x7);
1229                 bnx2_read_phy(bp, 0x18, &val);
1230                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1231
1232                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1233                 bnx2_read_phy(bp, 0x1c, &val);
1234                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1235         }
1236
1237         return 0;
1238 }
1239
1240 static int
1241 bnx2_init_copper_phy(struct bnx2 *bp)
1242 {
1243         u32 val;
1244
1245         bp->phy_flags |= PHY_CRC_FIX_FLAG;
1246
1247         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1248                 bnx2_write_phy(bp, 0x18, 0x0c00);
1249                 bnx2_write_phy(bp, 0x17, 0x000a);
1250                 bnx2_write_phy(bp, 0x15, 0x310b);
1251                 bnx2_write_phy(bp, 0x17, 0x201f);
1252                 bnx2_write_phy(bp, 0x15, 0x9506);
1253                 bnx2_write_phy(bp, 0x17, 0x401f);
1254                 bnx2_write_phy(bp, 0x15, 0x14e2);
1255                 bnx2_write_phy(bp, 0x18, 0x0400);
1256         }
1257
1258         if (bp->dev->mtu > 1500) {
1259                 /* Set extended packet length bit */
1260                 bnx2_write_phy(bp, 0x18, 0x7);
1261                 bnx2_read_phy(bp, 0x18, &val);
1262                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1263
1264                 bnx2_read_phy(bp, 0x10, &val);
1265                 bnx2_write_phy(bp, 0x10, val | 0x1);
1266         }
1267         else {
1268                 bnx2_write_phy(bp, 0x18, 0x7);
1269                 bnx2_read_phy(bp, 0x18, &val);
1270                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1271
1272                 bnx2_read_phy(bp, 0x10, &val);
1273                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1274         }
1275
1276         /* ethernet@wirespeed */
1277         bnx2_write_phy(bp, 0x18, 0x7007);
1278         bnx2_read_phy(bp, 0x18, &val);
1279         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1280         return 0;
1281 }
1282
1283
1284 static int
1285 bnx2_init_phy(struct bnx2 *bp)
1286 {
1287         u32 val;
1288         int rc = 0;
1289
1290         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1291         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1292
1293         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1294
1295         bnx2_reset_phy(bp);
1296
1297         bnx2_read_phy(bp, MII_PHYSID1, &val);
1298         bp->phy_id = val << 16;
1299         bnx2_read_phy(bp, MII_PHYSID2, &val);
1300         bp->phy_id |= val & 0xffff;
1301
1302         if (bp->phy_flags & PHY_SERDES_FLAG) {
1303                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1304                         rc = bnx2_init_5706s_phy(bp);
1305                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1306                         rc = bnx2_init_5708s_phy(bp);
1307         }
1308         else {
1309                 rc = bnx2_init_copper_phy(bp);
1310         }
1311
1312         bnx2_setup_phy(bp);
1313
1314         return rc;
1315 }
1316
1317 static int
1318 bnx2_set_mac_loopback(struct bnx2 *bp)
1319 {
1320         u32 mac_mode;
1321
1322         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1323         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1324         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1325         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1326         bp->link_up = 1;
1327         return 0;
1328 }
1329
1330 static int
1331 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1332 {
1333         int i;
1334         u32 val;
1335
1336         bp->fw_wr_seq++;
1337         msg_data |= bp->fw_wr_seq;
1338
1339         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1340
1341         /* wait for an acknowledgement. */
1342         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1343                 msleep(10);
1344
1345                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1346
1347                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1348                         break;
1349         }
1350         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1351                 return 0;
1352
1353         /* If we timed out, inform the firmware that this is the case. */
1354         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1355                 if (!silent)
1356                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
1357                                             "%x\n", msg_data);
1358
1359                 msg_data &= ~BNX2_DRV_MSG_CODE;
1360                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1361
1362                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1363
1364                 return -EBUSY;
1365         }
1366
1367         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1368                 return -EIO;
1369
1370         return 0;
1371 }
1372
1373 static void
1374 bnx2_init_context(struct bnx2 *bp)
1375 {
1376         u32 vcid;
1377
1378         vcid = 96;
1379         while (vcid) {
1380                 u32 vcid_addr, pcid_addr, offset;
1381
1382                 vcid--;
1383
1384                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1385                         u32 new_vcid;
1386
1387                         vcid_addr = GET_PCID_ADDR(vcid);
1388                         if (vcid & 0x8) {
1389                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1390                         }
1391                         else {
1392                                 new_vcid = vcid;
1393                         }
1394                         pcid_addr = GET_PCID_ADDR(new_vcid);
1395                 }
1396                 else {
1397                         vcid_addr = GET_CID_ADDR(vcid);
1398                         pcid_addr = vcid_addr;
1399                 }
1400
1401                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1402                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1403
1404                 /* Zero out the context. */
1405                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1406                         CTX_WR(bp, 0x00, offset, 0);
1407                 }
1408
1409                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1410                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1411         }
1412 }
1413
1414 static int
1415 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1416 {
1417         u16 *good_mbuf;
1418         u32 good_mbuf_cnt;
1419         u32 val;
1420
1421         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1422         if (good_mbuf == NULL) {
1423                 printk(KERN_ERR PFX "Failed to allocate memory in "
1424                                     "bnx2_alloc_bad_rbuf\n");
1425                 return -ENOMEM;
1426         }
1427
1428         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1429                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1430
1431         good_mbuf_cnt = 0;
1432
1433         /* Allocate a bunch of mbufs and save the good ones in an array. */
1434         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1435         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1436                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1437
1438                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1439
1440                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1441
1442                 /* The addresses with Bit 9 set are bad memory blocks. */
1443                 if (!(val & (1 << 9))) {
1444                         good_mbuf[good_mbuf_cnt] = (u16) val;
1445                         good_mbuf_cnt++;
1446                 }
1447
1448                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1449         }
1450
1451         /* Free the good ones back to the mbuf pool thus discarding
1452          * all the bad ones. */
1453         while (good_mbuf_cnt) {
1454                 good_mbuf_cnt--;
1455
1456                 val = good_mbuf[good_mbuf_cnt];
1457                 val = (val << 9) | val | 1;
1458
1459                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1460         }
1461         kfree(good_mbuf);
1462         return 0;
1463 }
1464
1465 static void
1466 bnx2_set_mac_addr(struct bnx2 *bp)
1467 {
1468         u32 val;
1469         u8 *mac_addr = bp->dev->dev_addr;
1470
1471         val = (mac_addr[0] << 8) | mac_addr[1];
1472
1473         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1474
1475         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1476                 (mac_addr[4] << 8) | mac_addr[5];
1477
1478         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1479 }
1480
1481 static inline int
1482 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1483 {
1484         struct sk_buff *skb;
1485         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1486         dma_addr_t mapping;
1487         struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1488         unsigned long align;
1489
1490         skb = dev_alloc_skb(bp->rx_buf_size);
1491         if (skb == NULL) {
1492                 return -ENOMEM;
1493         }
1494
1495         if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1496                 skb_reserve(skb, 8 - align);
1497         }
1498
1499         skb->dev = bp->dev;
1500         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1501                 PCI_DMA_FROMDEVICE);
1502
1503         rx_buf->skb = skb;
1504         pci_unmap_addr_set(rx_buf, mapping, mapping);
1505
1506         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1507         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1508
1509         bp->rx_prod_bseq += bp->rx_buf_use_size;
1510
1511         return 0;
1512 }
1513
1514 static void
1515 bnx2_phy_int(struct bnx2 *bp)
1516 {
1517         u32 new_link_state, old_link_state;
1518
1519         new_link_state = bp->status_blk->status_attn_bits &
1520                 STATUS_ATTN_BITS_LINK_STATE;
1521         old_link_state = bp->status_blk->status_attn_bits_ack &
1522                 STATUS_ATTN_BITS_LINK_STATE;
1523         if (new_link_state != old_link_state) {
1524                 if (new_link_state) {
1525                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1526                                 STATUS_ATTN_BITS_LINK_STATE);
1527                 }
1528                 else {
1529                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1530                                 STATUS_ATTN_BITS_LINK_STATE);
1531                 }
1532                 bnx2_set_link(bp);
1533         }
1534 }
1535
1536 static void
1537 bnx2_tx_int(struct bnx2 *bp)
1538 {
1539         struct status_block *sblk = bp->status_blk;
1540         u16 hw_cons, sw_cons, sw_ring_cons;
1541         int tx_free_bd = 0;
1542
1543         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1544         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1545                 hw_cons++;
1546         }
1547         sw_cons = bp->tx_cons;
1548
1549         while (sw_cons != hw_cons) {
1550                 struct sw_bd *tx_buf;
1551                 struct sk_buff *skb;
1552                 int i, last;
1553
1554                 sw_ring_cons = TX_RING_IDX(sw_cons);
1555
1556                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1557                 skb = tx_buf->skb;
1558 #ifdef BCM_TSO
1559                 /* partial BD completions possible with TSO packets */
1560                 if (skb_shinfo(skb)->tso_size) {
1561                         u16 last_idx, last_ring_idx;
1562
1563                         last_idx = sw_cons +
1564                                 skb_shinfo(skb)->nr_frags + 1;
1565                         last_ring_idx = sw_ring_cons +
1566                                 skb_shinfo(skb)->nr_frags + 1;
1567                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1568                                 last_idx++;
1569                         }
1570                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1571                                 break;
1572                         }
1573                 }
1574 #endif
1575                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1576                         skb_headlen(skb), PCI_DMA_TODEVICE);
1577
1578                 tx_buf->skb = NULL;
1579                 last = skb_shinfo(skb)->nr_frags;
1580
1581                 for (i = 0; i < last; i++) {
1582                         sw_cons = NEXT_TX_BD(sw_cons);
1583
1584                         pci_unmap_page(bp->pdev,
1585                                 pci_unmap_addr(
1586                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1587                                         mapping),
1588                                 skb_shinfo(skb)->frags[i].size,
1589                                 PCI_DMA_TODEVICE);
1590                 }
1591
1592                 sw_cons = NEXT_TX_BD(sw_cons);
1593
1594                 tx_free_bd += last + 1;
1595
1596                 dev_kfree_skb_irq(skb);
1597
1598                 hw_cons = bp->hw_tx_cons =
1599                         sblk->status_tx_quick_consumer_index0;
1600
1601                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1602                         hw_cons++;
1603                 }
1604         }
1605
1606         bp->tx_cons = sw_cons;
1607
1608         if (unlikely(netif_queue_stopped(bp->dev))) {
1609                 spin_lock(&bp->tx_lock);
1610                 if ((netif_queue_stopped(bp->dev)) &&
1611                     (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1612
1613                         netif_wake_queue(bp->dev);
1614                 }
1615                 spin_unlock(&bp->tx_lock);
1616         }
1617 }
1618
1619 static inline void
1620 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1621         u16 cons, u16 prod)
1622 {
1623         struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1624         struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1625         struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1626         struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1627
1628         pci_dma_sync_single_for_device(bp->pdev,
1629                 pci_unmap_addr(cons_rx_buf, mapping),
1630                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1631
1632         prod_rx_buf->skb = cons_rx_buf->skb;
1633         pci_unmap_addr_set(prod_rx_buf, mapping,
1634                         pci_unmap_addr(cons_rx_buf, mapping));
1635
1636         memcpy(prod_bd, cons_bd, 8);
1637
1638         bp->rx_prod_bseq += bp->rx_buf_use_size;
1639
1640 }
1641
1642 static int
1643 bnx2_rx_int(struct bnx2 *bp, int budget)
1644 {
1645         struct status_block *sblk = bp->status_blk;
1646         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1647         struct l2_fhdr *rx_hdr;
1648         int rx_pkt = 0;
1649
1650         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1651         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1652                 hw_cons++;
1653         }
1654         sw_cons = bp->rx_cons;
1655         sw_prod = bp->rx_prod;
1656
1657         /* Memory barrier necessary as speculative reads of the rx
1658          * buffer can be ahead of the index in the status block
1659          */
1660         rmb();
1661         while (sw_cons != hw_cons) {
1662                 unsigned int len;
1663                 u32 status;
1664                 struct sw_bd *rx_buf;
1665                 struct sk_buff *skb;
1666
1667                 sw_ring_cons = RX_RING_IDX(sw_cons);
1668                 sw_ring_prod = RX_RING_IDX(sw_prod);
1669
1670                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1671                 skb = rx_buf->skb;
1672                 pci_dma_sync_single_for_cpu(bp->pdev,
1673                         pci_unmap_addr(rx_buf, mapping),
1674                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1675
1676                 rx_hdr = (struct l2_fhdr *) skb->data;
1677                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1678
1679                 if ((status = rx_hdr->l2_fhdr_status) &
1680                         (L2_FHDR_ERRORS_BAD_CRC |
1681                         L2_FHDR_ERRORS_PHY_DECODE |
1682                         L2_FHDR_ERRORS_ALIGNMENT |
1683                         L2_FHDR_ERRORS_TOO_SHORT |
1684                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1685
1686                         goto reuse_rx;
1687                 }
1688
1689                 /* Since we don't have a jumbo ring, copy small packets
1690                  * if mtu > 1500
1691                  */
1692                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1693                         struct sk_buff *new_skb;
1694
1695                         new_skb = dev_alloc_skb(len + 2);
1696                         if (new_skb == NULL)
1697                                 goto reuse_rx;
1698
1699                         /* aligned copy */
1700                         memcpy(new_skb->data,
1701                                 skb->data + bp->rx_offset - 2,
1702                                 len + 2);
1703
1704                         skb_reserve(new_skb, 2);
1705                         skb_put(new_skb, len);
1706                         new_skb->dev = bp->dev;
1707
1708                         bnx2_reuse_rx_skb(bp, skb,
1709                                 sw_ring_cons, sw_ring_prod);
1710
1711                         skb = new_skb;
1712                 }
1713                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1714                         pci_unmap_single(bp->pdev,
1715                                 pci_unmap_addr(rx_buf, mapping),
1716                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1717
1718                         skb_reserve(skb, bp->rx_offset);
1719                         skb_put(skb, len);
1720                 }
1721                 else {
1722 reuse_rx:
1723                         bnx2_reuse_rx_skb(bp, skb,
1724                                 sw_ring_cons, sw_ring_prod);
1725                         goto next_rx;
1726                 }
1727
1728                 skb->protocol = eth_type_trans(skb, bp->dev);
1729
1730                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1731                         (htons(skb->protocol) != 0x8100)) {
1732
1733                         dev_kfree_skb_irq(skb);
1734                         goto next_rx;
1735
1736                 }
1737
1738                 skb->ip_summed = CHECKSUM_NONE;
1739                 if (bp->rx_csum &&
1740                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1741                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1742
1743                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1744                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1745                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1746                 }
1747
1748 #ifdef BCM_VLAN
1749                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1750                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1751                                 rx_hdr->l2_fhdr_vlan_tag);
1752                 }
1753                 else
1754 #endif
1755                         netif_receive_skb(skb);
1756
1757                 bp->dev->last_rx = jiffies;
1758                 rx_pkt++;
1759
1760 next_rx:
1761                 rx_buf->skb = NULL;
1762
1763                 sw_cons = NEXT_RX_BD(sw_cons);
1764                 sw_prod = NEXT_RX_BD(sw_prod);
1765
1766                 if ((rx_pkt == budget))
1767                         break;
1768
1769                 /* Refresh hw_cons to see if there is new work */
1770                 if (sw_cons == hw_cons) {
1771                         hw_cons = bp->hw_rx_cons =
1772                                 sblk->status_rx_quick_consumer_index0;
1773                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1774                                 hw_cons++;
1775                         rmb();
1776                 }
1777         }
1778         bp->rx_cons = sw_cons;
1779         bp->rx_prod = sw_prod;
1780
1781         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1782
1783         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1784
1785         mmiowb();
1786
1787         return rx_pkt;
1788
1789 }
1790
1791 /* MSI ISR - The only difference between this and the INTx ISR
1792  * is that the MSI interrupt is always serviced.
1793  */
1794 static irqreturn_t
1795 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1796 {
1797         struct net_device *dev = dev_instance;
1798         struct bnx2 *bp = dev->priv;
1799
1800         prefetch(bp->status_blk);
1801         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1802                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1803                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1804
1805         /* Return here if interrupt is disabled. */
1806         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1807                 return IRQ_HANDLED;
1808
1809         netif_rx_schedule(dev);
1810
1811         return IRQ_HANDLED;
1812 }
1813
1814 static irqreturn_t
1815 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1816 {
1817         struct net_device *dev = dev_instance;
1818         struct bnx2 *bp = dev->priv;
1819
1820         /* When using INTx, it is possible for the interrupt to arrive
1821          * at the CPU before the status block posted prior to the
1822          * interrupt. Reading a register will flush the status block.
1823          * When using MSI, the MSI message will always complete after
1824          * the status block write.
1825          */
1826         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1827             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1828              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1829                 return IRQ_NONE;
1830
1831         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1832                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1833                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1834
1835         /* Return here if interrupt is shared and is disabled. */
1836         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1837                 return IRQ_HANDLED;
1838
1839         netif_rx_schedule(dev);
1840
1841         return IRQ_HANDLED;
1842 }
1843
1844 static inline int
1845 bnx2_has_work(struct bnx2 *bp)
1846 {
1847         struct status_block *sblk = bp->status_blk;
1848
1849         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1850             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1851                 return 1;
1852
1853         if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1854             bp->link_up)
1855                 return 1;
1856
1857         return 0;
1858 }
1859
1860 static int
1861 bnx2_poll(struct net_device *dev, int *budget)
1862 {
1863         struct bnx2 *bp = dev->priv;
1864
1865         if ((bp->status_blk->status_attn_bits &
1866                 STATUS_ATTN_BITS_LINK_STATE) !=
1867                 (bp->status_blk->status_attn_bits_ack &
1868                 STATUS_ATTN_BITS_LINK_STATE)) {
1869
1870                 spin_lock(&bp->phy_lock);
1871                 bnx2_phy_int(bp);
1872                 spin_unlock(&bp->phy_lock);
1873         }
1874
1875         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1876                 bnx2_tx_int(bp);
1877
1878         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1879                 int orig_budget = *budget;
1880                 int work_done;
1881
1882                 if (orig_budget > dev->quota)
1883                         orig_budget = dev->quota;
1884
1885                 work_done = bnx2_rx_int(bp, orig_budget);
1886                 *budget -= work_done;
1887                 dev->quota -= work_done;
1888         }
1889
1890         bp->last_status_idx = bp->status_blk->status_idx;
1891         rmb();
1892
1893         if (!bnx2_has_work(bp)) {
1894                 netif_rx_complete(dev);
1895                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1896                         BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1897                         bp->last_status_idx);
1898                 return 0;
1899         }
1900
1901         return 1;
1902 }
1903
1904 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1905  * from set_multicast.
1906  */
1907 static void
1908 bnx2_set_rx_mode(struct net_device *dev)
1909 {
1910         struct bnx2 *bp = dev->priv;
1911         u32 rx_mode, sort_mode;
1912         int i;
1913
1914         spin_lock_bh(&bp->phy_lock);
1915
1916         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1917                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1918         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1919 #ifdef BCM_VLAN
1920         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
1921                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1922 #else
1923         if (!(bp->flags & ASF_ENABLE_FLAG))
1924                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1925 #endif
1926         if (dev->flags & IFF_PROMISC) {
1927                 /* Promiscuous mode. */
1928                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1929                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1930         }
1931         else if (dev->flags & IFF_ALLMULTI) {
1932                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1933                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1934                                0xffffffff);
1935                 }
1936                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1937         }
1938         else {
1939                 /* Accept one or more multicast(s). */
1940                 struct dev_mc_list *mclist;
1941                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1942                 u32 regidx;
1943                 u32 bit;
1944                 u32 crc;
1945
1946                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1947
1948                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1949                      i++, mclist = mclist->next) {
1950
1951                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1952                         bit = crc & 0xff;
1953                         regidx = (bit & 0xe0) >> 5;
1954                         bit &= 0x1f;
1955                         mc_filter[regidx] |= (1 << bit);
1956                 }
1957
1958                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1959                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1960                                mc_filter[i]);
1961                 }
1962
1963                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1964         }
1965
1966         if (rx_mode != bp->rx_mode) {
1967                 bp->rx_mode = rx_mode;
1968                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1969         }
1970
1971         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1972         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1973         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1974
1975         spin_unlock_bh(&bp->phy_lock);
1976 }
1977
1978 static void
1979 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1980         u32 rv2p_proc)
1981 {
1982         int i;
1983         u32 val;
1984
1985
1986         for (i = 0; i < rv2p_code_len; i += 8) {
1987                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1988                 rv2p_code++;
1989                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1990                 rv2p_code++;
1991
1992                 if (rv2p_proc == RV2P_PROC1) {
1993                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1994                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1995                 }
1996                 else {
1997                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1998                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1999                 }
2000         }
2001
2002         /* Reset the processor, un-stall is done later. */
2003         if (rv2p_proc == RV2P_PROC1) {
2004                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2005         }
2006         else {
2007                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2008         }
2009 }
2010
2011 static void
2012 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2013 {
2014         u32 offset;
2015         u32 val;
2016
2017         /* Halt the CPU. */
2018         val = REG_RD_IND(bp, cpu_reg->mode);
2019         val |= cpu_reg->mode_value_halt;
2020         REG_WR_IND(bp, cpu_reg->mode, val);
2021         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2022
2023         /* Load the Text area. */
2024         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2025         if (fw->text) {
2026                 int j;
2027
2028                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2029                         REG_WR_IND(bp, offset, fw->text[j]);
2030                 }
2031         }
2032
2033         /* Load the Data area. */
2034         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2035         if (fw->data) {
2036                 int j;
2037
2038                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2039                         REG_WR_IND(bp, offset, fw->data[j]);
2040                 }
2041         }
2042
2043         /* Load the SBSS area. */
2044         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2045         if (fw->sbss) {
2046                 int j;
2047
2048                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2049                         REG_WR_IND(bp, offset, fw->sbss[j]);
2050                 }
2051         }
2052
2053         /* Load the BSS area. */
2054         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2055         if (fw->bss) {
2056                 int j;
2057
2058                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2059                         REG_WR_IND(bp, offset, fw->bss[j]);
2060                 }
2061         }
2062
2063         /* Load the Read-Only area. */
2064         offset = cpu_reg->spad_base +
2065                 (fw->rodata_addr - cpu_reg->mips_view_base);
2066         if (fw->rodata) {
2067                 int j;
2068
2069                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2070                         REG_WR_IND(bp, offset, fw->rodata[j]);
2071                 }
2072         }
2073
2074         /* Clear the pre-fetch instruction. */
2075         REG_WR_IND(bp, cpu_reg->inst, 0);
2076         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2077
2078         /* Start the CPU. */
2079         val = REG_RD_IND(bp, cpu_reg->mode);
2080         val &= ~cpu_reg->mode_value_halt;
2081         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2082         REG_WR_IND(bp, cpu_reg->mode, val);
2083 }
2084
2085 static void
2086 bnx2_init_cpus(struct bnx2 *bp)
2087 {
2088         struct cpu_reg cpu_reg;
2089         struct fw_info fw;
2090
2091         /* Initialize the RV2P processor. */
2092         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2093         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2094
2095         /* Initialize the RX Processor. */
2096         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2097         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2098         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2099         cpu_reg.state = BNX2_RXP_CPU_STATE;
2100         cpu_reg.state_value_clear = 0xffffff;
2101         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2102         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2103         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2104         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2105         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2106         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2107         cpu_reg.mips_view_base = 0x8000000;
2108
2109         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2110         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2111         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2112         fw.start_addr = bnx2_RXP_b06FwStartAddr;
2113
2114         fw.text_addr = bnx2_RXP_b06FwTextAddr;
2115         fw.text_len = bnx2_RXP_b06FwTextLen;
2116         fw.text_index = 0;
2117         fw.text = bnx2_RXP_b06FwText;
2118
2119         fw.data_addr = bnx2_RXP_b06FwDataAddr;
2120         fw.data_len = bnx2_RXP_b06FwDataLen;
2121         fw.data_index = 0;
2122         fw.data = bnx2_RXP_b06FwData;
2123
2124         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2125         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2126         fw.sbss_index = 0;
2127         fw.sbss = bnx2_RXP_b06FwSbss;
2128
2129         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2130         fw.bss_len = bnx2_RXP_b06FwBssLen;
2131         fw.bss_index = 0;
2132         fw.bss = bnx2_RXP_b06FwBss;
2133
2134         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2135         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2136         fw.rodata_index = 0;
2137         fw.rodata = bnx2_RXP_b06FwRodata;
2138
2139         load_cpu_fw(bp, &cpu_reg, &fw);
2140
2141         /* Initialize the TX Processor. */
2142         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2143         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2144         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2145         cpu_reg.state = BNX2_TXP_CPU_STATE;
2146         cpu_reg.state_value_clear = 0xffffff;
2147         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2148         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2149         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2150         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2151         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2152         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2153         cpu_reg.mips_view_base = 0x8000000;
2154
2155         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2156         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2157         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2158         fw.start_addr = bnx2_TXP_b06FwStartAddr;
2159
2160         fw.text_addr = bnx2_TXP_b06FwTextAddr;
2161         fw.text_len = bnx2_TXP_b06FwTextLen;
2162         fw.text_index = 0;
2163         fw.text = bnx2_TXP_b06FwText;
2164
2165         fw.data_addr = bnx2_TXP_b06FwDataAddr;
2166         fw.data_len = bnx2_TXP_b06FwDataLen;
2167         fw.data_index = 0;
2168         fw.data = bnx2_TXP_b06FwData;
2169
2170         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2171         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2172         fw.sbss_index = 0;
2173         fw.sbss = bnx2_TXP_b06FwSbss;
2174
2175         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2176         fw.bss_len = bnx2_TXP_b06FwBssLen;
2177         fw.bss_index = 0;
2178         fw.bss = bnx2_TXP_b06FwBss;
2179
2180         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2181         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2182         fw.rodata_index = 0;
2183         fw.rodata = bnx2_TXP_b06FwRodata;
2184
2185         load_cpu_fw(bp, &cpu_reg, &fw);
2186
2187         /* Initialize the TX Patch-up Processor. */
2188         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2189         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2190         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2191         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2192         cpu_reg.state_value_clear = 0xffffff;
2193         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2194         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2195         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2196         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2197         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2198         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2199         cpu_reg.mips_view_base = 0x8000000;
2200
2201         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2202         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2203         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2204         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2205
2206         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2207         fw.text_len = bnx2_TPAT_b06FwTextLen;
2208         fw.text_index = 0;
2209         fw.text = bnx2_TPAT_b06FwText;
2210
2211         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2212         fw.data_len = bnx2_TPAT_b06FwDataLen;
2213         fw.data_index = 0;
2214         fw.data = bnx2_TPAT_b06FwData;
2215
2216         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2217         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2218         fw.sbss_index = 0;
2219         fw.sbss = bnx2_TPAT_b06FwSbss;
2220
2221         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2222         fw.bss_len = bnx2_TPAT_b06FwBssLen;
2223         fw.bss_index = 0;
2224         fw.bss = bnx2_TPAT_b06FwBss;
2225
2226         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2227         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2228         fw.rodata_index = 0;
2229         fw.rodata = bnx2_TPAT_b06FwRodata;
2230
2231         load_cpu_fw(bp, &cpu_reg, &fw);
2232
2233         /* Initialize the Completion Processor. */
2234         cpu_reg.mode = BNX2_COM_CPU_MODE;
2235         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2236         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2237         cpu_reg.state = BNX2_COM_CPU_STATE;
2238         cpu_reg.state_value_clear = 0xffffff;
2239         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2240         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2241         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2242         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2243         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2244         cpu_reg.spad_base = BNX2_COM_SCRATCH;
2245         cpu_reg.mips_view_base = 0x8000000;
2246
2247         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2248         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2249         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2250         fw.start_addr = bnx2_COM_b06FwStartAddr;
2251
2252         fw.text_addr = bnx2_COM_b06FwTextAddr;
2253         fw.text_len = bnx2_COM_b06FwTextLen;
2254         fw.text_index = 0;
2255         fw.text = bnx2_COM_b06FwText;
2256
2257         fw.data_addr = bnx2_COM_b06FwDataAddr;
2258         fw.data_len = bnx2_COM_b06FwDataLen;
2259         fw.data_index = 0;
2260         fw.data = bnx2_COM_b06FwData;
2261
2262         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2263         fw.sbss_len = bnx2_COM_b06FwSbssLen;
2264         fw.sbss_index = 0;
2265         fw.sbss = bnx2_COM_b06FwSbss;
2266
2267         fw.bss_addr = bnx2_COM_b06FwBssAddr;
2268         fw.bss_len = bnx2_COM_b06FwBssLen;
2269         fw.bss_index = 0;
2270         fw.bss = bnx2_COM_b06FwBss;
2271
2272         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2273         fw.rodata_len = bnx2_COM_b06FwRodataLen;
2274         fw.rodata_index = 0;
2275         fw.rodata = bnx2_COM_b06FwRodata;
2276
2277         load_cpu_fw(bp, &cpu_reg, &fw);
2278
2279 }
2280
2281 static int
2282 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2283 {
2284         u16 pmcsr;
2285
2286         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2287
2288         switch (state) {
2289         case PCI_D0: {
2290                 u32 val;
2291
2292                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2293                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2294                         PCI_PM_CTRL_PME_STATUS);
2295
2296                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2297                         /* delay required during transition out of D3hot */
2298                         msleep(20);
2299
2300                 val = REG_RD(bp, BNX2_EMAC_MODE);
2301                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2302                 val &= ~BNX2_EMAC_MODE_MPKT;
2303                 REG_WR(bp, BNX2_EMAC_MODE, val);
2304
2305                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2306                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2307                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2308                 break;
2309         }
2310         case PCI_D3hot: {
2311                 int i;
2312                 u32 val, wol_msg;
2313
2314                 if (bp->wol) {
2315                         u32 advertising;
2316                         u8 autoneg;
2317
2318                         autoneg = bp->autoneg;
2319                         advertising = bp->advertising;
2320
2321                         bp->autoneg = AUTONEG_SPEED;
2322                         bp->advertising = ADVERTISED_10baseT_Half |
2323                                 ADVERTISED_10baseT_Full |
2324                                 ADVERTISED_100baseT_Half |
2325                                 ADVERTISED_100baseT_Full |
2326                                 ADVERTISED_Autoneg;
2327
2328                         bnx2_setup_copper_phy(bp);
2329
2330                         bp->autoneg = autoneg;
2331                         bp->advertising = advertising;
2332
2333                         bnx2_set_mac_addr(bp);
2334
2335                         val = REG_RD(bp, BNX2_EMAC_MODE);
2336
2337                         /* Enable port mode. */
2338                         val &= ~BNX2_EMAC_MODE_PORT;
2339                         val |= BNX2_EMAC_MODE_PORT_MII |
2340                                BNX2_EMAC_MODE_MPKT_RCVD |
2341                                BNX2_EMAC_MODE_ACPI_RCVD |
2342                                BNX2_EMAC_MODE_MPKT;
2343
2344                         REG_WR(bp, BNX2_EMAC_MODE, val);
2345
2346                         /* receive all multicast */
2347                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2348                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2349                                        0xffffffff);
2350                         }
2351                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2352                                BNX2_EMAC_RX_MODE_SORT_MODE);
2353
2354                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2355                               BNX2_RPM_SORT_USER0_MC_EN;
2356                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2357                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2358                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2359                                BNX2_RPM_SORT_USER0_ENA);
2360
2361                         /* Need to enable EMAC and RPM for WOL. */
2362                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2363                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2364                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2365                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2366
2367                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2368                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2369                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2370
2371                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2372                 }
2373                 else {
2374                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2375                 }
2376
2377                 if (!(bp->flags & NO_WOL_FLAG))
2378                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2379
2380                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2381                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2382                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2383
2384                         if (bp->wol)
2385                                 pmcsr |= 3;
2386                 }
2387                 else {
2388                         pmcsr |= 3;
2389                 }
2390                 if (bp->wol) {
2391                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2392                 }
2393                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2394                                       pmcsr);
2395
2396                 /* No more memory access after this point until
2397                  * device is brought back to D0.
2398                  */
2399                 udelay(50);
2400                 break;
2401         }
2402         default:
2403                 return -EINVAL;
2404         }
2405         return 0;
2406 }
2407
2408 static int
2409 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2410 {
2411         u32 val;
2412         int j;
2413
2414         /* Request access to the flash interface. */
2415         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2416         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2417                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2418                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2419                         break;
2420
2421                 udelay(5);
2422         }
2423
2424         if (j >= NVRAM_TIMEOUT_COUNT)
2425                 return -EBUSY;
2426
2427         return 0;
2428 }
2429
2430 static int
2431 bnx2_release_nvram_lock(struct bnx2 *bp)
2432 {
2433         int j;
2434         u32 val;
2435
2436         /* Relinquish nvram interface. */
2437         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2438
2439         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2440                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2441                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2442                         break;
2443
2444                 udelay(5);
2445         }
2446
2447         if (j >= NVRAM_TIMEOUT_COUNT)
2448                 return -EBUSY;
2449
2450         return 0;
2451 }
2452
2453
2454 static int
2455 bnx2_enable_nvram_write(struct bnx2 *bp)
2456 {
2457         u32 val;
2458
2459         val = REG_RD(bp, BNX2_MISC_CFG);
2460         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2461
2462         if (!bp->flash_info->buffered) {
2463                 int j;
2464
2465                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2466                 REG_WR(bp, BNX2_NVM_COMMAND,
2467                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2468
2469                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2470                         udelay(5);
2471
2472                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2473                         if (val & BNX2_NVM_COMMAND_DONE)
2474                                 break;
2475                 }
2476
2477                 if (j >= NVRAM_TIMEOUT_COUNT)
2478                         return -EBUSY;
2479         }
2480         return 0;
2481 }
2482
2483 static void
2484 bnx2_disable_nvram_write(struct bnx2 *bp)
2485 {
2486         u32 val;
2487
2488         val = REG_RD(bp, BNX2_MISC_CFG);
2489         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2490 }
2491
2492
2493 static void
2494 bnx2_enable_nvram_access(struct bnx2 *bp)
2495 {
2496         u32 val;
2497
2498         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2499         /* Enable both bits, even on read. */
2500         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2501                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2502 }
2503
2504 static void
2505 bnx2_disable_nvram_access(struct bnx2 *bp)
2506 {
2507         u32 val;
2508
2509         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2510         /* Disable both bits, even after read. */
2511         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2512                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2513                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2514 }
2515
2516 static int
2517 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2518 {
2519         u32 cmd;
2520         int j;
2521
2522         if (bp->flash_info->buffered)
2523                 /* Buffered flash, no erase needed */
2524                 return 0;
2525
2526         /* Build an erase command */
2527         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2528               BNX2_NVM_COMMAND_DOIT;
2529
2530         /* Need to clear DONE bit separately. */
2531         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2532
2533         /* Address of the NVRAM to read from. */
2534         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2535
2536         /* Issue an erase command. */
2537         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2538
2539         /* Wait for completion. */
2540         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2541                 u32 val;
2542
2543                 udelay(5);
2544
2545                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2546                 if (val & BNX2_NVM_COMMAND_DONE)
2547                         break;
2548         }
2549
2550         if (j >= NVRAM_TIMEOUT_COUNT)
2551                 return -EBUSY;
2552
2553         return 0;
2554 }
2555
2556 static int
2557 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2558 {
2559         u32 cmd;
2560         int j;
2561
2562         /* Build the command word. */
2563         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2564
2565         /* Calculate an offset of a buffered flash. */
2566         if (bp->flash_info->buffered) {
2567                 offset = ((offset / bp->flash_info->page_size) <<
2568                            bp->flash_info->page_bits) +
2569                           (offset % bp->flash_info->page_size);
2570         }
2571
2572         /* Need to clear DONE bit separately. */
2573         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2574
2575         /* Address of the NVRAM to read from. */
2576         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2577
2578         /* Issue a read command. */
2579         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2580
2581         /* Wait for completion. */
2582         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2583                 u32 val;
2584
2585                 udelay(5);
2586
2587                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2588                 if (val & BNX2_NVM_COMMAND_DONE) {
2589                         val = REG_RD(bp, BNX2_NVM_READ);
2590
2591                         val = be32_to_cpu(val);
2592                         memcpy(ret_val, &val, 4);
2593                         break;
2594                 }
2595         }
2596         if (j >= NVRAM_TIMEOUT_COUNT)
2597                 return -EBUSY;
2598
2599         return 0;
2600 }
2601
2602
2603 static int
2604 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2605 {
2606         u32 cmd, val32;
2607         int j;
2608
2609         /* Build the command word. */
2610         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2611
2612         /* Calculate an offset of a buffered flash. */
2613         if (bp->flash_info->buffered) {
2614                 offset = ((offset / bp->flash_info->page_size) <<
2615                           bp->flash_info->page_bits) +
2616                          (offset % bp->flash_info->page_size);
2617         }
2618
2619         /* Need to clear DONE bit separately. */
2620         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2621
2622         memcpy(&val32, val, 4);
2623         val32 = cpu_to_be32(val32);
2624
2625         /* Write the data. */
2626         REG_WR(bp, BNX2_NVM_WRITE, val32);
2627
2628         /* Address of the NVRAM to write to. */
2629         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2630
2631         /* Issue the write command. */
2632         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2633
2634         /* Wait for completion. */
2635         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2636                 udelay(5);
2637
2638                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2639                         break;
2640         }
2641         if (j >= NVRAM_TIMEOUT_COUNT)
2642                 return -EBUSY;
2643
2644         return 0;
2645 }
2646
2647 static int
2648 bnx2_init_nvram(struct bnx2 *bp)
2649 {
2650         u32 val;
2651         int j, entry_count, rc;
2652         struct flash_spec *flash;
2653
2654         /* Determine the selected interface. */
2655         val = REG_RD(bp, BNX2_NVM_CFG1);
2656
2657         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2658
2659         rc = 0;
2660         if (val & 0x40000000) {
2661
2662                 /* Flash interface has been reconfigured */
2663                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2664                      j++, flash++) {
2665                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2666                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2667                                 bp->flash_info = flash;
2668                                 break;
2669                         }
2670                 }
2671         }
2672         else {
2673                 u32 mask;
2674                 /* Not yet been reconfigured */
2675
2676                 if (val & (1 << 23))
2677                         mask = FLASH_BACKUP_STRAP_MASK;
2678                 else
2679                         mask = FLASH_STRAP_MASK;
2680
2681                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2682                         j++, flash++) {
2683
2684                         if ((val & mask) == (flash->strapping & mask)) {
2685                                 bp->flash_info = flash;
2686
2687                                 /* Request access to the flash interface. */
2688                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2689                                         return rc;
2690
2691                                 /* Enable access to flash interface */
2692                                 bnx2_enable_nvram_access(bp);
2693
2694                                 /* Reconfigure the flash interface */
2695                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2696                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2697                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2698                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2699
2700                                 /* Disable access to flash interface */
2701                                 bnx2_disable_nvram_access(bp);
2702                                 bnx2_release_nvram_lock(bp);
2703
2704                                 break;
2705                         }
2706                 }
2707         } /* if (val & 0x40000000) */
2708
2709         if (j == entry_count) {
2710                 bp->flash_info = NULL;
2711                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2712                 rc = -ENODEV;
2713         }
2714
2715         return rc;
2716 }
2717
2718 static int
2719 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2720                 int buf_size)
2721 {
2722         int rc = 0;
2723         u32 cmd_flags, offset32, len32, extra;
2724
2725         if (buf_size == 0)
2726                 return 0;
2727
2728         /* Request access to the flash interface. */
2729         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2730                 return rc;
2731
2732         /* Enable access to flash interface */
2733         bnx2_enable_nvram_access(bp);
2734
2735         len32 = buf_size;
2736         offset32 = offset;
2737         extra = 0;
2738
2739         cmd_flags = 0;
2740
2741         if (offset32 & 3) {
2742                 u8 buf[4];
2743                 u32 pre_len;
2744
2745                 offset32 &= ~3;
2746                 pre_len = 4 - (offset & 3);
2747
2748                 if (pre_len >= len32) {
2749                         pre_len = len32;
2750                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2751                                     BNX2_NVM_COMMAND_LAST;
2752                 }
2753                 else {
2754                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2755                 }
2756
2757                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2758
2759                 if (rc)
2760                         return rc;
2761
2762                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2763
2764                 offset32 += 4;
2765                 ret_buf += pre_len;
2766                 len32 -= pre_len;
2767         }
2768         if (len32 & 3) {
2769                 extra = 4 - (len32 & 3);
2770                 len32 = (len32 + 4) & ~3;
2771         }
2772
2773         if (len32 == 4) {
2774                 u8 buf[4];
2775
2776                 if (cmd_flags)
2777                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2778                 else
2779                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2780                                     BNX2_NVM_COMMAND_LAST;
2781
2782                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2783
2784                 memcpy(ret_buf, buf, 4 - extra);
2785         }
2786         else if (len32 > 0) {
2787                 u8 buf[4];
2788
2789                 /* Read the first word. */
2790                 if (cmd_flags)
2791                         cmd_flags = 0;
2792                 else
2793                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2794
2795                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2796
2797                 /* Advance to the next dword. */
2798                 offset32 += 4;
2799                 ret_buf += 4;
2800                 len32 -= 4;
2801
2802                 while (len32 > 4 && rc == 0) {
2803                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2804
2805                         /* Advance to the next dword. */
2806                         offset32 += 4;
2807                         ret_buf += 4;
2808                         len32 -= 4;
2809                 }
2810
2811                 if (rc)
2812                         return rc;
2813
2814                 cmd_flags = BNX2_NVM_COMMAND_LAST;
2815                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2816
2817                 memcpy(ret_buf, buf, 4 - extra);
2818         }
2819
2820         /* Disable access to flash interface */
2821         bnx2_disable_nvram_access(bp);
2822
2823         bnx2_release_nvram_lock(bp);
2824
2825         return rc;
2826 }
2827
2828 static int
2829 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2830                 int buf_size)
2831 {
2832         u32 written, offset32, len32;
2833         u8 *buf, start[4], end[4];
2834         int rc = 0;
2835         int align_start, align_end;
2836
2837         buf = data_buf;
2838         offset32 = offset;
2839         len32 = buf_size;
2840         align_start = align_end = 0;
2841
2842         if ((align_start = (offset32 & 3))) {
2843                 offset32 &= ~3;
2844                 len32 += align_start;
2845                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2846                         return rc;
2847         }
2848
2849         if (len32 & 3) {
2850                 if ((len32 > 4) || !align_start) {
2851                         align_end = 4 - (len32 & 3);
2852                         len32 += align_end;
2853                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2854                                 end, 4))) {
2855                                 return rc;
2856                         }
2857                 }
2858         }
2859
2860         if (align_start || align_end) {
2861                 buf = kmalloc(len32, GFP_KERNEL);
2862                 if (buf == 0)
2863                         return -ENOMEM;
2864                 if (align_start) {
2865                         memcpy(buf, start, 4);
2866                 }
2867                 if (align_end) {
2868                         memcpy(buf + len32 - 4, end, 4);
2869                 }
2870                 memcpy(buf + align_start, data_buf, buf_size);
2871         }
2872
2873         written = 0;
2874         while ((written < len32) && (rc == 0)) {
2875                 u32 page_start, page_end, data_start, data_end;
2876                 u32 addr, cmd_flags;
2877                 int i;
2878                 u8 flash_buffer[264];
2879
2880                 /* Find the page_start addr */
2881                 page_start = offset32 + written;
2882                 page_start -= (page_start % bp->flash_info->page_size);
2883                 /* Find the page_end addr */
2884                 page_end = page_start + bp->flash_info->page_size;
2885                 /* Find the data_start addr */
2886                 data_start = (written == 0) ? offset32 : page_start;
2887                 /* Find the data_end addr */
2888                 data_end = (page_end > offset32 + len32) ?
2889                         (offset32 + len32) : page_end;
2890
2891                 /* Request access to the flash interface. */
2892                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2893                         goto nvram_write_end;
2894
2895                 /* Enable access to flash interface */
2896                 bnx2_enable_nvram_access(bp);
2897
2898                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2899                 if (bp->flash_info->buffered == 0) {
2900                         int j;
2901
2902                         /* Read the whole page into the buffer
2903                          * (non-buffer flash only) */
2904                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
2905                                 if (j == (bp->flash_info->page_size - 4)) {
2906                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
2907                                 }
2908                                 rc = bnx2_nvram_read_dword(bp,
2909                                         page_start + j,
2910                                         &flash_buffer[j],
2911                                         cmd_flags);
2912
2913                                 if (rc)
2914                                         goto nvram_write_end;
2915
2916                                 cmd_flags = 0;
2917                         }
2918                 }
2919
2920                 /* Enable writes to flash interface (unlock write-protect) */
2921                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2922                         goto nvram_write_end;
2923
2924                 /* Erase the page */
2925                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2926                         goto nvram_write_end;
2927
2928                 /* Re-enable the write again for the actual write */
2929                 bnx2_enable_nvram_write(bp);
2930
2931                 /* Loop to write back the buffer data from page_start to
2932                  * data_start */
2933                 i = 0;
2934                 if (bp->flash_info->buffered == 0) {
2935                         for (addr = page_start; addr < data_start;
2936                                 addr += 4, i += 4) {
2937
2938                                 rc = bnx2_nvram_write_dword(bp, addr,
2939                                         &flash_buffer[i], cmd_flags);
2940
2941                                 if (rc != 0)
2942                                         goto nvram_write_end;
2943
2944                                 cmd_flags = 0;
2945                         }
2946                 }
2947
2948                 /* Loop to write the new data from data_start to data_end */
2949                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2950                         if ((addr == page_end - 4) ||
2951                                 ((bp->flash_info->buffered) &&
2952                                  (addr == data_end - 4))) {
2953
2954                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2955                         }
2956                         rc = bnx2_nvram_write_dword(bp, addr, buf,
2957                                 cmd_flags);
2958
2959                         if (rc != 0)
2960                                 goto nvram_write_end;
2961
2962                         cmd_flags = 0;
2963                         buf += 4;
2964                 }
2965
2966                 /* Loop to write back the buffer data from data_end
2967                  * to page_end */
2968                 if (bp->flash_info->buffered == 0) {
2969                         for (addr = data_end; addr < page_end;
2970                                 addr += 4, i += 4) {
2971
2972                                 if (addr == page_end-4) {
2973                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2974                                 }
2975                                 rc = bnx2_nvram_write_dword(bp, addr,
2976                                         &flash_buffer[i], cmd_flags);
2977
2978                                 if (rc != 0)
2979                                         goto nvram_write_end;
2980
2981                                 cmd_flags = 0;
2982                         }
2983                 }
2984
2985                 /* Disable writes to flash interface (lock write-protect) */
2986                 bnx2_disable_nvram_write(bp);
2987
2988                 /* Disable access to flash interface */
2989                 bnx2_disable_nvram_access(bp);
2990                 bnx2_release_nvram_lock(bp);
2991
2992                 /* Increment written */
2993                 written += data_end - data_start;
2994         }
2995
2996 nvram_write_end:
2997         if (align_start || align_end)
2998                 kfree(buf);
2999         return rc;
3000 }
3001
3002 static int
3003 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3004 {
3005         u32 val;
3006         int i, rc = 0;
3007
3008         /* Wait for the current PCI transaction to complete before
3009          * issuing a reset. */
3010         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3011                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3012                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3013                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3014                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3015         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3016         udelay(5);
3017
3018         /* Wait for the firmware to tell us it is ok to issue a reset. */
3019         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3020
3021         /* Deposit a driver reset signature so the firmware knows that
3022          * this is a soft reset. */
3023         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3024                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3025
3026         /* Do a dummy read to force the chip to complete all current transaction
3027          * before we issue a reset. */
3028         val = REG_RD(bp, BNX2_MISC_ID);
3029
3030         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3031               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3032               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3033
3034         /* Chip reset. */
3035         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3036
3037         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3038             (CHIP_ID(bp) == CHIP_ID_5706_A1))
3039                 msleep(15);
3040
3041         /* Reset takes approximate 30 usec */
3042         for (i = 0; i < 10; i++) {
3043                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3044                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3045                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3046                         break;
3047                 }
3048                 udelay(10);
3049         }
3050
3051         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3052                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3053                 printk(KERN_ERR PFX "Chip reset did not complete\n");
3054                 return -EBUSY;
3055         }
3056
3057         /* Make sure byte swapping is properly configured. */
3058         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3059         if (val != 0x01020304) {
3060                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3061                 return -ENODEV;
3062         }
3063
3064         /* Wait for the firmware to finish its initialization. */
3065         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3066         if (rc)
3067                 return rc;
3068
3069         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3070                 /* Adjust the voltage regular to two steps lower.  The default
3071                  * of this register is 0x0000000e. */
3072                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3073
3074                 /* Remove bad rbuf memory from the free pool. */
3075                 rc = bnx2_alloc_bad_rbuf(bp);
3076         }
3077
3078         return rc;
3079 }
3080
3081 static int
3082 bnx2_init_chip(struct bnx2 *bp)
3083 {
3084         u32 val;
3085         int rc;
3086
3087         /* Make sure the interrupt is not active. */
3088         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3089
3090         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3091               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3092 #ifdef __BIG_ENDIAN
3093               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3094 #endif
3095               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3096               DMA_READ_CHANS << 12 |
3097               DMA_WRITE_CHANS << 16;
3098
3099         val |= (0x2 << 20) | (1 << 11);
3100
3101         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3102                 val |= (1 << 23);
3103
3104         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3105             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3106                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3107
3108         REG_WR(bp, BNX2_DMA_CONFIG, val);
3109
3110         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3111                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3112                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3113                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3114         }
3115
3116         if (bp->flags & PCIX_FLAG) {
3117                 u16 val16;
3118
3119                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3120                                      &val16);
3121                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3122                                       val16 & ~PCI_X_CMD_ERO);
3123         }
3124
3125         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3126                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3127                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3128                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3129
3130         /* Initialize context mapping and zero out the quick contexts.  The
3131          * context block must have already been enabled. */
3132         bnx2_init_context(bp);
3133
3134         bnx2_init_cpus(bp);
3135         bnx2_init_nvram(bp);
3136
3137         bnx2_set_mac_addr(bp);
3138
3139         val = REG_RD(bp, BNX2_MQ_CONFIG);
3140         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3141         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3142         REG_WR(bp, BNX2_MQ_CONFIG, val);
3143
3144         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3145         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3146         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3147
3148         val = (BCM_PAGE_BITS - 8) << 24;
3149         REG_WR(bp, BNX2_RV2P_CONFIG, val);
3150
3151         /* Configure page size. */
3152         val = REG_RD(bp, BNX2_TBDR_CONFIG);
3153         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3154         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3155         REG_WR(bp, BNX2_TBDR_CONFIG, val);
3156
3157         val = bp->mac_addr[0] +
3158               (bp->mac_addr[1] << 8) +
3159               (bp->mac_addr[2] << 16) +
3160               bp->mac_addr[3] +
3161               (bp->mac_addr[4] << 8) +
3162               (bp->mac_addr[5] << 16);
3163         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3164
3165         /* Program the MTU.  Also include 4 bytes for CRC32. */
3166         val = bp->dev->mtu + ETH_HLEN + 4;
3167         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3168                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3169         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3170
3171         bp->last_status_idx = 0;
3172         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3173
3174         /* Set up how to generate a link change interrupt. */
3175         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3176
3177         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3178                (u64) bp->status_blk_mapping & 0xffffffff);
3179         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3180
3181         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3182                (u64) bp->stats_blk_mapping & 0xffffffff);
3183         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3184                (u64) bp->stats_blk_mapping >> 32);
3185
3186         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3187                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3188
3189         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3190                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3191
3192         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3193                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3194
3195         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3196
3197         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3198
3199         REG_WR(bp, BNX2_HC_COM_TICKS,
3200                (bp->com_ticks_int << 16) | bp->com_ticks);
3201
3202         REG_WR(bp, BNX2_HC_CMD_TICKS,
3203                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3204
3205         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3206         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
3207
3208         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3209                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3210         else {
3211                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3212                        BNX2_HC_CONFIG_TX_TMR_MODE |
3213                        BNX2_HC_CONFIG_COLLECT_STATS);
3214         }
3215
3216         /* Clear internal stats counters. */
3217         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3218
3219         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3220
3221         if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3222             BNX2_PORT_FEATURE_ASF_ENABLED)
3223                 bp->flags |= ASF_ENABLE_FLAG;
3224
3225         /* Initialize the receive filter. */
3226         bnx2_set_rx_mode(bp->dev);
3227
3228         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3229                           0);
3230
3231         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3232         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3233
3234         udelay(20);
3235
3236         return rc;
3237 }
3238
3239
3240 static void
3241 bnx2_init_tx_ring(struct bnx2 *bp)
3242 {
3243         struct tx_bd *txbd;
3244         u32 val;
3245
3246         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3247
3248         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3249         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3250
3251         bp->tx_prod = 0;
3252         bp->tx_cons = 0;
3253         bp->hw_tx_cons = 0;
3254         bp->tx_prod_bseq = 0;
3255
3256         val = BNX2_L2CTX_TYPE_TYPE_L2;
3257         val |= BNX2_L2CTX_TYPE_SIZE_L2;
3258         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3259
3260         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3261         val |= 8 << 16;
3262         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3263
3264         val = (u64) bp->tx_desc_mapping >> 32;
3265         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3266
3267         val = (u64) bp->tx_desc_mapping & 0xffffffff;
3268         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3269 }
3270
3271 static void
3272 bnx2_init_rx_ring(struct bnx2 *bp)
3273 {
3274         struct rx_bd *rxbd;
3275         int i;
3276         u16 prod, ring_prod;
3277         u32 val;
3278
3279         /* 8 for CRC and VLAN */
3280         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3281         /* 8 for alignment */
3282         bp->rx_buf_size = bp->rx_buf_use_size + 8;
3283
3284         ring_prod = prod = bp->rx_prod = 0;
3285         bp->rx_cons = 0;
3286         bp->hw_rx_cons = 0;
3287         bp->rx_prod_bseq = 0;
3288
3289         rxbd = &bp->rx_desc_ring[0];
3290         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3291                 rxbd->rx_bd_len = bp->rx_buf_use_size;
3292                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3293         }
3294
3295         rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3296         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3297
3298         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3299         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3300         val |= 0x02 << 8;
3301         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3302
3303         val = (u64) bp->rx_desc_mapping >> 32;
3304         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3305
3306         val = (u64) bp->rx_desc_mapping & 0xffffffff;
3307         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3308
3309         for ( ;ring_prod < bp->rx_ring_size; ) {
3310                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3311                         break;
3312                 }
3313                 prod = NEXT_RX_BD(prod);
3314                 ring_prod = RX_RING_IDX(prod);
3315         }
3316         bp->rx_prod = prod;
3317
3318         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3319
3320         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3321 }
3322
3323 static void
3324 bnx2_free_tx_skbs(struct bnx2 *bp)
3325 {
3326         int i;
3327
3328         if (bp->tx_buf_ring == NULL)
3329                 return;
3330
3331         for (i = 0; i < TX_DESC_CNT; ) {
3332                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3333                 struct sk_buff *skb = tx_buf->skb;
3334                 int j, last;
3335
3336                 if (skb == NULL) {
3337                         i++;
3338                         continue;
3339                 }
3340
3341                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3342                         skb_headlen(skb), PCI_DMA_TODEVICE);
3343
3344                 tx_buf->skb = NULL;
3345
3346                 last = skb_shinfo(skb)->nr_frags;
3347                 for (j = 0; j < last; j++) {
3348                         tx_buf = &bp->tx_buf_ring[i + j + 1];
3349                         pci_unmap_page(bp->pdev,
3350                                 pci_unmap_addr(tx_buf, mapping),
3351                                 skb_shinfo(skb)->frags[j].size,
3352                                 PCI_DMA_TODEVICE);
3353                 }
3354                 dev_kfree_skb_any(skb);
3355                 i += j + 1;
3356         }
3357
3358 }
3359
3360 static void
3361 bnx2_free_rx_skbs(struct bnx2 *bp)
3362 {
3363         int i;
3364
3365         if (bp->rx_buf_ring == NULL)
3366                 return;
3367
3368         for (i = 0; i < RX_DESC_CNT; i++) {
3369                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3370                 struct sk_buff *skb = rx_buf->skb;
3371
3372                 if (skb == NULL)
3373                         continue;
3374
3375                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3376                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3377
3378                 rx_buf->skb = NULL;
3379
3380                 dev_kfree_skb_any(skb);
3381         }
3382 }
3383
3384 static void
3385 bnx2_free_skbs(struct bnx2 *bp)
3386 {
3387         bnx2_free_tx_skbs(bp);
3388         bnx2_free_rx_skbs(bp);
3389 }
3390
3391 static int
3392 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3393 {
3394         int rc;
3395
3396         rc = bnx2_reset_chip(bp, reset_code);
3397         bnx2_free_skbs(bp);
3398         if (rc)
3399                 return rc;
3400
3401         bnx2_init_chip(bp);
3402         bnx2_init_tx_ring(bp);
3403         bnx2_init_rx_ring(bp);
3404         return 0;
3405 }
3406
3407 static int
3408 bnx2_init_nic(struct bnx2 *bp)
3409 {
3410         int rc;
3411
3412         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3413                 return rc;
3414
3415         bnx2_init_phy(bp);
3416         bnx2_set_link(bp);
3417         return 0;
3418 }
3419
3420 static int
3421 bnx2_test_registers(struct bnx2 *bp)
3422 {
3423         int ret;
3424         int i;
3425         static struct {
3426                 u16   offset;
3427                 u16   flags;
3428                 u32   rw_mask;
3429                 u32   ro_mask;
3430         } reg_tbl[] = {
3431                 { 0x006c, 0, 0x00000000, 0x0000003f },
3432                 { 0x0090, 0, 0xffffffff, 0x00000000 },
3433                 { 0x0094, 0, 0x00000000, 0x00000000 },
3434
3435                 { 0x0404, 0, 0x00003f00, 0x00000000 },
3436                 { 0x0418, 0, 0x00000000, 0xffffffff },
3437                 { 0x041c, 0, 0x00000000, 0xffffffff },
3438                 { 0x0420, 0, 0x00000000, 0x80ffffff },
3439                 { 0x0424, 0, 0x00000000, 0x00000000 },
3440                 { 0x0428, 0, 0x00000000, 0x00000001 },
3441                 { 0x0450, 0, 0x00000000, 0x0000ffff },
3442                 { 0x0454, 0, 0x00000000, 0xffffffff },
3443                 { 0x0458, 0, 0x00000000, 0xffffffff },
3444
3445                 { 0x0808, 0, 0x00000000, 0xffffffff },
3446                 { 0x0854, 0, 0x00000000, 0xffffffff },
3447                 { 0x0868, 0, 0x00000000, 0x77777777 },
3448                 { 0x086c, 0, 0x00000000, 0x77777777 },
3449                 { 0x0870, 0, 0x00000000, 0x77777777 },
3450                 { 0x0874, 0, 0x00000000, 0x77777777 },
3451
3452                 { 0x0c00, 0, 0x00000000, 0x00000001 },
3453                 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3454                 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3455                 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3456                 { 0x0c30, 0, 0x00000000, 0xffffffff },
3457                 { 0x0c34, 0, 0x00000000, 0xffffffff },
3458                 { 0x0c38, 0, 0x00000000, 0xffffffff },
3459                 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3460                 { 0x0c40, 0, 0x00000000, 0xffffffff },
3461                 { 0x0c44, 0, 0x00000000, 0xffffffff },
3462                 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3463                 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3464                 { 0x0c50, 0, 0x00000000, 0xffffffff },
3465                 { 0x0c54, 0, 0x00000000, 0xffffffff },
3466                 { 0x0c58, 0, 0x00000000, 0xffffffff },
3467                 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3468                 { 0x0c60, 0, 0x00000000, 0xffffffff },
3469                 { 0x0c64, 0, 0x00000000, 0xffffffff },
3470                 { 0x0c68, 0, 0x00000000, 0xffffffff },
3471                 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3472                 { 0x0c70, 0, 0x00000000, 0xffffffff },
3473                 { 0x0c74, 0, 0x00000000, 0xffffffff },
3474                 { 0x0c78, 0, 0x00000000, 0xffffffff },
3475                 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3476                 { 0x0c80, 0, 0x00000000, 0xffffffff },
3477                 { 0x0c84, 0, 0x00000000, 0xffffffff },
3478                 { 0x0c88, 0, 0x00000000, 0xffffffff },
3479                 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3480                 { 0x0c90, 0, 0x00000000, 0xffffffff },
3481                 { 0x0c94, 0, 0x00000000, 0xffffffff },
3482                 { 0x0c98, 0, 0x00000000, 0xffffffff },
3483                 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3484                 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3485                 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3486                 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3487                 { 0x0cac, 0, 0x00000000, 0xffffffff },
3488                 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3489                 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3490                 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3491                 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3492                 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3493                 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3494                 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3495                 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3496                 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3497                 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3498                 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3499                 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3500                 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3501                 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3502                 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3503                 { 0x0cec, 0, 0x00000000, 0xffffffff },
3504                 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3505                 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3506                 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3507                 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3508                 { 0x0d00, 0, 0x00000000, 0xffffffff },
3509                 { 0x0d04, 0, 0x00000000, 0xffffffff },
3510
3511                 { 0x1000, 0, 0x00000000, 0x00000001 },
3512                 { 0x1004, 0, 0x00000000, 0x000f0001 },
3513                 { 0x1044, 0, 0x00000000, 0xffc003ff },
3514                 { 0x1080, 0, 0x00000000, 0x0001ffff },
3515                 { 0x1084, 0, 0x00000000, 0xffffffff },
3516                 { 0x1088, 0, 0x00000000, 0xffffffff },
3517                 { 0x108c, 0, 0x00000000, 0xffffffff },
3518                 { 0x1090, 0, 0x00000000, 0xffffffff },
3519                 { 0x1094, 0, 0x00000000, 0xffffffff },
3520                 { 0x1098, 0, 0x00000000, 0xffffffff },
3521                 { 0x109c, 0, 0x00000000, 0xffffffff },
3522                 { 0x10a0, 0, 0x00000000, 0xffffffff },
3523
3524                 { 0x1408, 0, 0x01c00800, 0x00000000 },
3525                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3526                 { 0x14a8, 0, 0x00000000, 0x000001ff },
3527                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3528                 { 0x14b0, 0, 0x00000002, 0x00000001 },
3529                 { 0x14b8, 0, 0x00000000, 0x00000000 },
3530                 { 0x14c0, 0, 0x00000000, 0x00000009 },
3531                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3532                 { 0x14cc, 0, 0x00000000, 0x00000001 },
3533                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3534                 { 0x1500, 0, 0x00000000, 0xffffffff },
3535                 { 0x1504, 0, 0x00000000, 0xffffffff },
3536                 { 0x1508, 0, 0x00000000, 0xffffffff },
3537                 { 0x150c, 0, 0x00000000, 0xffffffff },
3538                 { 0x1510, 0, 0x00000000, 0xffffffff },
3539                 { 0x1514, 0, 0x00000000, 0xffffffff },
3540                 { 0x1518, 0, 0x00000000, 0xffffffff },
3541                 { 0x151c, 0, 0x00000000, 0xffffffff },
3542                 { 0x1520, 0, 0x00000000, 0xffffffff },
3543                 { 0x1524, 0, 0x00000000, 0xffffffff },
3544                 { 0x1528, 0, 0x00000000, 0xffffffff },
3545                 { 0x152c, 0, 0x00000000, 0xffffffff },
3546                 { 0x1530, 0, 0x00000000, 0xffffffff },
3547                 { 0x1534, 0, 0x00000000, 0xffffffff },
3548                 { 0x1538, 0, 0x00000000, 0xffffffff },
3549                 { 0x153c, 0, 0x00000000, 0xffffffff },
3550                 { 0x1540, 0, 0x00000000, 0xffffffff },
3551                 { 0x1544, 0, 0x00000000, 0xffffffff },
3552                 { 0x1548, 0, 0x00000000, 0xffffffff },
3553                 { 0x154c, 0, 0x00000000, 0xffffffff },
3554                 { 0x1550, 0, 0x00000000, 0xffffffff },
3555                 { 0x1554, 0, 0x00000000, 0xffffffff },
3556                 { 0x1558, 0, 0x00000000, 0xffffffff },
3557                 { 0x1600, 0, 0x00000000, 0xffffffff },
3558                 { 0x1604, 0, 0x00000000, 0xffffffff },
3559                 { 0x1608, 0, 0x00000000, 0xffffffff },
3560                 { 0x160c, 0, 0x00000000, 0xffffffff },
3561                 { 0x1610, 0, 0x00000000, 0xffffffff },
3562                 { 0x1614, 0, 0x00000000, 0xffffffff },
3563                 { 0x1618, 0, 0x00000000, 0xffffffff },
3564                 { 0x161c, 0, 0x00000000, 0xffffffff },
3565                 { 0x1620, 0, 0x00000000, 0xffffffff },
3566                 { 0x1624, 0, 0x00000000, 0xffffffff },
3567                 { 0x1628, 0, 0x00000000, 0xffffffff },
3568                 { 0x162c, 0, 0x00000000, 0xffffffff },
3569                 { 0x1630, 0, 0x00000000, 0xffffffff },
3570                 { 0x1634, 0, 0x00000000, 0xffffffff },
3571                 { 0x1638, 0, 0x00000000, 0xffffffff },
3572                 { 0x163c, 0, 0x00000000, 0xffffffff },
3573                 { 0x1640, 0, 0x00000000, 0xffffffff },
3574                 { 0x1644, 0, 0x00000000, 0xffffffff },
3575                 { 0x1648, 0, 0x00000000, 0xffffffff },
3576                 { 0x164c, 0, 0x00000000, 0xffffffff },
3577                 { 0x1650, 0, 0x00000000, 0xffffffff },
3578                 { 0x1654, 0, 0x00000000, 0xffffffff },
3579
3580                 { 0x1800, 0, 0x00000000, 0x00000001 },
3581                 { 0x1804, 0, 0x00000000, 0x00000003 },
3582                 { 0x1840, 0, 0x00000000, 0xffffffff },
3583                 { 0x1844, 0, 0x00000000, 0xffffffff },
3584                 { 0x1848, 0, 0x00000000, 0xffffffff },
3585                 { 0x184c, 0, 0x00000000, 0xffffffff },
3586                 { 0x1850, 0, 0x00000000, 0xffffffff },
3587                 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3588                 { 0x1904, 0, 0xffffffff, 0x00000000 },
3589                 { 0x190c, 0, 0xffffffff, 0x00000000 },
3590                 { 0x1914, 0, 0xffffffff, 0x00000000 },
3591                 { 0x191c, 0, 0xffffffff, 0x00000000 },
3592                 { 0x1924, 0, 0xffffffff, 0x00000000 },
3593                 { 0x192c, 0, 0xffffffff, 0x00000000 },
3594                 { 0x1934, 0, 0xffffffff, 0x00000000 },
3595                 { 0x193c, 0, 0xffffffff, 0x00000000 },
3596                 { 0x1944, 0, 0xffffffff, 0x00000000 },
3597                 { 0x194c, 0, 0xffffffff, 0x00000000 },
3598                 { 0x1954, 0, 0xffffffff, 0x00000000 },
3599                 { 0x195c, 0, 0xffffffff, 0x00000000 },
3600                 { 0x1964, 0, 0xffffffff, 0x00000000 },
3601                 { 0x196c, 0, 0xffffffff, 0x00000000 },
3602                 { 0x1974, 0, 0xffffffff, 0x00000000 },
3603                 { 0x197c, 0, 0xffffffff, 0x00000000 },
3604                 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3605
3606                 { 0x1c00, 0, 0x00000000, 0x00000001 },
3607                 { 0x1c04, 0, 0x00000000, 0x00000003 },
3608                 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3609                 { 0x1c40, 0, 0x00000000, 0xffffffff },
3610                 { 0x1c44, 0, 0x00000000, 0xffffffff },
3611                 { 0x1c48, 0, 0x00000000, 0xffffffff },
3612                 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3613                 { 0x1c50, 0, 0x00000000, 0xffffffff },
3614                 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3615                 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3616                 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3617                 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3618                 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3619                 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3620                 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3621                 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3622                 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3623                 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3624                 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3625                 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3626                 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3627                 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3628                 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3629                 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3630                 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3631                 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3632
3633                 { 0x2004, 0, 0x00000000, 0x0337000f },
3634                 { 0x2008, 0, 0xffffffff, 0x00000000 },
3635                 { 0x200c, 0, 0xffffffff, 0x00000000 },
3636                 { 0x2010, 0, 0xffffffff, 0x00000000 },
3637                 { 0x2014, 0, 0x801fff80, 0x00000000 },
3638                 { 0x2018, 0, 0x000003ff, 0x00000000 },
3639
3640                 { 0x2800, 0, 0x00000000, 0x00000001 },
3641                 { 0x2804, 0, 0x00000000, 0x00003f01 },
3642                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3643                 { 0x2810, 0, 0xffff0000, 0x00000000 },
3644                 { 0x2814, 0, 0xffff0000, 0x00000000 },
3645                 { 0x2818, 0, 0xffff0000, 0x00000000 },
3646                 { 0x281c, 0, 0xffff0000, 0x00000000 },
3647                 { 0x2834, 0, 0xffffffff, 0x00000000 },
3648                 { 0x2840, 0, 0x00000000, 0xffffffff },
3649                 { 0x2844, 0, 0x00000000, 0xffffffff },
3650                 { 0x2848, 0, 0xffffffff, 0x00000000 },
3651                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3652
3653                 { 0x2c00, 0, 0x00000000, 0x00000011 },
3654                 { 0x2c04, 0, 0x00000000, 0x00030007 },
3655
3656                 { 0x3000, 0, 0x00000000, 0x00000001 },
3657                 { 0x3004, 0, 0x00000000, 0x007007ff },
3658                 { 0x3008, 0, 0x00000003, 0x00000000 },
3659                 { 0x300c, 0, 0xffffffff, 0x00000000 },
3660                 { 0x3010, 0, 0xffffffff, 0x00000000 },
3661                 { 0x3014, 0, 0xffffffff, 0x00000000 },
3662                 { 0x3034, 0, 0xffffffff, 0x00000000 },
3663                 { 0x3038, 0, 0xffffffff, 0x00000000 },
3664                 { 0x3050, 0, 0x00000001, 0x00000000 },
3665
3666                 { 0x3c00, 0, 0x00000000, 0x00000001 },
3667                 { 0x3c04, 0, 0x00000000, 0x00070000 },
3668                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3669                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3670                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3671                 { 0x3c14, 0, 0x00000000, 0xffffffff },
3672                 { 0x3c18, 0, 0x00000000, 0xffffffff },
3673                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3674                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3675                 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3676                 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3677                 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3678                 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3679                 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3680                 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3681                 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3682                 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3683                 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3684                 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3685                 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3686                 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3687                 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3688                 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3689                 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3690                 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3691                 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3692                 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3693                 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3694                 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3695                 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3696                 { 0x3c78, 0, 0x00000000, 0x00000000 },
3697                 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3698                 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3699                 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3700                 { 0x3c88, 0, 0x00000000, 0xffffffff },
3701                 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3702
3703                 { 0x4000, 0, 0x00000000, 0x00000001 },
3704                 { 0x4004, 0, 0x00000000, 0x00030000 },
3705                 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3706                 { 0x400c, 0, 0xffffffff, 0x00000000 },
3707                 { 0x4088, 0, 0x00000000, 0x00070303 },
3708
3709                 { 0x4400, 0, 0x00000000, 0x00000001 },
3710                 { 0x4404, 0, 0x00000000, 0x00003f01 },
3711                 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3712                 { 0x440c, 0, 0xffffffff, 0x00000000 },
3713                 { 0x4410, 0, 0xffff,     0x0000 },
3714                 { 0x4414, 0, 0xffff,     0x0000 },
3715                 { 0x4418, 0, 0xffff,     0x0000 },
3716                 { 0x441c, 0, 0xffff,     0x0000 },
3717                 { 0x4428, 0, 0xffffffff, 0x00000000 },
3718                 { 0x442c, 0, 0xffffffff, 0x00000000 },
3719                 { 0x4430, 0, 0xffffffff, 0x00000000 },
3720                 { 0x4434, 0, 0xffffffff, 0x00000000 },
3721                 { 0x4438, 0, 0xffffffff, 0x00000000 },
3722                 { 0x443c, 0, 0xffffffff, 0x00000000 },
3723                 { 0x4440, 0, 0xffffffff, 0x00000000 },
3724                 { 0x4444, 0, 0xffffffff, 0x00000000 },
3725
3726                 { 0x4c00, 0, 0x00000000, 0x00000001 },
3727                 { 0x4c04, 0, 0x00000000, 0x0000003f },
3728                 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3729                 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3730                 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3731                 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3732                 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3733                 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3734                 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3735                 { 0x4c50, 0, 0x00000000, 0xffffffff },
3736
3737                 { 0x5004, 0, 0x00000000, 0x0000007f },
3738                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3739                 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3740
3741                 { 0x5400, 0, 0x00000008, 0x00000001 },
3742                 { 0x5404, 0, 0x00000000, 0x0000003f },
3743                 { 0x5408, 0, 0x0000001f, 0x00000000 },
3744                 { 0x540c, 0, 0xffffffff, 0x00000000 },
3745                 { 0x5410, 0, 0xffffffff, 0x00000000 },
3746                 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3747                 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3748                 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3749                 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3750                 { 0x5428, 0, 0x000000ff, 0x00000000 },
3751                 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3752                 { 0x5430, 0, 0x001fff80, 0x00000000 },
3753                 { 0x5438, 0, 0xffffffff, 0x00000000 },
3754                 { 0x543c, 0, 0xffffffff, 0x00000000 },
3755                 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3756
3757                 { 0x5c00, 0, 0x00000000, 0x00000001 },
3758                 { 0x5c04, 0, 0x00000000, 0x0003000f },
3759                 { 0x5c08, 0, 0x00000003, 0x00000000 },
3760                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3761                 { 0x5c10, 0, 0x00000000, 0xffffffff },
3762                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3763                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3764                 { 0x5c88, 0, 0x00000000, 0x00077373 },
3765                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3766
3767                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3768                 { 0x680c, 0, 0xffffffff, 0x00000000 },
3769                 { 0x6810, 0, 0xffffffff, 0x00000000 },
3770                 { 0x6814, 0, 0xffffffff, 0x00000000 },
3771                 { 0x6818, 0, 0xffffffff, 0x00000000 },
3772                 { 0x681c, 0, 0xffffffff, 0x00000000 },
3773                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3774                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3775                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3776                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3777                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3778                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3779                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3780                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3781                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3782                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3783                 { 0x684c, 0, 0xffffffff, 0x00000000 },
3784                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3785                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3786                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3787                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3788                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3789                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3790
3791                 { 0xffff, 0, 0x00000000, 0x00000000 },
3792         };
3793
3794         ret = 0;
3795         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3796                 u32 offset, rw_mask, ro_mask, save_val, val;
3797
3798                 offset = (u32) reg_tbl[i].offset;
3799                 rw_mask = reg_tbl[i].rw_mask;
3800                 ro_mask = reg_tbl[i].ro_mask;
3801
3802                 save_val = readl(bp->regview + offset);
3803
3804                 writel(0, bp->regview + offset);
3805
3806                 val = readl(bp->regview + offset);
3807                 if ((val & rw_mask) != 0) {
3808                         goto reg_test_err;
3809                 }
3810
3811                 if ((val & ro_mask) != (save_val & ro_mask)) {
3812                         goto reg_test_err;
3813                 }
3814
3815                 writel(0xffffffff, bp->regview + offset);
3816
3817                 val = readl(bp->regview + offset);
3818                 if ((val & rw_mask) != rw_mask) {
3819                         goto reg_test_err;
3820                 }
3821
3822                 if ((val & ro_mask) != (save_val & ro_mask)) {
3823                         goto reg_test_err;
3824                 }
3825
3826                 writel(save_val, bp->regview + offset);
3827                 continue;
3828
3829 reg_test_err:
3830                 writel(save_val, bp->regview + offset);
3831                 ret = -ENODEV;
3832                 break;
3833         }
3834         return ret;
3835 }
3836
3837 static int
3838 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3839 {
3840         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3841                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3842         int i;
3843
3844         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3845                 u32 offset;
3846
3847                 for (offset = 0; offset < size; offset += 4) {
3848
3849                         REG_WR_IND(bp, start + offset, test_pattern[i]);
3850
3851                         if (REG_RD_IND(bp, start + offset) !=
3852                                 test_pattern[i]) {
3853                                 return -ENODEV;
3854                         }
3855                 }
3856         }
3857         return 0;
3858 }
3859
3860 static int
3861 bnx2_test_memory(struct bnx2 *bp)
3862 {
3863         int ret = 0;
3864         int i;
3865         static struct {
3866                 u32   offset;
3867                 u32   len;
3868         } mem_tbl[] = {
3869                 { 0x60000,  0x4000 },
3870                 { 0xa0000,  0x3000 },
3871                 { 0xe0000,  0x4000 },
3872                 { 0x120000, 0x4000 },
3873                 { 0x1a0000, 0x4000 },
3874                 { 0x160000, 0x4000 },
3875                 { 0xffffffff, 0    },
3876         };
3877
3878         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3879                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3880                         mem_tbl[i].len)) != 0) {
3881                         return ret;
3882                 }
3883         }
3884
3885         return ret;
3886 }
3887
3888 static int
3889 bnx2_test_loopback(struct bnx2 *bp)
3890 {
3891         unsigned int pkt_size, num_pkts, i;
3892         struct sk_buff *skb, *rx_skb;
3893         unsigned char *packet;
3894         u16 rx_start_idx, rx_idx, send_idx;
3895         u32 send_bseq, val;
3896         dma_addr_t map;
3897         struct tx_bd *txbd;
3898         struct sw_bd *rx_buf;
3899         struct l2_fhdr *rx_hdr;
3900         int ret = -ENODEV;
3901
3902         if (!netif_running(bp->dev))
3903                 return -ENODEV;
3904
3905         bp->loopback = MAC_LOOPBACK;
3906         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3907         bnx2_set_mac_loopback(bp);
3908
3909         pkt_size = 1514;
3910         skb = dev_alloc_skb(pkt_size);
3911         if (!skb)
3912                 return -ENOMEM;
3913         packet = skb_put(skb, pkt_size);
3914         memcpy(packet, bp->mac_addr, 6);
3915         memset(packet + 6, 0x0, 8);
3916         for (i = 14; i < pkt_size; i++)
3917                 packet[i] = (unsigned char) (i & 0xff);
3918
3919         map = pci_map_single(bp->pdev, skb->data, pkt_size,
3920                 PCI_DMA_TODEVICE);
3921
3922         val = REG_RD(bp, BNX2_HC_COMMAND);
3923         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3924         REG_RD(bp, BNX2_HC_COMMAND);
3925
3926         udelay(5);
3927         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3928
3929         send_idx = 0;
3930         send_bseq = 0;
3931         num_pkts = 0;
3932
3933         txbd = &bp->tx_desc_ring[send_idx];
3934
3935         txbd->tx_bd_haddr_hi = (u64) map >> 32;
3936         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3937         txbd->tx_bd_mss_nbytes = pkt_size;
3938         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3939
3940         num_pkts++;
3941         send_idx = NEXT_TX_BD(send_idx);
3942
3943         send_bseq += pkt_size;
3944
3945         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3946         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3947
3948
3949         udelay(100);
3950
3951         val = REG_RD(bp, BNX2_HC_COMMAND);
3952         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3953         REG_RD(bp, BNX2_HC_COMMAND);
3954
3955         udelay(5);
3956
3957         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3958         dev_kfree_skb_irq(skb);
3959
3960         if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3961                 goto loopback_test_done;
3962         }
3963
3964         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3965         if (rx_idx != rx_start_idx + num_pkts) {
3966                 goto loopback_test_done;
3967         }
3968
3969         rx_buf = &bp->rx_buf_ring[rx_start_idx];
3970         rx_skb = rx_buf->skb;
3971
3972         rx_hdr = (struct l2_fhdr *) rx_skb->data;
3973         skb_reserve(rx_skb, bp->rx_offset);
3974
3975         pci_dma_sync_single_for_cpu(bp->pdev,
3976                 pci_unmap_addr(rx_buf, mapping),
3977                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3978
3979         if (rx_hdr->l2_fhdr_status &
3980                 (L2_FHDR_ERRORS_BAD_CRC |
3981                 L2_FHDR_ERRORS_PHY_DECODE |
3982                 L2_FHDR_ERRORS_ALIGNMENT |
3983                 L2_FHDR_ERRORS_TOO_SHORT |
3984                 L2_FHDR_ERRORS_GIANT_FRAME)) {
3985
3986                 goto loopback_test_done;
3987         }
3988
3989         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3990                 goto loopback_test_done;
3991         }
3992
3993         for (i = 14; i < pkt_size; i++) {
3994                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3995                         goto loopback_test_done;
3996                 }
3997         }
3998
3999         ret = 0;
4000
4001 loopback_test_done:
4002         bp->loopback = 0;
4003         return ret;
4004 }
4005
4006 #define NVRAM_SIZE 0x200
4007 #define CRC32_RESIDUAL 0xdebb20e3
4008
4009 static int
4010 bnx2_test_nvram(struct bnx2 *bp)
4011 {
4012         u32 buf[NVRAM_SIZE / 4];
4013         u8 *data = (u8 *) buf;
4014         int rc = 0;
4015         u32 magic, csum;
4016
4017         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4018                 goto test_nvram_done;
4019
4020         magic = be32_to_cpu(buf[0]);
4021         if (magic != 0x669955aa) {
4022                 rc = -ENODEV;
4023                 goto test_nvram_done;
4024         }
4025
4026         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4027                 goto test_nvram_done;
4028
4029         csum = ether_crc_le(0x100, data);
4030         if (csum != CRC32_RESIDUAL) {
4031                 rc = -ENODEV;
4032                 goto test_nvram_done;
4033         }
4034
4035         csum = ether_crc_le(0x100, data + 0x100);
4036         if (csum != CRC32_RESIDUAL) {
4037                 rc = -ENODEV;
4038         }
4039
4040 test_nvram_done:
4041         return rc;
4042 }
4043
4044 static int
4045 bnx2_test_link(struct bnx2 *bp)
4046 {
4047         u32 bmsr;
4048
4049         spin_lock_bh(&bp->phy_lock);
4050         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4051         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4052         spin_unlock_bh(&bp->phy_lock);
4053
4054         if (bmsr & BMSR_LSTATUS) {
4055                 return 0;
4056         }
4057         return -ENODEV;
4058 }
4059
4060 static int
4061 bnx2_test_intr(struct bnx2 *bp)
4062 {
4063         int i;
4064         u32 val;
4065         u16 status_idx;
4066
4067         if (!netif_running(bp->dev))
4068                 return -ENODEV;
4069
4070         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4071
4072         /* This register is not touched during run-time. */
4073         val = REG_RD(bp, BNX2_HC_COMMAND);
4074         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
4075         REG_RD(bp, BNX2_HC_COMMAND);
4076
4077         for (i = 0; i < 10; i++) {
4078                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4079                         status_idx) {
4080
4081                         break;
4082                 }
4083
4084                 msleep_interruptible(10);
4085         }
4086         if (i < 10)
4087                 return 0;
4088
4089         return -ENODEV;
4090 }
4091
4092 static void
4093 bnx2_timer(unsigned long data)
4094 {
4095         struct bnx2 *bp = (struct bnx2 *) data;
4096         u32 msg;
4097
4098         if (!netif_running(bp->dev))
4099                 return;
4100
4101         if (atomic_read(&bp->intr_sem) != 0)
4102                 goto bnx2_restart_timer;
4103
4104         msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4105         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4106
4107         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4108             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4109
4110                 spin_lock(&bp->phy_lock);
4111                 if (bp->serdes_an_pending) {
4112                         bp->serdes_an_pending--;
4113                 }
4114                 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4115                         u32 bmcr;
4116
4117                         bp->current_interval = bp->timer_interval;
4118
4119                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4120
4121                         if (bmcr & BMCR_ANENABLE) {
4122                                 u32 phy1, phy2;
4123
4124                                 bnx2_write_phy(bp, 0x1c, 0x7c00);
4125                                 bnx2_read_phy(bp, 0x1c, &phy1);
4126
4127                                 bnx2_write_phy(bp, 0x17, 0x0f01);
4128                                 bnx2_read_phy(bp, 0x15, &phy2);
4129                                 bnx2_write_phy(bp, 0x17, 0x0f01);
4130                                 bnx2_read_phy(bp, 0x15, &phy2);
4131
4132                                 if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
4133                                         !(phy2 & 0x20)) {       /* no CONFIG */
4134
4135                                         bmcr &= ~BMCR_ANENABLE;
4136                                         bmcr |= BMCR_SPEED1000 |
4137                                                 BMCR_FULLDPLX;
4138                                         bnx2_write_phy(bp, MII_BMCR, bmcr);
4139                                         bp->phy_flags |=
4140                                                 PHY_PARALLEL_DETECT_FLAG;
4141                                 }
4142                         }
4143                 }
4144                 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4145                         (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4146                         u32 phy2;
4147
4148                         bnx2_write_phy(bp, 0x17, 0x0f01);
4149                         bnx2_read_phy(bp, 0x15, &phy2);
4150                         if (phy2 & 0x20) {
4151                                 u32 bmcr;
4152
4153                                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4154                                 bmcr |= BMCR_ANENABLE;
4155                                 bnx2_write_phy(bp, MII_BMCR, bmcr);
4156
4157                                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4158
4159                         }
4160                 }
4161                 else
4162                         bp->current_interval = bp->timer_interval;
4163
4164                 spin_unlock(&bp->phy_lock);
4165         }
4166
4167 bnx2_restart_timer:
4168         mod_timer(&bp->timer, jiffies + bp->current_interval);
4169 }
4170
4171 /* Called with rtnl_lock */
4172 static int
4173 bnx2_open(struct net_device *dev)
4174 {
4175         struct bnx2 *bp = dev->priv;
4176         int rc;
4177
4178         bnx2_set_power_state(bp, PCI_D0);
4179         bnx2_disable_int(bp);
4180
4181         rc = bnx2_alloc_mem(bp);
4182         if (rc)
4183                 return rc;
4184
4185         if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4186                 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4187                 !disable_msi) {
4188
4189                 if (pci_enable_msi(bp->pdev) == 0) {
4190                         bp->flags |= USING_MSI_FLAG;
4191                         rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4192                                         dev);
4193                 }
4194                 else {
4195                         rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4196                                         SA_SHIRQ, dev->name, dev);
4197                 }
4198         }
4199         else {
4200                 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4201                                 dev->name, dev);
4202         }
4203         if (rc) {
4204                 bnx2_free_mem(bp);
4205                 return rc;
4206         }
4207
4208         rc = bnx2_init_nic(bp);
4209
4210         if (rc) {
4211                 free_irq(bp->pdev->irq, dev);
4212                 if (bp->flags & USING_MSI_FLAG) {
4213                         pci_disable_msi(bp->pdev);
4214                         bp->flags &= ~USING_MSI_FLAG;
4215                 }
4216                 bnx2_free_skbs(bp);
4217                 bnx2_free_mem(bp);
4218                 return rc;
4219         }
4220
4221         mod_timer(&bp->timer, jiffies + bp->current_interval);
4222
4223         atomic_set(&bp->intr_sem, 0);
4224
4225         bnx2_enable_int(bp);
4226
4227         if (bp->flags & USING_MSI_FLAG) {
4228                 /* Test MSI to make sure it is working
4229                  * If MSI test fails, go back to INTx mode
4230                  */
4231                 if (bnx2_test_intr(bp) != 0) {
4232                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
4233                                " using MSI, switching to INTx mode. Please"
4234                                " report this failure to the PCI maintainer"
4235                                " and include system chipset information.\n",
4236                                bp->dev->name);
4237
4238                         bnx2_disable_int(bp);
4239                         free_irq(bp->pdev->irq, dev);
4240                         pci_disable_msi(bp->pdev);
4241                         bp->flags &= ~USING_MSI_FLAG;
4242
4243                         rc = bnx2_init_nic(bp);
4244
4245                         if (!rc) {
4246                                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4247                                         SA_SHIRQ, dev->name, dev);
4248                         }
4249                         if (rc) {
4250                                 bnx2_free_skbs(bp);
4251                                 bnx2_free_mem(bp);
4252                                 del_timer_sync(&bp->timer);
4253                                 return rc;
4254                         }
4255                         bnx2_enable_int(bp);
4256                 }
4257         }
4258         if (bp->flags & USING_MSI_FLAG) {
4259                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4260         }
4261
4262         netif_start_queue(dev);
4263
4264         return 0;
4265 }
4266
4267 static void
4268 bnx2_reset_task(void *data)
4269 {
4270         struct bnx2 *bp = data;
4271
4272         if (!netif_running(bp->dev))
4273                 return;
4274
4275         bp->in_reset_task = 1;
4276         bnx2_netif_stop(bp);
4277
4278         bnx2_init_nic(bp);
4279
4280         atomic_set(&bp->intr_sem, 1);
4281         bnx2_netif_start(bp);
4282         bp->in_reset_task = 0;
4283 }
4284
4285 static void
4286 bnx2_tx_timeout(struct net_device *dev)
4287 {
4288         struct bnx2 *bp = dev->priv;
4289
4290         /* This allows the netif to be shutdown gracefully before resetting */
4291         schedule_work(&bp->reset_task);
4292 }
4293
4294 #ifdef BCM_VLAN
4295 /* Called with rtnl_lock */
4296 static void
4297 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4298 {
4299         struct bnx2 *bp = dev->priv;
4300
4301         bnx2_netif_stop(bp);
4302
4303         bp->vlgrp = vlgrp;
4304         bnx2_set_rx_mode(dev);
4305
4306         bnx2_netif_start(bp);
4307 }
4308
4309 /* Called with rtnl_lock */
4310 static void
4311 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4312 {
4313         struct bnx2 *bp = dev->priv;
4314
4315         bnx2_netif_stop(bp);
4316
4317         if (bp->vlgrp)
4318                 bp->vlgrp->vlan_devices[vid] = NULL;
4319         bnx2_set_rx_mode(dev);
4320
4321         bnx2_netif_start(bp);
4322 }
4323 #endif
4324
4325 /* Called with dev->xmit_lock.
4326  * hard_start_xmit is pseudo-lockless - a lock is only required when
4327  * the tx queue is full. This way, we get the benefit of lockless
4328  * operations most of the time without the complexities to handle
4329  * netif_stop_queue/wake_queue race conditions.
4330  */
4331 static int
4332 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4333 {
4334         struct bnx2 *bp = dev->priv;
4335         dma_addr_t mapping;
4336         struct tx_bd *txbd;
4337         struct sw_bd *tx_buf;
4338         u32 len, vlan_tag_flags, last_frag, mss;
4339         u16 prod, ring_prod;
4340         int i;
4341
4342         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4343                 netif_stop_queue(dev);
4344                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4345                         dev->name);
4346
4347                 return NETDEV_TX_BUSY;
4348         }
4349         len = skb_headlen(skb);
4350         prod = bp->tx_prod;
4351         ring_prod = TX_RING_IDX(prod);
4352
4353         vlan_tag_flags = 0;
4354         if (skb->ip_summed == CHECKSUM_HW) {
4355                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4356         }
4357
4358         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4359                 vlan_tag_flags |=
4360                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4361         }
4362 #ifdef BCM_TSO
4363         if ((mss = skb_shinfo(skb)->tso_size) &&
4364                 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4365                 u32 tcp_opt_len, ip_tcp_len;
4366
4367                 if (skb_header_cloned(skb) &&
4368                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4369                         dev_kfree_skb(skb);
4370                         return NETDEV_TX_OK;
4371                 }
4372
4373                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4374                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4375
4376                 tcp_opt_len = 0;
4377                 if (skb->h.th->doff > 5) {
4378                         tcp_opt_len = (skb->h.th->doff - 5) << 2;
4379                 }
4380                 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4381
4382                 skb->nh.iph->check = 0;
4383                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4384                 skb->h.th->check =
4385                         ~csum_tcpudp_magic(skb->nh.iph->saddr,
4386                                             skb->nh.iph->daddr,
4387                                             0, IPPROTO_TCP, 0);
4388
4389                 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4390                         vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4391                                 (tcp_opt_len >> 2)) << 8;
4392                 }
4393         }
4394         else
4395 #endif
4396         {
4397                 mss = 0;
4398         }
4399
4400         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4401
4402         tx_buf = &bp->tx_buf_ring[ring_prod];
4403         tx_buf->skb = skb;
4404         pci_unmap_addr_set(tx_buf, mapping, mapping);
4405
4406         txbd = &bp->tx_desc_ring[ring_prod];
4407
4408         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4409         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4410         txbd->tx_bd_mss_nbytes = len | (mss << 16);
4411         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4412
4413         last_frag = skb_shinfo(skb)->nr_frags;
4414
4415         for (i = 0; i < last_frag; i++) {
4416                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4417
4418                 prod = NEXT_TX_BD(prod);
4419                 ring_prod = TX_RING_IDX(prod);
4420                 txbd = &bp->tx_desc_ring[ring_prod];
4421
4422                 len = frag->size;
4423                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4424                         len, PCI_DMA_TODEVICE);
4425                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4426                                 mapping, mapping);
4427
4428                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4429                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4430                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4431                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4432
4433         }
4434         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4435
4436         prod = NEXT_TX_BD(prod);
4437         bp->tx_prod_bseq += skb->len;
4438
4439         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4440         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4441
4442         mmiowb();
4443
4444         bp->tx_prod = prod;
4445         dev->trans_start = jiffies;
4446
4447         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4448                 spin_lock(&bp->tx_lock);
4449                 netif_stop_queue(dev);
4450
4451                 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4452                         netif_wake_queue(dev);
4453                 spin_unlock(&bp->tx_lock);
4454         }
4455
4456         return NETDEV_TX_OK;
4457 }
4458
4459 /* Called with rtnl_lock */
4460 static int
4461 bnx2_close(struct net_device *dev)
4462 {
4463         struct bnx2 *bp = dev->priv;
4464         u32 reset_code;
4465
4466         /* Calling flush_scheduled_work() may deadlock because
4467          * linkwatch_event() may be on the workqueue and it will try to get
4468          * the rtnl_lock which we are holding.
4469          */
4470         while (bp->in_reset_task)
4471                 msleep(1);
4472
4473         bnx2_netif_stop(bp);
4474         del_timer_sync(&bp->timer);
4475         if (bp->flags & NO_WOL_FLAG)
4476                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
4477         else if (bp->wol)
4478                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4479         else
4480                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4481         bnx2_reset_chip(bp, reset_code);
4482         free_irq(bp->pdev->irq, dev);
4483         if (bp->flags & USING_MSI_FLAG) {
4484                 pci_disable_msi(bp->pdev);
4485                 bp->flags &= ~USING_MSI_FLAG;
4486         }
4487         bnx2_free_skbs(bp);
4488         bnx2_free_mem(bp);
4489         bp->link_up = 0;
4490         netif_carrier_off(bp->dev);
4491         bnx2_set_power_state(bp, PCI_D3hot);
4492         return 0;
4493 }
4494
4495 #define GET_NET_STATS64(ctr)                                    \
4496         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
4497         (unsigned long) (ctr##_lo)
4498
4499 #define GET_NET_STATS32(ctr)            \
4500         (ctr##_lo)
4501
4502 #if (BITS_PER_LONG == 64)
4503 #define GET_NET_STATS   GET_NET_STATS64
4504 #else
4505 #define GET_NET_STATS   GET_NET_STATS32
4506 #endif
4507
4508 static struct net_device_stats *
4509 bnx2_get_stats(struct net_device *dev)
4510 {
4511         struct bnx2 *bp = dev->priv;
4512         struct statistics_block *stats_blk = bp->stats_blk;
4513         struct net_device_stats *net_stats = &bp->net_stats;
4514
4515         if (bp->stats_blk == NULL) {
4516                 return net_stats;
4517         }
4518         net_stats->rx_packets =
4519                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4520                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4521                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4522
4523         net_stats->tx_packets =
4524                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4525                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4526                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4527
4528         net_stats->rx_bytes =
4529                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4530
4531         net_stats->tx_bytes =
4532                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4533
4534         net_stats->multicast =
4535                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4536
4537         net_stats->collisions =
4538                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4539
4540         net_stats->rx_length_errors =
4541                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4542                 stats_blk->stat_EtherStatsOverrsizePkts);
4543
4544         net_stats->rx_over_errors =
4545                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4546
4547         net_stats->rx_frame_errors =
4548                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4549
4550         net_stats->rx_crc_errors =
4551                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4552
4553         net_stats->rx_errors = net_stats->rx_length_errors +
4554                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4555                 net_stats->rx_crc_errors;
4556
4557         net_stats->tx_aborted_errors =
4558                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4559                 stats_blk->stat_Dot3StatsLateCollisions);
4560
4561         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4562             (CHIP_ID(bp) == CHIP_ID_5708_A0))
4563                 net_stats->tx_carrier_errors = 0;
4564         else {
4565                 net_stats->tx_carrier_errors =
4566                         (unsigned long)
4567                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
4568         }
4569
4570         net_stats->tx_errors =
4571                 (unsigned long)
4572                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4573                 +
4574                 net_stats->tx_aborted_errors +
4575                 net_stats->tx_carrier_errors;
4576
4577         return net_stats;
4578 }
4579
4580 /* All ethtool functions called with rtnl_lock */
4581
4582 static int
4583 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4584 {
4585         struct bnx2 *bp = dev->priv;
4586
4587         cmd->supported = SUPPORTED_Autoneg;
4588         if (bp->phy_flags & PHY_SERDES_FLAG) {
4589                 cmd->supported |= SUPPORTED_1000baseT_Full |
4590                         SUPPORTED_FIBRE;
4591
4592                 cmd->port = PORT_FIBRE;
4593         }
4594         else {
4595                 cmd->supported |= SUPPORTED_10baseT_Half |
4596                         SUPPORTED_10baseT_Full |
4597                         SUPPORTED_100baseT_Half |
4598                         SUPPORTED_100baseT_Full |
4599                         SUPPORTED_1000baseT_Full |
4600                         SUPPORTED_TP;
4601
4602                 cmd->port = PORT_TP;
4603         }
4604
4605         cmd->advertising = bp->advertising;
4606
4607         if (bp->autoneg & AUTONEG_SPEED) {
4608                 cmd->autoneg = AUTONEG_ENABLE;
4609         }
4610         else {
4611                 cmd->autoneg = AUTONEG_DISABLE;
4612         }
4613
4614         if (netif_carrier_ok(dev)) {
4615                 cmd->speed = bp->line_speed;
4616                 cmd->duplex = bp->duplex;
4617         }
4618         else {
4619                 cmd->speed = -1;
4620                 cmd->duplex = -1;
4621         }
4622
4623         cmd->transceiver = XCVR_INTERNAL;
4624         cmd->phy_address = bp->phy_addr;
4625
4626         return 0;
4627 }
4628
4629 static int
4630 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4631 {
4632         struct bnx2 *bp = dev->priv;
4633         u8 autoneg = bp->autoneg;
4634         u8 req_duplex = bp->req_duplex;
4635         u16 req_line_speed = bp->req_line_speed;
4636         u32 advertising = bp->advertising;
4637
4638         if (cmd->autoneg == AUTONEG_ENABLE) {
4639                 autoneg |= AUTONEG_SPEED;
4640
4641                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4642
4643                 /* allow advertising 1 speed */
4644                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4645                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
4646                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
4647                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
4648
4649                         if (bp->phy_flags & PHY_SERDES_FLAG)
4650                                 return -EINVAL;
4651
4652                         advertising = cmd->advertising;
4653
4654                 }
4655                 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4656                         advertising = cmd->advertising;
4657                 }
4658                 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4659                         return -EINVAL;
4660                 }
4661                 else {
4662                         if (bp->phy_flags & PHY_SERDES_FLAG) {
4663                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4664                         }
4665                         else {
4666                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
4667                         }
4668                 }
4669                 advertising |= ADVERTISED_Autoneg;
4670         }
4671         else {
4672                 if (bp->phy_flags & PHY_SERDES_FLAG) {
4673                         if ((cmd->speed != SPEED_1000) ||
4674                                 (cmd->duplex != DUPLEX_FULL)) {
4675                                 return -EINVAL;
4676                         }
4677                 }
4678                 else if (cmd->speed == SPEED_1000) {
4679                         return -EINVAL;
4680                 }
4681                 autoneg &= ~AUTONEG_SPEED;
4682                 req_line_speed = cmd->speed;
4683                 req_duplex = cmd->duplex;
4684                 advertising = 0;
4685         }
4686
4687         bp->autoneg = autoneg;
4688         bp->advertising = advertising;
4689         bp->req_line_speed = req_line_speed;
4690         bp->req_duplex = req_duplex;
4691
4692         spin_lock_bh(&bp->phy_lock);
4693
4694         bnx2_setup_phy(bp);
4695
4696         spin_unlock_bh(&bp->phy_lock);
4697
4698         return 0;
4699 }
4700
4701 static void
4702 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4703 {
4704         struct bnx2 *bp = dev->priv;
4705
4706         strcpy(info->driver, DRV_MODULE_NAME);
4707         strcpy(info->version, DRV_MODULE_VERSION);
4708         strcpy(info->bus_info, pci_name(bp->pdev));
4709         info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4710         info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4711         info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4712         info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4713         info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4714         info->fw_version[7] = 0;
4715 }
4716
4717 static void
4718 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4719 {
4720         struct bnx2 *bp = dev->priv;
4721
4722         if (bp->flags & NO_WOL_FLAG) {
4723                 wol->supported = 0;
4724                 wol->wolopts = 0;
4725         }
4726         else {
4727                 wol->supported = WAKE_MAGIC;
4728                 if (bp->wol)
4729                         wol->wolopts = WAKE_MAGIC;
4730                 else
4731                         wol->wolopts = 0;
4732         }
4733         memset(&wol->sopass, 0, sizeof(wol->sopass));
4734 }
4735
4736 static int
4737 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4738 {
4739         struct bnx2 *bp = dev->priv;
4740
4741         if (wol->wolopts & ~WAKE_MAGIC)
4742                 return -EINVAL;
4743
4744         if (wol->wolopts & WAKE_MAGIC) {
4745                 if (bp->flags & NO_WOL_FLAG)
4746                         return -EINVAL;
4747
4748                 bp->wol = 1;
4749         }
4750         else {
4751                 bp->wol = 0;
4752         }
4753         return 0;
4754 }
4755
4756 static int
4757 bnx2_nway_reset(struct net_device *dev)
4758 {
4759         struct bnx2 *bp = dev->priv;
4760         u32 bmcr;
4761
4762         if (!(bp->autoneg & AUTONEG_SPEED)) {
4763                 return -EINVAL;
4764         }
4765
4766         spin_lock_bh(&bp->phy_lock);
4767
4768         /* Force a link down visible on the other side */
4769         if (bp->phy_flags & PHY_SERDES_FLAG) {
4770                 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4771                 spin_unlock_bh(&bp->phy_lock);
4772
4773                 msleep(20);
4774
4775                 spin_lock_bh(&bp->phy_lock);
4776                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4777                         bp->current_interval = SERDES_AN_TIMEOUT;
4778                         bp->serdes_an_pending = 1;
4779                         mod_timer(&bp->timer, jiffies + bp->current_interval);
4780                 }
4781         }
4782
4783         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4784         bmcr &= ~BMCR_LOOPBACK;
4785         bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4786
4787         spin_unlock_bh(&bp->phy_lock);
4788
4789         return 0;
4790 }
4791
4792 static int
4793 bnx2_get_eeprom_len(struct net_device *dev)
4794 {
4795         struct bnx2 *bp = dev->priv;
4796
4797         if (bp->flash_info == 0)
4798                 return 0;
4799
4800         return (int) bp->flash_info->total_size;
4801 }
4802
4803 static int
4804 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4805                 u8 *eebuf)
4806 {
4807         struct bnx2 *bp = dev->priv;
4808         int rc;
4809
4810         /* parameters already validated in ethtool_get_eeprom */
4811
4812         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4813
4814         return rc;
4815 }
4816
4817 static int
4818 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4819                 u8 *eebuf)
4820 {
4821         struct bnx2 *bp = dev->priv;
4822         int rc;
4823
4824         /* parameters already validated in ethtool_set_eeprom */
4825
4826         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4827
4828         return rc;
4829 }
4830
4831 static int
4832 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4833 {
4834         struct bnx2 *bp = dev->priv;
4835
4836         memset(coal, 0, sizeof(struct ethtool_coalesce));
4837
4838         coal->rx_coalesce_usecs = bp->rx_ticks;
4839         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4840         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4841         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4842
4843         coal->tx_coalesce_usecs = bp->tx_ticks;
4844         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4845         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4846         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4847
4848         coal->stats_block_coalesce_usecs = bp->stats_ticks;
4849
4850         return 0;
4851 }
4852
4853 static int
4854 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4855 {
4856         struct bnx2 *bp = dev->priv;
4857
4858         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4859         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4860
4861         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4862         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4863
4864         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4865         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4866
4867         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4868         if (bp->rx_quick_cons_trip_int > 0xff)
4869                 bp->rx_quick_cons_trip_int = 0xff;
4870
4871         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4872         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4873
4874         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4875         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4876
4877         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4878         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4879
4880         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4881         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4882                 0xff;
4883
4884         bp->stats_ticks = coal->stats_block_coalesce_usecs;
4885         if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4886         bp->stats_ticks &= 0xffff00;
4887
4888         if (netif_running(bp->dev)) {
4889                 bnx2_netif_stop(bp);
4890                 bnx2_init_nic(bp);
4891                 bnx2_netif_start(bp);
4892         }
4893
4894         return 0;
4895 }
4896
4897 static void
4898 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4899 {
4900         struct bnx2 *bp = dev->priv;
4901
4902         ering->rx_max_pending = MAX_RX_DESC_CNT;
4903         ering->rx_mini_max_pending = 0;
4904         ering->rx_jumbo_max_pending = 0;
4905
4906         ering->rx_pending = bp->rx_ring_size;
4907         ering->rx_mini_pending = 0;
4908         ering->rx_jumbo_pending = 0;
4909
4910         ering->tx_max_pending = MAX_TX_DESC_CNT;
4911         ering->tx_pending = bp->tx_ring_size;
4912 }
4913
4914 static int
4915 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4916 {
4917         struct bnx2 *bp = dev->priv;
4918
4919         if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4920                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4921                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4922
4923                 return -EINVAL;
4924         }
4925         bp->rx_ring_size = ering->rx_pending;
4926         bp->tx_ring_size = ering->tx_pending;
4927
4928         if (netif_running(bp->dev)) {
4929                 bnx2_netif_stop(bp);
4930                 bnx2_init_nic(bp);
4931                 bnx2_netif_start(bp);
4932         }
4933
4934         return 0;
4935 }
4936
4937 static void
4938 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4939 {
4940         struct bnx2 *bp = dev->priv;
4941
4942         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4943         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4944         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4945 }
4946
4947 static int
4948 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4949 {
4950         struct bnx2 *bp = dev->priv;
4951
4952         bp->req_flow_ctrl = 0;
4953         if (epause->rx_pause)
4954                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4955         if (epause->tx_pause)
4956                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4957
4958         if (epause->autoneg) {
4959                 bp->autoneg |= AUTONEG_FLOW_CTRL;
4960         }
4961         else {
4962                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4963         }
4964
4965         spin_lock_bh(&bp->phy_lock);
4966
4967         bnx2_setup_phy(bp);
4968
4969         spin_unlock_bh(&bp->phy_lock);
4970
4971         return 0;
4972 }
4973
4974 static u32
4975 bnx2_get_rx_csum(struct net_device *dev)
4976 {
4977         struct bnx2 *bp = dev->priv;
4978
4979         return bp->rx_csum;
4980 }
4981
4982 static int
4983 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4984 {
4985         struct bnx2 *bp = dev->priv;
4986
4987         bp->rx_csum = data;
4988         return 0;
4989 }
4990
4991 #define BNX2_NUM_STATS 45
4992
4993 static struct {
4994         char string[ETH_GSTRING_LEN];
4995 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4996         { "rx_bytes" },
4997         { "rx_error_bytes" },
4998         { "tx_bytes" },
4999         { "tx_error_bytes" },
5000         { "rx_ucast_packets" },
5001         { "rx_mcast_packets" },
5002         { "rx_bcast_packets" },
5003         { "tx_ucast_packets" },
5004         { "tx_mcast_packets" },
5005         { "tx_bcast_packets" },
5006         { "tx_mac_errors" },
5007         { "tx_carrier_errors" },
5008         { "rx_crc_errors" },
5009         { "rx_align_errors" },
5010         { "tx_single_collisions" },
5011         { "tx_multi_collisions" },
5012         { "tx_deferred" },
5013         { "tx_excess_collisions" },
5014         { "tx_late_collisions" },
5015         { "tx_total_collisions" },
5016         { "rx_fragments" },
5017         { "rx_jabbers" },
5018         { "rx_undersize_packets" },
5019         { "rx_oversize_packets" },
5020         { "rx_64_byte_packets" },
5021         { "rx_65_to_127_byte_packets" },
5022         { "rx_128_to_255_byte_packets" },
5023         { "rx_256_to_511_byte_packets" },
5024         { "rx_512_to_1023_byte_packets" },
5025         { "rx_1024_to_1522_byte_packets" },
5026         { "rx_1523_to_9022_byte_packets" },
5027         { "tx_64_byte_packets" },
5028         { "tx_65_to_127_byte_packets" },
5029         { "tx_128_to_255_byte_packets" },
5030         { "tx_256_to_511_byte_packets" },
5031         { "tx_512_to_1023_byte_packets" },
5032         { "tx_1024_to_1522_byte_packets" },
5033         { "tx_1523_to_9022_byte_packets" },
5034         { "rx_xon_frames" },
5035         { "rx_xoff_frames" },
5036         { "tx_xon_frames" },
5037         { "tx_xoff_frames" },
5038         { "rx_mac_ctrl_frames" },
5039         { "rx_filtered_packets" },
5040         { "rx_discards" },
5041 };
5042
5043 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5044
5045 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5046     STATS_OFFSET32(stat_IfHCInOctets_hi),
5047     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5048     STATS_OFFSET32(stat_IfHCOutOctets_hi),
5049     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5050     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5051     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5052     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5053     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5054     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5055     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5056     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5057     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5058     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5059     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5060     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5061     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5062     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5063     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5064     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5065     STATS_OFFSET32(stat_EtherStatsCollisions),
5066     STATS_OFFSET32(stat_EtherStatsFragments),
5067     STATS_OFFSET32(stat_EtherStatsJabbers),
5068     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5069     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5070     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5071     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5072     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5073     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5074     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5075     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5076     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5077     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5078     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5079     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5080     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5081     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5082     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5083     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5084     STATS_OFFSET32(stat_XonPauseFramesReceived),
5085     STATS_OFFSET32(stat_XoffPauseFramesReceived),
5086     STATS_OFFSET32(stat_OutXonSent),
5087     STATS_OFFSET32(stat_OutXoffSent),
5088     STATS_OFFSET32(stat_MacControlFramesReceived),
5089     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5090     STATS_OFFSET32(stat_IfInMBUFDiscards),
5091 };
5092
5093 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5094  * skipped because of errata.
5095  */
5096 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5097         8,0,8,8,8,8,8,8,8,8,
5098         4,0,4,4,4,4,4,4,4,4,
5099         4,4,4,4,4,4,4,4,4,4,
5100         4,4,4,4,4,4,4,4,4,4,
5101         4,4,4,4,4,
5102 };
5103
5104 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5105         8,0,8,8,8,8,8,8,8,8,
5106         4,4,4,4,4,4,4,4,4,4,
5107         4,4,4,4,4,4,4,4,4,4,
5108         4,4,4,4,4,4,4,4,4,4,
5109         4,4,4,4,4,
5110 };
5111
5112 #define BNX2_NUM_TESTS 6
5113
5114 static struct {
5115         char string[ETH_GSTRING_LEN];
5116 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5117         { "register_test (offline)" },
5118         { "memory_test (offline)" },
5119         { "loopback_test (offline)" },
5120         { "nvram_test (online)" },
5121         { "interrupt_test (online)" },
5122         { "link_test (online)" },
5123 };
5124
5125 static int
5126 bnx2_self_test_count(struct net_device *dev)
5127 {
5128         return BNX2_NUM_TESTS;
5129 }
5130
5131 static void
5132 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5133 {
5134         struct bnx2 *bp = dev->priv;
5135
5136         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5137         if (etest->flags & ETH_TEST_FL_OFFLINE) {
5138                 bnx2_netif_stop(bp);
5139                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5140                 bnx2_free_skbs(bp);
5141
5142                 if (bnx2_test_registers(bp) != 0) {
5143                         buf[0] = 1;
5144                         etest->flags |= ETH_TEST_FL_FAILED;
5145                 }
5146                 if (bnx2_test_memory(bp) != 0) {
5147                         buf[1] = 1;
5148                         etest->flags |= ETH_TEST_FL_FAILED;
5149                 }
5150                 if (bnx2_test_loopback(bp) != 0) {
5151                         buf[2] = 1;
5152                         etest->flags |= ETH_TEST_FL_FAILED;
5153                 }
5154
5155                 if (!netif_running(bp->dev)) {
5156                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5157                 }
5158                 else {
5159                         bnx2_init_nic(bp);
5160                         bnx2_netif_start(bp);
5161                 }
5162
5163                 /* wait for link up */
5164                 msleep_interruptible(3000);
5165                 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5166                         msleep_interruptible(4000);
5167         }
5168
5169         if (bnx2_test_nvram(bp) != 0) {
5170                 buf[3] = 1;
5171                 etest->flags |= ETH_TEST_FL_FAILED;
5172         }
5173         if (bnx2_test_intr(bp) != 0) {
5174                 buf[4] = 1;
5175                 etest->flags |= ETH_TEST_FL_FAILED;
5176         }
5177
5178         if (bnx2_test_link(bp) != 0) {
5179                 buf[5] = 1;
5180                 etest->flags |= ETH_TEST_FL_FAILED;
5181
5182         }
5183 }
5184
5185 static void
5186 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5187 {
5188         switch (stringset) {
5189         case ETH_SS_STATS:
5190                 memcpy(buf, bnx2_stats_str_arr,
5191                         sizeof(bnx2_stats_str_arr));
5192                 break;
5193         case ETH_SS_TEST:
5194                 memcpy(buf, bnx2_tests_str_arr,
5195                         sizeof(bnx2_tests_str_arr));
5196                 break;
5197         }
5198 }
5199
5200 static int
5201 bnx2_get_stats_count(struct net_device *dev)
5202 {
5203         return BNX2_NUM_STATS;
5204 }
5205
5206 static void
5207 bnx2_get_ethtool_stats(struct net_device *dev,
5208                 struct ethtool_stats *stats, u64 *buf)
5209 {
5210         struct bnx2 *bp = dev->priv;
5211         int i;
5212         u32 *hw_stats = (u32 *) bp->stats_blk;
5213         u8 *stats_len_arr = NULL;
5214
5215         if (hw_stats == NULL) {
5216                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5217                 return;
5218         }
5219
5220         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5221             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5222             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5223             (CHIP_ID(bp) == CHIP_ID_5708_A0))
5224                 stats_len_arr = bnx2_5706_stats_len_arr;
5225         else
5226                 stats_len_arr = bnx2_5708_stats_len_arr;
5227
5228         for (i = 0; i < BNX2_NUM_STATS; i++) {
5229                 if (stats_len_arr[i] == 0) {
5230                         /* skip this counter */
5231                         buf[i] = 0;
5232                         continue;
5233                 }
5234                 if (stats_len_arr[i] == 4) {
5235                         /* 4-byte counter */
5236                         buf[i] = (u64)
5237                                 *(hw_stats + bnx2_stats_offset_arr[i]);
5238                         continue;
5239                 }
5240                 /* 8-byte counter */
5241                 buf[i] = (((u64) *(hw_stats +
5242                                         bnx2_stats_offset_arr[i])) << 32) +
5243                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5244         }
5245 }
5246
5247 static int
5248 bnx2_phys_id(struct net_device *dev, u32 data)
5249 {
5250         struct bnx2 *bp = dev->priv;
5251         int i;
5252         u32 save;
5253
5254         if (data == 0)
5255                 data = 2;
5256
5257         save = REG_RD(bp, BNX2_MISC_CFG);
5258         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5259
5260         for (i = 0; i < (data * 2); i++) {
5261                 if ((i % 2) == 0) {
5262                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5263                 }
5264                 else {
5265                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5266                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
5267                                 BNX2_EMAC_LED_100MB_OVERRIDE |
5268                                 BNX2_EMAC_LED_10MB_OVERRIDE |
5269                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5270                                 BNX2_EMAC_LED_TRAFFIC);
5271                 }
5272                 msleep_interruptible(500);
5273                 if (signal_pending(current))
5274                         break;
5275         }
5276         REG_WR(bp, BNX2_EMAC_LED, 0);
5277         REG_WR(bp, BNX2_MISC_CFG, save);
5278         return 0;
5279 }
5280
5281 static struct ethtool_ops bnx2_ethtool_ops = {
5282         .get_settings           = bnx2_get_settings,
5283         .set_settings           = bnx2_set_settings,
5284         .get_drvinfo            = bnx2_get_drvinfo,
5285         .get_wol                = bnx2_get_wol,
5286         .set_wol                = bnx2_set_wol,
5287         .nway_reset             = bnx2_nway_reset,
5288         .get_link               = ethtool_op_get_link,
5289         .get_eeprom_len         = bnx2_get_eeprom_len,
5290         .get_eeprom             = bnx2_get_eeprom,
5291         .set_eeprom             = bnx2_set_eeprom,
5292         .get_coalesce           = bnx2_get_coalesce,
5293         .set_coalesce           = bnx2_set_coalesce,
5294         .get_ringparam          = bnx2_get_ringparam,
5295         .set_ringparam          = bnx2_set_ringparam,
5296         .get_pauseparam         = bnx2_get_pauseparam,
5297         .set_pauseparam         = bnx2_set_pauseparam,
5298         .get_rx_csum            = bnx2_get_rx_csum,
5299         .set_rx_csum            = bnx2_set_rx_csum,
5300         .get_tx_csum            = ethtool_op_get_tx_csum,
5301         .set_tx_csum            = ethtool_op_set_tx_csum,
5302         .get_sg                 = ethtool_op_get_sg,
5303         .set_sg                 = ethtool_op_set_sg,
5304 #ifdef BCM_TSO
5305         .get_tso                = ethtool_op_get_tso,
5306         .set_tso                = ethtool_op_set_tso,
5307 #endif
5308         .self_test_count        = bnx2_self_test_count,
5309         .self_test              = bnx2_self_test,
5310         .get_strings            = bnx2_get_strings,
5311         .phys_id                = bnx2_phys_id,
5312         .get_stats_count        = bnx2_get_stats_count,
5313         .get_ethtool_stats      = bnx2_get_ethtool_stats,
5314         .get_perm_addr          = ethtool_op_get_perm_addr,
5315 };
5316
5317 /* Called with rtnl_lock */
5318 static int
5319 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5320 {
5321         struct mii_ioctl_data *data = if_mii(ifr);
5322         struct bnx2 *bp = dev->priv;
5323         int err;
5324
5325         switch(cmd) {
5326         case SIOCGMIIPHY:
5327                 data->phy_id = bp->phy_addr;
5328
5329                 /* fallthru */
5330         case SIOCGMIIREG: {
5331                 u32 mii_regval;
5332
5333                 spin_lock_bh(&bp->phy_lock);
5334                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5335                 spin_unlock_bh(&bp->phy_lock);
5336
5337                 data->val_out = mii_regval;
5338
5339                 return err;
5340         }
5341
5342         case SIOCSMIIREG:
5343                 if (!capable(CAP_NET_ADMIN))
5344                         return -EPERM;
5345
5346                 spin_lock_bh(&bp->phy_lock);
5347                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5348                 spin_unlock_bh(&bp->phy_lock);
5349
5350                 return err;
5351
5352         default:
5353                 /* do nothing */
5354                 break;
5355         }
5356         return -EOPNOTSUPP;
5357 }
5358
5359 /* Called with rtnl_lock */
5360 static int
5361 bnx2_change_mac_addr(struct net_device *dev, void *p)
5362 {
5363         struct sockaddr *addr = p;
5364         struct bnx2 *bp = dev->priv;
5365
5366         if (!is_valid_ether_addr(addr->sa_data))
5367                 return -EINVAL;
5368
5369         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5370         if (netif_running(dev))
5371                 bnx2_set_mac_addr(bp);
5372
5373         return 0;
5374 }
5375
5376 /* Called with rtnl_lock */
5377 static int
5378 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5379 {
5380         struct bnx2 *bp = dev->priv;
5381
5382         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5383                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5384                 return -EINVAL;
5385
5386         dev->mtu = new_mtu;
5387         if (netif_running(dev)) {
5388                 bnx2_netif_stop(bp);
5389
5390                 bnx2_init_nic(bp);
5391
5392                 bnx2_netif_start(bp);
5393         }
5394         return 0;
5395 }
5396
5397 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5398 static void
5399 poll_bnx2(struct net_device *dev)
5400 {
5401         struct bnx2 *bp = dev->priv;
5402
5403         disable_irq(bp->pdev->irq);
5404         bnx2_interrupt(bp->pdev->irq, dev, NULL);
5405         enable_irq(bp->pdev->irq);
5406 }
5407 #endif
5408
5409 static int __devinit
5410 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5411 {
5412         struct bnx2 *bp;
5413         unsigned long mem_len;
5414         int rc;
5415         u32 reg;
5416
5417         SET_MODULE_OWNER(dev);
5418         SET_NETDEV_DEV(dev, &pdev->dev);
5419         bp = dev->priv;
5420
5421         bp->flags = 0;
5422         bp->phy_flags = 0;
5423
5424         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5425         rc = pci_enable_device(pdev);
5426         if (rc) {
5427                 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5428                 goto err_out;
5429         }
5430
5431         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5432                 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5433                        "aborting.\n");
5434                 rc = -ENODEV;
5435                 goto err_out_disable;
5436         }
5437
5438         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5439         if (rc) {
5440                 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5441                 goto err_out_disable;
5442         }
5443
5444         pci_set_master(pdev);
5445
5446         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5447         if (bp->pm_cap == 0) {
5448                 printk(KERN_ERR PFX "Cannot find power management capability, "
5449                                "aborting.\n");
5450                 rc = -EIO;
5451                 goto err_out_release;
5452         }
5453
5454         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5455         if (bp->pcix_cap == 0) {
5456                 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5457                 rc = -EIO;
5458                 goto err_out_release;
5459         }
5460
5461         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5462                 bp->flags |= USING_DAC_FLAG;
5463                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5464                         printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5465                                "failed, aborting.\n");
5466                         rc = -EIO;
5467                         goto err_out_release;
5468                 }
5469         }
5470         else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5471                 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5472                 rc = -EIO;
5473                 goto err_out_release;
5474         }
5475
5476         bp->dev = dev;
5477         bp->pdev = pdev;
5478
5479         spin_lock_init(&bp->phy_lock);
5480         spin_lock_init(&bp->tx_lock);
5481         INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5482
5483         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5484         mem_len = MB_GET_CID_ADDR(17);
5485         dev->mem_end = dev->mem_start + mem_len;
5486         dev->irq = pdev->irq;
5487
5488         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5489
5490         if (!bp->regview) {
5491                 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5492                 rc = -ENOMEM;
5493                 goto err_out_release;
5494         }
5495
5496         /* Configure byte swap and enable write to the reg_window registers.
5497          * Rely on CPU to do target byte swapping on big endian systems
5498          * The chip's target access swapping will not swap all accesses
5499          */
5500         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5501                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5502                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5503
5504         bnx2_set_power_state(bp, PCI_D0);
5505
5506         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5507
5508         /* Get bus information. */
5509         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5510         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5511                 u32 clkreg;
5512
5513                 bp->flags |= PCIX_FLAG;
5514
5515                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5516
5517                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5518                 switch (clkreg) {
5519                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5520                         bp->bus_speed_mhz = 133;
5521                         break;
5522
5523                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5524                         bp->bus_speed_mhz = 100;
5525                         break;
5526
5527                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5528                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5529                         bp->bus_speed_mhz = 66;
5530                         break;
5531
5532                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5533                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5534                         bp->bus_speed_mhz = 50;
5535                         break;
5536
5537                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5538                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5539                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5540                         bp->bus_speed_mhz = 33;
5541                         break;
5542                 }
5543         }
5544         else {
5545                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5546                         bp->bus_speed_mhz = 66;
5547                 else
5548                         bp->bus_speed_mhz = 33;
5549         }
5550
5551         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5552                 bp->flags |= PCI_32BIT_FLAG;
5553
5554         /* 5706A0 may falsely detect SERR and PERR. */
5555         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5556                 reg = REG_RD(bp, PCI_COMMAND);
5557                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5558                 REG_WR(bp, PCI_COMMAND, reg);
5559         }
5560         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5561                 !(bp->flags & PCIX_FLAG)) {
5562
5563                 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5564                        "aborting.\n");
5565                 goto err_out_unmap;
5566         }
5567
5568         bnx2_init_nvram(bp);
5569
5570         reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5571
5572         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5573             BNX2_SHM_HDR_SIGNATURE_SIG)
5574                 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5575         else
5576                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5577
5578         /* Get the permanent MAC address.  First we need to make sure the
5579          * firmware is actually running.
5580          */
5581         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5582
5583         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5584             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5585                 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5586                 rc = -ENODEV;
5587                 goto err_out_unmap;
5588         }
5589
5590         bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5591
5592         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5593         bp->mac_addr[0] = (u8) (reg >> 8);
5594         bp->mac_addr[1] = (u8) reg;
5595
5596         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5597         bp->mac_addr[2] = (u8) (reg >> 24);
5598         bp->mac_addr[3] = (u8) (reg >> 16);
5599         bp->mac_addr[4] = (u8) (reg >> 8);
5600         bp->mac_addr[5] = (u8) reg;
5601
5602         bp->tx_ring_size = MAX_TX_DESC_CNT;
5603         bp->rx_ring_size = 100;
5604
5605         bp->rx_csum = 1;
5606
5607         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5608
5609         bp->tx_quick_cons_trip_int = 20;
5610         bp->tx_quick_cons_trip = 20;
5611         bp->tx_ticks_int = 80;
5612         bp->tx_ticks = 80;
5613
5614         bp->rx_quick_cons_trip_int = 6;
5615         bp->rx_quick_cons_trip = 6;
5616         bp->rx_ticks_int = 18;
5617         bp->rx_ticks = 18;
5618
5619         bp->stats_ticks = 1000000 & 0xffff00;
5620
5621         bp->timer_interval =  HZ;
5622         bp->current_interval =  HZ;
5623
5624         bp->phy_addr = 1;
5625
5626         /* Disable WOL support if we are running on a SERDES chip. */
5627         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5628                 bp->phy_flags |= PHY_SERDES_FLAG;
5629                 bp->flags |= NO_WOL_FLAG;
5630                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5631                         bp->phy_addr = 2;
5632                         reg = REG_RD_IND(bp, bp->shmem_base +
5633                                          BNX2_SHARED_HW_CFG_CONFIG);
5634                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5635                                 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5636                 }
5637         }
5638
5639         if (CHIP_NUM(bp) == CHIP_NUM_5708)
5640                 bp->flags |= NO_WOL_FLAG;
5641
5642         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5643                 bp->tx_quick_cons_trip_int =
5644                         bp->tx_quick_cons_trip;
5645                 bp->tx_ticks_int = bp->tx_ticks;
5646                 bp->rx_quick_cons_trip_int =
5647                         bp->rx_quick_cons_trip;
5648                 bp->rx_ticks_int = bp->rx_ticks;
5649                 bp->comp_prod_trip_int = bp->comp_prod_trip;
5650                 bp->com_ticks_int = bp->com_ticks;
5651                 bp->cmd_ticks_int = bp->cmd_ticks;
5652         }
5653
5654         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5655         bp->req_line_speed = 0;
5656         if (bp->phy_flags & PHY_SERDES_FLAG) {
5657                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5658
5659                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5660                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5661                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5662                         bp->autoneg = 0;
5663                         bp->req_line_speed = bp->line_speed = SPEED_1000;
5664                         bp->req_duplex = DUPLEX_FULL;
5665                 }
5666         }
5667         else {
5668                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5669         }
5670
5671         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5672
5673         init_timer(&bp->timer);
5674         bp->timer.expires = RUN_AT(bp->timer_interval);
5675         bp->timer.data = (unsigned long) bp;
5676         bp->timer.function = bnx2_timer;
5677
5678         return 0;
5679
5680 err_out_unmap:
5681         if (bp->regview) {
5682                 iounmap(bp->regview);
5683                 bp->regview = NULL;
5684         }
5685
5686 err_out_release:
5687         pci_release_regions(pdev);
5688
5689 err_out_disable:
5690         pci_disable_device(pdev);
5691         pci_set_drvdata(pdev, NULL);
5692
5693 err_out:
5694         return rc;
5695 }
5696
5697 static int __devinit
5698 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5699 {
5700         static int version_printed = 0;
5701         struct net_device *dev = NULL;
5702         struct bnx2 *bp;
5703         int rc, i;
5704
5705         if (version_printed++ == 0)
5706                 printk(KERN_INFO "%s", version);
5707
5708         /* dev zeroed in init_etherdev */
5709         dev = alloc_etherdev(sizeof(*bp));
5710
5711         if (!dev)
5712                 return -ENOMEM;
5713
5714         rc = bnx2_init_board(pdev, dev);
5715         if (rc < 0) {
5716                 free_netdev(dev);
5717                 return rc;
5718         }
5719
5720         dev->open = bnx2_open;
5721         dev->hard_start_xmit = bnx2_start_xmit;
5722         dev->stop = bnx2_close;
5723         dev->get_stats = bnx2_get_stats;
5724         dev->set_multicast_list = bnx2_set_rx_mode;
5725         dev->do_ioctl = bnx2_ioctl;
5726         dev->set_mac_address = bnx2_change_mac_addr;
5727         dev->change_mtu = bnx2_change_mtu;
5728         dev->tx_timeout = bnx2_tx_timeout;
5729         dev->watchdog_timeo = TX_TIMEOUT;
5730 #ifdef BCM_VLAN
5731         dev->vlan_rx_register = bnx2_vlan_rx_register;
5732         dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5733 #endif
5734         dev->poll = bnx2_poll;
5735         dev->ethtool_ops = &bnx2_ethtool_ops;
5736         dev->weight = 64;
5737
5738         bp = dev->priv;
5739
5740 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5741         dev->poll_controller = poll_bnx2;
5742 #endif
5743
5744         if ((rc = register_netdev(dev))) {
5745                 printk(KERN_ERR PFX "Cannot register net device\n");
5746                 if (bp->regview)
5747                         iounmap(bp->regview);
5748                 pci_release_regions(pdev);
5749                 pci_disable_device(pdev);
5750                 pci_set_drvdata(pdev, NULL);
5751                 free_netdev(dev);
5752                 return rc;
5753         }
5754
5755         pci_set_drvdata(pdev, dev);
5756
5757         memcpy(dev->dev_addr, bp->mac_addr, 6);
5758         memcpy(dev->perm_addr, bp->mac_addr, 6);
5759         bp->name = board_info[ent->driver_data].name,
5760         printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5761                 "IRQ %d, ",
5762                 dev->name,
5763                 bp->name,
5764                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5765                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5766                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5767                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5768                 bp->bus_speed_mhz,
5769                 dev->base_addr,
5770                 bp->pdev->irq);
5771
5772         printk("node addr ");
5773         for (i = 0; i < 6; i++)
5774                 printk("%2.2x", dev->dev_addr[i]);
5775         printk("\n");
5776
5777         dev->features |= NETIF_F_SG;
5778         if (bp->flags & USING_DAC_FLAG)
5779                 dev->features |= NETIF_F_HIGHDMA;
5780         dev->features |= NETIF_F_IP_CSUM;
5781 #ifdef BCM_VLAN
5782         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5783 #endif
5784 #ifdef BCM_TSO
5785         dev->features |= NETIF_F_TSO;
5786 #endif
5787
5788         netif_carrier_off(bp->dev);
5789
5790         return 0;
5791 }
5792
5793 static void __devexit
5794 bnx2_remove_one(struct pci_dev *pdev)
5795 {
5796         struct net_device *dev = pci_get_drvdata(pdev);
5797         struct bnx2 *bp = dev->priv;
5798
5799         flush_scheduled_work();
5800
5801         unregister_netdev(dev);
5802
5803         if (bp->regview)
5804                 iounmap(bp->regview);
5805
5806         free_netdev(dev);
5807         pci_release_regions(pdev);
5808         pci_disable_device(pdev);
5809         pci_set_drvdata(pdev, NULL);
5810 }
5811
5812 static int
5813 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5814 {
5815         struct net_device *dev = pci_get_drvdata(pdev);
5816         struct bnx2 *bp = dev->priv;
5817         u32 reset_code;
5818
5819         if (!netif_running(dev))
5820                 return 0;
5821
5822         bnx2_netif_stop(bp);
5823         netif_device_detach(dev);
5824         del_timer_sync(&bp->timer);
5825         if (bp->flags & NO_WOL_FLAG)
5826                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
5827         else if (bp->wol)
5828                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5829         else
5830                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5831         bnx2_reset_chip(bp, reset_code);
5832         bnx2_free_skbs(bp);
5833         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5834         return 0;
5835 }
5836
5837 static int
5838 bnx2_resume(struct pci_dev *pdev)
5839 {
5840         struct net_device *dev = pci_get_drvdata(pdev);
5841         struct bnx2 *bp = dev->priv;
5842
5843         if (!netif_running(dev))
5844                 return 0;
5845
5846         bnx2_set_power_state(bp, PCI_D0);
5847         netif_device_attach(dev);
5848         bnx2_init_nic(bp);
5849         bnx2_netif_start(bp);
5850         return 0;
5851 }
5852
5853 static struct pci_driver bnx2_pci_driver = {
5854         .name           = DRV_MODULE_NAME,
5855         .id_table       = bnx2_pci_tbl,
5856         .probe          = bnx2_init_one,
5857         .remove         = __devexit_p(bnx2_remove_one),
5858         .suspend        = bnx2_suspend,
5859         .resume         = bnx2_resume,
5860 };
5861
5862 static int __init bnx2_init(void)
5863 {
5864         return pci_module_init(&bnx2_pci_driver);
5865 }
5866
5867 static void __exit bnx2_cleanup(void)
5868 {
5869         pci_unregister_driver(&bnx2_pci_driver);
5870 }
5871
5872 module_init(bnx2_init);
5873 module_exit(bnx2_cleanup);
5874
5875
5876