2 * Blackfin On-Chip MAC Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/irq.h>
21 #include <linux/ioport.h>
22 #include <linux/crc32.h>
23 #include <linux/device.h>
24 #include <linux/spinlock.h>
25 #include <linux/mii.h>
26 #include <linux/phy.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/skbuff.h>
31 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
36 #include <asm/div64.h>
38 #include <asm/blackfin.h>
39 #include <asm/cacheflush.h>
40 #include <asm/portmux.h>
44 #define DRV_NAME "bfin_mac"
45 #define DRV_VERSION "1.1"
46 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
47 #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
49 MODULE_AUTHOR(DRV_AUTHOR);
50 MODULE_LICENSE("GPL");
51 MODULE_DESCRIPTION(DRV_DESC);
52 MODULE_ALIAS("platform:bfin_mac");
54 #if defined(CONFIG_BFIN_MAC_USE_L1)
55 # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size)
56 # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr)
58 # define bfin_mac_alloc(dma_handle, size) \
59 dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL)
60 # define bfin_mac_free(dma_handle, ptr) \
61 dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle)
64 #define PKT_BUF_SZ 1580
66 #define MAX_TIMEOUT_CNT 500
68 /* pointers to maintain transmit list */
69 static struct net_dma_desc_tx *tx_list_head;
70 static struct net_dma_desc_tx *tx_list_tail;
71 static struct net_dma_desc_rx *rx_list_head;
72 static struct net_dma_desc_rx *rx_list_tail;
73 static struct net_dma_desc_rx *current_rx_ptr;
74 static struct net_dma_desc_tx *current_tx_ptr;
75 static struct net_dma_desc_tx *tx_desc;
76 static struct net_dma_desc_rx *rx_desc;
78 #if defined(CONFIG_BFIN_MAC_RMII)
79 static u16 pin_req[] = P_RMII0;
81 static u16 pin_req[] = P_MII0;
84 static void bfin_mac_disable(void);
85 static void bfin_mac_enable(void);
87 static void desc_list_free(void)
89 struct net_dma_desc_rx *r;
90 struct net_dma_desc_tx *t;
92 #if !defined(CONFIG_BFIN_MAC_USE_L1)
93 dma_addr_t dma_handle = 0;
98 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
101 dev_kfree_skb(t->skb);
107 bfin_mac_free(dma_handle, tx_desc);
112 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
115 dev_kfree_skb(r->skb);
121 bfin_mac_free(dma_handle, rx_desc);
125 static int desc_list_init(void)
128 struct sk_buff *new_skb;
129 #if !defined(CONFIG_BFIN_MAC_USE_L1)
131 * This dma_handle is useless in Blackfin dma_alloc_coherent().
132 * The real dma handler is the return value of dma_alloc_coherent().
134 dma_addr_t dma_handle;
137 tx_desc = bfin_mac_alloc(&dma_handle,
138 sizeof(struct net_dma_desc_tx) *
139 CONFIG_BFIN_TX_DESC_NUM);
143 rx_desc = bfin_mac_alloc(&dma_handle,
144 sizeof(struct net_dma_desc_rx) *
145 CONFIG_BFIN_RX_DESC_NUM);
150 tx_list_head = tx_list_tail = tx_desc;
152 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
153 struct net_dma_desc_tx *t = tx_desc + i;
154 struct dma_descriptor *a = &(t->desc_a);
155 struct dma_descriptor *b = &(t->desc_b);
159 * read from memory WNR = 0
160 * wordsize is 32 bits
161 * 6 half words is desc size
164 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
165 a->start_addr = (unsigned long)t->packet;
167 a->next_dma_desc = b;
171 * write to memory WNR = 1
172 * wordsize is 32 bits
174 * 6 half words is desc size
177 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
178 b->start_addr = (unsigned long)(&(t->status));
182 tx_list_tail->desc_b.next_dma_desc = a;
183 tx_list_tail->next = t;
186 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
187 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
188 current_tx_ptr = tx_list_head;
191 rx_list_head = rx_list_tail = rx_desc;
193 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
194 struct net_dma_desc_rx *r = rx_desc + i;
195 struct dma_descriptor *a = &(r->desc_a);
196 struct dma_descriptor *b = &(r->desc_b);
198 /* allocate a new skb for next time receive */
199 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
201 printk(KERN_NOTICE DRV_NAME
202 ": init: low on mem - packet dropped\n");
205 skb_reserve(new_skb, NET_IP_ALIGN);
210 * write to memory WNR = 1
211 * wordsize is 32 bits
213 * 6 half words is desc size
216 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
217 /* since RXDWA is enabled */
218 a->start_addr = (unsigned long)new_skb->data - 2;
220 a->next_dma_desc = b;
224 * write to memory WNR = 1
225 * wordsize is 32 bits
227 * 6 half words is desc size
230 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
231 NDSIZE_6 | DMAFLOW_LARGE;
232 b->start_addr = (unsigned long)(&(r->status));
235 rx_list_tail->desc_b.next_dma_desc = a;
236 rx_list_tail->next = r;
239 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
240 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
241 current_rx_ptr = rx_list_head;
247 printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
252 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
257 /* Wait until the previous MDC/MDIO transaction has completed */
258 static void bfin_mdio_poll(void)
260 int timeout_cnt = MAX_TIMEOUT_CNT;
262 /* poll the STABUSY bit */
263 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
265 if (timeout_cnt-- < 0) {
266 printk(KERN_ERR DRV_NAME
267 ": wait MDC/MDIO transaction to complete timeout\n");
273 /* Read an off-chip register in a PHY through the MDC/MDIO port */
274 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
279 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
280 SET_REGAD((u16) regnum) |
285 return (int) bfin_read_EMAC_STADAT();
288 /* Write an off-chip register in a PHY through the MDC/MDIO port */
289 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
294 bfin_write_EMAC_STADAT((u32) value);
297 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
298 SET_REGAD((u16) regnum) |
307 static int bfin_mdiobus_reset(struct mii_bus *bus)
312 static void bfin_mac_adjust_link(struct net_device *dev)
314 struct bfin_mac_local *lp = netdev_priv(dev);
315 struct phy_device *phydev = lp->phydev;
319 spin_lock_irqsave(&lp->lock, flags);
321 /* Now we make sure that we can be in full duplex mode.
322 * If not, we operate in half-duplex mode. */
323 if (phydev->duplex != lp->old_duplex) {
324 u32 opmode = bfin_read_EMAC_OPMODE();
332 bfin_write_EMAC_OPMODE(opmode);
333 lp->old_duplex = phydev->duplex;
336 if (phydev->speed != lp->old_speed) {
337 #if defined(CONFIG_BFIN_MAC_RMII)
338 u32 opmode = bfin_read_EMAC_OPMODE();
339 switch (phydev->speed) {
344 opmode &= ~(RMII_10);
348 "%s: Ack! Speed (%d) is not 10/100!\n",
349 DRV_NAME, phydev->speed);
352 bfin_write_EMAC_OPMODE(opmode);
356 lp->old_speed = phydev->speed;
363 } else if (lp->old_link) {
371 u32 opmode = bfin_read_EMAC_OPMODE();
372 phy_print_status(phydev);
373 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
376 spin_unlock_irqrestore(&lp->lock, flags);
380 #define MDC_CLK 2500000
382 static int mii_probe(struct net_device *dev)
384 struct bfin_mac_local *lp = netdev_priv(dev);
385 struct phy_device *phydev = NULL;
386 unsigned short sysctl;
390 /* Enable PHY output early */
391 if (!(bfin_read_VR_CTL() & CLKBUFOE))
392 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
395 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
397 sysctl = bfin_read_EMAC_SYSCTL();
398 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
399 bfin_write_EMAC_SYSCTL(sysctl);
401 /* search for connect PHY device */
402 for (i = 0; i < PHY_MAX_ADDR; i++) {
403 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
406 continue; /* no PHY here... */
409 break; /* found it */
412 /* now we are supposed to have a proper phydev, to attach to... */
414 printk(KERN_INFO "%s: Don't found any phy device at all\n",
419 #if defined(CONFIG_BFIN_MAC_RMII)
420 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
421 0, PHY_INTERFACE_MODE_RMII);
423 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
424 0, PHY_INTERFACE_MODE_MII);
427 if (IS_ERR(phydev)) {
428 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
429 return PTR_ERR(phydev);
432 /* mask with MAC supported features */
433 phydev->supported &= (SUPPORTED_10baseT_Half
434 | SUPPORTED_10baseT_Full
435 | SUPPORTED_100baseT_Half
436 | SUPPORTED_100baseT_Full
438 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
442 phydev->advertising = phydev->supported;
449 printk(KERN_INFO "%s: attached PHY driver [%s] "
450 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
452 DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
453 MDC_CLK, mdc_div, sclk/1000000);
463 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
465 struct bfin_mac_local *lp = netdev_priv(dev);
468 return phy_ethtool_gset(lp->phydev, cmd);
474 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
476 struct bfin_mac_local *lp = netdev_priv(dev);
478 if (!capable(CAP_NET_ADMIN))
482 return phy_ethtool_sset(lp->phydev, cmd);
487 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
488 struct ethtool_drvinfo *info)
490 strcpy(info->driver, DRV_NAME);
491 strcpy(info->version, DRV_VERSION);
492 strcpy(info->fw_version, "N/A");
493 strcpy(info->bus_info, dev_name(&dev->dev));
496 static const struct ethtool_ops bfin_mac_ethtool_ops = {
497 .get_settings = bfin_mac_ethtool_getsettings,
498 .set_settings = bfin_mac_ethtool_setsettings,
499 .get_link = ethtool_op_get_link,
500 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
503 /**************************************************************************/
504 void setup_system_regs(struct net_device *dev)
506 unsigned short sysctl;
509 * Odd word alignment for Receive Frame DMA word
510 * Configure checksum support and rcve frame word alignment
512 sysctl = bfin_read_EMAC_SYSCTL();
513 #if defined(BFIN_MAC_CSUM_OFFLOAD)
514 sysctl |= RXDWA | RXCKS;
518 bfin_write_EMAC_SYSCTL(sysctl);
520 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
522 /* Initialize the TX DMA channel registers */
523 bfin_write_DMA2_X_COUNT(0);
524 bfin_write_DMA2_X_MODIFY(4);
525 bfin_write_DMA2_Y_COUNT(0);
526 bfin_write_DMA2_Y_MODIFY(0);
528 /* Initialize the RX DMA channel registers */
529 bfin_write_DMA1_X_COUNT(0);
530 bfin_write_DMA1_X_MODIFY(4);
531 bfin_write_DMA1_Y_COUNT(0);
532 bfin_write_DMA1_Y_MODIFY(0);
535 static void setup_mac_addr(u8 *mac_addr)
537 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
538 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
540 /* this depends on a little-endian machine */
541 bfin_write_EMAC_ADDRLO(addr_low);
542 bfin_write_EMAC_ADDRHI(addr_hi);
545 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
547 struct sockaddr *addr = p;
548 if (netif_running(dev))
550 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
551 setup_mac_addr(dev->dev_addr);
555 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
556 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
558 static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
559 struct ifreq *ifr, int cmd)
561 struct hwtstamp_config config;
562 struct bfin_mac_local *lp = netdev_priv(netdev);
564 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
566 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
569 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
570 __func__, config.flags, config.tx_type, config.rx_filter);
572 /* reserved for future extensions */
576 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
577 (config.tx_type != HWTSTAMP_TX_ON))
580 ptpctl = bfin_read_EMAC_PTP_CTL();
582 switch (config.rx_filter) {
583 case HWTSTAMP_FILTER_NONE:
585 * Dont allow any timestamping
588 bfin_write_EMAC_PTP_FV3(ptpfv3);
590 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
591 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
592 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
594 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
595 * to enable all the field matches.
598 bfin_write_EMAC_PTP_CTL(ptpctl);
600 * Keep the default values of the EMAC_PTP_FOFF register.
602 ptpfoff = 0x4A24170C;
603 bfin_write_EMAC_PTP_FOFF(ptpfoff);
605 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
609 bfin_write_EMAC_PTP_FV1(ptpfv1);
611 bfin_write_EMAC_PTP_FV2(ptpfv2);
613 * The default value (0xFFFC) allows the timestamping of both
614 * received Sync messages and Delay_Req messages.
617 bfin_write_EMAC_PTP_FV3(ptpfv3);
619 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
621 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
622 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
623 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
624 /* Clear all five comparison mask bits (bits[12:8]) in the
625 * EMAC_PTP_CTL register to enable all the field matches.
628 bfin_write_EMAC_PTP_CTL(ptpctl);
630 * Keep the default values of the EMAC_PTP_FOFF register, except set
631 * the PTPCOF field to 0x2A.
633 ptpfoff = 0x2A24170C;
634 bfin_write_EMAC_PTP_FOFF(ptpfoff);
636 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
640 bfin_write_EMAC_PTP_FV1(ptpfv1);
642 bfin_write_EMAC_PTP_FV2(ptpfv2);
644 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
645 * the value to 0xFFF0.
648 bfin_write_EMAC_PTP_FV3(ptpfv3);
650 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
652 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
653 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
654 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
656 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
657 * EFTM and PTPCM field comparison.
660 bfin_write_EMAC_PTP_CTL(ptpctl);
662 * Keep the default values of all the fields of the EMAC_PTP_FOFF
663 * register, except set the PTPCOF field to 0x0E.
665 ptpfoff = 0x0E24170C;
666 bfin_write_EMAC_PTP_FOFF(ptpfoff);
668 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
669 * corresponds to PTP messages on the MAC layer.
672 bfin_write_EMAC_PTP_FV1(ptpfv1);
674 bfin_write_EMAC_PTP_FV2(ptpfv2);
676 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
677 * messages, set the value to 0xFFF0.
680 bfin_write_EMAC_PTP_FV3(ptpfv3);
682 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
688 if (config.tx_type == HWTSTAMP_TX_OFF &&
689 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
691 bfin_write_EMAC_PTP_CTL(ptpctl);
696 bfin_write_EMAC_PTP_CTL(ptpctl);
699 * clear any existing timestamp
701 bfin_read_EMAC_PTP_RXSNAPLO();
702 bfin_read_EMAC_PTP_RXSNAPHI();
704 bfin_read_EMAC_PTP_TXSNAPLO();
705 bfin_read_EMAC_PTP_TXSNAPHI();
708 * Set registers so that rollover occurs soon to test this.
710 bfin_write_EMAC_PTP_TIMELO(0x00000000);
711 bfin_write_EMAC_PTP_TIMEHI(0xFF800000);
715 lp->compare.last_update = 0;
716 timecounter_init(&lp->clock,
718 ktime_to_ns(ktime_get_real()));
719 timecompare_update(&lp->compare, 0);
722 lp->stamp_cfg = config;
723 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
727 static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp)
729 ktime_t sys = ktime_get_real();
731 pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n",
732 __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec,
733 sys.tv.nsec, cmp->offset, cmp->skew);
736 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
738 struct bfin_mac_local *lp = netdev_priv(netdev);
739 union skb_shared_tx *shtx = skb_tx(skb);
741 if (shtx->hardware) {
742 int timeout_cnt = MAX_TIMEOUT_CNT;
744 /* When doing time stamping, keep the connection to the socket
747 shtx->in_progress = 1;
750 * The timestamping is done at the EMAC module's MII/RMII interface
751 * when the module sees the Start of Frame of an event message packet. This
752 * interface is the closest possible place to the physical Ethernet transmission
753 * medium, providing the best timing accuracy.
755 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
757 if (timeout_cnt == 0)
758 printk(KERN_ERR DRV_NAME
759 ": fails to timestamp the TX packet\n");
761 struct skb_shared_hwtstamps shhwtstamps;
765 regval = bfin_read_EMAC_PTP_TXSNAPLO();
766 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
767 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
768 ns = timecounter_cyc2time(&lp->clock,
770 timecompare_update(&lp->compare, ns);
771 shhwtstamps.hwtstamp = ns_to_ktime(ns);
772 shhwtstamps.syststamp =
773 timecompare_transform(&lp->compare, ns);
774 skb_tstamp_tx(skb, &shhwtstamps);
776 bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare);
781 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
783 struct bfin_mac_local *lp = netdev_priv(netdev);
786 struct skb_shared_hwtstamps *shhwtstamps;
788 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
791 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
795 shhwtstamps = skb_hwtstamps(skb);
797 regval = bfin_read_EMAC_PTP_RXSNAPLO();
798 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
799 ns = timecounter_cyc2time(&lp->clock, regval);
800 timecompare_update(&lp->compare, ns);
801 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
802 shhwtstamps->hwtstamp = ns_to_ktime(ns);
803 shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns);
805 bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare);
809 * bfin_read_clock - read raw cycle counter (to be used by time counter)
811 static cycle_t bfin_read_clock(const struct cyclecounter *tc)
815 stamp = bfin_read_EMAC_PTP_TIMELO();
816 stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL;
821 #define PTP_CLK 25000000
823 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
825 struct bfin_mac_local *lp = netdev_priv(netdev);
828 /* Initialize hardware timer */
829 append = PTP_CLK * (1ULL << 32);
830 do_div(append, get_sclk());
831 bfin_write_EMAC_PTP_ADDEND((u32)append);
833 memset(&lp->cycles, 0, sizeof(lp->cycles));
834 lp->cycles.read = bfin_read_clock;
835 lp->cycles.mask = CLOCKSOURCE_MASK(64);
836 lp->cycles.mult = 1000000000 / PTP_CLK;
837 lp->cycles.shift = 0;
839 /* Synchronize our NIC clock against system wall clock */
840 memset(&lp->compare, 0, sizeof(lp->compare));
841 lp->compare.source = &lp->clock;
842 lp->compare.target = ktime_get_real;
843 lp->compare.num_samples = 10;
845 /* Initialize hwstamp config */
846 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
847 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
851 # define bfin_mac_hwtstamp_is_none(cfg) 0
852 # define bfin_mac_hwtstamp_init(dev)
853 # define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
854 # define bfin_rx_hwtstamp(dev, skb)
855 # define bfin_tx_hwtstamp(dev, skb)
858 static void adjust_tx_list(void)
860 int timeout_cnt = MAX_TIMEOUT_CNT;
862 if (tx_list_head->status.status_word != 0 &&
863 current_tx_ptr != tx_list_head) {
864 goto adjust_head; /* released something, just return; */
868 * if nothing released, check wait condition
869 * current's next can not be the head,
870 * otherwise the dma will not stop as we want
872 if (current_tx_ptr->next->next == tx_list_head) {
873 while (tx_list_head->status.status_word == 0) {
875 if (tx_list_head->status.status_word != 0 ||
876 !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) {
879 if (timeout_cnt-- < 0) {
880 printk(KERN_ERR DRV_NAME
881 ": wait for adjust tx list head timeout\n");
885 if (tx_list_head->status.status_word != 0) {
894 tx_list_head->desc_a.config &= ~DMAEN;
895 tx_list_head->status.status_word = 0;
896 if (tx_list_head->skb) {
897 dev_kfree_skb(tx_list_head->skb);
898 tx_list_head->skb = NULL;
900 printk(KERN_ERR DRV_NAME
901 ": no sk_buff in a transmitted frame!\n");
903 tx_list_head = tx_list_head->next;
904 } while (tx_list_head->status.status_word != 0 &&
905 current_tx_ptr != tx_list_head);
910 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
911 struct net_device *dev)
914 u32 data_align = (unsigned long)(skb->data) & 0x3;
915 union skb_shared_tx *shtx = skb_tx(skb);
917 current_tx_ptr->skb = skb;
919 if (data_align == 0x2) {
920 /* move skb->data to current_tx_ptr payload */
921 data = (u16 *)(skb->data) - 1;
922 *data = (u16)(skb->len);
924 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
925 * a DMA_Length_Word field associated with the packet. The lower 12 bits
926 * of this field are the length of the packet payload in bytes and the higher
927 * 4 bits are the timestamping enable field.
932 current_tx_ptr->desc_a.start_addr = (u32)data;
933 /* this is important! */
934 blackfin_dcache_flush_range((u32)data,
935 (u32)((u8 *)data + skb->len + 4));
937 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
938 /* enable timestamping for the sent packet */
940 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
941 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
943 current_tx_ptr->desc_a.start_addr =
944 (u32)current_tx_ptr->packet;
945 if (current_tx_ptr->status.status_word != 0)
946 current_tx_ptr->status.status_word = 0;
947 blackfin_dcache_flush_range(
948 (u32)current_tx_ptr->packet,
949 (u32)(current_tx_ptr->packet + skb->len + 2));
952 /* make sure the internal data buffers in the core are drained
953 * so that the DMA descriptors are completely written when the
954 * DMA engine goes to fetch them below
958 /* enable this packet's dma */
959 current_tx_ptr->desc_a.config |= DMAEN;
961 /* tx dma is running, just return */
962 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
965 /* tx dma is not running */
966 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
967 /* dma enabled, read from memory, size is 6 */
968 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
969 /* Turn on the EMAC tx */
970 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
975 bfin_tx_hwtstamp(dev, skb);
977 current_tx_ptr = current_tx_ptr->next;
978 dev->stats.tx_packets++;
979 dev->stats.tx_bytes += (skb->len);
983 static void bfin_mac_rx(struct net_device *dev)
985 struct sk_buff *skb, *new_skb;
987 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
989 /* allocate a new skb for next time receive */
990 skb = current_rx_ptr->skb;
992 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
994 printk(KERN_NOTICE DRV_NAME
995 ": rx: low on mem - packet dropped\n");
996 dev->stats.rx_dropped++;
999 /* reserve 2 bytes for RXDWA padding */
1000 skb_reserve(new_skb, NET_IP_ALIGN);
1001 current_rx_ptr->skb = new_skb;
1002 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1004 /* Invidate the data cache of skb->data range when it is write back
1005 * cache. It will prevent overwritting the new data from DMA
1007 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1008 (unsigned long)new_skb->end);
1010 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
1012 blackfin_dcache_invalidate_range((unsigned long)skb->head,
1013 (unsigned long)skb->tail);
1015 skb->protocol = eth_type_trans(skb, dev);
1017 bfin_rx_hwtstamp(dev, skb);
1019 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1020 skb->csum = current_rx_ptr->status.ip_payload_csum;
1021 skb->ip_summed = CHECKSUM_COMPLETE;
1025 dev->stats.rx_packets++;
1026 dev->stats.rx_bytes += len;
1027 current_rx_ptr->status.status_word = 0x00000000;
1028 current_rx_ptr = current_rx_ptr->next;
1034 /* interrupt routine to handle rx and error signal */
1035 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1037 struct net_device *dev = dev_id;
1041 if (current_rx_ptr->status.status_word == 0) {
1042 /* no more new packet received */
1044 if (current_rx_ptr->next->status.status_word != 0) {
1045 current_rx_ptr = current_rx_ptr->next;
1049 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1050 DMA_DONE | DMA_ERR);
1057 goto get_one_packet;
1060 #ifdef CONFIG_NET_POLL_CONTROLLER
1061 static void bfin_mac_poll(struct net_device *dev)
1063 disable_irq(IRQ_MAC_RX);
1064 bfin_mac_interrupt(IRQ_MAC_RX, dev);
1065 enable_irq(IRQ_MAC_RX);
1067 #endif /* CONFIG_NET_POLL_CONTROLLER */
1069 static void bfin_mac_disable(void)
1071 unsigned int opmode;
1073 opmode = bfin_read_EMAC_OPMODE();
1076 /* Turn off the EMAC */
1077 bfin_write_EMAC_OPMODE(opmode);
1081 * Enable Interrupts, Receive, and Transmit
1083 static void bfin_mac_enable(void)
1087 pr_debug("%s: %s\n", DRV_NAME, __func__);
1090 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1091 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1096 /* We enable only RX here */
1097 /* ASTP : Enable Automatic Pad Stripping
1098 PR : Promiscuous Mode for test
1099 PSF : Receive frames with total length less than 64 bytes.
1100 FDMODE : Full Duplex Mode
1101 LB : Internal Loopback for test
1102 RE : Receiver Enable */
1103 opmode = bfin_read_EMAC_OPMODE();
1104 if (opmode & FDMODE)
1107 opmode |= DRO | DC | PSF;
1110 #if defined(CONFIG_BFIN_MAC_RMII)
1111 opmode |= RMII; /* For Now only 100MBit are supported */
1112 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2
1116 /* Turn on the EMAC rx */
1117 bfin_write_EMAC_OPMODE(opmode);
1120 /* Our watchdog timed out. Called by the networking layer */
1121 static void bfin_mac_timeout(struct net_device *dev)
1123 pr_debug("%s: %s\n", dev->name, __func__);
1127 /* reset tx queue */
1128 tx_list_tail = tx_list_head->next;
1132 /* We can accept TX packets again */
1133 dev->trans_start = jiffies; /* prevent tx timeout */
1134 netif_wake_queue(dev);
1137 static void bfin_mac_multicast_hash(struct net_device *dev)
1139 u32 emac_hashhi, emac_hashlo;
1140 struct netdev_hw_addr *ha;
1144 emac_hashhi = emac_hashlo = 0;
1146 netdev_for_each_mc_addr(ha, dev) {
1149 /* skip non-multicast addresses */
1153 crc = ether_crc(ETH_ALEN, addrs);
1157 emac_hashhi |= 1 << (crc & 0x1f);
1159 emac_hashlo |= 1 << (crc & 0x1f);
1162 bfin_write_EMAC_HASHHI(emac_hashhi);
1163 bfin_write_EMAC_HASHLO(emac_hashlo);
1167 * This routine will, depending on the values passed to it,
1168 * either make it accept multicast packets, go into
1169 * promiscuous mode (for TCPDUMP and cousins) or accept
1170 * a select set of multicast packets
1172 static void bfin_mac_set_multicast_list(struct net_device *dev)
1176 if (dev->flags & IFF_PROMISC) {
1177 printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
1178 sysctl = bfin_read_EMAC_OPMODE();
1180 bfin_write_EMAC_OPMODE(sysctl);
1181 } else if (dev->flags & IFF_ALLMULTI) {
1182 /* accept all multicast */
1183 sysctl = bfin_read_EMAC_OPMODE();
1185 bfin_write_EMAC_OPMODE(sysctl);
1186 } else if (!netdev_mc_empty(dev)) {
1187 /* set up multicast hash table */
1188 sysctl = bfin_read_EMAC_OPMODE();
1190 bfin_write_EMAC_OPMODE(sysctl);
1191 bfin_mac_multicast_hash(dev);
1193 /* clear promisc or multicast mode */
1194 sysctl = bfin_read_EMAC_OPMODE();
1195 sysctl &= ~(RAF | PAM);
1196 bfin_write_EMAC_OPMODE(sysctl);
1200 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1204 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1211 * this puts the device in an inactive state
1213 static void bfin_mac_shutdown(struct net_device *dev)
1215 /* Turn off the EMAC */
1216 bfin_write_EMAC_OPMODE(0x00000000);
1217 /* Turn off the EMAC RX DMA */
1218 bfin_write_DMA1_CONFIG(0x0000);
1219 bfin_write_DMA2_CONFIG(0x0000);
1223 * Open and Initialize the interface
1225 * Set up everything, reset the card, etc..
1227 static int bfin_mac_open(struct net_device *dev)
1229 struct bfin_mac_local *lp = netdev_priv(dev);
1231 pr_debug("%s: %s\n", dev->name, __func__);
1234 * Check that the address is valid. If its not, refuse
1235 * to bring the device up. The user must specify an
1236 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1238 if (!is_valid_ether_addr(dev->dev_addr)) {
1239 printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
1243 /* initial rx and tx list */
1244 retval = desc_list_init();
1249 phy_start(lp->phydev);
1250 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
1251 setup_system_regs(dev);
1252 setup_mac_addr(dev->dev_addr);
1255 pr_debug("hardware init finished\n");
1256 netif_start_queue(dev);
1257 netif_carrier_on(dev);
1263 * this makes the board clean up everything that it can
1264 * and not talk to the outside world. Caused by
1265 * an 'ifconfig ethX down'
1267 static int bfin_mac_close(struct net_device *dev)
1269 struct bfin_mac_local *lp = netdev_priv(dev);
1270 pr_debug("%s: %s\n", dev->name, __func__);
1272 netif_stop_queue(dev);
1273 netif_carrier_off(dev);
1275 phy_stop(lp->phydev);
1276 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1278 /* clear everything */
1279 bfin_mac_shutdown(dev);
1281 /* free the rx/tx buffers */
1287 static const struct net_device_ops bfin_mac_netdev_ops = {
1288 .ndo_open = bfin_mac_open,
1289 .ndo_stop = bfin_mac_close,
1290 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1291 .ndo_set_mac_address = bfin_mac_set_mac_address,
1292 .ndo_tx_timeout = bfin_mac_timeout,
1293 .ndo_set_multicast_list = bfin_mac_set_multicast_list,
1294 .ndo_do_ioctl = bfin_mac_ioctl,
1295 .ndo_validate_addr = eth_validate_addr,
1296 .ndo_change_mtu = eth_change_mtu,
1297 #ifdef CONFIG_NET_POLL_CONTROLLER
1298 .ndo_poll_controller = bfin_mac_poll,
1302 static int __devinit bfin_mac_probe(struct platform_device *pdev)
1304 struct net_device *ndev;
1305 struct bfin_mac_local *lp;
1306 struct platform_device *pd;
1309 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1311 dev_err(&pdev->dev, "Cannot allocate net device!\n");
1315 SET_NETDEV_DEV(ndev, &pdev->dev);
1316 platform_set_drvdata(pdev, ndev);
1317 lp = netdev_priv(ndev);
1319 /* Grab the MAC address in the MAC */
1320 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1321 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1324 /*todo: how to proble? which is revision_register */
1325 bfin_write_EMAC_ADDRLO(0x12345678);
1326 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1327 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1329 goto out_err_probe_mac;
1334 * Is it valid? (Did bootloader initialize it?)
1335 * Grab the MAC from the board somehow
1336 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1338 if (!is_valid_ether_addr(ndev->dev_addr))
1339 bfin_get_ether_addr(ndev->dev_addr);
1341 /* If still not valid, get a random one */
1342 if (!is_valid_ether_addr(ndev->dev_addr))
1343 random_ether_addr(ndev->dev_addr);
1345 setup_mac_addr(ndev->dev_addr);
1347 if (!pdev->dev.platform_data) {
1348 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1350 goto out_err_probe_mac;
1352 pd = pdev->dev.platform_data;
1353 lp->mii_bus = platform_get_drvdata(pd);
1354 lp->mii_bus->priv = ndev;
1356 rc = mii_probe(ndev);
1358 dev_err(&pdev->dev, "MII Probe failed!\n");
1359 goto out_err_mii_probe;
1362 /* Fill in the fields of the device structure with ethernet values. */
1365 ndev->netdev_ops = &bfin_mac_netdev_ops;
1366 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1368 spin_lock_init(&lp->lock);
1370 /* now, enable interrupts */
1371 /* register irq handler */
1372 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1373 IRQF_DISABLED, "EMAC_RX", ndev);
1375 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1377 goto out_err_request_irq;
1380 rc = register_netdev(ndev);
1382 dev_err(&pdev->dev, "Cannot register net device!\n");
1383 goto out_err_reg_ndev;
1386 bfin_mac_hwtstamp_init(ndev);
1388 /* now, print out the card info, in a short format.. */
1389 dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1394 free_irq(IRQ_MAC_RX, ndev);
1395 out_err_request_irq:
1397 mdiobus_unregister(lp->mii_bus);
1398 mdiobus_free(lp->mii_bus);
1399 peripheral_free_list(pin_req);
1401 platform_set_drvdata(pdev, NULL);
1407 static int __devexit bfin_mac_remove(struct platform_device *pdev)
1409 struct net_device *ndev = platform_get_drvdata(pdev);
1410 struct bfin_mac_local *lp = netdev_priv(ndev);
1412 platform_set_drvdata(pdev, NULL);
1414 lp->mii_bus->priv = NULL;
1416 unregister_netdev(ndev);
1418 free_irq(IRQ_MAC_RX, ndev);
1422 peripheral_free_list(pin_req);
1428 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1430 struct net_device *net_dev = platform_get_drvdata(pdev);
1432 if (netif_running(net_dev))
1433 bfin_mac_close(net_dev);
1438 static int bfin_mac_resume(struct platform_device *pdev)
1440 struct net_device *net_dev = platform_get_drvdata(pdev);
1442 if (netif_running(net_dev))
1443 bfin_mac_open(net_dev);
1448 #define bfin_mac_suspend NULL
1449 #define bfin_mac_resume NULL
1450 #endif /* CONFIG_PM */
1452 static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1454 struct mii_bus *miibus;
1458 * We are setting up a network card,
1459 * so set the GPIO pins to Ethernet mode
1461 rc = peripheral_request_list(pin_req, DRV_NAME);
1463 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1468 miibus = mdiobus_alloc();
1471 miibus->read = bfin_mdiobus_read;
1472 miibus->write = bfin_mdiobus_write;
1473 miibus->reset = bfin_mdiobus_reset;
1475 miibus->parent = &pdev->dev;
1476 miibus->name = "bfin_mii_bus";
1477 snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
1478 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1479 if (miibus->irq == NULL)
1481 for (i = 0; i < PHY_MAX_ADDR; ++i)
1482 miibus->irq[i] = PHY_POLL;
1484 rc = mdiobus_register(miibus);
1486 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1487 goto out_err_mdiobus_register;
1490 platform_set_drvdata(pdev, miibus);
1493 out_err_mdiobus_register:
1494 mdiobus_free(miibus);
1496 peripheral_free_list(pin_req);
1501 static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1503 struct mii_bus *miibus = platform_get_drvdata(pdev);
1504 platform_set_drvdata(pdev, NULL);
1505 mdiobus_unregister(miibus);
1506 mdiobus_free(miibus);
1507 peripheral_free_list(pin_req);
1511 static struct platform_driver bfin_mii_bus_driver = {
1512 .probe = bfin_mii_bus_probe,
1513 .remove = __devexit_p(bfin_mii_bus_remove),
1515 .name = "bfin_mii_bus",
1516 .owner = THIS_MODULE,
1520 static struct platform_driver bfin_mac_driver = {
1521 .probe = bfin_mac_probe,
1522 .remove = __devexit_p(bfin_mac_remove),
1523 .resume = bfin_mac_resume,
1524 .suspend = bfin_mac_suspend,
1527 .owner = THIS_MODULE,
1531 static int __init bfin_mac_init(void)
1534 ret = platform_driver_register(&bfin_mii_bus_driver);
1536 return platform_driver_register(&bfin_mac_driver);
1540 module_init(bfin_mac_init);
1542 static void __exit bfin_mac_cleanup(void)
1544 platform_driver_unregister(&bfin_mac_driver);
1545 platform_driver_unregister(&bfin_mii_bus_driver);
1548 module_exit(bfin_mac_cleanup);