2 * Blackfin On-Chip MAC Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/irq.h>
21 #include <linux/ioport.h>
22 #include <linux/crc32.h>
23 #include <linux/device.h>
24 #include <linux/spinlock.h>
25 #include <linux/mii.h>
26 #include <linux/phy.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/skbuff.h>
31 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
36 #include <asm/div64.h>
38 #include <asm/blackfin.h>
39 #include <asm/cacheflush.h>
40 #include <asm/portmux.h>
44 #define DRV_NAME "bfin_mac"
45 #define DRV_VERSION "1.1"
46 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
47 #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
49 MODULE_AUTHOR(DRV_AUTHOR);
50 MODULE_LICENSE("GPL");
51 MODULE_DESCRIPTION(DRV_DESC);
52 MODULE_ALIAS("platform:bfin_mac");
54 #if defined(CONFIG_BFIN_MAC_USE_L1)
55 # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size)
56 # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr)
58 # define bfin_mac_alloc(dma_handle, size) \
59 dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL)
60 # define bfin_mac_free(dma_handle, ptr) \
61 dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle)
64 #define PKT_BUF_SZ 1580
66 #define MAX_TIMEOUT_CNT 500
68 /* pointers to maintain transmit list */
69 static struct net_dma_desc_tx *tx_list_head;
70 static struct net_dma_desc_tx *tx_list_tail;
71 static struct net_dma_desc_rx *rx_list_head;
72 static struct net_dma_desc_rx *rx_list_tail;
73 static struct net_dma_desc_rx *current_rx_ptr;
74 static struct net_dma_desc_tx *current_tx_ptr;
75 static struct net_dma_desc_tx *tx_desc;
76 static struct net_dma_desc_rx *rx_desc;
78 #if defined(CONFIG_BFIN_MAC_RMII)
79 static u16 pin_req[] = P_RMII0;
81 static u16 pin_req[] = P_MII0;
84 static void bfin_mac_disable(void);
85 static void bfin_mac_enable(void);
87 static void desc_list_free(void)
89 struct net_dma_desc_rx *r;
90 struct net_dma_desc_tx *t;
92 #if !defined(CONFIG_BFIN_MAC_USE_L1)
93 dma_addr_t dma_handle = 0;
98 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
101 dev_kfree_skb(t->skb);
107 bfin_mac_free(dma_handle, tx_desc);
112 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
115 dev_kfree_skb(r->skb);
121 bfin_mac_free(dma_handle, rx_desc);
125 static int desc_list_init(void)
128 struct sk_buff *new_skb;
129 #if !defined(CONFIG_BFIN_MAC_USE_L1)
131 * This dma_handle is useless in Blackfin dma_alloc_coherent().
132 * The real dma handler is the return value of dma_alloc_coherent().
134 dma_addr_t dma_handle;
137 tx_desc = bfin_mac_alloc(&dma_handle,
138 sizeof(struct net_dma_desc_tx) *
139 CONFIG_BFIN_TX_DESC_NUM);
143 rx_desc = bfin_mac_alloc(&dma_handle,
144 sizeof(struct net_dma_desc_rx) *
145 CONFIG_BFIN_RX_DESC_NUM);
150 tx_list_head = tx_list_tail = tx_desc;
152 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
153 struct net_dma_desc_tx *t = tx_desc + i;
154 struct dma_descriptor *a = &(t->desc_a);
155 struct dma_descriptor *b = &(t->desc_b);
159 * read from memory WNR = 0
160 * wordsize is 32 bits
161 * 6 half words is desc size
164 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
165 a->start_addr = (unsigned long)t->packet;
167 a->next_dma_desc = b;
171 * write to memory WNR = 1
172 * wordsize is 32 bits
174 * 6 half words is desc size
177 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
178 b->start_addr = (unsigned long)(&(t->status));
182 tx_list_tail->desc_b.next_dma_desc = a;
183 tx_list_tail->next = t;
186 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
187 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
188 current_tx_ptr = tx_list_head;
191 rx_list_head = rx_list_tail = rx_desc;
193 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
194 struct net_dma_desc_rx *r = rx_desc + i;
195 struct dma_descriptor *a = &(r->desc_a);
196 struct dma_descriptor *b = &(r->desc_b);
198 /* allocate a new skb for next time receive */
199 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
201 printk(KERN_NOTICE DRV_NAME
202 ": init: low on mem - packet dropped\n");
205 skb_reserve(new_skb, NET_IP_ALIGN);
206 /* Invidate the data cache of skb->data range when it is write back
207 * cache. It will prevent overwritting the new data from DMA
209 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
210 (unsigned long)new_skb->end);
215 * write to memory WNR = 1
216 * wordsize is 32 bits
218 * 6 half words is desc size
221 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
222 /* since RXDWA is enabled */
223 a->start_addr = (unsigned long)new_skb->data - 2;
225 a->next_dma_desc = b;
229 * write to memory WNR = 1
230 * wordsize is 32 bits
232 * 6 half words is desc size
235 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
236 NDSIZE_6 | DMAFLOW_LARGE;
237 b->start_addr = (unsigned long)(&(r->status));
240 rx_list_tail->desc_b.next_dma_desc = a;
241 rx_list_tail->next = r;
244 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
245 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
246 current_rx_ptr = rx_list_head;
252 printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
257 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
262 /* Wait until the previous MDC/MDIO transaction has completed */
263 static void bfin_mdio_poll(void)
265 int timeout_cnt = MAX_TIMEOUT_CNT;
267 /* poll the STABUSY bit */
268 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
270 if (timeout_cnt-- < 0) {
271 printk(KERN_ERR DRV_NAME
272 ": wait MDC/MDIO transaction to complete timeout\n");
278 /* Read an off-chip register in a PHY through the MDC/MDIO port */
279 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
284 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
285 SET_REGAD((u16) regnum) |
290 return (int) bfin_read_EMAC_STADAT();
293 /* Write an off-chip register in a PHY through the MDC/MDIO port */
294 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
299 bfin_write_EMAC_STADAT((u32) value);
302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
312 static int bfin_mdiobus_reset(struct mii_bus *bus)
317 static void bfin_mac_adjust_link(struct net_device *dev)
319 struct bfin_mac_local *lp = netdev_priv(dev);
320 struct phy_device *phydev = lp->phydev;
324 spin_lock_irqsave(&lp->lock, flags);
326 /* Now we make sure that we can be in full duplex mode.
327 * If not, we operate in half-duplex mode. */
328 if (phydev->duplex != lp->old_duplex) {
329 u32 opmode = bfin_read_EMAC_OPMODE();
337 bfin_write_EMAC_OPMODE(opmode);
338 lp->old_duplex = phydev->duplex;
341 if (phydev->speed != lp->old_speed) {
342 #if defined(CONFIG_BFIN_MAC_RMII)
343 u32 opmode = bfin_read_EMAC_OPMODE();
344 switch (phydev->speed) {
349 opmode &= ~(RMII_10);
353 "%s: Ack! Speed (%d) is not 10/100!\n",
354 DRV_NAME, phydev->speed);
357 bfin_write_EMAC_OPMODE(opmode);
361 lp->old_speed = phydev->speed;
368 } else if (lp->old_link) {
376 u32 opmode = bfin_read_EMAC_OPMODE();
377 phy_print_status(phydev);
378 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
381 spin_unlock_irqrestore(&lp->lock, flags);
385 #define MDC_CLK 2500000
387 static int mii_probe(struct net_device *dev)
389 struct bfin_mac_local *lp = netdev_priv(dev);
390 struct phy_device *phydev = NULL;
391 unsigned short sysctl;
395 /* Enable PHY output early */
396 if (!(bfin_read_VR_CTL() & CLKBUFOE))
397 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
400 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
402 sysctl = bfin_read_EMAC_SYSCTL();
403 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
404 bfin_write_EMAC_SYSCTL(sysctl);
406 /* search for connect PHY device */
407 for (i = 0; i < PHY_MAX_ADDR; i++) {
408 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
411 continue; /* no PHY here... */
414 break; /* found it */
417 /* now we are supposed to have a proper phydev, to attach to... */
419 printk(KERN_INFO "%s: Don't found any phy device at all\n",
424 #if defined(CONFIG_BFIN_MAC_RMII)
425 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
426 0, PHY_INTERFACE_MODE_RMII);
428 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
429 0, PHY_INTERFACE_MODE_MII);
432 if (IS_ERR(phydev)) {
433 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
434 return PTR_ERR(phydev);
437 /* mask with MAC supported features */
438 phydev->supported &= (SUPPORTED_10baseT_Half
439 | SUPPORTED_10baseT_Full
440 | SUPPORTED_100baseT_Half
441 | SUPPORTED_100baseT_Full
443 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
447 phydev->advertising = phydev->supported;
454 printk(KERN_INFO "%s: attached PHY driver [%s] "
455 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
457 DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
458 MDC_CLK, mdc_div, sclk/1000000);
468 * interrupt routine for magic packet wakeup
470 static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
476 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
478 struct bfin_mac_local *lp = netdev_priv(dev);
481 return phy_ethtool_gset(lp->phydev, cmd);
487 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
489 struct bfin_mac_local *lp = netdev_priv(dev);
491 if (!capable(CAP_NET_ADMIN))
495 return phy_ethtool_sset(lp->phydev, cmd);
500 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
501 struct ethtool_drvinfo *info)
503 strcpy(info->driver, DRV_NAME);
504 strcpy(info->version, DRV_VERSION);
505 strcpy(info->fw_version, "N/A");
506 strcpy(info->bus_info, dev_name(&dev->dev));
509 static void bfin_mac_ethtool_getwol(struct net_device *dev,
510 struct ethtool_wolinfo *wolinfo)
512 struct bfin_mac_local *lp = netdev_priv(dev);
514 wolinfo->supported = WAKE_MAGIC;
515 wolinfo->wolopts = lp->wol;
518 static int bfin_mac_ethtool_setwol(struct net_device *dev,
519 struct ethtool_wolinfo *wolinfo)
521 struct bfin_mac_local *lp = netdev_priv(dev);
524 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
531 lp->wol = wolinfo->wolopts;
533 if (lp->wol && !lp->irq_wake_requested) {
534 /* register wake irq handler */
535 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
536 IRQF_DISABLED, "EMAC_WAKE", dev);
539 lp->irq_wake_requested = true;
542 if (!lp->wol && lp->irq_wake_requested) {
543 free_irq(IRQ_MAC_WAKEDET, dev);
544 lp->irq_wake_requested = false;
547 /* Make sure the PHY driver doesn't suspend */
548 device_init_wakeup(&dev->dev, lp->wol);
553 static const struct ethtool_ops bfin_mac_ethtool_ops = {
554 .get_settings = bfin_mac_ethtool_getsettings,
555 .set_settings = bfin_mac_ethtool_setsettings,
556 .get_link = ethtool_op_get_link,
557 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
558 .get_wol = bfin_mac_ethtool_getwol,
559 .set_wol = bfin_mac_ethtool_setwol,
562 /**************************************************************************/
563 void setup_system_regs(struct net_device *dev)
565 unsigned short sysctl;
568 * Odd word alignment for Receive Frame DMA word
569 * Configure checksum support and rcve frame word alignment
571 sysctl = bfin_read_EMAC_SYSCTL();
573 #if defined(BFIN_MAC_CSUM_OFFLOAD)
578 bfin_write_EMAC_SYSCTL(sysctl);
580 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
582 /* Initialize the TX DMA channel registers */
583 bfin_write_DMA2_X_COUNT(0);
584 bfin_write_DMA2_X_MODIFY(4);
585 bfin_write_DMA2_Y_COUNT(0);
586 bfin_write_DMA2_Y_MODIFY(0);
588 /* Initialize the RX DMA channel registers */
589 bfin_write_DMA1_X_COUNT(0);
590 bfin_write_DMA1_X_MODIFY(4);
591 bfin_write_DMA1_Y_COUNT(0);
592 bfin_write_DMA1_Y_MODIFY(0);
595 static void setup_mac_addr(u8 *mac_addr)
597 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
598 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
600 /* this depends on a little-endian machine */
601 bfin_write_EMAC_ADDRLO(addr_low);
602 bfin_write_EMAC_ADDRHI(addr_hi);
605 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
607 struct sockaddr *addr = p;
608 if (netif_running(dev))
610 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
611 setup_mac_addr(dev->dev_addr);
615 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
616 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
618 static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
619 struct ifreq *ifr, int cmd)
621 struct hwtstamp_config config;
622 struct bfin_mac_local *lp = netdev_priv(netdev);
624 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
626 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
629 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
630 __func__, config.flags, config.tx_type, config.rx_filter);
632 /* reserved for future extensions */
636 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
637 (config.tx_type != HWTSTAMP_TX_ON))
640 ptpctl = bfin_read_EMAC_PTP_CTL();
642 switch (config.rx_filter) {
643 case HWTSTAMP_FILTER_NONE:
645 * Dont allow any timestamping
648 bfin_write_EMAC_PTP_FV3(ptpfv3);
650 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
651 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
652 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
654 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
655 * to enable all the field matches.
658 bfin_write_EMAC_PTP_CTL(ptpctl);
660 * Keep the default values of the EMAC_PTP_FOFF register.
662 ptpfoff = 0x4A24170C;
663 bfin_write_EMAC_PTP_FOFF(ptpfoff);
665 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
669 bfin_write_EMAC_PTP_FV1(ptpfv1);
671 bfin_write_EMAC_PTP_FV2(ptpfv2);
673 * The default value (0xFFFC) allows the timestamping of both
674 * received Sync messages and Delay_Req messages.
677 bfin_write_EMAC_PTP_FV3(ptpfv3);
679 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
681 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
682 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
683 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
684 /* Clear all five comparison mask bits (bits[12:8]) in the
685 * EMAC_PTP_CTL register to enable all the field matches.
688 bfin_write_EMAC_PTP_CTL(ptpctl);
690 * Keep the default values of the EMAC_PTP_FOFF register, except set
691 * the PTPCOF field to 0x2A.
693 ptpfoff = 0x2A24170C;
694 bfin_write_EMAC_PTP_FOFF(ptpfoff);
696 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
700 bfin_write_EMAC_PTP_FV1(ptpfv1);
702 bfin_write_EMAC_PTP_FV2(ptpfv2);
704 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
705 * the value to 0xFFF0.
708 bfin_write_EMAC_PTP_FV3(ptpfv3);
710 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
712 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
713 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
714 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
716 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
717 * EFTM and PTPCM field comparison.
720 bfin_write_EMAC_PTP_CTL(ptpctl);
722 * Keep the default values of all the fields of the EMAC_PTP_FOFF
723 * register, except set the PTPCOF field to 0x0E.
725 ptpfoff = 0x0E24170C;
726 bfin_write_EMAC_PTP_FOFF(ptpfoff);
728 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
729 * corresponds to PTP messages on the MAC layer.
732 bfin_write_EMAC_PTP_FV1(ptpfv1);
734 bfin_write_EMAC_PTP_FV2(ptpfv2);
736 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
737 * messages, set the value to 0xFFF0.
740 bfin_write_EMAC_PTP_FV3(ptpfv3);
742 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
748 if (config.tx_type == HWTSTAMP_TX_OFF &&
749 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
751 bfin_write_EMAC_PTP_CTL(ptpctl);
756 bfin_write_EMAC_PTP_CTL(ptpctl);
759 * clear any existing timestamp
761 bfin_read_EMAC_PTP_RXSNAPLO();
762 bfin_read_EMAC_PTP_RXSNAPHI();
764 bfin_read_EMAC_PTP_TXSNAPLO();
765 bfin_read_EMAC_PTP_TXSNAPHI();
768 * Set registers so that rollover occurs soon to test this.
770 bfin_write_EMAC_PTP_TIMELO(0x00000000);
771 bfin_write_EMAC_PTP_TIMEHI(0xFF800000);
775 lp->compare.last_update = 0;
776 timecounter_init(&lp->clock,
778 ktime_to_ns(ktime_get_real()));
779 timecompare_update(&lp->compare, 0);
782 lp->stamp_cfg = config;
783 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
787 static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp)
789 ktime_t sys = ktime_get_real();
791 pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n",
792 __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec,
793 sys.tv.nsec, cmp->offset, cmp->skew);
796 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
798 struct bfin_mac_local *lp = netdev_priv(netdev);
799 union skb_shared_tx *shtx = skb_tx(skb);
801 if (shtx->hardware) {
802 int timeout_cnt = MAX_TIMEOUT_CNT;
804 /* When doing time stamping, keep the connection to the socket
807 shtx->in_progress = 1;
810 * The timestamping is done at the EMAC module's MII/RMII interface
811 * when the module sees the Start of Frame of an event message packet. This
812 * interface is the closest possible place to the physical Ethernet transmission
813 * medium, providing the best timing accuracy.
815 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
817 if (timeout_cnt == 0)
818 printk(KERN_ERR DRV_NAME
819 ": fails to timestamp the TX packet\n");
821 struct skb_shared_hwtstamps shhwtstamps;
825 regval = bfin_read_EMAC_PTP_TXSNAPLO();
826 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
827 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
828 ns = timecounter_cyc2time(&lp->clock,
830 timecompare_update(&lp->compare, ns);
831 shhwtstamps.hwtstamp = ns_to_ktime(ns);
832 shhwtstamps.syststamp =
833 timecompare_transform(&lp->compare, ns);
834 skb_tstamp_tx(skb, &shhwtstamps);
836 bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare);
841 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
843 struct bfin_mac_local *lp = netdev_priv(netdev);
846 struct skb_shared_hwtstamps *shhwtstamps;
848 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
851 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
855 shhwtstamps = skb_hwtstamps(skb);
857 regval = bfin_read_EMAC_PTP_RXSNAPLO();
858 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
859 ns = timecounter_cyc2time(&lp->clock, regval);
860 timecompare_update(&lp->compare, ns);
861 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
862 shhwtstamps->hwtstamp = ns_to_ktime(ns);
863 shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns);
865 bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare);
869 * bfin_read_clock - read raw cycle counter (to be used by time counter)
871 static cycle_t bfin_read_clock(const struct cyclecounter *tc)
875 stamp = bfin_read_EMAC_PTP_TIMELO();
876 stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL;
881 #define PTP_CLK 25000000
883 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
885 struct bfin_mac_local *lp = netdev_priv(netdev);
888 /* Initialize hardware timer */
889 append = PTP_CLK * (1ULL << 32);
890 do_div(append, get_sclk());
891 bfin_write_EMAC_PTP_ADDEND((u32)append);
893 memset(&lp->cycles, 0, sizeof(lp->cycles));
894 lp->cycles.read = bfin_read_clock;
895 lp->cycles.mask = CLOCKSOURCE_MASK(64);
896 lp->cycles.mult = 1000000000 / PTP_CLK;
897 lp->cycles.shift = 0;
899 /* Synchronize our NIC clock against system wall clock */
900 memset(&lp->compare, 0, sizeof(lp->compare));
901 lp->compare.source = &lp->clock;
902 lp->compare.target = ktime_get_real;
903 lp->compare.num_samples = 10;
905 /* Initialize hwstamp config */
906 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
907 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
911 # define bfin_mac_hwtstamp_is_none(cfg) 0
912 # define bfin_mac_hwtstamp_init(dev)
913 # define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
914 # define bfin_rx_hwtstamp(dev, skb)
915 # define bfin_tx_hwtstamp(dev, skb)
918 static void adjust_tx_list(void)
920 int timeout_cnt = MAX_TIMEOUT_CNT;
922 if (tx_list_head->status.status_word != 0 &&
923 current_tx_ptr != tx_list_head) {
924 goto adjust_head; /* released something, just return; */
928 * if nothing released, check wait condition
929 * current's next can not be the head,
930 * otherwise the dma will not stop as we want
932 if (current_tx_ptr->next->next == tx_list_head) {
933 while (tx_list_head->status.status_word == 0) {
935 if (tx_list_head->status.status_word != 0 ||
936 !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) {
939 if (timeout_cnt-- < 0) {
940 printk(KERN_ERR DRV_NAME
941 ": wait for adjust tx list head timeout\n");
945 if (tx_list_head->status.status_word != 0) {
954 tx_list_head->desc_a.config &= ~DMAEN;
955 tx_list_head->status.status_word = 0;
956 if (tx_list_head->skb) {
957 dev_kfree_skb(tx_list_head->skb);
958 tx_list_head->skb = NULL;
960 printk(KERN_ERR DRV_NAME
961 ": no sk_buff in a transmitted frame!\n");
963 tx_list_head = tx_list_head->next;
964 } while (tx_list_head->status.status_word != 0 &&
965 current_tx_ptr != tx_list_head);
970 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
971 struct net_device *dev)
974 u32 data_align = (unsigned long)(skb->data) & 0x3;
975 union skb_shared_tx *shtx = skb_tx(skb);
977 current_tx_ptr->skb = skb;
979 if (data_align == 0x2) {
980 /* move skb->data to current_tx_ptr payload */
981 data = (u16 *)(skb->data) - 1;
982 *data = (u16)(skb->len);
984 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
985 * a DMA_Length_Word field associated with the packet. The lower 12 bits
986 * of this field are the length of the packet payload in bytes and the higher
987 * 4 bits are the timestamping enable field.
992 current_tx_ptr->desc_a.start_addr = (u32)data;
993 /* this is important! */
994 blackfin_dcache_flush_range((u32)data,
995 (u32)((u8 *)data + skb->len + 4));
997 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
998 /* enable timestamping for the sent packet */
1000 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
1001 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1003 current_tx_ptr->desc_a.start_addr =
1004 (u32)current_tx_ptr->packet;
1005 if (current_tx_ptr->status.status_word != 0)
1006 current_tx_ptr->status.status_word = 0;
1007 blackfin_dcache_flush_range(
1008 (u32)current_tx_ptr->packet,
1009 (u32)(current_tx_ptr->packet + skb->len + 2));
1012 /* make sure the internal data buffers in the core are drained
1013 * so that the DMA descriptors are completely written when the
1014 * DMA engine goes to fetch them below
1018 /* enable this packet's dma */
1019 current_tx_ptr->desc_a.config |= DMAEN;
1021 /* tx dma is running, just return */
1022 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
1025 /* tx dma is not running */
1026 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1027 /* dma enabled, read from memory, size is 6 */
1028 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1029 /* Turn on the EMAC tx */
1030 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1035 bfin_tx_hwtstamp(dev, skb);
1037 current_tx_ptr = current_tx_ptr->next;
1038 dev->stats.tx_packets++;
1039 dev->stats.tx_bytes += (skb->len);
1040 return NETDEV_TX_OK;
1043 #define IP_HEADER_OFF 0
1044 #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1045 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1047 static void bfin_mac_rx(struct net_device *dev)
1049 struct sk_buff *skb, *new_skb;
1051 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
1052 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1054 unsigned char fcs[ETH_FCS_LEN + 1];
1057 /* check if frame status word reports an error condition
1058 * we which case we simply drop the packet
1060 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1061 printk(KERN_NOTICE DRV_NAME
1062 ": rx: receive error - packet dropped\n");
1063 dev->stats.rx_dropped++;
1067 /* allocate a new skb for next time receive */
1068 skb = current_rx_ptr->skb;
1070 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
1072 printk(KERN_NOTICE DRV_NAME
1073 ": rx: low on mem - packet dropped\n");
1074 dev->stats.rx_dropped++;
1077 /* reserve 2 bytes for RXDWA padding */
1078 skb_reserve(new_skb, NET_IP_ALIGN);
1079 /* Invidate the data cache of skb->data range when it is write back
1080 * cache. It will prevent overwritting the new data from DMA
1082 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1083 (unsigned long)new_skb->end);
1085 current_rx_ptr->skb = new_skb;
1086 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1088 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
1089 /* Deduce Ethernet FCS length from Ethernet payload length */
1093 skb->protocol = eth_type_trans(skb, dev);
1095 bfin_rx_hwtstamp(dev, skb);
1097 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1098 /* Checksum offloading only works for IPv4 packets with the standard IP header
1099 * length of 20 bytes, because the blackfin MAC checksum calculation is
1100 * based on that assumption. We must NOT use the calculated checksum if our
1101 * IP version or header break that assumption.
1103 if (skb->data[IP_HEADER_OFF] == 0x45) {
1104 skb->csum = current_rx_ptr->status.ip_payload_csum;
1106 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1107 * IP checksum is based on 16-bit one's complement algorithm.
1108 * To deduce a value from checksum is equal to add its inversion.
1109 * If the IP payload len is odd, the inversed FCS should also
1110 * begin from odd address and leave first byte zero.
1114 for (i = 0; i < ETH_FCS_LEN; i++)
1115 fcs[i + 1] = ~skb->data[skb->len + i];
1116 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1118 for (i = 0; i < ETH_FCS_LEN; i++)
1119 fcs[i] = ~skb->data[skb->len + i];
1120 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1122 skb->ip_summed = CHECKSUM_COMPLETE;
1127 dev->stats.rx_packets++;
1128 dev->stats.rx_bytes += len;
1130 current_rx_ptr->status.status_word = 0x00000000;
1131 current_rx_ptr = current_rx_ptr->next;
1134 /* interrupt routine to handle rx and error signal */
1135 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1137 struct net_device *dev = dev_id;
1141 if (current_rx_ptr->status.status_word == 0) {
1142 /* no more new packet received */
1144 if (current_rx_ptr->next->status.status_word != 0) {
1145 current_rx_ptr = current_rx_ptr->next;
1149 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1150 DMA_DONE | DMA_ERR);
1157 goto get_one_packet;
1160 #ifdef CONFIG_NET_POLL_CONTROLLER
1161 static void bfin_mac_poll(struct net_device *dev)
1163 disable_irq(IRQ_MAC_RX);
1164 bfin_mac_interrupt(IRQ_MAC_RX, dev);
1165 enable_irq(IRQ_MAC_RX);
1167 #endif /* CONFIG_NET_POLL_CONTROLLER */
1169 static void bfin_mac_disable(void)
1171 unsigned int opmode;
1173 opmode = bfin_read_EMAC_OPMODE();
1176 /* Turn off the EMAC */
1177 bfin_write_EMAC_OPMODE(opmode);
1181 * Enable Interrupts, Receive, and Transmit
1183 static void bfin_mac_enable(void)
1187 pr_debug("%s: %s\n", DRV_NAME, __func__);
1190 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1191 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1196 /* We enable only RX here */
1197 /* ASTP : Enable Automatic Pad Stripping
1198 PR : Promiscuous Mode for test
1199 PSF : Receive frames with total length less than 64 bytes.
1200 FDMODE : Full Duplex Mode
1201 LB : Internal Loopback for test
1202 RE : Receiver Enable */
1203 opmode = bfin_read_EMAC_OPMODE();
1204 if (opmode & FDMODE)
1207 opmode |= DRO | DC | PSF;
1210 #if defined(CONFIG_BFIN_MAC_RMII)
1211 opmode |= RMII; /* For Now only 100MBit are supported */
1212 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2
1216 /* Turn on the EMAC rx */
1217 bfin_write_EMAC_OPMODE(opmode);
1220 /* Our watchdog timed out. Called by the networking layer */
1221 static void bfin_mac_timeout(struct net_device *dev)
1223 pr_debug("%s: %s\n", dev->name, __func__);
1227 /* reset tx queue */
1228 tx_list_tail = tx_list_head->next;
1232 /* We can accept TX packets again */
1233 dev->trans_start = jiffies; /* prevent tx timeout */
1234 netif_wake_queue(dev);
1237 static void bfin_mac_multicast_hash(struct net_device *dev)
1239 u32 emac_hashhi, emac_hashlo;
1240 struct netdev_hw_addr *ha;
1244 emac_hashhi = emac_hashlo = 0;
1246 netdev_for_each_mc_addr(ha, dev) {
1249 /* skip non-multicast addresses */
1253 crc = ether_crc(ETH_ALEN, addrs);
1257 emac_hashhi |= 1 << (crc & 0x1f);
1259 emac_hashlo |= 1 << (crc & 0x1f);
1262 bfin_write_EMAC_HASHHI(emac_hashhi);
1263 bfin_write_EMAC_HASHLO(emac_hashlo);
1267 * This routine will, depending on the values passed to it,
1268 * either make it accept multicast packets, go into
1269 * promiscuous mode (for TCPDUMP and cousins) or accept
1270 * a select set of multicast packets
1272 static void bfin_mac_set_multicast_list(struct net_device *dev)
1276 if (dev->flags & IFF_PROMISC) {
1277 printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
1278 sysctl = bfin_read_EMAC_OPMODE();
1280 bfin_write_EMAC_OPMODE(sysctl);
1281 } else if (dev->flags & IFF_ALLMULTI) {
1282 /* accept all multicast */
1283 sysctl = bfin_read_EMAC_OPMODE();
1285 bfin_write_EMAC_OPMODE(sysctl);
1286 } else if (!netdev_mc_empty(dev)) {
1287 /* set up multicast hash table */
1288 sysctl = bfin_read_EMAC_OPMODE();
1290 bfin_write_EMAC_OPMODE(sysctl);
1291 bfin_mac_multicast_hash(dev);
1293 /* clear promisc or multicast mode */
1294 sysctl = bfin_read_EMAC_OPMODE();
1295 sysctl &= ~(RAF | PAM);
1296 bfin_write_EMAC_OPMODE(sysctl);
1300 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1304 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1311 * this puts the device in an inactive state
1313 static void bfin_mac_shutdown(struct net_device *dev)
1315 /* Turn off the EMAC */
1316 bfin_write_EMAC_OPMODE(0x00000000);
1317 /* Turn off the EMAC RX DMA */
1318 bfin_write_DMA1_CONFIG(0x0000);
1319 bfin_write_DMA2_CONFIG(0x0000);
1323 * Open and Initialize the interface
1325 * Set up everything, reset the card, etc..
1327 static int bfin_mac_open(struct net_device *dev)
1329 struct bfin_mac_local *lp = netdev_priv(dev);
1331 pr_debug("%s: %s\n", dev->name, __func__);
1334 * Check that the address is valid. If its not, refuse
1335 * to bring the device up. The user must specify an
1336 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1338 if (!is_valid_ether_addr(dev->dev_addr)) {
1339 printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
1343 /* initial rx and tx list */
1344 retval = desc_list_init();
1349 phy_start(lp->phydev);
1350 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
1351 setup_system_regs(dev);
1352 setup_mac_addr(dev->dev_addr);
1355 pr_debug("hardware init finished\n");
1356 netif_start_queue(dev);
1357 netif_carrier_on(dev);
1363 * this makes the board clean up everything that it can
1364 * and not talk to the outside world. Caused by
1365 * an 'ifconfig ethX down'
1367 static int bfin_mac_close(struct net_device *dev)
1369 struct bfin_mac_local *lp = netdev_priv(dev);
1370 pr_debug("%s: %s\n", dev->name, __func__);
1372 netif_stop_queue(dev);
1373 netif_carrier_off(dev);
1375 phy_stop(lp->phydev);
1376 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1378 /* clear everything */
1379 bfin_mac_shutdown(dev);
1381 /* free the rx/tx buffers */
1387 static const struct net_device_ops bfin_mac_netdev_ops = {
1388 .ndo_open = bfin_mac_open,
1389 .ndo_stop = bfin_mac_close,
1390 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1391 .ndo_set_mac_address = bfin_mac_set_mac_address,
1392 .ndo_tx_timeout = bfin_mac_timeout,
1393 .ndo_set_multicast_list = bfin_mac_set_multicast_list,
1394 .ndo_do_ioctl = bfin_mac_ioctl,
1395 .ndo_validate_addr = eth_validate_addr,
1396 .ndo_change_mtu = eth_change_mtu,
1397 #ifdef CONFIG_NET_POLL_CONTROLLER
1398 .ndo_poll_controller = bfin_mac_poll,
1402 static int __devinit bfin_mac_probe(struct platform_device *pdev)
1404 struct net_device *ndev;
1405 struct bfin_mac_local *lp;
1406 struct platform_device *pd;
1409 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1411 dev_err(&pdev->dev, "Cannot allocate net device!\n");
1415 SET_NETDEV_DEV(ndev, &pdev->dev);
1416 platform_set_drvdata(pdev, ndev);
1417 lp = netdev_priv(ndev);
1419 /* Grab the MAC address in the MAC */
1420 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1421 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1424 /*todo: how to proble? which is revision_register */
1425 bfin_write_EMAC_ADDRLO(0x12345678);
1426 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1427 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1429 goto out_err_probe_mac;
1434 * Is it valid? (Did bootloader initialize it?)
1435 * Grab the MAC from the board somehow
1436 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1438 if (!is_valid_ether_addr(ndev->dev_addr))
1439 bfin_get_ether_addr(ndev->dev_addr);
1441 /* If still not valid, get a random one */
1442 if (!is_valid_ether_addr(ndev->dev_addr))
1443 random_ether_addr(ndev->dev_addr);
1445 setup_mac_addr(ndev->dev_addr);
1447 if (!pdev->dev.platform_data) {
1448 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1450 goto out_err_probe_mac;
1452 pd = pdev->dev.platform_data;
1453 lp->mii_bus = platform_get_drvdata(pd);
1454 lp->mii_bus->priv = ndev;
1456 rc = mii_probe(ndev);
1458 dev_err(&pdev->dev, "MII Probe failed!\n");
1459 goto out_err_mii_probe;
1462 /* Fill in the fields of the device structure with ethernet values. */
1465 ndev->netdev_ops = &bfin_mac_netdev_ops;
1466 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1468 spin_lock_init(&lp->lock);
1470 /* now, enable interrupts */
1471 /* register irq handler */
1472 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1473 IRQF_DISABLED, "EMAC_RX", ndev);
1475 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1477 goto out_err_request_irq;
1480 rc = register_netdev(ndev);
1482 dev_err(&pdev->dev, "Cannot register net device!\n");
1483 goto out_err_reg_ndev;
1486 bfin_mac_hwtstamp_init(ndev);
1488 /* now, print out the card info, in a short format.. */
1489 dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1494 free_irq(IRQ_MAC_RX, ndev);
1495 out_err_request_irq:
1497 mdiobus_unregister(lp->mii_bus);
1498 mdiobus_free(lp->mii_bus);
1499 peripheral_free_list(pin_req);
1501 platform_set_drvdata(pdev, NULL);
1507 static int __devexit bfin_mac_remove(struct platform_device *pdev)
1509 struct net_device *ndev = platform_get_drvdata(pdev);
1510 struct bfin_mac_local *lp = netdev_priv(ndev);
1512 platform_set_drvdata(pdev, NULL);
1514 lp->mii_bus->priv = NULL;
1516 unregister_netdev(ndev);
1518 free_irq(IRQ_MAC_RX, ndev);
1522 peripheral_free_list(pin_req);
1528 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1530 struct net_device *net_dev = platform_get_drvdata(pdev);
1531 struct bfin_mac_local *lp = netdev_priv(net_dev);
1534 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1535 bfin_write_EMAC_WKUP_CTL(MPKE);
1536 enable_irq_wake(IRQ_MAC_WAKEDET);
1538 if (netif_running(net_dev))
1539 bfin_mac_close(net_dev);
1545 static int bfin_mac_resume(struct platform_device *pdev)
1547 struct net_device *net_dev = platform_get_drvdata(pdev);
1548 struct bfin_mac_local *lp = netdev_priv(net_dev);
1551 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1552 bfin_write_EMAC_WKUP_CTL(0);
1553 disable_irq_wake(IRQ_MAC_WAKEDET);
1555 if (netif_running(net_dev))
1556 bfin_mac_open(net_dev);
1562 #define bfin_mac_suspend NULL
1563 #define bfin_mac_resume NULL
1564 #endif /* CONFIG_PM */
1566 static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1568 struct mii_bus *miibus;
1572 * We are setting up a network card,
1573 * so set the GPIO pins to Ethernet mode
1575 rc = peripheral_request_list(pin_req, DRV_NAME);
1577 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1582 miibus = mdiobus_alloc();
1585 miibus->read = bfin_mdiobus_read;
1586 miibus->write = bfin_mdiobus_write;
1587 miibus->reset = bfin_mdiobus_reset;
1589 miibus->parent = &pdev->dev;
1590 miibus->name = "bfin_mii_bus";
1591 snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
1592 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1593 if (miibus->irq == NULL)
1595 for (i = 0; i < PHY_MAX_ADDR; ++i)
1596 miibus->irq[i] = PHY_POLL;
1598 rc = mdiobus_register(miibus);
1600 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1601 goto out_err_mdiobus_register;
1604 platform_set_drvdata(pdev, miibus);
1607 out_err_mdiobus_register:
1608 mdiobus_free(miibus);
1610 peripheral_free_list(pin_req);
1615 static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1617 struct mii_bus *miibus = platform_get_drvdata(pdev);
1618 platform_set_drvdata(pdev, NULL);
1619 mdiobus_unregister(miibus);
1620 mdiobus_free(miibus);
1621 peripheral_free_list(pin_req);
1625 static struct platform_driver bfin_mii_bus_driver = {
1626 .probe = bfin_mii_bus_probe,
1627 .remove = __devexit_p(bfin_mii_bus_remove),
1629 .name = "bfin_mii_bus",
1630 .owner = THIS_MODULE,
1634 static struct platform_driver bfin_mac_driver = {
1635 .probe = bfin_mac_probe,
1636 .remove = __devexit_p(bfin_mac_remove),
1637 .resume = bfin_mac_resume,
1638 .suspend = bfin_mac_suspend,
1641 .owner = THIS_MODULE,
1645 static int __init bfin_mac_init(void)
1648 ret = platform_driver_register(&bfin_mii_bus_driver);
1650 return platform_driver_register(&bfin_mac_driver);
1654 module_init(bfin_mac_init);
1656 static void __exit bfin_mac_cleanup(void)
1658 platform_driver_unregister(&bfin_mac_driver);
1659 platform_driver_unregister(&bfin_mii_bus_driver);
1662 module_exit(bfin_mac_cleanup);