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   1 /* b44.c: Broadcom 4400 device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   5  *
   6  * Distribute under GPL.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/types.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/mii.h>
  16 #include <linux/if_ether.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/pci.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/version.h>
  22 #include <linux/dma-mapping.h>
  23
  24 #include <asm/uaccess.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include "b44.h"
  29
  30 #define DRV_MODULE_NAME         "b44"
  31 #define PFX DRV_MODULE_NAME     ": "
  32 #define DRV_MODULE_VERSION      "0.95"
  33 #define DRV_MODULE_RELDATE      "Aug 3, 2004"
  34
  35 #define B44_DEF_MSG_ENABLE        \
  36         (NETIF_MSG_DRV          | \
  37          NETIF_MSG_PROBE        | \
  38          NETIF_MSG_LINK         | \
  39          NETIF_MSG_TIMER        | \
  40          NETIF_MSG_IFDOWN       | \
  41          NETIF_MSG_IFUP         | \
  42          NETIF_MSG_RX_ERR       | \
  43          NETIF_MSG_TX_ERR)
  44
  45 /* length of time before we decide the hardware is borked,
  46  * and dev->tx_timeout() should be called to fix the problem
  47  */
  48 #define B44_TX_TIMEOUT                  (5 * HZ)
  49
  50 /* hardware minimum and maximum for a single frame's data payload */
  51 #define B44_MIN_MTU                     60
  52 #define B44_MAX_MTU                     1500
  53
  54 #define B44_RX_RING_SIZE                512
  55 #define B44_DEF_RX_RING_PENDING         200
  56 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  57                                  B44_RX_RING_SIZE)
  58 #define B44_TX_RING_SIZE                512
  59 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  60 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  61                                  B44_TX_RING_SIZE)
  62 #define B44_DMA_MASK 0x3fffffff
  63
  64 #define TX_RING_GAP(BP) \
  65         (B44_TX_RING_SIZE - (BP)->tx_pending)
  66 #define TX_BUFFS_AVAIL(BP)                                              \
  67         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  68           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  69           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  70 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  71
  72 #define RX_PKT_BUF_SZ           (1536 + bp->rx_offset + 64)
  73 #define TX_PKT_BUF_SZ           (B44_MAX_MTU + ETH_HLEN + 8)
  74
  75 /* minimum number of free TX descriptors required to wake up TX process */
  76 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  77
  78 static char version[] __devinitdata =
  79         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  80
  81 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  82 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  83 MODULE_LICENSE("GPL");
  84 MODULE_VERSION(DRV_MODULE_VERSION);
  85
  86 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
  87 module_param(b44_debug, int, 0);
  88 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  89
  90 static struct pci_device_id b44_pci_tbl[] = {
  91         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
  92           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  93         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
  94           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  95         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  96           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  97         { }     /* terminate list with empty entry */
  98 };
  99
 100 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
 101
 102 static void b44_halt(struct b44 *);
 103 static void b44_init_rings(struct b44 *);
 104 static void b44_init_hw(struct b44 *);
 105
 106 static int dma_desc_align_mask;
 107 static int dma_desc_sync_size;
 108
 109 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
 110 #define _B44(x...)      # x,
 111 B44_STAT_REG_DECLARE
 112 #undef _B44
 113 };
 114
 115 static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
 116                                                 dma_addr_t dma_base,
 117                                                 unsigned long offset,
 118                                                 enum dma_data_direction dir)
 119 {
 120         dma_sync_single_range_for_device(&pdev->dev, dma_base,
 121                                          offset & dma_desc_align_mask,
 122                                          dma_desc_sync_size, dir);
 123 }
 124
 125 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
 126                                              dma_addr_t dma_base,
 127                                              unsigned long offset,
 128                                              enum dma_data_direction dir)
 129 {
 130         dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
 131                                       offset & dma_desc_align_mask,
 132                                       dma_desc_sync_size, dir);
 133 }
 134
 135 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
 136 {
 137         return readl(bp->regs + reg);
 138 }
 139
 140 static inline void bw32(const struct b44 *bp,
 141                         unsigned long reg, unsigned long val)
 142 {
 143         writel(val, bp->regs + reg);
 144 }
 145
 146 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 147                         u32 bit, unsigned long timeout, const int clear)
 148 {
 149         unsigned long i;
 150
 151         for (i = 0; i < timeout; i++) {
 152                 u32 val = br32(bp, reg);
 153
 154                 if (clear && !(val & bit))
 155                         break;
 156                 if (!clear && (val & bit))
 157                         break;
 158                 udelay(10);
 159         }
 160         if (i == timeout) {
 161                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 162                        "%lx to %s.\n",
 163                        bp->dev->name,
 164                        bit, reg,
 165                        (clear ? "clear" : "set"));
 166                 return -ENODEV;
 167         }
 168         return 0;
 169 }
 170
 171 /* Sonics SiliconBackplane support routines.  ROFL, you should see all the
 172  * buzz words used on this company's website :-)
 173  *
 174  * All of these routines must be invoked with bp->lock held and
 175  * interrupts disabled.
 176  */
 177
 178 #define SB_PCI_DMA             0x40000000      /* Client Mode PCI memory access space (1 GB) */
 179 #define BCM4400_PCI_CORE_ADDR  0x18002000      /* Address of PCI core on BCM4400 cards */
 180
 181 static u32 ssb_get_core_rev(struct b44 *bp)
 182 {
 183         return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
 184 }
 185
 186 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
 187 {
 188         u32 bar_orig, pci_rev, val;
 189
 190         pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
 191         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
 192         pci_rev = ssb_get_core_rev(bp);
 193
 194         val = br32(bp, B44_SBINTVEC);
 195         val |= cores;
 196         bw32(bp, B44_SBINTVEC, val);
 197
 198         val = br32(bp, SSB_PCI_TRANS_2);
 199         val |= SSB_PCI_PREF | SSB_PCI_BURST;
 200         bw32(bp, SSB_PCI_TRANS_2, val);
 201
 202         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
 203
 204         return pci_rev;
 205 }
 206
 207 static void ssb_core_disable(struct b44 *bp)
 208 {
 209         if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
 210                 return;
 211
 212         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
 213         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
 214         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
 215         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 216                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 217         br32(bp, B44_SBTMSLOW);
 218         udelay(1);
 219         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 220         br32(bp, B44_SBTMSLOW);
 221         udelay(1);
 222 }
 223
 224 static void ssb_core_reset(struct b44 *bp)
 225 {
 226         u32 val;
 227
 228         ssb_core_disable(bp);
 229         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 230         br32(bp, B44_SBTMSLOW);
 231         udelay(1);
 232
 233         /* Clear SERR if set, this is a hw bug workaround.  */
 234         if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 235                 bw32(bp, B44_SBTMSHIGH, 0);
 236
 237         val = br32(bp, B44_SBIMSTATE);
 238         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 239                 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 240
 241         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 242         br32(bp, B44_SBTMSLOW);
 243         udelay(1);
 244
 245         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 246         br32(bp, B44_SBTMSLOW);
 247         udelay(1);
 248 }
 249
 250 static int ssb_core_unit(struct b44 *bp)
 251 {
 252 #if 0
 253         u32 val = br32(bp, B44_SBADMATCH0);
 254         u32 base;
 255
 256         type = val & SBADMATCH0_TYPE_MASK;
 257         switch (type) {
 258         case 0:
 259                 base = val & SBADMATCH0_BS0_MASK;
 260                 break;
 261
 262         case 1:
 263                 base = val & SBADMATCH0_BS1_MASK;
 264                 break;
 265
 266         case 2:
 267         default:
 268                 base = val & SBADMATCH0_BS2_MASK;
 269                 break;
 270         };
 271 #endif
 272         return 0;
 273 }
 274
 275 static int ssb_is_core_up(struct b44 *bp)
 276 {
 277         return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 278                 == SBTMSLOW_CLOCK);
 279 }
 280
 281 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 282 {
 283         u32 val;
 284
 285         val  = ((u32) data[2]) << 24;
 286         val |= ((u32) data[3]) << 16;
 287         val |= ((u32) data[4]) <<  8;
 288         val |= ((u32) data[5]) <<  0;
 289         bw32(bp, B44_CAM_DATA_LO, val);
 290         val = (CAM_DATA_HI_VALID |
 291                (((u32) data[0]) << 8) |
 292                (((u32) data[1]) << 0));
 293         bw32(bp, B44_CAM_DATA_HI, val);
 294         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 295                             (index << CAM_CTRL_INDEX_SHIFT)));
 296         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 297 }
 298
 299 static inline void __b44_disable_ints(struct b44 *bp)
 300 {
 301         bw32(bp, B44_IMASK, 0);
 302 }
 303
 304 static void b44_disable_ints(struct b44 *bp)
 305 {
 306         __b44_disable_ints(bp);
 307
 308         /* Flush posted writes. */
 309         br32(bp, B44_IMASK);
 310 }
 311
 312 static void b44_enable_ints(struct b44 *bp)
 313 {
 314         bw32(bp, B44_IMASK, bp->imask);
 315 }
 316
 317 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 318 {
 319         int err;
 320
 321         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 322         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 323                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 324                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 325                              (reg << MDIO_DATA_RA_SHIFT) |
 326                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 327         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 328         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 329
 330         return err;
 331 }
 332
 333 static int b44_writephy(struct b44 *bp, int reg, u32 val)
 334 {
 335         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 336         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 337                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 338                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 339                              (reg << MDIO_DATA_RA_SHIFT) |
 340                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 341                              (val & MDIO_DATA_DATA)));
 342         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 343 }
 344
 345 /* miilib interface */
 346 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 347  * due to code existing before miilib use was added to this driver.
 348  * Someone should remove this artificial driver limitation in
 349  * b44_{read,write}phy.  bp->phy_addr itself is fine (and needed).
 350  */
 351 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 352 {
 353         u32 val;
 354         struct b44 *bp = netdev_priv(dev);
 355         int rc = b44_readphy(bp, location, &val);
 356         if (rc)
 357                 return 0xffffffff;
 358         return val;
 359 }
 360
 361 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 362                          int val)
 363 {
 364         struct b44 *bp = netdev_priv(dev);
 365         b44_writephy(bp, location, val);
 366 }
 367
 368 static int b44_phy_reset(struct b44 *bp)
 369 {
 370         u32 val;
 371         int err;
 372
 373         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 374         if (err)
 375                 return err;
 376         udelay(100);
 377         err = b44_readphy(bp, MII_BMCR, &val);
 378         if (!err) {
 379                 if (val & BMCR_RESET) {
 380                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 381                                bp->dev->name);
 382                         err = -ENODEV;
 383                 }
 384         }
 385
 386         return 0;
 387 }
 388
 389 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 390 {
 391         u32 val;
 392
 393         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 394         bp->flags |= pause_flags;
 395
 396         val = br32(bp, B44_RXCONFIG);
 397         if (pause_flags & B44_FLAG_RX_PAUSE)
 398                 val |= RXCONFIG_FLOW;
 399         else
 400                 val &= ~RXCONFIG_FLOW;
 401         bw32(bp, B44_RXCONFIG, val);
 402
 403         val = br32(bp, B44_MAC_FLOW);
 404         if (pause_flags & B44_FLAG_TX_PAUSE)
 405                 val |= (MAC_FLOW_PAUSE_ENAB |
 406                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 407         else
 408                 val &= ~MAC_FLOW_PAUSE_ENAB;
 409         bw32(bp, B44_MAC_FLOW, val);
 410 }
 411
 412 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 413 {
 414         u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
 415                                       B44_FLAG_RX_PAUSE);
 416
 417         if (local & ADVERTISE_PAUSE_CAP) {
 418                 if (local & ADVERTISE_PAUSE_ASYM) {
 419                         if (remote & LPA_PAUSE_CAP)
 420                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 421                                                B44_FLAG_RX_PAUSE);
 422                         else if (remote & LPA_PAUSE_ASYM)
 423                                 pause_enab |= B44_FLAG_RX_PAUSE;
 424                 } else {
 425                         if (remote & LPA_PAUSE_CAP)
 426                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 427                                                B44_FLAG_RX_PAUSE);
 428                 }
 429         } else if (local & ADVERTISE_PAUSE_ASYM) {
 430                 if ((remote & LPA_PAUSE_CAP) &&
 431                     (remote & LPA_PAUSE_ASYM))
 432                         pause_enab |= B44_FLAG_TX_PAUSE;
 433         }
 434
 435         __b44_set_flow_ctrl(bp, pause_enab);
 436 }
 437
 438 static int b44_setup_phy(struct b44 *bp)
 439 {
 440         u32 val;
 441         int err;
 442
 443         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 444                 goto out;
 445         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 446                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 447                 goto out;
 448         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 449                 goto out;
 450         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 451                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 452                 goto out;
 453
 454         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 455                 u32 adv = ADVERTISE_CSMA;
 456
 457                 if (bp->flags & B44_FLAG_ADV_10HALF)
 458                         adv |= ADVERTISE_10HALF;
 459                 if (bp->flags & B44_FLAG_ADV_10FULL)
 460                         adv |= ADVERTISE_10FULL;
 461                 if (bp->flags & B44_FLAG_ADV_100HALF)
 462                         adv |= ADVERTISE_100HALF;
 463                 if (bp->flags & B44_FLAG_ADV_100FULL)
 464                         adv |= ADVERTISE_100FULL;
 465
 466                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 467                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 468
 469                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 470                         goto out;
 471                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 472                                                        BMCR_ANRESTART))) != 0)
 473                         goto out;
 474         } else {
 475                 u32 bmcr;
 476
 477                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 478                         goto out;
 479                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 480                 if (bp->flags & B44_FLAG_100_BASE_T)
 481                         bmcr |= BMCR_SPEED100;
 482                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 483                         bmcr |= BMCR_FULLDPLX;
 484                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 485                         goto out;
 486
 487                 /* Since we will not be negotiating there is no safe way
 488                  * to determine if the link partner supports flow control
 489                  * or not.  So just disable it completely in this case.
 490                  */
 491                 b44_set_flow_ctrl(bp, 0, 0);
 492         }
 493
 494 out:
 495         return err;
 496 }
 497
 498 static void b44_stats_update(struct b44 *bp)
 499 {
 500         unsigned long reg;
 501         u32 *val;
 502
 503         val = &bp->hw_stats.tx_good_octets;
 504         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 505                 *val++ += br32(bp, reg);
 506         }
 507
 508         /* Pad */
 509         reg += 8*4UL;
 510
 511         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 512                 *val++ += br32(bp, reg);
 513         }
 514 }
 515
 516 static void b44_link_report(struct b44 *bp)
 517 {
 518         if (!netif_carrier_ok(bp->dev)) {
 519                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 520         } else {
 521                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 522                        bp->dev->name,
 523                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 524                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 525
 526                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 527                        "%s for RX.\n",
 528                        bp->dev->name,
 529                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 530                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 531         }
 532 }
 533
 534 static void b44_check_phy(struct b44 *bp)
 535 {
 536         u32 bmsr, aux;
 537
 538         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 539             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 540             (bmsr != 0xffff)) {
 541                 if (aux & MII_AUXCTRL_SPEED)
 542                         bp->flags |= B44_FLAG_100_BASE_T;
 543                 else
 544                         bp->flags &= ~B44_FLAG_100_BASE_T;
 545                 if (aux & MII_AUXCTRL_DUPLEX)
 546                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 547                 else
 548                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 549
 550                 if (!netif_carrier_ok(bp->dev) &&
 551                     (bmsr & BMSR_LSTATUS)) {
 552                         u32 val = br32(bp, B44_TX_CTRL);
 553                         u32 local_adv, remote_adv;
 554
 555                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 556                                 val |= TX_CTRL_DUPLEX;
 557                         else
 558                                 val &= ~TX_CTRL_DUPLEX;
 559                         bw32(bp, B44_TX_CTRL, val);
 560
 561                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 562                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 563                             !b44_readphy(bp, MII_LPA, &remote_adv))
 564                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 565
 566                         /* Link now up */
 567                         netif_carrier_on(bp->dev);
 568                         b44_link_report(bp);
 569                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 570                         /* Link now down */
 571                         netif_carrier_off(bp->dev);
 572                         b44_link_report(bp);
 573                 }
 574
 575                 if (bmsr & BMSR_RFAULT)
 576                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 577                                bp->dev->name);
 578                 if (bmsr & BMSR_JCD)
 579                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 580                                bp->dev->name);
 581         }
 582 }
 583
 584 static void b44_timer(unsigned long __opaque)
 585 {
 586         struct b44 *bp = (struct b44 *) __opaque;
 587
 588         spin_lock_irq(&bp->lock);
 589
 590         b44_check_phy(bp);
 591
 592         b44_stats_update(bp);
 593
 594         spin_unlock_irq(&bp->lock);
 595
 596         bp->timer.expires = jiffies + HZ;
 597         add_timer(&bp->timer);
 598 }
 599
 600 static void b44_tx(struct b44 *bp)
 601 {
 602         u32 cur, cons;
 603
 604         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 605         cur /= sizeof(struct dma_desc);
 606
 607         /* XXX needs updating when NETIF_F_SG is supported */
 608         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 609                 struct ring_info *rp = &bp->tx_buffers[cons];
 610                 struct sk_buff *skb = rp->skb;
 611
 612                 if (unlikely(skb == NULL))
 613                         BUG();
 614
 615                 pci_unmap_single(bp->pdev,
 616                                  pci_unmap_addr(rp, mapping),
 617                                  skb->len,
 618                                  PCI_DMA_TODEVICE);
 619                 rp->skb = NULL;
 620                 dev_kfree_skb_irq(skb);
 621         }
 622
 623         bp->tx_cons = cons;
 624         if (netif_queue_stopped(bp->dev) &&
 625             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 626                 netif_wake_queue(bp->dev);
 627
 628         bw32(bp, B44_GPTIMER, 0);
 629 }
 630
 631 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 632  * before the DMA address you give it.  So we allocate 30 more bytes
 633  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 634  * point the chip at 30 bytes past where the rx_header will go.
 635  */
 636 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 637 {
 638         struct dma_desc *dp;
 639         struct ring_info *src_map, *map;
 640         struct rx_header *rh;
 641         struct sk_buff *skb;
 642         dma_addr_t mapping;
 643         int dest_idx;
 644         u32 ctrl;
 645
 646         src_map = NULL;
 647         if (src_idx >= 0)
 648                 src_map = &bp->rx_buffers[src_idx];
 649         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 650         map = &bp->rx_buffers[dest_idx];
 651         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
 652         if (skb == NULL)
 653                 return -ENOMEM;
 654
 655         mapping = pci_map_single(bp->pdev, skb->data,
 656                                  RX_PKT_BUF_SZ,
 657                                  PCI_DMA_FROMDEVICE);
 658
 659         /* Hardware bug work-around, the chip is unable to do PCI DMA
 660            to/from anything above 1GB :-( */
 661         if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
 662                 /* Sigh... */
 663                 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 664                 dev_kfree_skb_any(skb);
 665                 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
 666                 if (skb == NULL)
 667                         return -ENOMEM;
 668                 mapping = pci_map_single(bp->pdev, skb->data,
 669                                          RX_PKT_BUF_SZ,
 670                                          PCI_DMA_FROMDEVICE);
 671                 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
 672                         pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 673                         dev_kfree_skb_any(skb);
 674                         return -ENOMEM;
 675                 }
 676         }
 677
 678         skb->dev = bp->dev;
 679         skb_reserve(skb, bp->rx_offset);
 680
 681         rh = (struct rx_header *)
 682                 (skb->data - bp->rx_offset);
 683         rh->len = 0;
 684         rh->flags = 0;
 685
 686         map->skb = skb;
 687         pci_unmap_addr_set(map, mapping, mapping);
 688
 689         if (src_map != NULL)
 690                 src_map->skb = NULL;
 691
 692         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
 693         if (dest_idx == (B44_RX_RING_SIZE - 1))
 694                 ctrl |= DESC_CTRL_EOT;
 695
 696         dp = &bp->rx_ring[dest_idx];
 697         dp->ctrl = cpu_to_le32(ctrl);
 698         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 699
 700         if (bp->flags & B44_FLAG_RX_RING_HACK)
 701                 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 702                                              dest_idx * sizeof(dp),
 703                                              DMA_BIDIRECTIONAL);
 704
 705         return RX_PKT_BUF_SZ;
 706 }
 707
 708 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 709 {
 710         struct dma_desc *src_desc, *dest_desc;
 711         struct ring_info *src_map, *dest_map;
 712         struct rx_header *rh;
 713         int dest_idx;
 714         u32 ctrl;
 715
 716         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 717         dest_desc = &bp->rx_ring[dest_idx];
 718         dest_map = &bp->rx_buffers[dest_idx];
 719         src_desc = &bp->rx_ring[src_idx];
 720         src_map = &bp->rx_buffers[src_idx];
 721
 722         dest_map->skb = src_map->skb;
 723         rh = (struct rx_header *) src_map->skb->data;
 724         rh->len = 0;
 725         rh->flags = 0;
 726         pci_unmap_addr_set(dest_map, mapping,
 727                            pci_unmap_addr(src_map, mapping));
 728
 729         if (bp->flags & B44_FLAG_RX_RING_HACK)
 730                 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
 731                                           src_idx * sizeof(src_desc),
 732                                           DMA_BIDIRECTIONAL);
 733
 734         ctrl = src_desc->ctrl;
 735         if (dest_idx == (B44_RX_RING_SIZE - 1))
 736                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 737         else
 738                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 739
 740         dest_desc->ctrl = ctrl;
 741         dest_desc->addr = src_desc->addr;
 742
 743         src_map->skb = NULL;
 744
 745         if (bp->flags & B44_FLAG_RX_RING_HACK)
 746                 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 747                                              dest_idx * sizeof(dest_desc),
 748                                              DMA_BIDIRECTIONAL);
 749
 750         pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
 751                                        RX_PKT_BUF_SZ,
 752                                        PCI_DMA_FROMDEVICE);
 753 }
 754
 755 static int b44_rx(struct b44 *bp, int budget)
 756 {
 757         int received;
 758         u32 cons, prod;
 759
 760         received = 0;
 761         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 762         prod /= sizeof(struct dma_desc);
 763         cons = bp->rx_cons;
 764
 765         while (cons != prod && budget > 0) {
 766                 struct ring_info *rp = &bp->rx_buffers[cons];
 767                 struct sk_buff *skb = rp->skb;
 768                 dma_addr_t map = pci_unmap_addr(rp, mapping);
 769                 struct rx_header *rh;
 770                 u16 len;
 771
 772                 pci_dma_sync_single_for_cpu(bp->pdev, map,
 773                                             RX_PKT_BUF_SZ,
 774                                             PCI_DMA_FROMDEVICE);
 775                 rh = (struct rx_header *) skb->data;
 776                 len = cpu_to_le16(rh->len);
 777                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
 778                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 779                 drop_it:
 780                         b44_recycle_rx(bp, cons, bp->rx_prod);
 781                 drop_it_no_recycle:
 782                         bp->stats.rx_dropped++;
 783                         goto next_pkt;
 784                 }
 785
 786                 if (len == 0) {
 787                         int i = 0;
 788
 789                         do {
 790                                 udelay(2);
 791                                 barrier();
 792                                 len = cpu_to_le16(rh->len);
 793                         } while (len == 0 && i++ < 5);
 794                         if (len == 0)
 795                                 goto drop_it;
 796                 }
 797
 798                 /* Omit CRC. */
 799                 len -= 4;
 800
 801                 if (len > RX_COPY_THRESHOLD) {
 802                         int skb_size;
 803                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 804                         if (skb_size < 0)
 805                                 goto drop_it;
 806                         pci_unmap_single(bp->pdev, map,
 807                                          skb_size, PCI_DMA_FROMDEVICE);
 808                         /* Leave out rx_header */
 809                         skb_put(skb, len+bp->rx_offset);
 810                         skb_pull(skb,bp->rx_offset);
 811                 } else {
 812                         struct sk_buff *copy_skb;
 813
 814                         b44_recycle_rx(bp, cons, bp->rx_prod);
 815                         copy_skb = dev_alloc_skb(len + 2);
 816                         if (copy_skb == NULL)
 817                                 goto drop_it_no_recycle;
 818
 819                         copy_skb->dev = bp->dev;
 820                         skb_reserve(copy_skb, 2);
 821                         skb_put(copy_skb, len);
 822                         /* DMA sync done above, copy just the actual packet */
 823                         memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
 824
 825                         skb = copy_skb;
 826                 }
 827                 skb->ip_summed = CHECKSUM_NONE;
 828                 skb->protocol = eth_type_trans(skb, bp->dev);
 829                 netif_receive_skb(skb);
 830                 bp->dev->last_rx = jiffies;
 831                 received++;
 832                 budget--;
 833         next_pkt:
 834                 bp->rx_prod = (bp->rx_prod + 1) &
 835                         (B44_RX_RING_SIZE - 1);
 836                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 837         }
 838
 839         bp->rx_cons = cons;
 840         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 841
 842         return received;
 843 }
 844
 845 static int b44_poll(struct net_device *netdev, int *budget)
 846 {
 847         struct b44 *bp = netdev_priv(netdev);
 848         int done;
 849
 850         spin_lock_irq(&bp->lock);
 851
 852         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 853                 /* spin_lock(&bp->tx_lock); */
 854                 b44_tx(bp);
 855                 /* spin_unlock(&bp->tx_lock); */
 856         }
 857         spin_unlock_irq(&bp->lock);
 858
 859         done = 1;
 860         if (bp->istat & ISTAT_RX) {
 861                 int orig_budget = *budget;
 862                 int work_done;
 863
 864                 if (orig_budget > netdev->quota)
 865                         orig_budget = netdev->quota;
 866
 867                 work_done = b44_rx(bp, orig_budget);
 868
 869                 *budget -= work_done;
 870                 netdev->quota -= work_done;
 871
 872                 if (work_done >= orig_budget)
 873                         done = 0;
 874         }
 875
 876         if (bp->istat & ISTAT_ERRORS) {
 877                 spin_lock_irq(&bp->lock);
 878                 b44_halt(bp);
 879                 b44_init_rings(bp);
 880                 b44_init_hw(bp);
 881                 netif_wake_queue(bp->dev);
 882                 spin_unlock_irq(&bp->lock);
 883                 done = 1;
 884         }
 885
 886         if (done) {
 887                 netif_rx_complete(netdev);
 888                 b44_enable_ints(bp);
 889         }
 890
 891         return (done ? 0 : 1);
 892 }
 893
 894 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 895 {
 896         struct net_device *dev = dev_id;
 897         struct b44 *bp = netdev_priv(dev);
 898         u32 istat, imask;
 899         int handled = 0;
 900
 901         spin_lock(&bp->lock);
 902
 903         istat = br32(bp, B44_ISTAT);
 904         imask = br32(bp, B44_IMASK);
 905
 906         /* ??? What the fuck is the purpose of the interrupt mask
 907          * ??? register if we have to mask it out by hand anyways?
 908          */
 909         istat &= imask;
 910         if (istat) {
 911                 handled = 1;
 912
 913                 if (unlikely(!netif_running(dev))) {
 914                         printk(KERN_INFO "%s: late interrupt.\n", dev->name);
 915                         goto irq_ack;
 916                 }
 917
 918                 if (netif_rx_schedule_prep(dev)) {
 919                         /* NOTE: These writes are posted by the readback of
 920                          *       the ISTAT register below.
 921                          */
 922                         bp->istat = istat;
 923                         __b44_disable_ints(bp);
 924                         __netif_rx_schedule(dev);
 925                 } else {
 926                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 927                                dev->name);
 928                 }
 929
 930 irq_ack:
 931                 bw32(bp, B44_ISTAT, istat);
 932                 br32(bp, B44_ISTAT);
 933         }
 934         spin_unlock(&bp->lock);
 935         return IRQ_RETVAL(handled);
 936 }
 937
 938 static void b44_tx_timeout(struct net_device *dev)
 939 {
 940         struct b44 *bp = netdev_priv(dev);
 941
 942         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 943                dev->name);
 944
 945         spin_lock_irq(&bp->lock);
 946
 947         b44_halt(bp);
 948         b44_init_rings(bp);
 949         b44_init_hw(bp);
 950
 951         spin_unlock_irq(&bp->lock);
 952
 953         b44_enable_ints(bp);
 954
 955         netif_wake_queue(dev);
 956 }
 957
 958 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 959 {
 960         struct b44 *bp = netdev_priv(dev);
 961         struct sk_buff *bounce_skb;
 962         int rc = NETDEV_TX_OK;
 963         dma_addr_t mapping;
 964         u32 len, entry, ctrl;
 965
 966         len = skb->len;
 967         spin_lock_irq(&bp->lock);
 968
 969         /* This is a hard error, log it. */
 970         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 971                 netif_stop_queue(dev);
 972                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 973                        dev->name);
 974                 goto err_out;
 975         }
 976
 977         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
 978         if (mapping + len > B44_DMA_MASK) {
 979                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 980                 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
 981
 982                 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
 983                                              GFP_ATOMIC|GFP_DMA);
 984                 if (!bounce_skb)
 985                         goto err_out;
 986
 987                 mapping = pci_map_single(bp->pdev, bounce_skb->data,
 988                                          len, PCI_DMA_TODEVICE);
 989                 if (mapping + len > B44_DMA_MASK) {
 990                         pci_unmap_single(bp->pdev, mapping,
 991                                          len, PCI_DMA_TODEVICE);
 992                         dev_kfree_skb_any(bounce_skb);
 993                         goto err_out;
 994                 }
 995
 996                 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
 997                 dev_kfree_skb_any(skb);
 998                 skb = bounce_skb;
 999         }
1000
1001         entry = bp->tx_prod;
1002         bp->tx_buffers[entry].skb = skb;
1003         pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
1004
1005         ctrl  = (len & DESC_CTRL_LEN);
1006         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1007         if (entry == (B44_TX_RING_SIZE - 1))
1008                 ctrl |= DESC_CTRL_EOT;
1009
1010         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1011         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1012
1013         if (bp->flags & B44_FLAG_TX_RING_HACK)
1014                 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1015                                              entry * sizeof(bp->tx_ring[0]),
1016                                              DMA_TO_DEVICE);
1017
1018         entry = NEXT_TX(entry);
1019
1020         bp->tx_prod = entry;
1021
1022         wmb();
1023
1024         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1025         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1026                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1027         if (bp->flags & B44_FLAG_REORDER_BUG)
1028                 br32(bp, B44_DMATX_PTR);
1029
1030         if (TX_BUFFS_AVAIL(bp) < 1)
1031                 netif_stop_queue(dev);
1032
1033         dev->trans_start = jiffies;
1034
1035 out_unlock:
1036         spin_unlock_irq(&bp->lock);
1037
1038         return rc;
1039
1040 err_out:
1041         rc = NETDEV_TX_BUSY;
1042         goto out_unlock;
1043 }
1044
1045 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1046 {
1047         struct b44 *bp = netdev_priv(dev);
1048
1049         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1050                 return -EINVAL;
1051
1052         if (!netif_running(dev)) {
1053                 /* We'll just catch it later when the
1054                  * device is up'd.
1055                  */
1056                 dev->mtu = new_mtu;
1057                 return 0;
1058         }
1059
1060         spin_lock_irq(&bp->lock);
1061         b44_halt(bp);
1062         dev->mtu = new_mtu;
1063         b44_init_rings(bp);
1064         b44_init_hw(bp);
1065         spin_unlock_irq(&bp->lock);
1066
1067         b44_enable_ints(bp);
1068
1069         return 0;
1070 }
1071
1072 /* Free up pending packets in all rx/tx rings.
1073  *
1074  * The chip has been shut down and the driver detached from
1075  * the networking, so no interrupts or new tx packets will
1076  * end up in the driver.  bp->lock is not held and we are not
1077  * in an interrupt context and thus may sleep.
1078  */
1079 static void b44_free_rings(struct b44 *bp)
1080 {
1081         struct ring_info *rp;
1082         int i;
1083
1084         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1085                 rp = &bp->rx_buffers[i];
1086
1087                 if (rp->skb == NULL)
1088                         continue;
1089                 pci_unmap_single(bp->pdev,
1090                                  pci_unmap_addr(rp, mapping),
1091                                  RX_PKT_BUF_SZ,
1092                                  PCI_DMA_FROMDEVICE);
1093                 dev_kfree_skb_any(rp->skb);
1094                 rp->skb = NULL;
1095         }
1096
1097         /* XXX needs changes once NETIF_F_SG is set... */
1098         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1099                 rp = &bp->tx_buffers[i];
1100
1101                 if (rp->skb == NULL)
1102                         continue;
1103                 pci_unmap_single(bp->pdev,
1104                                  pci_unmap_addr(rp, mapping),
1105                                  rp->skb->len,
1106                                  PCI_DMA_TODEVICE);
1107                 dev_kfree_skb_any(rp->skb);
1108                 rp->skb = NULL;
1109         }
1110 }
1111
1112 /* Initialize tx/rx rings for packet processing.
1113  *
1114  * The chip has been shut down and the driver detached from
1115  * the networking, so no interrupts or new tx packets will
1116  * end up in the driver.
1117  */
1118 static void b44_init_rings(struct b44 *bp)
1119 {
1120         int i;
1121
1122         b44_free_rings(bp);
1123
1124         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1125         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1126
1127         if (bp->flags & B44_FLAG_RX_RING_HACK)
1128                 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1129                                            DMA_TABLE_BYTES,
1130                                            PCI_DMA_BIDIRECTIONAL);
1131
1132         if (bp->flags & B44_FLAG_TX_RING_HACK)
1133                 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1134                                            DMA_TABLE_BYTES,
1135                                            PCI_DMA_TODEVICE);
1136
1137         for (i = 0; i < bp->rx_pending; i++) {
1138                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1139                         break;
1140         }
1141 }
1142
1143 /*
1144  * Must not be invoked with interrupt sources disabled and
1145  * the hardware shutdown down.
1146  */
1147 static void b44_free_consistent(struct b44 *bp)
1148 {
1149         kfree(bp->rx_buffers);
1150         bp->rx_buffers = NULL;
1151         kfree(bp->tx_buffers);
1152         bp->tx_buffers = NULL;
1153         if (bp->rx_ring) {
1154                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1155                         dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1156                                          DMA_TABLE_BYTES,
1157                                          DMA_BIDIRECTIONAL);
1158                         kfree(bp->rx_ring);
1159                 } else
1160                         pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1161                                             bp->rx_ring, bp->rx_ring_dma);
1162                 bp->rx_ring = NULL;
1163                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1164         }
1165         if (bp->tx_ring) {
1166                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1167                         dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1168                                          DMA_TABLE_BYTES,
1169                                          DMA_TO_DEVICE);
1170                         kfree(bp->tx_ring);
1171                 } else
1172                         pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1173                                             bp->tx_ring, bp->tx_ring_dma);
1174                 bp->tx_ring = NULL;
1175                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1176         }
1177 }
1178
1179 /*
1180  * Must not be invoked with interrupt sources disabled and
1181  * the hardware shutdown down.  Can sleep.
1182  */
1183 static int b44_alloc_consistent(struct b44 *bp)
1184 {
1185         int size;
1186
1187         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1188         bp->rx_buffers = kzalloc(size, GFP_KERNEL);
1189         if (!bp->rx_buffers)
1190                 goto out_err;
1191
1192         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1193         bp->tx_buffers = kzalloc(size, GFP_KERNEL);
1194         if (!bp->tx_buffers)
1195                 goto out_err;
1196
1197         size = DMA_TABLE_BYTES;
1198         bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1199         if (!bp->rx_ring) {
1200                 /* Allocation may have failed due to pci_alloc_consistent
1201                    insisting on use of GFP_DMA, which is more restrictive
1202                    than necessary...  */
1203                 struct dma_desc *rx_ring;
1204                 dma_addr_t rx_ring_dma;
1205
1206                 rx_ring = kzalloc(size, GFP_KERNEL);
1207                 if (!rx_ring)
1208                         goto out_err;
1209
1210                 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1211                                              DMA_TABLE_BYTES,
1212                                              DMA_BIDIRECTIONAL);
1213
1214                 if (rx_ring_dma + size > B44_DMA_MASK) {
1215                         kfree(rx_ring);
1216                         goto out_err;
1217                 }
1218
1219                 bp->rx_ring = rx_ring;
1220                 bp->rx_ring_dma = rx_ring_dma;
1221                 bp->flags |= B44_FLAG_RX_RING_HACK;
1222         }
1223
1224         bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1225         if (!bp->tx_ring) {
1226                 /* Allocation may have failed due to pci_alloc_consistent
1227                    insisting on use of GFP_DMA, which is more restrictive
1228                    than necessary...  */
1229                 struct dma_desc *tx_ring;
1230                 dma_addr_t tx_ring_dma;
1231
1232                 tx_ring = kzalloc(size, GFP_KERNEL);
1233                 if (!tx_ring)
1234                         goto out_err;
1235
1236                 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1237                                              DMA_TABLE_BYTES,
1238                                              DMA_TO_DEVICE);
1239
1240                 if (tx_ring_dma + size > B44_DMA_MASK) {
1241                         kfree(tx_ring);
1242                         goto out_err;
1243                 }
1244
1245                 bp->tx_ring = tx_ring;
1246                 bp->tx_ring_dma = tx_ring_dma;
1247                 bp->flags |= B44_FLAG_TX_RING_HACK;
1248         }
1249
1250         return 0;
1251
1252 out_err:
1253         b44_free_consistent(bp);
1254         return -ENOMEM;
1255 }
1256
1257 /* bp->lock is held. */
1258 static void b44_clear_stats(struct b44 *bp)
1259 {
1260         unsigned long reg;
1261
1262         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1263         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1264                 br32(bp, reg);
1265         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1266                 br32(bp, reg);
1267 }
1268
1269 /* bp->lock is held. */
1270 static void b44_chip_reset(struct b44 *bp)
1271 {
1272         if (ssb_is_core_up(bp)) {
1273                 bw32(bp, B44_RCV_LAZY, 0);
1274                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1275                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1276                 bw32(bp, B44_DMATX_CTRL, 0);
1277                 bp->tx_prod = bp->tx_cons = 0;
1278                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1279                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1280                                      100, 0);
1281                 }
1282                 bw32(bp, B44_DMARX_CTRL, 0);
1283                 bp->rx_prod = bp->rx_cons = 0;
1284         } else {
1285                 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1286                                    SBINTVEC_ENET0 :
1287                                    SBINTVEC_ENET1));
1288         }
1289
1290         ssb_core_reset(bp);
1291
1292         b44_clear_stats(bp);
1293
1294         /* Make PHY accessible. */
1295         bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1296                              (0x0d & MDIO_CTRL_MAXF_MASK)));
1297         br32(bp, B44_MDIO_CTRL);
1298
1299         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1300                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1301                 br32(bp, B44_ENET_CTRL);
1302                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1303         } else {
1304                 u32 val = br32(bp, B44_DEVCTRL);
1305
1306                 if (val & DEVCTRL_EPR) {
1307                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1308                         br32(bp, B44_DEVCTRL);
1309                         udelay(100);
1310                 }
1311                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1312         }
1313 }
1314
1315 /* bp->lock is held. */
1316 static void b44_halt(struct b44 *bp)
1317 {
1318         b44_disable_ints(bp);
1319         b44_chip_reset(bp);
1320 }
1321
1322 /* bp->lock is held. */
1323 static void __b44_set_mac_addr(struct b44 *bp)
1324 {
1325         bw32(bp, B44_CAM_CTRL, 0);
1326         if (!(bp->dev->flags & IFF_PROMISC)) {
1327                 u32 val;
1328
1329                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1330                 val = br32(bp, B44_CAM_CTRL);
1331                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1332         }
1333 }
1334
1335 static int b44_set_mac_addr(struct net_device *dev, void *p)
1336 {
1337         struct b44 *bp = netdev_priv(dev);
1338         struct sockaddr *addr = p;
1339
1340         if (netif_running(dev))
1341                 return -EBUSY;
1342
1343         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1344
1345         spin_lock_irq(&bp->lock);
1346         __b44_set_mac_addr(bp);
1347         spin_unlock_irq(&bp->lock);
1348
1349         return 0;
1350 }
1351
1352 /* Called at device open time to get the chip ready for
1353  * packet processing.  Invoked with bp->lock held.
1354  */
1355 static void __b44_set_rx_mode(struct net_device *);
1356 static void b44_init_hw(struct b44 *bp)
1357 {
1358         u32 val;
1359
1360         b44_chip_reset(bp);
1361         b44_phy_reset(bp);
1362         b44_setup_phy(bp);
1363
1364         /* Enable CRC32, set proper LED modes and power on PHY */
1365         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1366         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1367
1368         /* This sets the MAC address too.  */
1369         __b44_set_rx_mode(bp->dev);
1370
1371         /* MTU + eth header + possible VLAN tag + struct rx_header */
1372         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1373         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1374
1375         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1376         bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1377         bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1378         bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1379                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1380         bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1381
1382         bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1383         bp->rx_prod = bp->rx_pending;
1384
1385         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1386
1387         val = br32(bp, B44_ENET_CTRL);
1388         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1389 }
1390
1391 static int b44_open(struct net_device *dev)
1392 {
1393         struct b44 *bp = netdev_priv(dev);
1394         int err;
1395
1396         err = b44_alloc_consistent(bp);
1397         if (err)
1398                 goto out;
1399
1400         b44_init_rings(bp);
1401         b44_init_hw(bp);
1402
1403         netif_carrier_off(dev);
1404         b44_check_phy(bp);
1405
1406         err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1407         if (unlikely(err < 0)) {
1408                 b44_chip_reset(bp);
1409                 b44_free_rings(bp);
1410                 b44_free_consistent(bp);
1411                 goto out;
1412         }
1413
1414         init_timer(&bp->timer);
1415         bp->timer.expires = jiffies + HZ;
1416         bp->timer.data = (unsigned long) bp;
1417         bp->timer.function = b44_timer;
1418         add_timer(&bp->timer);
1419
1420         b44_enable_ints(bp);
1421 out:
1422         return err;
1423 }
1424
1425 #if 0
1426 /*static*/ void b44_dump_state(struct b44 *bp)
1427 {
1428         u32 val32, val32_2, val32_3, val32_4, val32_5;
1429         u16 val16;
1430
1431         pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1432         printk("DEBUG: PCI status [%04x] \n", val16);
1433
1434 }
1435 #endif
1436
1437 #ifdef CONFIG_NET_POLL_CONTROLLER
1438 /*
1439  * Polling receive - used by netconsole and other diagnostic tools
1440  * to allow network i/o with interrupts disabled.
1441  */
1442 static void b44_poll_controller(struct net_device *dev)
1443 {
1444         disable_irq(dev->irq);
1445         b44_interrupt(dev->irq, dev, NULL);
1446         enable_irq(dev->irq);
1447 }
1448 #endif
1449
1450 static int b44_close(struct net_device *dev)
1451 {
1452         struct b44 *bp = netdev_priv(dev);
1453
1454         netif_stop_queue(dev);
1455
1456         netif_poll_disable(dev);
1457
1458         del_timer_sync(&bp->timer);
1459
1460         spin_lock_irq(&bp->lock);
1461
1462 #if 0
1463         b44_dump_state(bp);
1464 #endif
1465         b44_halt(bp);
1466         b44_free_rings(bp);
1467         netif_carrier_off(bp->dev);
1468
1469         spin_unlock_irq(&bp->lock);
1470
1471         free_irq(dev->irq, dev);
1472
1473         netif_poll_enable(dev);
1474
1475         b44_free_consistent(bp);
1476
1477         return 0;
1478 }
1479
1480 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1481 {
1482         struct b44 *bp = netdev_priv(dev);
1483         struct net_device_stats *nstat = &bp->stats;
1484         struct b44_hw_stats *hwstat = &bp->hw_stats;
1485
1486         /* Convert HW stats into netdevice stats. */
1487         nstat->rx_packets = hwstat->rx_pkts;
1488         nstat->tx_packets = hwstat->tx_pkts;
1489         nstat->rx_bytes   = hwstat->rx_octets;
1490         nstat->tx_bytes   = hwstat->tx_octets;
1491         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1492                              hwstat->tx_oversize_pkts +
1493                              hwstat->tx_underruns +
1494                              hwstat->tx_excessive_cols +
1495                              hwstat->tx_late_cols);
1496         nstat->multicast  = hwstat->tx_multicast_pkts;
1497         nstat->collisions = hwstat->tx_total_cols;
1498
1499         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1500                                    hwstat->rx_undersize);
1501         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1502         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1503         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1504         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1505                                    hwstat->rx_oversize_pkts +
1506                                    hwstat->rx_missed_pkts +
1507                                    hwstat->rx_crc_align_errs +
1508                                    hwstat->rx_undersize +
1509                                    hwstat->rx_crc_errs +
1510                                    hwstat->rx_align_errs +
1511                                    hwstat->rx_symbol_errs);
1512
1513         nstat->tx_aborted_errors = hwstat->tx_underruns;
1514 #if 0
1515         /* Carrier lost counter seems to be broken for some devices */
1516         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1517 #endif
1518
1519         return nstat;
1520 }
1521
1522 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1523 {
1524         struct dev_mc_list *mclist;
1525         int i, num_ents;
1526
1527         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1528         mclist = dev->mc_list;
1529         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1530                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1531         }
1532         return i+1;
1533 }
1534
1535 static void __b44_set_rx_mode(struct net_device *dev)
1536 {
1537         struct b44 *bp = netdev_priv(dev);
1538         u32 val;
1539
1540         val = br32(bp, B44_RXCONFIG);
1541         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1542         if (dev->flags & IFF_PROMISC) {
1543                 val |= RXCONFIG_PROMISC;
1544                 bw32(bp, B44_RXCONFIG, val);
1545         } else {
1546                 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1547                 int i = 0;
1548
1549                 __b44_set_mac_addr(bp);
1550
1551                 if (dev->flags & IFF_ALLMULTI)
1552                         val |= RXCONFIG_ALLMULTI;
1553                 else
1554                         i = __b44_load_mcast(bp, dev);
1555
1556                 for (; i < 64; i++) {
1557                         __b44_cam_write(bp, zero, i);
1558                 }
1559                 bw32(bp, B44_RXCONFIG, val);
1560                 val = br32(bp, B44_CAM_CTRL);
1561                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1562         }
1563 }
1564
1565 static void b44_set_rx_mode(struct net_device *dev)
1566 {
1567         struct b44 *bp = netdev_priv(dev);
1568
1569         spin_lock_irq(&bp->lock);
1570         __b44_set_rx_mode(dev);
1571         spin_unlock_irq(&bp->lock);
1572 }
1573
1574 static u32 b44_get_msglevel(struct net_device *dev)
1575 {
1576         struct b44 *bp = netdev_priv(dev);
1577         return bp->msg_enable;
1578 }
1579
1580 static void b44_set_msglevel(struct net_device *dev, u32 value)
1581 {
1582         struct b44 *bp = netdev_priv(dev);
1583         bp->msg_enable = value;
1584 }
1585
1586 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1587 {
1588         struct b44 *bp = netdev_priv(dev);
1589         struct pci_dev *pci_dev = bp->pdev;
1590
1591         strcpy (info->driver, DRV_MODULE_NAME);
1592         strcpy (info->version, DRV_MODULE_VERSION);
1593         strcpy (info->bus_info, pci_name(pci_dev));
1594 }
1595
1596 static int b44_nway_reset(struct net_device *dev)
1597 {
1598         struct b44 *bp = netdev_priv(dev);
1599         u32 bmcr;
1600         int r;
1601
1602         spin_lock_irq(&bp->lock);
1603         b44_readphy(bp, MII_BMCR, &bmcr);
1604         b44_readphy(bp, MII_BMCR, &bmcr);
1605         r = -EINVAL;
1606         if (bmcr & BMCR_ANENABLE) {
1607                 b44_writephy(bp, MII_BMCR,
1608                              bmcr | BMCR_ANRESTART);
1609                 r = 0;
1610         }
1611         spin_unlock_irq(&bp->lock);
1612
1613         return r;
1614 }
1615
1616 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1617 {
1618         struct b44 *bp = netdev_priv(dev);
1619
1620         if (!netif_running(dev))
1621                 return -EAGAIN;
1622         cmd->supported = (SUPPORTED_Autoneg);
1623         cmd->supported |= (SUPPORTED_100baseT_Half |
1624                           SUPPORTED_100baseT_Full |
1625                           SUPPORTED_10baseT_Half |
1626                           SUPPORTED_10baseT_Full |
1627                           SUPPORTED_MII);
1628
1629         cmd->advertising = 0;
1630         if (bp->flags & B44_FLAG_ADV_10HALF)
1631                 cmd->advertising |= ADVERTISED_10baseT_Half;
1632         if (bp->flags & B44_FLAG_ADV_10FULL)
1633                 cmd->advertising |= ADVERTISED_10baseT_Full;
1634         if (bp->flags & B44_FLAG_ADV_100HALF)
1635                 cmd->advertising |= ADVERTISED_100baseT_Half;
1636         if (bp->flags & B44_FLAG_ADV_100FULL)
1637                 cmd->advertising |= ADVERTISED_100baseT_Full;
1638         cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1639         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1640                 SPEED_100 : SPEED_10;
1641         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1642                 DUPLEX_FULL : DUPLEX_HALF;
1643         cmd->port = 0;
1644         cmd->phy_address = bp->phy_addr;
1645         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1646                 XCVR_INTERNAL : XCVR_EXTERNAL;
1647         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1648                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1649         cmd->maxtxpkt = 0;
1650         cmd->maxrxpkt = 0;
1651         return 0;
1652 }
1653
1654 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1655 {
1656         struct b44 *bp = netdev_priv(dev);
1657
1658         if (!netif_running(dev))
1659                 return -EAGAIN;
1660
1661         /* We do not support gigabit. */
1662         if (cmd->autoneg == AUTONEG_ENABLE) {
1663                 if (cmd->advertising &
1664                     (ADVERTISED_1000baseT_Half |
1665                      ADVERTISED_1000baseT_Full))
1666                         return -EINVAL;
1667         } else if ((cmd->speed != SPEED_100 &&
1668                     cmd->speed != SPEED_10) ||
1669                    (cmd->duplex != DUPLEX_HALF &&
1670                     cmd->duplex != DUPLEX_FULL)) {
1671                         return -EINVAL;
1672         }
1673
1674         spin_lock_irq(&bp->lock);
1675
1676         if (cmd->autoneg == AUTONEG_ENABLE) {
1677                 bp->flags &= ~B44_FLAG_FORCE_LINK;
1678                 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1679                                B44_FLAG_ADV_10FULL |
1680                                B44_FLAG_ADV_100HALF |
1681                                B44_FLAG_ADV_100FULL);
1682                 if (cmd->advertising & ADVERTISE_10HALF)
1683                         bp->flags |= B44_FLAG_ADV_10HALF;
1684                 if (cmd->advertising & ADVERTISE_10FULL)
1685                         bp->flags |= B44_FLAG_ADV_10FULL;
1686                 if (cmd->advertising & ADVERTISE_100HALF)
1687                         bp->flags |= B44_FLAG_ADV_100HALF;
1688                 if (cmd->advertising & ADVERTISE_100FULL)
1689                         bp->flags |= B44_FLAG_ADV_100FULL;
1690         } else {
1691                 bp->flags |= B44_FLAG_FORCE_LINK;
1692                 if (cmd->speed == SPEED_100)
1693                         bp->flags |= B44_FLAG_100_BASE_T;
1694                 if (cmd->duplex == DUPLEX_FULL)
1695                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1696         }
1697
1698         b44_setup_phy(bp);
1699
1700         spin_unlock_irq(&bp->lock);
1701
1702         return 0;
1703 }
1704
1705 static void b44_get_ringparam(struct net_device *dev,
1706                               struct ethtool_ringparam *ering)
1707 {
1708         struct b44 *bp = netdev_priv(dev);
1709
1710         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1711         ering->rx_pending = bp->rx_pending;
1712
1713         /* XXX ethtool lacks a tx_max_pending, oops... */
1714 }
1715
1716 static int b44_set_ringparam(struct net_device *dev,
1717                              struct ethtool_ringparam *ering)
1718 {
1719         struct b44 *bp = netdev_priv(dev);
1720
1721         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1722             (ering->rx_mini_pending != 0) ||
1723             (ering->rx_jumbo_pending != 0) ||
1724             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1725                 return -EINVAL;
1726
1727         spin_lock_irq(&bp->lock);
1728
1729         bp->rx_pending = ering->rx_pending;
1730         bp->tx_pending = ering->tx_pending;
1731
1732         b44_halt(bp);
1733         b44_init_rings(bp);
1734         b44_init_hw(bp);
1735         netif_wake_queue(bp->dev);
1736         spin_unlock_irq(&bp->lock);
1737
1738         b44_enable_ints(bp);
1739
1740         return 0;
1741 }
1742
1743 static void b44_get_pauseparam(struct net_device *dev,
1744                                 struct ethtool_pauseparam *epause)
1745 {
1746         struct b44 *bp = netdev_priv(dev);
1747
1748         epause->autoneg =
1749                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1750         epause->rx_pause =
1751                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1752         epause->tx_pause =
1753                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1754 }
1755
1756 static int b44_set_pauseparam(struct net_device *dev,
1757                                 struct ethtool_pauseparam *epause)
1758 {
1759         struct b44 *bp = netdev_priv(dev);
1760
1761         spin_lock_irq(&bp->lock);
1762         if (epause->autoneg)
1763                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1764         else
1765                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1766         if (epause->rx_pause)
1767                 bp->flags |= B44_FLAG_RX_PAUSE;
1768         else
1769                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1770         if (epause->tx_pause)
1771                 bp->flags |= B44_FLAG_TX_PAUSE;
1772         else
1773                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1774         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1775                 b44_halt(bp);
1776                 b44_init_rings(bp);
1777                 b44_init_hw(bp);
1778         } else {
1779                 __b44_set_flow_ctrl(bp, bp->flags);
1780         }
1781         spin_unlock_irq(&bp->lock);
1782
1783         b44_enable_ints(bp);
1784
1785         return 0;
1786 }
1787
1788 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1789 {
1790         switch(stringset) {
1791         case ETH_SS_STATS:
1792                 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1793                 break;
1794         }
1795 }
1796
1797 static int b44_get_stats_count(struct net_device *dev)
1798 {
1799         return ARRAY_SIZE(b44_gstrings);
1800 }
1801
1802 static void b44_get_ethtool_stats(struct net_device *dev,
1803                                   struct ethtool_stats *stats, u64 *data)
1804 {
1805         struct b44 *bp = netdev_priv(dev);
1806         u32 *val = &bp->hw_stats.tx_good_octets;
1807         u32 i;
1808
1809         spin_lock_irq(&bp->lock);
1810
1811         b44_stats_update(bp);
1812
1813         for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
1814                 *data++ = *val++;
1815
1816         spin_unlock_irq(&bp->lock);
1817 }
1818
1819 static struct ethtool_ops b44_ethtool_ops = {
1820         .get_drvinfo            = b44_get_drvinfo,
1821         .get_settings           = b44_get_settings,
1822         .set_settings           = b44_set_settings,
1823         .nway_reset             = b44_nway_reset,
1824         .get_link               = ethtool_op_get_link,
1825         .get_ringparam          = b44_get_ringparam,
1826         .set_ringparam          = b44_set_ringparam,
1827         .get_pauseparam         = b44_get_pauseparam,
1828         .set_pauseparam         = b44_set_pauseparam,
1829         .get_msglevel           = b44_get_msglevel,
1830         .set_msglevel           = b44_set_msglevel,
1831         .get_strings            = b44_get_strings,
1832         .get_stats_count        = b44_get_stats_count,
1833         .get_ethtool_stats      = b44_get_ethtool_stats,
1834         .get_perm_addr          = ethtool_op_get_perm_addr,
1835 };
1836
1837 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1838 {
1839         struct mii_ioctl_data *data = if_mii(ifr);
1840         struct b44 *bp = netdev_priv(dev);
1841         int err;
1842
1843         spin_lock_irq(&bp->lock);
1844         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1845         spin_unlock_irq(&bp->lock);
1846
1847         return err;
1848 }
1849
1850 /* Read 128-bytes of EEPROM. */
1851 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1852 {
1853         long i;
1854         u16 *ptr = (u16 *) data;
1855
1856         for (i = 0; i < 128; i += 2)
1857                 ptr[i / 2] = readw(bp->regs + 4096 + i);
1858
1859         return 0;
1860 }
1861
1862 static int __devinit b44_get_invariants(struct b44 *bp)
1863 {
1864         u8 eeprom[128];
1865         int err;
1866
1867         err = b44_read_eeprom(bp, &eeprom[0]);
1868         if (err)
1869                 goto out;
1870
1871         bp->dev->dev_addr[0] = eeprom[79];
1872         bp->dev->dev_addr[1] = eeprom[78];
1873         bp->dev->dev_addr[2] = eeprom[81];
1874         bp->dev->dev_addr[3] = eeprom[80];
1875         bp->dev->dev_addr[4] = eeprom[83];
1876         bp->dev->dev_addr[5] = eeprom[82];
1877         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1878
1879         bp->phy_addr = eeprom[90] & 0x1f;
1880
1881         /* With this, plus the rx_header prepended to the data by the
1882          * hardware, we'll land the ethernet header on a 2-byte boundary.
1883          */
1884         bp->rx_offset = 30;
1885
1886         bp->imask = IMASK_DEF;
1887
1888         bp->core_unit = ssb_core_unit(bp);
1889         bp->dma_offset = SB_PCI_DMA;
1890
1891         /* XXX - really required?
1892            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1893          */
1894 out:
1895         return err;
1896 }
1897
1898 static int __devinit b44_init_one(struct pci_dev *pdev,
1899                                   const struct pci_device_id *ent)
1900 {
1901         static int b44_version_printed = 0;
1902         unsigned long b44reg_base, b44reg_len;
1903         struct net_device *dev;
1904         struct b44 *bp;
1905         int err, i;
1906
1907         if (b44_version_printed++ == 0)
1908                 printk(KERN_INFO "%s", version);
1909
1910         err = pci_enable_device(pdev);
1911         if (err) {
1912                 printk(KERN_ERR PFX "Cannot enable PCI device, "
1913                        "aborting.\n");
1914                 return err;
1915         }
1916
1917         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1918                 printk(KERN_ERR PFX "Cannot find proper PCI device "
1919                        "base address, aborting.\n");
1920                 err = -ENODEV;
1921                 goto err_out_disable_pdev;
1922         }
1923
1924         err = pci_request_regions(pdev, DRV_MODULE_NAME);
1925         if (err) {
1926                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1927                        "aborting.\n");
1928                 goto err_out_disable_pdev;
1929         }
1930
1931         pci_set_master(pdev);
1932
1933         err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1934         if (err) {
1935                 printk(KERN_ERR PFX "No usable DMA configuration, "
1936                        "aborting.\n");
1937                 goto err_out_free_res;
1938         }
1939
1940         err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1941         if (err) {
1942                 printk(KERN_ERR PFX "No usable DMA configuration, "
1943                        "aborting.\n");
1944                 goto err_out_free_res;
1945         }
1946
1947         b44reg_base = pci_resource_start(pdev, 0);
1948         b44reg_len = pci_resource_len(pdev, 0);
1949
1950         dev = alloc_etherdev(sizeof(*bp));
1951         if (!dev) {
1952                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1953                 err = -ENOMEM;
1954                 goto err_out_free_res;
1955         }
1956
1957         SET_MODULE_OWNER(dev);
1958         SET_NETDEV_DEV(dev,&pdev->dev);
1959
1960         /* No interesting netdevice features in this card... */
1961         dev->features |= 0;
1962
1963         bp = netdev_priv(dev);
1964         bp->pdev = pdev;
1965         bp->dev = dev;
1966
1967         bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1968
1969         spin_lock_init(&bp->lock);
1970
1971         bp->regs = ioremap(b44reg_base, b44reg_len);
1972         if (bp->regs == 0UL) {
1973                 printk(KERN_ERR PFX "Cannot map device registers, "
1974                        "aborting.\n");
1975                 err = -ENOMEM;
1976                 goto err_out_free_dev;
1977         }
1978
1979         bp->rx_pending = B44_DEF_RX_RING_PENDING;
1980         bp->tx_pending = B44_DEF_TX_RING_PENDING;
1981
1982         dev->open = b44_open;
1983         dev->stop = b44_close;
1984         dev->hard_start_xmit = b44_start_xmit;
1985         dev->get_stats = b44_get_stats;
1986         dev->set_multicast_list = b44_set_rx_mode;
1987         dev->set_mac_address = b44_set_mac_addr;
1988         dev->do_ioctl = b44_ioctl;
1989         dev->tx_timeout = b44_tx_timeout;
1990         dev->poll = b44_poll;
1991         dev->weight = 64;
1992         dev->watchdog_timeo = B44_TX_TIMEOUT;
1993 #ifdef CONFIG_NET_POLL_CONTROLLER
1994         dev->poll_controller = b44_poll_controller;
1995 #endif
1996         dev->change_mtu = b44_change_mtu;
1997         dev->irq = pdev->irq;
1998         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1999
2000         err = b44_get_invariants(bp);
2001         if (err) {
2002                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
2003                        "aborting.\n");
2004                 goto err_out_iounmap;
2005         }
2006
2007         bp->mii_if.dev = dev;
2008         bp->mii_if.mdio_read = b44_mii_read;
2009         bp->mii_if.mdio_write = b44_mii_write;
2010         bp->mii_if.phy_id = bp->phy_addr;
2011         bp->mii_if.phy_id_mask = 0x1f;
2012         bp->mii_if.reg_num_mask = 0x1f;
2013
2014         /* By default, advertise all speed/duplex settings. */
2015         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2016                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2017
2018         /* By default, auto-negotiate PAUSE. */
2019         bp->flags |= B44_FLAG_PAUSE_AUTO;
2020
2021         err = register_netdev(dev);
2022         if (err) {
2023                 printk(KERN_ERR PFX "Cannot register net device, "
2024                        "aborting.\n");
2025                 goto err_out_iounmap;
2026         }
2027
2028         pci_set_drvdata(pdev, dev);
2029
2030         pci_save_state(bp->pdev);
2031
2032         printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
2033         for (i = 0; i < 6; i++)
2034                 printk("%2.2x%c", dev->dev_addr[i],
2035                        i == 5 ? '\n' : ':');
2036
2037         return 0;
2038
2039 err_out_iounmap:
2040         iounmap(bp->regs);
2041
2042 err_out_free_dev:
2043         free_netdev(dev);
2044
2045 err_out_free_res:
2046         pci_release_regions(pdev);
2047
2048 err_out_disable_pdev:
2049         pci_disable_device(pdev);
2050         pci_set_drvdata(pdev, NULL);
2051         return err;
2052 }
2053
2054 static void __devexit b44_remove_one(struct pci_dev *pdev)
2055 {
2056         struct net_device *dev = pci_get_drvdata(pdev);
2057         struct b44 *bp = netdev_priv(dev);
2058
2059         unregister_netdev(dev);
2060         iounmap(bp->regs);
2061         free_netdev(dev);
2062         pci_release_regions(pdev);
2063         pci_disable_device(pdev);
2064         pci_set_drvdata(pdev, NULL);
2065 }
2066
2067 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2068 {
2069         struct net_device *dev = pci_get_drvdata(pdev);
2070         struct b44 *bp = netdev_priv(dev);
2071
2072         if (!netif_running(dev))
2073                  return 0;
2074
2075         del_timer_sync(&bp->timer);
2076
2077         spin_lock_irq(&bp->lock);
2078
2079         b44_halt(bp);
2080         netif_carrier_off(bp->dev);
2081         netif_device_detach(bp->dev);
2082         b44_free_rings(bp);
2083
2084         spin_unlock_irq(&bp->lock);
2085
2086         free_irq(dev->irq, dev);
2087         pci_disable_device(pdev);
2088         return 0;
2089 }
2090
2091 static int b44_resume(struct pci_dev *pdev)
2092 {
2093         struct net_device *dev = pci_get_drvdata(pdev);
2094         struct b44 *bp = netdev_priv(dev);
2095
2096         pci_restore_state(pdev);
2097         pci_enable_device(pdev);
2098         pci_set_master(pdev);
2099
2100         if (!netif_running(dev))
2101                 return 0;
2102
2103         if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2104                 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2105
2106         spin_lock_irq(&bp->lock);
2107
2108         b44_init_rings(bp);
2109         b44_init_hw(bp);
2110         netif_device_attach(bp->dev);
2111         spin_unlock_irq(&bp->lock);
2112
2113         bp->timer.expires = jiffies + HZ;
2114         add_timer(&bp->timer);
2115
2116         b44_enable_ints(bp);
2117         return 0;
2118 }
2119
2120 static struct pci_driver b44_driver = {
2121         .name           = DRV_MODULE_NAME,
2122         .id_table       = b44_pci_tbl,
2123         .probe          = b44_init_one,
2124         .remove         = __devexit_p(b44_remove_one),
2125         .suspend        = b44_suspend,
2126         .resume         = b44_resume,
2127 };
2128
2129 static int __init b44_init(void)
2130 {
2131         unsigned int dma_desc_align_size = dma_get_cache_alignment();
2132
2133         /* Setup paramaters for syncing RX/TX DMA descriptors */
2134         dma_desc_align_mask = ~(dma_desc_align_size - 1);
2135         dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2136
2137         return pci_module_init(&b44_driver);
2138 }
2139
2140 static void __exit b44_cleanup(void)
2141 {
2142         pci_unregister_driver(&b44_driver);
2143 }
2144
2145 module_init(b44_init);
2146 module_exit(b44_cleanup);
2147