1 /* b44.c: Broadcom 4400 device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
6 * Distribute under GPL.
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/types.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/mii.h>
16 #include <linux/if_ether.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/dma-mapping.h>
23 #include <asm/uaccess.h>
29 #define DRV_MODULE_NAME "b44"
30 #define PFX DRV_MODULE_NAME ": "
31 #define DRV_MODULE_VERSION "0.95"
32 #define DRV_MODULE_RELDATE "Aug 3, 2004"
34 #define B44_DEF_MSG_ENABLE \
44 /* length of time before we decide the hardware is borked,
45 * and dev->tx_timeout() should be called to fix the problem
47 #define B44_TX_TIMEOUT (5 * HZ)
49 /* hardware minimum and maximum for a single frame's data payload */
50 #define B44_MIN_MTU 60
51 #define B44_MAX_MTU 1500
53 #define B44_RX_RING_SIZE 512
54 #define B44_DEF_RX_RING_PENDING 200
55 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
57 #define B44_TX_RING_SIZE 512
58 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
59 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
61 #define B44_DMA_MASK 0x3fffffff
63 #define TX_RING_GAP(BP) \
64 (B44_TX_RING_SIZE - (BP)->tx_pending)
65 #define TX_BUFFS_AVAIL(BP) \
66 (((BP)->tx_cons <= (BP)->tx_prod) ? \
67 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
68 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
69 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
71 #define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
72 #define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
74 /* minimum number of free TX descriptors required to wake up TX process */
75 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
77 static char version[] __devinitdata =
78 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
81 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
85 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
86 module_param(b44_debug, int, 0);
87 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
89 static struct pci_device_id b44_pci_tbl[] = {
90 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
92 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
94 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
95 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
96 { } /* terminate list with empty entry */
99 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
101 static void b44_halt(struct b44 *);
102 static void b44_init_rings(struct b44 *);
103 static void b44_init_hw(struct b44 *);
104 static int b44_poll(struct net_device *dev, int *budget);
105 #ifdef CONFIG_NET_POLL_CONTROLLER
106 static void b44_poll_controller(struct net_device *dev);
109 static int dma_desc_align_mask;
110 static int dma_desc_sync_size;
112 static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
114 unsigned long offset,
115 enum dma_data_direction dir)
117 dma_sync_single_range_for_device(&pdev->dev, dma_base,
118 offset & dma_desc_align_mask,
119 dma_desc_sync_size, dir);
122 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
124 unsigned long offset,
125 enum dma_data_direction dir)
127 dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
128 offset & dma_desc_align_mask,
129 dma_desc_sync_size, dir);
132 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
134 return readl(bp->regs + reg);
137 static inline void bw32(const struct b44 *bp,
138 unsigned long reg, unsigned long val)
140 writel(val, bp->regs + reg);
143 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
144 u32 bit, unsigned long timeout, const int clear)
148 for (i = 0; i < timeout; i++) {
149 u32 val = br32(bp, reg);
151 if (clear && !(val & bit))
153 if (!clear && (val & bit))
158 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
162 (clear ? "clear" : "set"));
168 /* Sonics SiliconBackplane support routines. ROFL, you should see all the
169 * buzz words used on this company's website :-)
171 * All of these routines must be invoked with bp->lock held and
172 * interrupts disabled.
175 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
176 #define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
178 static u32 ssb_get_core_rev(struct b44 *bp)
180 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
183 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
185 u32 bar_orig, pci_rev, val;
187 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
188 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
189 pci_rev = ssb_get_core_rev(bp);
191 val = br32(bp, B44_SBINTVEC);
193 bw32(bp, B44_SBINTVEC, val);
195 val = br32(bp, SSB_PCI_TRANS_2);
196 val |= SSB_PCI_PREF | SSB_PCI_BURST;
197 bw32(bp, SSB_PCI_TRANS_2, val);
199 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
204 static void ssb_core_disable(struct b44 *bp)
206 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
209 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
210 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
211 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
212 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
213 SBTMSLOW_REJECT | SBTMSLOW_RESET));
214 br32(bp, B44_SBTMSLOW);
216 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
217 br32(bp, B44_SBTMSLOW);
221 static void ssb_core_reset(struct b44 *bp)
225 ssb_core_disable(bp);
226 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
227 br32(bp, B44_SBTMSLOW);
230 /* Clear SERR if set, this is a hw bug workaround. */
231 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
232 bw32(bp, B44_SBTMSHIGH, 0);
234 val = br32(bp, B44_SBIMSTATE);
235 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
236 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
238 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
239 br32(bp, B44_SBTMSLOW);
242 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
243 br32(bp, B44_SBTMSLOW);
247 static int ssb_core_unit(struct b44 *bp)
250 u32 val = br32(bp, B44_SBADMATCH0);
253 type = val & SBADMATCH0_TYPE_MASK;
256 base = val & SBADMATCH0_BS0_MASK;
260 base = val & SBADMATCH0_BS1_MASK;
265 base = val & SBADMATCH0_BS2_MASK;
272 static int ssb_is_core_up(struct b44 *bp)
274 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
278 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
282 val = ((u32) data[2]) << 24;
283 val |= ((u32) data[3]) << 16;
284 val |= ((u32) data[4]) << 8;
285 val |= ((u32) data[5]) << 0;
286 bw32(bp, B44_CAM_DATA_LO, val);
287 val = (CAM_DATA_HI_VALID |
288 (((u32) data[0]) << 8) |
289 (((u32) data[1]) << 0));
290 bw32(bp, B44_CAM_DATA_HI, val);
291 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
292 (index << CAM_CTRL_INDEX_SHIFT)));
293 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
296 static inline void __b44_disable_ints(struct b44 *bp)
298 bw32(bp, B44_IMASK, 0);
301 static void b44_disable_ints(struct b44 *bp)
303 __b44_disable_ints(bp);
305 /* Flush posted writes. */
309 static void b44_enable_ints(struct b44 *bp)
311 bw32(bp, B44_IMASK, bp->imask);
314 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
318 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
319 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
320 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
321 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
322 (reg << MDIO_DATA_RA_SHIFT) |
323 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
324 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
325 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
330 static int b44_writephy(struct b44 *bp, int reg, u32 val)
332 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
333 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
334 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
335 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
336 (reg << MDIO_DATA_RA_SHIFT) |
337 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
338 (val & MDIO_DATA_DATA)));
339 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
342 /* miilib interface */
343 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
344 * due to code existing before miilib use was added to this driver.
345 * Someone should remove this artificial driver limitation in
346 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
348 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
351 struct b44 *bp = netdev_priv(dev);
352 int rc = b44_readphy(bp, location, &val);
358 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
361 struct b44 *bp = netdev_priv(dev);
362 b44_writephy(bp, location, val);
365 static int b44_phy_reset(struct b44 *bp)
370 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
374 err = b44_readphy(bp, MII_BMCR, &val);
376 if (val & BMCR_RESET) {
377 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
386 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
390 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
391 bp->flags |= pause_flags;
393 val = br32(bp, B44_RXCONFIG);
394 if (pause_flags & B44_FLAG_RX_PAUSE)
395 val |= RXCONFIG_FLOW;
397 val &= ~RXCONFIG_FLOW;
398 bw32(bp, B44_RXCONFIG, val);
400 val = br32(bp, B44_MAC_FLOW);
401 if (pause_flags & B44_FLAG_TX_PAUSE)
402 val |= (MAC_FLOW_PAUSE_ENAB |
403 (0xc0 & MAC_FLOW_RX_HI_WATER));
405 val &= ~MAC_FLOW_PAUSE_ENAB;
406 bw32(bp, B44_MAC_FLOW, val);
409 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
411 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
414 if (local & ADVERTISE_PAUSE_CAP) {
415 if (local & ADVERTISE_PAUSE_ASYM) {
416 if (remote & LPA_PAUSE_CAP)
417 pause_enab |= (B44_FLAG_TX_PAUSE |
419 else if (remote & LPA_PAUSE_ASYM)
420 pause_enab |= B44_FLAG_RX_PAUSE;
422 if (remote & LPA_PAUSE_CAP)
423 pause_enab |= (B44_FLAG_TX_PAUSE |
426 } else if (local & ADVERTISE_PAUSE_ASYM) {
427 if ((remote & LPA_PAUSE_CAP) &&
428 (remote & LPA_PAUSE_ASYM))
429 pause_enab |= B44_FLAG_TX_PAUSE;
432 __b44_set_flow_ctrl(bp, pause_enab);
435 static int b44_setup_phy(struct b44 *bp)
440 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
442 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
443 val & MII_ALEDCTRL_ALLMSK)) != 0)
445 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
447 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
448 val | MII_TLEDCTRL_ENABLE)) != 0)
451 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
452 u32 adv = ADVERTISE_CSMA;
454 if (bp->flags & B44_FLAG_ADV_10HALF)
455 adv |= ADVERTISE_10HALF;
456 if (bp->flags & B44_FLAG_ADV_10FULL)
457 adv |= ADVERTISE_10FULL;
458 if (bp->flags & B44_FLAG_ADV_100HALF)
459 adv |= ADVERTISE_100HALF;
460 if (bp->flags & B44_FLAG_ADV_100FULL)
461 adv |= ADVERTISE_100FULL;
463 if (bp->flags & B44_FLAG_PAUSE_AUTO)
464 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
466 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
468 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
469 BMCR_ANRESTART))) != 0)
474 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
476 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
477 if (bp->flags & B44_FLAG_100_BASE_T)
478 bmcr |= BMCR_SPEED100;
479 if (bp->flags & B44_FLAG_FULL_DUPLEX)
480 bmcr |= BMCR_FULLDPLX;
481 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
484 /* Since we will not be negotiating there is no safe way
485 * to determine if the link partner supports flow control
486 * or not. So just disable it completely in this case.
488 b44_set_flow_ctrl(bp, 0, 0);
495 static void b44_stats_update(struct b44 *bp)
500 val = &bp->hw_stats.tx_good_octets;
501 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
504 val = &bp->hw_stats.rx_good_octets;
505 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
506 *val++ += br32(bp, reg);
510 static void b44_link_report(struct b44 *bp)
512 if (!netif_carrier_ok(bp->dev)) {
513 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
515 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
517 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
518 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
520 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
523 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
524 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
528 static void b44_check_phy(struct b44 *bp)
532 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
533 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
535 if (aux & MII_AUXCTRL_SPEED)
536 bp->flags |= B44_FLAG_100_BASE_T;
538 bp->flags &= ~B44_FLAG_100_BASE_T;
539 if (aux & MII_AUXCTRL_DUPLEX)
540 bp->flags |= B44_FLAG_FULL_DUPLEX;
542 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
544 if (!netif_carrier_ok(bp->dev) &&
545 (bmsr & BMSR_LSTATUS)) {
546 u32 val = br32(bp, B44_TX_CTRL);
547 u32 local_adv, remote_adv;
549 if (bp->flags & B44_FLAG_FULL_DUPLEX)
550 val |= TX_CTRL_DUPLEX;
552 val &= ~TX_CTRL_DUPLEX;
553 bw32(bp, B44_TX_CTRL, val);
555 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
556 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
557 !b44_readphy(bp, MII_LPA, &remote_adv))
558 b44_set_flow_ctrl(bp, local_adv, remote_adv);
561 netif_carrier_on(bp->dev);
563 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
565 netif_carrier_off(bp->dev);
569 if (bmsr & BMSR_RFAULT)
570 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
573 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
578 static void b44_timer(unsigned long __opaque)
580 struct b44 *bp = (struct b44 *) __opaque;
582 spin_lock_irq(&bp->lock);
586 b44_stats_update(bp);
588 spin_unlock_irq(&bp->lock);
590 bp->timer.expires = jiffies + HZ;
591 add_timer(&bp->timer);
594 static void b44_tx(struct b44 *bp)
598 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
599 cur /= sizeof(struct dma_desc);
601 /* XXX needs updating when NETIF_F_SG is supported */
602 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
603 struct ring_info *rp = &bp->tx_buffers[cons];
604 struct sk_buff *skb = rp->skb;
606 if (unlikely(skb == NULL))
609 pci_unmap_single(bp->pdev,
610 pci_unmap_addr(rp, mapping),
614 dev_kfree_skb_irq(skb);
618 if (netif_queue_stopped(bp->dev) &&
619 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
620 netif_wake_queue(bp->dev);
622 bw32(bp, B44_GPTIMER, 0);
625 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
626 * before the DMA address you give it. So we allocate 30 more bytes
627 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
628 * point the chip at 30 bytes past where the rx_header will go.
630 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
633 struct ring_info *src_map, *map;
634 struct rx_header *rh;
642 src_map = &bp->rx_buffers[src_idx];
643 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
644 map = &bp->rx_buffers[dest_idx];
645 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
649 mapping = pci_map_single(bp->pdev, skb->data,
653 /* Hardware bug work-around, the chip is unable to do PCI DMA
654 to/from anything above 1GB :-( */
655 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
657 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
658 dev_kfree_skb_any(skb);
659 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
662 mapping = pci_map_single(bp->pdev, skb->data,
665 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
666 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
667 dev_kfree_skb_any(skb);
673 skb_reserve(skb, bp->rx_offset);
675 rh = (struct rx_header *)
676 (skb->data - bp->rx_offset);
681 pci_unmap_addr_set(map, mapping, mapping);
686 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
687 if (dest_idx == (B44_RX_RING_SIZE - 1))
688 ctrl |= DESC_CTRL_EOT;
690 dp = &bp->rx_ring[dest_idx];
691 dp->ctrl = cpu_to_le32(ctrl);
692 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
694 if (bp->flags & B44_FLAG_RX_RING_HACK)
695 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
696 dest_idx * sizeof(dp),
699 return RX_PKT_BUF_SZ;
702 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
704 struct dma_desc *src_desc, *dest_desc;
705 struct ring_info *src_map, *dest_map;
706 struct rx_header *rh;
710 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
711 dest_desc = &bp->rx_ring[dest_idx];
712 dest_map = &bp->rx_buffers[dest_idx];
713 src_desc = &bp->rx_ring[src_idx];
714 src_map = &bp->rx_buffers[src_idx];
716 dest_map->skb = src_map->skb;
717 rh = (struct rx_header *) src_map->skb->data;
720 pci_unmap_addr_set(dest_map, mapping,
721 pci_unmap_addr(src_map, mapping));
723 if (bp->flags & B44_FLAG_RX_RING_HACK)
724 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
725 src_idx * sizeof(src_desc),
728 ctrl = src_desc->ctrl;
729 if (dest_idx == (B44_RX_RING_SIZE - 1))
730 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
732 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
734 dest_desc->ctrl = ctrl;
735 dest_desc->addr = src_desc->addr;
739 if (bp->flags & B44_FLAG_RX_RING_HACK)
740 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
741 dest_idx * sizeof(dest_desc),
744 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
749 static int b44_rx(struct b44 *bp, int budget)
755 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
756 prod /= sizeof(struct dma_desc);
759 while (cons != prod && budget > 0) {
760 struct ring_info *rp = &bp->rx_buffers[cons];
761 struct sk_buff *skb = rp->skb;
762 dma_addr_t map = pci_unmap_addr(rp, mapping);
763 struct rx_header *rh;
766 pci_dma_sync_single_for_cpu(bp->pdev, map,
769 rh = (struct rx_header *) skb->data;
770 len = cpu_to_le16(rh->len);
771 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
772 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
774 b44_recycle_rx(bp, cons, bp->rx_prod);
776 bp->stats.rx_dropped++;
786 len = cpu_to_le16(rh->len);
787 } while (len == 0 && i++ < 5);
795 if (len > RX_COPY_THRESHOLD) {
797 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
800 pci_unmap_single(bp->pdev, map,
801 skb_size, PCI_DMA_FROMDEVICE);
802 /* Leave out rx_header */
803 skb_put(skb, len+bp->rx_offset);
804 skb_pull(skb,bp->rx_offset);
806 struct sk_buff *copy_skb;
808 b44_recycle_rx(bp, cons, bp->rx_prod);
809 copy_skb = dev_alloc_skb(len + 2);
810 if (copy_skb == NULL)
811 goto drop_it_no_recycle;
813 copy_skb->dev = bp->dev;
814 skb_reserve(copy_skb, 2);
815 skb_put(copy_skb, len);
816 /* DMA sync done above, copy just the actual packet */
817 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
821 skb->ip_summed = CHECKSUM_NONE;
822 skb->protocol = eth_type_trans(skb, bp->dev);
823 netif_receive_skb(skb);
824 bp->dev->last_rx = jiffies;
828 bp->rx_prod = (bp->rx_prod + 1) &
829 (B44_RX_RING_SIZE - 1);
830 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
834 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
839 static int b44_poll(struct net_device *netdev, int *budget)
841 struct b44 *bp = netdev_priv(netdev);
844 spin_lock_irq(&bp->lock);
846 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
847 /* spin_lock(&bp->tx_lock); */
849 /* spin_unlock(&bp->tx_lock); */
851 spin_unlock_irq(&bp->lock);
854 if (bp->istat & ISTAT_RX) {
855 int orig_budget = *budget;
858 if (orig_budget > netdev->quota)
859 orig_budget = netdev->quota;
861 work_done = b44_rx(bp, orig_budget);
863 *budget -= work_done;
864 netdev->quota -= work_done;
866 if (work_done >= orig_budget)
870 if (bp->istat & ISTAT_ERRORS) {
871 spin_lock_irq(&bp->lock);
875 netif_wake_queue(bp->dev);
876 spin_unlock_irq(&bp->lock);
881 netif_rx_complete(netdev);
885 return (done ? 0 : 1);
888 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
890 struct net_device *dev = dev_id;
891 struct b44 *bp = netdev_priv(dev);
896 spin_lock_irqsave(&bp->lock, flags);
898 istat = br32(bp, B44_ISTAT);
899 imask = br32(bp, B44_IMASK);
901 /* ??? What the fuck is the purpose of the interrupt mask
902 * ??? register if we have to mask it out by hand anyways?
907 if (netif_rx_schedule_prep(dev)) {
908 /* NOTE: These writes are posted by the readback of
909 * the ISTAT register below.
912 __b44_disable_ints(bp);
913 __netif_rx_schedule(dev);
915 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
919 bw32(bp, B44_ISTAT, istat);
922 spin_unlock_irqrestore(&bp->lock, flags);
923 return IRQ_RETVAL(handled);
926 static void b44_tx_timeout(struct net_device *dev)
928 struct b44 *bp = netdev_priv(dev);
930 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
933 spin_lock_irq(&bp->lock);
939 spin_unlock_irq(&bp->lock);
943 netif_wake_queue(dev);
946 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
948 struct b44 *bp = netdev_priv(dev);
949 struct sk_buff *bounce_skb;
951 u32 len, entry, ctrl;
954 spin_lock_irq(&bp->lock);
956 /* This is a hard error, log it. */
957 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
958 netif_stop_queue(dev);
959 spin_unlock_irq(&bp->lock);
960 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
965 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
966 if(mapping+len > B44_DMA_MASK) {
967 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
968 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
970 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
973 return NETDEV_TX_BUSY;
975 mapping = pci_map_single(bp->pdev, bounce_skb->data,
976 len, PCI_DMA_TODEVICE);
977 if(mapping+len > B44_DMA_MASK) {
978 pci_unmap_single(bp->pdev, mapping,
979 len, PCI_DMA_TODEVICE);
980 dev_kfree_skb_any(bounce_skb);
981 return NETDEV_TX_BUSY;
984 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
985 dev_kfree_skb_any(skb);
990 bp->tx_buffers[entry].skb = skb;
991 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
993 ctrl = (len & DESC_CTRL_LEN);
994 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
995 if (entry == (B44_TX_RING_SIZE - 1))
996 ctrl |= DESC_CTRL_EOT;
998 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
999 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1001 if (bp->flags & B44_FLAG_TX_RING_HACK)
1002 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1003 entry * sizeof(bp->tx_ring[0]),
1006 entry = NEXT_TX(entry);
1008 bp->tx_prod = entry;
1012 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1013 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1014 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1015 if (bp->flags & B44_FLAG_REORDER_BUG)
1016 br32(bp, B44_DMATX_PTR);
1018 if (TX_BUFFS_AVAIL(bp) < 1)
1019 netif_stop_queue(dev);
1021 spin_unlock_irq(&bp->lock);
1023 dev->trans_start = jiffies;
1028 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1030 struct b44 *bp = netdev_priv(dev);
1032 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1035 if (!netif_running(dev)) {
1036 /* We'll just catch it later when the
1043 spin_lock_irq(&bp->lock);
1048 spin_unlock_irq(&bp->lock);
1050 b44_enable_ints(bp);
1055 /* Free up pending packets in all rx/tx rings.
1057 * The chip has been shut down and the driver detached from
1058 * the networking, so no interrupts or new tx packets will
1059 * end up in the driver. bp->lock is not held and we are not
1060 * in an interrupt context and thus may sleep.
1062 static void b44_free_rings(struct b44 *bp)
1064 struct ring_info *rp;
1067 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1068 rp = &bp->rx_buffers[i];
1070 if (rp->skb == NULL)
1072 pci_unmap_single(bp->pdev,
1073 pci_unmap_addr(rp, mapping),
1075 PCI_DMA_FROMDEVICE);
1076 dev_kfree_skb_any(rp->skb);
1080 /* XXX needs changes once NETIF_F_SG is set... */
1081 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1082 rp = &bp->tx_buffers[i];
1084 if (rp->skb == NULL)
1086 pci_unmap_single(bp->pdev,
1087 pci_unmap_addr(rp, mapping),
1090 dev_kfree_skb_any(rp->skb);
1095 /* Initialize tx/rx rings for packet processing.
1097 * The chip has been shut down and the driver detached from
1098 * the networking, so no interrupts or new tx packets will
1099 * end up in the driver. bp->lock is not held and we are not
1100 * in an interrupt context and thus may sleep.
1102 static void b44_init_rings(struct b44 *bp)
1108 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1109 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1111 if (bp->flags & B44_FLAG_RX_RING_HACK)
1112 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1114 PCI_DMA_BIDIRECTIONAL);
1116 if (bp->flags & B44_FLAG_TX_RING_HACK)
1117 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1121 for (i = 0; i < bp->rx_pending; i++) {
1122 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1128 * Must not be invoked with interrupt sources disabled and
1129 * the hardware shutdown down.
1131 static void b44_free_consistent(struct b44 *bp)
1133 kfree(bp->rx_buffers);
1134 bp->rx_buffers = NULL;
1135 kfree(bp->tx_buffers);
1136 bp->tx_buffers = NULL;
1138 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1139 dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1144 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1145 bp->rx_ring, bp->rx_ring_dma);
1147 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1150 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1151 dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1156 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1157 bp->tx_ring, bp->tx_ring_dma);
1159 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1164 * Must not be invoked with interrupt sources disabled and
1165 * the hardware shutdown down. Can sleep.
1167 static int b44_alloc_consistent(struct b44 *bp)
1171 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1172 bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1173 if (!bp->rx_buffers)
1175 memset(bp->rx_buffers, 0, size);
1177 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1178 bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1179 if (!bp->tx_buffers)
1181 memset(bp->tx_buffers, 0, size);
1183 size = DMA_TABLE_BYTES;
1184 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1186 /* Allocation may have failed due to pci_alloc_consistent
1187 insisting on use of GFP_DMA, which is more restrictive
1188 than necessary... */
1189 struct dma_desc *rx_ring;
1190 dma_addr_t rx_ring_dma;
1192 if (!(rx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
1195 memset(rx_ring, 0, size);
1196 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1200 if (rx_ring_dma + size > B44_DMA_MASK) {
1205 bp->rx_ring = rx_ring;
1206 bp->rx_ring_dma = rx_ring_dma;
1207 bp->flags |= B44_FLAG_RX_RING_HACK;
1210 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1212 /* Allocation may have failed due to pci_alloc_consistent
1213 insisting on use of GFP_DMA, which is more restrictive
1214 than necessary... */
1215 struct dma_desc *tx_ring;
1216 dma_addr_t tx_ring_dma;
1218 if (!(tx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
1221 memset(tx_ring, 0, size);
1222 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1226 if (tx_ring_dma + size > B44_DMA_MASK) {
1231 bp->tx_ring = tx_ring;
1232 bp->tx_ring_dma = tx_ring_dma;
1233 bp->flags |= B44_FLAG_TX_RING_HACK;
1239 b44_free_consistent(bp);
1243 /* bp->lock is held. */
1244 static void b44_clear_stats(struct b44 *bp)
1248 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1249 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1251 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1255 /* bp->lock is held. */
1256 static void b44_chip_reset(struct b44 *bp)
1258 if (ssb_is_core_up(bp)) {
1259 bw32(bp, B44_RCV_LAZY, 0);
1260 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1261 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1262 bw32(bp, B44_DMATX_CTRL, 0);
1263 bp->tx_prod = bp->tx_cons = 0;
1264 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1265 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1268 bw32(bp, B44_DMARX_CTRL, 0);
1269 bp->rx_prod = bp->rx_cons = 0;
1271 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1278 b44_clear_stats(bp);
1280 /* Make PHY accessible. */
1281 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1282 (0x0d & MDIO_CTRL_MAXF_MASK)));
1283 br32(bp, B44_MDIO_CTRL);
1285 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1286 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1287 br32(bp, B44_ENET_CTRL);
1288 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1290 u32 val = br32(bp, B44_DEVCTRL);
1292 if (val & DEVCTRL_EPR) {
1293 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1294 br32(bp, B44_DEVCTRL);
1297 bp->flags |= B44_FLAG_INTERNAL_PHY;
1301 /* bp->lock is held. */
1302 static void b44_halt(struct b44 *bp)
1304 b44_disable_ints(bp);
1308 /* bp->lock is held. */
1309 static void __b44_set_mac_addr(struct b44 *bp)
1311 bw32(bp, B44_CAM_CTRL, 0);
1312 if (!(bp->dev->flags & IFF_PROMISC)) {
1315 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1316 val = br32(bp, B44_CAM_CTRL);
1317 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1321 static int b44_set_mac_addr(struct net_device *dev, void *p)
1323 struct b44 *bp = netdev_priv(dev);
1324 struct sockaddr *addr = p;
1326 if (netif_running(dev))
1329 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1331 spin_lock_irq(&bp->lock);
1332 __b44_set_mac_addr(bp);
1333 spin_unlock_irq(&bp->lock);
1338 /* Called at device open time to get the chip ready for
1339 * packet processing. Invoked with bp->lock held.
1341 static void __b44_set_rx_mode(struct net_device *);
1342 static void b44_init_hw(struct b44 *bp)
1350 /* Enable CRC32, set proper LED modes and power on PHY */
1351 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1352 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1354 /* This sets the MAC address too. */
1355 __b44_set_rx_mode(bp->dev);
1357 /* MTU + eth header + possible VLAN tag + struct rx_header */
1358 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1359 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1361 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1362 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1363 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1364 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1365 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1366 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1368 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1369 bp->rx_prod = bp->rx_pending;
1371 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1373 val = br32(bp, B44_ENET_CTRL);
1374 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1377 static int b44_open(struct net_device *dev)
1379 struct b44 *bp = netdev_priv(dev);
1382 err = b44_alloc_consistent(bp);
1386 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1390 spin_lock_irq(&bp->lock);
1394 bp->flags |= B44_FLAG_INIT_COMPLETE;
1396 netif_carrier_off(dev);
1399 spin_unlock_irq(&bp->lock);
1401 init_timer(&bp->timer);
1402 bp->timer.expires = jiffies + HZ;
1403 bp->timer.data = (unsigned long) bp;
1404 bp->timer.function = b44_timer;
1405 add_timer(&bp->timer);
1407 b44_enable_ints(bp);
1412 b44_free_consistent(bp);
1417 /*static*/ void b44_dump_state(struct b44 *bp)
1419 u32 val32, val32_2, val32_3, val32_4, val32_5;
1422 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1423 printk("DEBUG: PCI status [%04x] \n", val16);
1428 #ifdef CONFIG_NET_POLL_CONTROLLER
1430 * Polling receive - used by netconsole and other diagnostic tools
1431 * to allow network i/o with interrupts disabled.
1433 static void b44_poll_controller(struct net_device *dev)
1435 disable_irq(dev->irq);
1436 b44_interrupt(dev->irq, dev, NULL);
1437 enable_irq(dev->irq);
1441 static int b44_close(struct net_device *dev)
1443 struct b44 *bp = netdev_priv(dev);
1445 netif_stop_queue(dev);
1447 del_timer_sync(&bp->timer);
1449 spin_lock_irq(&bp->lock);
1456 bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1457 netif_carrier_off(bp->dev);
1459 spin_unlock_irq(&bp->lock);
1461 free_irq(dev->irq, dev);
1463 b44_free_consistent(bp);
1468 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1470 struct b44 *bp = netdev_priv(dev);
1471 struct net_device_stats *nstat = &bp->stats;
1472 struct b44_hw_stats *hwstat = &bp->hw_stats;
1474 /* Convert HW stats into netdevice stats. */
1475 nstat->rx_packets = hwstat->rx_pkts;
1476 nstat->tx_packets = hwstat->tx_pkts;
1477 nstat->rx_bytes = hwstat->rx_octets;
1478 nstat->tx_bytes = hwstat->tx_octets;
1479 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1480 hwstat->tx_oversize_pkts +
1481 hwstat->tx_underruns +
1482 hwstat->tx_excessive_cols +
1483 hwstat->tx_late_cols);
1484 nstat->multicast = hwstat->tx_multicast_pkts;
1485 nstat->collisions = hwstat->tx_total_cols;
1487 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1488 hwstat->rx_undersize);
1489 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1490 nstat->rx_frame_errors = hwstat->rx_align_errs;
1491 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1492 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1493 hwstat->rx_oversize_pkts +
1494 hwstat->rx_missed_pkts +
1495 hwstat->rx_crc_align_errs +
1496 hwstat->rx_undersize +
1497 hwstat->rx_crc_errs +
1498 hwstat->rx_align_errs +
1499 hwstat->rx_symbol_errs);
1501 nstat->tx_aborted_errors = hwstat->tx_underruns;
1503 /* Carrier lost counter seems to be broken for some devices */
1504 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1510 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1512 struct dev_mc_list *mclist;
1515 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1516 mclist = dev->mc_list;
1517 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1518 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1523 static void __b44_set_rx_mode(struct net_device *dev)
1525 struct b44 *bp = netdev_priv(dev);
1528 unsigned char zero[6] = {0,0,0,0,0,0};
1530 val = br32(bp, B44_RXCONFIG);
1531 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1532 if (dev->flags & IFF_PROMISC) {
1533 val |= RXCONFIG_PROMISC;
1534 bw32(bp, B44_RXCONFIG, val);
1536 __b44_set_mac_addr(bp);
1538 if (dev->flags & IFF_ALLMULTI)
1539 val |= RXCONFIG_ALLMULTI;
1541 i=__b44_load_mcast(bp, dev);
1544 __b44_cam_write(bp, zero, i);
1546 bw32(bp, B44_RXCONFIG, val);
1547 val = br32(bp, B44_CAM_CTRL);
1548 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1552 static void b44_set_rx_mode(struct net_device *dev)
1554 struct b44 *bp = netdev_priv(dev);
1556 spin_lock_irq(&bp->lock);
1557 __b44_set_rx_mode(dev);
1558 spin_unlock_irq(&bp->lock);
1561 static u32 b44_get_msglevel(struct net_device *dev)
1563 struct b44 *bp = netdev_priv(dev);
1564 return bp->msg_enable;
1567 static void b44_set_msglevel(struct net_device *dev, u32 value)
1569 struct b44 *bp = netdev_priv(dev);
1570 bp->msg_enable = value;
1573 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1575 struct b44 *bp = netdev_priv(dev);
1576 struct pci_dev *pci_dev = bp->pdev;
1578 strcpy (info->driver, DRV_MODULE_NAME);
1579 strcpy (info->version, DRV_MODULE_VERSION);
1580 strcpy (info->bus_info, pci_name(pci_dev));
1583 static int b44_nway_reset(struct net_device *dev)
1585 struct b44 *bp = netdev_priv(dev);
1589 spin_lock_irq(&bp->lock);
1590 b44_readphy(bp, MII_BMCR, &bmcr);
1591 b44_readphy(bp, MII_BMCR, &bmcr);
1593 if (bmcr & BMCR_ANENABLE) {
1594 b44_writephy(bp, MII_BMCR,
1595 bmcr | BMCR_ANRESTART);
1598 spin_unlock_irq(&bp->lock);
1603 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1605 struct b44 *bp = netdev_priv(dev);
1607 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1609 cmd->supported = (SUPPORTED_Autoneg);
1610 cmd->supported |= (SUPPORTED_100baseT_Half |
1611 SUPPORTED_100baseT_Full |
1612 SUPPORTED_10baseT_Half |
1613 SUPPORTED_10baseT_Full |
1616 cmd->advertising = 0;
1617 if (bp->flags & B44_FLAG_ADV_10HALF)
1618 cmd->advertising |= ADVERTISED_10baseT_Half;
1619 if (bp->flags & B44_FLAG_ADV_10FULL)
1620 cmd->advertising |= ADVERTISED_10baseT_Full;
1621 if (bp->flags & B44_FLAG_ADV_100HALF)
1622 cmd->advertising |= ADVERTISED_100baseT_Half;
1623 if (bp->flags & B44_FLAG_ADV_100FULL)
1624 cmd->advertising |= ADVERTISED_100baseT_Full;
1625 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1626 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1627 SPEED_100 : SPEED_10;
1628 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1629 DUPLEX_FULL : DUPLEX_HALF;
1631 cmd->phy_address = bp->phy_addr;
1632 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1633 XCVR_INTERNAL : XCVR_EXTERNAL;
1634 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1635 AUTONEG_DISABLE : AUTONEG_ENABLE;
1641 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1643 struct b44 *bp = netdev_priv(dev);
1645 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1648 /* We do not support gigabit. */
1649 if (cmd->autoneg == AUTONEG_ENABLE) {
1650 if (cmd->advertising &
1651 (ADVERTISED_1000baseT_Half |
1652 ADVERTISED_1000baseT_Full))
1654 } else if ((cmd->speed != SPEED_100 &&
1655 cmd->speed != SPEED_10) ||
1656 (cmd->duplex != DUPLEX_HALF &&
1657 cmd->duplex != DUPLEX_FULL)) {
1661 spin_lock_irq(&bp->lock);
1663 if (cmd->autoneg == AUTONEG_ENABLE) {
1664 bp->flags &= ~B44_FLAG_FORCE_LINK;
1665 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1666 B44_FLAG_ADV_10FULL |
1667 B44_FLAG_ADV_100HALF |
1668 B44_FLAG_ADV_100FULL);
1669 if (cmd->advertising & ADVERTISE_10HALF)
1670 bp->flags |= B44_FLAG_ADV_10HALF;
1671 if (cmd->advertising & ADVERTISE_10FULL)
1672 bp->flags |= B44_FLAG_ADV_10FULL;
1673 if (cmd->advertising & ADVERTISE_100HALF)
1674 bp->flags |= B44_FLAG_ADV_100HALF;
1675 if (cmd->advertising & ADVERTISE_100FULL)
1676 bp->flags |= B44_FLAG_ADV_100FULL;
1678 bp->flags |= B44_FLAG_FORCE_LINK;
1679 if (cmd->speed == SPEED_100)
1680 bp->flags |= B44_FLAG_100_BASE_T;
1681 if (cmd->duplex == DUPLEX_FULL)
1682 bp->flags |= B44_FLAG_FULL_DUPLEX;
1687 spin_unlock_irq(&bp->lock);
1692 static void b44_get_ringparam(struct net_device *dev,
1693 struct ethtool_ringparam *ering)
1695 struct b44 *bp = netdev_priv(dev);
1697 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1698 ering->rx_pending = bp->rx_pending;
1700 /* XXX ethtool lacks a tx_max_pending, oops... */
1703 static int b44_set_ringparam(struct net_device *dev,
1704 struct ethtool_ringparam *ering)
1706 struct b44 *bp = netdev_priv(dev);
1708 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1709 (ering->rx_mini_pending != 0) ||
1710 (ering->rx_jumbo_pending != 0) ||
1711 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1714 spin_lock_irq(&bp->lock);
1716 bp->rx_pending = ering->rx_pending;
1717 bp->tx_pending = ering->tx_pending;
1722 netif_wake_queue(bp->dev);
1723 spin_unlock_irq(&bp->lock);
1725 b44_enable_ints(bp);
1730 static void b44_get_pauseparam(struct net_device *dev,
1731 struct ethtool_pauseparam *epause)
1733 struct b44 *bp = netdev_priv(dev);
1736 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1738 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1740 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1743 static int b44_set_pauseparam(struct net_device *dev,
1744 struct ethtool_pauseparam *epause)
1746 struct b44 *bp = netdev_priv(dev);
1748 spin_lock_irq(&bp->lock);
1749 if (epause->autoneg)
1750 bp->flags |= B44_FLAG_PAUSE_AUTO;
1752 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1753 if (epause->rx_pause)
1754 bp->flags |= B44_FLAG_RX_PAUSE;
1756 bp->flags &= ~B44_FLAG_RX_PAUSE;
1757 if (epause->tx_pause)
1758 bp->flags |= B44_FLAG_TX_PAUSE;
1760 bp->flags &= ~B44_FLAG_TX_PAUSE;
1761 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1766 __b44_set_flow_ctrl(bp, bp->flags);
1768 spin_unlock_irq(&bp->lock);
1770 b44_enable_ints(bp);
1775 static struct ethtool_ops b44_ethtool_ops = {
1776 .get_drvinfo = b44_get_drvinfo,
1777 .get_settings = b44_get_settings,
1778 .set_settings = b44_set_settings,
1779 .nway_reset = b44_nway_reset,
1780 .get_link = ethtool_op_get_link,
1781 .get_ringparam = b44_get_ringparam,
1782 .set_ringparam = b44_set_ringparam,
1783 .get_pauseparam = b44_get_pauseparam,
1784 .set_pauseparam = b44_set_pauseparam,
1785 .get_msglevel = b44_get_msglevel,
1786 .set_msglevel = b44_set_msglevel,
1787 .get_perm_addr = ethtool_op_get_perm_addr,
1790 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1792 struct mii_ioctl_data *data = if_mii(ifr);
1793 struct b44 *bp = netdev_priv(dev);
1796 spin_lock_irq(&bp->lock);
1797 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1798 spin_unlock_irq(&bp->lock);
1803 /* Read 128-bytes of EEPROM. */
1804 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1807 u16 *ptr = (u16 *) data;
1809 for (i = 0; i < 128; i += 2)
1810 ptr[i / 2] = readw(bp->regs + 4096 + i);
1815 static int __devinit b44_get_invariants(struct b44 *bp)
1820 err = b44_read_eeprom(bp, &eeprom[0]);
1824 bp->dev->dev_addr[0] = eeprom[79];
1825 bp->dev->dev_addr[1] = eeprom[78];
1826 bp->dev->dev_addr[2] = eeprom[81];
1827 bp->dev->dev_addr[3] = eeprom[80];
1828 bp->dev->dev_addr[4] = eeprom[83];
1829 bp->dev->dev_addr[5] = eeprom[82];
1830 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1832 bp->phy_addr = eeprom[90] & 0x1f;
1834 /* With this, plus the rx_header prepended to the data by the
1835 * hardware, we'll land the ethernet header on a 2-byte boundary.
1839 bp->imask = IMASK_DEF;
1841 bp->core_unit = ssb_core_unit(bp);
1842 bp->dma_offset = SB_PCI_DMA;
1844 /* XXX - really required?
1845 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1851 static int __devinit b44_init_one(struct pci_dev *pdev,
1852 const struct pci_device_id *ent)
1854 static int b44_version_printed = 0;
1855 unsigned long b44reg_base, b44reg_len;
1856 struct net_device *dev;
1860 if (b44_version_printed++ == 0)
1861 printk(KERN_INFO "%s", version);
1863 err = pci_enable_device(pdev);
1865 printk(KERN_ERR PFX "Cannot enable PCI device, "
1870 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1871 printk(KERN_ERR PFX "Cannot find proper PCI device "
1872 "base address, aborting.\n");
1874 goto err_out_disable_pdev;
1877 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1879 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1881 goto err_out_disable_pdev;
1884 pci_set_master(pdev);
1886 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1888 printk(KERN_ERR PFX "No usable DMA configuration, "
1890 goto err_out_free_res;
1893 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1895 printk(KERN_ERR PFX "No usable DMA configuration, "
1897 goto err_out_free_res;
1900 b44reg_base = pci_resource_start(pdev, 0);
1901 b44reg_len = pci_resource_len(pdev, 0);
1903 dev = alloc_etherdev(sizeof(*bp));
1905 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1907 goto err_out_free_res;
1910 SET_MODULE_OWNER(dev);
1911 SET_NETDEV_DEV(dev,&pdev->dev);
1913 /* No interesting netdevice features in this card... */
1916 bp = netdev_priv(dev);
1920 bp->msg_enable = (1 << b44_debug) - 1;
1922 bp->msg_enable = B44_DEF_MSG_ENABLE;
1924 spin_lock_init(&bp->lock);
1926 bp->regs = ioremap(b44reg_base, b44reg_len);
1927 if (bp->regs == 0UL) {
1928 printk(KERN_ERR PFX "Cannot map device registers, "
1931 goto err_out_free_dev;
1934 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1935 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1937 dev->open = b44_open;
1938 dev->stop = b44_close;
1939 dev->hard_start_xmit = b44_start_xmit;
1940 dev->get_stats = b44_get_stats;
1941 dev->set_multicast_list = b44_set_rx_mode;
1942 dev->set_mac_address = b44_set_mac_addr;
1943 dev->do_ioctl = b44_ioctl;
1944 dev->tx_timeout = b44_tx_timeout;
1945 dev->poll = b44_poll;
1947 dev->watchdog_timeo = B44_TX_TIMEOUT;
1948 #ifdef CONFIG_NET_POLL_CONTROLLER
1949 dev->poll_controller = b44_poll_controller;
1951 dev->change_mtu = b44_change_mtu;
1952 dev->irq = pdev->irq;
1953 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1955 err = b44_get_invariants(bp);
1957 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1959 goto err_out_iounmap;
1962 bp->mii_if.dev = dev;
1963 bp->mii_if.mdio_read = b44_mii_read;
1964 bp->mii_if.mdio_write = b44_mii_write;
1965 bp->mii_if.phy_id = bp->phy_addr;
1966 bp->mii_if.phy_id_mask = 0x1f;
1967 bp->mii_if.reg_num_mask = 0x1f;
1969 /* By default, advertise all speed/duplex settings. */
1970 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1971 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1973 /* By default, auto-negotiate PAUSE. */
1974 bp->flags |= B44_FLAG_PAUSE_AUTO;
1976 err = register_netdev(dev);
1978 printk(KERN_ERR PFX "Cannot register net device, "
1980 goto err_out_iounmap;
1983 pci_set_drvdata(pdev, dev);
1985 pci_save_state(bp->pdev);
1987 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1988 for (i = 0; i < 6; i++)
1989 printk("%2.2x%c", dev->dev_addr[i],
1990 i == 5 ? '\n' : ':');
2001 pci_release_regions(pdev);
2003 err_out_disable_pdev:
2004 pci_disable_device(pdev);
2005 pci_set_drvdata(pdev, NULL);
2009 static void __devexit b44_remove_one(struct pci_dev *pdev)
2011 struct net_device *dev = pci_get_drvdata(pdev);
2014 struct b44 *bp = netdev_priv(dev);
2016 unregister_netdev(dev);
2019 pci_release_regions(pdev);
2020 pci_disable_device(pdev);
2021 pci_set_drvdata(pdev, NULL);
2025 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2027 struct net_device *dev = pci_get_drvdata(pdev);
2028 struct b44 *bp = netdev_priv(dev);
2030 if (!netif_running(dev))
2033 del_timer_sync(&bp->timer);
2035 spin_lock_irq(&bp->lock);
2038 netif_carrier_off(bp->dev);
2039 netif_device_detach(bp->dev);
2042 spin_unlock_irq(&bp->lock);
2044 free_irq(dev->irq, dev);
2045 pci_disable_device(pdev);
2049 static int b44_resume(struct pci_dev *pdev)
2051 struct net_device *dev = pci_get_drvdata(pdev);
2052 struct b44 *bp = netdev_priv(dev);
2054 pci_restore_state(pdev);
2055 pci_enable_device(pdev);
2056 pci_set_master(pdev);
2058 if (!netif_running(dev))
2061 if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2062 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2064 spin_lock_irq(&bp->lock);
2068 netif_device_attach(bp->dev);
2069 spin_unlock_irq(&bp->lock);
2071 bp->timer.expires = jiffies + HZ;
2072 add_timer(&bp->timer);
2074 b44_enable_ints(bp);
2078 static struct pci_driver b44_driver = {
2079 .name = DRV_MODULE_NAME,
2080 .id_table = b44_pci_tbl,
2081 .probe = b44_init_one,
2082 .remove = __devexit_p(b44_remove_one),
2083 .suspend = b44_suspend,
2084 .resume = b44_resume,
2087 static int __init b44_init(void)
2089 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2091 /* Setup paramaters for syncing RX/TX DMA descriptors */
2092 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2093 dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2095 return pci_module_init(&b44_driver);
2098 static void __exit b44_cleanup(void)
2100 pci_unregister_driver(&b44_driver);
2103 module_init(b44_init);
2104 module_exit(b44_cleanup);