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   1 /* b44.c: Broadcom 4400 device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   5  *
   6  * Distribute under GPL.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/types.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/mii.h>
  16 #include <linux/if_ether.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/pci.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/version.h>
  22 #include <linux/dma-mapping.h>
  23
  24 #include <asm/uaccess.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include "b44.h"
  29
  30 #define DRV_MODULE_NAME         "b44"
  31 #define PFX DRV_MODULE_NAME     ": "
  32 #define DRV_MODULE_VERSION      "0.95"
  33 #define DRV_MODULE_RELDATE      "Aug 3, 2004"
  34
  35 #define B44_DEF_MSG_ENABLE        \
  36         (NETIF_MSG_DRV          | \
  37          NETIF_MSG_PROBE        | \
  38          NETIF_MSG_LINK         | \
  39          NETIF_MSG_TIMER        | \
  40          NETIF_MSG_IFDOWN       | \
  41          NETIF_MSG_IFUP         | \
  42          NETIF_MSG_RX_ERR       | \
  43          NETIF_MSG_TX_ERR)
  44
  45 /* length of time before we decide the hardware is borked,
  46  * and dev->tx_timeout() should be called to fix the problem
  47  */
  48 #define B44_TX_TIMEOUT                  (5 * HZ)
  49
  50 /* hardware minimum and maximum for a single frame's data payload */
  51 #define B44_MIN_MTU                     60
  52 #define B44_MAX_MTU                     1500
  53
  54 #define B44_RX_RING_SIZE                512
  55 #define B44_DEF_RX_RING_PENDING         200
  56 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  57                                  B44_RX_RING_SIZE)
  58 #define B44_TX_RING_SIZE                512
  59 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  60 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  61                                  B44_TX_RING_SIZE)
  62 #define B44_DMA_MASK 0x3fffffff
  63
  64 #define TX_RING_GAP(BP) \
  65         (B44_TX_RING_SIZE - (BP)->tx_pending)
  66 #define TX_BUFFS_AVAIL(BP)                                              \
  67         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  68           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  69           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  70 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  71
  72 #define RX_PKT_BUF_SZ           (1536 + bp->rx_offset + 64)
  73 #define TX_PKT_BUF_SZ           (B44_MAX_MTU + ETH_HLEN + 8)
  74
  75 /* minimum number of free TX descriptors required to wake up TX process */
  76 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  77
  78 static char version[] __devinitdata =
  79         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  80
  81 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  82 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  83 MODULE_LICENSE("GPL");
  84 MODULE_VERSION(DRV_MODULE_VERSION);
  85
  86 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
  87 module_param(b44_debug, int, 0);
  88 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  89
  90 static struct pci_device_id b44_pci_tbl[] = {
  91         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
  92           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  93         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
  94           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  95         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  96           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  97         { }     /* terminate list with empty entry */
  98 };
  99
 100 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
 101
 102 static void b44_halt(struct b44 *);
 103 static void b44_init_rings(struct b44 *);
 104 static void b44_init_hw(struct b44 *);
 105
 106 static int dma_desc_align_mask;
 107 static int dma_desc_sync_size;
 108
 109 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
 110 #define _B44(x...)      # x,
 111 B44_STAT_REG_DECLARE
 112 #undef _B44
 113 };
 114
 115 static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
 116                                                 dma_addr_t dma_base,
 117                                                 unsigned long offset,
 118                                                 enum dma_data_direction dir)
 119 {
 120         dma_sync_single_range_for_device(&pdev->dev, dma_base,
 121                                          offset & dma_desc_align_mask,
 122                                          dma_desc_sync_size, dir);
 123 }
 124
 125 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
 126                                              dma_addr_t dma_base,
 127                                              unsigned long offset,
 128                                              enum dma_data_direction dir)
 129 {
 130         dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
 131                                       offset & dma_desc_align_mask,
 132                                       dma_desc_sync_size, dir);
 133 }
 134
 135 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
 136 {
 137         return readl(bp->regs + reg);
 138 }
 139
 140 static inline void bw32(const struct b44 *bp,
 141                         unsigned long reg, unsigned long val)
 142 {
 143         writel(val, bp->regs + reg);
 144 }
 145
 146 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 147                         u32 bit, unsigned long timeout, const int clear)
 148 {
 149         unsigned long i;
 150
 151         for (i = 0; i < timeout; i++) {
 152                 u32 val = br32(bp, reg);
 153
 154                 if (clear && !(val & bit))
 155                         break;
 156                 if (!clear && (val & bit))
 157                         break;
 158                 udelay(10);
 159         }
 160         if (i == timeout) {
 161                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 162                        "%lx to %s.\n",
 163                        bp->dev->name,
 164                        bit, reg,
 165                        (clear ? "clear" : "set"));
 166                 return -ENODEV;
 167         }
 168         return 0;
 169 }
 170
 171 /* Sonics SiliconBackplane support routines.  ROFL, you should see all the
 172  * buzz words used on this company's website :-)
 173  *
 174  * All of these routines must be invoked with bp->lock held and
 175  * interrupts disabled.
 176  */
 177
 178 #define SB_PCI_DMA             0x40000000      /* Client Mode PCI memory access space (1 GB) */
 179 #define BCM4400_PCI_CORE_ADDR  0x18002000      /* Address of PCI core on BCM4400 cards */
 180
 181 static u32 ssb_get_core_rev(struct b44 *bp)
 182 {
 183         return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
 184 }
 185
 186 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
 187 {
 188         u32 bar_orig, pci_rev, val;
 189
 190         pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
 191         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
 192         pci_rev = ssb_get_core_rev(bp);
 193
 194         val = br32(bp, B44_SBINTVEC);
 195         val |= cores;
 196         bw32(bp, B44_SBINTVEC, val);
 197
 198         val = br32(bp, SSB_PCI_TRANS_2);
 199         val |= SSB_PCI_PREF | SSB_PCI_BURST;
 200         bw32(bp, SSB_PCI_TRANS_2, val);
 201
 202         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
 203
 204         return pci_rev;
 205 }
 206
 207 static void ssb_core_disable(struct b44 *bp)
 208 {
 209         if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
 210                 return;
 211
 212         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
 213         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
 214         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
 215         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 216                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 217         br32(bp, B44_SBTMSLOW);
 218         udelay(1);
 219         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 220         br32(bp, B44_SBTMSLOW);
 221         udelay(1);
 222 }
 223
 224 static void ssb_core_reset(struct b44 *bp)
 225 {
 226         u32 val;
 227
 228         ssb_core_disable(bp);
 229         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 230         br32(bp, B44_SBTMSLOW);
 231         udelay(1);
 232
 233         /* Clear SERR if set, this is a hw bug workaround.  */
 234         if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 235                 bw32(bp, B44_SBTMSHIGH, 0);
 236
 237         val = br32(bp, B44_SBIMSTATE);
 238         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 239                 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 240
 241         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 242         br32(bp, B44_SBTMSLOW);
 243         udelay(1);
 244
 245         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 246         br32(bp, B44_SBTMSLOW);
 247         udelay(1);
 248 }
 249
 250 static int ssb_core_unit(struct b44 *bp)
 251 {
 252 #if 0
 253         u32 val = br32(bp, B44_SBADMATCH0);
 254         u32 base;
 255
 256         type = val & SBADMATCH0_TYPE_MASK;
 257         switch (type) {
 258         case 0:
 259                 base = val & SBADMATCH0_BS0_MASK;
 260                 break;
 261
 262         case 1:
 263                 base = val & SBADMATCH0_BS1_MASK;
 264                 break;
 265
 266         case 2:
 267         default:
 268                 base = val & SBADMATCH0_BS2_MASK;
 269                 break;
 270         };
 271 #endif
 272         return 0;
 273 }
 274
 275 static int ssb_is_core_up(struct b44 *bp)
 276 {
 277         return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 278                 == SBTMSLOW_CLOCK);
 279 }
 280
 281 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 282 {
 283         u32 val;
 284
 285         val  = ((u32) data[2]) << 24;
 286         val |= ((u32) data[3]) << 16;
 287         val |= ((u32) data[4]) <<  8;
 288         val |= ((u32) data[5]) <<  0;
 289         bw32(bp, B44_CAM_DATA_LO, val);
 290         val = (CAM_DATA_HI_VALID |
 291                (((u32) data[0]) << 8) |
 292                (((u32) data[1]) << 0));
 293         bw32(bp, B44_CAM_DATA_HI, val);
 294         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 295                             (index << CAM_CTRL_INDEX_SHIFT)));
 296         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 297 }
 298
 299 static inline void __b44_disable_ints(struct b44 *bp)
 300 {
 301         bw32(bp, B44_IMASK, 0);
 302 }
 303
 304 static void b44_disable_ints(struct b44 *bp)
 305 {
 306         __b44_disable_ints(bp);
 307
 308         /* Flush posted writes. */
 309         br32(bp, B44_IMASK);
 310 }
 311
 312 static void b44_enable_ints(struct b44 *bp)
 313 {
 314         bw32(bp, B44_IMASK, bp->imask);
 315 }
 316
 317 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 318 {
 319         int err;
 320
 321         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 322         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 323                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 324                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 325                              (reg << MDIO_DATA_RA_SHIFT) |
 326                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 327         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 328         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 329
 330         return err;
 331 }
 332
 333 static int b44_writephy(struct b44 *bp, int reg, u32 val)
 334 {
 335         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 336         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 337                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 338                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 339                              (reg << MDIO_DATA_RA_SHIFT) |
 340                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 341                              (val & MDIO_DATA_DATA)));
 342         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 343 }
 344
 345 /* miilib interface */
 346 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 347  * due to code existing before miilib use was added to this driver.
 348  * Someone should remove this artificial driver limitation in
 349  * b44_{read,write}phy.  bp->phy_addr itself is fine (and needed).
 350  */
 351 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 352 {
 353         u32 val;
 354         struct b44 *bp = netdev_priv(dev);
 355         int rc = b44_readphy(bp, location, &val);
 356         if (rc)
 357                 return 0xffffffff;
 358         return val;
 359 }
 360
 361 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 362                          int val)
 363 {
 364         struct b44 *bp = netdev_priv(dev);
 365         b44_writephy(bp, location, val);
 366 }
 367
 368 static int b44_phy_reset(struct b44 *bp)
 369 {
 370         u32 val;
 371         int err;
 372
 373         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 374         if (err)
 375                 return err;
 376         udelay(100);
 377         err = b44_readphy(bp, MII_BMCR, &val);
 378         if (!err) {
 379                 if (val & BMCR_RESET) {
 380                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 381                                bp->dev->name);
 382                         err = -ENODEV;
 383                 }
 384         }
 385
 386         return 0;
 387 }
 388
 389 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 390 {
 391         u32 val;
 392
 393         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 394         bp->flags |= pause_flags;
 395
 396         val = br32(bp, B44_RXCONFIG);
 397         if (pause_flags & B44_FLAG_RX_PAUSE)
 398                 val |= RXCONFIG_FLOW;
 399         else
 400                 val &= ~RXCONFIG_FLOW;
 401         bw32(bp, B44_RXCONFIG, val);
 402
 403         val = br32(bp, B44_MAC_FLOW);
 404         if (pause_flags & B44_FLAG_TX_PAUSE)
 405                 val |= (MAC_FLOW_PAUSE_ENAB |
 406                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 407         else
 408                 val &= ~MAC_FLOW_PAUSE_ENAB;
 409         bw32(bp, B44_MAC_FLOW, val);
 410 }
 411
 412 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 413 {
 414         u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
 415                                       B44_FLAG_RX_PAUSE);
 416
 417         if (local & ADVERTISE_PAUSE_CAP) {
 418                 if (local & ADVERTISE_PAUSE_ASYM) {
 419                         if (remote & LPA_PAUSE_CAP)
 420                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 421                                                B44_FLAG_RX_PAUSE);
 422                         else if (remote & LPA_PAUSE_ASYM)
 423                                 pause_enab |= B44_FLAG_RX_PAUSE;
 424                 } else {
 425                         if (remote & LPA_PAUSE_CAP)
 426                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 427                                                B44_FLAG_RX_PAUSE);
 428                 }
 429         } else if (local & ADVERTISE_PAUSE_ASYM) {
 430                 if ((remote & LPA_PAUSE_CAP) &&
 431                     (remote & LPA_PAUSE_ASYM))
 432                         pause_enab |= B44_FLAG_TX_PAUSE;
 433         }
 434
 435         __b44_set_flow_ctrl(bp, pause_enab);
 436 }
 437
 438 static int b44_setup_phy(struct b44 *bp)
 439 {
 440         u32 val;
 441         int err;
 442
 443         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 444                 goto out;
 445         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 446                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 447                 goto out;
 448         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 449                 goto out;
 450         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 451                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 452                 goto out;
 453
 454         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 455                 u32 adv = ADVERTISE_CSMA;
 456
 457                 if (bp->flags & B44_FLAG_ADV_10HALF)
 458                         adv |= ADVERTISE_10HALF;
 459                 if (bp->flags & B44_FLAG_ADV_10FULL)
 460                         adv |= ADVERTISE_10FULL;
 461                 if (bp->flags & B44_FLAG_ADV_100HALF)
 462                         adv |= ADVERTISE_100HALF;
 463                 if (bp->flags & B44_FLAG_ADV_100FULL)
 464                         adv |= ADVERTISE_100FULL;
 465
 466                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 467                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 468
 469                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 470                         goto out;
 471                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 472                                                        BMCR_ANRESTART))) != 0)
 473                         goto out;
 474         } else {
 475                 u32 bmcr;
 476
 477                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 478                         goto out;
 479                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 480                 if (bp->flags & B44_FLAG_100_BASE_T)
 481                         bmcr |= BMCR_SPEED100;
 482                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 483                         bmcr |= BMCR_FULLDPLX;
 484                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 485                         goto out;
 486
 487                 /* Since we will not be negotiating there is no safe way
 488                  * to determine if the link partner supports flow control
 489                  * or not.  So just disable it completely in this case.
 490                  */
 491                 b44_set_flow_ctrl(bp, 0, 0);
 492         }
 493
 494 out:
 495         return err;
 496 }
 497
 498 static void b44_stats_update(struct b44 *bp)
 499 {
 500         unsigned long reg;
 501         u32 *val;
 502
 503         val = &bp->hw_stats.tx_good_octets;
 504         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 505                 *val++ += br32(bp, reg);
 506         }
 507
 508         /* Pad */
 509         reg += 8*4UL;
 510
 511         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 512                 *val++ += br32(bp, reg);
 513         }
 514 }
 515
 516 static void b44_link_report(struct b44 *bp)
 517 {
 518         if (!netif_carrier_ok(bp->dev)) {
 519                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 520         } else {
 521                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 522                        bp->dev->name,
 523                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 524                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 525
 526                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 527                        "%s for RX.\n",
 528                        bp->dev->name,
 529                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 530                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 531         }
 532 }
 533
 534 static void b44_check_phy(struct b44 *bp)
 535 {
 536         u32 bmsr, aux;
 537
 538         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 539             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 540             (bmsr != 0xffff)) {
 541                 if (aux & MII_AUXCTRL_SPEED)
 542                         bp->flags |= B44_FLAG_100_BASE_T;
 543                 else
 544                         bp->flags &= ~B44_FLAG_100_BASE_T;
 545                 if (aux & MII_AUXCTRL_DUPLEX)
 546                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 547                 else
 548                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 549
 550                 if (!netif_carrier_ok(bp->dev) &&
 551                     (bmsr & BMSR_LSTATUS)) {
 552                         u32 val = br32(bp, B44_TX_CTRL);
 553                         u32 local_adv, remote_adv;
 554
 555                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 556                                 val |= TX_CTRL_DUPLEX;
 557                         else
 558                                 val &= ~TX_CTRL_DUPLEX;
 559                         bw32(bp, B44_TX_CTRL, val);
 560
 561                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 562                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 563                             !b44_readphy(bp, MII_LPA, &remote_adv))
 564                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 565
 566                         /* Link now up */
 567                         netif_carrier_on(bp->dev);
 568                         b44_link_report(bp);
 569                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 570                         /* Link now down */
 571                         netif_carrier_off(bp->dev);
 572                         b44_link_report(bp);
 573                 }
 574
 575                 if (bmsr & BMSR_RFAULT)
 576                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 577                                bp->dev->name);
 578                 if (bmsr & BMSR_JCD)
 579                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 580                                bp->dev->name);
 581         }
 582 }
 583
 584 static void b44_timer(unsigned long __opaque)
 585 {
 586         struct b44 *bp = (struct b44 *) __opaque;
 587
 588         spin_lock_irq(&bp->lock);
 589
 590         b44_check_phy(bp);
 591
 592         b44_stats_update(bp);
 593
 594         spin_unlock_irq(&bp->lock);
 595
 596         bp->timer.expires = jiffies + HZ;
 597         add_timer(&bp->timer);
 598 }
 599
 600 static void b44_tx(struct b44 *bp)
 601 {
 602         u32 cur, cons;
 603
 604         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 605         cur /= sizeof(struct dma_desc);
 606
 607         /* XXX needs updating when NETIF_F_SG is supported */
 608         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 609                 struct ring_info *rp = &bp->tx_buffers[cons];
 610                 struct sk_buff *skb = rp->skb;
 611
 612                 if (unlikely(skb == NULL))
 613                         BUG();
 614
 615                 pci_unmap_single(bp->pdev,
 616                                  pci_unmap_addr(rp, mapping),
 617                                  skb->len,
 618                                  PCI_DMA_TODEVICE);
 619                 rp->skb = NULL;
 620                 dev_kfree_skb_irq(skb);
 621         }
 622
 623         bp->tx_cons = cons;
 624         if (netif_queue_stopped(bp->dev) &&
 625             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 626                 netif_wake_queue(bp->dev);
 627
 628         bw32(bp, B44_GPTIMER, 0);
 629 }
 630
 631 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 632  * before the DMA address you give it.  So we allocate 30 more bytes
 633  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 634  * point the chip at 30 bytes past where the rx_header will go.
 635  */
 636 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 637 {
 638         struct dma_desc *dp;
 639         struct ring_info *src_map, *map;
 640         struct rx_header *rh;
 641         struct sk_buff *skb;
 642         dma_addr_t mapping;
 643         int dest_idx;
 644         u32 ctrl;
 645
 646         src_map = NULL;
 647         if (src_idx >= 0)
 648                 src_map = &bp->rx_buffers[src_idx];
 649         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 650         map = &bp->rx_buffers[dest_idx];
 651         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
 652         if (skb == NULL)
 653                 return -ENOMEM;
 654
 655         mapping = pci_map_single(bp->pdev, skb->data,
 656                                  RX_PKT_BUF_SZ,
 657                                  PCI_DMA_FROMDEVICE);
 658
 659         /* Hardware bug work-around, the chip is unable to do PCI DMA
 660            to/from anything above 1GB :-( */
 661         if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
 662                 /* Sigh... */
 663                 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 664                 dev_kfree_skb_any(skb);
 665                 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
 666                 if (skb == NULL)
 667                         return -ENOMEM;
 668                 mapping = pci_map_single(bp->pdev, skb->data,
 669                                          RX_PKT_BUF_SZ,
 670                                          PCI_DMA_FROMDEVICE);
 671                 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
 672                         pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 673                         dev_kfree_skb_any(skb);
 674                         return -ENOMEM;
 675                 }
 676         }
 677
 678         skb->dev = bp->dev;
 679         skb_reserve(skb, bp->rx_offset);
 680
 681         rh = (struct rx_header *)
 682                 (skb->data - bp->rx_offset);
 683         rh->len = 0;
 684         rh->flags = 0;
 685
 686         map->skb = skb;
 687         pci_unmap_addr_set(map, mapping, mapping);
 688
 689         if (src_map != NULL)
 690                 src_map->skb = NULL;
 691
 692         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
 693         if (dest_idx == (B44_RX_RING_SIZE - 1))
 694                 ctrl |= DESC_CTRL_EOT;
 695
 696         dp = &bp->rx_ring[dest_idx];
 697         dp->ctrl = cpu_to_le32(ctrl);
 698         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 699
 700         if (bp->flags & B44_FLAG_RX_RING_HACK)
 701                 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 702                                              dest_idx * sizeof(dp),
 703                                              DMA_BIDIRECTIONAL);
 704
 705         return RX_PKT_BUF_SZ;
 706 }
 707
 708 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 709 {
 710         struct dma_desc *src_desc, *dest_desc;
 711         struct ring_info *src_map, *dest_map;
 712         struct rx_header *rh;
 713         int dest_idx;
 714         u32 ctrl;
 715
 716         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 717         dest_desc = &bp->rx_ring[dest_idx];
 718         dest_map = &bp->rx_buffers[dest_idx];
 719         src_desc = &bp->rx_ring[src_idx];
 720         src_map = &bp->rx_buffers[src_idx];
 721
 722         dest_map->skb = src_map->skb;
 723         rh = (struct rx_header *) src_map->skb->data;
 724         rh->len = 0;
 725         rh->flags = 0;
 726         pci_unmap_addr_set(dest_map, mapping,
 727                            pci_unmap_addr(src_map, mapping));
 728
 729         if (bp->flags & B44_FLAG_RX_RING_HACK)
 730                 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
 731                                           src_idx * sizeof(src_desc),
 732                                           DMA_BIDIRECTIONAL);
 733
 734         ctrl = src_desc->ctrl;
 735         if (dest_idx == (B44_RX_RING_SIZE - 1))
 736                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 737         else
 738                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 739
 740         dest_desc->ctrl = ctrl;
 741         dest_desc->addr = src_desc->addr;
 742
 743         src_map->skb = NULL;
 744
 745         if (bp->flags & B44_FLAG_RX_RING_HACK)
 746                 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 747                                              dest_idx * sizeof(dest_desc),
 748                                              DMA_BIDIRECTIONAL);
 749
 750         pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
 751                                        RX_PKT_BUF_SZ,
 752                                        PCI_DMA_FROMDEVICE);
 753 }
 754
 755 static int b44_rx(struct b44 *bp, int budget)
 756 {
 757         int received;
 758         u32 cons, prod;
 759
 760         received = 0;
 761         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 762         prod /= sizeof(struct dma_desc);
 763         cons = bp->rx_cons;
 764
 765         while (cons != prod && budget > 0) {
 766                 struct ring_info *rp = &bp->rx_buffers[cons];
 767                 struct sk_buff *skb = rp->skb;
 768                 dma_addr_t map = pci_unmap_addr(rp, mapping);
 769                 struct rx_header *rh;
 770                 u16 len;
 771
 772                 pci_dma_sync_single_for_cpu(bp->pdev, map,
 773                                             RX_PKT_BUF_SZ,
 774                                             PCI_DMA_FROMDEVICE);
 775                 rh = (struct rx_header *) skb->data;
 776                 len = cpu_to_le16(rh->len);
 777                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
 778                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 779                 drop_it:
 780                         b44_recycle_rx(bp, cons, bp->rx_prod);
 781                 drop_it_no_recycle:
 782                         bp->stats.rx_dropped++;
 783                         goto next_pkt;
 784                 }
 785
 786                 if (len == 0) {
 787                         int i = 0;
 788
 789                         do {
 790                                 udelay(2);
 791                                 barrier();
 792                                 len = cpu_to_le16(rh->len);
 793                         } while (len == 0 && i++ < 5);
 794                         if (len == 0)
 795                                 goto drop_it;
 796                 }
 797
 798                 /* Omit CRC. */
 799                 len -= 4;
 800
 801                 if (len > RX_COPY_THRESHOLD) {
 802                         int skb_size;
 803                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 804                         if (skb_size < 0)
 805                                 goto drop_it;
 806                         pci_unmap_single(bp->pdev, map,
 807                                          skb_size, PCI_DMA_FROMDEVICE);
 808                         /* Leave out rx_header */
 809                         skb_put(skb, len+bp->rx_offset);
 810                         skb_pull(skb,bp->rx_offset);
 811                 } else {
 812                         struct sk_buff *copy_skb;
 813
 814                         b44_recycle_rx(bp, cons, bp->rx_prod);
 815                         copy_skb = dev_alloc_skb(len + 2);
 816                         if (copy_skb == NULL)
 817                                 goto drop_it_no_recycle;
 818
 819                         copy_skb->dev = bp->dev;
 820                         skb_reserve(copy_skb, 2);
 821                         skb_put(copy_skb, len);
 822                         /* DMA sync done above, copy just the actual packet */
 823                         memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
 824
 825                         skb = copy_skb;
 826                 }
 827                 skb->ip_summed = CHECKSUM_NONE;
 828                 skb->protocol = eth_type_trans(skb, bp->dev);
 829                 netif_receive_skb(skb);
 830                 bp->dev->last_rx = jiffies;
 831                 received++;
 832                 budget--;
 833         next_pkt:
 834                 bp->rx_prod = (bp->rx_prod + 1) &
 835                         (B44_RX_RING_SIZE - 1);
 836                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 837         }
 838
 839         bp->rx_cons = cons;
 840         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 841
 842         return received;
 843 }
 844
 845 static int b44_poll(struct net_device *netdev, int *budget)
 846 {
 847         struct b44 *bp = netdev_priv(netdev);
 848         int done;
 849
 850         spin_lock_irq(&bp->lock);
 851
 852         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 853                 /* spin_lock(&bp->tx_lock); */
 854                 b44_tx(bp);
 855                 /* spin_unlock(&bp->tx_lock); */
 856         }
 857         spin_unlock_irq(&bp->lock);
 858
 859         done = 1;
 860         if (bp->istat & ISTAT_RX) {
 861                 int orig_budget = *budget;
 862                 int work_done;
 863
 864                 if (orig_budget > netdev->quota)
 865                         orig_budget = netdev->quota;
 866
 867                 work_done = b44_rx(bp, orig_budget);
 868
 869                 *budget -= work_done;
 870                 netdev->quota -= work_done;
 871
 872                 if (work_done >= orig_budget)
 873                         done = 0;
 874         }
 875
 876         if (bp->istat & ISTAT_ERRORS) {
 877                 spin_lock_irq(&bp->lock);
 878                 b44_halt(bp);
 879                 b44_init_rings(bp);
 880                 b44_init_hw(bp);
 881                 netif_wake_queue(bp->dev);
 882                 spin_unlock_irq(&bp->lock);
 883                 done = 1;
 884         }
 885
 886         if (done) {
 887                 netif_rx_complete(netdev);
 888                 b44_enable_ints(bp);
 889         }
 890
 891         return (done ? 0 : 1);
 892 }
 893
 894 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 895 {
 896         struct net_device *dev = dev_id;
 897         struct b44 *bp = netdev_priv(dev);
 898         u32 istat, imask;
 899         int handled = 0;
 900
 901         spin_lock(&bp->lock);
 902
 903         istat = br32(bp, B44_ISTAT);
 904         imask = br32(bp, B44_IMASK);
 905
 906         /* ??? What the fuck is the purpose of the interrupt mask
 907          * ??? register if we have to mask it out by hand anyways?
 908          */
 909         istat &= imask;
 910         if (istat) {
 911                 handled = 1;
 912                 if (netif_rx_schedule_prep(dev)) {
 913                         /* NOTE: These writes are posted by the readback of
 914                          *       the ISTAT register below.
 915                          */
 916                         bp->istat = istat;
 917                         __b44_disable_ints(bp);
 918                         __netif_rx_schedule(dev);
 919                 } else {
 920                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 921                                dev->name);
 922                 }
 923
 924                 bw32(bp, B44_ISTAT, istat);
 925                 br32(bp, B44_ISTAT);
 926         }
 927         spin_unlock(&bp->lock);
 928         return IRQ_RETVAL(handled);
 929 }
 930
 931 static void b44_tx_timeout(struct net_device *dev)
 932 {
 933         struct b44 *bp = netdev_priv(dev);
 934
 935         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 936                dev->name);
 937
 938         spin_lock_irq(&bp->lock);
 939
 940         b44_halt(bp);
 941         b44_init_rings(bp);
 942         b44_init_hw(bp);
 943
 944         spin_unlock_irq(&bp->lock);
 945
 946         b44_enable_ints(bp);
 947
 948         netif_wake_queue(dev);
 949 }
 950
 951 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 952 {
 953         struct b44 *bp = netdev_priv(dev);
 954         struct sk_buff *bounce_skb;
 955         int rc = NETDEV_TX_OK;
 956         dma_addr_t mapping;
 957         u32 len, entry, ctrl;
 958
 959         len = skb->len;
 960         spin_lock_irq(&bp->lock);
 961
 962         /* This is a hard error, log it. */
 963         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 964                 netif_stop_queue(dev);
 965                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 966                        dev->name);
 967                 goto err_out;
 968         }
 969
 970         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
 971         if (mapping + len > B44_DMA_MASK) {
 972                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 973                 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
 974
 975                 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
 976                                              GFP_ATOMIC|GFP_DMA);
 977                 if (!bounce_skb)
 978                         goto err_out;
 979
 980                 mapping = pci_map_single(bp->pdev, bounce_skb->data,
 981                                          len, PCI_DMA_TODEVICE);
 982                 if (mapping + len > B44_DMA_MASK) {
 983                         pci_unmap_single(bp->pdev, mapping,
 984                                          len, PCI_DMA_TODEVICE);
 985                         dev_kfree_skb_any(bounce_skb);
 986                         goto err_out;
 987                 }
 988
 989                 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
 990                 dev_kfree_skb_any(skb);
 991                 skb = bounce_skb;
 992         }
 993
 994         entry = bp->tx_prod;
 995         bp->tx_buffers[entry].skb = skb;
 996         pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
 997
 998         ctrl  = (len & DESC_CTRL_LEN);
 999         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1000         if (entry == (B44_TX_RING_SIZE - 1))
1001                 ctrl |= DESC_CTRL_EOT;
1002
1003         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1004         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1005
1006         if (bp->flags & B44_FLAG_TX_RING_HACK)
1007                 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1008                                              entry * sizeof(bp->tx_ring[0]),
1009                                              DMA_TO_DEVICE);
1010
1011         entry = NEXT_TX(entry);
1012
1013         bp->tx_prod = entry;
1014
1015         wmb();
1016
1017         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1018         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1019                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1020         if (bp->flags & B44_FLAG_REORDER_BUG)
1021                 br32(bp, B44_DMATX_PTR);
1022
1023         if (TX_BUFFS_AVAIL(bp) < 1)
1024                 netif_stop_queue(dev);
1025
1026         dev->trans_start = jiffies;
1027
1028 out_unlock:
1029         spin_unlock_irq(&bp->lock);
1030
1031         return rc;
1032
1033 err_out:
1034         rc = NETDEV_TX_BUSY;
1035         goto out_unlock;
1036 }
1037
1038 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1039 {
1040         struct b44 *bp = netdev_priv(dev);
1041
1042         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1043                 return -EINVAL;
1044
1045         if (!netif_running(dev)) {
1046                 /* We'll just catch it later when the
1047                  * device is up'd.
1048                  */
1049                 dev->mtu = new_mtu;
1050                 return 0;
1051         }
1052
1053         spin_lock_irq(&bp->lock);
1054         b44_halt(bp);
1055         dev->mtu = new_mtu;
1056         b44_init_rings(bp);
1057         b44_init_hw(bp);
1058         spin_unlock_irq(&bp->lock);
1059
1060         b44_enable_ints(bp);
1061
1062         return 0;
1063 }
1064
1065 /* Free up pending packets in all rx/tx rings.
1066  *
1067  * The chip has been shut down and the driver detached from
1068  * the networking, so no interrupts or new tx packets will
1069  * end up in the driver.  bp->lock is not held and we are not
1070  * in an interrupt context and thus may sleep.
1071  */
1072 static void b44_free_rings(struct b44 *bp)
1073 {
1074         struct ring_info *rp;
1075         int i;
1076
1077         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1078                 rp = &bp->rx_buffers[i];
1079
1080                 if (rp->skb == NULL)
1081                         continue;
1082                 pci_unmap_single(bp->pdev,
1083                                  pci_unmap_addr(rp, mapping),
1084                                  RX_PKT_BUF_SZ,
1085                                  PCI_DMA_FROMDEVICE);
1086                 dev_kfree_skb_any(rp->skb);
1087                 rp->skb = NULL;
1088         }
1089
1090         /* XXX needs changes once NETIF_F_SG is set... */
1091         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1092                 rp = &bp->tx_buffers[i];
1093
1094                 if (rp->skb == NULL)
1095                         continue;
1096                 pci_unmap_single(bp->pdev,
1097                                  pci_unmap_addr(rp, mapping),
1098                                  rp->skb->len,
1099                                  PCI_DMA_TODEVICE);
1100                 dev_kfree_skb_any(rp->skb);
1101                 rp->skb = NULL;
1102         }
1103 }
1104
1105 /* Initialize tx/rx rings for packet processing.
1106  *
1107  * The chip has been shut down and the driver detached from
1108  * the networking, so no interrupts or new tx packets will
1109  * end up in the driver.
1110  */
1111 static void b44_init_rings(struct b44 *bp)
1112 {
1113         int i;
1114
1115         b44_free_rings(bp);
1116
1117         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1118         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1119
1120         if (bp->flags & B44_FLAG_RX_RING_HACK)
1121                 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1122                                            DMA_TABLE_BYTES,
1123                                            PCI_DMA_BIDIRECTIONAL);
1124
1125         if (bp->flags & B44_FLAG_TX_RING_HACK)
1126                 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1127                                            DMA_TABLE_BYTES,
1128                                            PCI_DMA_TODEVICE);
1129
1130         for (i = 0; i < bp->rx_pending; i++) {
1131                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1132                         break;
1133         }
1134 }
1135
1136 /*
1137  * Must not be invoked with interrupt sources disabled and
1138  * the hardware shutdown down.
1139  */
1140 static void b44_free_consistent(struct b44 *bp)
1141 {
1142         kfree(bp->rx_buffers);
1143         bp->rx_buffers = NULL;
1144         kfree(bp->tx_buffers);
1145         bp->tx_buffers = NULL;
1146         if (bp->rx_ring) {
1147                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1148                         dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1149                                          DMA_TABLE_BYTES,
1150                                          DMA_BIDIRECTIONAL);
1151                         kfree(bp->rx_ring);
1152                 } else
1153                         pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1154                                             bp->rx_ring, bp->rx_ring_dma);
1155                 bp->rx_ring = NULL;
1156                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1157         }
1158         if (bp->tx_ring) {
1159                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1160                         dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1161                                          DMA_TABLE_BYTES,
1162                                          DMA_TO_DEVICE);
1163                         kfree(bp->tx_ring);
1164                 } else
1165                         pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1166                                             bp->tx_ring, bp->tx_ring_dma);
1167                 bp->tx_ring = NULL;
1168                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1169         }
1170 }
1171
1172 /*
1173  * Must not be invoked with interrupt sources disabled and
1174  * the hardware shutdown down.  Can sleep.
1175  */
1176 static int b44_alloc_consistent(struct b44 *bp)
1177 {
1178         int size;
1179
1180         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1181         bp->rx_buffers = kzalloc(size, GFP_KERNEL);
1182         if (!bp->rx_buffers)
1183                 goto out_err;
1184
1185         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1186         bp->tx_buffers = kzalloc(size, GFP_KERNEL);
1187         if (!bp->tx_buffers)
1188                 goto out_err;
1189
1190         size = DMA_TABLE_BYTES;
1191         bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1192         if (!bp->rx_ring) {
1193                 /* Allocation may have failed due to pci_alloc_consistent
1194                    insisting on use of GFP_DMA, which is more restrictive
1195                    than necessary...  */
1196                 struct dma_desc *rx_ring;
1197                 dma_addr_t rx_ring_dma;
1198
1199                 rx_ring = kzalloc(size, GFP_KERNEL);
1200                 if (!rx_ring)
1201                         goto out_err;
1202
1203                 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1204                                              DMA_TABLE_BYTES,
1205                                              DMA_BIDIRECTIONAL);
1206
1207                 if (rx_ring_dma + size > B44_DMA_MASK) {
1208                         kfree(rx_ring);
1209                         goto out_err;
1210                 }
1211
1212                 bp->rx_ring = rx_ring;
1213                 bp->rx_ring_dma = rx_ring_dma;
1214                 bp->flags |= B44_FLAG_RX_RING_HACK;
1215         }
1216
1217         bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1218         if (!bp->tx_ring) {
1219                 /* Allocation may have failed due to pci_alloc_consistent
1220                    insisting on use of GFP_DMA, which is more restrictive
1221                    than necessary...  */
1222                 struct dma_desc *tx_ring;
1223                 dma_addr_t tx_ring_dma;
1224
1225                 tx_ring = kzalloc(size, GFP_KERNEL);
1226                 if (!tx_ring)
1227                         goto out_err;
1228
1229                 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1230                                              DMA_TABLE_BYTES,
1231                                              DMA_TO_DEVICE);
1232
1233                 if (tx_ring_dma + size > B44_DMA_MASK) {
1234                         kfree(tx_ring);
1235                         goto out_err;
1236                 }
1237
1238                 bp->tx_ring = tx_ring;
1239                 bp->tx_ring_dma = tx_ring_dma;
1240                 bp->flags |= B44_FLAG_TX_RING_HACK;
1241         }
1242
1243         return 0;
1244
1245 out_err:
1246         b44_free_consistent(bp);
1247         return -ENOMEM;
1248 }
1249
1250 /* bp->lock is held. */
1251 static void b44_clear_stats(struct b44 *bp)
1252 {
1253         unsigned long reg;
1254
1255         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1256         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1257                 br32(bp, reg);
1258         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1259                 br32(bp, reg);
1260 }
1261
1262 /* bp->lock is held. */
1263 static void b44_chip_reset(struct b44 *bp)
1264 {
1265         if (ssb_is_core_up(bp)) {
1266                 bw32(bp, B44_RCV_LAZY, 0);
1267                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1268                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1269                 bw32(bp, B44_DMATX_CTRL, 0);
1270                 bp->tx_prod = bp->tx_cons = 0;
1271                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1272                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1273                                      100, 0);
1274                 }
1275                 bw32(bp, B44_DMARX_CTRL, 0);
1276                 bp->rx_prod = bp->rx_cons = 0;
1277         } else {
1278                 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1279                                    SBINTVEC_ENET0 :
1280                                    SBINTVEC_ENET1));
1281         }
1282
1283         ssb_core_reset(bp);
1284
1285         b44_clear_stats(bp);
1286
1287         /* Make PHY accessible. */
1288         bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1289                              (0x0d & MDIO_CTRL_MAXF_MASK)));
1290         br32(bp, B44_MDIO_CTRL);
1291
1292         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1293                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1294                 br32(bp, B44_ENET_CTRL);
1295                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1296         } else {
1297                 u32 val = br32(bp, B44_DEVCTRL);
1298
1299                 if (val & DEVCTRL_EPR) {
1300                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1301                         br32(bp, B44_DEVCTRL);
1302                         udelay(100);
1303                 }
1304                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1305         }
1306 }
1307
1308 /* bp->lock is held. */
1309 static void b44_halt(struct b44 *bp)
1310 {
1311         b44_disable_ints(bp);
1312         b44_chip_reset(bp);
1313 }
1314
1315 /* bp->lock is held. */
1316 static void __b44_set_mac_addr(struct b44 *bp)
1317 {
1318         bw32(bp, B44_CAM_CTRL, 0);
1319         if (!(bp->dev->flags & IFF_PROMISC)) {
1320                 u32 val;
1321
1322                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1323                 val = br32(bp, B44_CAM_CTRL);
1324                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1325         }
1326 }
1327
1328 static int b44_set_mac_addr(struct net_device *dev, void *p)
1329 {
1330         struct b44 *bp = netdev_priv(dev);
1331         struct sockaddr *addr = p;
1332
1333         if (netif_running(dev))
1334                 return -EBUSY;
1335
1336         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1337
1338         spin_lock_irq(&bp->lock);
1339         __b44_set_mac_addr(bp);
1340         spin_unlock_irq(&bp->lock);
1341
1342         return 0;
1343 }
1344
1345 /* Called at device open time to get the chip ready for
1346  * packet processing.  Invoked with bp->lock held.
1347  */
1348 static void __b44_set_rx_mode(struct net_device *);
1349 static void b44_init_hw(struct b44 *bp)
1350 {
1351         u32 val;
1352
1353         b44_chip_reset(bp);
1354         b44_phy_reset(bp);
1355         b44_setup_phy(bp);
1356
1357         /* Enable CRC32, set proper LED modes and power on PHY */
1358         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1359         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1360
1361         /* This sets the MAC address too.  */
1362         __b44_set_rx_mode(bp->dev);
1363
1364         /* MTU + eth header + possible VLAN tag + struct rx_header */
1365         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1366         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1367
1368         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1369         bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1370         bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1371         bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1372                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1373         bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1374
1375         bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1376         bp->rx_prod = bp->rx_pending;
1377
1378         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1379
1380         val = br32(bp, B44_ENET_CTRL);
1381         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1382 }
1383
1384 static int b44_open(struct net_device *dev)
1385 {
1386         struct b44 *bp = netdev_priv(dev);
1387         int err;
1388
1389         err = b44_alloc_consistent(bp);
1390         if (err)
1391                 return err;
1392
1393         err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1394         if (err)
1395                 goto err_out_free;
1396
1397         spin_lock_irq(&bp->lock);
1398
1399         b44_init_rings(bp);
1400         b44_init_hw(bp);
1401         bp->flags |= B44_FLAG_INIT_COMPLETE;
1402
1403         netif_carrier_off(dev);
1404         b44_check_phy(bp);
1405
1406         spin_unlock_irq(&bp->lock);
1407
1408         init_timer(&bp->timer);
1409         bp->timer.expires = jiffies + HZ;
1410         bp->timer.data = (unsigned long) bp;
1411         bp->timer.function = b44_timer;
1412         add_timer(&bp->timer);
1413
1414         b44_enable_ints(bp);
1415
1416         return 0;
1417
1418 err_out_free:
1419         b44_free_consistent(bp);
1420         return err;
1421 }
1422
1423 #if 0
1424 /*static*/ void b44_dump_state(struct b44 *bp)
1425 {
1426         u32 val32, val32_2, val32_3, val32_4, val32_5;
1427         u16 val16;
1428
1429         pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1430         printk("DEBUG: PCI status [%04x] \n", val16);
1431
1432 }
1433 #endif
1434
1435 #ifdef CONFIG_NET_POLL_CONTROLLER
1436 /*
1437  * Polling receive - used by netconsole and other diagnostic tools
1438  * to allow network i/o with interrupts disabled.
1439  */
1440 static void b44_poll_controller(struct net_device *dev)
1441 {
1442         disable_irq(dev->irq);
1443         b44_interrupt(dev->irq, dev, NULL);
1444         enable_irq(dev->irq);
1445 }
1446 #endif
1447
1448 static int b44_close(struct net_device *dev)
1449 {
1450         struct b44 *bp = netdev_priv(dev);
1451
1452         netif_stop_queue(dev);
1453
1454         del_timer_sync(&bp->timer);
1455
1456         spin_lock_irq(&bp->lock);
1457
1458 #if 0
1459         b44_dump_state(bp);
1460 #endif
1461         b44_halt(bp);
1462         b44_free_rings(bp);
1463         bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1464         netif_carrier_off(bp->dev);
1465
1466         spin_unlock_irq(&bp->lock);
1467
1468         free_irq(dev->irq, dev);
1469
1470         b44_free_consistent(bp);
1471
1472         return 0;
1473 }
1474
1475 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1476 {
1477         struct b44 *bp = netdev_priv(dev);
1478         struct net_device_stats *nstat = &bp->stats;
1479         struct b44_hw_stats *hwstat = &bp->hw_stats;
1480
1481         /* Convert HW stats into netdevice stats. */
1482         nstat->rx_packets = hwstat->rx_pkts;
1483         nstat->tx_packets = hwstat->tx_pkts;
1484         nstat->rx_bytes   = hwstat->rx_octets;
1485         nstat->tx_bytes   = hwstat->tx_octets;
1486         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1487                              hwstat->tx_oversize_pkts +
1488                              hwstat->tx_underruns +
1489                              hwstat->tx_excessive_cols +
1490                              hwstat->tx_late_cols);
1491         nstat->multicast  = hwstat->tx_multicast_pkts;
1492         nstat->collisions = hwstat->tx_total_cols;
1493
1494         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1495                                    hwstat->rx_undersize);
1496         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1497         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1498         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1499         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1500                                    hwstat->rx_oversize_pkts +
1501                                    hwstat->rx_missed_pkts +
1502                                    hwstat->rx_crc_align_errs +
1503                                    hwstat->rx_undersize +
1504                                    hwstat->rx_crc_errs +
1505                                    hwstat->rx_align_errs +
1506                                    hwstat->rx_symbol_errs);
1507
1508         nstat->tx_aborted_errors = hwstat->tx_underruns;
1509 #if 0
1510         /* Carrier lost counter seems to be broken for some devices */
1511         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1512 #endif
1513
1514         return nstat;
1515 }
1516
1517 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1518 {
1519         struct dev_mc_list *mclist;
1520         int i, num_ents;
1521
1522         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1523         mclist = dev->mc_list;
1524         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1525                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1526         }
1527         return i+1;
1528 }
1529
1530 static void __b44_set_rx_mode(struct net_device *dev)
1531 {
1532         struct b44 *bp = netdev_priv(dev);
1533         u32 val;
1534
1535         val = br32(bp, B44_RXCONFIG);
1536         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1537         if (dev->flags & IFF_PROMISC) {
1538                 val |= RXCONFIG_PROMISC;
1539                 bw32(bp, B44_RXCONFIG, val);
1540         } else {
1541                 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1542                 int i = 0;
1543
1544                 __b44_set_mac_addr(bp);
1545
1546                 if (dev->flags & IFF_ALLMULTI)
1547                         val |= RXCONFIG_ALLMULTI;
1548                 else
1549                         i = __b44_load_mcast(bp, dev);
1550
1551                 for (; i < 64; i++) {
1552                         __b44_cam_write(bp, zero, i);
1553                 }
1554                 bw32(bp, B44_RXCONFIG, val);
1555                 val = br32(bp, B44_CAM_CTRL);
1556                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1557         }
1558 }
1559
1560 static void b44_set_rx_mode(struct net_device *dev)
1561 {
1562         struct b44 *bp = netdev_priv(dev);
1563
1564         spin_lock_irq(&bp->lock);
1565         __b44_set_rx_mode(dev);
1566         spin_unlock_irq(&bp->lock);
1567 }
1568
1569 static u32 b44_get_msglevel(struct net_device *dev)
1570 {
1571         struct b44 *bp = netdev_priv(dev);
1572         return bp->msg_enable;
1573 }
1574
1575 static void b44_set_msglevel(struct net_device *dev, u32 value)
1576 {
1577         struct b44 *bp = netdev_priv(dev);
1578         bp->msg_enable = value;
1579 }
1580
1581 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1582 {
1583         struct b44 *bp = netdev_priv(dev);
1584         struct pci_dev *pci_dev = bp->pdev;
1585
1586         strcpy (info->driver, DRV_MODULE_NAME);
1587         strcpy (info->version, DRV_MODULE_VERSION);
1588         strcpy (info->bus_info, pci_name(pci_dev));
1589 }
1590
1591 static int b44_nway_reset(struct net_device *dev)
1592 {
1593         struct b44 *bp = netdev_priv(dev);
1594         u32 bmcr;
1595         int r;
1596
1597         spin_lock_irq(&bp->lock);
1598         b44_readphy(bp, MII_BMCR, &bmcr);
1599         b44_readphy(bp, MII_BMCR, &bmcr);
1600         r = -EINVAL;
1601         if (bmcr & BMCR_ANENABLE) {
1602                 b44_writephy(bp, MII_BMCR,
1603                              bmcr | BMCR_ANRESTART);
1604                 r = 0;
1605         }
1606         spin_unlock_irq(&bp->lock);
1607
1608         return r;
1609 }
1610
1611 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1612 {
1613         struct b44 *bp = netdev_priv(dev);
1614
1615         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1616                 return -EAGAIN;
1617         cmd->supported = (SUPPORTED_Autoneg);
1618         cmd->supported |= (SUPPORTED_100baseT_Half |
1619                           SUPPORTED_100baseT_Full |
1620                           SUPPORTED_10baseT_Half |
1621                           SUPPORTED_10baseT_Full |
1622                           SUPPORTED_MII);
1623
1624         cmd->advertising = 0;
1625         if (bp->flags & B44_FLAG_ADV_10HALF)
1626                 cmd->advertising |= ADVERTISED_10baseT_Half;
1627         if (bp->flags & B44_FLAG_ADV_10FULL)
1628                 cmd->advertising |= ADVERTISED_10baseT_Full;
1629         if (bp->flags & B44_FLAG_ADV_100HALF)
1630                 cmd->advertising |= ADVERTISED_100baseT_Half;
1631         if (bp->flags & B44_FLAG_ADV_100FULL)
1632                 cmd->advertising |= ADVERTISED_100baseT_Full;
1633         cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1634         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1635                 SPEED_100 : SPEED_10;
1636         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1637                 DUPLEX_FULL : DUPLEX_HALF;
1638         cmd->port = 0;
1639         cmd->phy_address = bp->phy_addr;
1640         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1641                 XCVR_INTERNAL : XCVR_EXTERNAL;
1642         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1643                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1644         cmd->maxtxpkt = 0;
1645         cmd->maxrxpkt = 0;
1646         return 0;
1647 }
1648
1649 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1650 {
1651         struct b44 *bp = netdev_priv(dev);
1652
1653         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1654                 return -EAGAIN;
1655
1656         /* We do not support gigabit. */
1657         if (cmd->autoneg == AUTONEG_ENABLE) {
1658                 if (cmd->advertising &
1659                     (ADVERTISED_1000baseT_Half |
1660                      ADVERTISED_1000baseT_Full))
1661                         return -EINVAL;
1662         } else if ((cmd->speed != SPEED_100 &&
1663                     cmd->speed != SPEED_10) ||
1664                    (cmd->duplex != DUPLEX_HALF &&
1665                     cmd->duplex != DUPLEX_FULL)) {
1666                         return -EINVAL;
1667         }
1668
1669         spin_lock_irq(&bp->lock);
1670
1671         if (cmd->autoneg == AUTONEG_ENABLE) {
1672                 bp->flags &= ~B44_FLAG_FORCE_LINK;
1673                 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1674                                B44_FLAG_ADV_10FULL |
1675                                B44_FLAG_ADV_100HALF |
1676                                B44_FLAG_ADV_100FULL);
1677                 if (cmd->advertising & ADVERTISE_10HALF)
1678                         bp->flags |= B44_FLAG_ADV_10HALF;
1679                 if (cmd->advertising & ADVERTISE_10FULL)
1680                         bp->flags |= B44_FLAG_ADV_10FULL;
1681                 if (cmd->advertising & ADVERTISE_100HALF)
1682                         bp->flags |= B44_FLAG_ADV_100HALF;
1683                 if (cmd->advertising & ADVERTISE_100FULL)
1684                         bp->flags |= B44_FLAG_ADV_100FULL;
1685         } else {
1686                 bp->flags |= B44_FLAG_FORCE_LINK;
1687                 if (cmd->speed == SPEED_100)
1688                         bp->flags |= B44_FLAG_100_BASE_T;
1689                 if (cmd->duplex == DUPLEX_FULL)
1690                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1691         }
1692
1693         b44_setup_phy(bp);
1694
1695         spin_unlock_irq(&bp->lock);
1696
1697         return 0;
1698 }
1699
1700 static void b44_get_ringparam(struct net_device *dev,
1701                               struct ethtool_ringparam *ering)
1702 {
1703         struct b44 *bp = netdev_priv(dev);
1704
1705         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1706         ering->rx_pending = bp->rx_pending;
1707
1708         /* XXX ethtool lacks a tx_max_pending, oops... */
1709 }
1710
1711 static int b44_set_ringparam(struct net_device *dev,
1712                              struct ethtool_ringparam *ering)
1713 {
1714         struct b44 *bp = netdev_priv(dev);
1715
1716         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1717             (ering->rx_mini_pending != 0) ||
1718             (ering->rx_jumbo_pending != 0) ||
1719             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1720                 return -EINVAL;
1721
1722         spin_lock_irq(&bp->lock);
1723
1724         bp->rx_pending = ering->rx_pending;
1725         bp->tx_pending = ering->tx_pending;
1726
1727         b44_halt(bp);
1728         b44_init_rings(bp);
1729         b44_init_hw(bp);
1730         netif_wake_queue(bp->dev);
1731         spin_unlock_irq(&bp->lock);
1732
1733         b44_enable_ints(bp);
1734
1735         return 0;
1736 }
1737
1738 static void b44_get_pauseparam(struct net_device *dev,
1739                                 struct ethtool_pauseparam *epause)
1740 {
1741         struct b44 *bp = netdev_priv(dev);
1742
1743         epause->autoneg =
1744                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1745         epause->rx_pause =
1746                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1747         epause->tx_pause =
1748                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1749 }
1750
1751 static int b44_set_pauseparam(struct net_device *dev,
1752                                 struct ethtool_pauseparam *epause)
1753 {
1754         struct b44 *bp = netdev_priv(dev);
1755
1756         spin_lock_irq(&bp->lock);
1757         if (epause->autoneg)
1758                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1759         else
1760                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1761         if (epause->rx_pause)
1762                 bp->flags |= B44_FLAG_RX_PAUSE;
1763         else
1764                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1765         if (epause->tx_pause)
1766                 bp->flags |= B44_FLAG_TX_PAUSE;
1767         else
1768                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1769         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1770                 b44_halt(bp);
1771                 b44_init_rings(bp);
1772                 b44_init_hw(bp);
1773         } else {
1774                 __b44_set_flow_ctrl(bp, bp->flags);
1775         }
1776         spin_unlock_irq(&bp->lock);
1777
1778         b44_enable_ints(bp);
1779
1780         return 0;
1781 }
1782
1783 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1784 {
1785         switch(stringset) {
1786         case ETH_SS_STATS:
1787                 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1788                 break;
1789         }
1790 }
1791
1792 static int b44_get_stats_count(struct net_device *dev)
1793 {
1794         return ARRAY_SIZE(b44_gstrings);
1795 }
1796
1797 static void b44_get_ethtool_stats(struct net_device *dev,
1798                                   struct ethtool_stats *stats, u64 *data)
1799 {
1800         struct b44 *bp = netdev_priv(dev);
1801         u32 *val = &bp->hw_stats.tx_good_octets;
1802         u32 i;
1803
1804         spin_lock_irq(&bp->lock);
1805
1806         b44_stats_update(bp);
1807
1808         for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
1809                 *data++ = *val++;
1810
1811         spin_unlock_irq(&bp->lock);
1812 }
1813
1814 static struct ethtool_ops b44_ethtool_ops = {
1815         .get_drvinfo            = b44_get_drvinfo,
1816         .get_settings           = b44_get_settings,
1817         .set_settings           = b44_set_settings,
1818         .nway_reset             = b44_nway_reset,
1819         .get_link               = ethtool_op_get_link,
1820         .get_ringparam          = b44_get_ringparam,
1821         .set_ringparam          = b44_set_ringparam,
1822         .get_pauseparam         = b44_get_pauseparam,
1823         .set_pauseparam         = b44_set_pauseparam,
1824         .get_msglevel           = b44_get_msglevel,
1825         .set_msglevel           = b44_set_msglevel,
1826         .get_strings            = b44_get_strings,
1827         .get_stats_count        = b44_get_stats_count,
1828         .get_ethtool_stats      = b44_get_ethtool_stats,
1829         .get_perm_addr          = ethtool_op_get_perm_addr,
1830 };
1831
1832 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1833 {
1834         struct mii_ioctl_data *data = if_mii(ifr);
1835         struct b44 *bp = netdev_priv(dev);
1836         int err;
1837
1838         spin_lock_irq(&bp->lock);
1839         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1840         spin_unlock_irq(&bp->lock);
1841
1842         return err;
1843 }
1844
1845 /* Read 128-bytes of EEPROM. */
1846 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1847 {
1848         long i;
1849         u16 *ptr = (u16 *) data;
1850
1851         for (i = 0; i < 128; i += 2)
1852                 ptr[i / 2] = readw(bp->regs + 4096 + i);
1853
1854         return 0;
1855 }
1856
1857 static int __devinit b44_get_invariants(struct b44 *bp)
1858 {
1859         u8 eeprom[128];
1860         int err;
1861
1862         err = b44_read_eeprom(bp, &eeprom[0]);
1863         if (err)
1864                 goto out;
1865
1866         bp->dev->dev_addr[0] = eeprom[79];
1867         bp->dev->dev_addr[1] = eeprom[78];
1868         bp->dev->dev_addr[2] = eeprom[81];
1869         bp->dev->dev_addr[3] = eeprom[80];
1870         bp->dev->dev_addr[4] = eeprom[83];
1871         bp->dev->dev_addr[5] = eeprom[82];
1872         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1873
1874         bp->phy_addr = eeprom[90] & 0x1f;
1875
1876         /* With this, plus the rx_header prepended to the data by the
1877          * hardware, we'll land the ethernet header on a 2-byte boundary.
1878          */
1879         bp->rx_offset = 30;
1880
1881         bp->imask = IMASK_DEF;
1882
1883         bp->core_unit = ssb_core_unit(bp);
1884         bp->dma_offset = SB_PCI_DMA;
1885
1886         /* XXX - really required?
1887            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1888          */
1889 out:
1890         return err;
1891 }
1892
1893 static int __devinit b44_init_one(struct pci_dev *pdev,
1894                                   const struct pci_device_id *ent)
1895 {
1896         static int b44_version_printed = 0;
1897         unsigned long b44reg_base, b44reg_len;
1898         struct net_device *dev;
1899         struct b44 *bp;
1900         int err, i;
1901
1902         if (b44_version_printed++ == 0)
1903                 printk(KERN_INFO "%s", version);
1904
1905         err = pci_enable_device(pdev);
1906         if (err) {
1907                 printk(KERN_ERR PFX "Cannot enable PCI device, "
1908                        "aborting.\n");
1909                 return err;
1910         }
1911
1912         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1913                 printk(KERN_ERR PFX "Cannot find proper PCI device "
1914                        "base address, aborting.\n");
1915                 err = -ENODEV;
1916                 goto err_out_disable_pdev;
1917         }
1918
1919         err = pci_request_regions(pdev, DRV_MODULE_NAME);
1920         if (err) {
1921                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1922                        "aborting.\n");
1923                 goto err_out_disable_pdev;
1924         }
1925
1926         pci_set_master(pdev);
1927
1928         err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1929         if (err) {
1930                 printk(KERN_ERR PFX "No usable DMA configuration, "
1931                        "aborting.\n");
1932                 goto err_out_free_res;
1933         }
1934
1935         err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1936         if (err) {
1937                 printk(KERN_ERR PFX "No usable DMA configuration, "
1938                        "aborting.\n");
1939                 goto err_out_free_res;
1940         }
1941
1942         b44reg_base = pci_resource_start(pdev, 0);
1943         b44reg_len = pci_resource_len(pdev, 0);
1944
1945         dev = alloc_etherdev(sizeof(*bp));
1946         if (!dev) {
1947                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1948                 err = -ENOMEM;
1949                 goto err_out_free_res;
1950         }
1951
1952         SET_MODULE_OWNER(dev);
1953         SET_NETDEV_DEV(dev,&pdev->dev);
1954
1955         /* No interesting netdevice features in this card... */
1956         dev->features |= 0;
1957
1958         bp = netdev_priv(dev);
1959         bp->pdev = pdev;
1960         bp->dev = dev;
1961
1962         bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1963
1964         spin_lock_init(&bp->lock);
1965
1966         bp->regs = ioremap(b44reg_base, b44reg_len);
1967         if (bp->regs == 0UL) {
1968                 printk(KERN_ERR PFX "Cannot map device registers, "
1969                        "aborting.\n");
1970                 err = -ENOMEM;
1971                 goto err_out_free_dev;
1972         }
1973
1974         bp->rx_pending = B44_DEF_RX_RING_PENDING;
1975         bp->tx_pending = B44_DEF_TX_RING_PENDING;
1976
1977         dev->open = b44_open;
1978         dev->stop = b44_close;
1979         dev->hard_start_xmit = b44_start_xmit;
1980         dev->get_stats = b44_get_stats;
1981         dev->set_multicast_list = b44_set_rx_mode;
1982         dev->set_mac_address = b44_set_mac_addr;
1983         dev->do_ioctl = b44_ioctl;
1984         dev->tx_timeout = b44_tx_timeout;
1985         dev->poll = b44_poll;
1986         dev->weight = 64;
1987         dev->watchdog_timeo = B44_TX_TIMEOUT;
1988 #ifdef CONFIG_NET_POLL_CONTROLLER
1989         dev->poll_controller = b44_poll_controller;
1990 #endif
1991         dev->change_mtu = b44_change_mtu;
1992         dev->irq = pdev->irq;
1993         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1994
1995         err = b44_get_invariants(bp);
1996         if (err) {
1997                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1998                        "aborting.\n");
1999                 goto err_out_iounmap;
2000         }
2001
2002         bp->mii_if.dev = dev;
2003         bp->mii_if.mdio_read = b44_mii_read;
2004         bp->mii_if.mdio_write = b44_mii_write;
2005         bp->mii_if.phy_id = bp->phy_addr;
2006         bp->mii_if.phy_id_mask = 0x1f;
2007         bp->mii_if.reg_num_mask = 0x1f;
2008
2009         /* By default, advertise all speed/duplex settings. */
2010         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2011                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2012
2013         /* By default, auto-negotiate PAUSE. */
2014         bp->flags |= B44_FLAG_PAUSE_AUTO;
2015
2016         err = register_netdev(dev);
2017         if (err) {
2018                 printk(KERN_ERR PFX "Cannot register net device, "
2019                        "aborting.\n");
2020                 goto err_out_iounmap;
2021         }
2022
2023         pci_set_drvdata(pdev, dev);
2024
2025         pci_save_state(bp->pdev);
2026
2027         printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
2028         for (i = 0; i < 6; i++)
2029                 printk("%2.2x%c", dev->dev_addr[i],
2030                        i == 5 ? '\n' : ':');
2031
2032         return 0;
2033
2034 err_out_iounmap:
2035         iounmap(bp->regs);
2036
2037 err_out_free_dev:
2038         free_netdev(dev);
2039
2040 err_out_free_res:
2041         pci_release_regions(pdev);
2042
2043 err_out_disable_pdev:
2044         pci_disable_device(pdev);
2045         pci_set_drvdata(pdev, NULL);
2046         return err;
2047 }
2048
2049 static void __devexit b44_remove_one(struct pci_dev *pdev)
2050 {
2051         struct net_device *dev = pci_get_drvdata(pdev);
2052         struct b44 *bp = netdev_priv(dev);
2053
2054         unregister_netdev(dev);
2055         iounmap(bp->regs);
2056         free_netdev(dev);
2057         pci_release_regions(pdev);
2058         pci_disable_device(pdev);
2059         pci_set_drvdata(pdev, NULL);
2060 }
2061
2062 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2063 {
2064         struct net_device *dev = pci_get_drvdata(pdev);
2065         struct b44 *bp = netdev_priv(dev);
2066
2067         if (!netif_running(dev))
2068                  return 0;
2069
2070         del_timer_sync(&bp->timer);
2071
2072         spin_lock_irq(&bp->lock);
2073
2074         b44_halt(bp);
2075         netif_carrier_off(bp->dev);
2076         netif_device_detach(bp->dev);
2077         b44_free_rings(bp);
2078
2079         spin_unlock_irq(&bp->lock);
2080
2081         free_irq(dev->irq, dev);
2082         pci_disable_device(pdev);
2083         return 0;
2084 }
2085
2086 static int b44_resume(struct pci_dev *pdev)
2087 {
2088         struct net_device *dev = pci_get_drvdata(pdev);
2089         struct b44 *bp = netdev_priv(dev);
2090
2091         pci_restore_state(pdev);
2092         pci_enable_device(pdev);
2093         pci_set_master(pdev);
2094
2095         if (!netif_running(dev))
2096                 return 0;
2097
2098         if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2099                 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2100
2101         spin_lock_irq(&bp->lock);
2102
2103         b44_init_rings(bp);
2104         b44_init_hw(bp);
2105         netif_device_attach(bp->dev);
2106         spin_unlock_irq(&bp->lock);
2107
2108         bp->timer.expires = jiffies + HZ;
2109         add_timer(&bp->timer);
2110
2111         b44_enable_ints(bp);
2112         return 0;
2113 }
2114
2115 static struct pci_driver b44_driver = {
2116         .name           = DRV_MODULE_NAME,
2117         .id_table       = b44_pci_tbl,
2118         .probe          = b44_init_one,
2119         .remove         = __devexit_p(b44_remove_one),
2120         .suspend        = b44_suspend,
2121         .resume         = b44_resume,
2122 };
2123
2124 static int __init b44_init(void)
2125 {
2126         unsigned int dma_desc_align_size = dma_get_cache_alignment();
2127
2128         /* Setup paramaters for syncing RX/TX DMA descriptors */
2129         dma_desc_align_mask = ~(dma_desc_align_size - 1);
2130         dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2131
2132         return pci_module_init(&b44_driver);
2133 }
2134
2135 static void __exit b44_cleanup(void)
2136 {
2137         pci_unregister_driver(&b44_driver);
2138 }
2139
2140 module_init(b44_init);
2141 module_exit(b44_cleanup);
2142