1 /* linux/drivers/mtd/nand/s3c2410.c
3 * Copyright (c) 2004,2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
7 * Samsung S3C2410/S3C240 NAND driver
10 * 21-Sep-2004 BJD Initial version
11 * 23-Sep-2004 BJD Mulitple device support
12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
13 * 12-Oct-2004 BJD Fixed errors in use of platform data
14 * 18-Feb-2005 BJD Fix sparse errors
15 * 14-Mar-2005 BJD Applied tglx's code reduction patch
16 * 02-May-2005 BJD Fixed s3c2440 support
17 * 02-May-2005 BJD Reduced hwcontrol decode
18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug
19 * 08-Jul-2005 BJD Fix OOPS when no platform data supplied
20 * 20-Oct-2005 BJD Fix timing calculation bug
22 * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * (at your option) any later version.
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 #include <config/mtd/nand/s3c2410/hwecc.h>
40 #include <config/mtd/nand/s3c2410/debug.h>
42 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
46 #include <linux/module.h>
47 #include <linux/types.h>
48 #include <linux/init.h>
49 #include <linux/kernel.h>
50 #include <linux/string.h>
51 #include <linux/ioport.h>
52 #include <linux/platform_device.h>
53 #include <linux/delay.h>
54 #include <linux/err.h>
55 #include <linux/slab.h>
56 #include <linux/clk.h>
58 #include <linux/mtd/mtd.h>
59 #include <linux/mtd/nand.h>
60 #include <linux/mtd/nand_ecc.h>
61 #include <linux/mtd/partitions.h>
65 #include <asm/arch/regs-nand.h>
66 #include <asm/arch/nand.h>
68 #define PFX "s3c2410-nand: "
70 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
71 static int hardware_ecc = 1;
73 static int hardware_ecc = 0;
76 /* new oob placement block for use with hardware ecc generation
79 static struct nand_oobinfo nand_hw_eccoob = {
80 .useecc = MTD_NANDECC_AUTOPLACE,
86 /* controller and mtd information */
88 struct s3c2410_nand_info;
90 struct s3c2410_nand_mtd {
92 struct nand_chip chip;
93 struct s3c2410_nand_set *set;
94 struct s3c2410_nand_info *info;
98 /* overview of the s3c2410 nand state */
100 struct s3c2410_nand_info {
102 struct nand_hw_control controller;
103 struct s3c2410_nand_mtd *mtds;
104 struct s3c2410_platform_nand *platform;
107 struct device *device;
108 struct resource *area;
113 unsigned char is_s3c2440;
116 /* conversion functions */
118 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
120 return container_of(mtd, struct s3c2410_nand_mtd, mtd);
123 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
125 return s3c2410_nand_mtd_toours(mtd)->info;
128 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
130 return platform_get_drvdata(dev);
133 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
135 return dev->dev.platform_data;
138 /* timing calculations */
140 #define NS_IN_KHZ 1000000
142 static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
146 result = (wanted * clk) / NS_IN_KHZ;
149 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
152 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
162 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
164 /* controller setup */
166 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev)
168 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
169 unsigned long clkrate = clk_get_rate(info->clk);
170 int tacls, twrph0, twrph1;
173 /* calculate the timing information for the controller */
175 clkrate /= 1000; /* turn clock into kHz for ease of use */
178 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4);
179 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
180 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
182 /* default timings */
188 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
189 printk(KERN_ERR PFX "cannot get timings suitable for board\n");
193 printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
194 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
196 if (!info->is_s3c2440) {
197 cfg = S3C2410_NFCONF_EN;
198 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
199 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
200 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
202 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
203 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
204 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
207 pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
209 writel(cfg, info->regs + S3C2410_NFCONF);
215 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
217 struct s3c2410_nand_info *info;
218 struct s3c2410_nand_mtd *nmtd;
219 struct nand_chip *this = mtd->priv;
227 bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE;
228 reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF);
235 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
236 printk(KERN_ERR PFX "chip %d out of range\n", chip);
240 if (info->platform != NULL) {
241 if (info->platform->select_chip != NULL)
242 (info->platform->select_chip) (nmtd->set, chip);
251 /* command and control functions
253 * Note, these all use tglx's method of changing the IO_ADDR_W field
254 * to make the code simpler, and use the nand layer's code to issue the
255 * command and address sequences via the proper IO ports.
259 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
262 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
263 struct nand_chip *chip = mtd->priv;
265 if (cmd == NAND_CMD_NONE)
269 writeb(cmd, info->regs + S3C2410_NFCMD);
271 writeb(cmd, info->regs + S3C2410_NFADDR);
274 /* command and control functions */
276 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
279 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
280 struct nand_chip *chip = mtd->priv;
282 if (cmd == NAND_CMD_NONE)
286 writeb(cmd, info->regs + S3C2440_NFCMD);
288 writeb(cmd, info->regs + S3C2440_NFADDR);
291 /* s3c2410_nand_devready()
293 * returns 0 if the nand is busy, 1 if it is ready
296 static int s3c2410_nand_devready(struct mtd_info *mtd)
298 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
300 if (info->is_s3c2440)
301 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
302 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
305 /* ECC handling functions */
307 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
309 pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc);
311 pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
312 read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]);
314 if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2])
317 /* we curently have no method for correcting the error */
324 * These allow the s3c2410 and s3c2440 to use the controller's ECC
325 * generator block to ECC the data as it passes through]
328 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
330 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
333 ctrl = readl(info->regs + S3C2410_NFCONF);
334 ctrl |= S3C2410_NFCONF_INITECC;
335 writel(ctrl, info->regs + S3C2410_NFCONF);
338 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
340 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
343 ctrl = readl(info->regs + S3C2440_NFCONT);
344 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
347 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
349 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
351 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
352 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
353 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
355 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
360 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
362 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
363 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
366 ecc_code[1] = ecc >> 8;
367 ecc_code[2] = ecc >> 16;
369 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
374 /* over-ride the standard functions for a little more speed. We can
375 * use read/write block to move the data buffers to/from the controller
378 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
380 struct nand_chip *this = mtd->priv;
381 readsb(this->IO_ADDR_R, buf, len);
384 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
386 struct nand_chip *this = mtd->priv;
387 writesb(this->IO_ADDR_W, buf, len);
390 /* device management functions */
392 static int s3c2410_nand_remove(struct platform_device *pdev)
394 struct s3c2410_nand_info *info = to_nand_info(pdev);
396 platform_set_drvdata(pdev, NULL);
401 /* first thing we need to do is release all our mtds
402 * and their partitions, then go through freeing the
406 if (info->mtds != NULL) {
407 struct s3c2410_nand_mtd *ptr = info->mtds;
410 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
411 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
412 nand_release(&ptr->mtd);
418 /* free the common resources */
420 if (info->clk != NULL && !IS_ERR(info->clk)) {
421 clk_disable(info->clk);
425 if (info->regs != NULL) {
430 if (info->area != NULL) {
431 release_resource(info->area);
441 #ifdef CONFIG_MTD_PARTITIONS
442 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
443 struct s3c2410_nand_mtd *mtd,
444 struct s3c2410_nand_set *set)
447 return add_mtd_device(&mtd->mtd);
449 if (set->nr_partitions > 0 && set->partitions != NULL) {
450 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
453 return add_mtd_device(&mtd->mtd);
456 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
457 struct s3c2410_nand_mtd *mtd,
458 struct s3c2410_nand_set *set)
460 return add_mtd_device(&mtd->mtd);
464 /* s3c2410_nand_init_chip
466 * init a single instance of an chip
469 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
470 struct s3c2410_nand_mtd *nmtd,
471 struct s3c2410_nand_set *set)
473 struct nand_chip *chip = &nmtd->chip;
475 chip->IO_ADDR_R = info->regs + S3C2410_NFDATA;
476 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
477 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
478 chip->dev_ready = s3c2410_nand_devready;
479 chip->write_buf = s3c2410_nand_write_buf;
480 chip->read_buf = s3c2410_nand_read_buf;
481 chip->select_chip = s3c2410_nand_select_chip;
482 chip->chip_delay = 50;
485 chip->controller = &info->controller;
487 if (info->is_s3c2440) {
488 chip->IO_ADDR_R = info->regs + S3C2440_NFDATA;
489 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA;
490 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
494 nmtd->mtd.priv = chip;
495 nmtd->mtd.owner = THIS_MODULE;
499 chip->ecc.correct = s3c2410_nand_correct_data;
500 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
501 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
502 chip->ecc.mode = NAND_ECC_HW;
503 chip->ecc.size = 512;
505 chip->autooob = &nand_hw_eccoob;
507 if (info->is_s3c2440) {
508 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
509 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
512 chip->ecc.mode = NAND_ECC_SOFT;
516 /* s3c2410_nand_probe
518 * called by device layer when it finds a device matching
519 * one our driver can handled. This code checks to see if
520 * it can allocate all necessary resources then calls the
521 * nand layer to look for devices
524 static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440)
526 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
527 struct s3c2410_nand_info *info;
528 struct s3c2410_nand_mtd *nmtd;
529 struct s3c2410_nand_set *sets;
530 struct resource *res;
536 pr_debug("s3c2410_nand_probe(%p)\n", pdev);
538 info = kmalloc(sizeof(*info), GFP_KERNEL);
540 dev_err(&pdev->dev, "no memory for flash info\n");
545 memzero(info, sizeof(*info));
546 platform_set_drvdata(pdev, info);
548 spin_lock_init(&info->controller.lock);
549 init_waitqueue_head(&info->controller.wq);
551 /* get the clock source and enable it */
553 info->clk = clk_get(&pdev->dev, "nand");
554 if (IS_ERR(info->clk)) {
555 dev_err(&pdev->dev, "failed to get clock");
560 clk_enable(info->clk);
562 /* allocate and map the resource */
564 /* currently we assume we have the one resource */
565 res = pdev->resource;
566 size = res->end - res->start + 1;
568 info->area = request_mem_region(res->start, size, pdev->name);
570 if (info->area == NULL) {
571 dev_err(&pdev->dev, "cannot reserve register region\n");
576 info->device = &pdev->dev;
577 info->platform = plat;
578 info->regs = ioremap(res->start, size);
579 info->is_s3c2440 = is_s3c2440;
581 if (info->regs == NULL) {
582 dev_err(&pdev->dev, "cannot reserve register region\n");
587 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
589 /* initialise the hardware */
591 err = s3c2410_nand_inithw(info, pdev);
595 sets = (plat != NULL) ? plat->sets : NULL;
596 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
598 info->mtd_count = nr_sets;
600 /* allocate our information */
602 size = nr_sets * sizeof(*info->mtds);
603 info->mtds = kmalloc(size, GFP_KERNEL);
604 if (info->mtds == NULL) {
605 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
610 memzero(info->mtds, size);
612 /* initialise all possible chips */
616 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
617 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
619 s3c2410_nand_init_chip(info, nmtd, sets);
621 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
623 if (nmtd->scan_res == 0) {
624 s3c2410_nand_add_partition(info, nmtd, sets);
631 pr_debug("initialised ok\n");
635 s3c2410_nand_remove(pdev);
642 /* driver device registration */
644 static int s3c2410_nand_probe(struct platform_device *dev)
646 return s3c24xx_nand_probe(dev, 0);
649 static int s3c2440_nand_probe(struct platform_device *dev)
651 return s3c24xx_nand_probe(dev, 1);
654 static struct platform_driver s3c2410_nand_driver = {
655 .probe = s3c2410_nand_probe,
656 .remove = s3c2410_nand_remove,
658 .name = "s3c2410-nand",
659 .owner = THIS_MODULE,
663 static struct platform_driver s3c2440_nand_driver = {
664 .probe = s3c2440_nand_probe,
665 .remove = s3c2410_nand_remove,
667 .name = "s3c2440-nand",
668 .owner = THIS_MODULE,
672 static int __init s3c2410_nand_init(void)
674 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
676 platform_driver_register(&s3c2440_nand_driver);
677 return platform_driver_register(&s3c2410_nand_driver);
680 static void __exit s3c2410_nand_exit(void)
682 platform_driver_unregister(&s3c2440_nand_driver);
683 platform_driver_unregister(&s3c2410_nand_driver);
686 module_init(s3c2410_nand_init);
687 module_exit(s3c2410_nand_exit);
689 MODULE_LICENSE("GPL");
690 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
691 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");