2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
37 #define DRIVER_NAME "mxc_nand"
39 /* Addresses for NFC registers */
40 #define NFC_BUF_SIZE 0xE00
41 #define NFC_BUF_ADDR 0xE04
42 #define NFC_FLASH_ADDR 0xE06
43 #define NFC_FLASH_CMD 0xE08
44 #define NFC_CONFIG 0xE0A
45 #define NFC_ECC_STATUS_RESULT 0xE0C
46 #define NFC_RSLTMAIN_AREA 0xE0E
47 #define NFC_RSLTSPARE_AREA 0xE10
48 #define NFC_WRPROT 0xE12
49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
50 #define NFC_UNLOCKEND_BLKADDR 0xE16
51 #define NFC_NF_WRPRST 0xE18
52 #define NFC_CONFIG1 0xE1A
53 #define NFC_CONFIG2 0xE1C
55 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
56 * for Command operation */
59 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
60 * for Address operation */
63 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
64 * for Input operation */
67 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
68 * for Data Output operation */
69 #define NFC_OUTPUT 0x8
71 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
72 * for Read ID operation */
75 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
76 * for Read Status operation */
77 #define NFC_STATUS 0x20
79 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
81 #define NFC_INT 0x8000
83 #define NFC_SP_EN (1 << 2)
84 #define NFC_ECC_EN (1 << 3)
85 #define NFC_INT_MSK (1 << 4)
86 #define NFC_BIG (1 << 5)
87 #define NFC_RST (1 << 6)
88 #define NFC_CE (1 << 7)
89 #define NFC_ONE_CYCLE (1 << 8)
91 struct mxc_nand_host {
93 struct nand_chip nand;
94 struct mtd_partition *parts;
109 wait_queue_head_t irq_waitq;
112 unsigned int buf_start;
116 /* Define delays in microsec for NAND device operations */
117 #define TROP_US_DELAY 2000
119 /* OOB placement block for use with hardware ecc generation */
120 static struct nand_ecclayout nand_hw_eccoob_smallpage = {
122 .eccpos = {6, 7, 8, 9, 10},
123 .oobfree = {{0, 5}, {12, 4}, }
126 static struct nand_ecclayout nand_hw_eccoob_largepage = {
128 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
129 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
130 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
133 #ifdef CONFIG_MTD_PARTITIONS
134 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
137 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
139 struct mxc_nand_host *host = dev_id;
143 tmp = readw(host->regs + NFC_CONFIG1);
144 tmp |= NFC_INT_MSK; /* Disable interrupt */
145 writew(tmp, host->regs + NFC_CONFIG1);
147 wake_up(&host->irq_waitq);
152 /* This function polls the NANDFC to wait for the basic operation to
153 * complete by checking the INT bit of config2 register.
155 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
161 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
163 tmp = readw(host->regs + NFC_CONFIG1);
164 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
165 writew(tmp, host->regs + NFC_CONFIG1);
167 wait_event(host->irq_waitq,
168 readw(host->regs + NFC_CONFIG2) & NFC_INT);
170 tmp = readw(host->regs + NFC_CONFIG2);
172 writew(tmp, host->regs + NFC_CONFIG2);
175 while (max_retries-- > 0) {
176 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
177 tmp = readw(host->regs + NFC_CONFIG2);
179 writew(tmp, host->regs + NFC_CONFIG2);
185 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
190 /* This function issues the specified command to the NAND device and
191 * waits for completion. */
192 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
194 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
196 writew(cmd, host->regs + NFC_FLASH_CMD);
197 writew(NFC_CMD, host->regs + NFC_CONFIG2);
199 /* Wait for operation to complete */
200 wait_op_done(host, TROP_US_DELAY, useirq);
203 /* This function sends an address (or partial address) to the
204 * NAND device. The address is used to select the source/destination for
206 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
208 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
210 writew(addr, host->regs + NFC_FLASH_ADDR);
211 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
213 /* Wait for operation to complete */
214 wait_op_done(host, TROP_US_DELAY, islast);
217 static void send_page(struct mxc_nand_host *host, unsigned int ops)
221 if (host->pagesize_2k)
226 for (i = 0; i < bufs; i++) {
228 /* NANDFC buffer 0 is used for page read/write */
229 writew(i, host->regs + NFC_BUF_ADDR);
231 writew(ops, host->regs + NFC_CONFIG2);
233 /* Wait for operation to complete */
234 wait_op_done(host, TROP_US_DELAY, true);
238 /* Request the NANDFC to perform a read of the NAND device ID. */
239 static void send_read_id(struct mxc_nand_host *host)
241 struct nand_chip *this = &host->nand;
244 /* NANDFC buffer 0 is used for device ID output */
245 writew(0x0, host->regs + NFC_BUF_ADDR);
247 /* Read ID into main buffer */
248 tmp = readw(host->regs + NFC_CONFIG1);
250 writew(tmp, host->regs + NFC_CONFIG1);
252 writew(NFC_ID, host->regs + NFC_CONFIG2);
254 /* Wait for operation to complete */
255 wait_op_done(host, TROP_US_DELAY, true);
257 if (this->options & NAND_BUSWIDTH_16) {
258 void __iomem *main_buf = host->main_area0;
259 /* compress the ID info */
260 writeb(readb(main_buf + 2), main_buf + 1);
261 writeb(readb(main_buf + 4), main_buf + 2);
262 writeb(readb(main_buf + 6), main_buf + 3);
263 writeb(readb(main_buf + 8), main_buf + 4);
264 writeb(readb(main_buf + 10), main_buf + 5);
266 memcpy(host->data_buf, host->main_area0, 16);
269 /* This function requests the NANDFC to perform a read of the
270 * NAND device status and returns the current status. */
271 static uint16_t get_dev_status(struct mxc_nand_host *host)
273 void __iomem *main_buf = host->main_area1;
276 /* Issue status request to NAND device */
278 /* store the main area1 first word, later do recovery */
279 store = readl(main_buf);
280 /* NANDFC buffer 1 is used for device status to prevent
281 * corruption of read/write buffer on status requests. */
282 writew(1, host->regs + NFC_BUF_ADDR);
284 /* Read status into main buffer */
285 tmp = readw(host->regs + NFC_CONFIG1);
287 writew(tmp, host->regs + NFC_CONFIG1);
289 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
291 /* Wait for operation to complete */
292 wait_op_done(host, TROP_US_DELAY, true);
294 /* Status is placed in first word of main buffer */
295 /* get status, then recovery area 1 data */
296 ret = readw(main_buf);
297 writel(store, main_buf);
302 /* This functions is used by upper layer to checks if device is ready */
303 static int mxc_nand_dev_ready(struct mtd_info *mtd)
306 * NFC handles R/B internally. Therefore, this function
307 * always returns status as ready.
312 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
315 * If HW ECC is enabled, we turn it on during init. There is
316 * no need to enable again here.
320 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
321 u_char *read_ecc, u_char *calc_ecc)
323 struct nand_chip *nand_chip = mtd->priv;
324 struct mxc_nand_host *host = nand_chip->priv;
327 * 1-Bit errors are automatically corrected in HW. No need for
328 * additional correction. 2-Bit errors cannot be corrected by
329 * HW ECC, so we need to return failure
331 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
333 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
334 DEBUG(MTD_DEBUG_LEVEL0,
335 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
342 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
348 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
350 struct nand_chip *nand_chip = mtd->priv;
351 struct mxc_nand_host *host = nand_chip->priv;
354 /* Check for status request */
355 if (host->status_request)
356 return get_dev_status(host) & 0xFF;
358 ret = *(uint8_t *)(host->data_buf + host->buf_start);
364 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
366 struct nand_chip *nand_chip = mtd->priv;
367 struct mxc_nand_host *host = nand_chip->priv;
370 ret = *(uint16_t *)(host->data_buf + host->buf_start);
371 host->buf_start += 2;
376 /* Write data of length len to buffer buf. The data to be
377 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
378 * Operation by the NFC, the data is written to NAND Flash */
379 static void mxc_nand_write_buf(struct mtd_info *mtd,
380 const u_char *buf, int len)
382 struct nand_chip *nand_chip = mtd->priv;
383 struct mxc_nand_host *host = nand_chip->priv;
384 u16 col = host->buf_start;
385 int n = mtd->oobsize + mtd->writesize - col;
389 memcpy(host->data_buf + col, buf, n);
391 host->buf_start += n;
394 /* Read the data buffer from the NAND Flash. To read the data from NAND
395 * Flash first the data output cycle is initiated by the NFC, which copies
396 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
398 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
400 struct nand_chip *nand_chip = mtd->priv;
401 struct mxc_nand_host *host = nand_chip->priv;
402 u16 col = host->buf_start;
403 int n = mtd->oobsize + mtd->writesize - col;
407 memcpy(buf, host->data_buf + col, len);
409 host->buf_start += len;
412 /* Used by the upper layer to verify the data in NAND Flash
413 * with the data in the buf. */
414 static int mxc_nand_verify_buf(struct mtd_info *mtd,
415 const u_char *buf, int len)
420 /* This function is used by upper layer for select and
421 * deselect of the NAND chip */
422 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
424 struct nand_chip *nand_chip = mtd->priv;
425 struct mxc_nand_host *host = nand_chip->priv;
429 /* Disable the NFC clock */
431 clk_disable(host->clk);
436 /* Enable the NFC clock */
437 if (!host->clk_act) {
438 clk_enable(host->clk);
449 * Function to transfer data to/from spare area.
451 static void copy_spare(struct mtd_info *mtd, bool bfrom)
453 struct nand_chip *this = mtd->priv;
454 struct mxc_nand_host *host = this->priv;
456 u16 n = mtd->writesize >> 9;
457 u8 *d = host->data_buf + mtd->writesize;
458 u8 *s = host->spare0;
459 u16 t = host->spare_len;
461 j = (mtd->oobsize / n >> 1) << 1;
464 for (i = 0; i < n - 1; i++)
465 memcpy(d + i * j, s + i * t, j);
467 /* the last section */
468 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
470 for (i = 0; i < n - 1; i++)
471 memcpy(&s[i * t], &d[i * j], j);
473 /* the last section */
474 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
478 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
480 struct nand_chip *nand_chip = mtd->priv;
481 struct mxc_nand_host *host = nand_chip->priv;
483 /* Write out column address, if necessary */
486 * MXC NANDFC can only perform full page+spare or
487 * spare-only read/write. When the upper layers
488 * layers perform a read/write buf operation,
489 * we will used the saved column adress to index into
492 send_addr(host, 0, page_addr == -1);
493 if (host->pagesize_2k)
494 /* another col addr cycle for 2k page */
495 send_addr(host, 0, false);
498 /* Write out page address, if necessary */
499 if (page_addr != -1) {
500 /* paddr_0 - p_addr_7 */
501 send_addr(host, (page_addr & 0xff), false);
503 if (host->pagesize_2k) {
504 if (mtd->size >= 0x10000000) {
505 /* paddr_8 - paddr_15 */
506 send_addr(host, (page_addr >> 8) & 0xff, false);
507 send_addr(host, (page_addr >> 16) & 0xff, true);
509 /* paddr_8 - paddr_15 */
510 send_addr(host, (page_addr >> 8) & 0xff, true);
512 /* One more address cycle for higher density devices */
513 if (mtd->size >= 0x4000000) {
514 /* paddr_8 - paddr_15 */
515 send_addr(host, (page_addr >> 8) & 0xff, false);
516 send_addr(host, (page_addr >> 16) & 0xff, true);
518 /* paddr_8 - paddr_15 */
519 send_addr(host, (page_addr >> 8) & 0xff, true);
524 /* Used by the upper layer to write command to NAND Flash for
525 * different operations to be carried out on NAND Flash */
526 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
527 int column, int page_addr)
529 struct nand_chip *nand_chip = mtd->priv;
530 struct mxc_nand_host *host = nand_chip->priv;
532 DEBUG(MTD_DEBUG_LEVEL3,
533 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
534 command, column, page_addr);
536 /* Reset command state information */
537 host->status_request = false;
539 /* Command pre-processing step */
542 case NAND_CMD_STATUS:
544 host->status_request = true;
546 send_cmd(host, command, true);
547 mxc_do_addr_cycle(mtd, column, page_addr);
551 case NAND_CMD_READOOB:
552 if (command == NAND_CMD_READ0)
553 host->buf_start = column;
555 host->buf_start = column + mtd->writesize;
557 if (host->pagesize_2k)
558 command = NAND_CMD_READ0; /* only READ0 is valid */
560 send_cmd(host, command, false);
561 mxc_do_addr_cycle(mtd, column, page_addr);
563 if (host->pagesize_2k)
564 send_cmd(host, NAND_CMD_READSTART, true);
566 send_page(host, NFC_OUTPUT);
568 memcpy(host->data_buf, host->main_area0, mtd->writesize);
569 copy_spare(mtd, true);
573 if (column >= mtd->writesize) {
575 * FIXME: before send SEQIN command for write OOB,
576 * We must read one page out.
577 * For K9F1GXX has no READ1 command to set current HW
578 * pointer to spare area, we must write the whole page
579 * including OOB together.
581 if (host->pagesize_2k)
582 /* call ourself to read a page */
583 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
586 host->buf_start = column;
588 /* Set program pointer to spare region */
589 if (!host->pagesize_2k)
590 send_cmd(host, NAND_CMD_READOOB, false);
592 host->buf_start = column;
594 /* Set program pointer to page start */
595 if (!host->pagesize_2k)
596 send_cmd(host, NAND_CMD_READ0, false);
599 send_cmd(host, command, false);
600 mxc_do_addr_cycle(mtd, column, page_addr);
603 case NAND_CMD_PAGEPROG:
604 memcpy(host->main_area0, host->data_buf, mtd->writesize);
605 copy_spare(mtd, false);
606 send_page(host, NFC_INPUT);
607 send_cmd(host, command, true);
608 mxc_do_addr_cycle(mtd, column, page_addr);
611 case NAND_CMD_READID:
612 send_cmd(host, command, true);
613 mxc_do_addr_cycle(mtd, column, page_addr);
617 case NAND_CMD_ERASE1:
618 case NAND_CMD_ERASE2:
619 send_cmd(host, command, false);
620 mxc_do_addr_cycle(mtd, column, page_addr);
626 static int __init mxcnd_probe(struct platform_device *pdev)
628 struct nand_chip *this;
629 struct mtd_info *mtd;
630 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
631 struct mxc_nand_host *host;
632 struct resource *res;
634 int err = 0, nr_parts = 0;
636 /* Allocate memory for MTD device structure and private data */
637 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
638 NAND_MAX_OOBSIZE, GFP_KERNEL);
642 host->data_buf = (uint8_t *)(host + 1);
643 host->spare_len = 16;
645 host->dev = &pdev->dev;
646 /* structures must be linked */
650 mtd->owner = THIS_MODULE;
651 mtd->dev.parent = &pdev->dev;
652 mtd->name = "mxc_nand";
654 /* 50 us command delay time */
655 this->chip_delay = 5;
658 this->dev_ready = mxc_nand_dev_ready;
659 this->cmdfunc = mxc_nand_command;
660 this->select_chip = mxc_nand_select_chip;
661 this->read_byte = mxc_nand_read_byte;
662 this->read_word = mxc_nand_read_word;
663 this->write_buf = mxc_nand_write_buf;
664 this->read_buf = mxc_nand_read_buf;
665 this->verify_buf = mxc_nand_verify_buf;
667 host->clk = clk_get(&pdev->dev, "nfc");
668 if (IS_ERR(host->clk)) {
669 err = PTR_ERR(host->clk);
673 clk_enable(host->clk);
676 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
682 host->base = ioremap(res->start, resource_size(res));
688 host->regs = host->base;
689 host->main_area0 = host->base;
690 host->main_area1 = host->base + 0x200;
691 host->spare0 = host->base + 0x800;
693 tmp = readw(host->regs + NFC_CONFIG1);
695 writew(tmp, host->regs + NFC_CONFIG1);
697 init_waitqueue_head(&host->irq_waitq);
699 host->irq = platform_get_irq(pdev, 0);
701 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
706 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
708 /* preset operation */
709 /* Unlock the internal RAM Buffer */
710 writew(0x2, host->regs + NFC_CONFIG);
712 /* Blocks to be unlocked */
713 writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
714 writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
716 /* Unlock Block Command for given address range */
717 writew(0x4, host->regs + NFC_WRPROT);
719 this->ecc.size = 512;
721 this->ecc.layout = &nand_hw_eccoob_smallpage;
724 this->ecc.calculate = mxc_nand_calculate_ecc;
725 this->ecc.hwctl = mxc_nand_enable_hwecc;
726 this->ecc.correct = mxc_nand_correct_data;
727 this->ecc.mode = NAND_ECC_HW;
728 tmp = readw(host->regs + NFC_CONFIG1);
730 writew(tmp, host->regs + NFC_CONFIG1);
732 this->ecc.mode = NAND_ECC_SOFT;
733 tmp = readw(host->regs + NFC_CONFIG1);
735 writew(tmp, host->regs + NFC_CONFIG1);
738 /* NAND bus width determines access funtions used by upper layer */
739 if (pdata->width == 2)
740 this->options |= NAND_BUSWIDTH_16;
742 /* first scan to find the device and get the page size */
743 if (nand_scan_ident(mtd, 1)) {
748 if (mtd->writesize == 2048) {
749 host->pagesize_2k = 1;
750 this->ecc.layout = &nand_hw_eccoob_largepage;
753 /* second phase scan */
754 if (nand_scan_tail(mtd)) {
759 /* Register the partitions */
760 #ifdef CONFIG_MTD_PARTITIONS
762 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
764 add_mtd_partitions(mtd, host->parts, nr_parts);
768 pr_info("Registering %s as whole device\n", mtd->name);
772 platform_set_drvdata(pdev, host);
777 free_irq(host->irq, host);
788 static int __exit mxcnd_remove(struct platform_device *pdev)
790 struct mxc_nand_host *host = platform_get_drvdata(pdev);
794 platform_set_drvdata(pdev, NULL);
796 nand_release(&host->mtd);
797 free_irq(host->irq, host);
805 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
807 struct mtd_info *mtd = platform_get_drvdata(pdev);
808 struct nand_chip *nand_chip = mtd->priv;
809 struct mxc_nand_host *host = nand_chip->priv;
812 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
814 ret = mtd->suspend(mtd);
815 /* Disable the NFC clock */
816 clk_disable(host->clk);
822 static int mxcnd_resume(struct platform_device *pdev)
824 struct mtd_info *mtd = platform_get_drvdata(pdev);
825 struct nand_chip *nand_chip = mtd->priv;
826 struct mxc_nand_host *host = nand_chip->priv;
829 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
832 /* Enable the NFC clock */
833 clk_enable(host->clk);
841 # define mxcnd_suspend NULL
842 # define mxcnd_resume NULL
843 #endif /* CONFIG_PM */
845 static struct platform_driver mxcnd_driver = {
849 .remove = __exit_p(mxcnd_remove),
850 .suspend = mxcnd_suspend,
851 .resume = mxcnd_resume,
854 static int __init mxc_nd_init(void)
856 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
859 static void __exit mxc_nd_cleanup(void)
861 /* Unregister the device structure */
862 platform_driver_unregister(&mxcnd_driver);
865 module_init(mxc_nd_init);
866 module_exit(mxc_nd_cleanup);
868 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
869 MODULE_DESCRIPTION("MXC NAND MTD driver");
870 MODULE_LICENSE("GPL");